Boot log: meson-sm1-s905d3-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 09:25:01.002938 lava-dispatcher, installed at version: 2024.01
2 09:25:01.003724 start: 0 validate
3 09:25:01.004248 Start time: 2024-11-01 09:25:01.004218+00:00 (UTC)
4 09:25:01.004796 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 09:25:01.005336 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230703.0%2Farm64%2Frootfs.cpio.gz exists
6 09:25:01.050772 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 09:25:01.051370 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241101%2Farm64%2Fdefconfig%2BCONFIG_ARM64_64K_PAGES%3Dy%2Fclang-17%2Fkernel%2FImage exists
8 09:25:01.083565 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 09:25:01.084203 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241101%2Farm64%2Fdefconfig%2BCONFIG_ARM64_64K_PAGES%3Dy%2Fclang-17%2Fdtbs%2Famlogic%2Fmeson-sm1-s905d3-libretech-cc.dtb exists
10 09:25:02.133815 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 09:25:02.134289 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241101%2Farm64%2Fdefconfig%2BCONFIG_ARM64_64K_PAGES%3Dy%2Fclang-17%2Fmodules.tar.xz exists
12 09:25:02.183564 validate duration: 1.18
14 09:25:02.185126 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 09:25:02.185739 start: 1.1 download-retry (timeout 00:10:00) [common]
16 09:25:02.186319 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 09:25:02.187299 Not decompressing ramdisk as can be used compressed.
18 09:25:02.188059 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230703.0/arm64/rootfs.cpio.gz
19 09:25:02.188582 saving as /var/lib/lava/dispatcher/tmp/922081/tftp-deploy-60x18je2/ramdisk/rootfs.cpio.gz
20 09:25:02.189101 total size: 8181887 (7 MB)
21 09:25:02.232247 progress 0 % (0 MB)
22 09:25:02.243665 progress 5 % (0 MB)
23 09:25:02.254810 progress 10 % (0 MB)
24 09:25:02.266637 progress 15 % (1 MB)
25 09:25:02.274524 progress 20 % (1 MB)
26 09:25:02.280219 progress 25 % (1 MB)
27 09:25:02.285343 progress 30 % (2 MB)
28 09:25:02.290981 progress 35 % (2 MB)
29 09:25:02.296153 progress 40 % (3 MB)
30 09:25:02.301870 progress 45 % (3 MB)
31 09:25:02.307059 progress 50 % (3 MB)
32 09:25:02.312674 progress 55 % (4 MB)
33 09:25:02.317859 progress 60 % (4 MB)
34 09:25:02.323472 progress 65 % (5 MB)
35 09:25:02.328742 progress 70 % (5 MB)
36 09:25:02.334340 progress 75 % (5 MB)
37 09:25:02.339511 progress 80 % (6 MB)
38 09:25:02.345068 progress 85 % (6 MB)
39 09:25:02.350238 progress 90 % (7 MB)
40 09:25:02.355996 progress 95 % (7 MB)
41 09:25:02.360751 progress 100 % (7 MB)
42 09:25:02.361398 7 MB downloaded in 0.17 s (45.29 MB/s)
43 09:25:02.361943 end: 1.1.1 http-download (duration 00:00:00) [common]
45 09:25:02.362855 end: 1.1 download-retry (duration 00:00:00) [common]
46 09:25:02.363148 start: 1.2 download-retry (timeout 00:10:00) [common]
47 09:25:02.363423 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 09:25:02.363877 downloading http://storage.kernelci.org/next/master/next-20241101/arm64/defconfig+CONFIG_ARM64_64K_PAGES=y/clang-17/kernel/Image
49 09:25:02.364155 saving as /var/lib/lava/dispatcher/tmp/922081/tftp-deploy-60x18je2/kernel/Image
50 09:25:02.364367 total size: 39686656 (37 MB)
51 09:25:02.364580 No compression specified
52 09:25:02.406693 progress 0 % (0 MB)
53 09:25:02.431335 progress 5 % (1 MB)
54 09:25:02.455933 progress 10 % (3 MB)
55 09:25:02.479844 progress 15 % (5 MB)
56 09:25:02.504590 progress 20 % (7 MB)
57 09:25:02.528496 progress 25 % (9 MB)
58 09:25:02.552775 progress 30 % (11 MB)
59 09:25:02.576861 progress 35 % (13 MB)
60 09:25:02.601573 progress 40 % (15 MB)
61 09:25:02.626484 progress 45 % (17 MB)
62 09:25:02.650815 progress 50 % (18 MB)
63 09:25:02.675535 progress 55 % (20 MB)
64 09:25:02.699818 progress 60 % (22 MB)
65 09:25:02.724676 progress 65 % (24 MB)
66 09:25:02.748503 progress 70 % (26 MB)
67 09:25:02.772770 progress 75 % (28 MB)
68 09:25:02.796666 progress 80 % (30 MB)
69 09:25:02.821014 progress 85 % (32 MB)
70 09:25:02.845481 progress 90 % (34 MB)
71 09:25:02.869523 progress 95 % (35 MB)
72 09:25:02.893354 progress 100 % (37 MB)
73 09:25:02.893924 37 MB downloaded in 0.53 s (71.47 MB/s)
74 09:25:02.894416 end: 1.2.1 http-download (duration 00:00:01) [common]
76 09:25:02.895509 end: 1.2 download-retry (duration 00:00:01) [common]
77 09:25:02.895854 start: 1.3 download-retry (timeout 00:09:59) [common]
78 09:25:02.896197 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 09:25:02.896676 downloading http://storage.kernelci.org/next/master/next-20241101/arm64/defconfig+CONFIG_ARM64_64K_PAGES=y/clang-17/dtbs/amlogic/meson-sm1-s905d3-libretech-cc.dtb
80 09:25:02.896955 saving as /var/lib/lava/dispatcher/tmp/922081/tftp-deploy-60x18je2/dtb/meson-sm1-s905d3-libretech-cc.dtb
81 09:25:02.897166 total size: 53209 (0 MB)
82 09:25:02.897380 No compression specified
83 09:25:02.941657 progress 61 % (0 MB)
84 09:25:02.942528 progress 100 % (0 MB)
85 09:25:02.943061 0 MB downloaded in 0.05 s (1.11 MB/s)
86 09:25:02.943529 end: 1.3.1 http-download (duration 00:00:00) [common]
88 09:25:02.944402 end: 1.3 download-retry (duration 00:00:00) [common]
89 09:25:02.944672 start: 1.4 download-retry (timeout 00:09:59) [common]
90 09:25:02.944939 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 09:25:02.945470 downloading http://storage.kernelci.org/next/master/next-20241101/arm64/defconfig+CONFIG_ARM64_64K_PAGES=y/clang-17/modules.tar.xz
92 09:25:02.945740 saving as /var/lib/lava/dispatcher/tmp/922081/tftp-deploy-60x18je2/modules/modules.tar
93 09:25:02.945948 total size: 11735240 (11 MB)
94 09:25:02.946162 Using unxz to decompress xz
95 09:25:02.987042 progress 0 % (0 MB)
96 09:25:03.054709 progress 5 % (0 MB)
97 09:25:03.131236 progress 10 % (1 MB)
98 09:25:03.213205 progress 15 % (1 MB)
99 09:25:03.294160 progress 20 % (2 MB)
100 09:25:03.371834 progress 25 % (2 MB)
101 09:25:03.453450 progress 30 % (3 MB)
102 09:25:03.530603 progress 35 % (3 MB)
103 09:25:03.612401 progress 40 % (4 MB)
104 09:25:03.697788 progress 45 % (5 MB)
105 09:25:03.779474 progress 50 % (5 MB)
106 09:25:03.859003 progress 55 % (6 MB)
107 09:25:03.941592 progress 60 % (6 MB)
108 09:25:04.026381 progress 65 % (7 MB)
109 09:25:04.106824 progress 70 % (7 MB)
110 09:25:04.191022 progress 75 % (8 MB)
111 09:25:04.273680 progress 80 % (8 MB)
112 09:25:04.353885 progress 85 % (9 MB)
113 09:25:04.428515 progress 90 % (10 MB)
114 09:25:04.527903 progress 95 % (10 MB)
115 09:25:04.621999 progress 100 % (11 MB)
116 09:25:04.632976 11 MB downloaded in 1.69 s (6.63 MB/s)
117 09:25:04.633562 end: 1.4.1 http-download (duration 00:00:02) [common]
119 09:25:04.634393 end: 1.4 download-retry (duration 00:00:02) [common]
120 09:25:04.634668 start: 1.5 prepare-tftp-overlay (timeout 00:09:58) [common]
121 09:25:04.634938 start: 1.5.1 extract-nfsrootfs (timeout 00:09:58) [common]
122 09:25:04.635187 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 09:25:04.635442 start: 1.5.2 lava-overlay (timeout 00:09:58) [common]
124 09:25:04.636067 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/922081/lava-overlay-ktiflck5
125 09:25:04.637034 makedir: /var/lib/lava/dispatcher/tmp/922081/lava-overlay-ktiflck5/lava-922081/bin
126 09:25:04.637752 makedir: /var/lib/lava/dispatcher/tmp/922081/lava-overlay-ktiflck5/lava-922081/tests
127 09:25:04.638436 makedir: /var/lib/lava/dispatcher/tmp/922081/lava-overlay-ktiflck5/lava-922081/results
128 09:25:04.639100 Creating /var/lib/lava/dispatcher/tmp/922081/lava-overlay-ktiflck5/lava-922081/bin/lava-add-keys
129 09:25:04.640188 Creating /var/lib/lava/dispatcher/tmp/922081/lava-overlay-ktiflck5/lava-922081/bin/lava-add-sources
130 09:25:04.641226 Creating /var/lib/lava/dispatcher/tmp/922081/lava-overlay-ktiflck5/lava-922081/bin/lava-background-process-start
131 09:25:04.642276 Creating /var/lib/lava/dispatcher/tmp/922081/lava-overlay-ktiflck5/lava-922081/bin/lava-background-process-stop
132 09:25:04.643361 Creating /var/lib/lava/dispatcher/tmp/922081/lava-overlay-ktiflck5/lava-922081/bin/lava-common-functions
133 09:25:04.644422 Creating /var/lib/lava/dispatcher/tmp/922081/lava-overlay-ktiflck5/lava-922081/bin/lava-echo-ipv4
134 09:25:04.645455 Creating /var/lib/lava/dispatcher/tmp/922081/lava-overlay-ktiflck5/lava-922081/bin/lava-install-packages
135 09:25:04.646451 Creating /var/lib/lava/dispatcher/tmp/922081/lava-overlay-ktiflck5/lava-922081/bin/lava-installed-packages
136 09:25:04.647436 Creating /var/lib/lava/dispatcher/tmp/922081/lava-overlay-ktiflck5/lava-922081/bin/lava-os-build
137 09:25:04.648524 Creating /var/lib/lava/dispatcher/tmp/922081/lava-overlay-ktiflck5/lava-922081/bin/lava-probe-channel
138 09:25:04.649533 Creating /var/lib/lava/dispatcher/tmp/922081/lava-overlay-ktiflck5/lava-922081/bin/lava-probe-ip
139 09:25:04.650525 Creating /var/lib/lava/dispatcher/tmp/922081/lava-overlay-ktiflck5/lava-922081/bin/lava-target-ip
140 09:25:04.651565 Creating /var/lib/lava/dispatcher/tmp/922081/lava-overlay-ktiflck5/lava-922081/bin/lava-target-mac
141 09:25:04.652644 Creating /var/lib/lava/dispatcher/tmp/922081/lava-overlay-ktiflck5/lava-922081/bin/lava-target-storage
142 09:25:04.653697 Creating /var/lib/lava/dispatcher/tmp/922081/lava-overlay-ktiflck5/lava-922081/bin/lava-test-case
143 09:25:04.654742 Creating /var/lib/lava/dispatcher/tmp/922081/lava-overlay-ktiflck5/lava-922081/bin/lava-test-event
144 09:25:04.655726 Creating /var/lib/lava/dispatcher/tmp/922081/lava-overlay-ktiflck5/lava-922081/bin/lava-test-feedback
145 09:25:04.656754 Creating /var/lib/lava/dispatcher/tmp/922081/lava-overlay-ktiflck5/lava-922081/bin/lava-test-raise
146 09:25:04.657738 Creating /var/lib/lava/dispatcher/tmp/922081/lava-overlay-ktiflck5/lava-922081/bin/lava-test-reference
147 09:25:04.658721 Creating /var/lib/lava/dispatcher/tmp/922081/lava-overlay-ktiflck5/lava-922081/bin/lava-test-runner
148 09:25:04.659704 Creating /var/lib/lava/dispatcher/tmp/922081/lava-overlay-ktiflck5/lava-922081/bin/lava-test-set
149 09:25:04.660753 Creating /var/lib/lava/dispatcher/tmp/922081/lava-overlay-ktiflck5/lava-922081/bin/lava-test-shell
150 09:25:04.661757 Updating /var/lib/lava/dispatcher/tmp/922081/lava-overlay-ktiflck5/lava-922081/bin/lava-install-packages (oe)
151 09:25:04.662844 Updating /var/lib/lava/dispatcher/tmp/922081/lava-overlay-ktiflck5/lava-922081/bin/lava-installed-packages (oe)
152 09:25:04.663777 Creating /var/lib/lava/dispatcher/tmp/922081/lava-overlay-ktiflck5/lava-922081/environment
153 09:25:04.664617 LAVA metadata
154 09:25:04.665157 - LAVA_JOB_ID=922081
155 09:25:04.665634 - LAVA_DISPATCHER_IP=192.168.6.2
156 09:25:04.666355 start: 1.5.2.1 ssh-authorize (timeout 00:09:58) [common]
157 09:25:04.668415 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 09:25:04.669088 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:58) [common]
159 09:25:04.669547 skipped lava-vland-overlay
160 09:25:04.670092 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 09:25:04.670660 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:58) [common]
162 09:25:04.671136 skipped lava-multinode-overlay
163 09:25:04.671672 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 09:25:04.672269 start: 1.5.2.4 test-definition (timeout 00:09:58) [common]
165 09:25:04.672762 Loading test definitions
166 09:25:04.673315 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:58) [common]
167 09:25:04.673758 Using /lava-922081 at stage 0
168 09:25:04.676016 uuid=922081_1.5.2.4.1 testdef=None
169 09:25:04.676612 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 09:25:04.677134 start: 1.5.2.4.2 test-overlay (timeout 00:09:58) [common]
171 09:25:04.680423 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 09:25:04.681260 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:58) [common]
174 09:25:04.683734 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 09:25:04.684650 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:58) [common]
177 09:25:04.686918 runner path: /var/lib/lava/dispatcher/tmp/922081/lava-overlay-ktiflck5/lava-922081/0/tests/0_dmesg test_uuid 922081_1.5.2.4.1
178 09:25:04.687511 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 09:25:04.688331 Creating lava-test-runner.conf files
181 09:25:04.688543 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/922081/lava-overlay-ktiflck5/lava-922081/0 for stage 0
182 09:25:04.688921 - 0_dmesg
183 09:25:04.689292 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 09:25:04.689581 start: 1.5.2.5 compress-overlay (timeout 00:09:57) [common]
185 09:25:04.713619 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 09:25:04.714053 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:57) [common]
187 09:25:04.714323 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 09:25:04.714595 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 09:25:04.714862 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:57) [common]
190 09:25:05.644341 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
191 09:25:05.644815 start: 1.5.4 extract-modules (timeout 00:09:57) [common]
192 09:25:05.645064 extracting modules file /var/lib/lava/dispatcher/tmp/922081/tftp-deploy-60x18je2/modules/modules.tar to /var/lib/lava/dispatcher/tmp/922081/extract-overlay-ramdisk-4iv8bvcm/ramdisk
193 09:25:07.069679 end: 1.5.4 extract-modules (duration 00:00:01) [common]
194 09:25:07.070285 start: 1.5.5 apply-overlay-tftp (timeout 00:09:55) [common]
195 09:25:07.070623 [common] Applying overlay /var/lib/lava/dispatcher/tmp/922081/compress-overlay-qx9uut5b/overlay-1.5.2.5.tar.gz to ramdisk
196 09:25:07.070889 [common] Applying overlay /var/lib/lava/dispatcher/tmp/922081/compress-overlay-qx9uut5b/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/922081/extract-overlay-ramdisk-4iv8bvcm/ramdisk
197 09:25:07.108099 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 09:25:07.108625 start: 1.5.6 prepare-kernel (timeout 00:09:55) [common]
199 09:25:07.108957 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:55) [common]
200 09:25:07.109232 Converting downloaded kernel to a uImage
201 09:25:07.109602 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/922081/tftp-deploy-60x18je2/kernel/Image /var/lib/lava/dispatcher/tmp/922081/tftp-deploy-60x18je2/kernel/uImage
202 09:25:07.530412 output: Image Name:
203 09:25:07.530824 output: Created: Fri Nov 1 09:25:07 2024
204 09:25:07.531037 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 09:25:07.531243 output: Data Size: 39686656 Bytes = 38756.50 KiB = 37.85 MiB
206 09:25:07.531445 output: Load Address: 01080000
207 09:25:07.531646 output: Entry Point: 01080000
208 09:25:07.531843 output:
209 09:25:07.532214 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
210 09:25:07.532486 end: 1.5.6 prepare-kernel (duration 00:00:00) [common]
211 09:25:07.532756 start: 1.5.7 configure-preseed-file (timeout 00:09:55) [common]
212 09:25:07.533008 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 09:25:07.533265 start: 1.5.8 compress-ramdisk (timeout 00:09:55) [common]
214 09:25:07.533520 Building ramdisk /var/lib/lava/dispatcher/tmp/922081/extract-overlay-ramdisk-4iv8bvcm/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/922081/extract-overlay-ramdisk-4iv8bvcm/ramdisk
215 09:25:10.014237 >> 188653 blocks
216 09:25:18.598480 Adding RAMdisk u-boot header.
217 09:25:18.599194 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/922081/extract-overlay-ramdisk-4iv8bvcm/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/922081/extract-overlay-ramdisk-4iv8bvcm/ramdisk.cpio.gz.uboot
218 09:25:18.887235 output: Image Name:
219 09:25:18.887632 output: Created: Fri Nov 1 09:25:18 2024
220 09:25:18.887836 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 09:25:18.888189 output: Data Size: 26771227 Bytes = 26143.78 KiB = 25.53 MiB
222 09:25:18.888641 output: Load Address: 00000000
223 09:25:18.889098 output: Entry Point: 00000000
224 09:25:18.889530 output:
225 09:25:18.890595 rename /var/lib/lava/dispatcher/tmp/922081/extract-overlay-ramdisk-4iv8bvcm/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/922081/tftp-deploy-60x18je2/ramdisk/ramdisk.cpio.gz.uboot
226 09:25:18.891346 end: 1.5.8 compress-ramdisk (duration 00:00:11) [common]
227 09:25:18.891936 end: 1.5 prepare-tftp-overlay (duration 00:00:14) [common]
228 09:25:18.892555 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:43) [common]
229 09:25:18.893051 No LXC device requested
230 09:25:18.893595 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 09:25:18.894146 start: 1.7 deploy-device-env (timeout 00:09:43) [common]
232 09:25:18.894684 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 09:25:18.895132 Checking files for TFTP limit of 4294967296 bytes.
234 09:25:18.898040 end: 1 tftp-deploy (duration 00:00:17) [common]
235 09:25:18.898664 start: 2 uboot-action (timeout 00:05:00) [common]
236 09:25:18.899236 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 09:25:18.899779 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 09:25:18.900370 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 09:25:18.901484 Using kernel file from prepare-kernel: 922081/tftp-deploy-60x18je2/kernel/uImage
240 09:25:18.902377 substitutions:
241 09:25:18.902861 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 09:25:18.903309 - {DTB_ADDR}: 0x01070000
243 09:25:18.903754 - {DTB}: 922081/tftp-deploy-60x18je2/dtb/meson-sm1-s905d3-libretech-cc.dtb
244 09:25:18.904236 - {INITRD}: 922081/tftp-deploy-60x18je2/ramdisk/ramdisk.cpio.gz.uboot
245 09:25:18.904675 - {KERNEL_ADDR}: 0x01080000
246 09:25:18.905106 - {KERNEL}: 922081/tftp-deploy-60x18je2/kernel/uImage
247 09:25:18.905540 - {LAVA_MAC}: None
248 09:25:18.906015 - {PRESEED_CONFIG}: None
249 09:25:18.906453 - {PRESEED_LOCAL}: None
250 09:25:18.906880 - {RAMDISK_ADDR}: 0x08000000
251 09:25:18.907309 - {RAMDISK}: 922081/tftp-deploy-60x18je2/ramdisk/ramdisk.cpio.gz.uboot
252 09:25:18.907743 - {ROOT_PART}: None
253 09:25:18.908238 - {ROOT}: None
254 09:25:18.908674 - {SERVER_IP}: 192.168.6.2
255 09:25:18.909111 - {TEE_ADDR}: 0x83000000
256 09:25:18.909540 - {TEE}: None
257 09:25:18.909971 Parsed boot commands:
258 09:25:18.910388 - setenv autoload no
259 09:25:18.910817 - setenv initrd_high 0xffffffff
260 09:25:18.911243 - setenv fdt_high 0xffffffff
261 09:25:18.911667 - dhcp
262 09:25:18.912125 - setenv serverip 192.168.6.2
263 09:25:18.912556 - tftpboot 0x01080000 922081/tftp-deploy-60x18je2/kernel/uImage
264 09:25:18.912988 - tftpboot 0x08000000 922081/tftp-deploy-60x18je2/ramdisk/ramdisk.cpio.gz.uboot
265 09:25:18.913417 - tftpboot 0x01070000 922081/tftp-deploy-60x18je2/dtb/meson-sm1-s905d3-libretech-cc.dtb
266 09:25:18.913847 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 09:25:18.914285 - bootm 0x01080000 0x08000000 0x01070000
268 09:25:18.914831 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 09:25:18.916484 start: 2.3 connect-device (timeout 00:05:00) [common]
271 09:25:18.916969 [common] connect-device Connecting to device using 'telnet conserv1 3008'
272 09:25:18.931887 Setting prompt string to ['lava-test: # ']
273 09:25:18.933492 end: 2.3 connect-device (duration 00:00:00) [common]
274 09:25:18.934133 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 09:25:18.934726 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 09:25:18.935294 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 09:25:18.936574 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=solitude-01'
278 09:25:18.973162 >> OK - accepted request
279 09:25:18.975497 Returned 0 in 0 seconds
280 09:25:19.076715 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
282 09:25:19.078420 end: 2.4.1 reset-device (duration 00:00:00) [common]
283 09:25:19.079038 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
284 09:25:19.079583 Setting prompt string to ['Hit any key to stop autoboot']
285 09:25:19.080126 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 09:25:19.081825 Trying 192.168.56.21...
287 09:25:19.082337 Connected to conserv1.
288 09:25:19.082784 Escape character is '^]'.
289 09:25:19.083251
290 09:25:19.083720 ser2net port telnet,3008 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.3.3:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
291 09:25:19.084231
292 09:25:26.487390 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
293 09:25:26.488096 bl2_stage_init 0x01
294 09:25:26.488585 bl2_stage_init 0x81
295 09:25:26.492983 hw id: 0x0000 - pwm id 0x01
296 09:25:26.493498 bl2_stage_init 0xc1
297 09:25:26.497917 bl2_stage_init 0x02
298 09:25:26.498408
299 09:25:26.498858 L0:00000000
300 09:25:26.499300 L1:00000703
301 09:25:26.499734 L2:00008067
302 09:25:26.503429 L3:15000000
303 09:25:26.503918 S1:00000000
304 09:25:26.504397 B2:20282000
305 09:25:26.504835 B1:a0f83180
306 09:25:26.505267
307 09:25:26.505698 TE: 69038
308 09:25:26.506135
309 09:25:26.514666 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
310 09:25:26.515151
311 09:25:26.515588 Board ID = 1
312 09:25:26.516052 Set cpu clk to 24M
313 09:25:26.516487 Set clk81 to 24M
314 09:25:26.518271 Use GP1_pll as DSU clk.
315 09:25:26.518735 DSU clk: 1200 Mhz
316 09:25:26.523880 CPU clk: 1200 MHz
317 09:25:26.524380 Set clk81 to 166.6M
318 09:25:26.529454 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
319 09:25:26.529923 board id: 1
320 09:25:26.539255 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
321 09:25:26.549908 fw parse done
322 09:25:26.555888 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
323 09:25:26.598700 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
324 09:25:26.609487 PIEI prepare done
325 09:25:26.610011 fastboot data load
326 09:25:26.610456 fastboot data verify
327 09:25:26.615077 verify result: 266
328 09:25:26.620661 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
329 09:25:26.621148 LPDDR4 probe
330 09:25:26.621585 ddr clk to 1584MHz
331 09:25:26.628658 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
332 09:25:26.666069
333 09:25:26.666627 dmc_version 0001
334 09:25:26.672715 Check phy result
335 09:25:26.678513 INFO : End of CA training
336 09:25:26.679018 INFO : End of initialization
337 09:25:26.684247 INFO : Training has run successfully!
338 09:25:26.684790 Check phy result
339 09:25:26.689685 INFO : End of initialization
340 09:25:26.690205 INFO : End of read enable training
341 09:25:26.692972 INFO : End of fine write leveling
342 09:25:26.698670 INFO : End of Write leveling coarse delay
343 09:25:26.704262 INFO : Training has run successfully!
344 09:25:26.704770 Check phy result
345 09:25:26.705218 INFO : End of initialization
346 09:25:26.709852 INFO : End of read dq deskew training
347 09:25:26.715389 INFO : End of MPR read delay center optimization
348 09:25:26.715877 INFO : End of write delay center optimization
349 09:25:26.721056 INFO : End of read delay center optimization
350 09:25:26.726699 INFO : End of max read latency training
351 09:25:26.727213 INFO : Training has run successfully!
352 09:25:26.732276 1D training succeed
353 09:25:26.738146 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
354 09:25:26.785720 Check phy result
355 09:25:26.786275 INFO : End of initialization
356 09:25:26.808058 INFO : End of 2D read delay Voltage center optimization
357 09:25:26.827171 INFO : End of 2D read delay Voltage center optimization
358 09:25:26.879129 INFO : End of 2D write delay Voltage center optimization
359 09:25:26.928305 INFO : End of 2D write delay Voltage center optimization
360 09:25:26.933872 INFO : Training has run successfully!
361 09:25:26.934385
362 09:25:26.934851 channel==0
363 09:25:26.939457 RxClkDly_Margin_A0==88 ps 9
364 09:25:26.939932 TxDqDly_Margin_A0==98 ps 10
365 09:25:26.942813 RxClkDly_Margin_A1==69 ps 7
366 09:25:26.943299 TxDqDly_Margin_A1==88 ps 9
367 09:25:26.948442 TrainedVREFDQ_A0==74
368 09:25:26.948954 TrainedVREFDQ_A1==74
369 09:25:26.949412 VrefDac_Margin_A0==24
370 09:25:26.954213 DeviceVref_Margin_A0==40
371 09:25:26.954722 VrefDac_Margin_A1==23
372 09:25:26.959773 DeviceVref_Margin_A1==40
373 09:25:26.960318
374 09:25:26.960763
375 09:25:26.961200 channel==1
376 09:25:26.961652 RxClkDly_Margin_A0==78 ps 8
377 09:25:26.963083 TxDqDly_Margin_A0==98 ps 10
378 09:25:26.968568 RxClkDly_Margin_A1==78 ps 8
379 09:25:26.969078 TxDqDly_Margin_A1==98 ps 10
380 09:25:26.969538 TrainedVREFDQ_A0==78
381 09:25:26.974124 TrainedVREFDQ_A1==75
382 09:25:26.974666 VrefDac_Margin_A0==22
383 09:25:26.979811 DeviceVref_Margin_A0==36
384 09:25:26.980368 VrefDac_Margin_A1==22
385 09:25:26.980826 DeviceVref_Margin_A1==39
386 09:25:26.981264
387 09:25:26.985184 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
388 09:25:26.985678
389 09:25:27.018772 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000017 00000017 00000018 00000019 00000017 00000018 00000015 00000018 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001c 00000017 00000015 00000017 dram_vref_reg_value 0x 00000061
390 09:25:27.019359 2D training succeed
391 09:25:27.024386 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
392 09:25:27.029970 auto size-- 65535DDR cs0 size: 2048MB
393 09:25:27.030456 DDR cs1 size: 2048MB
394 09:25:27.035677 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
395 09:25:27.036198 cs0 DataBus test pass
396 09:25:27.036652 cs1 DataBus test pass
397 09:25:27.041191 cs0 AddrBus test pass
398 09:25:27.041685 cs1 AddrBus test pass
399 09:25:27.042123
400 09:25:27.046813 100bdlr_step_size ps== 478
401 09:25:27.047329 result report
402 09:25:27.047783 boot times 0Enable ddr reg access
403 09:25:27.056640 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
404 09:25:27.070430 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
405 09:25:27.725378 bl2z: ptr: 05129330, size: 00001e40
406 09:25:27.731963 0.0;M3 CHK:0;cm4_sp_mode 0
407 09:25:27.732514 MVN_1=0x00000000
408 09:25:27.732969 MVN_2=0x00000000
409 09:25:27.743450 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
410 09:25:27.743929 OPS=0x04
411 09:25:27.744420 ring efuse init
412 09:25:27.749081 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
413 09:25:27.749562 [0.017319 Inits done]
414 09:25:27.750010 secure task start!
415 09:25:27.756546 high task start!
416 09:25:27.757014 low task start!
417 09:25:27.757461 run into bl31
418 09:25:27.765162 NOTICE: BL31: v1.3(release):4fc40b1
419 09:25:27.772973 NOTICE: BL31: Built : 15:57:33, May 22 2019
420 09:25:27.773450 NOTICE: BL31: G12A normal boot!
421 09:25:27.788444 NOTICE: BL31: BL33 decompress pass
422 09:25:27.794156 ERROR: Error initializing runtime service opteed_fast
423 09:25:29.039396 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
424 09:25:29.039923 bl2_stage_init 0x01
425 09:25:29.040431 bl2_stage_init 0x81
426 09:25:29.044952 hw id: 0x0000 - pwm id 0x01
427 09:25:29.045423 bl2_stage_init 0xc1
428 09:25:29.050562 bl2_stage_init 0x02
429 09:25:29.051028
430 09:25:29.051482 L0:00000000
431 09:25:29.051923 L1:00000703
432 09:25:29.052411 L2:00008067
433 09:25:29.052847 L3:15000000
434 09:25:29.056171 S1:00000000
435 09:25:29.056638 B2:20282000
436 09:25:29.057090 B1:a0f83180
437 09:25:29.057533
438 09:25:29.057971 TE: 70936
439 09:25:29.058410
440 09:25:29.061757 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
441 09:25:29.062223
442 09:25:29.067354 Board ID = 1
443 09:25:29.067816 Set cpu clk to 24M
444 09:25:29.068297 Set clk81 to 24M
445 09:25:29.072953 Use GP1_pll as DSU clk.
446 09:25:29.073419 DSU clk: 1200 Mhz
447 09:25:29.073864 CPU clk: 1200 MHz
448 09:25:29.078531 Set clk81 to 166.6M
449 09:25:29.084148 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
450 09:25:29.084615 board id: 1
451 09:25:29.091355 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
452 09:25:29.102056 fw parse done
453 09:25:29.108032 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
454 09:25:29.150617 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
455 09:25:29.161605 PIEI prepare done
456 09:25:29.162055 fastboot data load
457 09:25:29.162486 fastboot data verify
458 09:25:29.167173 verify result: 266
459 09:25:29.172827 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
460 09:25:29.173298 LPDDR4 probe
461 09:25:29.173726 ddr clk to 1584MHz
462 09:25:30.538977 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
463 09:25:30.539621 bl2_stage_init 0x01
464 09:25:30.540135 bl2_stage_init 0x81
465 09:25:30.544549 hw id: 0x0000 - pwm id 0x01
466 09:25:30.545028 bl2_stage_init 0xc1
467 09:25:30.549291 bl2_stage_init 0x02
468 09:25:30.549765
469 09:25:30.550214 L0:00000000
470 09:25:30.550660 L1:00000703
471 09:25:30.551107 L2:00008067
472 09:25:30.554880 L3:15000000
473 09:25:30.555349 S1:00000000
474 09:25:30.555794 B2:20282000
475 09:25:30.556275 B1:a0f83180
476 09:25:30.556712
477 09:25:30.557150 TE: 69955
478 09:25:30.557586
479 09:25:30.566089 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
480 09:25:30.566564
481 09:25:30.567010 Board ID = 1
482 09:25:30.567446 Set cpu clk to 24M
483 09:25:30.567882 Set clk81 to 24M
484 09:25:30.571670 Use GP1_pll as DSU clk.
485 09:25:30.572174 DSU clk: 1200 Mhz
486 09:25:30.572622 CPU clk: 1200 MHz
487 09:25:30.577256 Set clk81 to 166.6M
488 09:25:30.582870 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
489 09:25:30.583340 board id: 1
490 09:25:30.590941 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
491 09:25:30.601605 fw parse done
492 09:25:30.606627 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
493 09:25:30.650218 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
494 09:25:30.661212 PIEI prepare done
495 09:25:30.661670 fastboot data load
496 09:25:30.662117 fastboot data verify
497 09:25:30.666795 verify result: 266
498 09:25:30.672368 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
499 09:25:30.672839 LPDDR4 probe
500 09:25:30.673281 ddr clk to 1584MHz
501 09:25:30.680334 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
502 09:25:30.717577
503 09:25:30.718042 dmc_version 0001
504 09:25:30.724059 Check phy result
505 09:25:30.730169 INFO : End of CA training
506 09:25:30.730630 INFO : End of initialization
507 09:25:30.735793 INFO : Training has run successfully!
508 09:25:30.736289 Check phy result
509 09:25:30.741379 INFO : End of initialization
510 09:25:30.741847 INFO : End of read enable training
511 09:25:30.747050 INFO : End of fine write leveling
512 09:25:30.752585 INFO : End of Write leveling coarse delay
513 09:25:30.753050 INFO : Training has run successfully!
514 09:25:30.753497 Check phy result
515 09:25:30.758166 INFO : End of initialization
516 09:25:30.758638 INFO : End of read dq deskew training
517 09:25:30.763772 INFO : End of MPR read delay center optimization
518 09:25:30.769417 INFO : End of write delay center optimization
519 09:25:30.774982 INFO : End of read delay center optimization
520 09:25:30.775446 INFO : End of max read latency training
521 09:25:30.780587 INFO : Training has run successfully!
522 09:25:30.781054 1D training succeed
523 09:25:30.788907 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
524 09:25:30.837334 Check phy result
525 09:25:30.837801 INFO : End of initialization
526 09:25:30.859701 INFO : End of 2D read delay Voltage center optimization
527 09:25:30.878852 INFO : End of 2D read delay Voltage center optimization
528 09:25:30.930718 INFO : End of 2D write delay Voltage center optimization
529 09:25:30.979892 INFO : End of 2D write delay Voltage center optimization
530 09:25:30.985498 INFO : Training has run successfully!
531 09:25:30.985958
532 09:25:30.986409 channel==0
533 09:25:30.991225 RxClkDly_Margin_A0==78 ps 8
534 09:25:30.991698 TxDqDly_Margin_A0==98 ps 10
535 09:25:30.996701 RxClkDly_Margin_A1==88 ps 9
536 09:25:30.997161 TxDqDly_Margin_A1==98 ps 10
537 09:25:30.997606 TrainedVREFDQ_A0==74
538 09:25:31.002278 TrainedVREFDQ_A1==74
539 09:25:31.002739 VrefDac_Margin_A0==24
540 09:25:31.003183 DeviceVref_Margin_A0==40
541 09:25:31.007876 VrefDac_Margin_A1==23
542 09:25:31.008371 DeviceVref_Margin_A1==40
543 09:25:31.008817
544 09:25:31.009261
545 09:25:31.013477 channel==1
546 09:25:31.013941 RxClkDly_Margin_A0==88 ps 9
547 09:25:31.014380 TxDqDly_Margin_A0==98 ps 10
548 09:25:31.019232 RxClkDly_Margin_A1==78 ps 8
549 09:25:31.019696 TxDqDly_Margin_A1==88 ps 9
550 09:25:31.024716 TrainedVREFDQ_A0==75
551 09:25:31.025185 TrainedVREFDQ_A1==77
552 09:25:31.025630 VrefDac_Margin_A0==22
553 09:25:31.030305 DeviceVref_Margin_A0==39
554 09:25:31.030771 VrefDac_Margin_A1==22
555 09:25:31.035895 DeviceVref_Margin_A1==37
556 09:25:31.036392
557 09:25:31.036837 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
558 09:25:31.037278
559 09:25:31.069508 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000017 00000015 00000017 00000017 00000017 00000017 00000017 00000017 00000017 00000018 00000018 00000017 00000018 00000015 00000017 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001c 00000017 00000016 00000017 dram_vref_reg_value 0x 00000061
560 09:25:31.070014 2D training succeed
561 09:25:31.075091 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
562 09:25:31.080689 auto size-- 65535DDR cs0 size: 2048MB
563 09:25:31.081157 DDR cs1 size: 2048MB
564 09:25:31.086309 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
565 09:25:31.086772 cs0 DataBus test pass
566 09:25:31.091901 cs1 DataBus test pass
567 09:25:31.092405 cs0 AddrBus test pass
568 09:25:31.092850 cs1 AddrBus test pass
569 09:25:31.093289
570 09:25:31.097491 100bdlr_step_size ps== 478
571 09:25:31.097974 result report
572 09:25:31.103094 boot times 0Enable ddr reg access
573 09:25:31.108335 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
574 09:25:31.122302 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
575 09:25:31.777111 bl2z: ptr: 05129330, size: 00001e40
576 09:25:31.784158 0.0;M3 CHK:0;cm4_sp_mode 0
577 09:25:31.784645 MVN_1=0x00000000
578 09:25:31.785089 MVN_2=0x00000000
579 09:25:31.795615 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
580 09:25:31.796133 OPS=0x04
581 09:25:31.796583 ring efuse init
582 09:25:31.801262 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
583 09:25:31.801743 [0.017310 Inits done]
584 09:25:31.802185 secure task start!
585 09:25:31.809303 high task start!
586 09:25:31.809773 low task start!
587 09:25:31.810212 run into bl31
588 09:25:31.817953 NOTICE: BL31: v1.3(release):4fc40b1
589 09:25:31.825758 NOTICE: BL31: Built : 15:57:33, May 22 2019
590 09:25:31.826232 NOTICE: BL31: G12A normal boot!
591 09:25:31.841262 NOTICE: BL31: BL33 decompress pass
592 09:25:31.846939 ERROR: Error initializing runtime service opteed_fast
593 09:25:33.236402 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
594 09:25:33.236962 bl2_stage_init 0x01
595 09:25:33.237390 bl2_stage_init 0x81
596 09:25:33.242047 hw id: 0x0000 - pwm id 0x01
597 09:25:33.242499 bl2_stage_init 0xc1
598 09:25:33.247683 bl2_stage_init 0x02
599 09:25:33.248170
600 09:25:33.248594 L0:00000000
601 09:25:33.248999 L1:00000703
602 09:25:33.249399 L2:00008067
603 09:25:33.249796 L3:15000000
604 09:25:33.253175 S1:00000000
605 09:25:33.253618 B2:20282000
606 09:25:33.254029 B1:a0f83180
607 09:25:33.254428
608 09:25:33.254823 TE: 67844
609 09:25:33.255217
610 09:25:33.258909 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
611 09:25:33.259369
612 09:25:33.264291 Board ID = 1
613 09:25:33.264732 Set cpu clk to 24M
614 09:25:33.265137 Set clk81 to 24M
615 09:25:33.269900 Use GP1_pll as DSU clk.
616 09:25:33.270337 DSU clk: 1200 Mhz
617 09:25:33.270744 CPU clk: 1200 MHz
618 09:25:33.275531 Set clk81 to 166.6M
619 09:25:33.281098 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
620 09:25:33.281541 board id: 1
621 09:25:33.288315 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
622 09:25:33.299169 fw parse done
623 09:25:33.305174 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
624 09:25:33.348302 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
625 09:25:33.359531 PIEI prepare done
626 09:25:33.360022 fastboot data load
627 09:25:33.360444 fastboot data verify
628 09:25:33.365050 verify result: 266
629 09:25:33.370677 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
630 09:25:33.371132 LPDDR4 probe
631 09:25:33.371540 ddr clk to 1584MHz
632 09:25:33.377838 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
633 09:25:33.416393
634 09:25:33.416850 dmc_version 0001
635 09:25:33.423454 Check phy result
636 09:25:33.429414 INFO : End of CA training
637 09:25:33.429865 INFO : End of initialization
638 09:25:33.435017 INFO : Training has run successfully!
639 09:25:33.435474 Check phy result
640 09:25:33.440661 INFO : End of initialization
641 09:25:33.441111 INFO : End of read enable training
642 09:25:33.446178 INFO : End of fine write leveling
643 09:25:33.451812 INFO : End of Write leveling coarse delay
644 09:25:33.452292 INFO : Training has run successfully!
645 09:25:33.452698 Check phy result
646 09:25:33.457426 INFO : End of initialization
647 09:25:33.457878 INFO : End of read dq deskew training
648 09:25:33.462988 INFO : End of MPR read delay center optimization
649 09:25:33.468651 INFO : End of write delay center optimization
650 09:25:33.474160 INFO : End of read delay center optimization
651 09:25:33.474611 INFO : End of max read latency training
652 09:25:33.479797 INFO : Training has run successfully!
653 09:25:33.480285 1D training succeed
654 09:25:33.488963 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
655 09:25:33.537264 Check phy result
656 09:25:33.537716 INFO : End of initialization
657 09:25:33.564659 INFO : End of 2D read delay Voltage center optimization
658 09:25:33.588848 INFO : End of 2D read delay Voltage center optimization
659 09:25:33.645498 INFO : End of 2D write delay Voltage center optimization
660 09:25:33.699577 INFO : End of 2D write delay Voltage center optimization
661 09:25:33.705135 INFO : Training has run successfully!
662 09:25:33.705586
663 09:25:33.706008 channel==0
664 09:25:33.710877 RxClkDly_Margin_A0==78 ps 8
665 09:25:33.711327 TxDqDly_Margin_A0==98 ps 10
666 09:25:33.716393 RxClkDly_Margin_A1==69 ps 7
667 09:25:33.716863 TxDqDly_Margin_A1==98 ps 10
668 09:25:33.717278 TrainedVREFDQ_A0==74
669 09:25:33.721954 TrainedVREFDQ_A1==74
670 09:25:33.722408 VrefDac_Margin_A0==24
671 09:25:33.722814 DeviceVref_Margin_A0==40
672 09:25:33.727564 VrefDac_Margin_A1==23
673 09:25:33.728041 DeviceVref_Margin_A1==40
674 09:25:33.728454
675 09:25:33.728855
676 09:25:33.733213 channel==1
677 09:25:33.733661 RxClkDly_Margin_A0==78 ps 8
678 09:25:33.734064 TxDqDly_Margin_A0==98 ps 10
679 09:25:33.738808 RxClkDly_Margin_A1==78 ps 8
680 09:25:33.739260 TxDqDly_Margin_A1==88 ps 9
681 09:25:33.744339 TrainedVREFDQ_A0==78
682 09:25:33.744796 TrainedVREFDQ_A1==77
683 09:25:33.745205 VrefDac_Margin_A0==22
684 09:25:33.750007 DeviceVref_Margin_A0==36
685 09:25:33.750458 VrefDac_Margin_A1==22
686 09:25:33.755554 DeviceVref_Margin_A1==37
687 09:25:33.756038
688 09:25:33.756457 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
689 09:25:33.756858
690 09:25:33.788951 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000018 00000017 00000018 00000018 00000017 00000018 00000015 00000018 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001c 00000017 00000016 00000017 dram_vref_reg_value 0x 00000061
691 09:25:33.789434 2D training succeed
692 09:25:33.794692 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
693 09:25:33.800241 auto size-- 65535DDR cs0 size: 2048MB
694 09:25:33.800693 DDR cs1 size: 2048MB
695 09:25:33.805795 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
696 09:25:33.806250 cs0 DataBus test pass
697 09:25:33.811407 cs1 DataBus test pass
698 09:25:33.811856 cs0 AddrBus test pass
699 09:25:33.812312 cs1 AddrBus test pass
700 09:25:33.812710
701 09:25:33.816994 100bdlr_step_size ps== 471
702 09:25:33.817456 result report
703 09:25:33.822665 boot times 0Enable ddr reg access
704 09:25:33.827859 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
705 09:25:33.841680 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
706 09:25:34.501210 bl2z: ptr: 05129330, size: 00001e40
707 09:25:34.508425 0.0;M3 CHK:0;cm4_sp_mode 0
708 09:25:34.508912 MVN_1=0x00000000
709 09:25:34.509307 MVN_2=0x00000000
710 09:25:34.519913 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
711 09:25:34.520451 OPS=0x04
712 09:25:34.520846 ring efuse init
713 09:25:34.525522 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
714 09:25:34.525974 [0.017354 Inits done]
715 09:25:34.526363 secure task start!
716 09:25:34.532910 high task start!
717 09:25:34.533343 low task start!
718 09:25:34.533730 run into bl31
719 09:25:34.541503 NOTICE: BL31: v1.3(release):4fc40b1
720 09:25:34.549302 NOTICE: BL31: Built : 15:57:33, May 22 2019
721 09:25:34.549734 NOTICE: BL31: G12A normal boot!
722 09:25:34.564942 NOTICE: BL31: BL33 decompress pass
723 09:25:34.570761 ERROR: Error initializing runtime service opteed_fast
724 09:25:35.366039
725 09:25:35.366603
726 09:25:35.371452 U-Boot 2024.01-rc4+ (Dec 14 2023 - 02:26:00 -0500) Libre Computer AML-S905D3-CC
727 09:25:35.371924
728 09:25:35.374952 Model: Libre Computer AML-S905D3-CC Solitude
729 09:25:35.520976 SoC: Amlogic Meson SM1 (S905D3) Revision 2b:c (4:2)
730 09:25:35.536443 DRAM: 2 GiB (effective 3.8 GiB)
731 09:25:35.638281 Core: 406 devices, 33 uclasses, devicetree: separate
732 09:25:35.643254 WDT: Not starting watchdog@f0d0
733 09:25:35.669243 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
734 09:25:35.681496 Loading Environment from FAT... Card did not respond to voltage select! : -110
735 09:25:35.685533 ** Bad device specification mmc 0 **
736 09:25:35.696530 Card did not respond to voltage select! : -110
737 09:25:35.703246 ** Bad device specification mmc 0 **
738 09:25:35.703697 Couldn't find partition mmc 0
739 09:25:35.712550 Card did not respond to voltage select! : -110
740 09:25:35.718106 ** Bad device specification mmc 0 **
741 09:25:35.718732 Couldn't find partition mmc 0
742 09:25:35.722262 Error: could not access storage.
743 09:25:36.019556 Net: eth0: ethernet@ff3f0000
744 09:25:36.020284 starting USB...
745 09:25:36.264300 Bus usb@ff500000: Register 3000140 NbrPorts 3
746 09:25:36.264970 Starting the controller
747 09:25:36.271218 USB XHCI 1.10
748 09:25:37.828244 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
749 09:25:37.833913 scanning usb for storage devices... 0 Storage Device(s) found
751 09:25:37.886021 Hit any key to stop autoboot: 1
752 09:25:37.887306 end: 2.4.2 bootloader-interrupt (duration 00:00:19) [common]
753 09:25:37.888145 start: 2.4.3 bootloader-commands (timeout 00:04:41) [common]
754 09:25:37.888786 Setting prompt string to ['=>']
755 09:25:37.889411 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:41)
756 09:25:37.899796 0
757 09:25:37.901055 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
759 09:25:38.002720 => setenv autoload no
760 09:25:38.003738 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
761 09:25:38.009973 setenv autoload no
763 09:25:38.111914 => setenv initrd_high 0xffffffff
764 09:25:38.112637 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
765 09:25:38.117008 setenv initrd_high 0xffffffff
767 09:25:38.218234 => setenv fdt_high 0xffffffff
768 09:25:38.219047 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
769 09:25:38.223334 setenv fdt_high 0xffffffff
771 09:25:38.325063 => dhcp
772 09:25:38.325808 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
773 09:25:38.329895 dhcp
774 09:25:39.284787 ethernet@ff3f0000 Waiting for PHY auto negotiation to complete.. done
775 09:25:39.285528 Speed: 1000, full duplex
776 09:25:39.286077 BOOTP broadcast 1
777 09:25:39.533014 BOOTP broadcast 2
778 09:25:39.547924 DHCP client bound to address 192.168.6.21 (262 ms)
780 09:25:39.649749 => setenv serverip 192.168.6.2
781 09:25:39.650512 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:39)
782 09:25:39.653877 setenv serverip 192.168.6.2
784 09:25:39.755584 => tftpboot 0x01080000 922081/tftp-deploy-60x18je2/kernel/uImage
785 09:25:39.756492 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:39)
786 09:25:39.762982 tftpboot 0x01080000 922081/tftp-deploy-60x18je2/kernel/uImage
787 09:25:39.763571 Speed: 1000, full duplex
788 09:25:39.764132 Using ethernet@ff3f0000 device
789 09:25:39.768490 TFTP from server 192.168.6.2; our IP address is 192.168.6.21
790 09:25:39.774015 Filename '922081/tftp-deploy-60x18je2/kernel/uImage'.
791 09:25:39.777447 Load address: 0x1080000
792 09:25:42.280638 Loading: *################################################## 37.8 MiB
793 09:25:42.281292 15.1 MiB/s
794 09:25:42.281788 done
795 09:25:42.284904 Bytes transferred = 39686720 (25d9240 hex)
797 09:25:42.386106 => tftpboot 0x08000000 922081/tftp-deploy-60x18je2/ramdisk/ramdisk.cpio.gz.uboot
798 09:25:42.386963 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:37)
799 09:25:42.393673 tftpboot 0x08000000 922081/tftp-deploy-60x18je2/ramdisk/ramdisk.cpio.gz.uboot
800 09:25:42.394250 Speed: 1000, full duplex
801 09:25:42.394701 Using ethernet@ff3f0000 device
802 09:25:42.399202 TFTP from server 192.168.6.2; our IP address is 192.168.6.21
803 09:25:42.408827 Filename '922081/tftp-deploy-60x18je2/ramdisk/ramdisk.cpio.gz.uboot'.
804 09:25:42.409291 Load address: 0x8000000
805 09:25:44.182017 Loading: *################################################# UDP wrong checksum 00000005 00000771
806 09:25:49.183300 T UDP wrong checksum 00000005 00000771
807 09:25:59.185272 T T UDP wrong checksum 00000005 00000771
808 09:26:09.669871 T T UDP wrong checksum 000000ff 0000bd32
809 09:26:09.831565 UDP wrong checksum 000000ff 00005325
810 09:26:14.051742 UDP wrong checksum 000000ff 0000a638
811 09:26:14.101467 UDP wrong checksum 000000ff 0000392b
812 09:26:19.189164 T T UDP wrong checksum 00000005 00000771
813 09:26:23.377091 UDP wrong checksum 000000ff 0000917b
814 09:26:23.413284 UDP wrong checksum 000000ff 00002d6e
815 09:26:39.193875 T T T
816 09:26:39.194477 Retry count exceeded; starting again
818 09:26:39.195963 end: 2.4.3 bootloader-commands (duration 00:01:01) [common]
821 09:26:39.197883 end: 2.4 uboot-commands (duration 00:01:20) [common]
823 09:26:39.199248 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
825 09:26:39.200318 end: 2 uboot-action (duration 00:01:20) [common]
827 09:26:39.201814 Cleaning after the job
828 09:26:39.202358 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/922081/tftp-deploy-60x18je2/ramdisk
829 09:26:39.203585 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/922081/tftp-deploy-60x18je2/kernel
830 09:26:39.210101 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/922081/tftp-deploy-60x18je2/dtb
831 09:26:39.211189 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/922081/tftp-deploy-60x18je2/modules
832 09:26:39.217336 start: 4.1 power-off (timeout 00:00:30) [common]
833 09:26:39.218313 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=solitude-01'
834 09:26:39.251373 >> OK - accepted request
835 09:26:39.253876 Returned 0 in 0 seconds
836 09:26:39.354994 end: 4.1 power-off (duration 00:00:00) [common]
838 09:26:39.356698 start: 4.2 read-feedback (timeout 00:10:00) [common]
839 09:26:39.357830 Listened to connection for namespace 'common' for up to 1s
840 09:26:40.358748 Finalising connection for namespace 'common'
841 09:26:40.359629 Disconnecting from shell: Finalise
842 09:26:40.360226 =>
843 09:26:40.461300 end: 4.2 read-feedback (duration 00:00:01) [common]
844 09:26:40.462035 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/922081
845 09:26:40.747475 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/922081
846 09:26:40.748113 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.