Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 09:14:20.567914 lava-dispatcher, installed at version: 2024.01
2 09:14:20.568705 start: 0 validate
3 09:14:20.569178 Start time: 2024-11-01 09:14:20.569149+00:00 (UTC)
4 09:14:20.569705 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 09:14:20.570245 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 09:14:20.610891 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 09:14:20.611441 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241101%2Farm64%2Fdefconfig%2Bkselftest%2Fgcc-12%2Fkernel%2FImage exists
8 09:14:20.643719 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 09:14:20.644356 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241101%2Farm64%2Fdefconfig%2Bkselftest%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 09:14:20.671677 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 09:14:20.672228 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 09:14:20.704480 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 09:14:20.705002 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241101%2Farm64%2Fdefconfig%2Bkselftest%2Fgcc-12%2Fmodules.tar.xz exists
14 09:14:20.742790 validate duration: 0.17
16 09:14:20.743640 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 09:14:20.743962 start: 1.1 download-retry (timeout 00:10:00) [common]
18 09:14:20.744315 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 09:14:20.744896 Not decompressing ramdisk as can be used compressed.
20 09:14:20.745358 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm/20240313.0/arm64/initrd.cpio.gz
21 09:14:20.745639 saving as /var/lib/lava/dispatcher/tmp/921892/tftp-deploy-5oml_rjo/ramdisk/initrd.cpio.gz
22 09:14:20.745899 total size: 5628182 (5 MB)
23 09:14:20.781786 progress 0 % (0 MB)
24 09:14:20.786230 progress 5 % (0 MB)
25 09:14:20.790857 progress 10 % (0 MB)
26 09:14:20.794880 progress 15 % (0 MB)
27 09:14:20.799455 progress 20 % (1 MB)
28 09:14:20.803428 progress 25 % (1 MB)
29 09:14:20.807870 progress 30 % (1 MB)
30 09:14:20.812284 progress 35 % (1 MB)
31 09:14:20.816233 progress 40 % (2 MB)
32 09:14:20.820517 progress 45 % (2 MB)
33 09:14:20.824483 progress 50 % (2 MB)
34 09:14:20.828847 progress 55 % (2 MB)
35 09:14:20.833214 progress 60 % (3 MB)
36 09:14:20.837100 progress 65 % (3 MB)
37 09:14:20.841494 progress 70 % (3 MB)
38 09:14:20.845357 progress 75 % (4 MB)
39 09:14:20.849738 progress 80 % (4 MB)
40 09:14:20.853630 progress 85 % (4 MB)
41 09:14:20.857934 progress 90 % (4 MB)
42 09:14:20.862601 progress 95 % (5 MB)
43 09:14:20.866116 progress 100 % (5 MB)
44 09:14:20.866829 5 MB downloaded in 0.12 s (44.39 MB/s)
45 09:14:20.867478 end: 1.1.1 http-download (duration 00:00:00) [common]
47 09:14:20.868638 end: 1.1 download-retry (duration 00:00:00) [common]
48 09:14:20.869039 start: 1.2 download-retry (timeout 00:10:00) [common]
49 09:14:20.869405 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 09:14:20.869964 downloading http://storage.kernelci.org/next/master/next-20241101/arm64/defconfig+kselftest/gcc-12/kernel/Image
51 09:14:20.870280 saving as /var/lib/lava/dispatcher/tmp/921892/tftp-deploy-5oml_rjo/kernel/Image
52 09:14:20.870548 total size: 66843136 (63 MB)
53 09:14:20.870824 No compression specified
54 09:14:20.908117 progress 0 % (0 MB)
55 09:14:20.955532 progress 5 % (3 MB)
56 09:14:21.002793 progress 10 % (6 MB)
57 09:14:21.049962 progress 15 % (9 MB)
58 09:14:21.097087 progress 20 % (12 MB)
59 09:14:21.144996 progress 25 % (15 MB)
60 09:14:21.192220 progress 30 % (19 MB)
61 09:14:21.239951 progress 35 % (22 MB)
62 09:14:21.287804 progress 40 % (25 MB)
63 09:14:21.335576 progress 45 % (28 MB)
64 09:14:21.383403 progress 50 % (31 MB)
65 09:14:21.431294 progress 55 % (35 MB)
66 09:14:21.479207 progress 60 % (38 MB)
67 09:14:21.528347 progress 65 % (41 MB)
68 09:14:21.577828 progress 70 % (44 MB)
69 09:14:21.655762 progress 75 % (47 MB)
70 09:14:21.706249 progress 80 % (51 MB)
71 09:14:21.763088 progress 85 % (54 MB)
72 09:14:21.805227 progress 90 % (57 MB)
73 09:14:21.846544 progress 95 % (60 MB)
74 09:14:21.887666 progress 100 % (63 MB)
75 09:14:21.888534 63 MB downloaded in 1.02 s (62.62 MB/s)
76 09:14:21.889035 end: 1.2.1 http-download (duration 00:00:01) [common]
78 09:14:21.889849 end: 1.2 download-retry (duration 00:00:01) [common]
79 09:14:21.890124 start: 1.3 download-retry (timeout 00:09:59) [common]
80 09:14:21.890388 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 09:14:21.890869 downloading http://storage.kernelci.org/next/master/next-20241101/arm64/defconfig+kselftest/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
82 09:14:21.891152 saving as /var/lib/lava/dispatcher/tmp/921892/tftp-deploy-5oml_rjo/dtb/meson-g12b-a311d-libretech-cc.dtb
83 09:14:21.891359 total size: 54703 (0 MB)
84 09:14:21.891567 No compression specified
85 09:14:21.932290 progress 59 % (0 MB)
86 09:14:21.933258 progress 100 % (0 MB)
87 09:14:21.933926 0 MB downloaded in 0.04 s (1.23 MB/s)
88 09:14:21.934518 end: 1.3.1 http-download (duration 00:00:00) [common]
90 09:14:21.935483 end: 1.3 download-retry (duration 00:00:00) [common]
91 09:14:21.935845 start: 1.4 download-retry (timeout 00:09:59) [common]
92 09:14:21.936221 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 09:14:21.936799 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm/20240313.0/arm64/full.rootfs.tar.xz
94 09:14:21.937104 saving as /var/lib/lava/dispatcher/tmp/921892/tftp-deploy-5oml_rjo/nfsrootfs/full.rootfs.tar
95 09:14:21.937360 total size: 107552908 (102 MB)
96 09:14:21.937627 Using unxz to decompress xz
97 09:14:21.978722 progress 0 % (0 MB)
98 09:14:22.615599 progress 5 % (5 MB)
99 09:14:23.343949 progress 10 % (10 MB)
100 09:14:24.060580 progress 15 % (15 MB)
101 09:14:24.820503 progress 20 % (20 MB)
102 09:14:25.391042 progress 25 % (25 MB)
103 09:14:26.010394 progress 30 % (30 MB)
104 09:14:26.742645 progress 35 % (35 MB)
105 09:14:27.105099 progress 40 % (41 MB)
106 09:14:27.532795 progress 45 % (46 MB)
107 09:14:28.226029 progress 50 % (51 MB)
108 09:14:28.905735 progress 55 % (56 MB)
109 09:14:29.659718 progress 60 % (61 MB)
110 09:14:30.407735 progress 65 % (66 MB)
111 09:14:31.142116 progress 70 % (71 MB)
112 09:14:31.979082 progress 75 % (76 MB)
113 09:14:32.652732 progress 80 % (82 MB)
114 09:14:33.360097 progress 85 % (87 MB)
115 09:14:34.118749 progress 90 % (92 MB)
116 09:14:34.873748 progress 95 % (97 MB)
117 09:14:35.609538 progress 100 % (102 MB)
118 09:14:35.621278 102 MB downloaded in 13.68 s (7.50 MB/s)
119 09:14:35.621983 end: 1.4.1 http-download (duration 00:00:14) [common]
121 09:14:35.623779 end: 1.4 download-retry (duration 00:00:14) [common]
122 09:14:35.624413 start: 1.5 download-retry (timeout 00:09:45) [common]
123 09:14:35.624994 start: 1.5.1 http-download (timeout 00:09:45) [common]
124 09:14:35.626143 downloading http://storage.kernelci.org/next/master/next-20241101/arm64/defconfig+kselftest/gcc-12/modules.tar.xz
125 09:14:35.626665 saving as /var/lib/lava/dispatcher/tmp/921892/tftp-deploy-5oml_rjo/modules/modules.tar
126 09:14:35.627118 total size: 16180864 (15 MB)
127 09:14:35.627580 Using unxz to decompress xz
128 09:14:35.676434 progress 0 % (0 MB)
129 09:14:35.776351 progress 5 % (0 MB)
130 09:14:35.887912 progress 10 % (1 MB)
131 09:14:36.008323 progress 15 % (2 MB)
132 09:14:36.135900 progress 20 % (3 MB)
133 09:14:36.279419 progress 25 % (3 MB)
134 09:14:36.391015 progress 30 % (4 MB)
135 09:14:36.497405 progress 35 % (5 MB)
136 09:14:36.610778 progress 40 % (6 MB)
137 09:14:36.717955 progress 45 % (6 MB)
138 09:14:36.831324 progress 50 % (7 MB)
139 09:14:36.942740 progress 55 % (8 MB)
140 09:14:37.062210 progress 60 % (9 MB)
141 09:14:37.176604 progress 65 % (10 MB)
142 09:14:37.290693 progress 70 % (10 MB)
143 09:14:37.408512 progress 75 % (11 MB)
144 09:14:37.525495 progress 80 % (12 MB)
145 09:14:37.634259 progress 85 % (13 MB)
146 09:14:37.749556 progress 90 % (13 MB)
147 09:14:37.854085 progress 95 % (14 MB)
148 09:14:37.966999 progress 100 % (15 MB)
149 09:14:37.980222 15 MB downloaded in 2.35 s (6.56 MB/s)
150 09:14:37.980823 end: 1.5.1 http-download (duration 00:00:02) [common]
152 09:14:37.981648 end: 1.5 download-retry (duration 00:00:02) [common]
153 09:14:37.981916 start: 1.6 prepare-tftp-overlay (timeout 00:09:43) [common]
154 09:14:37.982183 start: 1.6.1 extract-nfsrootfs (timeout 00:09:43) [common]
155 09:14:47.461998 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/921892/extract-nfsrootfs-9egcm7h5
156 09:14:47.462602 end: 1.6.1 extract-nfsrootfs (duration 00:00:09) [common]
157 09:14:47.462889 start: 1.6.2 lava-overlay (timeout 00:09:33) [common]
158 09:14:47.463529 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/921892/lava-overlay-5_7l4jjm
159 09:14:47.464012 makedir: /var/lib/lava/dispatcher/tmp/921892/lava-overlay-5_7l4jjm/lava-921892/bin
160 09:14:47.464357 makedir: /var/lib/lava/dispatcher/tmp/921892/lava-overlay-5_7l4jjm/lava-921892/tests
161 09:14:47.464669 makedir: /var/lib/lava/dispatcher/tmp/921892/lava-overlay-5_7l4jjm/lava-921892/results
162 09:14:47.465005 Creating /var/lib/lava/dispatcher/tmp/921892/lava-overlay-5_7l4jjm/lava-921892/bin/lava-add-keys
163 09:14:47.465526 Creating /var/lib/lava/dispatcher/tmp/921892/lava-overlay-5_7l4jjm/lava-921892/bin/lava-add-sources
164 09:14:47.466034 Creating /var/lib/lava/dispatcher/tmp/921892/lava-overlay-5_7l4jjm/lava-921892/bin/lava-background-process-start
165 09:14:47.466539 Creating /var/lib/lava/dispatcher/tmp/921892/lava-overlay-5_7l4jjm/lava-921892/bin/lava-background-process-stop
166 09:14:47.467059 Creating /var/lib/lava/dispatcher/tmp/921892/lava-overlay-5_7l4jjm/lava-921892/bin/lava-common-functions
167 09:14:47.467535 Creating /var/lib/lava/dispatcher/tmp/921892/lava-overlay-5_7l4jjm/lava-921892/bin/lava-echo-ipv4
168 09:14:47.468036 Creating /var/lib/lava/dispatcher/tmp/921892/lava-overlay-5_7l4jjm/lava-921892/bin/lava-install-packages
169 09:14:47.468529 Creating /var/lib/lava/dispatcher/tmp/921892/lava-overlay-5_7l4jjm/lava-921892/bin/lava-installed-packages
170 09:14:47.468999 Creating /var/lib/lava/dispatcher/tmp/921892/lava-overlay-5_7l4jjm/lava-921892/bin/lava-os-build
171 09:14:47.469462 Creating /var/lib/lava/dispatcher/tmp/921892/lava-overlay-5_7l4jjm/lava-921892/bin/lava-probe-channel
172 09:14:47.469926 Creating /var/lib/lava/dispatcher/tmp/921892/lava-overlay-5_7l4jjm/lava-921892/bin/lava-probe-ip
173 09:14:47.470388 Creating /var/lib/lava/dispatcher/tmp/921892/lava-overlay-5_7l4jjm/lava-921892/bin/lava-target-ip
174 09:14:47.470872 Creating /var/lib/lava/dispatcher/tmp/921892/lava-overlay-5_7l4jjm/lava-921892/bin/lava-target-mac
175 09:14:47.471358 Creating /var/lib/lava/dispatcher/tmp/921892/lava-overlay-5_7l4jjm/lava-921892/bin/lava-target-storage
176 09:14:47.471852 Creating /var/lib/lava/dispatcher/tmp/921892/lava-overlay-5_7l4jjm/lava-921892/bin/lava-test-case
177 09:14:47.472352 Creating /var/lib/lava/dispatcher/tmp/921892/lava-overlay-5_7l4jjm/lava-921892/bin/lava-test-event
178 09:14:47.472816 Creating /var/lib/lava/dispatcher/tmp/921892/lava-overlay-5_7l4jjm/lava-921892/bin/lava-test-feedback
179 09:14:47.473280 Creating /var/lib/lava/dispatcher/tmp/921892/lava-overlay-5_7l4jjm/lava-921892/bin/lava-test-raise
180 09:14:47.473739 Creating /var/lib/lava/dispatcher/tmp/921892/lava-overlay-5_7l4jjm/lava-921892/bin/lava-test-reference
181 09:14:47.474205 Creating /var/lib/lava/dispatcher/tmp/921892/lava-overlay-5_7l4jjm/lava-921892/bin/lava-test-runner
182 09:14:47.474673 Creating /var/lib/lava/dispatcher/tmp/921892/lava-overlay-5_7l4jjm/lava-921892/bin/lava-test-set
183 09:14:47.475157 Creating /var/lib/lava/dispatcher/tmp/921892/lava-overlay-5_7l4jjm/lava-921892/bin/lava-test-shell
184 09:14:47.475645 Updating /var/lib/lava/dispatcher/tmp/921892/lava-overlay-5_7l4jjm/lava-921892/bin/lava-install-packages (oe)
185 09:14:47.476194 Updating /var/lib/lava/dispatcher/tmp/921892/lava-overlay-5_7l4jjm/lava-921892/bin/lava-installed-packages (oe)
186 09:14:47.476637 Creating /var/lib/lava/dispatcher/tmp/921892/lava-overlay-5_7l4jjm/lava-921892/environment
187 09:14:47.476993 LAVA metadata
188 09:14:47.477247 - LAVA_JOB_ID=921892
189 09:14:47.477460 - LAVA_DISPATCHER_IP=192.168.6.2
190 09:14:47.477809 start: 1.6.2.1 ssh-authorize (timeout 00:09:33) [common]
191 09:14:47.478728 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
192 09:14:47.479035 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:33) [common]
193 09:14:47.479246 skipped lava-vland-overlay
194 09:14:47.479488 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
195 09:14:47.479741 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:33) [common]
196 09:14:47.479959 skipped lava-multinode-overlay
197 09:14:47.480229 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
198 09:14:47.480481 start: 1.6.2.4 test-definition (timeout 00:09:33) [common]
199 09:14:47.480726 Loading test definitions
200 09:14:47.481004 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:33) [common]
201 09:14:47.481222 Using /lava-921892 at stage 0
202 09:14:47.482373 uuid=921892_1.6.2.4.1 testdef=None
203 09:14:47.482671 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
204 09:14:47.482932 start: 1.6.2.4.2 test-overlay (timeout 00:09:33) [common]
205 09:14:47.484839 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
207 09:14:47.485629 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:33) [common]
208 09:14:47.487850 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
210 09:14:47.488707 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:33) [common]
211 09:14:47.490831 runner path: /var/lib/lava/dispatcher/tmp/921892/lava-overlay-5_7l4jjm/lava-921892/0/tests/0_dmesg test_uuid 921892_1.6.2.4.1
212 09:14:47.491364 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
214 09:14:47.492146 Creating lava-test-runner.conf files
215 09:14:47.492350 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/921892/lava-overlay-5_7l4jjm/lava-921892/0 for stage 0
216 09:14:47.492678 - 0_dmesg
217 09:14:47.493018 end: 1.6.2.4 test-definition (duration 00:00:00) [common]
218 09:14:47.493289 start: 1.6.2.5 compress-overlay (timeout 00:09:33) [common]
219 09:14:47.514636 end: 1.6.2.5 compress-overlay (duration 00:00:00) [common]
220 09:14:47.515007 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:09:33) [common]
221 09:14:47.515268 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
222 09:14:47.515535 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
223 09:14:47.515796 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:33) [common]
224 09:14:48.127505 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:01) [common]
225 09:14:48.127970 start: 1.6.4 extract-modules (timeout 00:09:33) [common]
226 09:14:48.128270 extracting modules file /var/lib/lava/dispatcher/tmp/921892/tftp-deploy-5oml_rjo/modules/modules.tar to /var/lib/lava/dispatcher/tmp/921892/extract-nfsrootfs-9egcm7h5
227 09:14:49.787223 extracting modules file /var/lib/lava/dispatcher/tmp/921892/tftp-deploy-5oml_rjo/modules/modules.tar to /var/lib/lava/dispatcher/tmp/921892/extract-overlay-ramdisk-freg4mhr/ramdisk
228 09:14:51.381959 end: 1.6.4 extract-modules (duration 00:00:03) [common]
229 09:14:51.382453 start: 1.6.5 apply-overlay-tftp (timeout 00:09:29) [common]
230 09:14:51.382751 [common] Applying overlay to NFS
231 09:14:51.382979 [common] Applying overlay /var/lib/lava/dispatcher/tmp/921892/compress-overlay-gqg_zhmk/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/921892/extract-nfsrootfs-9egcm7h5
232 09:14:51.412451 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
233 09:14:51.412858 start: 1.6.6 prepare-kernel (timeout 00:09:29) [common]
234 09:14:51.413152 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:09:29) [common]
235 09:14:51.413396 Converting downloaded kernel to a uImage
236 09:14:51.413717 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/921892/tftp-deploy-5oml_rjo/kernel/Image /var/lib/lava/dispatcher/tmp/921892/tftp-deploy-5oml_rjo/kernel/uImage
237 09:14:52.103459 output: Image Name:
238 09:14:52.103874 output: Created: Fri Nov 1 09:14:51 2024
239 09:14:52.104133 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
240 09:14:52.104341 output: Data Size: 66843136 Bytes = 65276.50 KiB = 63.75 MiB
241 09:14:52.104543 output: Load Address: 01080000
242 09:14:52.104744 output: Entry Point: 01080000
243 09:14:52.104942 output:
244 09:14:52.105272 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:01) [common]
245 09:14:52.105534 end: 1.6.6 prepare-kernel (duration 00:00:01) [common]
246 09:14:52.105800 start: 1.6.7 configure-preseed-file (timeout 00:09:29) [common]
247 09:14:52.106052 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
248 09:14:52.106306 start: 1.6.8 compress-ramdisk (timeout 00:09:29) [common]
249 09:14:52.106562 Building ramdisk /var/lib/lava/dispatcher/tmp/921892/extract-overlay-ramdisk-freg4mhr/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/921892/extract-overlay-ramdisk-freg4mhr/ramdisk
250 09:14:55.177352 >> 242294 blocks
251 09:15:06.129763 Adding RAMdisk u-boot header.
252 09:15:06.130474 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/921892/extract-overlay-ramdisk-freg4mhr/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/921892/extract-overlay-ramdisk-freg4mhr/ramdisk.cpio.gz.uboot
253 09:15:06.451882 output: Image Name:
254 09:15:06.452566 output: Created: Fri Nov 1 09:15:06 2024
255 09:15:06.453046 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
256 09:15:06.453497 output: Data Size: 31173849 Bytes = 30443.21 KiB = 29.73 MiB
257 09:15:06.453937 output: Load Address: 00000000
258 09:15:06.454372 output: Entry Point: 00000000
259 09:15:06.454804 output:
260 09:15:06.455945 rename /var/lib/lava/dispatcher/tmp/921892/extract-overlay-ramdisk-freg4mhr/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/921892/tftp-deploy-5oml_rjo/ramdisk/ramdisk.cpio.gz.uboot
261 09:15:06.456751 end: 1.6.8 compress-ramdisk (duration 00:00:14) [common]
262 09:15:06.457344 end: 1.6 prepare-tftp-overlay (duration 00:00:28) [common]
263 09:15:06.457926 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:14) [common]
264 09:15:06.458427 No LXC device requested
265 09:15:06.458974 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
266 09:15:06.459530 start: 1.8 deploy-device-env (timeout 00:09:14) [common]
267 09:15:06.460104 end: 1.8 deploy-device-env (duration 00:00:00) [common]
268 09:15:06.460561 Checking files for TFTP limit of 4294967296 bytes.
269 09:15:06.463454 end: 1 tftp-deploy (duration 00:00:46) [common]
270 09:15:06.464105 start: 2 uboot-action (timeout 00:05:00) [common]
271 09:15:06.464686 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
272 09:15:06.465228 end: 2.1 uboot-from-media (duration 00:00:00) [common]
273 09:15:06.465774 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
274 09:15:06.466344 Using kernel file from prepare-kernel: 921892/tftp-deploy-5oml_rjo/kernel/uImage
275 09:15:06.467032 substitutions:
276 09:15:06.467475 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
277 09:15:06.467917 - {DTB_ADDR}: 0x01070000
278 09:15:06.468385 - {DTB}: 921892/tftp-deploy-5oml_rjo/dtb/meson-g12b-a311d-libretech-cc.dtb
279 09:15:06.468821 - {INITRD}: 921892/tftp-deploy-5oml_rjo/ramdisk/ramdisk.cpio.gz.uboot
280 09:15:06.469255 - {KERNEL_ADDR}: 0x01080000
281 09:15:06.469687 - {KERNEL}: 921892/tftp-deploy-5oml_rjo/kernel/uImage
282 09:15:06.470113 - {LAVA_MAC}: None
283 09:15:06.470584 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/921892/extract-nfsrootfs-9egcm7h5
284 09:15:06.471016 - {NFS_SERVER_IP}: 192.168.6.2
285 09:15:06.471442 - {PRESEED_CONFIG}: None
286 09:15:06.471867 - {PRESEED_LOCAL}: None
287 09:15:06.472320 - {RAMDISK_ADDR}: 0x08000000
288 09:15:06.472745 - {RAMDISK}: 921892/tftp-deploy-5oml_rjo/ramdisk/ramdisk.cpio.gz.uboot
289 09:15:06.473173 - {ROOT_PART}: None
290 09:15:06.473597 - {ROOT}: None
291 09:15:06.474022 - {SERVER_IP}: 192.168.6.2
292 09:15:06.474443 - {TEE_ADDR}: 0x83000000
293 09:15:06.474862 - {TEE}: None
294 09:15:06.475284 Parsed boot commands:
295 09:15:06.475699 - setenv autoload no
296 09:15:06.476147 - setenv initrd_high 0xffffffff
297 09:15:06.476574 - setenv fdt_high 0xffffffff
298 09:15:06.476996 - dhcp
299 09:15:06.477415 - setenv serverip 192.168.6.2
300 09:15:06.477834 - tftpboot 0x01080000 921892/tftp-deploy-5oml_rjo/kernel/uImage
301 09:15:06.478257 - tftpboot 0x08000000 921892/tftp-deploy-5oml_rjo/ramdisk/ramdisk.cpio.gz.uboot
302 09:15:06.478680 - tftpboot 0x01070000 921892/tftp-deploy-5oml_rjo/dtb/meson-g12b-a311d-libretech-cc.dtb
303 09:15:06.479104 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/921892/extract-nfsrootfs-9egcm7h5,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
304 09:15:06.479541 - bootm 0x01080000 0x08000000 0x01070000
305 09:15:06.480098 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
307 09:15:06.481713 start: 2.3 connect-device (timeout 00:05:00) [common]
308 09:15:06.482166 [common] connect-device Connecting to device using 'telnet conserv1 3007'
309 09:15:06.496848 Setting prompt string to ['lava-test: # ']
310 09:15:06.498446 end: 2.3 connect-device (duration 00:00:00) [common]
311 09:15:06.499091 start: 2.4 uboot-commands (timeout 00:05:00) [common]
312 09:15:06.499786 start: 2.4.1 reset-device (timeout 00:05:00) [common]
313 09:15:06.500539 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
314 09:15:06.501787 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
315 09:15:06.539197 >> OK - accepted request
316 09:15:06.541303 Returned 0 in 0 seconds
317 09:15:06.642474 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
319 09:15:06.644319 end: 2.4.1 reset-device (duration 00:00:00) [common]
320 09:15:06.644962 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
321 09:15:06.645523 Setting prompt string to ['Hit any key to stop autoboot']
322 09:15:06.646031 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
323 09:15:06.647737 Trying 192.168.56.21...
324 09:15:06.648298 Connected to conserv1.
325 09:15:06.648757 Escape character is '^]'.
326 09:15:06.649221
327 09:15:06.649686 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
328 09:15:06.650151
329 09:15:18.307429 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
330 09:15:18.308106 bl2_stage_init 0x01
331 09:15:18.308566 bl2_stage_init 0x81
332 09:15:18.313107 hw id: 0x0000 - pwm id 0x01
333 09:15:18.313593 bl2_stage_init 0xc1
334 09:15:18.314033 bl2_stage_init 0x02
335 09:15:18.314465
336 09:15:18.318576 L0:00000000
337 09:15:18.319042 L1:20000703
338 09:15:18.319488 L2:00008067
339 09:15:18.319918 L3:14000000
340 09:15:18.324137 B2:00402000
341 09:15:18.324604 B1:e0f83180
342 09:15:18.325050
343 09:15:18.325486 TE: 58158
344 09:15:18.325921
345 09:15:18.329753 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
346 09:15:18.330218
347 09:15:18.330657 Board ID = 1
348 09:15:18.335279 Set A53 clk to 24M
349 09:15:18.335744 Set A73 clk to 24M
350 09:15:18.336212 Set clk81 to 24M
351 09:15:18.341041 A53 clk: 1200 MHz
352 09:15:18.341498 A73 clk: 1200 MHz
353 09:15:18.341925 CLK81: 166.6M
354 09:15:18.342347 smccc: 00012ab4
355 09:15:18.346550 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
356 09:15:18.352059 board id: 1
357 09:15:18.357982 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
358 09:15:18.368599 fw parse done
359 09:15:18.374564 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
360 09:15:18.417215 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
361 09:15:18.428096 PIEI prepare done
362 09:15:18.428547 fastboot data load
363 09:15:18.428983 fastboot data verify
364 09:15:18.433839 verify result: 266
365 09:15:18.439369 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
366 09:15:18.439828 LPDDR4 probe
367 09:15:18.440321 ddr clk to 1584MHz
368 09:15:18.447407 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
369 09:15:18.484606
370 09:15:18.485086 dmc_version 0001
371 09:15:18.491262 Check phy result
372 09:15:18.497194 INFO : End of CA training
373 09:15:18.497662 INFO : End of initialization
374 09:15:18.502732 INFO : Training has run successfully!
375 09:15:18.503202 Check phy result
376 09:15:18.508401 INFO : End of initialization
377 09:15:18.508870 INFO : End of read enable training
378 09:15:18.513970 INFO : End of fine write leveling
379 09:15:18.519543 INFO : End of Write leveling coarse delay
380 09:15:18.520031 INFO : Training has run successfully!
381 09:15:18.520481 Check phy result
382 09:15:18.525156 INFO : End of initialization
383 09:15:18.525636 INFO : End of read dq deskew training
384 09:15:18.530770 INFO : End of MPR read delay center optimization
385 09:15:18.536341 INFO : End of write delay center optimization
386 09:15:18.541974 INFO : End of read delay center optimization
387 09:15:18.542434 INFO : End of max read latency training
388 09:15:18.547570 INFO : Training has run successfully!
389 09:15:18.548070 1D training succeed
390 09:15:18.556733 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
391 09:15:18.604296 Check phy result
392 09:15:18.604762 INFO : End of initialization
393 09:15:18.626113 INFO : End of 2D read delay Voltage center optimization
394 09:15:18.646304 INFO : End of 2D read delay Voltage center optimization
395 09:15:18.698377 INFO : End of 2D write delay Voltage center optimization
396 09:15:18.747629 INFO : End of 2D write delay Voltage center optimization
397 09:15:18.753315 INFO : Training has run successfully!
398 09:15:18.753794
399 09:15:18.754245 channel==0
400 09:15:18.758952 RxClkDly_Margin_A0==78 ps 8
401 09:15:18.759417 TxDqDly_Margin_A0==98 ps 10
402 09:15:18.762201 RxClkDly_Margin_A1==88 ps 9
403 09:15:18.762669 TxDqDly_Margin_A1==98 ps 10
404 09:15:18.767762 TrainedVREFDQ_A0==74
405 09:15:18.768258 TrainedVREFDQ_A1==74
406 09:15:18.773347 VrefDac_Margin_A0==25
407 09:15:18.773811 DeviceVref_Margin_A0==40
408 09:15:18.774258 VrefDac_Margin_A1==25
409 09:15:18.778929 DeviceVref_Margin_A1==40
410 09:15:18.779392
411 09:15:18.779842
412 09:15:18.780318 channel==1
413 09:15:18.780759 RxClkDly_Margin_A0==98 ps 10
414 09:15:18.782421 TxDqDly_Margin_A0==98 ps 10
415 09:15:18.787955 RxClkDly_Margin_A1==98 ps 10
416 09:15:18.788446 TxDqDly_Margin_A1==98 ps 10
417 09:15:18.793533 TrainedVREFDQ_A0==77
418 09:15:18.794004 TrainedVREFDQ_A1==78
419 09:15:18.794450 VrefDac_Margin_A0==23
420 09:15:18.799193 DeviceVref_Margin_A0==37
421 09:15:18.799762 VrefDac_Margin_A1==23
422 09:15:18.800301 DeviceVref_Margin_A1==36
423 09:15:18.800773
424 09:15:18.808216 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
425 09:15:18.808742
426 09:15:18.836196 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000018 00000019 00000018 00000019 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
427 09:15:18.836781 2D training succeed
428 09:15:18.847297 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
429 09:15:18.847833 auto size-- 65535DDR cs0 size: 2048MB
430 09:15:18.853064 DDR cs1 size: 2048MB
431 09:15:18.853575 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
432 09:15:18.854033 cs0 DataBus test pass
433 09:15:18.858465 cs1 DataBus test pass
434 09:15:18.858942 cs0 AddrBus test pass
435 09:15:18.864067 cs1 AddrBus test pass
436 09:15:18.864558
437 09:15:18.865011 100bdlr_step_size ps== 420
438 09:15:18.865462 result report
439 09:15:18.869631 boot times 0Enable ddr reg access
440 09:15:18.876596 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
441 09:15:18.889805 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
442 09:15:19.463524 0.0;M3 CHK:0;cm4_sp_mode 0
443 09:15:19.464200 MVN_1=0x00000000
444 09:15:19.469023 MVN_2=0x00000000
445 09:15:19.474719 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
446 09:15:19.475197 OPS=0x10
447 09:15:19.475654 ring efuse init
448 09:15:19.476134 chipver efuse init
449 09:15:19.480317 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
450 09:15:19.485994 [0.018961 Inits done]
451 09:15:19.486472 secure task start!
452 09:15:19.486920 high task start!
453 09:15:19.490498 low task start!
454 09:15:19.490964 run into bl31
455 09:15:19.497177 NOTICE: BL31: v1.3(release):4fc40b1
456 09:15:19.505059 NOTICE: BL31: Built : 15:58:17, May 22 2019
457 09:15:19.505535 NOTICE: BL31: G12A normal boot!
458 09:15:19.530295 NOTICE: BL31: BL33 decompress pass
459 09:15:19.536231 ERROR: Error initializing runtime service opteed_fast
460 09:15:20.769019
461 09:15:20.769686
462 09:15:20.777265 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
463 09:15:20.777750
464 09:15:20.778210 Model: Libre Computer AML-A311D-CC Alta
465 09:15:20.985715 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
466 09:15:21.009058 DRAM: 2 GiB (effective 3.8 GiB)
467 09:15:21.152176 Core: 408 devices, 31 uclasses, devicetree: separate
468 09:15:21.157939 WDT: Not starting watchdog@f0d0
469 09:15:21.190255 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
470 09:15:21.202673 Loading Environment from FAT... Card did not respond to voltage select! : -110
471 09:15:21.207636 ** Bad device specification mmc 0 **
472 09:15:21.217983 Card did not respond to voltage select! : -110
473 09:15:21.225629 ** Bad device specification mmc 0 **
474 09:15:21.226100 Couldn't find partition mmc 0
475 09:15:21.233984 Card did not respond to voltage select! : -110
476 09:15:21.239563 ** Bad device specification mmc 0 **
477 09:15:21.240058 Couldn't find partition mmc 0
478 09:15:21.244663 Error: could not access storage.
479 09:15:22.507655 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
480 09:15:22.508369 bl2_stage_init 0x01
481 09:15:22.508854 bl2_stage_init 0x81
482 09:15:22.513236 hw id: 0x0000 - pwm id 0x01
483 09:15:22.513728 bl2_stage_init 0xc1
484 09:15:22.514185 bl2_stage_init 0x02
485 09:15:22.514637
486 09:15:22.518802 L0:00000000
487 09:15:22.519279 L1:20000703
488 09:15:22.519726 L2:00008067
489 09:15:22.520209 L3:14000000
490 09:15:22.524465 B2:00402000
491 09:15:22.524941 B1:e0f83180
492 09:15:22.525387
493 09:15:22.525833 TE: 58167
494 09:15:22.526274
495 09:15:22.529993 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
496 09:15:22.530472
497 09:15:22.530923 Board ID = 1
498 09:15:22.535580 Set A53 clk to 24M
499 09:15:22.536078 Set A73 clk to 24M
500 09:15:22.536527 Set clk81 to 24M
501 09:15:22.541192 A53 clk: 1200 MHz
502 09:15:22.541656 A73 clk: 1200 MHz
503 09:15:22.542100 CLK81: 166.6M
504 09:15:22.542544 smccc: 00012abe
505 09:15:22.546818 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
506 09:15:22.552430 board id: 1
507 09:15:22.558291 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
508 09:15:22.568932 fw parse done
509 09:15:22.574892 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
510 09:15:22.617542 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
511 09:15:22.628475 PIEI prepare done
512 09:15:22.628944 fastboot data load
513 09:15:22.629398 fastboot data verify
514 09:15:22.634025 verify result: 266
515 09:15:22.639621 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
516 09:15:22.640126 LPDDR4 probe
517 09:15:22.640576 ddr clk to 1584MHz
518 09:15:22.647642 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
519 09:15:22.684856
520 09:15:22.685346 dmc_version 0001
521 09:15:22.691566 Check phy result
522 09:15:22.697487 INFO : End of CA training
523 09:15:22.697955 INFO : End of initialization
524 09:15:22.703014 INFO : Training has run successfully!
525 09:15:22.703479 Check phy result
526 09:15:22.708628 INFO : End of initialization
527 09:15:22.709098 INFO : End of read enable training
528 09:15:22.714227 INFO : End of fine write leveling
529 09:15:22.719815 INFO : End of Write leveling coarse delay
530 09:15:22.720311 INFO : Training has run successfully!
531 09:15:22.720760 Check phy result
532 09:15:22.725483 INFO : End of initialization
533 09:15:22.725950 INFO : End of read dq deskew training
534 09:15:22.731003 INFO : End of MPR read delay center optimization
535 09:15:22.736609 INFO : End of write delay center optimization
536 09:15:22.742206 INFO : End of read delay center optimization
537 09:15:22.742672 INFO : End of max read latency training
538 09:15:22.747867 INFO : Training has run successfully!
539 09:15:22.748380 1D training succeed
540 09:15:22.756996 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
541 09:15:22.804613 Check phy result
542 09:15:22.805094 INFO : End of initialization
543 09:15:22.826993 INFO : End of 2D read delay Voltage center optimization
544 09:15:22.847224 INFO : End of 2D read delay Voltage center optimization
545 09:15:22.899024 INFO : End of 2D write delay Voltage center optimization
546 09:15:22.948332 INFO : End of 2D write delay Voltage center optimization
547 09:15:22.953847 INFO : Training has run successfully!
548 09:15:22.954318
549 09:15:22.954784 channel==0
550 09:15:22.959532 RxClkDly_Margin_A0==88 ps 9
551 09:15:22.960039 TxDqDly_Margin_A0==98 ps 10
552 09:15:22.965041 RxClkDly_Margin_A1==88 ps 9
553 09:15:22.965514 TxDqDly_Margin_A1==98 ps 10
554 09:15:22.965966 TrainedVREFDQ_A0==74
555 09:15:22.970647 TrainedVREFDQ_A1==74
556 09:15:22.971117 VrefDac_Margin_A0==24
557 09:15:22.971559 DeviceVref_Margin_A0==40
558 09:15:22.976247 VrefDac_Margin_A1==24
559 09:15:22.976712 DeviceVref_Margin_A1==40
560 09:15:22.977153
561 09:15:22.977590
562 09:15:22.981848 channel==1
563 09:15:22.982322 RxClkDly_Margin_A0==98 ps 10
564 09:15:22.982762 TxDqDly_Margin_A0==88 ps 9
565 09:15:22.987513 RxClkDly_Margin_A1==88 ps 9
566 09:15:22.988022 TxDqDly_Margin_A1==88 ps 9
567 09:15:22.993039 TrainedVREFDQ_A0==76
568 09:15:22.993516 TrainedVREFDQ_A1==77
569 09:15:22.993965 VrefDac_Margin_A0==23
570 09:15:22.998674 DeviceVref_Margin_A0==38
571 09:15:22.999139 VrefDac_Margin_A1==24
572 09:15:23.004248 DeviceVref_Margin_A1==37
573 09:15:23.004712
574 09:15:23.005161 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
575 09:15:23.005601
576 09:15:23.037828 soc_vref_reg_value 0x 00000019 0000001a 00000018 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000018 00000019 00000018 00000019 00000018 0000001a 0000001a 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
577 09:15:23.038336 2D training succeed
578 09:15:23.043539 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
579 09:15:23.049074 auto size-- 65535DDR cs0 size: 2048MB
580 09:15:23.049549 DDR cs1 size: 2048MB
581 09:15:23.054644 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
582 09:15:23.055109 cs0 DataBus test pass
583 09:15:23.060246 cs1 DataBus test pass
584 09:15:23.060714 cs0 AddrBus test pass
585 09:15:23.061156 cs1 AddrBus test pass
586 09:15:23.061595
587 09:15:23.065839 100bdlr_step_size ps== 420
588 09:15:23.066324 result report
589 09:15:23.071547 boot times 0Enable ddr reg access
590 09:15:23.076692 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
591 09:15:23.090148 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
592 09:15:23.662358 0.0;M3 CHK:0;cm4_sp_mode 0
593 09:15:23.662986 MVN_1=0x00000000
594 09:15:23.667731 MVN_2=0x00000000
595 09:15:23.673519 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
596 09:15:23.674032 OPS=0x10
597 09:15:23.674508 ring efuse init
598 09:15:23.674992 chipver efuse init
599 09:15:23.679098 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
600 09:15:23.684656 [0.018960 Inits done]
601 09:15:23.685139 secure task start!
602 09:15:23.685585 high task start!
603 09:15:23.689197 low task start!
604 09:15:23.689663 run into bl31
605 09:15:23.695853 NOTICE: BL31: v1.3(release):4fc40b1
606 09:15:23.703675 NOTICE: BL31: Built : 15:58:17, May 22 2019
607 09:15:23.704180 NOTICE: BL31: G12A normal boot!
608 09:15:23.729053 NOTICE: BL31: BL33 decompress pass
609 09:15:23.734714 ERROR: Error initializing runtime service opteed_fast
610 09:15:24.967840
611 09:15:24.968579
612 09:15:24.976176 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
613 09:15:24.976689
614 09:15:24.977155 Model: Libre Computer AML-A311D-CC Alta
615 09:15:25.184776 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
616 09:15:25.208048 DRAM: 2 GiB (effective 3.8 GiB)
617 09:15:25.351158 Core: 408 devices, 31 uclasses, devicetree: separate
618 09:15:25.356985 WDT: Not starting watchdog@f0d0
619 09:15:25.389044 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
620 09:15:25.401636 Loading Environment from FAT... Card did not respond to voltage select! : -110
621 09:15:25.406585 ** Bad device specification mmc 0 **
622 09:15:25.416894 Card did not respond to voltage select! : -110
623 09:15:25.424496 ** Bad device specification mmc 0 **
624 09:15:25.424975 Couldn't find partition mmc 0
625 09:15:25.432968 Card did not respond to voltage select! : -110
626 09:15:25.438390 ** Bad device specification mmc 0 **
627 09:15:25.438864 Couldn't find partition mmc 0
628 09:15:25.443456 Error: could not access storage.
629 09:15:25.787023 Net: eth0: ethernet@ff3f0000
630 09:15:25.787567 starting USB...
631 09:15:26.038851 Bus usb@ff500000: Register 3000140 NbrPorts 3
632 09:15:26.039370 Starting the controller
633 09:15:26.045710 USB XHCI 1.10
634 09:15:27.757983 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
635 09:15:27.758632 bl2_stage_init 0x01
636 09:15:27.759093 bl2_stage_init 0x81
637 09:15:27.763524 hw id: 0x0000 - pwm id 0x01
638 09:15:27.764032 bl2_stage_init 0xc1
639 09:15:27.764495 bl2_stage_init 0x02
640 09:15:27.764944
641 09:15:27.769147 L0:00000000
642 09:15:27.769622 L1:20000703
643 09:15:27.770067 L2:00008067
644 09:15:27.770507 L3:14000000
645 09:15:27.772058 B2:00402000
646 09:15:27.772535 B1:e0f83180
647 09:15:27.772976
648 09:15:27.773416 TE: 58167
649 09:15:27.773858
650 09:15:27.783185 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
651 09:15:27.783667
652 09:15:27.784157 Board ID = 1
653 09:15:27.784601 Set A53 clk to 24M
654 09:15:27.785040 Set A73 clk to 24M
655 09:15:27.788787 Set clk81 to 24M
656 09:15:27.789259 A53 clk: 1200 MHz
657 09:15:27.789716 A73 clk: 1200 MHz
658 09:15:27.794312 CLK81: 166.6M
659 09:15:27.794785 smccc: 00012abe
660 09:15:27.799929 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
661 09:15:27.800431 board id: 1
662 09:15:27.808685 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
663 09:15:27.819455 fw parse done
664 09:15:27.825254 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
665 09:15:27.867747 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
666 09:15:27.878657 PIEI prepare done
667 09:15:27.879135 fastboot data load
668 09:15:27.879593 fastboot data verify
669 09:15:27.884244 verify result: 266
670 09:15:27.889832 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
671 09:15:27.890307 LPDDR4 probe
672 09:15:27.890762 ddr clk to 1584MHz
673 09:15:27.897824 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
674 09:15:27.935054
675 09:15:27.935521 dmc_version 0001
676 09:15:27.941745 Check phy result
677 09:15:27.947621 INFO : End of CA training
678 09:15:27.948126 INFO : End of initialization
679 09:15:27.953293 INFO : Training has run successfully!
680 09:15:27.953766 Check phy result
681 09:15:27.958840 INFO : End of initialization
682 09:15:27.959312 INFO : End of read enable training
683 09:15:27.964441 INFO : End of fine write leveling
684 09:15:27.970088 INFO : End of Write leveling coarse delay
685 09:15:27.970556 INFO : Training has run successfully!
686 09:15:27.971003 Check phy result
687 09:15:27.975667 INFO : End of initialization
688 09:15:27.976172 INFO : End of read dq deskew training
689 09:15:27.981288 INFO : End of MPR read delay center optimization
690 09:15:27.986884 INFO : End of write delay center optimization
691 09:15:27.992484 INFO : End of read delay center optimization
692 09:15:27.992967 INFO : End of max read latency training
693 09:15:27.998020 INFO : Training has run successfully!
694 09:15:27.998491 1D training succeed
695 09:15:28.007246 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
696 09:15:28.054799 Check phy result
697 09:15:28.055276 INFO : End of initialization
698 09:15:28.077396 INFO : End of 2D read delay Voltage center optimization
699 09:15:28.097598 INFO : End of 2D read delay Voltage center optimization
700 09:15:28.149693 INFO : End of 2D write delay Voltage center optimization
701 09:15:28.199109 INFO : End of 2D write delay Voltage center optimization
702 09:15:28.204658 INFO : Training has run successfully!
703 09:15:28.205128
704 09:15:28.205588 channel==0
705 09:15:28.210362 RxClkDly_Margin_A0==88 ps 9
706 09:15:28.210830 TxDqDly_Margin_A0==98 ps 10
707 09:15:28.213568 RxClkDly_Margin_A1==88 ps 9
708 09:15:28.214032 TxDqDly_Margin_A1==88 ps 9
709 09:15:28.219102 TrainedVREFDQ_A0==74
710 09:15:28.219574 TrainedVREFDQ_A1==74
711 09:15:28.220068 VrefDac_Margin_A0==25
712 09:15:28.224650 DeviceVref_Margin_A0==40
713 09:15:28.225118 VrefDac_Margin_A1==25
714 09:15:28.230434 DeviceVref_Margin_A1==40
715 09:15:28.230898
716 09:15:28.231343
717 09:15:28.231783 channel==1
718 09:15:28.232256 RxClkDly_Margin_A0==98 ps 10
719 09:15:28.233771 TxDqDly_Margin_A0==98 ps 10
720 09:15:28.239409 RxClkDly_Margin_A1==88 ps 9
721 09:15:28.239875 TxDqDly_Margin_A1==88 ps 9
722 09:15:28.240358 TrainedVREFDQ_A0==77
723 09:15:28.244915 TrainedVREFDQ_A1==77
724 09:15:28.245391 VrefDac_Margin_A0==23
725 09:15:28.250496 DeviceVref_Margin_A0==37
726 09:15:28.250965 VrefDac_Margin_A1==24
727 09:15:28.251408 DeviceVref_Margin_A1==37
728 09:15:28.251848
729 09:15:28.259417 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
730 09:15:28.259888
731 09:15:28.287454 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000017 00000017 00000018 00000016 00000017 00000015 00000018 00000019 00000017 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
732 09:15:28.287967 2D training succeed
733 09:15:28.298646 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
734 09:15:28.299119 auto size-- 65535DDR cs0 size: 2048MB
735 09:15:28.299563 DDR cs1 size: 2048MB
736 09:15:28.304290 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
737 09:15:28.304757 cs0 DataBus test pass
738 09:15:28.309829 cs1 DataBus test pass
739 09:15:28.310295 cs0 AddrBus test pass
740 09:15:28.315451 cs1 AddrBus test pass
741 09:15:28.315913
742 09:15:28.316398 100bdlr_step_size ps== 420
743 09:15:28.316853 result report
744 09:15:28.321046 boot times 0Enable ddr reg access
745 09:15:28.327462 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
746 09:15:28.340930 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
747 09:15:28.913923 0.0;M3 CHK:0;cm4_sp_mode 0
748 09:15:28.914430 MVN_1=0x00000000
749 09:15:28.919410 MVN_2=0x00000000
750 09:15:28.925181 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
751 09:15:28.925705 OPS=0x10
752 09:15:28.926144 ring efuse init
753 09:15:28.926573 chipver efuse init
754 09:15:28.930722 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
755 09:15:28.936318 [0.018961 Inits done]
756 09:15:28.936781 secure task start!
757 09:15:28.937210 high task start!
758 09:15:28.940865 low task start!
759 09:15:28.941315 run into bl31
760 09:15:28.947532 NOTICE: BL31: v1.3(release):4fc40b1
761 09:15:28.955428 NOTICE: BL31: Built : 15:58:17, May 22 2019
762 09:15:28.955895 NOTICE: BL31: G12A normal boot!
763 09:15:28.980743 NOTICE: BL31: BL33 decompress pass
764 09:15:28.986432 ERROR: Error initializing runtime service opteed_fast
765 09:15:30.219316
766 09:15:30.219901
767 09:15:30.227675 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
768 09:15:30.228195
769 09:15:30.228649 Model: Libre Computer AML-A311D-CC Alta
770 09:15:30.436184 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
771 09:15:30.459516 DRAM: 2 GiB (effective 3.8 GiB)
772 09:15:30.602577 Core: 408 devices, 31 uclasses, devicetree: separate
773 09:15:30.608346 WDT: Not starting watchdog@f0d0
774 09:15:30.640580 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
775 09:15:30.653070 Loading Environment from FAT... Card did not respond to voltage select! : -110
776 09:15:30.658030 ** Bad device specification mmc 0 **
777 09:15:30.668362 Card did not respond to voltage select! : -110
778 09:15:30.676042 ** Bad device specification mmc 0 **
779 09:15:30.676535 Couldn't find partition mmc 0
780 09:15:30.684399 Card did not respond to voltage select! : -110
781 09:15:30.689879 ** Bad device specification mmc 0 **
782 09:15:30.690356 Couldn't find partition mmc 0
783 09:15:30.694941 Error: could not access storage.
784 09:15:31.038443 Net: eth0: ethernet@ff3f0000
785 09:15:31.038935 starting USB...
786 09:15:31.290356 Bus usb@ff500000: Register 3000140 NbrPorts 3
787 09:15:31.290895 Starting the controller
788 09:15:31.297231 USB XHCI 1.10
789 09:15:33.458014 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
790 09:15:33.458581 bl2_stage_init 0x01
791 09:15:33.459040 bl2_stage_init 0x81
792 09:15:33.463506 hw id: 0x0000 - pwm id 0x01
793 09:15:33.464001 bl2_stage_init 0xc1
794 09:15:33.464463 bl2_stage_init 0x02
795 09:15:33.464910
796 09:15:33.469081 L0:00000000
797 09:15:33.469552 L1:20000703
798 09:15:33.469998 L2:00008067
799 09:15:33.470438 L3:14000000
800 09:15:33.472073 B2:00402000
801 09:15:33.472540 B1:e0f83180
802 09:15:33.472984
803 09:15:33.473428 TE: 58124
804 09:15:33.473871
805 09:15:33.483124 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
806 09:15:33.483600
807 09:15:33.484086 Board ID = 1
808 09:15:33.484532 Set A53 clk to 24M
809 09:15:33.484970 Set A73 clk to 24M
810 09:15:33.488849 Set clk81 to 24M
811 09:15:33.489318 A53 clk: 1200 MHz
812 09:15:33.489769 A73 clk: 1200 MHz
813 09:15:33.492374 CLK81: 166.6M
814 09:15:33.492842 smccc: 00012a92
815 09:15:33.497878 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
816 09:15:33.503490 board id: 1
817 09:15:33.508602 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
818 09:15:33.519278 fw parse done
819 09:15:33.525201 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
820 09:15:33.567880 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
821 09:15:33.578701 PIEI prepare done
822 09:15:33.579165 fastboot data load
823 09:15:33.579613 fastboot data verify
824 09:15:33.584244 verify result: 266
825 09:15:33.589965 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
826 09:15:33.590434 LPDDR4 probe
827 09:15:33.590876 ddr clk to 1584MHz
828 09:15:33.597871 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
829 09:15:33.635127
830 09:15:33.635592 dmc_version 0001
831 09:15:33.641783 Check phy result
832 09:15:33.647654 INFO : End of CA training
833 09:15:33.648145 INFO : End of initialization
834 09:15:33.653247 INFO : Training has run successfully!
835 09:15:33.653711 Check phy result
836 09:15:33.658905 INFO : End of initialization
837 09:15:33.659369 INFO : End of read enable training
838 09:15:33.664538 INFO : End of fine write leveling
839 09:15:33.670043 INFO : End of Write leveling coarse delay
840 09:15:33.670515 INFO : Training has run successfully!
841 09:15:33.670959 Check phy result
842 09:15:33.675656 INFO : End of initialization
843 09:15:33.676151 INFO : End of read dq deskew training
844 09:15:33.681316 INFO : End of MPR read delay center optimization
845 09:15:33.686907 INFO : End of write delay center optimization
846 09:15:33.692589 INFO : End of read delay center optimization
847 09:15:33.693055 INFO : End of max read latency training
848 09:15:33.698066 INFO : Training has run successfully!
849 09:15:33.698529 1D training succeed
850 09:15:33.707301 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
851 09:15:33.754835 Check phy result
852 09:15:33.755305 INFO : End of initialization
853 09:15:33.777434 INFO : End of 2D read delay Voltage center optimization
854 09:15:33.797751 INFO : End of 2D read delay Voltage center optimization
855 09:15:33.849752 INFO : End of 2D write delay Voltage center optimization
856 09:15:33.899242 INFO : End of 2D write delay Voltage center optimization
857 09:15:33.904724 INFO : Training has run successfully!
858 09:15:33.905195
859 09:15:33.905646 channel==0
860 09:15:33.910311 RxClkDly_Margin_A0==88 ps 9
861 09:15:33.910777 TxDqDly_Margin_A0==98 ps 10
862 09:15:33.913664 RxClkDly_Margin_A1==88 ps 9
863 09:15:33.914129 TxDqDly_Margin_A1==98 ps 10
864 09:15:33.919265 TrainedVREFDQ_A0==74
865 09:15:33.919789 TrainedVREFDQ_A1==74
866 09:15:33.920294 VrefDac_Margin_A0==25
867 09:15:33.924861 DeviceVref_Margin_A0==40
868 09:15:33.925362 VrefDac_Margin_A1==25
869 09:15:33.930417 DeviceVref_Margin_A1==40
870 09:15:33.930874
871 09:15:33.931305
872 09:15:33.931729 channel==1
873 09:15:33.932192 RxClkDly_Margin_A0==98 ps 10
874 09:15:33.933885 TxDqDly_Margin_A0==88 ps 9
875 09:15:33.939461 RxClkDly_Margin_A1==88 ps 9
876 09:15:33.939919 TxDqDly_Margin_A1==88 ps 9
877 09:15:33.940390 TrainedVREFDQ_A0==77
878 09:15:33.945131 TrainedVREFDQ_A1==77
879 09:15:33.945593 VrefDac_Margin_A0==22
880 09:15:33.950645 DeviceVref_Margin_A0==37
881 09:15:33.951098 VrefDac_Margin_A1==24
882 09:15:33.951527 DeviceVref_Margin_A1==37
883 09:15:33.951977
884 09:15:33.956271 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
885 09:15:33.956735
886 09:15:33.989963 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000016 00000018 00000019 00000017 00000019 00000018 00000019 0000001a 00000018 00000017 00000018 00000017 0000001a 00000018 00000017 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
887 09:15:33.990478 2D training succeed
888 09:15:33.995490 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
889 09:15:34.000921 auto size-- 65535DDR cs0 size: 2048MB
890 09:15:34.001379 DDR cs1 size: 2048MB
891 09:15:34.006509 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
892 09:15:34.006967 cs0 DataBus test pass
893 09:15:34.007396 cs1 DataBus test pass
894 09:15:34.012153 cs0 AddrBus test pass
895 09:15:34.012611 cs1 AddrBus test pass
896 09:15:34.013040
897 09:15:34.017726 100bdlr_step_size ps== 420
898 09:15:34.018193 result report
899 09:15:34.018619 boot times 0Enable ddr reg access
900 09:15:34.027438 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
901 09:15:34.041007 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
902 09:15:34.614640 0.0;M3 CHK:0;cm4_sp_mode 0
903 09:15:34.615177 MVN_1=0x00000000
904 09:15:34.620158 MVN_2=0x00000000
905 09:15:34.625855 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
906 09:15:34.626329 OPS=0x10
907 09:15:34.626777 ring efuse init
908 09:15:34.627219 chipver efuse init
909 09:15:34.631472 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
910 09:15:34.637093 [0.018960 Inits done]
911 09:15:34.637566 secure task start!
912 09:15:34.638012 high task start!
913 09:15:34.641621 low task start!
914 09:15:34.642088 run into bl31
915 09:15:34.648293 NOTICE: BL31: v1.3(release):4fc40b1
916 09:15:34.656174 NOTICE: BL31: Built : 15:58:17, May 22 2019
917 09:15:34.656649 NOTICE: BL31: G12A normal boot!
918 09:15:34.681449 NOTICE: BL31: BL33 decompress pass
919 09:15:34.687143 ERROR: Error initializing runtime service opteed_fast
920 09:15:35.920080
921 09:15:35.920589
922 09:15:35.928404 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
923 09:15:35.928877
924 09:15:35.929329 Model: Libre Computer AML-A311D-CC Alta
925 09:15:36.136835 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
926 09:15:36.160304 DRAM: 2 GiB (effective 3.8 GiB)
927 09:15:36.303278 Core: 408 devices, 31 uclasses, devicetree: separate
928 09:15:36.309075 WDT: Not starting watchdog@f0d0
929 09:15:36.341327 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
930 09:15:36.353804 Loading Environment from FAT... Card did not respond to voltage select! : -110
931 09:15:36.358782 ** Bad device specification mmc 0 **
932 09:15:36.369099 Card did not respond to voltage select! : -110
933 09:15:36.376765 ** Bad device specification mmc 0 **
934 09:15:36.377237 Couldn't find partition mmc 0
935 09:15:36.385087 Card did not respond to voltage select! : -110
936 09:15:36.390619 ** Bad device specification mmc 0 **
937 09:15:36.391097 Couldn't find partition mmc 0
938 09:15:36.395658 Error: could not access storage.
939 09:15:36.738178 Net: eth0: ethernet@ff3f0000
940 09:15:36.738666 starting USB...
941 09:15:36.989952 Bus usb@ff500000: Register 3000140 NbrPorts 3
942 09:15:36.990422 Starting the controller
943 09:15:36.996916 USB XHCI 1.10
944 09:15:38.857592 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
945 09:15:38.858215 bl2_stage_init 0x01
946 09:15:38.858688 bl2_stage_init 0x81
947 09:15:38.863137 hw id: 0x0000 - pwm id 0x01
948 09:15:38.863620 bl2_stage_init 0xc1
949 09:15:38.864136 bl2_stage_init 0x02
950 09:15:38.864592
951 09:15:38.868733 L0:00000000
952 09:15:38.869210 L1:20000703
953 09:15:38.869656 L2:00008067
954 09:15:38.870096 L3:14000000
955 09:15:38.871695 B2:00402000
956 09:15:38.872205 B1:e0f83180
957 09:15:38.872657
958 09:15:38.873101 TE: 58124
959 09:15:38.873548
960 09:15:38.882817 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
961 09:15:38.883299
962 09:15:38.883750 Board ID = 1
963 09:15:38.884234 Set A53 clk to 24M
964 09:15:38.884678 Set A73 clk to 24M
965 09:15:38.888426 Set clk81 to 24M
966 09:15:38.888895 A53 clk: 1200 MHz
967 09:15:38.889339 A73 clk: 1200 MHz
968 09:15:38.894039 CLK81: 166.6M
969 09:15:38.894504 smccc: 00012a92
970 09:15:38.899662 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
971 09:15:38.900165 board id: 1
972 09:15:38.908228 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
973 09:15:38.918871 fw parse done
974 09:15:38.924865 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
975 09:15:38.967492 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
976 09:15:38.978387 PIEI prepare done
977 09:15:38.978878 fastboot data load
978 09:15:38.979314 fastboot data verify
979 09:15:38.984053 verify result: 266
980 09:15:38.989744 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
981 09:15:38.990203 LPDDR4 probe
982 09:15:38.990632 ddr clk to 1584MHz
983 09:15:38.997691 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
984 09:15:39.035109
985 09:15:39.035581 dmc_version 0001
986 09:15:39.041691 Check phy result
987 09:15:39.047485 INFO : End of CA training
988 09:15:39.047942 INFO : End of initialization
989 09:15:39.053114 INFO : Training has run successfully!
990 09:15:39.053618 Check phy result
991 09:15:39.058852 INFO : End of initialization
992 09:15:39.059325 INFO : End of read enable training
993 09:15:39.062131 INFO : End of fine write leveling
994 09:15:39.067702 INFO : End of Write leveling coarse delay
995 09:15:39.073293 INFO : Training has run successfully!
996 09:15:39.073761 Check phy result
997 09:15:39.074204 INFO : End of initialization
998 09:15:39.078923 INFO : End of read dq deskew training
999 09:15:39.082415 INFO : End of MPR read delay center optimization
1000 09:15:39.087922 INFO : End of write delay center optimization
1001 09:15:39.093593 INFO : End of read delay center optimization
1002 09:15:39.094059 INFO : End of max read latency training
1003 09:15:39.099121 INFO : Training has run successfully!
1004 09:15:39.099589 1D training succeed
1005 09:15:39.107032 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
1006 09:15:39.154558 Check phy result
1007 09:15:39.155025 INFO : End of initialization
1008 09:15:39.176194 INFO : End of 2D read delay Voltage center optimization
1009 09:15:39.196304 INFO : End of 2D read delay Voltage center optimization
1010 09:15:39.248199 INFO : End of 2D write delay Voltage center optimization
1011 09:15:39.297415 INFO : End of 2D write delay Voltage center optimization
1012 09:15:39.303000 INFO : Training has run successfully!
1013 09:15:39.303469
1014 09:15:39.303923 channel==0
1015 09:15:39.308664 RxClkDly_Margin_A0==88 ps 9
1016 09:15:39.309141 TxDqDly_Margin_A0==98 ps 10
1017 09:15:39.314192 RxClkDly_Margin_A1==88 ps 9
1018 09:15:39.314658 TxDqDly_Margin_A1==98 ps 10
1019 09:15:39.315106 TrainedVREFDQ_A0==74
1020 09:15:39.319792 TrainedVREFDQ_A1==74
1021 09:15:39.320300 VrefDac_Margin_A0==25
1022 09:15:39.320749 DeviceVref_Margin_A0==40
1023 09:15:39.325401 VrefDac_Margin_A1==25
1024 09:15:39.325867 DeviceVref_Margin_A1==40
1025 09:15:39.326312
1026 09:15:39.326749
1027 09:15:39.331026 channel==1
1028 09:15:39.331521 RxClkDly_Margin_A0==98 ps 10
1029 09:15:39.331968 TxDqDly_Margin_A0==98 ps 10
1030 09:15:39.336641 RxClkDly_Margin_A1==98 ps 10
1031 09:15:39.337117 TxDqDly_Margin_A1==88 ps 9
1032 09:15:39.342158 TrainedVREFDQ_A0==77
1033 09:15:39.342630 TrainedVREFDQ_A1==77
1034 09:15:39.343079 VrefDac_Margin_A0==22
1035 09:15:39.347748 DeviceVref_Margin_A0==37
1036 09:15:39.348264 VrefDac_Margin_A1==23
1037 09:15:39.353388 DeviceVref_Margin_A1==37
1038 09:15:39.353853
1039 09:15:39.354296 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
1040 09:15:39.359007
1041 09:15:39.387003 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000019 00000017 00000019 00000018 0000001a 0000001a 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
1042 09:15:39.387517 2D training succeed
1043 09:15:39.392592 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
1044 09:15:39.398181 auto size-- 65535DDR cs0 size: 2048MB
1045 09:15:39.398648 DDR cs1 size: 2048MB
1046 09:15:39.403783 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
1047 09:15:39.404289 cs0 DataBus test pass
1048 09:15:39.409376 cs1 DataBus test pass
1049 09:15:39.409843 cs0 AddrBus test pass
1050 09:15:39.410289 cs1 AddrBus test pass
1051 09:15:39.410725
1052 09:15:39.415012 100bdlr_step_size ps== 420
1053 09:15:39.415491 result report
1054 09:15:39.420600 boot times 0Enable ddr reg access
1055 09:15:39.426039 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
1056 09:15:39.439494 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
1057 09:15:40.011593 0.0;M3 CHK:0;cm4_sp_mode 0
1058 09:15:40.012289 MVN_1=0x00000000
1059 09:15:40.016983 MVN_2=0x00000000
1060 09:15:40.022829 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
1061 09:15:40.023317 OPS=0x10
1062 09:15:40.023770 ring efuse init
1063 09:15:40.024269 chipver efuse init
1064 09:15:40.028335 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
1065 09:15:40.033952 [0.018961 Inits done]
1066 09:15:40.034433 secure task start!
1067 09:15:40.034883 high task start!
1068 09:15:40.038510 low task start!
1069 09:15:40.038988 run into bl31
1070 09:15:40.045186 NOTICE: BL31: v1.3(release):4fc40b1
1071 09:15:40.052984 NOTICE: BL31: Built : 15:58:17, May 22 2019
1072 09:15:40.053467 NOTICE: BL31: G12A normal boot!
1073 09:15:40.078886 NOTICE: BL31: BL33 decompress pass
1074 09:15:40.084590 ERROR: Error initializing runtime service opteed_fast
1075 09:15:41.317588
1076 09:15:41.318252
1077 09:15:41.326009 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
1078 09:15:41.326528
1079 09:15:41.326993 Model: Libre Computer AML-A311D-CC Alta
1080 09:15:41.534443 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
1081 09:15:41.557794 DRAM: 2 GiB (effective 3.8 GiB)
1082 09:15:41.700756 Core: 408 devices, 31 uclasses, devicetree: separate
1083 09:15:41.706693 WDT: Not starting watchdog@f0d0
1084 09:15:41.738971 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
1085 09:15:41.751366 Loading Environment from FAT... Card did not respond to voltage select! : -110
1086 09:15:41.756391 ** Bad device specification mmc 0 **
1087 09:15:41.766717 Card did not respond to voltage select! : -110
1088 09:15:41.774365 ** Bad device specification mmc 0 **
1089 09:15:41.774840 Couldn't find partition mmc 0
1090 09:15:41.782704 Card did not respond to voltage select! : -110
1091 09:15:41.788236 ** Bad device specification mmc 0 **
1092 09:15:41.788711 Couldn't find partition mmc 0
1093 09:15:41.793288 Error: could not access storage.
1094 09:15:42.136012 Net: eth0: ethernet@ff3f0000
1095 09:15:42.136407 starting USB...
1096 09:15:42.387503 Bus usb@ff500000: Register 3000140 NbrPorts 3
1097 09:15:42.388103 Starting the controller
1098 09:15:42.394567 USB XHCI 1.10
1099 09:15:43.951673 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
1100 09:15:43.959844 scanning usb for storage devices... 0 Storage Device(s) found
1102 09:15:44.011433 Hit any key to stop autoboot: 1
1103 09:15:44.012181 end: 2.4.2 bootloader-interrupt (duration 00:00:37) [common]
1104 09:15:44.012771 start: 2.4.3 bootloader-commands (timeout 00:04:22) [common]
1105 09:15:44.013224 Setting prompt string to ['=>']
1106 09:15:44.013692 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:22)
1107 09:15:44.028279 0
1108 09:15:44.029125 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1109 09:15:44.029608 Sending with 10 millisecond of delay
1111 09:15:45.164039 => setenv autoload no
1112 09:15:45.174818 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:21)
1113 09:15:45.179664 setenv autoload no
1114 09:15:45.180436 Sending with 10 millisecond of delay
1116 09:15:46.977218 => setenv initrd_high 0xffffffff
1117 09:15:46.988044 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:19)
1118 09:15:46.988909 setenv initrd_high 0xffffffff
1119 09:15:46.989624 Sending with 10 millisecond of delay
1121 09:15:48.605968 => setenv fdt_high 0xffffffff
1122 09:15:48.616695 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1123 09:15:48.617503 setenv fdt_high 0xffffffff
1124 09:15:48.618205 Sending with 10 millisecond of delay
1126 09:15:48.909930 => dhcp
1127 09:15:48.920595 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1128 09:15:48.921364 dhcp
1129 09:15:48.921795 Speed: 1000, full duplex
1130 09:15:48.922207 BOOTP broadcast 1
1131 09:15:48.948353 DHCP client bound to address 192.168.6.27 (28 ms)
1132 09:15:48.949040 Sending with 10 millisecond of delay
1134 09:15:50.625210 => setenv serverip 192.168.6.2
1135 09:15:50.636018 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:16)
1136 09:15:50.636909 setenv serverip 192.168.6.2
1137 09:15:50.637591 Sending with 10 millisecond of delay
1139 09:15:54.360157 => tftpboot 0x01080000 921892/tftp-deploy-5oml_rjo/kernel/uImage
1140 09:15:54.370959 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:12)
1141 09:15:54.371759 tftpboot 0x01080000 921892/tftp-deploy-5oml_rjo/kernel/uImage
1142 09:15:54.372263 Speed: 1000, full duplex
1143 09:15:54.372683 Using ethernet@ff3f0000 device
1144 09:15:54.373589 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1145 09:15:54.379141 Filename '921892/tftp-deploy-5oml_rjo/kernel/uImage'.
1146 09:15:54.383242 Load address: 0x1080000
1147 09:15:58.455437 Loading: *#################################################
1148 09:15:58.456128 TFTP error: trying to overwrite reserved memory...
1150 09:15:58.457538 end: 2.4.3 bootloader-commands (duration 00:00:14) [common]
1153 09:15:58.459357 end: 2.4 uboot-commands (duration 00:00:52) [common]
1155 09:15:58.460857 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'TFTP error: trying to overwrite reserved memory' (12)'
1157 09:15:58.461879 end: 2 uboot-action (duration 00:00:52) [common]
1159 09:15:58.463335 Cleaning after the job
1160 09:15:58.463872 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/921892/tftp-deploy-5oml_rjo/ramdisk
1161 09:15:58.480450 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/921892/tftp-deploy-5oml_rjo/kernel
1162 09:15:58.511531 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/921892/tftp-deploy-5oml_rjo/dtb
1163 09:15:58.512254 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/921892/tftp-deploy-5oml_rjo/nfsrootfs
1164 09:15:58.658770 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/921892/tftp-deploy-5oml_rjo/modules
1165 09:15:58.688929 start: 4.1 power-off (timeout 00:00:30) [common]
1166 09:15:58.689587 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1167 09:15:58.722516 >> OK - accepted request
1168 09:15:58.724526 Returned 0 in 0 seconds
1169 09:15:58.825210 end: 4.1 power-off (duration 00:00:00) [common]
1171 09:15:58.826104 start: 4.2 read-feedback (timeout 00:10:00) [common]
1172 09:15:58.826758 Listened to connection for namespace 'common' for up to 1s
1173 09:15:59.827668 Finalising connection for namespace 'common'
1174 09:15:59.828120 Disconnecting from shell: Finalise
1175 09:15:59.828411 =>
1176 09:15:59.929086 end: 4.2 read-feedback (duration 00:00:01) [common]
1177 09:15:59.929686 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/921892
1178 09:16:01.868553 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/921892
1179 09:16:01.869274 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.