Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 10:11:02.803919 lava-dispatcher, installed at version: 2024.01
2 10:11:02.804735 start: 0 validate
3 10:11:02.805217 Start time: 2024-11-01 10:11:02.805188+00:00 (UTC)
4 10:11:02.805757 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 10:11:02.806312 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-igt%2F20240313.0%2Farm64%2Frootfs.cpio.gz exists
6 10:11:02.848918 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 10:11:02.849443 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241101%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 10:11:02.880407 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 10:11:02.881024 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241101%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 10:11:02.910212 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 10:11:02.910733 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241101%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
12 10:11:02.948322 validate duration: 0.14
14 10:11:02.949173 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 10:11:02.949499 start: 1.1 download-retry (timeout 00:10:00) [common]
16 10:11:02.949789 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 10:11:02.950360 Not decompressing ramdisk as can be used compressed.
18 10:11:02.950812 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-igt/20240313.0/arm64/rootfs.cpio.gz
19 10:11:02.951044 saving as /var/lib/lava/dispatcher/tmp/921981/tftp-deploy-ghypho9e/ramdisk/rootfs.cpio.gz
20 10:11:02.951288 total size: 47897469 (45 MB)
21 10:11:02.992961 progress 0 % (0 MB)
22 10:11:03.023269 progress 5 % (2 MB)
23 10:11:03.052710 progress 10 % (4 MB)
24 10:11:03.082185 progress 15 % (6 MB)
25 10:11:03.112066 progress 20 % (9 MB)
26 10:11:03.141550 progress 25 % (11 MB)
27 10:11:03.170959 progress 30 % (13 MB)
28 10:11:03.200780 progress 35 % (16 MB)
29 10:11:03.230076 progress 40 % (18 MB)
30 10:11:03.259456 progress 45 % (20 MB)
31 10:11:03.288756 progress 50 % (22 MB)
32 10:11:03.318427 progress 55 % (25 MB)
33 10:11:03.348279 progress 60 % (27 MB)
34 10:11:03.377485 progress 65 % (29 MB)
35 10:11:03.406852 progress 70 % (32 MB)
36 10:11:03.435861 progress 75 % (34 MB)
37 10:11:03.464937 progress 80 % (36 MB)
38 10:11:03.494072 progress 85 % (38 MB)
39 10:11:03.523325 progress 90 % (41 MB)
40 10:11:03.552366 progress 95 % (43 MB)
41 10:11:03.580258 progress 100 % (45 MB)
42 10:11:03.581011 45 MB downloaded in 0.63 s (72.54 MB/s)
43 10:11:03.581554 end: 1.1.1 http-download (duration 00:00:01) [common]
45 10:11:03.582424 end: 1.1 download-retry (duration 00:00:01) [common]
46 10:11:03.582713 start: 1.2 download-retry (timeout 00:09:59) [common]
47 10:11:03.582982 start: 1.2.1 http-download (timeout 00:09:59) [common]
48 10:11:03.583527 downloading http://storage.kernelci.org/next/master/next-20241101/arm64/defconfig/gcc-12/kernel/Image
49 10:11:03.583792 saving as /var/lib/lava/dispatcher/tmp/921981/tftp-deploy-ghypho9e/kernel/Image
50 10:11:03.584025 total size: 45908480 (43 MB)
51 10:11:03.584240 No compression specified
52 10:11:03.625742 progress 0 % (0 MB)
53 10:11:03.654213 progress 5 % (2 MB)
54 10:11:03.682750 progress 10 % (4 MB)
55 10:11:03.711428 progress 15 % (6 MB)
56 10:11:03.739848 progress 20 % (8 MB)
57 10:11:03.768516 progress 25 % (10 MB)
58 10:11:03.796409 progress 30 % (13 MB)
59 10:11:03.824284 progress 35 % (15 MB)
60 10:11:03.852691 progress 40 % (17 MB)
61 10:11:03.880916 progress 45 % (19 MB)
62 10:11:03.909482 progress 50 % (21 MB)
63 10:11:03.937908 progress 55 % (24 MB)
64 10:11:03.966397 progress 60 % (26 MB)
65 10:11:03.994841 progress 65 % (28 MB)
66 10:11:04.023233 progress 70 % (30 MB)
67 10:11:04.051892 progress 75 % (32 MB)
68 10:11:04.080299 progress 80 % (35 MB)
69 10:11:04.108738 progress 85 % (37 MB)
70 10:11:04.137231 progress 90 % (39 MB)
71 10:11:04.165922 progress 95 % (41 MB)
72 10:11:04.193750 progress 100 % (43 MB)
73 10:11:04.194275 43 MB downloaded in 0.61 s (71.75 MB/s)
74 10:11:04.194756 end: 1.2.1 http-download (duration 00:00:01) [common]
76 10:11:04.195564 end: 1.2 download-retry (duration 00:00:01) [common]
77 10:11:04.195837 start: 1.3 download-retry (timeout 00:09:59) [common]
78 10:11:04.196128 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 10:11:04.196596 downloading http://storage.kernelci.org/next/master/next-20241101/arm64/defconfig/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
80 10:11:04.196843 saving as /var/lib/lava/dispatcher/tmp/921981/tftp-deploy-ghypho9e/dtb/meson-g12b-a311d-libretech-cc.dtb
81 10:11:04.197048 total size: 54703 (0 MB)
82 10:11:04.197257 No compression specified
83 10:11:04.238077 progress 59 % (0 MB)
84 10:11:04.238922 progress 100 % (0 MB)
85 10:11:04.239461 0 MB downloaded in 0.04 s (1.23 MB/s)
86 10:11:04.239928 end: 1.3.1 http-download (duration 00:00:00) [common]
88 10:11:04.240779 end: 1.3 download-retry (duration 00:00:00) [common]
89 10:11:04.241039 start: 1.4 download-retry (timeout 00:09:59) [common]
90 10:11:04.241301 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 10:11:04.241767 downloading http://storage.kernelci.org/next/master/next-20241101/arm64/defconfig/gcc-12/modules.tar.xz
92 10:11:04.242038 saving as /var/lib/lava/dispatcher/tmp/921981/tftp-deploy-ghypho9e/modules/modules.tar
93 10:11:04.242246 total size: 11594840 (11 MB)
94 10:11:04.242458 Using unxz to decompress xz
95 10:11:04.276393 progress 0 % (0 MB)
96 10:11:04.343235 progress 5 % (0 MB)
97 10:11:04.417546 progress 10 % (1 MB)
98 10:11:04.497276 progress 15 % (1 MB)
99 10:11:04.573382 progress 20 % (2 MB)
100 10:11:04.649001 progress 25 % (2 MB)
101 10:11:04.728405 progress 30 % (3 MB)
102 10:11:04.800744 progress 35 % (3 MB)
103 10:11:04.880050 progress 40 % (4 MB)
104 10:11:04.965968 progress 45 % (5 MB)
105 10:11:05.042938 progress 50 % (5 MB)
106 10:11:05.126246 progress 55 % (6 MB)
107 10:11:05.206695 progress 60 % (6 MB)
108 10:11:05.291694 progress 65 % (7 MB)
109 10:11:05.367921 progress 70 % (7 MB)
110 10:11:05.455113 progress 75 % (8 MB)
111 10:11:05.536960 progress 80 % (8 MB)
112 10:11:05.612342 progress 85 % (9 MB)
113 10:11:05.685753 progress 90 % (9 MB)
114 10:11:05.786755 progress 95 % (10 MB)
115 10:11:05.878810 progress 100 % (11 MB)
116 10:11:05.892762 11 MB downloaded in 1.65 s (6.70 MB/s)
117 10:11:05.893511 end: 1.4.1 http-download (duration 00:00:02) [common]
119 10:11:05.895332 end: 1.4 download-retry (duration 00:00:02) [common]
120 10:11:05.896023 start: 1.5 prepare-tftp-overlay (timeout 00:09:57) [common]
121 10:11:05.896659 start: 1.5.1 extract-nfsrootfs (timeout 00:09:57) [common]
122 10:11:05.897228 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 10:11:05.897787 start: 1.5.2 lava-overlay (timeout 00:09:57) [common]
124 10:11:05.898829 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/921981/lava-overlay-4waf414j
125 10:11:05.899815 makedir: /var/lib/lava/dispatcher/tmp/921981/lava-overlay-4waf414j/lava-921981/bin
126 10:11:05.900579 makedir: /var/lib/lava/dispatcher/tmp/921981/lava-overlay-4waf414j/lava-921981/tests
127 10:11:05.901309 makedir: /var/lib/lava/dispatcher/tmp/921981/lava-overlay-4waf414j/lava-921981/results
128 10:11:05.902012 Creating /var/lib/lava/dispatcher/tmp/921981/lava-overlay-4waf414j/lava-921981/bin/lava-add-keys
129 10:11:05.903133 Creating /var/lib/lava/dispatcher/tmp/921981/lava-overlay-4waf414j/lava-921981/bin/lava-add-sources
130 10:11:05.904199 Creating /var/lib/lava/dispatcher/tmp/921981/lava-overlay-4waf414j/lava-921981/bin/lava-background-process-start
131 10:11:05.905252 Creating /var/lib/lava/dispatcher/tmp/921981/lava-overlay-4waf414j/lava-921981/bin/lava-background-process-stop
132 10:11:05.906325 Creating /var/lib/lava/dispatcher/tmp/921981/lava-overlay-4waf414j/lava-921981/bin/lava-common-functions
133 10:11:05.907412 Creating /var/lib/lava/dispatcher/tmp/921981/lava-overlay-4waf414j/lava-921981/bin/lava-echo-ipv4
134 10:11:05.908507 Creating /var/lib/lava/dispatcher/tmp/921981/lava-overlay-4waf414j/lava-921981/bin/lava-install-packages
135 10:11:05.909540 Creating /var/lib/lava/dispatcher/tmp/921981/lava-overlay-4waf414j/lava-921981/bin/lava-installed-packages
136 10:11:05.910538 Creating /var/lib/lava/dispatcher/tmp/921981/lava-overlay-4waf414j/lava-921981/bin/lava-os-build
137 10:11:05.911541 Creating /var/lib/lava/dispatcher/tmp/921981/lava-overlay-4waf414j/lava-921981/bin/lava-probe-channel
138 10:11:05.912620 Creating /var/lib/lava/dispatcher/tmp/921981/lava-overlay-4waf414j/lava-921981/bin/lava-probe-ip
139 10:11:05.913661 Creating /var/lib/lava/dispatcher/tmp/921981/lava-overlay-4waf414j/lava-921981/bin/lava-target-ip
140 10:11:05.914651 Creating /var/lib/lava/dispatcher/tmp/921981/lava-overlay-4waf414j/lava-921981/bin/lava-target-mac
141 10:11:05.915646 Creating /var/lib/lava/dispatcher/tmp/921981/lava-overlay-4waf414j/lava-921981/bin/lava-target-storage
142 10:11:05.916730 Creating /var/lib/lava/dispatcher/tmp/921981/lava-overlay-4waf414j/lava-921981/bin/lava-test-case
143 10:11:05.917742 Creating /var/lib/lava/dispatcher/tmp/921981/lava-overlay-4waf414j/lava-921981/bin/lava-test-event
144 10:11:05.918816 Creating /var/lib/lava/dispatcher/tmp/921981/lava-overlay-4waf414j/lava-921981/bin/lava-test-feedback
145 10:11:05.919868 Creating /var/lib/lava/dispatcher/tmp/921981/lava-overlay-4waf414j/lava-921981/bin/lava-test-raise
146 10:11:05.920945 Creating /var/lib/lava/dispatcher/tmp/921981/lava-overlay-4waf414j/lava-921981/bin/lava-test-reference
147 10:11:05.921957 Creating /var/lib/lava/dispatcher/tmp/921981/lava-overlay-4waf414j/lava-921981/bin/lava-test-runner
148 10:11:05.922945 Creating /var/lib/lava/dispatcher/tmp/921981/lava-overlay-4waf414j/lava-921981/bin/lava-test-set
149 10:11:05.923966 Creating /var/lib/lava/dispatcher/tmp/921981/lava-overlay-4waf414j/lava-921981/bin/lava-test-shell
150 10:11:05.925088 Updating /var/lib/lava/dispatcher/tmp/921981/lava-overlay-4waf414j/lava-921981/bin/lava-install-packages (oe)
151 10:11:05.926191 Updating /var/lib/lava/dispatcher/tmp/921981/lava-overlay-4waf414j/lava-921981/bin/lava-installed-packages (oe)
152 10:11:05.927099 Creating /var/lib/lava/dispatcher/tmp/921981/lava-overlay-4waf414j/lava-921981/environment
153 10:11:05.927873 LAVA metadata
154 10:11:05.928449 - LAVA_JOB_ID=921981
155 10:11:05.928918 - LAVA_DISPATCHER_IP=192.168.6.2
156 10:11:05.929652 start: 1.5.2.1 ssh-authorize (timeout 00:09:57) [common]
157 10:11:05.931722 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 10:11:05.932413 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:57) [common]
159 10:11:05.932847 skipped lava-vland-overlay
160 10:11:05.933351 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 10:11:05.933869 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:57) [common]
162 10:11:05.934304 skipped lava-multinode-overlay
163 10:11:05.934798 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 10:11:05.935341 start: 1.5.2.4 test-definition (timeout 00:09:57) [common]
165 10:11:05.935847 Loading test definitions
166 10:11:05.936461 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:57) [common]
167 10:11:05.936913 Using /lava-921981 at stage 0
168 10:11:05.939188 uuid=921981_1.5.2.4.1 testdef=None
169 10:11:05.939754 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 10:11:05.940192 start: 1.5.2.4.2 test-overlay (timeout 00:09:57) [common]
171 10:11:05.942081 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 10:11:05.942894 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:57) [common]
174 10:11:05.945535 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 10:11:05.946436 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:57) [common]
177 10:11:05.948715 runner path: /var/lib/lava/dispatcher/tmp/921981/lava-overlay-4waf414j/lava-921981/0/tests/0_igt-gpu-panfrost test_uuid 921981_1.5.2.4.1
178 10:11:05.949332 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 10:11:05.950146 Creating lava-test-runner.conf files
181 10:11:05.950355 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/921981/lava-overlay-4waf414j/lava-921981/0 for stage 0
182 10:11:05.950713 - 0_igt-gpu-panfrost
183 10:11:05.951067 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 10:11:05.951350 start: 1.5.2.5 compress-overlay (timeout 00:09:57) [common]
185 10:11:05.975524 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 10:11:05.975913 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:57) [common]
187 10:11:05.976197 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 10:11:05.976464 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 10:11:05.976725 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:57) [common]
190 10:11:12.821215 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:07) [common]
191 10:11:12.821785 start: 1.5.4 extract-modules (timeout 00:09:50) [common]
192 10:11:12.822089 extracting modules file /var/lib/lava/dispatcher/tmp/921981/tftp-deploy-ghypho9e/modules/modules.tar to /var/lib/lava/dispatcher/tmp/921981/extract-overlay-ramdisk-afq83fr6/ramdisk
193 10:11:14.297487 end: 1.5.4 extract-modules (duration 00:00:01) [common]
194 10:11:14.297971 start: 1.5.5 apply-overlay-tftp (timeout 00:09:49) [common]
195 10:11:14.298269 [common] Applying overlay /var/lib/lava/dispatcher/tmp/921981/compress-overlay-ykl3z1yk/overlay-1.5.2.5.tar.gz to ramdisk
196 10:11:14.298499 [common] Applying overlay /var/lib/lava/dispatcher/tmp/921981/compress-overlay-ykl3z1yk/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/921981/extract-overlay-ramdisk-afq83fr6/ramdisk
197 10:11:14.328449 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 10:11:14.328827 start: 1.5.6 prepare-kernel (timeout 00:09:49) [common]
199 10:11:14.329121 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:49) [common]
200 10:11:14.329361 Converting downloaded kernel to a uImage
201 10:11:14.329672 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/921981/tftp-deploy-ghypho9e/kernel/Image /var/lib/lava/dispatcher/tmp/921981/tftp-deploy-ghypho9e/kernel/uImage
202 10:11:14.875354 output: Image Name:
203 10:11:14.875849 output: Created: Fri Nov 1 10:11:14 2024
204 10:11:14.876149 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 10:11:14.876401 output: Data Size: 45908480 Bytes = 44832.50 KiB = 43.78 MiB
206 10:11:14.876646 output: Load Address: 01080000
207 10:11:14.876891 output: Entry Point: 01080000
208 10:11:14.877132 output:
209 10:11:14.877524 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:01) [common]
210 10:11:14.877849 end: 1.5.6 prepare-kernel (duration 00:00:01) [common]
211 10:11:14.878176 start: 1.5.7 configure-preseed-file (timeout 00:09:48) [common]
212 10:11:14.878477 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 10:11:14.878782 start: 1.5.8 compress-ramdisk (timeout 00:09:48) [common]
214 10:11:14.879091 Building ramdisk /var/lib/lava/dispatcher/tmp/921981/extract-overlay-ramdisk-afq83fr6/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/921981/extract-overlay-ramdisk-afq83fr6/ramdisk
215 10:11:21.371253 >> 502773 blocks
216 10:11:41.942200 Adding RAMdisk u-boot header.
217 10:11:41.942897 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/921981/extract-overlay-ramdisk-afq83fr6/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/921981/extract-overlay-ramdisk-afq83fr6/ramdisk.cpio.gz.uboot
218 10:11:42.624622 output: Image Name:
219 10:11:42.625291 output: Created: Fri Nov 1 10:11:41 2024
220 10:11:42.625764 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 10:11:42.626220 output: Data Size: 65730643 Bytes = 64190.08 KiB = 62.69 MiB
222 10:11:42.626666 output: Load Address: 00000000
223 10:11:42.627106 output: Entry Point: 00000000
224 10:11:42.627545 output:
225 10:11:42.628850 rename /var/lib/lava/dispatcher/tmp/921981/extract-overlay-ramdisk-afq83fr6/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/921981/tftp-deploy-ghypho9e/ramdisk/ramdisk.cpio.gz.uboot
226 10:11:42.629641 end: 1.5.8 compress-ramdisk (duration 00:00:28) [common]
227 10:11:42.630243 end: 1.5 prepare-tftp-overlay (duration 00:00:37) [common]
228 10:11:42.630826 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:20) [common]
229 10:11:42.631328 No LXC device requested
230 10:11:42.631882 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 10:11:42.632491 start: 1.7 deploy-device-env (timeout 00:09:20) [common]
232 10:11:42.633049 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 10:11:42.633504 Checking files for TFTP limit of 4294967296 bytes.
234 10:11:42.636418 end: 1 tftp-deploy (duration 00:00:40) [common]
235 10:11:42.637060 start: 2 uboot-action (timeout 00:05:00) [common]
236 10:11:42.637708 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 10:11:42.638285 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 10:11:42.638854 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 10:11:42.639446 Using kernel file from prepare-kernel: 921981/tftp-deploy-ghypho9e/kernel/uImage
240 10:11:42.640180 substitutions:
241 10:11:42.640655 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 10:11:42.641106 - {DTB_ADDR}: 0x01070000
243 10:11:42.641550 - {DTB}: 921981/tftp-deploy-ghypho9e/dtb/meson-g12b-a311d-libretech-cc.dtb
244 10:11:42.641995 - {INITRD}: 921981/tftp-deploy-ghypho9e/ramdisk/ramdisk.cpio.gz.uboot
245 10:11:42.642432 - {KERNEL_ADDR}: 0x01080000
246 10:11:42.642867 - {KERNEL}: 921981/tftp-deploy-ghypho9e/kernel/uImage
247 10:11:42.643303 - {LAVA_MAC}: None
248 10:11:42.643783 - {PRESEED_CONFIG}: None
249 10:11:42.644313 - {PRESEED_LOCAL}: None
250 10:11:42.644760 - {RAMDISK_ADDR}: 0x08000000
251 10:11:42.645193 - {RAMDISK}: 921981/tftp-deploy-ghypho9e/ramdisk/ramdisk.cpio.gz.uboot
252 10:11:42.645634 - {ROOT_PART}: None
253 10:11:42.646066 - {ROOT}: None
254 10:11:42.646504 - {SERVER_IP}: 192.168.6.2
255 10:11:42.646944 - {TEE_ADDR}: 0x83000000
256 10:11:42.647382 - {TEE}: None
257 10:11:42.647817 Parsed boot commands:
258 10:11:42.648272 - setenv autoload no
259 10:11:42.648710 - setenv initrd_high 0xffffffff
260 10:11:42.649141 - setenv fdt_high 0xffffffff
261 10:11:42.649572 - dhcp
262 10:11:42.650003 - setenv serverip 192.168.6.2
263 10:11:42.650433 - tftpboot 0x01080000 921981/tftp-deploy-ghypho9e/kernel/uImage
264 10:11:42.650865 - tftpboot 0x08000000 921981/tftp-deploy-ghypho9e/ramdisk/ramdisk.cpio.gz.uboot
265 10:11:42.651297 - tftpboot 0x01070000 921981/tftp-deploy-ghypho9e/dtb/meson-g12b-a311d-libretech-cc.dtb
266 10:11:42.651730 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 10:11:42.652243 - bootm 0x01080000 0x08000000 0x01070000
268 10:11:42.652812 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 10:11:42.654463 start: 2.3 connect-device (timeout 00:05:00) [common]
271 10:11:42.654963 [common] connect-device Connecting to device using 'telnet conserv1 3007'
272 10:11:42.670394 Setting prompt string to ['lava-test: # ']
273 10:11:42.672075 end: 2.3 connect-device (duration 00:00:00) [common]
274 10:11:42.672770 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 10:11:42.673482 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 10:11:42.674123 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 10:11:42.675413 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
278 10:11:42.713869 >> OK - accepted request
279 10:11:42.716065 Returned 0 in 0 seconds
280 10:11:42.817350 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
282 10:11:42.819186 end: 2.4.1 reset-device (duration 00:00:00) [common]
283 10:11:42.819852 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
284 10:11:42.820492 Setting prompt string to ['Hit any key to stop autoboot']
285 10:11:42.821002 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 10:11:42.822725 Trying 192.168.56.21...
287 10:11:42.823281 Connected to conserv1.
288 10:11:42.823770 Escape character is '^]'.
289 10:11:42.824269
290 10:11:42.824759 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
291 10:11:42.825240
292 10:11:53.660818 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
293 10:11:53.661515 bl2_stage_init 0x01
294 10:11:53.662011 bl2_stage_init 0x81
295 10:11:53.666397 hw id: 0x0000 - pwm id 0x01
296 10:11:53.666987 bl2_stage_init 0xc1
297 10:11:53.667464 bl2_stage_init 0x02
298 10:11:53.667915
299 10:11:53.672044 L0:00000000
300 10:11:53.672544 L1:20000703
301 10:11:53.672981 L2:00008067
302 10:11:53.673409 L3:14000000
303 10:11:53.677470 B2:00402000
304 10:11:53.677959 B1:e0f83180
305 10:11:53.678404
306 10:11:53.678834 TE: 58124
307 10:11:53.679264
308 10:11:53.683117 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
309 10:11:53.683612
310 10:11:53.684082 Board ID = 1
311 10:11:53.688740 Set A53 clk to 24M
312 10:11:53.689223 Set A73 clk to 24M
313 10:11:53.689650 Set clk81 to 24M
314 10:11:53.694316 A53 clk: 1200 MHz
315 10:11:53.694800 A73 clk: 1200 MHz
316 10:11:53.695228 CLK81: 166.6M
317 10:11:53.695651 smccc: 00012a92
318 10:11:53.700081 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
319 10:11:53.705450 board id: 1
320 10:11:53.711561 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
321 10:11:53.721907 fw parse done
322 10:11:53.727933 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
323 10:11:53.770506 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
324 10:11:53.781401 PIEI prepare done
325 10:11:53.781895 fastboot data load
326 10:11:53.782330 fastboot data verify
327 10:11:53.787094 verify result: 266
328 10:11:53.792724 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
329 10:11:53.793219 LPDDR4 probe
330 10:11:53.793650 ddr clk to 1584MHz
331 10:11:53.800677 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
332 10:11:53.837967
333 10:11:53.838504 dmc_version 0001
334 10:11:53.844612 Check phy result
335 10:11:53.850494 INFO : End of CA training
336 10:11:53.851003 INFO : End of initialization
337 10:11:53.856137 INFO : Training has run successfully!
338 10:11:53.856650 Check phy result
339 10:11:53.861716 INFO : End of initialization
340 10:11:53.862221 INFO : End of read enable training
341 10:11:53.867291 INFO : End of fine write leveling
342 10:11:53.872998 INFO : End of Write leveling coarse delay
343 10:11:53.873505 INFO : Training has run successfully!
344 10:11:53.873956 Check phy result
345 10:11:53.878501 INFO : End of initialization
346 10:11:53.879007 INFO : End of read dq deskew training
347 10:11:53.884101 INFO : End of MPR read delay center optimization
348 10:11:53.889684 INFO : End of write delay center optimization
349 10:11:53.895299 INFO : End of read delay center optimization
350 10:11:53.895829 INFO : End of max read latency training
351 10:11:53.901015 INFO : Training has run successfully!
352 10:11:53.901523 1D training succeed
353 10:11:53.910079 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
354 10:11:53.957677 Check phy result
355 10:11:53.958221 INFO : End of initialization
356 10:11:53.980286 INFO : End of 2D read delay Voltage center optimization
357 10:11:54.000473 INFO : End of 2D read delay Voltage center optimization
358 10:11:54.052495 INFO : End of 2D write delay Voltage center optimization
359 10:11:54.101934 INFO : End of 2D write delay Voltage center optimization
360 10:11:54.107426 INFO : Training has run successfully!
361 10:11:54.107934
362 10:11:54.108440 channel==0
363 10:11:54.113027 RxClkDly_Margin_A0==88 ps 9
364 10:11:54.113534 TxDqDly_Margin_A0==98 ps 10
365 10:11:54.118635 RxClkDly_Margin_A1==88 ps 9
366 10:11:54.119134 TxDqDly_Margin_A1==98 ps 10
367 10:11:54.119589 TrainedVREFDQ_A0==74
368 10:11:54.124255 TrainedVREFDQ_A1==74
369 10:11:54.124766 VrefDac_Margin_A0==24
370 10:11:54.125213 DeviceVref_Margin_A0==40
371 10:11:54.129826 VrefDac_Margin_A1==24
372 10:11:54.130327 DeviceVref_Margin_A1==40
373 10:11:54.130770
374 10:11:54.131214
375 10:11:54.135433 channel==1
376 10:11:54.135936 RxClkDly_Margin_A0==98 ps 10
377 10:11:54.136421 TxDqDly_Margin_A0==88 ps 9
378 10:11:54.141016 RxClkDly_Margin_A1==98 ps 10
379 10:11:54.141535 TxDqDly_Margin_A1==98 ps 10
380 10:11:54.146641 TrainedVREFDQ_A0==77
381 10:11:54.147144 TrainedVREFDQ_A1==77
382 10:11:54.147596 VrefDac_Margin_A0==22
383 10:11:54.152253 DeviceVref_Margin_A0==37
384 10:11:54.152747 VrefDac_Margin_A1==22
385 10:11:54.157898 DeviceVref_Margin_A1==37
386 10:11:54.158399
387 10:11:54.158849 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
388 10:11:54.163403
389 10:11:54.191380 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000017 00000018 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
390 10:11:54.192036 2D training succeed
391 10:11:54.197050 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
392 10:11:54.203162 auto size-- 65535DDR cs0 size: 2048MB
393 10:11:54.203692 DDR cs1 size: 2048MB
394 10:11:54.208261 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
395 10:11:54.208767 cs0 DataBus test pass
396 10:11:54.213844 cs1 DataBus test pass
397 10:11:54.214347 cs0 AddrBus test pass
398 10:11:54.214794 cs1 AddrBus test pass
399 10:11:54.215228
400 10:11:54.219433 100bdlr_step_size ps== 420
401 10:11:54.219941 result report
402 10:11:54.225014 boot times 0Enable ddr reg access
403 10:11:54.230400 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
404 10:11:54.243880 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
405 10:11:54.817581 0.0;M3 CHK:0;cm4_sp_mode 0
406 10:11:54.818218 MVN_1=0x00000000
407 10:11:54.823037 MVN_2=0x00000000
408 10:11:54.828825 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
409 10:11:54.829285 OPS=0x10
410 10:11:54.829709 ring efuse init
411 10:11:54.830123 chipver efuse init
412 10:11:54.834358 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
413 10:11:54.840032 [0.018960 Inits done]
414 10:11:54.840494 secure task start!
415 10:11:54.840910 high task start!
416 10:11:54.844546 low task start!
417 10:11:54.844987 run into bl31
418 10:11:54.851223 NOTICE: BL31: v1.3(release):4fc40b1
419 10:11:54.859029 NOTICE: BL31: Built : 15:58:17, May 22 2019
420 10:11:54.859481 NOTICE: BL31: G12A normal boot!
421 10:11:54.884353 NOTICE: BL31: BL33 decompress pass
422 10:11:54.890014 ERROR: Error initializing runtime service opteed_fast
423 10:11:56.122963
424 10:11:56.123586
425 10:11:56.131259 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
426 10:11:56.131718
427 10:11:56.132163 Model: Libre Computer AML-A311D-CC Alta
428 10:11:56.339701 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
429 10:11:56.363124 DRAM: 2 GiB (effective 3.8 GiB)
430 10:11:56.506098 Core: 408 devices, 31 uclasses, devicetree: separate
431 10:11:56.511924 WDT: Not starting watchdog@f0d0
432 10:11:56.544271 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
433 10:11:56.556620 Loading Environment from FAT... Card did not respond to voltage select! : -110
434 10:11:56.561617 ** Bad device specification mmc 0 **
435 10:11:56.571947 Card did not respond to voltage select! : -110
436 10:11:56.579621 ** Bad device specification mmc 0 **
437 10:11:56.580092 Couldn't find partition mmc 0
438 10:11:56.587955 Card did not respond to voltage select! : -110
439 10:11:56.593527 ** Bad device specification mmc 0 **
440 10:11:56.594048 Couldn't find partition mmc 0
441 10:11:56.598535 Error: could not access storage.
442 10:11:57.861041 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
443 10:11:57.861624 bl2_stage_init 0x01
444 10:11:57.862055 bl2_stage_init 0x81
445 10:11:57.866597 hw id: 0x0000 - pwm id 0x01
446 10:11:57.867040 bl2_stage_init 0xc1
447 10:11:57.867446 bl2_stage_init 0x02
448 10:11:57.867842
449 10:11:57.872254 L0:00000000
450 10:11:57.872695 L1:20000703
451 10:11:57.873098 L2:00008067
452 10:11:57.873495 L3:14000000
453 10:11:57.875071 B2:00402000
454 10:11:57.875545 B1:e0f83180
455 10:11:57.875957
456 10:11:57.876402 TE: 58167
457 10:11:57.876806
458 10:11:57.886351 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
459 10:11:57.886790
460 10:11:57.887195 Board ID = 1
461 10:11:57.887594 Set A53 clk to 24M
462 10:11:57.888018 Set A73 clk to 24M
463 10:11:57.891850 Set clk81 to 24M
464 10:11:57.892317 A53 clk: 1200 MHz
465 10:11:57.892722 A73 clk: 1200 MHz
466 10:11:57.897459 CLK81: 166.6M
467 10:11:57.897893 smccc: 00012abe
468 10:11:57.903073 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
469 10:11:57.903512 board id: 1
470 10:11:57.911666 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
471 10:11:57.922389 fw parse done
472 10:11:57.928316 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
473 10:11:57.970919 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
474 10:11:57.981821 PIEI prepare done
475 10:11:57.982252 fastboot data load
476 10:11:57.982659 fastboot data verify
477 10:11:57.987518 verify result: 266
478 10:11:57.993087 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
479 10:11:57.993524 LPDDR4 probe
480 10:11:57.993926 ddr clk to 1584MHz
481 10:11:58.001041 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
482 10:11:58.038311
483 10:11:58.038754 dmc_version 0001
484 10:11:58.045066 Check phy result
485 10:11:58.050997 INFO : End of CA training
486 10:11:58.051536 INFO : End of initialization
487 10:11:58.056574 INFO : Training has run successfully!
488 10:11:58.057105 Check phy result
489 10:11:58.062182 INFO : End of initialization
490 10:11:58.062715 INFO : End of read enable training
491 10:11:58.065619 INFO : End of fine write leveling
492 10:11:58.071095 INFO : End of Write leveling coarse delay
493 10:11:58.076698 INFO : Training has run successfully!
494 10:11:58.077230 Check phy result
495 10:11:58.077691 INFO : End of initialization
496 10:11:58.082316 INFO : End of read dq deskew training
497 10:11:58.087904 INFO : End of MPR read delay center optimization
498 10:11:58.088470 INFO : End of write delay center optimization
499 10:11:58.093571 INFO : End of read delay center optimization
500 10:11:58.099089 INFO : End of max read latency training
501 10:11:58.099630 INFO : Training has run successfully!
502 10:11:58.104705 1D training succeed
503 10:11:58.110657 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
504 10:11:58.158153 Check phy result
505 10:11:58.158720 INFO : End of initialization
506 10:11:58.179752 INFO : End of 2D read delay Voltage center optimization
507 10:11:58.199872 INFO : End of 2D read delay Voltage center optimization
508 10:11:58.251791 INFO : End of 2D write delay Voltage center optimization
509 10:11:58.301014 INFO : End of 2D write delay Voltage center optimization
510 10:11:58.306645 INFO : Training has run successfully!
511 10:11:58.307195
512 10:11:58.307666 channel==0
513 10:11:58.312240 RxClkDly_Margin_A0==88 ps 9
514 10:11:58.312816 TxDqDly_Margin_A0==98 ps 10
515 10:11:58.317814 RxClkDly_Margin_A1==88 ps 9
516 10:11:58.318399 TxDqDly_Margin_A1==98 ps 10
517 10:11:58.318870 TrainedVREFDQ_A0==74
518 10:11:58.323371 TrainedVREFDQ_A1==74
519 10:11:58.323927 VrefDac_Margin_A0==25
520 10:11:58.324437 DeviceVref_Margin_A0==40
521 10:11:58.328980 VrefDac_Margin_A1==25
522 10:11:58.329531 DeviceVref_Margin_A1==40
523 10:11:58.329994
524 10:11:58.330445
525 10:11:58.334644 channel==1
526 10:11:58.335194 RxClkDly_Margin_A0==98 ps 10
527 10:11:58.335653 TxDqDly_Margin_A0==98 ps 10
528 10:11:58.340184 RxClkDly_Margin_A1==98 ps 10
529 10:11:58.340756 TxDqDly_Margin_A1==88 ps 9
530 10:11:58.345777 TrainedVREFDQ_A0==77
531 10:11:58.346327 TrainedVREFDQ_A1==77
532 10:11:58.346795 VrefDac_Margin_A0==22
533 10:11:58.351385 DeviceVref_Margin_A0==37
534 10:11:58.351924 VrefDac_Margin_A1==24
535 10:11:58.356985 DeviceVref_Margin_A1==37
536 10:11:58.357532
537 10:11:58.358000 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
538 10:11:58.362656
539 10:11:58.390534 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000019 00000017 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
540 10:11:58.391141 2D training succeed
541 10:11:58.396219 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
542 10:11:58.401786 auto size-- 65535DDR cs0 size: 2048MB
543 10:11:58.402351 DDR cs1 size: 2048MB
544 10:11:58.407403 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
545 10:11:58.407959 cs0 DataBus test pass
546 10:11:58.412982 cs1 DataBus test pass
547 10:11:58.413532 cs0 AddrBus test pass
548 10:11:58.413994 cs1 AddrBus test pass
549 10:11:58.414453
550 10:11:58.418652 100bdlr_step_size ps== 420
551 10:11:58.419215 result report
552 10:11:58.424200 boot times 0Enable ddr reg access
553 10:11:58.429712 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
554 10:11:58.442990 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
555 10:11:59.015263 0.0;M3 CHK:0;cm4_sp_mode 0
556 10:11:59.015908 MVN_1=0x00000000
557 10:11:59.020728 MVN_2=0x00000000
558 10:11:59.026338 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
559 10:11:59.026904 OPS=0x10
560 10:11:59.027369 ring efuse init
561 10:11:59.027844 chipver efuse init
562 10:11:59.032057 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
563 10:11:59.037532 [0.018961 Inits done]
564 10:11:59.038056 secure task start!
565 10:11:59.038487 high task start!
566 10:11:59.042234 low task start!
567 10:11:59.042747 run into bl31
568 10:11:59.048772 NOTICE: BL31: v1.3(release):4fc40b1
569 10:11:59.056751 NOTICE: BL31: Built : 15:58:17, May 22 2019
570 10:11:59.057288 NOTICE: BL31: G12A normal boot!
571 10:11:59.082052 NOTICE: BL31: BL33 decompress pass
572 10:11:59.087742 ERROR: Error initializing runtime service opteed_fast
573 10:12:00.320775
574 10:12:00.321427
575 10:12:00.329107 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
576 10:12:00.329657
577 10:12:00.330123 Model: Libre Computer AML-A311D-CC Alta
578 10:12:00.537579 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
579 10:12:00.560920 DRAM: 2 GiB (effective 3.8 GiB)
580 10:12:00.703882 Core: 408 devices, 31 uclasses, devicetree: separate
581 10:12:00.709766 WDT: Not starting watchdog@f0d0
582 10:12:00.742050 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
583 10:12:00.754387 Loading Environment from FAT... Card did not respond to voltage select! : -110
584 10:12:00.759411 ** Bad device specification mmc 0 **
585 10:12:00.769801 Card did not respond to voltage select! : -110
586 10:12:00.777436 ** Bad device specification mmc 0 **
587 10:12:00.777960 Couldn't find partition mmc 0
588 10:12:00.785713 Card did not respond to voltage select! : -110
589 10:12:00.791248 ** Bad device specification mmc 0 **
590 10:12:00.791774 Couldn't find partition mmc 0
591 10:12:00.796399 Error: could not access storage.
592 10:12:01.138849 Net: eth0: ethernet@ff3f0000
593 10:12:01.139454 starting USB...
594 10:12:01.390609 Bus usb@ff500000: Register 3000140 NbrPorts 3
595 10:12:01.391216 Starting the controller
596 10:12:01.397531 USB XHCI 1.10
597 10:12:03.113056 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
598 10:12:03.113710 bl2_stage_init 0x01
599 10:12:03.114172 bl2_stage_init 0x81
600 10:12:03.118669 hw id: 0x0000 - pwm id 0x01
601 10:12:03.119196 bl2_stage_init 0xc1
602 10:12:03.119653 bl2_stage_init 0x02
603 10:12:03.120174
604 10:12:03.124348 L0:00000000
605 10:12:03.124865 L1:20000703
606 10:12:03.125312 L2:00008067
607 10:12:03.125747 L3:14000000
608 10:12:03.127149 B2:00402000
609 10:12:03.127646 B1:e0f83180
610 10:12:03.128127
611 10:12:03.128575 TE: 58159
612 10:12:03.129019
613 10:12:03.138305 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
614 10:12:03.138839
615 10:12:03.139292 Board ID = 1
616 10:12:03.139728 Set A53 clk to 24M
617 10:12:03.140255 Set A73 clk to 24M
618 10:12:03.143830 Set clk81 to 24M
619 10:12:03.144371 A53 clk: 1200 MHz
620 10:12:03.144817 A73 clk: 1200 MHz
621 10:12:03.149340 CLK81: 166.6M
622 10:12:03.149848 smccc: 00012ab4
623 10:12:03.154887 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
624 10:12:03.155396 board id: 1
625 10:12:03.160525 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
626 10:12:03.174271 fw parse done
627 10:12:03.180314 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
628 10:12:03.222959 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
629 10:12:03.233869 PIEI prepare done
630 10:12:03.234389 fastboot data load
631 10:12:03.234843 fastboot data verify
632 10:12:03.239534 verify result: 266
633 10:12:03.245072 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
634 10:12:03.245586 LPDDR4 probe
635 10:12:03.246031 ddr clk to 1584MHz
636 10:12:03.253063 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
637 10:12:03.290329
638 10:12:03.290862 dmc_version 0001
639 10:12:03.297007 Check phy result
640 10:12:03.302852 INFO : End of CA training
641 10:12:03.303358 INFO : End of initialization
642 10:12:03.308511 INFO : Training has run successfully!
643 10:12:03.309017 Check phy result
644 10:12:03.314032 INFO : End of initialization
645 10:12:03.314540 INFO : End of read enable training
646 10:12:03.317356 INFO : End of fine write leveling
647 10:12:03.322880 INFO : End of Write leveling coarse delay
648 10:12:03.328543 INFO : Training has run successfully!
649 10:12:03.329053 Check phy result
650 10:12:03.329498 INFO : End of initialization
651 10:12:03.334094 INFO : End of read dq deskew training
652 10:12:03.339683 INFO : End of MPR read delay center optimization
653 10:12:03.340237 INFO : End of write delay center optimization
654 10:12:03.345340 INFO : End of read delay center optimization
655 10:12:03.350944 INFO : End of max read latency training
656 10:12:03.351452 INFO : Training has run successfully!
657 10:12:03.356496 1D training succeed
658 10:12:03.362503 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
659 10:12:03.410065 Check phy result
660 10:12:03.410601 INFO : End of initialization
661 10:12:03.431773 INFO : End of 2D read delay Voltage center optimization
662 10:12:03.452076 INFO : End of 2D read delay Voltage center optimization
663 10:12:03.504113 INFO : End of 2D write delay Voltage center optimization
664 10:12:03.553466 INFO : End of 2D write delay Voltage center optimization
665 10:12:03.558943 INFO : Training has run successfully!
666 10:12:03.559453
667 10:12:03.559903 channel==0
668 10:12:03.564639 RxClkDly_Margin_A0==88 ps 9
669 10:12:03.565146 TxDqDly_Margin_A0==98 ps 10
670 10:12:03.570246 RxClkDly_Margin_A1==88 ps 9
671 10:12:03.570754 TxDqDly_Margin_A1==98 ps 10
672 10:12:03.571205 TrainedVREFDQ_A0==74
673 10:12:03.575826 TrainedVREFDQ_A1==74
674 10:12:03.576367 VrefDac_Margin_A0==25
675 10:12:03.576814 DeviceVref_Margin_A0==40
676 10:12:03.581525 VrefDac_Margin_A1==25
677 10:12:03.582032 DeviceVref_Margin_A1==40
678 10:12:03.582472
679 10:12:03.582907
680 10:12:03.586931 channel==1
681 10:12:03.587435 RxClkDly_Margin_A0==98 ps 10
682 10:12:03.587876 TxDqDly_Margin_A0==98 ps 10
683 10:12:03.592546 RxClkDly_Margin_A1==88 ps 9
684 10:12:03.593057 TxDqDly_Margin_A1==98 ps 10
685 10:12:03.598223 TrainedVREFDQ_A0==77
686 10:12:03.598731 TrainedVREFDQ_A1==78
687 10:12:03.599175 VrefDac_Margin_A0==22
688 10:12:03.603841 DeviceVref_Margin_A0==37
689 10:12:03.604378 VrefDac_Margin_A1==24
690 10:12:03.609518 DeviceVref_Margin_A1==36
691 10:12:03.610022
692 10:12:03.610463 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
693 10:12:03.614953
694 10:12:03.642964 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000018 00000019 00000017 00000019 00000018 00000019 0000001a 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 0000005f
695 10:12:03.643539 2D training succeed
696 10:12:03.648643 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
697 10:12:03.654091 auto size-- 65535DDR cs0 size: 2048MB
698 10:12:03.654597 DDR cs1 size: 2048MB
699 10:12:03.659698 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
700 10:12:03.660247 cs0 DataBus test pass
701 10:12:03.665357 cs1 DataBus test pass
702 10:12:03.665862 cs0 AddrBus test pass
703 10:12:03.666304 cs1 AddrBus test pass
704 10:12:03.666739
705 10:12:03.670877 100bdlr_step_size ps== 420
706 10:12:03.671392 result report
707 10:12:03.676498 boot times 0Enable ddr reg access
708 10:12:03.681936 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
709 10:12:03.695443 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
710 10:12:04.269110 0.0;M3 CHK:0;cm4_sp_mode 0
711 10:12:04.269760 MVN_1=0x00000000
712 10:12:04.274544 MVN_2=0x00000000
713 10:12:04.280367 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
714 10:12:04.280924 OPS=0x10
715 10:12:04.281369 ring efuse init
716 10:12:04.281790 chipver efuse init
717 10:12:04.285904 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
718 10:12:04.291481 [0.018961 Inits done]
719 10:12:04.291969 secure task start!
720 10:12:04.292448 high task start!
721 10:12:04.296082 low task start!
722 10:12:04.296572 run into bl31
723 10:12:04.302716 NOTICE: BL31: v1.3(release):4fc40b1
724 10:12:04.310564 NOTICE: BL31: Built : 15:58:17, May 22 2019
725 10:12:04.311079 NOTICE: BL31: G12A normal boot!
726 10:12:04.335913 NOTICE: BL31: BL33 decompress pass
727 10:12:04.341604 ERROR: Error initializing runtime service opteed_fast
728 10:12:05.574701
729 10:12:05.575354
730 10:12:05.582928 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
731 10:12:05.583444
732 10:12:05.583898 Model: Libre Computer AML-A311D-CC Alta
733 10:12:05.791365 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
734 10:12:05.814727 DRAM: 2 GiB (effective 3.8 GiB)
735 10:12:05.957799 Core: 408 devices, 31 uclasses, devicetree: separate
736 10:12:05.963678 WDT: Not starting watchdog@f0d0
737 10:12:05.995861 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
738 10:12:06.008273 Loading Environment from FAT... Card did not respond to voltage select! : -110
739 10:12:06.013297 ** Bad device specification mmc 0 **
740 10:12:06.023617 Card did not respond to voltage select! : -110
741 10:12:06.031293 ** Bad device specification mmc 0 **
742 10:12:06.031795 Couldn't find partition mmc 0
743 10:12:06.039619 Card did not respond to voltage select! : -110
744 10:12:06.045127 ** Bad device specification mmc 0 **
745 10:12:06.045627 Couldn't find partition mmc 0
746 10:12:06.050206 Error: could not access storage.
747 10:12:06.393712 Net: eth0: ethernet@ff3f0000
748 10:12:06.394336 starting USB...
749 10:12:06.645544 Bus usb@ff500000: Register 3000140 NbrPorts 3
750 10:12:06.646173 Starting the controller
751 10:12:06.652533 USB XHCI 1.10
752 10:12:08.811419 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
753 10:12:08.812136 bl2_stage_init 0x01
754 10:12:08.812610 bl2_stage_init 0x81
755 10:12:08.817238 hw id: 0x0000 - pwm id 0x01
756 10:12:08.817780 bl2_stage_init 0xc1
757 10:12:08.818232 bl2_stage_init 0x02
758 10:12:08.818671
759 10:12:08.822611 L0:00000000
760 10:12:08.823171 L1:20000703
761 10:12:08.823620 L2:00008067
762 10:12:08.824098 L3:14000000
763 10:12:08.828297 B2:00402000
764 10:12:08.828822 B1:e0f83180
765 10:12:08.829268
766 10:12:08.829712 TE: 58159
767 10:12:08.830145
768 10:12:08.833857 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
769 10:12:08.834386
770 10:12:08.834833 Board ID = 1
771 10:12:08.839476 Set A53 clk to 24M
772 10:12:08.840030 Set A73 clk to 24M
773 10:12:08.840478 Set clk81 to 24M
774 10:12:08.845237 A53 clk: 1200 MHz
775 10:12:08.845766 A73 clk: 1200 MHz
776 10:12:08.846208 CLK81: 166.6M
777 10:12:08.846637 smccc: 00012ab5
778 10:12:08.850651 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
779 10:12:08.856130 board id: 1
780 10:12:08.862308 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
781 10:12:08.872792 fw parse done
782 10:12:08.878718 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
783 10:12:08.921221 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
784 10:12:08.932184 PIEI prepare done
785 10:12:08.932724 fastboot data load
786 10:12:08.933176 fastboot data verify
787 10:12:08.937820 verify result: 266
788 10:12:08.943412 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
789 10:12:08.943942 LPDDR4 probe
790 10:12:08.944439 ddr clk to 1584MHz
791 10:12:08.951426 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
792 10:12:08.988664
793 10:12:08.989228 dmc_version 0001
794 10:12:08.995330 Check phy result
795 10:12:09.001208 INFO : End of CA training
796 10:12:09.001739 INFO : End of initialization
797 10:12:09.006813 INFO : Training has run successfully!
798 10:12:09.007337 Check phy result
799 10:12:09.012392 INFO : End of initialization
800 10:12:09.012914 INFO : End of read enable training
801 10:12:09.018108 INFO : End of fine write leveling
802 10:12:09.023586 INFO : End of Write leveling coarse delay
803 10:12:09.024152 INFO : Training has run successfully!
804 10:12:09.024601 Check phy result
805 10:12:09.029216 INFO : End of initialization
806 10:12:09.029736 INFO : End of read dq deskew training
807 10:12:09.034797 INFO : End of MPR read delay center optimization
808 10:12:09.040396 INFO : End of write delay center optimization
809 10:12:09.046112 INFO : End of read delay center optimization
810 10:12:09.046646 INFO : End of max read latency training
811 10:12:09.051619 INFO : Training has run successfully!
812 10:12:09.052177 1D training succeed
813 10:12:09.060726 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
814 10:12:09.108392 Check phy result
815 10:12:09.108963 INFO : End of initialization
816 10:12:09.130268 INFO : End of 2D read delay Voltage center optimization
817 10:12:09.150406 INFO : End of 2D read delay Voltage center optimization
818 10:12:09.202429 INFO : End of 2D write delay Voltage center optimization
819 10:12:09.251813 INFO : End of 2D write delay Voltage center optimization
820 10:12:09.257376 INFO : Training has run successfully!
821 10:12:09.257905
822 10:12:09.258359 channel==0
823 10:12:09.263019 RxClkDly_Margin_A0==88 ps 9
824 10:12:09.263537 TxDqDly_Margin_A0==98 ps 10
825 10:12:09.268585 RxClkDly_Margin_A1==88 ps 9
826 10:12:09.269191 TxDqDly_Margin_A1==98 ps 10
827 10:12:09.269666 TrainedVREFDQ_A0==74
828 10:12:09.274304 TrainedVREFDQ_A1==74
829 10:12:09.274894 VrefDac_Margin_A0==25
830 10:12:09.275324 DeviceVref_Margin_A0==40
831 10:12:09.280163 VrefDac_Margin_A1==25
832 10:12:09.280513 DeviceVref_Margin_A1==40
833 10:12:09.280733
834 10:12:09.280941
835 10:12:09.285314 channel==1
836 10:12:09.285648 RxClkDly_Margin_A0==98 ps 10
837 10:12:09.285873 TxDqDly_Margin_A0==98 ps 10
838 10:12:09.290899 RxClkDly_Margin_A1==88 ps 9
839 10:12:09.291225 TxDqDly_Margin_A1==88 ps 9
840 10:12:09.296426 TrainedVREFDQ_A0==77
841 10:12:09.296753 TrainedVREFDQ_A1==77
842 10:12:09.296972 VrefDac_Margin_A0==22
843 10:12:09.302042 DeviceVref_Margin_A0==37
844 10:12:09.302375 VrefDac_Margin_A1==24
845 10:12:09.307635 DeviceVref_Margin_A1==37
846 10:12:09.307973
847 10:12:09.308230 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
848 10:12:09.308441
849 10:12:09.341210 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000018 00000015 00000017 00000019 00000018 00000019 00000018 0000001a 0000001a 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
850 10:12:09.341626 2D training succeed
851 10:12:09.346866 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
852 10:12:09.352389 auto size-- 65535DDR cs0 size: 2048MB
853 10:12:09.352710 DDR cs1 size: 2048MB
854 10:12:09.358035 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
855 10:12:09.358361 cs0 DataBus test pass
856 10:12:09.363639 cs1 DataBus test pass
857 10:12:09.363968 cs0 AddrBus test pass
858 10:12:09.364234 cs1 AddrBus test pass
859 10:12:09.364450
860 10:12:09.369227 100bdlr_step_size ps== 420
861 10:12:09.369579 result report
862 10:12:09.374887 boot times 0Enable ddr reg access
863 10:12:09.380204 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
864 10:12:09.393675 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
865 10:12:09.967453 0.0;M3 CHK:0;cm4_sp_mode 0
866 10:12:09.967880 MVN_1=0x00000000
867 10:12:09.972867 MVN_2=0x00000000
868 10:12:09.978593 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
869 10:12:09.979052 OPS=0x10
870 10:12:09.979461 ring efuse init
871 10:12:09.979856 chipver efuse init
872 10:12:09.984205 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
873 10:12:09.989783 [0.018961 Inits done]
874 10:12:09.990216 secure task start!
875 10:12:09.990619 high task start!
876 10:12:09.994351 low task start!
877 10:12:09.994787 run into bl31
878 10:12:10.001110 NOTICE: BL31: v1.3(release):4fc40b1
879 10:12:10.008841 NOTICE: BL31: Built : 15:58:17, May 22 2019
880 10:12:10.009283 NOTICE: BL31: G12A normal boot!
881 10:12:10.034753 NOTICE: BL31: BL33 decompress pass
882 10:12:10.040444 ERROR: Error initializing runtime service opteed_fast
883 10:12:11.273515
884 10:12:11.273946
885 10:12:11.281685 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
886 10:12:11.282112
887 10:12:11.282454 Model: Libre Computer AML-A311D-CC Alta
888 10:12:11.490145 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
889 10:12:11.513527 DRAM: 2 GiB (effective 3.8 GiB)
890 10:12:11.656506 Core: 408 devices, 31 uclasses, devicetree: separate
891 10:12:11.662390 WDT: Not starting watchdog@f0d0
892 10:12:11.695131 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
893 10:12:11.707264 Loading Environment from FAT... Card did not respond to voltage select! : -110
894 10:12:11.712259 ** Bad device specification mmc 0 **
895 10:12:11.722423 Card did not respond to voltage select! : -110
896 10:12:11.730041 ** Bad device specification mmc 0 **
897 10:12:11.730353 Couldn't find partition mmc 0
898 10:12:11.738341 Card did not respond to voltage select! : -110
899 10:12:11.743869 ** Bad device specification mmc 0 **
900 10:12:11.744322 Couldn't find partition mmc 0
901 10:12:11.748909 Error: could not access storage.
902 10:12:12.092522 Net: eth0: ethernet@ff3f0000
903 10:12:12.092948 starting USB...
904 10:12:12.344433 Bus usb@ff500000: Register 3000140 NbrPorts 3
905 10:12:12.345050 Starting the controller
906 10:12:12.351329 USB XHCI 1.10
907 10:12:13.905385 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
908 10:12:13.913628 scanning usb for storage devices... 0 Storage Device(s) found
910 10:12:13.965077 Hit any key to stop autoboot: 1
911 10:12:13.965841 end: 2.4.2 bootloader-interrupt (duration 00:00:31) [common]
912 10:12:13.966423 start: 2.4.3 bootloader-commands (timeout 00:04:29) [common]
913 10:12:13.966881 Setting prompt string to ['=>']
914 10:12:13.967343 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:29)
915 10:12:13.981278 0
916 10:12:13.982133 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
917 10:12:13.982617 Sending with 10 millisecond of delay
919 10:12:15.117743 => setenv autoload no
920 10:12:15.128585 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:28)
921 10:12:15.131417 setenv autoload no
922 10:12:15.131913 Sending with 10 millisecond of delay
924 10:12:16.930517 => setenv initrd_high 0xffffffff
925 10:12:16.941360 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:26)
926 10:12:16.942255 setenv initrd_high 0xffffffff
927 10:12:16.943012 Sending with 10 millisecond of delay
929 10:12:18.559399 => setenv fdt_high 0xffffffff
930 10:12:18.570265 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:24)
931 10:12:18.571119 setenv fdt_high 0xffffffff
932 10:12:18.571871 Sending with 10 millisecond of delay
934 10:12:18.863745 => dhcp
935 10:12:18.874508 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:24)
936 10:12:18.875349 dhcp
937 10:12:18.875812 Speed: 1000, full duplex
938 10:12:18.876294 BOOTP broadcast 1
939 10:12:18.882660 DHCP client bound to address 192.168.6.27 (8 ms)
940 10:12:18.883388 Sending with 10 millisecond of delay
942 10:12:20.559777 => setenv serverip 192.168.6.2
943 10:12:20.570633 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:22)
944 10:12:20.571561 setenv serverip 192.168.6.2
945 10:12:20.572327 Sending with 10 millisecond of delay
947 10:12:24.296209 => tftpboot 0x01080000 921981/tftp-deploy-ghypho9e/kernel/uImage
948 10:12:24.306973 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
949 10:12:24.307782 tftpboot 0x01080000 921981/tftp-deploy-ghypho9e/kernel/uImage
950 10:12:24.308306 Speed: 1000, full duplex
951 10:12:24.308718 Using ethernet@ff3f0000 device
952 10:12:24.309708 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
953 10:12:24.315269 Filename '921981/tftp-deploy-ghypho9e/kernel/uImage'.
954 10:12:24.318481 Load address: 0x1080000
955 10:12:24.323599 Loading: * UDP wrong checksum 000000ff 0000adb2
956 10:12:24.344857 UDP wrong checksum 000000ff 000049a5
957 10:12:27.439461 ################################################## 43.8 MiB
958 10:12:27.440126 14 MiB/s
959 10:12:27.440570 done
960 10:12:27.443587 Bytes transferred = 45908544 (2bc8240 hex)
961 10:12:27.444479 Sending with 10 millisecond of delay
963 10:12:32.132300 => tftpboot 0x08000000 921981/tftp-deploy-ghypho9e/ramdisk/ramdisk.cpio.gz.uboot
964 10:12:32.143125 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:10)
965 10:12:32.144019 tftpboot 0x08000000 921981/tftp-deploy-ghypho9e/ramdisk/ramdisk.cpio.gz.uboot
966 10:12:32.144514 Speed: 1000, full duplex
967 10:12:32.144963 Using ethernet@ff3f0000 device
968 10:12:32.145766 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
969 10:12:32.157712 Filename '921981/tftp-deploy-ghypho9e/ramdisk/ramdisk.cpio.gz.uboot'.
970 10:12:32.158249 Load address: 0x8000000
971 10:12:36.916328 Loading: *#### UDP wrong checksum 000000ff 0000154f
972 10:12:36.959211 UDP wrong checksum 000000ff 0000ae41
973 10:12:41.396448 T ############################################# UDP wrong checksum 0000000f 00008e36
974 10:12:46.397491 T UDP wrong checksum 0000000f 00008e36
975 10:12:56.399395 T T UDP wrong checksum 0000000f 00008e36
976 10:13:16.403457 T T T T UDP wrong checksum 0000000f 00008e36
977 10:13:31.407605 T T
978 10:13:31.408079 Retry count exceeded; starting again
980 10:13:31.408927 end: 2.4.3 bootloader-commands (duration 00:01:17) [common]
983 10:13:31.409845 end: 2.4 uboot-commands (duration 00:01:49) [common]
985 10:13:31.410517 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
987 10:13:31.411045 end: 2 uboot-action (duration 00:01:49) [common]
989 10:13:31.411886 Cleaning after the job
990 10:13:31.412242 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/921981/tftp-deploy-ghypho9e/ramdisk
991 10:13:31.413062 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/921981/tftp-deploy-ghypho9e/kernel
992 10:13:31.417204 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/921981/tftp-deploy-ghypho9e/dtb
993 10:13:31.417973 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/921981/tftp-deploy-ghypho9e/modules
994 10:13:31.421319 start: 4.1 power-off (timeout 00:00:30) [common]
995 10:13:31.421880 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
996 10:13:31.456354 >> OK - accepted request
997 10:13:31.458690 Returned 0 in 0 seconds
998 10:13:31.560146 end: 4.1 power-off (duration 00:00:00) [common]
1000 10:13:31.562018 start: 4.2 read-feedback (timeout 00:10:00) [common]
1001 10:13:31.563629 Listened to connection for namespace 'common' for up to 1s
1002 10:13:32.564140 Finalising connection for namespace 'common'
1003 10:13:32.564970 Disconnecting from shell: Finalise
1004 10:13:32.565571 =>
1005 10:13:32.666580 end: 4.2 read-feedback (duration 00:00:01) [common]
1006 10:13:32.667285 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/921981
1007 10:13:33.219344 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/921981
1008 10:13:33.219999 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.