[ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x000f0510] [ 0.000000] Linux version 6.12.0-rc5-next-20241101 (KernelCI@build-j358953-arm64-gcc-12-defconfig-4x8l9) (aarch64-linux-gnu-gcc (Debian 12.2.0-14) 12.2.0, GNU ld (GNU Binutils for Debian) 2.40) #1 SMP PREEMPT Fri Nov 1 09:03:28 UTC 2024 [ 0.000000] KASLR enabled [ 0.000000] random: crng init done [ 0.000000] Machine model: linux,dummy-virt [ 0.000000] efi: UEFI not found. [ 0.000000] earlycon: pl11 at MMIO 0x0000000009000000 (options '') [ 0.000000] printk: legacy bootconsole [pl11] enabled [ 0.000000] OF: reserved mem: Reserved memory: No reserved-memory node in the DT [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000007fffffff] [ 0.000000] NODE_DATA(0) allocated [mem 0x7fdfcb00-0x7fdff13f] [ 0.000000] Zone ranges: [ 0.000000] DMA [mem 0x0000000040000000-0x000000007fffffff] [ 0.000000] DMA32 empty [ 0.000000] Normal empty [ 0.000000] Movable zone start for each node [ 0.000000] Early memory node ranges [ 0.000000] node 0: [mem 0x0000000040000000-0x000000007fffffff] [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000007fffffff] [ 0.000000] cma: Reserved 32 MiB at 0x000000007cc00000 on node -1 [ 0.000000] psci: probing for conduit method from DT. [ 0.000000] psci: PSCIv1.1 detected in firmware. [ 0.000000] psci: Using standard PSCI v0.2 function IDs [ 0.000000] psci: Trusted OS migration not required [ 0.000000] psci: SMC Calling Convention v1.0 [ 0.000000] percpu: Embedded 24 pages/cpu s61336 r8192 d28776 u98304 [ 0.000000] Detected PIPT I-cache on CPU0 [ 0.000000] CPU features: detected: Address authentication (IMP DEF algorithm) [ 0.000000] CPU features: detected: GIC system register CPU interface [ 0.000000] CPU features: detected: HCRX_EL2 register [ 0.000000] CPU features: detected: 52-bit Virtual Addressing (LPA2) [ 0.000000] CPU features: detected: Memory Tagging Extension [ 0.000000] CPU features: detected: Asymmetric MTE Tag Check Fault [ 0.000000] CPU features: detected: Spectre-v4 [ 0.000000] alternatives: applying boot alternatives [ 0.000000] Kernel command line: console=ttyAMA0,115200 root=/dev/ram0 verbose console_msg_format=syslog earlycon deferred_probe_timeout=60 <5>[ 0.000000] Unknown kernel command line parameters "verbose", will be passed to user space. <6>[ 0.000000] printk: log buffer data + meta data: 131072 + 458752 = 589824 bytes <6>[ 0.000000] Dentry cache hash table entries: 131072 (order: 8, 1048576 bytes, linear) <6>[ 0.000000] Inode-cache hash table entries: 65536 (order: 7, 524288 bytes, linear) <6>[ 0.000000] Fallback order for Node 0: 0 <6>[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 262144 <6>[ 0.000000] Policy zone: DMA <6>[ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off <6>[ 0.000000] software IO TLB: SWIOTLB bounce buffer size adjusted to 1MB <6>[ 0.000000] software IO TLB: area num 1. <6>[ 0.000000] software IO TLB: mapped [mem 0x000000007ca00000-0x000000007cb00000] (1MB) <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation. <6>[ 0.000000] rcu: RCU event tracing is enabled. <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=512 to nr_cpu_ids=1. <6>[ 0.000000] Trampoline variant of Tasks RCU enabled. <6>[ 0.000000] Tracing variant of Tasks RCU enabled. <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies. <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=1 <6>[ 0.000000] RCU Tasks: Setting shift to 0 and lim to 1 rcu_task_cb_adjust=1 rcu_task_cpu_ids=1. <6>[ 0.000000] RCU Tasks Trace: Setting shift to 0 and lim to 1 rcu_task_cb_adjust=1 rcu_task_cpu_ids=1. <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0 <6>[ 0.000000] GICv3: 256 SPIs implemented <6>[ 0.000000] GICv3: 0 Extended SPIs implemented <6>[ 0.000000] Root IRQ handler: gic_handle_irq <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs <6>[ 0.000000] GICv3: GICD_CTRL.DS=1, SCR_EL3.FIQ=0 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x00000000080a0000 <6>[ 0.000000] ITS [mem 0x08080000-0x0809ffff] <6>[ 0.000000] ITS@0x0000000008080000: allocated 8192 Devices @43040000 (indirect, esz 8, psz 64K, shr 1) <6>[ 0.000000] ITS@0x0000000008080000: allocated 8192 Interrupt Collections @43050000 (flat, esz 8, psz 64K, shr 1) <6>[ 0.000000] GICv3: using LPI property table @0x0000000043060000 <6>[ 0.000000] GICv3: CPU0: using allocated LPI pending table @0x0000000043070000 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention. <6>[ 0.000000] arch_timer: cp15 timer(s) running at 62.50MHz (virt). <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0x1ffffffffffffff max_cycles: 0x1cd42e208c, max_idle_ns: 881590405314 ns <6>[ 0.000083] sched_clock: 57 bits at 63MHz, resolution 16ns, wraps every 4398046511096ns <6>[ 0.018557] Console: colour dummy device 80x25 <6>[ 0.026040] Calibrating delay loop (skipped), value calculated using timer frequency.. 125.00 BogoMIPS (lpj=250000) <6>[ 0.027226] pid_max: default: 32768 minimum: 301 <6>[ 0.029738] LSM: initializing lsm=capability <6>[ 0.034184] Mount-cache hash table entries: 2048 (order: 2, 16384 bytes, linear) <6>[ 0.034691] Mountpoint-cache hash table entries: 2048 (order: 2, 16384 bytes, linear) <4>[ 0.071945] cacheinfo: Unable to detect cache hierarchy for CPU 0 <6>[ 0.086316] rcu: Hierarchical SRCU implementation. <6>[ 0.086549] rcu: Max phase no-delay instances is 1000. <6>[ 0.093907] fsl-mc MSI: its@8080000 domain created <6>[ 0.097280] EFI services will not be available. <6>[ 0.098383] smp: Bringing up secondary CPUs ... <6>[ 0.099547] smp: Brought up 1 node, 1 CPU <6>[ 0.099767] SMP: Total of 1 processors activated. <6>[ 0.100006] CPU: All CPU(s) started at EL1 <6>[ 0.100569] CPU features: detected: Branch Target Identification <6>[ 0.100876] CPU features: detected: 32-bit EL0 Support <6>[ 0.101335] CPU features: detected: 32-bit EL1 Support <6>[ 0.101551] CPU features: detected: ARMv8.4 Translation Table Level <6>[ 0.101822] CPU features: detected: Instruction cache invalidation not required for I/D coherence <6>[ 0.102191] CPU features: detected: Data cache clean to the PoU not required for I/D coherence <6>[ 0.102574] CPU features: detected: Common not Private translations <6>[ 0.102810] CPU features: detected: CRC32 instructions <6>[ 0.103017] CPU features: detected: Data independent timing control (DIT) <6>[ 0.103268] CPU features: detected: E0PD <6>[ 0.103409] CPU features: detected: Enhanced Counter Virtualization <6>[ 0.103701] CPU features: detected: Enhanced Counter Virtualization (CNTPOFF) <6>[ 0.104048] CPU features: detected: Enhanced Privileged Access Never <6>[ 0.104301] CPU features: detected: Enhanced Virtualization Traps <6>[ 0.104560] CPU features: detected: Fine Grained Traps <6>[ 0.104873] CPU features: detected: Generic authentication (IMP DEF algorithm) <6>[ 0.105430] CPU features: detected: RCpc load-acquire (LDAPR) <6>[ 0.105740] CPU features: detected: 52-bit Virtual Addressing for KVM (LPA2) <6>[ 0.106061] CPU features: detected: LSE atomic instructions <6>[ 0.106341] CPU features: detected: Memory Copy and Memory Set instructions <6>[ 0.106654] CPU features: detected: Privileged Access Never <6>[ 0.106913] CPU features: detected: RAS Extension Support <6>[ 0.107219] CPU features: detected: Random Number Generator <6>[ 0.107508] CPU features: detected: Speculation barrier (SB) <6>[ 0.107804] CPU features: detected: Stage-2 Force Write-Back <6>[ 0.108086] CPU features: detected: Trap EL0 IMPLEMENTATION DEFINED functionality <6>[ 0.108416] CPU features: detected: TLB range maintenance instructions <6>[ 0.108838] CPU features: detected: Scalable Matrix Extension <6>[ 0.109124] CPU features: detected: FA64 <6>[ 0.109509] CPU features: detected: Speculative Store Bypassing Safe (SSBS) <6>[ 0.109797] CPU features: detected: Scalable Vector Extension <6>[ 0.119566] alternatives: applying system-wide alternatives <6>[ 0.134570] CPU features: detected: Hardware dirty bit management on CPU0 <6>[ 0.135755] SVE: maximum available vector length 256 bytes per vector <6>[ 0.136082] SVE: default vector length 64 bytes per vector <6>[ 0.137989] SME: minimum available vector length 16 bytes per vector <6>[ 0.139568] SME: maximum available vector length 256 bytes per vector <6>[ 0.139846] SME: default vector length 32 bytes per vector ** ERROR:target/arm/internals.h:923:regime_is_user: code should not be reached Bail out! ERROR:target/arm/internals.h:923:regime_is_user: code should not be reached