Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 09:49:21.952354 lava-dispatcher, installed at version: 2024.01
2 09:49:21.953136 start: 0 validate
3 09:49:21.953620 Start time: 2024-11-01 09:49:21.953591+00:00 (UTC)
4 09:49:21.954147 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 09:49:21.954696 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-gst-fluster%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 09:49:21.994793 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 09:49:21.995328 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241101%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 09:49:22.025801 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 09:49:22.026409 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241101%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 09:49:22.059239 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 09:49:22.059725 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-gst-fluster%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 09:49:22.092687 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 09:49:22.093164 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241101%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
14 09:49:22.131746 validate duration: 0.18
16 09:49:22.132624 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 09:49:22.132947 start: 1.1 download-retry (timeout 00:10:00) [common]
18 09:49:22.133262 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 09:49:22.134061 Not decompressing ramdisk as can be used compressed.
20 09:49:22.134884 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-gst-fluster/20240313.0/arm64/initrd.cpio.gz
21 09:49:22.135420 saving as /var/lib/lava/dispatcher/tmp/921925/tftp-deploy-m284d0us/ramdisk/initrd.cpio.gz
22 09:49:22.135954 total size: 5628140 (5 MB)
23 09:49:22.179806 progress 0 % (0 MB)
24 09:49:22.188548 progress 5 % (0 MB)
25 09:49:22.197662 progress 10 % (0 MB)
26 09:49:22.205783 progress 15 % (0 MB)
27 09:49:22.213135 progress 20 % (1 MB)
28 09:49:22.217029 progress 25 % (1 MB)
29 09:49:22.221277 progress 30 % (1 MB)
30 09:49:22.225550 progress 35 % (1 MB)
31 09:49:22.229321 progress 40 % (2 MB)
32 09:49:22.233474 progress 45 % (2 MB)
33 09:49:22.237196 progress 50 % (2 MB)
34 09:49:22.241265 progress 55 % (2 MB)
35 09:49:22.245375 progress 60 % (3 MB)
36 09:49:22.249028 progress 65 % (3 MB)
37 09:49:22.253229 progress 70 % (3 MB)
38 09:49:22.256826 progress 75 % (4 MB)
39 09:49:22.260897 progress 80 % (4 MB)
40 09:49:22.264587 progress 85 % (4 MB)
41 09:49:22.268556 progress 90 % (4 MB)
42 09:49:22.272565 progress 95 % (5 MB)
43 09:49:22.275848 progress 100 % (5 MB)
44 09:49:22.276526 5 MB downloaded in 0.14 s (38.18 MB/s)
45 09:49:22.277092 end: 1.1.1 http-download (duration 00:00:00) [common]
47 09:49:22.278006 end: 1.1 download-retry (duration 00:00:00) [common]
48 09:49:22.278303 start: 1.2 download-retry (timeout 00:10:00) [common]
49 09:49:22.278580 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 09:49:22.279206 downloading http://storage.kernelci.org/next/master/next-20241101/arm64/defconfig/gcc-12/kernel/Image
51 09:49:22.279505 saving as /var/lib/lava/dispatcher/tmp/921925/tftp-deploy-m284d0us/kernel/Image
52 09:49:22.279735 total size: 45908480 (43 MB)
53 09:49:22.279963 No compression specified
54 09:49:22.318347 progress 0 % (0 MB)
55 09:49:22.346725 progress 5 % (2 MB)
56 09:49:22.374617 progress 10 % (4 MB)
57 09:49:22.402412 progress 15 % (6 MB)
58 09:49:22.430396 progress 20 % (8 MB)
59 09:49:22.458030 progress 25 % (10 MB)
60 09:49:22.485295 progress 30 % (13 MB)
61 09:49:22.512582 progress 35 % (15 MB)
62 09:49:22.540339 progress 40 % (17 MB)
63 09:49:22.567931 progress 45 % (19 MB)
64 09:49:22.595755 progress 50 % (21 MB)
65 09:49:22.623826 progress 55 % (24 MB)
66 09:49:22.651552 progress 60 % (26 MB)
67 09:49:22.681568 progress 65 % (28 MB)
68 09:49:22.709233 progress 70 % (30 MB)
69 09:49:22.736903 progress 75 % (32 MB)
70 09:49:22.764401 progress 80 % (35 MB)
71 09:49:22.792211 progress 85 % (37 MB)
72 09:49:22.819785 progress 90 % (39 MB)
73 09:49:22.847437 progress 95 % (41 MB)
74 09:49:22.875137 progress 100 % (43 MB)
75 09:49:22.875654 43 MB downloaded in 0.60 s (73.47 MB/s)
76 09:49:22.876175 end: 1.2.1 http-download (duration 00:00:01) [common]
78 09:49:22.877028 end: 1.2 download-retry (duration 00:00:01) [common]
79 09:49:22.877313 start: 1.3 download-retry (timeout 00:09:59) [common]
80 09:49:22.877590 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 09:49:22.878084 downloading http://storage.kernelci.org/next/master/next-20241101/arm64/defconfig/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
82 09:49:22.878371 saving as /var/lib/lava/dispatcher/tmp/921925/tftp-deploy-m284d0us/dtb/meson-g12b-a311d-libretech-cc.dtb
83 09:49:22.878587 total size: 54703 (0 MB)
84 09:49:22.878800 No compression specified
85 09:49:22.922187 progress 59 % (0 MB)
86 09:49:22.923050 progress 100 % (0 MB)
87 09:49:22.923616 0 MB downloaded in 0.05 s (1.16 MB/s)
88 09:49:22.924124 end: 1.3.1 http-download (duration 00:00:00) [common]
90 09:49:22.924972 end: 1.3 download-retry (duration 00:00:00) [common]
91 09:49:22.925241 start: 1.4 download-retry (timeout 00:09:59) [common]
92 09:49:22.925513 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 09:49:22.925972 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-gst-fluster/20240313.0/arm64/full.rootfs.tar.xz
94 09:49:22.926252 saving as /var/lib/lava/dispatcher/tmp/921925/tftp-deploy-m284d0us/nfsrootfs/full.rootfs.tar
95 09:49:22.926463 total size: 474398908 (452 MB)
96 09:49:22.926677 Using unxz to decompress xz
97 09:49:22.964459 progress 0 % (0 MB)
98 09:49:24.058765 progress 5 % (22 MB)
99 09:49:25.533103 progress 10 % (45 MB)
100 09:49:25.978151 progress 15 % (67 MB)
101 09:49:26.800758 progress 20 % (90 MB)
102 09:49:27.309431 progress 25 % (113 MB)
103 09:49:27.661983 progress 30 % (135 MB)
104 09:49:28.262222 progress 35 % (158 MB)
105 09:49:29.152636 progress 40 % (181 MB)
106 09:49:29.876086 progress 45 % (203 MB)
107 09:49:30.419399 progress 50 % (226 MB)
108 09:49:31.060097 progress 55 % (248 MB)
109 09:49:32.339559 progress 60 % (271 MB)
110 09:49:33.833082 progress 65 % (294 MB)
111 09:49:35.477164 progress 70 % (316 MB)
112 09:49:38.573622 progress 75 % (339 MB)
113 09:49:41.004843 progress 80 % (361 MB)
114 09:49:43.987658 progress 85 % (384 MB)
115 09:49:47.639852 progress 90 % (407 MB)
116 09:49:50.837036 progress 95 % (429 MB)
117 09:49:54.075464 progress 100 % (452 MB)
118 09:49:54.088617 452 MB downloaded in 31.16 s (14.52 MB/s)
119 09:49:54.089612 end: 1.4.1 http-download (duration 00:00:31) [common]
121 09:49:54.091444 end: 1.4 download-retry (duration 00:00:31) [common]
122 09:49:54.092077 start: 1.5 download-retry (timeout 00:09:28) [common]
123 09:49:54.092688 start: 1.5.1 http-download (timeout 00:09:28) [common]
124 09:49:54.093715 downloading http://storage.kernelci.org/next/master/next-20241101/arm64/defconfig/gcc-12/modules.tar.xz
125 09:49:54.094249 saving as /var/lib/lava/dispatcher/tmp/921925/tftp-deploy-m284d0us/modules/modules.tar
126 09:49:54.094721 total size: 11594840 (11 MB)
127 09:49:54.095207 Using unxz to decompress xz
128 09:49:54.145272 progress 0 % (0 MB)
129 09:49:54.212400 progress 5 % (0 MB)
130 09:49:54.286190 progress 10 % (1 MB)
131 09:49:54.366007 progress 15 % (1 MB)
132 09:49:54.441889 progress 20 % (2 MB)
133 09:49:54.517263 progress 25 % (2 MB)
134 09:49:54.596440 progress 30 % (3 MB)
135 09:49:54.668376 progress 35 % (3 MB)
136 09:49:54.747392 progress 40 % (4 MB)
137 09:49:54.832546 progress 45 % (5 MB)
138 09:49:54.908563 progress 50 % (5 MB)
139 09:49:54.991116 progress 55 % (6 MB)
140 09:49:55.071055 progress 60 % (6 MB)
141 09:49:55.154162 progress 65 % (7 MB)
142 09:49:55.228603 progress 70 % (7 MB)
143 09:49:55.311914 progress 75 % (8 MB)
144 09:49:55.393177 progress 80 % (8 MB)
145 09:49:55.468206 progress 85 % (9 MB)
146 09:49:55.541539 progress 90 % (9 MB)
147 09:49:55.644235 progress 95 % (10 MB)
148 09:49:55.736923 progress 100 % (11 MB)
149 09:49:55.751226 11 MB downloaded in 1.66 s (6.68 MB/s)
150 09:49:55.752222 end: 1.5.1 http-download (duration 00:00:02) [common]
152 09:49:55.754470 end: 1.5 download-retry (duration 00:00:02) [common]
153 09:49:55.755296 start: 1.6 prepare-tftp-overlay (timeout 00:09:26) [common]
154 09:49:55.756021 start: 1.6.1 extract-nfsrootfs (timeout 00:09:26) [common]
155 09:50:12.097080 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/921925/extract-nfsrootfs-oy6kac8l
156 09:50:12.097692 end: 1.6.1 extract-nfsrootfs (duration 00:00:16) [common]
157 09:50:12.097981 start: 1.6.2 lava-overlay (timeout 00:09:10) [common]
158 09:50:12.098579 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/921925/lava-overlay-bun2vxv6
159 09:50:12.099015 makedir: /var/lib/lava/dispatcher/tmp/921925/lava-overlay-bun2vxv6/lava-921925/bin
160 09:50:12.099389 makedir: /var/lib/lava/dispatcher/tmp/921925/lava-overlay-bun2vxv6/lava-921925/tests
161 09:50:12.099722 makedir: /var/lib/lava/dispatcher/tmp/921925/lava-overlay-bun2vxv6/lava-921925/results
162 09:50:12.100095 Creating /var/lib/lava/dispatcher/tmp/921925/lava-overlay-bun2vxv6/lava-921925/bin/lava-add-keys
163 09:50:12.100675 Creating /var/lib/lava/dispatcher/tmp/921925/lava-overlay-bun2vxv6/lava-921925/bin/lava-add-sources
164 09:50:12.102369 Creating /var/lib/lava/dispatcher/tmp/921925/lava-overlay-bun2vxv6/lava-921925/bin/lava-background-process-start
165 09:50:12.103343 Creating /var/lib/lava/dispatcher/tmp/921925/lava-overlay-bun2vxv6/lava-921925/bin/lava-background-process-stop
166 09:50:12.103962 Creating /var/lib/lava/dispatcher/tmp/921925/lava-overlay-bun2vxv6/lava-921925/bin/lava-common-functions
167 09:50:12.104821 Creating /var/lib/lava/dispatcher/tmp/921925/lava-overlay-bun2vxv6/lava-921925/bin/lava-echo-ipv4
168 09:50:12.105531 Creating /var/lib/lava/dispatcher/tmp/921925/lava-overlay-bun2vxv6/lava-921925/bin/lava-install-packages
169 09:50:12.106189 Creating /var/lib/lava/dispatcher/tmp/921925/lava-overlay-bun2vxv6/lava-921925/bin/lava-installed-packages
170 09:50:12.106780 Creating /var/lib/lava/dispatcher/tmp/921925/lava-overlay-bun2vxv6/lava-921925/bin/lava-os-build
171 09:50:12.107349 Creating /var/lib/lava/dispatcher/tmp/921925/lava-overlay-bun2vxv6/lava-921925/bin/lava-probe-channel
172 09:50:12.108606 Creating /var/lib/lava/dispatcher/tmp/921925/lava-overlay-bun2vxv6/lava-921925/bin/lava-probe-ip
173 09:50:12.109291 Creating /var/lib/lava/dispatcher/tmp/921925/lava-overlay-bun2vxv6/lava-921925/bin/lava-target-ip
174 09:50:12.109871 Creating /var/lib/lava/dispatcher/tmp/921925/lava-overlay-bun2vxv6/lava-921925/bin/lava-target-mac
175 09:50:12.110779 Creating /var/lib/lava/dispatcher/tmp/921925/lava-overlay-bun2vxv6/lava-921925/bin/lava-target-storage
176 09:50:12.111690 Creating /var/lib/lava/dispatcher/tmp/921925/lava-overlay-bun2vxv6/lava-921925/bin/lava-test-case
177 09:50:12.112474 Creating /var/lib/lava/dispatcher/tmp/921925/lava-overlay-bun2vxv6/lava-921925/bin/lava-test-event
178 09:50:12.113144 Creating /var/lib/lava/dispatcher/tmp/921925/lava-overlay-bun2vxv6/lava-921925/bin/lava-test-feedback
179 09:50:12.113714 Creating /var/lib/lava/dispatcher/tmp/921925/lava-overlay-bun2vxv6/lava-921925/bin/lava-test-raise
180 09:50:12.114701 Creating /var/lib/lava/dispatcher/tmp/921925/lava-overlay-bun2vxv6/lava-921925/bin/lava-test-reference
181 09:50:12.115450 Creating /var/lib/lava/dispatcher/tmp/921925/lava-overlay-bun2vxv6/lava-921925/bin/lava-test-runner
182 09:50:12.116063 Creating /var/lib/lava/dispatcher/tmp/921925/lava-overlay-bun2vxv6/lava-921925/bin/lava-test-set
183 09:50:12.116656 Creating /var/lib/lava/dispatcher/tmp/921925/lava-overlay-bun2vxv6/lava-921925/bin/lava-test-shell
184 09:50:12.117239 Updating /var/lib/lava/dispatcher/tmp/921925/lava-overlay-bun2vxv6/lava-921925/bin/lava-install-packages (oe)
185 09:50:12.118009 Updating /var/lib/lava/dispatcher/tmp/921925/lava-overlay-bun2vxv6/lava-921925/bin/lava-installed-packages (oe)
186 09:50:12.118641 Creating /var/lib/lava/dispatcher/tmp/921925/lava-overlay-bun2vxv6/lava-921925/environment
187 09:50:12.119124 LAVA metadata
188 09:50:12.119432 - LAVA_JOB_ID=921925
189 09:50:12.119677 - LAVA_DISPATCHER_IP=192.168.6.2
190 09:50:12.120108 start: 1.6.2.1 ssh-authorize (timeout 00:09:10) [common]
191 09:50:12.121731 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
192 09:50:12.122128 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:10) [common]
193 09:50:12.122378 skipped lava-vland-overlay
194 09:50:12.122651 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
195 09:50:12.122942 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:10) [common]
196 09:50:12.123198 skipped lava-multinode-overlay
197 09:50:12.123473 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
198 09:50:12.123757 start: 1.6.2.4 test-definition (timeout 00:09:10) [common]
199 09:50:12.124077 Loading test definitions
200 09:50:12.124431 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:10) [common]
201 09:50:12.124697 Using /lava-921925 at stage 0
202 09:50:12.126767 uuid=921925_1.6.2.4.1 testdef=None
203 09:50:12.127156 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
204 09:50:12.127484 start: 1.6.2.4.2 test-overlay (timeout 00:09:10) [common]
205 09:50:12.129503 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
207 09:50:12.130446 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:10) [common]
208 09:50:12.133766 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
210 09:50:12.134781 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:10) [common]
211 09:50:12.137712 runner path: /var/lib/lava/dispatcher/tmp/921925/lava-overlay-bun2vxv6/lava-921925/0/tests/0_v4l2-decoder-conformance-vp9 test_uuid 921925_1.6.2.4.1
212 09:50:12.138483 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
214 09:50:12.139373 Creating lava-test-runner.conf files
215 09:50:12.139733 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/921925/lava-overlay-bun2vxv6/lava-921925/0 for stage 0
216 09:50:12.144160 - 0_v4l2-decoder-conformance-vp9
217 09:50:12.144636 end: 1.6.2.4 test-definition (duration 00:00:00) [common]
218 09:50:12.144968 start: 1.6.2.5 compress-overlay (timeout 00:09:10) [common]
219 09:50:12.171314 end: 1.6.2.5 compress-overlay (duration 00:00:00) [common]
220 09:50:12.171782 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:09:10) [common]
221 09:50:12.172092 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
222 09:50:12.172429 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
223 09:50:12.172707 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:10) [common]
224 09:50:12.870899 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:01) [common]
225 09:50:12.871364 start: 1.6.4 extract-modules (timeout 00:09:09) [common]
226 09:50:12.871614 extracting modules file /var/lib/lava/dispatcher/tmp/921925/tftp-deploy-m284d0us/modules/modules.tar to /var/lib/lava/dispatcher/tmp/921925/extract-nfsrootfs-oy6kac8l
227 09:50:14.289734 extracting modules file /var/lib/lava/dispatcher/tmp/921925/tftp-deploy-m284d0us/modules/modules.tar to /var/lib/lava/dispatcher/tmp/921925/extract-overlay-ramdisk-jy8buzcl/ramdisk
228 09:50:15.772474 end: 1.6.4 extract-modules (duration 00:00:03) [common]
229 09:50:15.773061 start: 1.6.5 apply-overlay-tftp (timeout 00:09:06) [common]
230 09:50:15.773401 [common] Applying overlay to NFS
231 09:50:15.773667 [common] Applying overlay /var/lib/lava/dispatcher/tmp/921925/compress-overlay-f8abowip/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/921925/extract-nfsrootfs-oy6kac8l
232 09:50:15.809832 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
233 09:50:15.810353 start: 1.6.6 prepare-kernel (timeout 00:09:06) [common]
234 09:50:15.810686 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:09:06) [common]
235 09:50:15.810969 Converting downloaded kernel to a uImage
236 09:50:15.811339 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/921925/tftp-deploy-m284d0us/kernel/Image /var/lib/lava/dispatcher/tmp/921925/tftp-deploy-m284d0us/kernel/uImage
237 09:50:16.312363 output: Image Name:
238 09:50:16.312793 output: Created: Fri Nov 1 09:50:15 2024
239 09:50:16.313006 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
240 09:50:16.313210 output: Data Size: 45908480 Bytes = 44832.50 KiB = 43.78 MiB
241 09:50:16.313412 output: Load Address: 01080000
242 09:50:16.313612 output: Entry Point: 01080000
243 09:50:16.313811 output:
244 09:50:16.314146 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:01) [common]
245 09:50:16.314413 end: 1.6.6 prepare-kernel (duration 00:00:01) [common]
246 09:50:16.314683 start: 1.6.7 configure-preseed-file (timeout 00:09:06) [common]
247 09:50:16.314936 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
248 09:50:16.315191 start: 1.6.8 compress-ramdisk (timeout 00:09:06) [common]
249 09:50:16.315445 Building ramdisk /var/lib/lava/dispatcher/tmp/921925/extract-overlay-ramdisk-jy8buzcl/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/921925/extract-overlay-ramdisk-jy8buzcl/ramdisk
250 09:50:18.607754 >> 167186 blocks
251 09:50:26.377144 Adding RAMdisk u-boot header.
252 09:50:26.377805 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/921925/extract-overlay-ramdisk-jy8buzcl/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/921925/extract-overlay-ramdisk-jy8buzcl/ramdisk.cpio.gz.uboot
253 09:50:26.632231 output: Image Name:
254 09:50:26.632858 output: Created: Fri Nov 1 09:50:26 2024
255 09:50:26.633278 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
256 09:50:26.633686 output: Data Size: 23441761 Bytes = 22892.34 KiB = 22.36 MiB
257 09:50:26.634087 output: Load Address: 00000000
258 09:50:26.634482 output: Entry Point: 00000000
259 09:50:26.634893 output:
260 09:50:26.636055 rename /var/lib/lava/dispatcher/tmp/921925/extract-overlay-ramdisk-jy8buzcl/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/921925/tftp-deploy-m284d0us/ramdisk/ramdisk.cpio.gz.uboot
261 09:50:26.636779 end: 1.6.8 compress-ramdisk (duration 00:00:10) [common]
262 09:50:26.637319 end: 1.6 prepare-tftp-overlay (duration 00:00:31) [common]
263 09:50:26.637839 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:55) [common]
264 09:50:26.638293 No LXC device requested
265 09:50:26.638806 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
266 09:50:26.639316 start: 1.8 deploy-device-env (timeout 00:08:55) [common]
267 09:50:26.639804 end: 1.8 deploy-device-env (duration 00:00:00) [common]
268 09:50:26.640251 Checking files for TFTP limit of 4294967296 bytes.
269 09:50:26.642910 end: 1 tftp-deploy (duration 00:01:05) [common]
270 09:50:26.643485 start: 2 uboot-action (timeout 00:05:00) [common]
271 09:50:26.644033 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
272 09:50:26.644533 end: 2.1 uboot-from-media (duration 00:00:00) [common]
273 09:50:26.645077 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
274 09:50:26.645595 Using kernel file from prepare-kernel: 921925/tftp-deploy-m284d0us/kernel/uImage
275 09:50:26.646216 substitutions:
276 09:50:26.646617 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
277 09:50:26.647010 - {DTB_ADDR}: 0x01070000
278 09:50:26.647403 - {DTB}: 921925/tftp-deploy-m284d0us/dtb/meson-g12b-a311d-libretech-cc.dtb
279 09:50:26.647791 - {INITRD}: 921925/tftp-deploy-m284d0us/ramdisk/ramdisk.cpio.gz.uboot
280 09:50:26.648275 - {KERNEL_ADDR}: 0x01080000
281 09:50:26.648679 - {KERNEL}: 921925/tftp-deploy-m284d0us/kernel/uImage
282 09:50:26.649079 - {LAVA_MAC}: None
283 09:50:26.649487 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/921925/extract-nfsrootfs-oy6kac8l
284 09:50:26.649876 - {NFS_SERVER_IP}: 192.168.6.2
285 09:50:26.650259 - {PRESEED_CONFIG}: None
286 09:50:26.650644 - {PRESEED_LOCAL}: None
287 09:50:26.651028 - {RAMDISK_ADDR}: 0x08000000
288 09:50:26.651424 - {RAMDISK}: 921925/tftp-deploy-m284d0us/ramdisk/ramdisk.cpio.gz.uboot
289 09:50:26.651815 - {ROOT_PART}: None
290 09:50:26.652240 - {ROOT}: None
291 09:50:26.652622 - {SERVER_IP}: 192.168.6.2
292 09:50:26.653002 - {TEE_ADDR}: 0x83000000
293 09:50:26.653385 - {TEE}: None
294 09:50:26.653766 Parsed boot commands:
295 09:50:26.654138 - setenv autoload no
296 09:50:26.654519 - setenv initrd_high 0xffffffff
297 09:50:26.654916 - setenv fdt_high 0xffffffff
298 09:50:26.655302 - dhcp
299 09:50:26.655686 - setenv serverip 192.168.6.2
300 09:50:26.656096 - tftpboot 0x01080000 921925/tftp-deploy-m284d0us/kernel/uImage
301 09:50:26.656486 - tftpboot 0x08000000 921925/tftp-deploy-m284d0us/ramdisk/ramdisk.cpio.gz.uboot
302 09:50:26.656867 - tftpboot 0x01070000 921925/tftp-deploy-m284d0us/dtb/meson-g12b-a311d-libretech-cc.dtb
303 09:50:26.657245 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/921925/extract-nfsrootfs-oy6kac8l,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
304 09:50:26.657637 - bootm 0x01080000 0x08000000 0x01070000
305 09:50:26.658154 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
307 09:50:26.659675 start: 2.3 connect-device (timeout 00:05:00) [common]
308 09:50:26.660123 [common] connect-device Connecting to device using 'telnet conserv1 3007'
309 09:50:26.674347 Setting prompt string to ['lava-test: # ']
310 09:50:26.676306 end: 2.3 connect-device (duration 00:00:00) [common]
311 09:50:26.676977 start: 2.4 uboot-commands (timeout 00:05:00) [common]
312 09:50:26.677544 start: 2.4.1 reset-device (timeout 00:05:00) [common]
313 09:50:26.678093 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
314 09:50:26.679331 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
315 09:50:26.717210 >> OK - accepted request
316 09:50:26.719160 Returned 0 in 0 seconds
317 09:50:26.820235 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
319 09:50:26.821270 end: 2.4.1 reset-device (duration 00:00:00) [common]
320 09:50:26.821627 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
321 09:50:26.821943 Setting prompt string to ['Hit any key to stop autoboot']
322 09:50:26.822208 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
323 09:50:26.823267 Trying 192.168.56.21...
324 09:50:26.823566 Connected to conserv1.
325 09:50:26.823807 Escape character is '^]'.
326 09:50:26.824045
327 09:50:26.824270 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
328 09:50:26.824498
329 09:50:37.972966 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
330 09:50:37.973391 bl2_stage_init 0x01
331 09:50:37.973622 bl2_stage_init 0x81
332 09:50:37.978540 hw id: 0x0000 - pwm id 0x01
333 09:50:37.978851 bl2_stage_init 0xc1
334 09:50:37.979063 bl2_stage_init 0x02
335 09:50:37.979269
336 09:50:37.984181 L0:00000000
337 09:50:37.984735 L1:20000703
338 09:50:37.985192 L2:00008067
339 09:50:37.985635 L3:14000000
340 09:50:37.989558 B2:00402000
341 09:50:37.990047 B1:e0f83180
342 09:50:37.990509
343 09:50:37.990949 TE: 58159
344 09:50:37.991388
345 09:50:37.995227 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
346 09:50:37.995723
347 09:50:37.996201 Board ID = 1
348 09:50:38.000863 Set A53 clk to 24M
349 09:50:38.001400 Set A73 clk to 24M
350 09:50:38.001851 Set clk81 to 24M
351 09:50:38.006525 A53 clk: 1200 MHz
352 09:50:38.007012 A73 clk: 1200 MHz
353 09:50:38.007452 CLK81: 166.6M
354 09:50:38.007887 smccc: 00012ab5
355 09:50:38.012074 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
356 09:50:38.017576 board id: 1
357 09:50:38.023446 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
358 09:50:38.034112 fw parse done
359 09:50:38.040102 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
360 09:50:38.082742 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
361 09:50:38.093579 PIEI prepare done
362 09:50:38.094071 fastboot data load
363 09:50:38.094514 fastboot data verify
364 09:50:38.099289 verify result: 266
365 09:50:38.104865 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
366 09:50:38.105386 LPDDR4 probe
367 09:50:38.105850 ddr clk to 1584MHz
368 09:50:38.113069 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
369 09:50:38.150258
370 09:50:38.150877 dmc_version 0001
371 09:50:38.156877 Check phy result
372 09:50:38.162630 INFO : End of CA training
373 09:50:38.163144 INFO : End of initialization
374 09:50:38.168261 INFO : Training has run successfully!
375 09:50:38.168766 Check phy result
376 09:50:38.173791 INFO : End of initialization
377 09:50:38.174352 INFO : End of read enable training
378 09:50:38.179483 INFO : End of fine write leveling
379 09:50:38.185051 INFO : End of Write leveling coarse delay
380 09:50:38.185575 INFO : Training has run successfully!
381 09:50:38.186043 Check phy result
382 09:50:38.190642 INFO : End of initialization
383 09:50:38.191140 INFO : End of read dq deskew training
384 09:50:38.196217 INFO : End of MPR read delay center optimization
385 09:50:38.201789 INFO : End of write delay center optimization
386 09:50:38.207464 INFO : End of read delay center optimization
387 09:50:38.207956 INFO : End of max read latency training
388 09:50:38.213069 INFO : Training has run successfully!
389 09:50:38.213574 1D training succeed
390 09:50:38.222256 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
391 09:50:38.269917 Check phy result
392 09:50:38.270610 INFO : End of initialization
393 09:50:38.292237 INFO : End of 2D read delay Voltage center optimization
394 09:50:38.312400 INFO : End of 2D read delay Voltage center optimization
395 09:50:38.364398 INFO : End of 2D write delay Voltage center optimization
396 09:50:38.413653 INFO : End of 2D write delay Voltage center optimization
397 09:50:38.419156 INFO : Training has run successfully!
398 09:50:38.419523
399 09:50:38.419787 channel==0
400 09:50:38.424713 RxClkDly_Margin_A0==88 ps 9
401 09:50:38.425313 TxDqDly_Margin_A0==98 ps 10
402 09:50:38.430328 RxClkDly_Margin_A1==88 ps 9
403 09:50:38.430905 TxDqDly_Margin_A1==98 ps 10
404 09:50:38.431390 TrainedVREFDQ_A0==74
405 09:50:38.435947 TrainedVREFDQ_A1==74
406 09:50:38.436501 VrefDac_Margin_A0==24
407 09:50:38.436971 DeviceVref_Margin_A0==40
408 09:50:38.441568 VrefDac_Margin_A1==25
409 09:50:38.442098 DeviceVref_Margin_A1==40
410 09:50:38.442568
411 09:50:38.443031
412 09:50:38.447193 channel==1
413 09:50:38.447718 RxClkDly_Margin_A0==98 ps 10
414 09:50:38.448232 TxDqDly_Margin_A0==98 ps 10
415 09:50:38.452659 RxClkDly_Margin_A1==98 ps 10
416 09:50:38.453179 TxDqDly_Margin_A1==88 ps 9
417 09:50:38.458331 TrainedVREFDQ_A0==77
418 09:50:38.458865 TrainedVREFDQ_A1==77
419 09:50:38.459337 VrefDac_Margin_A0==22
420 09:50:38.463903 DeviceVref_Margin_A0==37
421 09:50:38.464457 VrefDac_Margin_A1==24
422 09:50:38.469549 DeviceVref_Margin_A1==37
423 09:50:38.470069
424 09:50:38.470539 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
425 09:50:38.475219
426 09:50:38.503221 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000016 00000018 00000019 00000017 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
427 09:50:38.503718 2D training succeed
428 09:50:38.508779 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
429 09:50:38.514360 auto size-- 65535DDR cs0 size: 2048MB
430 09:50:38.514897 DDR cs1 size: 2048MB
431 09:50:38.520003 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
432 09:50:38.520353 cs0 DataBus test pass
433 09:50:38.525607 cs1 DataBus test pass
434 09:50:38.526169 cs0 AddrBus test pass
435 09:50:38.526563 cs1 AddrBus test pass
436 09:50:38.526919
437 09:50:38.531250 100bdlr_step_size ps== 420
438 09:50:38.531646 result report
439 09:50:38.536823 boot times 0Enable ddr reg access
440 09:50:38.542240 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
441 09:50:38.555675 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
442 09:50:39.127563 0.0;M3 CHK:0;cm4_sp_mode 0
443 09:50:39.128240 MVN_1=0x00000000
444 09:50:39.133149 MVN_2=0x00000000
445 09:50:39.138814 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
446 09:50:39.139385 OPS=0x10
447 09:50:39.139802 ring efuse init
448 09:50:39.140245 chipver efuse init
449 09:50:39.144397 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
450 09:50:39.149986 [0.018961 Inits done]
451 09:50:39.150474 secure task start!
452 09:50:39.150878 high task start!
453 09:50:39.154590 low task start!
454 09:50:39.155134 run into bl31
455 09:50:39.161287 NOTICE: BL31: v1.3(release):4fc40b1
456 09:50:39.169081 NOTICE: BL31: Built : 15:58:17, May 22 2019
457 09:50:39.169599 NOTICE: BL31: G12A normal boot!
458 09:50:39.194427 NOTICE: BL31: BL33 decompress pass
459 09:50:39.199785 ERROR: Error initializing runtime service opteed_fast
460 09:50:40.432956
461 09:50:40.433593
462 09:50:40.441487 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
463 09:50:40.442023
464 09:50:40.442500 Model: Libre Computer AML-A311D-CC Alta
465 09:50:40.649851 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
466 09:50:40.673208 DRAM: 2 GiB (effective 3.8 GiB)
467 09:50:40.816274 Core: 408 devices, 31 uclasses, devicetree: separate
468 09:50:40.822019 WDT: Not starting watchdog@f0d0
469 09:50:40.854314 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
470 09:50:40.866926 Loading Environment from FAT... Card did not respond to voltage select! : -110
471 09:50:40.871721 ** Bad device specification mmc 0 **
472 09:50:40.882186 Card did not respond to voltage select! : -110
473 09:50:40.890251 ** Bad device specification mmc 0 **
474 09:50:40.890774 Couldn't find partition mmc 0
475 09:50:40.898110 Card did not respond to voltage select! : -110
476 09:50:40.903559 ** Bad device specification mmc 0 **
477 09:50:40.904099 Couldn't find partition mmc 0
478 09:50:40.908686 Error: could not access storage.
479 09:50:42.173299 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.�!,K��х��}���с0x01
480 09:50:42.173991 bl2_stage_init 0x81
481 09:50:42.178730 hw id: 0x0000 - pwm id 0x01
482 09:50:42.179246 bl2_stage_init 0xc1
483 09:50:42.179710 bl2_stage_init 0x02
484 09:50:42.180293
485 09:50:42.184502 L0:00000000
486 09:50:42.185020 L1:20000703
487 09:50:42.185480 L2:00008067
488 09:50:42.185929 L3:14000000
489 09:50:42.186372 B2:00402000
490 09:50:42.187202 B1:e0f83180
491 09:50:42.187676
492 09:50:42.188167 TE: 58150
493 09:50:42.188620
494 09:50:42.198394 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
495 09:50:42.198767
496 09:50:42.199012 Board ID = 1
497 09:50:42.199236 Set A53 clk to 24M
498 09:50:42.199482 Set A73 clk to 24M
499 09:50:42.203912 Set clk81 to 24M
500 09:50:42.204254 A53 clk: 1200 MHz
501 09:50:42.204477 A73 clk: 1200 MHz
502 09:50:42.209580 CLK81: 166.6M
503 09:50:42.209916 smccc: 00012aab
504 09:50:42.215123 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
505 09:50:42.215443 board id: 1
506 09:50:42.223799 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
507 09:50:42.234405 fw parse done
508 09:50:42.240336 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
509 09:50:42.282984 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
510 09:50:42.293880 PIEI prepare done
511 09:50:42.294382 fastboot data load
512 09:50:42.294840 fastboot data verify
513 09:50:42.299460 verify result: 266
514 09:50:42.305071 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
515 09:50:42.305568 LPDDR4 probe
516 09:50:42.306021 ddr clk to 1584MHz
517 09:50:42.313045 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
518 09:50:42.350471
519 09:50:42.350987 dmc_version 0001
520 09:50:42.357103 Check phy result
521 09:50:42.362966 INFO : End of CA training
522 09:50:42.363465 INFO : End of initialization
523 09:50:42.368491 INFO : Training has run successfully!
524 09:50:42.368983 Check phy result
525 09:50:42.374018 INFO : End of initialization
526 09:50:42.374505 INFO : End of read enable training
527 09:50:42.377415 INFO : End of fine write leveling
528 09:50:42.383018 INFO : End of Write leveling coarse delay
529 09:50:42.388638 INFO : Training has run successfully!
530 09:50:42.389144 Check phy result
531 09:50:42.389600 INFO : End of initialization
532 09:50:42.394179 INFO : End of read dq deskew training
533 09:50:42.399772 INFO : End of MPR read delay center optimization
534 09:50:42.400313 INFO : End of write delay center optimization
535 09:50:42.405449 INFO : End of read delay center optimization
536 09:50:42.410973 INFO : End of max read latency training
537 09:50:42.411480 INFO : Training has run successfully!
538 09:50:42.416646 1D training succeed
539 09:50:42.422493 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
540 09:50:42.470079 Check phy result
541 09:50:42.470606 INFO : End of initialization
542 09:50:42.491688 INFO : End of 2D read delay Voltage center optimization
543 09:50:42.511312 INFO : End of 2D read delay Voltage center optimization
544 09:50:42.563668 INFO : End of 2D write delay Voltage center optimization
545 09:50:42.612942 INFO : End of 2D write delay Voltage center optimization
546 09:50:42.618419 INFO : Training has run successfully!
547 09:50:42.618941
548 09:50:42.619408 channel==0
549 09:50:42.624094 RxClkDly_Margin_A0==88 ps 9
550 09:50:42.624657 TxDqDly_Margin_A0==98 ps 10
551 09:50:42.629703 RxClkDly_Margin_A1==88 ps 9
552 09:50:42.630249 TxDqDly_Margin_A1==98 ps 10
553 09:50:42.630723 TrainedVREFDQ_A0==74
554 09:50:42.635247 TrainedVREFDQ_A1==74
555 09:50:42.635757 VrefDac_Margin_A0==25
556 09:50:42.636364 DeviceVref_Margin_A0==40
557 09:50:42.640799 VrefDac_Margin_A1==25
558 09:50:42.641294 DeviceVref_Margin_A1==40
559 09:50:42.641750
560 09:50:42.642198
561 09:50:42.646388 channel==1
562 09:50:42.646888 RxClkDly_Margin_A0==98 ps 10
563 09:50:42.647342 TxDqDly_Margin_A0==98 ps 10
564 09:50:42.652013 RxClkDly_Margin_A1==88 ps 9
565 09:50:42.652500 TxDqDly_Margin_A1==98 ps 10
566 09:50:42.657676 TrainedVREFDQ_A0==77
567 09:50:42.658172 TrainedVREFDQ_A1==77
568 09:50:42.658629 VrefDac_Margin_A0==22
569 09:50:42.663179 DeviceVref_Margin_A0==37
570 09:50:42.663679 VrefDac_Margin_A1==24
571 09:50:42.668772 DeviceVref_Margin_A1==37
572 09:50:42.669263
573 09:50:42.669718 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
574 09:50:42.674411
575 09:50:42.702389 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000019 00000017 00000018 00000016 00000018 00000015 00000017 00000019 00000017 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000017 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
576 09:50:42.702935 2D training succeed
577 09:50:42.708122 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
578 09:50:42.713731 auto size-- 65535DDR cs0 size: 2048MB
579 09:50:42.714239 DDR cs1 size: 2048MB
580 09:50:42.719167 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
581 09:50:42.719662 cs0 DataBus test pass
582 09:50:42.724958 cs1 DataBus test pass
583 09:50:42.725446 cs0 AddrBus test pass
584 09:50:42.725900 cs1 AddrBus test pass
585 09:50:42.726346
586 09:50:42.730433 100bdlr_step_size ps== 420
587 09:50:42.730931 result report
588 09:50:42.736057 boot times 0Enable ddr reg access
589 09:50:42.741538 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
590 09:50:42.754493 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
591 09:50:43.327015 0.0;M3 CHK:0;cm4_sp_mode 0
592 09:50:43.327710 MVN_1=0x00000000
593 09:50:43.332459 MVN_2=0x00000000
594 09:50:43.338239 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
595 09:50:43.338792 OPS=0x10
596 09:50:43.339263 ring efuse init
597 09:50:43.339763 chipver efuse init
598 09:50:43.343851 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
599 09:50:43.349430 [0.018961 Inits done]
600 09:50:43.349936 secure task start!
601 09:50:43.350378 high task start!
602 09:50:43.354008 low task start!
603 09:50:43.354493 run into bl31
604 09:50:43.360765 NOTICE: BL31: v1.3(release):4fc40b1
605 09:50:43.368455 NOTICE: BL31: Built : 15:58:17, May 22 2019
606 09:50:43.368950 NOTICE: BL31: G12A normal boot!
607 09:50:43.393964 NOTICE: BL31: BL33 decompress pass
608 09:50:43.399510 ERROR: Error initializing runtime service opteed_fast
609 09:50:44.632645
610 09:50:44.633288
611 09:50:44.640951 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
612 09:50:44.641470
613 09:50:44.641937 Model: Libre Computer AML-A311D-CC Alta
614 09:50:44.849531 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
615 09:50:44.872721 DRAM: 2 GiB (effective 3.8 GiB)
616 09:50:45.015727 Core: 408 devices, 31 uclasses, devicetree: separate
617 09:50:45.021564 WDT: Not starting watchdog@f0d0
618 09:50:45.053994 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
619 09:50:45.066222 Loading Environment from FAT... Card did not respond to voltage select! : -110
620 09:50:45.071306 ** Bad device specification mmc 0 **
621 09:50:45.081621 Card did not respond to voltage select! : -110
622 09:50:45.089358 ** Bad device specification mmc 0 **
623 09:50:45.089677 Couldn't find partition mmc 0
624 09:50:45.097607 Card did not respond to voltage select! : -110
625 09:50:45.103123 ** Bad device specification mmc 0 **
626 09:50:45.103556 Couldn't find partition mmc 0
627 09:50:45.107163 Error: could not access storage.
628 09:50:45.451910 Net: eth0: ethernet@ff3f0000
629 09:50:45.452630 starting USB...
630 09:50:45.703547 Bus usb@ff500000: Register 3000140 NbrPorts 3
631 09:50:45.704283 Starting the controller
632 09:50:45.709925 USB XHCI 1.10
633 09:50:47.424953 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
634 09:50:47.425640 bl2_stage_init 0x01
635 09:50:47.426122 bl2_stage_init 0x81
636 09:50:47.430417 hw id: 0x0000 - pwm id 0x01
637 09:50:47.430940 bl2_stage_init 0xc1
638 09:50:47.431403 bl2_stage_init 0x02
639 09:50:47.431853
640 09:50:47.436066 L0:00000000
641 09:50:47.436577 L1:20000703
642 09:50:47.437036 L2:00008067
643 09:50:47.437482 L3:14000000
644 09:50:47.443167 B2:00402000
645 09:50:47.443671 B1:e0f83180
646 09:50:47.444165
647 09:50:47.444626 TE: 58124
648 09:50:47.445077
649 09:50:47.447348 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
650 09:50:47.447843
651 09:50:47.448343 Board ID = 1
652 09:50:47.452811 Set A53 clk to 24M
653 09:50:47.453321 Set A73 clk to 24M
654 09:50:47.453773 Set clk81 to 24M
655 09:50:47.458394 A53 clk: 1200 MHz
656 09:50:47.458895 A73 clk: 1200 MHz
657 09:50:47.459347 CLK81: 166.6M
658 09:50:47.459795 smccc: 00012a92
659 09:50:47.463957 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
660 09:50:47.469619 board id: 1
661 09:50:47.474535 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
662 09:50:47.486180 fw parse done
663 09:50:47.491285 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
664 09:50:47.534350 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
665 09:50:47.545629 PIEI prepare done
666 09:50:47.546136 fastboot data load
667 09:50:47.546596 fastboot data verify
668 09:50:47.551382 verify result: 266
669 09:50:47.556823 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
670 09:50:47.557324 LPDDR4 probe
671 09:50:47.557782 ddr clk to 1584MHz
672 09:50:47.564809 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
673 09:50:47.602139
674 09:50:47.602658 dmc_version 0001
675 09:50:47.608723 Check phy result
676 09:50:47.614637 INFO : End of CA training
677 09:50:47.615133 INFO : End of initialization
678 09:50:47.620233 INFO : Training has run successfully!
679 09:50:47.620730 Check phy result
680 09:50:47.625835 INFO : End of initialization
681 09:50:47.626328 INFO : End of read enable training
682 09:50:47.629164 INFO : End of fine write leveling
683 09:50:47.634554 INFO : End of Write leveling coarse delay
684 09:50:47.640234 INFO : Training has run successfully!
685 09:50:47.640730 Check phy result
686 09:50:47.641185 INFO : End of initialization
687 09:50:47.645777 INFO : End of read dq deskew training
688 09:50:47.651373 INFO : End of MPR read delay center optimization
689 09:50:47.651876 INFO : End of write delay center optimization
690 09:50:47.657010 INFO : End of read delay center optimization
691 09:50:47.662548 INFO : End of max read latency training
692 09:50:47.663051 INFO : Training has run successfully!
693 09:50:47.668248 1D training succeed
694 09:50:47.673344 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
695 09:50:47.721880 Check phy result
696 09:50:47.722418 INFO : End of initialization
697 09:50:47.743585 INFO : End of 2D read delay Voltage center optimization
698 09:50:47.763510 INFO : End of 2D read delay Voltage center optimization
699 09:50:47.814546 INFO : End of 2D write delay Voltage center optimization
700 09:50:47.864619 INFO : End of 2D write delay Voltage center optimization
701 09:50:47.870179 INFO : Training has run successfully!
702 09:50:47.870668
703 09:50:47.871119 channel==0
704 09:50:47.875796 RxClkDly_Margin_A0==88 ps 9
705 09:50:47.876336 TxDqDly_Margin_A0==98 ps 10
706 09:50:47.879151 RxClkDly_Margin_A1==88 ps 9
707 09:50:47.879633 TxDqDly_Margin_A1==98 ps 10
708 09:50:47.884591 TrainedVREFDQ_A0==74
709 09:50:47.885083 TrainedVREFDQ_A1==74
710 09:50:47.890207 VrefDac_Margin_A0==25
711 09:50:47.890753 DeviceVref_Margin_A0==40
712 09:50:47.891217 VrefDac_Margin_A1==25
713 09:50:47.895811 DeviceVref_Margin_A1==40
714 09:50:47.896396
715 09:50:47.896869
716 09:50:47.897322 channel==1
717 09:50:47.897761 RxClkDly_Margin_A0==98 ps 10
718 09:50:47.901489 TxDqDly_Margin_A0==98 ps 10
719 09:50:47.902017 RxClkDly_Margin_A1==88 ps 9
720 09:50:47.907169 TxDqDly_Margin_A1==88 ps 9
721 09:50:47.907721 TrainedVREFDQ_A0==77
722 09:50:47.908222 TrainedVREFDQ_A1==77
723 09:50:47.912626 VrefDac_Margin_A0==22
724 09:50:47.913161 DeviceVref_Margin_A0==37
725 09:50:47.918226 VrefDac_Margin_A1==24
726 09:50:47.918755 DeviceVref_Margin_A1==37
727 09:50:47.919239
728 09:50:47.923853 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
729 09:50:47.924441
730 09:50:47.951818 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000017 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
731 09:50:47.957408 2D training succeed
732 09:50:47.963003 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
733 09:50:47.963502 auto size-- 65535DDR cs0 size: 2048MB
734 09:50:47.968606 DDR cs1 size: 2048MB
735 09:50:47.969100 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
736 09:50:47.974197 cs0 DataBus test pass
737 09:50:47.974679 cs1 DataBus test pass
738 09:50:47.975129 cs0 AddrBus test pass
739 09:50:47.980099 cs1 AddrBus test pass
740 09:50:47.980588
741 09:50:47.981038 100bdlr_step_size ps== 432
742 09:50:47.981497 result report
743 09:50:47.985527 boot times 0Enable ddr reg access
744 09:50:47.992222 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
745 09:50:48.006712 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
746 09:50:48.578610 0.0;M3 CHK:0;cm4_sp_mode 0
747 09:50:48.579027 MVN_1=0x00000000
748 09:50:48.584062 MVN_2=0x00000000
749 09:50:48.589822 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
750 09:50:48.590124 OPS=0x10
751 09:50:48.590336 ring efuse init
752 09:50:48.590539 chipver efuse init
753 09:50:48.595418 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
754 09:50:48.601077 [0.018961 Inits done]
755 09:50:48.601374 secure task start!
756 09:50:48.601587 high task start!
757 09:50:48.605668 low task start!
758 09:50:48.605964 run into bl31
759 09:50:48.612274 NOTICE: BL31: v1.3(release):4fc40b1
760 09:50:48.620074 NOTICE: BL31: Built : 15:58:17, May 22 2019
761 09:50:48.620391 NOTICE: BL31: G12A normal boot!
762 09:50:48.645465 NOTICE: BL31: BL33 decompress pass
763 09:50:48.651140 ERROR: Error initializing runtime service opteed_fast
764 09:50:49.884169
765 09:50:49.884599
766 09:50:49.892503 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
767 09:50:49.892950
768 09:50:49.893282 Model: Libre Computer AML-A311D-CC Alta
769 09:50:50.101028 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
770 09:50:50.124353 DRAM: 2 GiB (effective 3.8 GiB)
771 09:50:50.267370 Core: 408 devices, 31 uclasses, devicetree: separate
772 09:50:50.273127 WDT: Not starting watchdog@f0d0
773 09:50:50.305559 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
774 09:50:50.317984 Loading Environment from FAT... Card did not respond to voltage select! : -110
775 09:50:50.322959 ** Bad device specification mmc 0 **
776 09:50:50.333264 Card did not respond to voltage select! : -110
777 09:50:50.340909 ** Bad device specification mmc 0 **
778 09:50:50.341419 Couldn't find partition mmc 0
779 09:50:50.349258 Card did not respond to voltage select! : -110
780 09:50:50.354827 ** Bad device specification mmc 0 **
781 09:50:50.355394 Couldn't find partition mmc 0
782 09:50:50.359831 Error: could not access storage.
783 09:50:50.702413 Net: eth0: ethernet@ff3f0000
784 09:50:50.703030 starting USB...
785 09:50:50.954094 Bus usb@ff500000: Register 3000140 NbrPorts 3
786 09:50:50.954716 Starting the controller
787 09:50:50.960127 USB XHCI 1.10
788 09:50:53.123679 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
789 09:50:53.124127 bl2_stage_init 0x01
790 09:50:53.124359 bl2_stage_init 0x81
791 09:50:53.129265 hw id: 0x0000 - pwm id 0x01
792 09:50:53.129708 bl2_stage_init 0xc1
793 09:50:53.130041 bl2_stage_init 0x02
794 09:50:53.130362
795 09:50:53.134629 L0:00000000
796 09:50:53.135019 L1:20000703
797 09:50:53.135268 L2:00008067
798 09:50:53.135482 L3:14000000
799 09:50:53.140432 B2:00402000
800 09:50:53.140831 B1:e0f83180
801 09:50:53.141148
802 09:50:53.141452 TE: 58124
803 09:50:53.141774
804 09:50:53.145927 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
805 09:50:53.146224
806 09:50:53.146435 Board ID = 1
807 09:50:53.151564 Set A53 clk to 24M
808 09:50:53.151964 Set A73 clk to 24M
809 09:50:53.152310 Set clk81 to 24M
810 09:50:53.157235 A53 clk: 1200 MHz
811 09:50:53.157634 A73 clk: 1200 MHz
812 09:50:53.157873 CLK81: 166.6M
813 09:50:53.158088 smccc: 00012a92
814 09:50:53.162752 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
815 09:50:53.168440 board id: 1
816 09:50:53.174407 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
817 09:50:53.184811 fw parse done
818 09:50:53.190726 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
819 09:50:53.233383 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
820 09:50:53.244329 PIEI prepare done
821 09:50:53.244674 fastboot data load
822 09:50:53.244908 fastboot data verify
823 09:50:53.249888 verify result: 266
824 09:50:53.255488 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
825 09:50:53.255925 LPDDR4 probe
826 09:50:53.256202 ddr clk to 1584MHz
827 09:50:53.263512 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
828 09:50:53.300812
829 09:50:53.301212 dmc_version 0001
830 09:50:53.307480 Check phy result
831 09:50:53.313362 INFO : End of CA training
832 09:50:53.313789 INFO : End of initialization
833 09:50:53.318952 INFO : Training has run successfully!
834 09:50:53.319235 Check phy result
835 09:50:53.324528 INFO : End of initialization
836 09:50:53.324943 INFO : End of read enable training
837 09:50:53.330185 INFO : End of fine write leveling
838 09:50:53.335729 INFO : End of Write leveling coarse delay
839 09:50:53.336043 INFO : Training has run successfully!
840 09:50:53.336278 Check phy result
841 09:50:53.341344 INFO : End of initialization
842 09:50:53.341747 INFO : End of read dq deskew training
843 09:50:53.346898 INFO : End of MPR read delay center optimization
844 09:50:53.352525 INFO : End of write delay center optimization
845 09:50:53.358557 INFO : End of read delay center optimization
846 09:50:53.358855 INFO : End of max read latency training
847 09:50:53.363617 INFO : Training has run successfully!
848 09:50:53.363895 1D training succeed
849 09:50:53.373039 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
850 09:50:53.420734 Check phy result
851 09:50:53.421614 INFO : End of initialization
852 09:50:53.443056 INFO : End of 2D read delay Voltage center optimization
853 09:50:53.462435 INFO : End of 2D read delay Voltage center optimization
854 09:50:53.514323 INFO : End of 2D write delay Voltage center optimization
855 09:50:53.563558 INFO : End of 2D write delay Voltage center optimization
856 09:50:53.569092 INFO : Training has run successfully!
857 09:50:53.569602
858 09:50:53.570081 channel==0
859 09:50:53.574573 RxClkDly_Margin_A0==88 ps 9
860 09:50:53.575058 TxDqDly_Margin_A0==108 ps 11
861 09:50:53.577893 RxClkDly_Margin_A1==88 ps 9
862 09:50:53.578375 TxDqDly_Margin_A1==98 ps 10
863 09:50:53.583458 TrainedVREFDQ_A0==74
864 09:50:53.583944 TrainedVREFDQ_A1==76
865 09:50:53.589073 VrefDac_Margin_A0==24
866 09:50:53.589619 DeviceVref_Margin_A0==40
867 09:50:53.590079 VrefDac_Margin_A1==24
868 09:50:53.594646 DeviceVref_Margin_A1==38
869 09:50:53.595169
870 09:50:53.595611
871 09:50:53.596076 channel==1
872 09:50:53.596506 RxClkDly_Margin_A0==88 ps 9
873 09:50:53.600302 TxDqDly_Margin_A0==88 ps 9
874 09:50:53.600789 RxClkDly_Margin_A1==78 ps 8
875 09:50:53.605830 TxDqDly_Margin_A1==88 ps 9
876 09:50:53.606307 TrainedVREFDQ_A0==76
877 09:50:53.606742 TrainedVREFDQ_A1==77
878 09:50:53.611435 VrefDac_Margin_A0==23
879 09:50:53.611898 DeviceVref_Margin_A0==38
880 09:50:53.617145 VrefDac_Margin_A1==24
881 09:50:53.617616 DeviceVref_Margin_A1==37
882 09:50:53.618048
883 09:50:53.622563 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
884 09:50:53.623035
885 09:50:53.650570 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000016 00000018 00000019 00000018 00000019 00000018 0000001a 0000001a 00000018 00000017 00000018 00000017 00000019 00000018 00000018 00000019 00000019 00000019 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
886 09:50:53.656231 2D training succeed
887 09:50:53.661757 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
888 09:50:53.662231 auto size-- 65535DDR cs0 size: 2048MB
889 09:50:53.667401 DDR cs1 size: 2048MB
890 09:50:53.667873 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
891 09:50:53.672999 cs0 DataBus test pass
892 09:50:53.673468 cs1 DataBus test pass
893 09:50:53.673901 cs0 AddrBus test pass
894 09:50:53.678552 cs1 AddrBus test pass
895 09:50:53.679017
896 09:50:53.679449 100bdlr_step_size ps== 420
897 09:50:53.679883 result report
898 09:50:53.684232 boot times 0Enable ddr reg access
899 09:50:53.691824 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
900 09:50:53.705325 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
901 09:50:54.277510 0.0;M3 CHK:0;cm4_sp_mode 0
902 09:50:54.278163 MVN_1=0x00000000
903 09:50:54.282864 MVN_2=0x00000000
904 09:50:54.288620 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
905 09:50:54.289123 OPS=0x10
906 09:50:54.289581 ring efuse init
907 09:50:54.290025 chipver efuse init
908 09:50:54.294131 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
909 09:50:54.299817 [0.018961 Inits done]
910 09:50:54.300363 secure task start!
911 09:50:54.300819 high task start!
912 09:50:54.304528 low task start!
913 09:50:54.305024 run into bl31
914 09:50:54.311133 NOTICE: BL31: v1.3(release):4fc40b1
915 09:50:54.318862 NOTICE: BL31: Built : 15:58:17, May 22 2019
916 09:50:54.319372 NOTICE: BL31: G12A normal boot!
917 09:50:54.344818 NOTICE: BL31: BL33 decompress pass
918 09:50:54.349855 ERROR: Error initializing runtime service opteed_fast
919 09:50:55.583136
920 09:50:55.583777
921 09:50:55.591551 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
922 09:50:55.592088
923 09:50:55.592549 Model: Libre Computer AML-A311D-CC Alta
924 09:50:55.799954 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
925 09:50:55.823321 DRAM: 2 GiB (effective 3.8 GiB)
926 09:50:55.966489 Core: 408 devices, 31 uclasses, devicetree: separate
927 09:50:55.972181 WDT: Not starting watchdog@f0d0
928 09:50:56.004552 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
929 09:50:56.016918 Loading Environment from FAT... Card did not respond to voltage select! : -110
930 09:50:56.021844 ** Bad device specification mmc 0 **
931 09:50:56.032205 Card did not respond to voltage select! : -110
932 09:50:56.039883 ** Bad device specification mmc 0 **
933 09:50:56.040226 Couldn't find partition mmc 0
934 09:50:56.048203 Card did not respond to voltage select! : -110
935 09:50:56.053689 ** Bad device specification mmc 0 **
936 09:50:56.054072 Couldn't find partition mmc 0
937 09:50:56.058756 Error: could not access storage.
938 09:50:56.401363 Net: eth0: ethernet@ff3f0000
939 09:50:56.401784 starting USB...
940 09:50:56.653103 Bus usb@ff500000: Register 3000140 NbrPorts 3
941 09:50:56.653691 Starting the controller
942 09:50:56.660074 USB XHCI 1.10
943 09:50:58.523134 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
944 09:50:58.523762 bl2_stage_init 0x01
945 09:50:58.524282 bl2_stage_init 0x81
946 09:50:58.528687 hw id: 0x0000 - pwm id 0x01
947 09:50:58.529181 bl2_stage_init 0xc1
948 09:50:58.529634 bl2_stage_init 0x02
949 09:50:58.530083
950 09:50:58.534232 L0:00000000
951 09:50:58.534739 L1:20000703
952 09:50:58.535192 L2:00008067
953 09:50:58.535638 L3:14000000
954 09:50:58.539841 B2:00402000
955 09:50:58.540358 B1:e0f83180
956 09:50:58.540804
957 09:50:58.541246 TE: 58124
958 09:50:58.541689
959 09:50:58.545484 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
960 09:50:58.545972
961 09:50:58.546425 Board ID = 1
962 09:50:58.551066 Set A53 clk to 24M
963 09:50:58.551550 Set A73 clk to 24M
964 09:50:58.552027 Set clk81 to 24M
965 09:50:58.556658 A53 clk: 1200 MHz
966 09:50:58.557156 A73 clk: 1200 MHz
967 09:50:58.557612 CLK81: 166.6M
968 09:50:58.558054 smccc: 00012a92
969 09:50:58.562238 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
970 09:50:58.567934 board id: 1
971 09:50:58.573790 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
972 09:50:58.584502 fw parse done
973 09:50:58.590559 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
974 09:50:58.633057 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
975 09:50:58.643942 PIEI prepare done
976 09:50:58.644492 fastboot data load
977 09:50:58.644935 fastboot data verify
978 09:50:58.649547 verify result: 266
979 09:50:58.655136 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
980 09:50:58.655615 LPDDR4 probe
981 09:50:58.656082 ddr clk to 1584MHz
982 09:50:58.663123 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
983 09:50:58.700365
984 09:50:58.700895 dmc_version 0001
985 09:50:58.707115 Check phy result
986 09:50:58.712926 INFO : End of CA training
987 09:50:58.713397 INFO : End of initialization
988 09:50:58.718521 INFO : Training has run successfully!
989 09:50:58.719044 Check phy result
990 09:50:58.724174 INFO : End of initialization
991 09:50:58.724688 INFO : End of read enable training
992 09:50:58.729712 INFO : End of fine write leveling
993 09:50:58.735329 INFO : End of Write leveling coarse delay
994 09:50:58.735827 INFO : Training has run successfully!
995 09:50:58.736319 Check phy result
996 09:50:58.740941 INFO : End of initialization
997 09:50:58.741438 INFO : End of read dq deskew training
998 09:50:58.746507 INFO : End of MPR read delay center optimization
999 09:50:58.752172 INFO : End of write delay center optimization
1000 09:50:58.757731 INFO : End of read delay center optimization
1001 09:50:58.758225 INFO : End of max read latency training
1002 09:50:58.763341 INFO : Training has run successfully!
1003 09:50:58.763832 1D training succeed
1004 09:50:58.772495 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
1005 09:50:58.820102 Check phy result
1006 09:50:58.820636 INFO : End of initialization
1007 09:50:58.841818 INFO : End of 2D read delay Voltage center optimization
1008 09:50:58.861934 INFO : End of 2D read delay Voltage center optimization
1009 09:50:58.913843 INFO : End of 2D write delay Voltage center optimization
1010 09:50:58.963054 INFO : End of 2D write delay Voltage center optimization
1011 09:50:58.968569 INFO : Training has run successfully!
1012 09:50:58.969086
1013 09:50:58.969576 channel==0
1014 09:50:58.974137 RxClkDly_Margin_A0==88 ps 9
1015 09:50:58.974636 TxDqDly_Margin_A0==98 ps 10
1016 09:50:58.979752 RxClkDly_Margin_A1==88 ps 9
1017 09:50:58.980276 TxDqDly_Margin_A1==88 ps 9
1018 09:50:58.980742 TrainedVREFDQ_A0==74
1019 09:50:58.985355 TrainedVREFDQ_A1==74
1020 09:50:58.985855 VrefDac_Margin_A0==25
1021 09:50:58.986323 DeviceVref_Margin_A0==40
1022 09:50:58.990977 VrefDac_Margin_A1==25
1023 09:50:58.991465 DeviceVref_Margin_A1==40
1024 09:50:58.991918
1025 09:50:58.992408
1026 09:50:58.992855 channel==1
1027 09:50:58.996547 RxClkDly_Margin_A0==98 ps 10
1028 09:50:58.997038 TxDqDly_Margin_A0==98 ps 10
1029 09:50:59.002150 RxClkDly_Margin_A1==88 ps 9
1030 09:50:59.002638 TxDqDly_Margin_A1==98 ps 10
1031 09:50:59.007742 TrainedVREFDQ_A0==77
1032 09:50:59.008268 TrainedVREFDQ_A1==77
1033 09:50:59.008729 VrefDac_Margin_A0==22
1034 09:50:59.013315 DeviceVref_Margin_A0==37
1035 09:50:59.013798 VrefDac_Margin_A1==24
1036 09:50:59.018990 DeviceVref_Margin_A1==37
1037 09:50:59.019485
1038 09:50:59.019936 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
1039 09:50:59.020426
1040 09:50:59.052560 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000017 00000019 00000018 00000019 00000019 00000018 00000017 00000018 00000017 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
1041 09:50:59.053096 2D training succeed
1042 09:50:59.058150 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
1043 09:50:59.063733 auto size-- 65535DDR cs0 size: 2048MB
1044 09:50:59.064274 DDR cs1 size: 2048MB
1045 09:50:59.069339 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
1046 09:50:59.069826 cs0 DataBus test pass
1047 09:50:59.074936 cs1 DataBus test pass
1048 09:50:59.075423 cs0 AddrBus test pass
1049 09:50:59.075880 cs1 AddrBus test pass
1050 09:50:59.076365
1051 09:50:59.080549 100bdlr_step_size ps== 420
1052 09:50:59.081055 result report
1053 09:50:59.086164 boot times 0Enable ddr reg access
1054 09:50:59.091494 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
1055 09:50:59.104998 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
1056 09:50:59.677347 0.0;M3 CHK:0;cm4_sp_mode 0
1057 09:50:59.677999 MVN_1=0x00000000
1058 09:50:59.682659 MVN_2=0x00000000
1059 09:50:59.688445 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
1060 09:50:59.688943 OPS=0x10
1061 09:50:59.689406 ring efuse init
1062 09:50:59.689856 chipver efuse init
1063 09:50:59.694146 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
1064 09:50:59.699609 [0.018961 Inits done]
1065 09:50:59.700147 secure task start!
1066 09:50:59.700605 high task start!
1067 09:50:59.704292 low task start!
1068 09:50:59.704773 run into bl31
1069 09:50:59.710928 NOTICE: BL31: v1.3(release):4fc40b1
1070 09:50:59.718622 NOTICE: BL31: Built : 15:58:17, May 22 2019
1071 09:50:59.719115 NOTICE: BL31: G12A normal boot!
1072 09:50:59.743952 NOTICE: BL31: BL33 decompress pass
1073 09:50:59.749592 ERROR: Error initializing runtime service opteed_fast
1074 09:51:00.982646
1075 09:51:00.983286
1076 09:51:00.991014 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
1077 09:51:00.991519
1078 09:51:00.992011 Model: Libre Computer AML-A311D-CC Alta
1079 09:51:01.199507 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
1080 09:51:01.222762 DRAM: 2 GiB (effective 3.8 GiB)
1081 09:51:01.365704 Core: 408 devices, 31 uclasses, devicetree: separate
1082 09:51:01.371590 WDT: Not starting watchdog@f0d0
1083 09:51:01.403819 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
1084 09:51:01.416365 Loading Environment from FAT... Card did not respond to voltage select! : -110
1085 09:51:01.421333 ** Bad device specification mmc 0 **
1086 09:51:01.431622 Card did not respond to voltage select! : -110
1087 09:51:01.439363 ** Bad device specification mmc 0 **
1088 09:51:01.439848 Couldn't find partition mmc 0
1089 09:51:01.447495 Card did not respond to voltage select! : -110
1090 09:51:01.453007 ** Bad device specification mmc 0 **
1091 09:51:01.453500 Couldn't find partition mmc 0
1092 09:51:01.458122 Error: could not access storage.
1093 09:51:01.800659 Net: eth0: ethernet@ff3f0000
1094 09:51:01.801194 starting USB...
1095 09:51:02.239777 Bus usb@ff500000: Register 3000140 NbrPorts 3
1096 09:51:02.240236 Starting the controller
1097 09:51:02.242940 USB XHCI 1.10
1098 09:51:03.613827 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
1099 09:51:03.621950 scanning usb for storage devices... 0 Storage Device(s) found
1101 09:51:03.673157 Hit any key to stop autoboot: 1
1102 09:51:03.673848 end: 2.4.2 bootloader-interrupt (duration 00:00:37) [common]
1103 09:51:03.674338 start: 2.4.3 bootloader-commands (timeout 00:04:23) [common]
1104 09:51:03.674641 Setting prompt string to ['=>']
1105 09:51:03.674931 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:23)
1106 09:51:03.689578 0
1107 09:51:03.690305 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1108 09:51:03.690614 Sending with 10 millisecond of delay
1110 09:51:04.825124 => setenv autoload no
1111 09:51:04.835741 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:22)
1112 09:51:04.838485 setenv autoload no
1113 09:51:04.839010 Sending with 10 millisecond of delay
1115 09:51:06.635741 => setenv initrd_high 0xffffffff
1116 09:51:06.646368 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:20)
1117 09:51:06.646975 setenv initrd_high 0xffffffff
1118 09:51:06.647473 Sending with 10 millisecond of delay
1120 09:51:08.263457 => setenv fdt_high 0xffffffff
1121 09:51:08.274334 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1122 09:51:08.275201 setenv fdt_high 0xffffffff
1123 09:51:08.275926 Sending with 10 millisecond of delay
1125 09:51:08.567759 => dhcp
1126 09:51:08.578614 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1127 09:51:08.579535 dhcp
1128 09:51:08.580013 Speed: 1000, full duplex
1129 09:51:08.580441 BOOTP broadcast 1
1130 09:51:08.594183 DHCP client bound to address 192.168.6.27 (15 ms)
1131 09:51:08.594974 Sending with 10 millisecond of delay
1133 09:51:10.272909 => setenv serverip 192.168.6.2
1134 09:51:10.283767 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:16)
1135 09:51:10.284768 setenv serverip 192.168.6.2
1136 09:51:10.285460 Sending with 10 millisecond of delay
1138 09:51:14.009248 => tftpboot 0x01080000 921925/tftp-deploy-m284d0us/kernel/uImage
1139 09:51:14.020076 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:13)
1140 09:51:14.020901 tftpboot 0x01080000 921925/tftp-deploy-m284d0us/kernel/uImage
1141 09:51:14.021365 Speed: 1000, full duplex
1142 09:51:14.021782 Using ethernet@ff3f0000 device
1143 09:51:14.022902 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1144 09:51:14.028287 Filename '921925/tftp-deploy-m284d0us/kernel/uImage'.
1145 09:51:14.032176 Load address: 0x1080000
1146 09:51:17.334044 Loading: *################################################## 43.8 MiB
1147 09:51:17.334468 13.2 MiB/s
1148 09:51:17.334693 done
1149 09:51:17.338552 Bytes transferred = 45908544 (2bc8240 hex)
1150 09:51:17.339089 Sending with 10 millisecond of delay
1152 09:51:22.025600 => tftpboot 0x08000000 921925/tftp-deploy-m284d0us/ramdisk/ramdisk.cpio.gz.uboot
1153 09:51:22.036354 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:05)
1154 09:51:22.036893 tftpboot 0x08000000 921925/tftp-deploy-m284d0us/ramdisk/ramdisk.cpio.gz.uboot
1155 09:51:22.037229 Speed: 1000, full duplex
1156 09:51:22.037442 Using ethernet@ff3f0000 device
1157 09:51:22.038780 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1158 09:51:22.050640 Filename '921925/tftp-deploy-m284d0us/ramdisk/ramdisk.cpio.gz.uboot'.
1159 09:51:22.050931 Load address: 0x8000000
1160 09:51:29.352595 Loading: *#######T ########################################## UDP wrong checksum 00000005 0000d3c4
1161 09:51:34.353278 T UDP wrong checksum 00000005 0000d3c4
1162 09:51:44.356397 T T UDP wrong checksum 00000005 0000d3c4
1163 09:51:46.341139 UDP wrong checksum 000000ff 00009dfa
1164 09:51:46.354273 UDP wrong checksum 000000ff 000026ed
1165 09:51:57.016219 T T UDP wrong checksum 000000ff 0000b9b2
1166 09:51:57.064328 UDP wrong checksum 000000ff 000045a5
1167 09:52:04.360736 T T UDP wrong checksum 00000005 0000d3c4
1168 09:52:19.364667 T T
1169 09:52:19.365117 Retry count exceeded; starting again
1171 09:52:19.366065 end: 2.4.3 bootloader-commands (duration 00:01:16) [common]
1174 09:52:19.367101 end: 2.4 uboot-commands (duration 00:01:53) [common]
1176 09:52:19.367909 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
1178 09:52:19.368565 end: 2 uboot-action (duration 00:01:53) [common]
1180 09:52:19.369452 Cleaning after the job
1181 09:52:19.369791 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/921925/tftp-deploy-m284d0us/ramdisk
1182 09:52:19.370982 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/921925/tftp-deploy-m284d0us/kernel
1183 09:52:19.394675 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/921925/tftp-deploy-m284d0us/dtb
1184 09:52:19.395881 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/921925/tftp-deploy-m284d0us/nfsrootfs
1185 09:52:19.452745 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/921925/tftp-deploy-m284d0us/modules
1186 09:52:19.459416 start: 4.1 power-off (timeout 00:00:30) [common]
1187 09:52:19.460059 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1188 09:52:19.493218 >> OK - accepted request
1189 09:52:19.495198 Returned 0 in 0 seconds
1190 09:52:19.595911 end: 4.1 power-off (duration 00:00:00) [common]
1192 09:52:19.596847 start: 4.2 read-feedback (timeout 00:10:00) [common]
1193 09:52:19.597542 Listened to connection for namespace 'common' for up to 1s
1194 09:52:20.598420 Finalising connection for namespace 'common'
1195 09:52:20.598843 Disconnecting from shell: Finalise
1196 09:52:20.599127 =>
1197 09:52:20.699729 end: 4.2 read-feedback (duration 00:00:01) [common]
1198 09:52:20.700119 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/921925
1199 09:52:23.133760 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/921925
1200 09:52:23.134401 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.