Boot log: beaglebone-black

    1 07:26:50.852514  lava-dispatcher, installed at version: 2023.08
    2 07:26:50.852922  start: 0 validate
    3 07:26:50.853167  Start time: 2024-11-04 07:26:50.853152+00:00 (UTC)
    4 07:26:50.853439  Validating that http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/initrd.cpio.gz exists
    5 07:26:51.193485  Validating that http://storage.kernelci.org/next/master/next-20241104/arm/multi_v7_defconfig/clang-17/kernel/zImage exists
    6 07:26:51.350713  Validating that http://storage.kernelci.org/next/master/next-20241104/arm/multi_v7_defconfig/clang-17/dtbs/ti/omap/am335x-boneblack.dtb exists
    7 07:26:51.509339  Validating that http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/full.rootfs.tar.xz exists
    8 07:26:51.667946  Validating that http://storage.kernelci.org/next/master/next-20241104/arm/multi_v7_defconfig/clang-17/modules.tar.xz exists
    9 07:26:51.834050  validate duration: 0.98
   11 07:26:51.835158  start: 1 tftp-deploy (timeout 00:10:00) [common]
   12 07:26:51.835632  start: 1.1 download-retry (timeout 00:10:00) [common]
   13 07:26:51.836071  start: 1.1.1 http-download (timeout 00:10:00) [common]
   14 07:26:51.836817  Not decompressing ramdisk as can be used compressed.
   15 07:26:51.837274  downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/initrd.cpio.gz
   16 07:26:51.837611  saving as /var/lib/lava/dispatcher/tmp/1216189/tftp-deploy-s4rhchl0/ramdisk/initrd.cpio.gz
   17 07:26:51.837957  total size: 4775763 (4 MB)
   18 07:26:52.156571  progress   0 % (0 MB)
   19 07:26:52.627998  progress   5 % (0 MB)
   20 07:26:52.815929  progress  10 % (0 MB)
   21 07:26:52.960731  progress  15 % (0 MB)
   22 07:26:52.974133  progress  20 % (0 MB)
   23 07:26:53.120572  progress  25 % (1 MB)
   24 07:26:53.274145  progress  30 % (1 MB)
   25 07:26:53.435449  progress  35 % (1 MB)
   26 07:26:53.591357  progress  40 % (1 MB)
   27 07:26:53.747672  progress  45 % (2 MB)
   28 07:26:53.902904  progress  50 % (2 MB)
   29 07:26:54.062359  progress  55 % (2 MB)
   30 07:26:54.217010  progress  60 % (2 MB)
   31 07:26:54.372482  progress  65 % (2 MB)
   32 07:26:54.530897  progress  70 % (3 MB)
   33 07:26:54.684727  progress  75 % (3 MB)
   34 07:26:54.839223  progress  80 % (3 MB)
   35 07:26:54.991783  progress  85 % (3 MB)
   36 07:26:55.148664  progress  90 % (4 MB)
   37 07:26:55.296039  progress  95 % (4 MB)
   38 07:26:55.444489  progress 100 % (4 MB)
   39 07:26:55.445543  4 MB downloaded in 3.61 s (1.26 MB/s)
   40 07:26:55.446232  end: 1.1.1 http-download (duration 00:00:04) [common]
   42 07:26:55.447402  end: 1.1 download-retry (duration 00:00:04) [common]
   43 07:26:55.447812  start: 1.2 download-retry (timeout 00:09:56) [common]
   44 07:26:55.448212  start: 1.2.1 http-download (timeout 00:09:56) [common]
   45 07:26:55.448845  downloading http://storage.kernelci.org/next/master/next-20241104/arm/multi_v7_defconfig/clang-17/kernel/zImage
   46 07:26:55.449163  saving as /var/lib/lava/dispatcher/tmp/1216189/tftp-deploy-s4rhchl0/kernel/zImage
   47 07:26:55.449466  total size: 12120576 (11 MB)
   48 07:26:55.449768  No compression specified
   49 07:26:55.610843  progress   0 % (0 MB)
   50 07:26:55.941675  progress   5 % (0 MB)
   51 07:26:56.413578  progress  10 % (1 MB)
   52 07:26:57.011393  progress  15 % (1 MB)
   53 07:26:57.349848  progress  20 % (2 MB)
   54 07:26:57.816234  progress  25 % (2 MB)
   55 07:26:58.280595  progress  30 % (3 MB)
   56 07:26:58.739150  progress  35 % (4 MB)
   57 07:26:59.146031  progress  40 % (4 MB)
   58 07:26:59.544360  progress  45 % (5 MB)
   59 07:26:59.996670  progress  50 % (5 MB)
   60 07:27:00.451662  progress  55 % (6 MB)
   61 07:27:00.798279  progress  60 % (6 MB)
   62 07:27:01.264507  progress  65 % (7 MB)
   63 07:27:01.709933  progress  70 % (8 MB)
   64 07:27:02.165853  progress  75 % (8 MB)
   65 07:27:02.507314  progress  80 % (9 MB)
   66 07:27:02.959439  progress  85 % (9 MB)
   67 07:27:03.296489  progress  90 % (10 MB)
   68 07:27:03.740854  progress  95 % (11 MB)
   69 07:27:04.072075  progress 100 % (11 MB)
   70 07:27:04.073623  11 MB downloaded in 8.62 s (1.34 MB/s)
   71 07:27:04.075598  end: 1.2.1 http-download (duration 00:00:09) [common]
   73 07:27:04.077172  end: 1.2 download-retry (duration 00:00:09) [common]
   74 07:27:04.077632  start: 1.3 download-retry (timeout 00:09:48) [common]
   75 07:27:04.078128  start: 1.3.1 http-download (timeout 00:09:48) [common]
   76 07:27:04.078972  downloading http://storage.kernelci.org/next/master/next-20241104/arm/multi_v7_defconfig/clang-17/dtbs/ti/omap/am335x-boneblack.dtb
   77 07:27:04.079288  saving as /var/lib/lava/dispatcher/tmp/1216189/tftp-deploy-s4rhchl0/dtb/am335x-boneblack.dtb
   78 07:27:04.079583  total size: 70544 (0 MB)
   79 07:27:04.079879  No compression specified
   80 07:27:04.244989  progress  46 % (0 MB)
   81 07:27:04.247845  progress  92 % (0 MB)
   82 07:27:04.249167  progress 100 % (0 MB)
   83 07:27:04.249707  0 MB downloaded in 0.17 s (0.40 MB/s)
   84 07:27:04.250300  end: 1.3.1 http-download (duration 00:00:00) [common]
   86 07:27:04.251377  end: 1.3 download-retry (duration 00:00:00) [common]
   87 07:27:04.251767  start: 1.4 download-retry (timeout 00:09:48) [common]
   88 07:27:04.252223  start: 1.4.1 http-download (timeout 00:09:48) [common]
   89 07:27:04.252756  downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/full.rootfs.tar.xz
   90 07:27:04.253093  saving as /var/lib/lava/dispatcher/tmp/1216189/tftp-deploy-s4rhchl0/nfsrootfs/full.rootfs.tar
   91 07:27:04.253419  total size: 117747780 (112 MB)
   92 07:27:04.253775  Using unxz to decompress xz
   93 07:27:04.423395  progress   0 % (0 MB)
   94 07:27:08.269200  progress   5 % (5 MB)
   95 07:27:11.801494  progress  10 % (11 MB)
   96 07:27:20.917976  progress  15 % (16 MB)
   97 07:27:28.251524  progress  20 % (22 MB)
   98 07:27:34.106649  progress  25 % (28 MB)
   99 07:27:39.304023  progress  30 % (33 MB)
  100 07:27:43.837600  progress  35 % (39 MB)
  101 07:27:49.442343  progress  40 % (44 MB)
  102 07:27:57.607997  progress  45 % (50 MB)
  103 07:28:03.460425  progress  50 % (56 MB)
  104 07:28:06.051405  progress  55 % (61 MB)
  105 07:28:08.881192  progress  60 % (67 MB)
  106 07:28:11.607060  progress  65 % (73 MB)
  107 07:28:14.294767  progress  70 % (78 MB)
  108 07:28:16.793722  progress  75 % (84 MB)
  109 07:28:18.737459  progress  80 % (89 MB)
  110 07:28:20.251395  progress  85 % (95 MB)
  111 07:28:21.622247  progress  90 % (101 MB)
  112 07:28:23.044121  progress  95 % (106 MB)
  113 07:28:24.678141  progress 100 % (112 MB)
  114 07:28:24.686220  112 MB downloaded in 80.43 s (1.40 MB/s)
  115 07:28:24.686903  end: 1.4.1 http-download (duration 00:01:20) [common]
  117 07:28:24.688014  end: 1.4 download-retry (duration 00:01:20) [common]
  118 07:28:24.688410  start: 1.5 download-retry (timeout 00:08:27) [common]
  119 07:28:24.688835  start: 1.5.1 http-download (timeout 00:08:27) [common]
  120 07:28:24.689462  downloading http://storage.kernelci.org/next/master/next-20241104/arm/multi_v7_defconfig/clang-17/modules.tar.xz
  121 07:28:24.689777  saving as /var/lib/lava/dispatcher/tmp/1216189/tftp-deploy-s4rhchl0/modules/modules.tar
  122 07:28:24.690103  total size: 6937024 (6 MB)
  123 07:28:24.690435  Using unxz to decompress xz
  124 07:28:24.851404  progress   0 % (0 MB)
  125 07:28:25.036246  progress   5 % (0 MB)
  126 07:28:25.082926  progress  10 % (0 MB)
  127 07:28:25.174815  progress  15 % (1 MB)
  128 07:28:25.327793  progress  20 % (1 MB)
  129 07:28:25.364846  progress  25 % (1 MB)
  130 07:28:25.516118  progress  30 % (2 MB)
  131 07:28:25.666631  progress  35 % (2 MB)
  132 07:28:25.811287  progress  40 % (2 MB)
  133 07:28:25.961877  progress  45 % (3 MB)
  134 07:28:26.107014  progress  50 % (3 MB)
  135 07:28:26.253309  progress  55 % (3 MB)
  136 07:28:26.302043  progress  60 % (4 MB)
  137 07:28:26.441925  progress  65 % (4 MB)
  138 07:28:26.588243  progress  70 % (4 MB)
  139 07:28:26.729633  progress  75 % (4 MB)
  140 07:28:26.783553  progress  80 % (5 MB)
  141 07:28:26.916996  progress  85 % (5 MB)
  142 07:28:27.062231  progress  90 % (5 MB)
  143 07:28:27.208717  progress  95 % (6 MB)
  144 07:28:27.338811  progress 100 % (6 MB)
  145 07:28:27.342505  6 MB downloaded in 2.65 s (2.49 MB/s)
  146 07:28:27.343072  end: 1.5.1 http-download (duration 00:00:03) [common]
  148 07:28:27.344242  end: 1.5 download-retry (duration 00:00:03) [common]
  149 07:28:27.344768  start: 1.6 prepare-tftp-overlay (timeout 00:08:24) [common]
  150 07:28:27.345194  start: 1.6.1 extract-nfsrootfs (timeout 00:08:24) [common]
  151 07:28:35.741440  Extracted nfsroot to /var/lib/lava/dispatcher/tmp/1216189/extract-nfsrootfs-fliunf5j
  152 07:28:35.741785  end: 1.6.1 extract-nfsrootfs (duration 00:00:08) [common]
  153 07:28:35.741959  start: 1.6.2 lava-overlay (timeout 00:08:16) [common]
  154 07:28:35.885232  [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/1216189/lava-overlay-0nxs1u9n
  155 07:28:35.885583  makedir: /var/lib/lava/dispatcher/tmp/1216189/lava-overlay-0nxs1u9n/lava-1216189/bin
  156 07:28:35.885789  makedir: /var/lib/lava/dispatcher/tmp/1216189/lava-overlay-0nxs1u9n/lava-1216189/tests
  157 07:28:35.885984  makedir: /var/lib/lava/dispatcher/tmp/1216189/lava-overlay-0nxs1u9n/lava-1216189/results
  158 07:28:35.886189  Creating /var/lib/lava/dispatcher/tmp/1216189/lava-overlay-0nxs1u9n/lava-1216189/bin/lava-add-keys
  159 07:28:35.886490  Creating /var/lib/lava/dispatcher/tmp/1216189/lava-overlay-0nxs1u9n/lava-1216189/bin/lava-add-sources
  160 07:28:35.886752  Creating /var/lib/lava/dispatcher/tmp/1216189/lava-overlay-0nxs1u9n/lava-1216189/bin/lava-background-process-start
  161 07:28:35.887014  Creating /var/lib/lava/dispatcher/tmp/1216189/lava-overlay-0nxs1u9n/lava-1216189/bin/lava-background-process-stop
  162 07:28:35.887294  Creating /var/lib/lava/dispatcher/tmp/1216189/lava-overlay-0nxs1u9n/lava-1216189/bin/lava-common-functions
  163 07:28:35.887554  Creating /var/lib/lava/dispatcher/tmp/1216189/lava-overlay-0nxs1u9n/lava-1216189/bin/lava-echo-ipv4
  164 07:28:35.887810  Creating /var/lib/lava/dispatcher/tmp/1216189/lava-overlay-0nxs1u9n/lava-1216189/bin/lava-install-packages
  165 07:28:35.888062  Creating /var/lib/lava/dispatcher/tmp/1216189/lava-overlay-0nxs1u9n/lava-1216189/bin/lava-installed-packages
  166 07:28:35.888313  Creating /var/lib/lava/dispatcher/tmp/1216189/lava-overlay-0nxs1u9n/lava-1216189/bin/lava-os-build
  167 07:28:35.888569  Creating /var/lib/lava/dispatcher/tmp/1216189/lava-overlay-0nxs1u9n/lava-1216189/bin/lava-probe-channel
  168 07:28:35.888846  Creating /var/lib/lava/dispatcher/tmp/1216189/lava-overlay-0nxs1u9n/lava-1216189/bin/lava-probe-ip
  169 07:28:35.889100  Creating /var/lib/lava/dispatcher/tmp/1216189/lava-overlay-0nxs1u9n/lava-1216189/bin/lava-target-ip
  170 07:28:35.889353  Creating /var/lib/lava/dispatcher/tmp/1216189/lava-overlay-0nxs1u9n/lava-1216189/bin/lava-target-mac
  171 07:28:35.889604  Creating /var/lib/lava/dispatcher/tmp/1216189/lava-overlay-0nxs1u9n/lava-1216189/bin/lava-target-storage
  172 07:28:35.889862  Creating /var/lib/lava/dispatcher/tmp/1216189/lava-overlay-0nxs1u9n/lava-1216189/bin/lava-test-case
  173 07:28:35.890114  Creating /var/lib/lava/dispatcher/tmp/1216189/lava-overlay-0nxs1u9n/lava-1216189/bin/lava-test-event
  174 07:28:35.890362  Creating /var/lib/lava/dispatcher/tmp/1216189/lava-overlay-0nxs1u9n/lava-1216189/bin/lava-test-feedback
  175 07:28:35.890610  Creating /var/lib/lava/dispatcher/tmp/1216189/lava-overlay-0nxs1u9n/lava-1216189/bin/lava-test-raise
  176 07:28:35.890858  Creating /var/lib/lava/dispatcher/tmp/1216189/lava-overlay-0nxs1u9n/lava-1216189/bin/lava-test-reference
  177 07:28:35.891109  Creating /var/lib/lava/dispatcher/tmp/1216189/lava-overlay-0nxs1u9n/lava-1216189/bin/lava-test-runner
  178 07:28:35.891418  Creating /var/lib/lava/dispatcher/tmp/1216189/lava-overlay-0nxs1u9n/lava-1216189/bin/lava-test-set
  179 07:28:35.891667  Creating /var/lib/lava/dispatcher/tmp/1216189/lava-overlay-0nxs1u9n/lava-1216189/bin/lava-test-shell
  180 07:28:35.891922  Updating /var/lib/lava/dispatcher/tmp/1216189/lava-overlay-0nxs1u9n/lava-1216189/bin/lava-add-keys (debian)
  181 07:28:35.892244  Updating /var/lib/lava/dispatcher/tmp/1216189/lava-overlay-0nxs1u9n/lava-1216189/bin/lava-add-sources (debian)
  182 07:28:35.892529  Updating /var/lib/lava/dispatcher/tmp/1216189/lava-overlay-0nxs1u9n/lava-1216189/bin/lava-install-packages (debian)
  183 07:28:35.892821  Updating /var/lib/lava/dispatcher/tmp/1216189/lava-overlay-0nxs1u9n/lava-1216189/bin/lava-installed-packages (debian)
  184 07:28:35.893106  Updating /var/lib/lava/dispatcher/tmp/1216189/lava-overlay-0nxs1u9n/lava-1216189/bin/lava-os-build (debian)
  185 07:28:35.893347  Creating /var/lib/lava/dispatcher/tmp/1216189/lava-overlay-0nxs1u9n/lava-1216189/environment
  186 07:28:35.893532  LAVA metadata
  187 07:28:35.893667  - LAVA_JOB_ID=1216189
  188 07:28:35.893793  - LAVA_DISPATCHER_IP=172.16.3.3
  189 07:28:35.894001  start: 1.6.2.1 ssh-authorize (timeout 00:08:16) [common]
  190 07:28:35.894498  end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
  191 07:28:35.894663  start: 1.6.2.2 lava-vland-overlay (timeout 00:08:16) [common]
  192 07:28:35.894784  skipped lava-vland-overlay
  193 07:28:35.894933  end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
  194 07:28:35.895089  start: 1.6.2.3 lava-multinode-overlay (timeout 00:08:16) [common]
  195 07:28:35.895216  skipped lava-multinode-overlay
  196 07:28:35.895364  end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
  197 07:28:35.895516  start: 1.6.2.4 test-definition (timeout 00:08:16) [common]
  198 07:28:35.895650  Loading test definitions
  199 07:28:35.895810  start: 1.6.2.4.1 inline-repo-action (timeout 00:08:16) [common]
  200 07:28:35.895940  Using /lava-1216189 at stage 0
  201 07:28:35.896560  uuid=1216189_1.6.2.4.1 testdef=None
  202 07:28:35.896728  end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
  203 07:28:35.896899  start: 1.6.2.4.2 test-overlay (timeout 00:08:16) [common]
  204 07:28:35.897769  end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
  206 07:28:35.898191  start: 1.6.2.4.3 test-install-overlay (timeout 00:08:16) [common]
  207 07:28:35.899264  end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
  209 07:28:35.899697  start: 1.6.2.4.4 test-runscript-overlay (timeout 00:08:16) [common]
  210 07:28:35.937517  runner path: /var/lib/lava/dispatcher/tmp/1216189/lava-overlay-0nxs1u9n/lava-1216189/0/tests/0_timesync-off test_uuid 1216189_1.6.2.4.1
  211 07:28:35.937823  end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
  213 07:28:35.938262  start: 1.6.2.4.5 git-repo-action (timeout 00:08:16) [common]
  214 07:28:35.938399  Using /lava-1216189 at stage 0
  215 07:28:35.938592  Fetching tests from https://github.com/kernelci/test-definitions.git
  216 07:28:35.938730  Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/1216189/lava-overlay-0nxs1u9n/lava-1216189/0/tests/1_kselftest-dt'
  217 07:28:43.826970  Running '/usr/bin/git checkout kernelci.org
  218 07:28:44.150641  Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/1216189/lava-overlay-0nxs1u9n/lava-1216189/0/tests/1_kselftest-dt/automated/linux/kselftest/kselftest.yaml
  219 07:28:44.152374  uuid=1216189_1.6.2.4.5 testdef=None
  220 07:28:44.152861  end: 1.6.2.4.5 git-repo-action (duration 00:00:08) [common]
  222 07:28:44.153648  start: 1.6.2.4.6 test-overlay (timeout 00:08:08) [common]
  223 07:28:44.156881  end: 1.6.2.4.6 test-overlay (duration 00:00:00) [common]
  225 07:28:44.157745  start: 1.6.2.4.7 test-install-overlay (timeout 00:08:08) [common]
  226 07:28:44.161759  end: 1.6.2.4.7 test-install-overlay (duration 00:00:00) [common]
  228 07:28:44.162885  start: 1.6.2.4.8 test-runscript-overlay (timeout 00:08:08) [common]
  229 07:28:44.166606  runner path: /var/lib/lava/dispatcher/tmp/1216189/lava-overlay-0nxs1u9n/lava-1216189/0/tests/1_kselftest-dt test_uuid 1216189_1.6.2.4.5
  230 07:28:44.166991  BOARD='beaglebone-black'
  231 07:28:44.167304  BRANCH='next'
  232 07:28:44.167601  SKIPFILE='/dev/null'
  233 07:28:44.167892  SKIP_INSTALL='True'
  234 07:28:44.168177  TESTPROG_URL='http://storage.kernelci.org/next/master/next-20241104/arm/multi_v7_defconfig/clang-17/kselftest.tar.xz'
  235 07:28:44.168470  TST_CASENAME=''
  236 07:28:44.168754  TST_CMDFILES='dt'
  237 07:28:44.169254  end: 1.6.2.4.8 test-runscript-overlay (duration 00:00:00) [common]
  239 07:28:44.170243  Creating lava-test-runner.conf files
  240 07:28:44.170541  Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/1216189/lava-overlay-0nxs1u9n/lava-1216189/0 for stage 0
  241 07:28:44.170983  - 0_timesync-off
  242 07:28:44.171299  - 1_kselftest-dt
  243 07:28:44.171764  end: 1.6.2.4 test-definition (duration 00:00:08) [common]
  244 07:28:44.172156  start: 1.6.2.5 compress-overlay (timeout 00:08:08) [common]
  245 07:28:55.618147  end: 1.6.2.5 compress-overlay (duration 00:00:11) [common]
  246 07:28:55.618410  start: 1.6.2.6 persistent-nfs-overlay (timeout 00:07:56) [common]
  247 07:28:55.618578  end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
  248 07:28:55.618747  end: 1.6.2 lava-overlay (duration 00:00:20) [common]
  249 07:28:55.618914  start: 1.6.3 extract-overlay-ramdisk (timeout 00:07:56) [common]
  250 07:28:55.766731  end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
  251 07:28:55.767018  start: 1.6.4 extract-modules (timeout 00:07:56) [common]
  252 07:28:55.767169  extracting modules file /var/lib/lava/dispatcher/tmp/1216189/tftp-deploy-s4rhchl0/modules/modules.tar to /var/lib/lava/dispatcher/tmp/1216189/extract-nfsrootfs-fliunf5j
  253 07:28:56.223120  extracting modules file /var/lib/lava/dispatcher/tmp/1216189/tftp-deploy-s4rhchl0/modules/modules.tar to /var/lib/lava/dispatcher/tmp/1216189/extract-overlay-ramdisk-k5iog9vk/ramdisk
  254 07:28:56.692682  end: 1.6.4 extract-modules (duration 00:00:01) [common]
  255 07:28:56.692961  start: 1.6.5 apply-overlay-tftp (timeout 00:07:55) [common]
  256 07:28:56.693112  [common] Applying overlay to NFS
  257 07:28:56.693238  [common] Applying overlay /var/lib/lava/dispatcher/tmp/1216189/compress-overlay-j4u5jcb4/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/1216189/extract-nfsrootfs-fliunf5j
  258 07:28:58.283789  end: 1.6.5 apply-overlay-tftp (duration 00:00:02) [common]
  259 07:28:58.284055  start: 1.6.6 prepare-kernel (timeout 00:07:54) [common]
  260 07:28:58.284223  start: 1.6.6.1 uboot-prepare-kernel (timeout 00:07:54) [common]
  261 07:28:58.284394  end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
  262 07:28:58.284552  end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
  263 07:28:58.284712  start: 1.6.7 configure-preseed-file (timeout 00:07:54) [common]
  264 07:28:58.284887  end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
  265 07:28:58.285048  start: 1.6.8 compress-ramdisk (timeout 00:07:54) [common]
  266 07:28:58.285186  Building ramdisk /var/lib/lava/dispatcher/tmp/1216189/extract-overlay-ramdisk-k5iog9vk/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/1216189/extract-overlay-ramdisk-k5iog9vk/ramdisk
  267 07:28:58.597289  >> 79376 blocks

  268 07:29:01.309265  Adding RAMdisk u-boot header.
  269 07:29:01.309646  mkimage -A arm -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/1216189/extract-overlay-ramdisk-k5iog9vk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/1216189/extract-overlay-ramdisk-k5iog9vk/ramdisk.cpio.gz.uboot
  270 07:29:01.597368  output: Image Name:   
  271 07:29:01.597717  output: Created:      Mon Nov  4 07:29:01 2024
  272 07:29:01.597916  output: Image Type:   ARM Linux RAMDisk Image (uncompressed)
  273 07:29:01.598114  output: Data Size:    15390182 Bytes = 15029.47 KiB = 14.68 MiB
  274 07:29:01.598310  output: Load Address: 00000000
  275 07:29:01.598505  output: Entry Point:  00000000
  276 07:29:01.598697  output: 
  277 07:29:01.598996  rename /var/lib/lava/dispatcher/tmp/1216189/extract-overlay-ramdisk-k5iog9vk/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/1216189/tftp-deploy-s4rhchl0/ramdisk/ramdisk.cpio.gz.uboot
  278 07:29:01.599316  end: 1.6.8 compress-ramdisk (duration 00:00:03) [common]
  279 07:29:01.599574  end: 1.6 prepare-tftp-overlay (duration 00:00:34) [common]
  280 07:29:01.599822  start: 1.7 lxc-create-udev-rule-action (timeout 00:07:50) [common]
  281 07:29:01.600024  No LXC device requested
  282 07:29:01.600258  end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
  283 07:29:01.600449  start: 1.8 deploy-device-env (timeout 00:07:50) [common]
  284 07:29:01.600613  end: 1.8 deploy-device-env (duration 00:00:00) [common]
  285 07:29:01.600745  Checking files for TFTP limit of 4294967296 bytes.
  286 07:29:01.601567  end: 1 tftp-deploy (duration 00:02:10) [common]
  287 07:29:01.601742  start: 2 uboot-action (timeout 00:05:00) [common]
  288 07:29:01.601909  start: 2.1 uboot-from-media (timeout 00:05:00) [common]
  289 07:29:01.602065  end: 2.1 uboot-from-media (duration 00:00:00) [common]
  290 07:29:01.602224  start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
  291 07:29:01.602461  substitutions:
  292 07:29:01.602588  - {BOOTX}: bootz 0x82000000 0x83000000 0x88000000
  293 07:29:01.602711  - {DTB_ADDR}: 0x88000000
  294 07:29:01.602830  - {DTB}: 1216189/tftp-deploy-s4rhchl0/dtb/am335x-boneblack.dtb
  295 07:29:01.602948  - {INITRD}: 1216189/tftp-deploy-s4rhchl0/ramdisk/ramdisk.cpio.gz.uboot
  296 07:29:01.603064  - {KERNEL_ADDR}: 0x82000000
  297 07:29:01.603195  - {KERNEL}: 1216189/tftp-deploy-s4rhchl0/kernel/zImage
  298 07:29:01.603371  - {LAVA_MAC}: None
  299 07:29:01.603563  - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/1216189/extract-nfsrootfs-fliunf5j
  300 07:29:01.603747  - {NFS_SERVER_IP}: 172.16.3.3
  301 07:29:01.603924  - {PRESEED_CONFIG}: None
  302 07:29:01.604104  - {PRESEED_LOCAL}: None
  303 07:29:01.604283  - {RAMDISK_ADDR}: 0x83000000
  304 07:29:01.604462  - {RAMDISK}: 1216189/tftp-deploy-s4rhchl0/ramdisk/ramdisk.cpio.gz.uboot
  305 07:29:01.604640  - {ROOT_PART}: None
  306 07:29:01.604830  - {ROOT}: None
  307 07:29:01.605009  - {SERVER_IP}: 172.16.3.3
  308 07:29:01.605185  - {TEE_ADDR}: 0x83000000
  309 07:29:01.605365  - {TEE}: None
  310 07:29:01.605543  Parsed boot commands:
  311 07:29:01.605719  - setenv autoload no
  312 07:29:01.605894  - setenv initrd_high 0xffffffff
  313 07:29:01.606073  - setenv fdt_high 0xffffffff
  314 07:29:01.606252  - dhcp
  315 07:29:01.606430  - setenv serverip 172.16.3.3
  316 07:29:01.606605  - tftp 0x82000000 1216189/tftp-deploy-s4rhchl0/kernel/zImage
  317 07:29:01.606785  - tftp 0x83000000 1216189/tftp-deploy-s4rhchl0/ramdisk/ramdisk.cpio.gz.uboot
  318 07:29:01.606965  - setenv initrd_size ${filesize}
  319 07:29:01.607131  - tftp 0x88000000 1216189/tftp-deploy-s4rhchl0/dtb/am335x-boneblack.dtb
  320 07:29:01.607251  - setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=172.16.3.3:/var/lib/lava/dispatcher/tmp/1216189/extract-nfsrootfs-fliunf5j,tcp,hard,v3 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
  321 07:29:01.607372  - bootz 0x82000000 0x83000000 0x88000000
  322 07:29:01.607522  end: 2.2 bootloader-overlay (duration 00:00:00) [common]
  324 07:29:01.607934  start: 2.3 connect-device (timeout 00:05:00) [common]
  325 07:29:01.608059  [common] connect-device Connecting to device using 'telnet ts5 2002'
  326 07:29:01.614777  Setting prompt string to ['lava-test: # ']
  327 07:29:01.615251  end: 2.3 connect-device (duration 00:00:00) [common]
  328 07:29:01.615440  start: 2.4 uboot-commands (timeout 00:05:00) [common]
  329 07:29:01.615619  start: 2.4.1 reset-device (timeout 00:05:00) [common]
  330 07:29:01.615789  start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
  331 07:29:01.616076  Calling: 'drpm' 'lf-bbb-02' 'powercycle'
  332 07:29:02.042374  >> OFF

  333 07:29:17.382909  >> ON

  334 07:29:17.383562  Returned 0 in 15 seconds
  335 07:29:17.483986  end: 2.4.1.1 pdu-reboot (duration 00:00:16) [common]
  337 07:29:17.484442  end: 2.4.1 reset-device (duration 00:00:16) [common]
  338 07:29:17.484617  start: 2.4.2 bootloader-interrupt (timeout 00:04:44) [common]
  339 07:29:17.484777  Setting prompt string to ['Hit any key to stop autoboot']
  340 07:29:17.484926  bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
  341 07:29:17.485328  Trying 192.168.1.205...
  342 07:29:17.485455  Connected to ts5.
  343 07:29:17.485574  Escape character is '^]'.
  344 07:29:17.485690  
  345 07:29:17.485806  ser2net port telnet,2002 device serialdev,/dev/ttyUSB-lf-bbb-02,115200n81,local [] (Debian GNU/Linux)
  346 07:29:17.485923  
  347 07:29:17.999178  
  348 07:29:18.007012  U-Boot SPL 2021.10-nethacked-for-LAVA_hws@denx.de-dirty (Oct 19 2021 - 19:02:35 +0200)
  349 07:29:18.007152  Trying to boot from MMC2
  350 07:29:18.520197  
  351 07:29:18.520521  
  352 07:29:18.524964  U-Boot 2021.10-nethacked-for-LAVA_hws@denx.de-dirty (Oct 19 2021 - 19:02:35 +0200)
  353 07:29:18.525127  
  354 07:29:18.525261  CPU  : AM335X-GP rev 2.1
  355 07:29:18.532831  Model: TI AM335x BeagleBone Black
  356 07:29:18.532993  DRAM:  512 MiB
  357 07:29:18.612858  WDT:   Started with servicing (60s timeout)
  358 07:29:19.019029  NAND:  0 MiB
  359 07:29:19.028707  MMC:   OMAP SD/MMC: 0, OMAP SD/MMC: 1
  360 07:29:19.062090  Loading Environment from FAT... <ethaddr> not set. Validating first E-fuse MAC
  361 07:29:19.091400  Net:   eth2: ethernet@4a100000, eth3: usb_ether
  362 07:29:19.150076  end: 2.4.2 bootloader-interrupt (duration 00:00:02) [common]
  363 07:29:19.150310  start: 2.4.3 bootloader-commands (timeout 00:04:42) [common]
  364 07:29:19.150481  Setting prompt string to ['=> ']
  365 07:29:19.150655  bootloader-commands: Wait for prompt ['=> '] (timeout 00:04:42)
  366 07:29:19.159935  Hit any key to stop autoboot:  2   0 
  367 07:29:19.160392  Setting prompt string to ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid']
  368 07:29:19.160552  Sending with 10 millisecond of delay
  370 07:29:20.293692  => setenv autoload no
  371 07:29:20.304027  bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:41)
  372 07:29:20.305385  setenv autoload no
  373 07:29:20.305724  Sending with 10 millisecond of delay
  375 07:29:22.100524  => setenv initrd_high 0xffffffff
  376 07:29:22.110880  bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:39)
  377 07:29:22.111173  setenv initrd_high 0xffffffff
  378 07:29:22.111497  Sending with 10 millisecond of delay
  380 07:29:23.725890  => setenv fdt_high 0xffffffff
  381 07:29:23.736228  bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:38)
  382 07:29:23.736511  setenv fdt_high 0xffffffff
  383 07:29:23.736822  Sending with 10 millisecond of delay
  385 07:29:24.027770  => dhcp
  386 07:29:24.038096  bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:38)
  387 07:29:24.039080  dhcp
  388 07:29:24.039239  link up on port 0, speed 100, full duplex
  389 07:29:24.039381  BOOTP broadcast 1
  390 07:29:24.087564  DHCP client bound to address 172.16.3.191 (42 ms)
  391 07:29:24.088005  Sending with 10 millisecond of delay
  393 07:29:25.702406  => setenv serverip 172.16.3.3
  394 07:29:25.712802  bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:36)
  395 07:29:25.713116  setenv serverip 172.16.3.3
  396 07:29:25.713444  Sending with 10 millisecond of delay
  398 07:29:29.252597  => tftp 0x82000000 1216189/tftp-deploy-s4rhchl0/kernel/zImage
  399 07:29:29.262966  bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:32)
  400 07:29:29.263241  tftp 0x82000000 1216189/tftp-deploy-s4rhchl0/kernel/zImage
  401 07:29:29.263373  link up on port 0, speed 100, full duplex
  402 07:29:29.268937  Using ethernet@4a100000 device
  403 07:29:29.273831  TFTP from server 172.16.3.3; our IP address is 172.16.3.191
  404 07:29:29.281856  Filename '1216189/tftp-deploy-s4rhchl0/kernel/zImage'.
  405 07:29:29.282015  Load address: 0x82000000
  406 07:29:31.588496  Loading: *##################################################  11.6 MiB
  407 07:29:31.588892  	 5 MiB/s
  408 07:29:31.589047  done
  409 07:29:31.592929  Bytes transferred = 12120576 (b8f200 hex)
  410 07:29:31.593423  Sending with 10 millisecond of delay
  412 07:29:36.101129  => tftp 0x83000000 1216189/tftp-deploy-s4rhchl0/ramdisk/ramdisk.cpio.gz.uboot
  413 07:29:36.111856  bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:25)
  414 07:29:36.112852  tftp 0x83000000 1216189/tftp-deploy-s4rhchl0/ramdisk/ramdisk.cpio.gz.uboot
  415 07:29:36.113187  link up on port 0, speed 100, full duplex
  416 07:29:36.119065  Using ethernet@4a100000 device
  417 07:29:36.123806  TFTP from server 172.16.3.3; our IP address is 172.16.3.191
  418 07:29:36.129851  Filename '1216189/tftp-deploy-s4rhchl0/ramdisk/ramdisk.cpio.gz.uboot'.
  419 07:29:36.130121  Load address: 0x83000000
  420 07:29:39.806788  Loading: *##################################################  14.7 MiB
  421 07:29:39.807285  	 4 MiB/s
  422 07:29:39.807595  done
  423 07:29:39.811040  Bytes transferred = 15390246 (ead626 hex)
  424 07:29:39.811716  Sending with 10 millisecond of delay
  426 07:29:41.670258  => setenv initrd_size ${filesize}
  427 07:29:41.680913  bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:20)
  428 07:29:41.681546  setenv initrd_size ${filesize}
  429 07:29:41.682118  Sending with 10 millisecond of delay
  431 07:29:45.888520  => tftp 0x88000000 1216189/tftp-deploy-s4rhchl0/dtb/am335x-boneblack.dtb
  432 07:29:45.898930  bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:16)
  433 07:29:45.899239  tftp 0x88000000 1216189/tftp-deploy-s4rhchl0/dtb/am335x-boneblack.dtb
  434 07:29:45.899376  link up on port 0, speed 100, full duplex
  435 07:29:45.904864  Using ethernet@4a100000 device
  436 07:29:45.910828  TFTP from server 172.16.3.3; our IP address is 172.16.3.191
  437 07:29:45.919499  Filename '1216189/tftp-deploy-s4rhchl0/dtb/am335x-boneblack.dtb'.
  438 07:29:45.919657  Load address: 0x88000000
  439 07:29:45.939093  Loading: *##################################################  68.9 KiB
  440 07:29:45.939252  	 4.2 MiB/s
  441 07:29:45.939407  done
  442 07:29:45.943386  Bytes transferred = 70544 (11390 hex)
  443 07:29:45.943735  Sending with 10 millisecond of delay
  445 07:29:59.308600  => setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=172.16.3.3:/var/lib/lava/dispatcher/tmp/1216189/extract-nfsrootfs-fliunf5j,tcp,hard,v3 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
  446 07:29:59.319318  bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:02)
  447 07:29:59.319981  setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=172.16.3.3:/var/lib/lava/dispatcher/tmp/1216189/extract-nfsrootfs-fliunf5j,tcp,hard,v3 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
  448 07:29:59.320566  Sending with 10 millisecond of delay
  450 07:30:01.660095  => bootz 0x82000000 0x83000000 0x88000000
  451 07:30:01.670707  Setting prompt string to ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid']
  452 07:30:01.671207  bootloader-commands: Wait for prompt ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:00)
  453 07:30:01.671980  bootz 0x82000000 0x83000000 0x88000000
  454 07:30:01.672276  Kernel image @ 0x82000000 [ 0x000000 - 0xb8f200 ]
  455 07:30:01.674073  ## Loading init Ramdisk from Legacy Image at 83000000 ...
  456 07:30:01.680240     Image Name:   
  457 07:30:01.680625     Created:      2024-11-04   7:29:01 UTC
  458 07:30:01.683779     Image Type:   ARM Linux RAMDisk Image (uncompressed)
  459 07:30:01.688807     Data Size:    15390182 Bytes = 14.7 MiB
  460 07:30:01.696815     Load Address: 00000000
  461 07:30:01.697205     Entry Point:  00000000
  462 07:30:01.872055     Verifying Checksum ... OK
  463 07:30:01.872440  ## Flattened Device Tree blob at 88000000
  464 07:30:01.879578     Booting using the fdt blob at 0x88000000
  465 07:30:01.882788     Using Device Tree in place at 88000000, end 8801438f
  466 07:30:01.896905  
  467 07:30:01.897317  Starting kernel ...
  468 07:30:01.897703  
  469 07:30:01.898485  end: 2.4.3 bootloader-commands (duration 00:00:43) [common]
  470 07:30:01.898989  start: 2.4.4 auto-login-action (timeout 00:04:00) [common]
  471 07:30:01.899379  Setting prompt string to ['Linux version [0-9]']
  472 07:30:01.899778  Setting prompt string to ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid']
  473 07:30:01.900173  auto-login-action: Wait for prompt ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:05:00)
  474 07:30:02.816125  [    0.000000] Booting Linux on physical CPU 0x0
  475 07:30:02.822783  start: 2.4.4.1 login-action (timeout 00:03:59) [common]
  476 07:30:02.823279  The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
  477 07:30:02.823659  Setting prompt string to []
  478 07:30:02.824120  Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
  479 07:30:02.824544  Using line separator: #'\n'#
  480 07:30:02.824909  No login prompt set.
  481 07:30:02.825300  Parsing kernel messages
  482 07:30:02.825643  ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
  483 07:30:02.826280  [login-action] Waiting for messages, (timeout 00:03:59)
  484 07:30:02.841870  [    0.000000] Linux version 6.12.0-rc5-next-20241104 (KernelCI@build-j361521-arm-clang-17-multi-v7-defconfig-z6lf7) (Debian clang version 17.0.6 (++20231208085813+6009708b4367-1~exp1~20231208085906.81), Debian LLD 17.0.6) #1 SMP Mon Nov  4 07:04:33 UTC 2024
  485 07:30:02.847950  [    0.000000] CPU: ARMv7 Processor [413fc082] revision 2 (ARMv7), cr=10c5387d
  486 07:30:02.856491  [    0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
  487 07:30:02.862567  [    0.000000] OF: fdt: Machine model: TI AM335x BeagleBone Black
  488 07:30:02.868679  [    0.000000] earlycon: omap8250 at MMIO 0x44e09000 (options '')
  489 07:30:02.872236  [    0.000000] printk: legacy bootconsole [omap8250] enabled
  490 07:30:02.877221  [    0.000000] Memory policy: Data cache writeback
  491 07:30:02.883523  [    0.000000] efi: UEFI not found.
  492 07:30:02.887837  [    0.000000] cma: Reserved 64 MiB at 0x9b800000 on node -1
  493 07:30:02.902547  [    0.000000] Zone ranges:
  494 07:30:02.903075  [    0.000000]   DMA      [mem 0x0000000080000000-0x000000009fdfffff]
  495 07:30:02.903236  [    0.000000]   Normal   empty
  496 07:30:02.906599  [    0.000000]   HighMem  empty
  497 07:30:02.912561  [    0.000000] Movable zone start for each node
  498 07:30:02.912754  [    0.000000] Early memory node ranges
  499 07:30:02.917494  [    0.000000]   node   0: [mem 0x0000000080000000-0x000000009fdfffff]
  500 07:30:02.927968  [    0.000000] Initmem setup node 0 [mem 0x0000000080000000-0x000000009fdfffff]
  501 07:30:02.940815  [    0.000000] OF: reserved mem: Reserved memory: No reserved-memory node in the DT
  502 07:30:02.954561  [    0.000000] CPU: All CPU(s) started in SVC mode.
  503 07:30:02.960144  [    0.000000] AM335X ES2.1 (sgx neon)
  504 07:30:02.972451  [    0.000000] percpu: Embedded 17 pages/cpu s40204 r8192 d21236 u69632
  505 07:30:02.992407  [    0.000000] Kernel command line: console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=172.16.3.3:/var/lib/lava/dispatcher/tmp/1216189/extract-nfsrootfs-fliunf5j,tcp,hard,v3 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp
  506 07:30:02.998531  <6>[    0.000000] printk: log buffer data + meta data: 131072 + 409600 = 540672 bytes
  507 07:30:03.007030  <6>[    0.000000] Dentry cache hash table entries: 65536 (order: 6, 262144 bytes, linear)
  508 07:30:03.019253  <6>[    0.000000] Inode-cache hash table entries: 32768 (order: 5, 131072 bytes, linear)
  509 07:30:03.022769  <6>[    0.000000] Built 1 zonelists, mobility grouping on.  Total pages: 130560
  510 07:30:03.030903  <6>[    0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
  511 07:30:03.060290  <6>[    0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
  512 07:30:03.066332  <6>[    0.000000] trace event string verifier disabled
  513 07:30:03.066713  <6>[    0.000000] rcu: Hierarchical RCU implementation.
  514 07:30:03.073758  <6>[    0.000000] rcu: 	RCU event tracing is enabled.
  515 07:30:03.079866  <6>[    0.000000] rcu: 	RCU restricting CPUs from NR_CPUS=16 to nr_cpu_ids=1.
  516 07:30:03.085990  <6>[    0.000000] 	Tracing variant of Tasks RCU enabled.
  517 07:30:03.094574  <6>[    0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 10 jiffies.
  518 07:30:03.100661  <6>[    0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=1
  519 07:30:03.110168  <6>[    0.000000] RCU Tasks Trace: Setting shift to 0 and lim to 1 rcu_task_cb_adjust=1 rcu_task_cpu_ids=1.
  520 07:30:03.126940  <6>[    0.000000] NR_IRQS: 16, nr_irqs: 16, preallocated irqs: 16
  521 07:30:03.144620  <6>[    0.000000] IRQ: Found an INTC at 0x(ptrval) (revision 5.0) with 128 interrupts
  522 07:30:03.152625  <6>[    0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
  523 07:30:03.255685  <6>[    0.000000] TI gptimer clocksource: always-on /ocp/interconnect@44c00000/segment@200000/target-module@31000
  524 07:30:03.264149  <6>[    0.000003] sched_clock: 32 bits at 24MHz, resolution 41ns, wraps every 89478484971ns
  525 07:30:03.276484  <6>[    0.008339] clocksource: dmtimer: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 79635851949 ns
  526 07:30:03.284984  <6>[    0.019217] TI gptimer clockevent: 24000000 Hz at /ocp/interconnect@48000000/segment@0/target-module@40000
  527 07:30:03.295711  <6>[    0.034439] Console: colour dummy device 80x30
  528 07:30:03.300952  Matched prompt #6: WARNING:
  529 07:30:03.301348  Setting prompt string to ['end trace[^\\r]*\\r', '/ #', 'Login timed out', 'Login incorrect']
  530 07:30:03.306634  <3>[    0.039332] WARNING: Your 'console=ttyO0' has been replaced by 'ttyS0'
  531 07:30:03.309010  <3>[    0.046400] This ensures that you still see kernel messages. Please
  532 07:30:03.315882  <3>[    0.053124] update your kernel commandline.
  533 07:30:03.354716  <6>[    0.057733] Calibrating delay loop... 996.14 BogoMIPS (lpj=4980736)
  534 07:30:03.360877  <6>[    0.096220] CPU: Testing write buffer coherency: ok
  535 07:30:03.364389  <6>[    0.101589] CPU0: Spectre v2: using BPIALL workaround
  536 07:30:03.369406  <6>[    0.107056] pid_max: default: 32768 minimum: 301
  537 07:30:03.375531  <6>[    0.112252] Mount-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
  538 07:30:03.385184  <6>[    0.120074] Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
  539 07:30:03.392718  <6>[    0.129530] CPU0: thread -1, cpu 0, socket -1, mpidr 0
  540 07:30:03.405789  <6>[    0.136634] Setting up static identity map for 0x80300000 - 0x803000ac
  541 07:30:03.410788  <6>[    0.146419] rcu: Hierarchical SRCU implementation.
  542 07:30:03.415098  <6>[    0.151698] rcu: 	Max phase no-delay instances is 1000.
  543 07:30:03.424882  <6>[    0.163242] EFI services will not be available.
  544 07:30:03.429715  <6>[    0.168532] smp: Bringing up secondary CPUs ...
  545 07:30:03.434724  <6>[    0.173579] smp: Brought up 1 node, 1 CPU
  546 07:30:03.440768  <6>[    0.177977] SMP: Total of 1 processors activated (996.14 BogoMIPS).
  547 07:30:03.446910  <6>[    0.184746] CPU: All CPU(s) started in SVC mode.
  548 07:30:03.461710  <6>[    0.189942] Memory: 404396K/522240K available (17408K kernel code, 2535K rwdata, 6732K rodata, 2048K init, 428K bss, 50648K reserved, 65536K cma-reserved, 0K highmem)
  549 07:30:03.467153  <6>[    0.206240] devtmpfs: initialized
  550 07:30:03.490174  <6>[    0.223857] VFP support v0.3: implementor 41 architecture 3 part 30 variant c rev 3
  551 07:30:03.498708  <6>[    0.232453] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
  552 07:30:03.508003  <6>[    0.242912] futex hash table entries: 256 (order: 2, 16384 bytes, linear)
  553 07:30:03.518528  <6>[    0.255184] pinctrl core: initialized pinctrl subsystem
  554 07:30:03.528341  <6>[    0.266154] DMI not present or invalid.
  555 07:30:03.536966  <6>[    0.272045] NET: Registered PF_NETLINK/PF_ROUTE protocol family
  556 07:30:03.546269  <6>[    0.281069] DMA: preallocated 256 KiB pool for atomic coherent allocations
  557 07:30:03.560627  <6>[    0.292787] thermal_sys: Registered thermal governor 'step_wise'
  558 07:30:03.561029  <6>[    0.292982] cpuidle: using governor menu
  559 07:30:03.583872  <6>[    0.323659] No ATAGs?
  560 07:30:03.590589  <6>[    0.326302] hw-breakpoint: debug architecture 0x4 unsupported.
  561 07:30:03.599751  <6>[    0.338470] Serial: AMBA PL011 UART driver
  562 07:30:03.635610  <6>[    0.375378] iommu: Default domain type: Translated
  563 07:30:03.644953  <6>[    0.380724] iommu: DMA domain TLB invalidation policy: strict mode
  564 07:30:03.672465  <5>[    0.410610] SCSI subsystem initialized
  565 07:30:03.677315  <6>[    0.415520] usbcore: registered new interface driver usbfs
  566 07:30:03.683412  <6>[    0.421566] usbcore: registered new interface driver hub
  567 07:30:03.691966  <6>[    0.427354] usbcore: registered new device driver usb
  568 07:30:03.698089  <6>[    0.433920] pps_core: LinuxPPS API ver. 1 registered
  569 07:30:03.704220  <6>[    0.439309] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
  570 07:30:03.711589  <6>[    0.449042] PTP clock support registered
  571 07:30:03.714830  <6>[    0.453526] EDAC MC: Ver: 3.0.0
  572 07:30:03.763949  <6>[    0.501410] scmi_core: SCMI protocol bus registered
  573 07:30:03.778287  <6>[    0.517959] vgaarb: loaded
  574 07:30:03.789963  <6>[    0.530166] clocksource: Switched to clocksource dmtimer
  575 07:30:03.820631  <6>[    0.559361] NET: Registered PF_INET protocol family
  576 07:30:03.832977  <6>[    0.565079] IP idents hash table entries: 8192 (order: 4, 65536 bytes, linear)
  577 07:30:03.839037  <6>[    0.574096] tcp_listen_portaddr_hash hash table entries: 512 (order: 0, 4096 bytes, linear)
  578 07:30:03.850087  <6>[    0.583031] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
  579 07:30:03.856161  <6>[    0.591276] TCP established hash table entries: 4096 (order: 2, 16384 bytes, linear)
  580 07:30:03.867145  <6>[    0.599565] TCP bind hash table entries: 4096 (order: 4, 65536 bytes, linear)
  581 07:30:03.873271  <6>[    0.607286] TCP: Hash tables configured (established 4096 bind 4096)
  582 07:30:03.879422  <6>[    0.614225] UDP hash table entries: 256 (order: 1, 8192 bytes, linear)
  583 07:30:03.885478  <6>[    0.621237] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes, linear)
  584 07:30:03.892238  <6>[    0.628851] NET: Registered PF_UNIX/PF_LOCAL protocol family
  585 07:30:03.984860  <6>[    0.718882] RPC: Registered named UNIX socket transport module.
  586 07:30:03.985243  <6>[    0.725332] RPC: Registered udp transport module.
  587 07:30:03.990922  <6>[    0.730442] RPC: Registered tcp transport module.
  588 07:30:03.998336  <6>[    0.735563] RPC: Registered tcp-with-tls transport module.
  589 07:30:04.004373  <6>[    0.741471] RPC: Registered tcp NFSv4.1 backchannel transport module.
  590 07:30:04.011716  <6>[    0.748390] PCI: CLS 0 bytes, default 64
  591 07:30:04.017257  <5>[    0.754264] Initialise system trusted keyrings
  592 07:30:04.035189  <6>[    0.771644] Trying to unpack rootfs image as initramfs...
  593 07:30:04.108973  <6>[    0.842290] workingset: timestamp_bits=30 max_order=17 bucket_order=0
  594 07:30:04.114487  <6>[    0.849815] squashfs: version 4.0 (2009/01/31) Phillip Lougher
  595 07:30:04.150554  <5>[    0.889528] NFS: Registering the id_resolver key type
  596 07:30:04.156711  <5>[    0.895194] Key type id_resolver registered
  597 07:30:04.161566  <5>[    0.899773] Key type id_legacy registered
  598 07:30:04.168961  <6>[    0.904243] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
  599 07:30:04.176917  <6>[    0.911410] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
  600 07:30:04.252955  <5>[    0.992855] Key type asymmetric registered
  601 07:30:04.259189  <5>[    0.997383] Asymmetric key parser 'x509' registered
  602 07:30:04.267719  <6>[    1.002871] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 246)
  603 07:30:04.272707  <6>[    1.010758] io scheduler mq-deadline registered
  604 07:30:04.281956  <6>[    1.015737] io scheduler kyber registered
  605 07:30:04.282333  <6>[    1.020191] io scheduler bfq registered
  606 07:30:04.387583  <6>[    1.122643] ledtrig-cpu: registered to indicate activity on CPUs
  607 07:30:04.731676  <6>[    1.466887] Serial: 8250/16550 driver, 5 ports, IRQ sharing enabled
  608 07:30:04.774029  <6>[    1.513861] msm_serial: driver initialized
  609 07:30:04.780146  <6>[    1.518663] SuperH (H)SCI(F) driver initialized
  610 07:30:04.786263  <6>[    1.523918] STMicroelectronics ASC driver initialized
  611 07:30:04.788683  <6>[    1.529520] STM32 USART driver initialized
  612 07:30:04.896831  <6>[    1.636369] brd: module loaded
  613 07:30:04.941797  <6>[    1.681422] loop: module loaded
  614 07:30:04.981066  <6>[    1.719908] CAN device driver interface
  615 07:30:04.988312  <6>[    1.725328] bgmac_bcma: Broadcom 47xx GBit MAC driver loaded
  616 07:30:04.994240  <6>[    1.732507] e1000e: Intel(R) PRO/1000 Network Driver
  617 07:30:04.999312  <6>[    1.737895] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
  618 07:30:05.005432  <6>[    1.744359] igb: Intel(R) Gigabit Ethernet Network Driver
  619 07:30:05.014864  <6>[    1.750182] igb: Copyright (c) 2007-2014 Intel Corporation.
  620 07:30:05.025930  <6>[    1.759710] pegasus: Pegasus/Pegasus II USB Ethernet driver
  621 07:30:05.032292  <6>[    1.765896] usbcore: registered new interface driver pegasus
  622 07:30:05.035818  <6>[    1.772053] usbcore: registered new interface driver asix
  623 07:30:05.040871  <6>[    1.777904] usbcore: registered new interface driver ax88179_178a
  624 07:30:05.046982  <6>[    1.784514] usbcore: registered new interface driver cdc_ether
  625 07:30:05.053099  <6>[    1.790811] usbcore: registered new interface driver smsc75xx
  626 07:30:05.061737  <6>[    1.797047] usbcore: registered new interface driver smsc95xx
  627 07:30:05.067797  <6>[    1.803279] usbcore: registered new interface driver net1080
  628 07:30:05.073871  <6>[    1.809405] usbcore: registered new interface driver cdc_subset
  629 07:30:05.077443  <6>[    1.815819] usbcore: registered new interface driver zaurus
  630 07:30:05.084711  <6>[    1.821886] usbcore: registered new interface driver cdc_ncm
  631 07:30:05.095343  <6>[    1.831574] usbcore: registered new interface driver usb-storage
  632 07:30:05.105524  <6>[    1.843196] i2c_dev: i2c /dev entries driver
  633 07:30:05.129941  <5>[    1.862094] cpuidle: enable-method property 'ti,am3352' found operations
  634 07:30:05.136109  <6>[    1.871518] sdhci: Secure Digital Host Controller Interface driver
  635 07:30:05.144601  <6>[    1.878288] sdhci: Copyright(c) Pierre Ossman
  636 07:30:05.150732  <6>[    1.884789] Synopsys Designware Multimedia Card Interface Driver
  637 07:30:05.156209  <6>[    1.892815] sdhci-pltfm: SDHCI platform and OF driver helper
  638 07:30:05.170562  <6>[    1.902971] usbcore: registered new interface driver usbhid
  639 07:30:05.170957  <6>[    1.909002] usbhid: USB HID core driver
  640 07:30:05.184216  <6>[    1.920720] NET: Registered PF_INET6 protocol family
  641 07:30:05.633816  <6>[    2.373333] Segment Routing with IPv6
  642 07:30:05.639889  <6>[    2.377481] In-situ OAM (IOAM) with IPv6
  643 07:30:05.645986  <6>[    2.382007] sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver
  644 07:30:05.653359  <6>[    2.389330] NET: Registered PF_PACKET protocol family
  645 07:30:05.659453  <6>[    2.394921] can: controller area network core
  646 07:30:05.665568  <6>[    2.399748] NET: Registered PF_CAN protocol family
  647 07:30:05.665944  <6>[    2.404978] can: raw protocol
  648 07:30:05.669082  <6>[    2.408304] can: broadcast manager protocol
  649 07:30:05.675452  <6>[    2.412903] can: netlink gateway - max_hops=1
  650 07:30:05.681560  <5>[    2.418447] Key type dns_resolver registered
  651 07:30:05.687601  <6>[    2.423518] ThumbEE CPU extension supported.
  652 07:30:05.689921  <5>[    2.428208] Registering SWP/SWPB emulation handler
  653 07:30:05.698055  <3>[    2.433908] omap_voltage_late_init: Voltage driver support not added
  654 07:30:05.895340  <5>[    2.632123] Loading compiled-in X.509 certificates
  655 07:30:06.035267  <6>[    2.761668] platform 44e10800.pinmux: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800/clkout2-pins
  656 07:30:06.041976  <6>[    2.778436] pinctrl-single 44e10800.pinmux: 142 pins, size 568
  657 07:30:06.068852  <3>[    2.802831] ti-sysc 44e31000.target-module: probe with driver ti-sysc failed with error -16
  658 07:30:06.268630  <3>[    3.003084] ti-sysc 48040000.target-module: probe with driver ti-sysc failed with error -16
  659 07:30:06.464712  <6>[    3.203027] OMAP GPIO hardware version 0.1
  660 07:30:06.485907  <6>[    3.222230] omap-mailbox 480c8000.mailbox: omap mailbox rev 0x400
  661 07:30:06.548326  <4>[    3.283652] at24 2-0054: supply vcc not found, using dummy regulator
  662 07:30:06.581118  <4>[    3.317039] at24 2-0055: supply vcc not found, using dummy regulator
  663 07:30:06.620393  <4>[    3.356233] at24 2-0056: supply vcc not found, using dummy regulator
  664 07:30:06.661678  <4>[    3.396908] at24 2-0057: supply vcc not found, using dummy regulator
  665 07:30:06.698736  <6>[    3.434961] omap_i2c 4819c000.i2c: bus 2 rev0.11 at 100 kHz
  666 07:30:06.751860  <3>[    3.485034] 48000000.interconnect:segment@200000:target-module@0:mpu@0:fck: device ID is greater than 24
  667 07:30:06.776998  <6>[    3.506344] platform 4830e000.lcdc: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
  668 07:30:06.798782  <4>[    3.533178] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
  669 07:30:06.806769  <4>[    3.541719] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
  670 07:30:06.906049  <6>[    3.645640] Freeing initrd memory: 15032K
  671 07:30:06.914000  <6>[    3.650381] omap_rng 48310000.rng: Random Number Generator ver. 20
  672 07:30:06.937878  <5>[    3.677259] random: crng init done
  673 07:30:06.986476  <6>[    3.721818] davinci_mdio 4a101000.mdio: davinci mdio revision 1.6, bus freq 1000000
  674 07:30:07.070665  <6>[    3.804255] davinci_mdio 4a101000.mdio: phy[0]: device 4a101000.mdio:00, driver SMSC LAN8710/LAN8720
  675 07:30:07.075546  <6>[    3.814588] cpsw-switch 4a100000.switch: initialized cpsw ale version 1.4
  676 07:30:07.085321  <6>[    3.821924] cpsw-switch 4a100000.switch: ALE Table size 1024, Policers 0
  677 07:30:07.095293  <6>[    3.829374] cpsw-switch 4a100000.switch: cpts: overflow check period 500 (jiffies)
  678 07:30:07.104956  <6>[    3.837522] cpsw-switch 4a100000.switch: CPTS: ref_clk_freq:250000000 calc_mult:2147483648 calc_shift:29 error:0 nsec/sec
  679 07:30:07.112312  <6>[    3.849163] cpsw-switch 4a100000.switch: Detected MACID = 04:79:b7:e7:06:e0
  680 07:30:07.126455  <5>[    3.858291] cpsw-switch 4a100000.switch: initialized (regs 0x4a100000, pool size 256) hw_ver:0019010C 1.12 (0)
  681 07:30:07.154684  <3>[    3.888616] debugfs: Directory '49000000.dma' with parent 'dmaengine' already present!
  682 07:30:07.160263  <6>[    3.897222] edma 49000000.dma: TI EDMA DMA engine driver
  683 07:30:07.233626  <3>[    3.966485] target-module@4b000000:target-module@140000:pmu@0:fck: device ID is greater than 24
  684 07:30:07.247934  <6>[    3.980986] hw perfevents: enabled with armv7_cortex_a8 PMU driver, 5 (8000000f) counters available
  685 07:30:07.261686  <3>[    3.998220] l3-aon-clkctrl:0000:0: failed to disable
  686 07:30:07.316118  <6>[    4.050452] 44e09000.serial: ttyS0 at MMIO 0x44e09000 (irq = 36, base_baud = 3000000) is a 8250
  687 07:30:07.322184  <6>[    4.059976] printk: legacy console [ttyS0] enabled
  688 07:30:07.329539  <6>[    4.059976] printk: legacy console [ttyS0] enabled
  689 07:30:07.335643  <6>[    4.070323] printk: legacy bootconsole [omap8250] disabled
  690 07:30:07.338897  <6>[    4.070323] printk: legacy bootconsole [omap8250] disabled
  691 07:30:07.369414  <4>[    4.102663] tps65217-pmic: Failed to locate of_node [id: -1]
  692 07:30:07.372612  <4>[    4.110099] tps65217-bl: Failed to locate of_node [id: -1]
  693 07:30:07.390384  <6>[    4.130329] tps65217 0-0024: TPS65217 ID 0xe version 1.2
  694 07:30:07.410039  <6>[    4.137324] platform 4830e000.lcdc: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
  695 07:30:07.422280  <6>[    4.151055] i2c 0-0070: Fixed dependency cycle(s) with /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
  696 07:30:07.425520  <6>[    4.162950] omap_i2c 44e0b000.i2c: bus 0 rev0.11 at 400 kHz
  697 07:30:07.448412  <6>[    4.183172] omap_gpio 44e07000.gpio: Could not set line 6 debounce to 200000 microseconds (-22)
  698 07:30:07.454402  <6>[    4.192339] sdhci-omap 48060000.mmc: Got CD GPIO
  699 07:30:07.462460  <4>[    4.197458] sdhci-omap 48060000.mmc: supply pbias not found, using dummy regulator
  700 07:30:07.478154  <4>[    4.211260] sdhci-omap 48060000.mmc: supply vqmmc not found, using dummy regulator
  701 07:30:07.484396  <4>[    4.220059] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
  702 07:30:07.493615  <4>[    4.228704] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
  703 07:30:07.592815  <6>[    4.328633] at24 0-0050: 32768 byte 24c256 EEPROM, writable, 1 bytes/write
  704 07:30:07.633225  <6>[    4.367593] mmc0: SDHCI controller on 48060000.mmc [48060000.mmc] using External DMA
  705 07:30:07.678366  <6>[    4.412013] mmc1: SDHCI controller on 481d8000.mmc [481d8000.mmc] using External DMA
  706 07:30:07.685169  <6>[    4.420813] cpsw-switch 4a100000.switch: starting ndev. mode: dual_mac
  707 07:30:07.752347  <6>[    4.482303] mmc1: new high speed MMC card at address 0001
  708 07:30:07.752528  <6>[    4.490393] mmcblk1: mmc1:0001 M62704 3.56 GiB
  709 07:30:07.767973  <6>[    4.502500] SMSC LAN8710/LAN8720 4a101000.mdio:00: attached PHY driver (mii_bus:phy_addr=4a101000.mdio:00, irq=POLL)
  710 07:30:07.776305  <6>[    4.513730]  mmcblk1: p1
  711 07:30:07.781845  <6>[    4.519276] mmcblk1boot0: mmc1:0001 M62704 2.00 MiB
  712 07:30:07.794667  <6>[    4.531540] mmcblk1boot1: mmc1:0001 M62704 2.00 MiB
  713 07:30:07.808507  <6>[    4.543898] mmcblk1rpmb: mmc1:0001 M62704 512 KiB, chardev (236:0)
  714 07:30:09.938694  <6>[    6.672874] cpsw-switch 4a100000.switch eth0: Link is Up - 100Mbps/Full - flow control off
  715 07:30:10.042301  <5>[    6.701885] Sending DHCP requests ., OK
  716 07:30:10.053269  <6>[    6.786280] IP-Config: Got DHCP answer from 172.16.3.3, my address is 172.16.3.191
  717 07:30:10.053652  <6>[    6.794373] IP-Config: Complete:
  718 07:30:10.067955  <6>[    6.797911]      device=eth0, hwaddr=04:79:b7:e7:06:e0, ipaddr=172.16.3.191, mask=255.255.255.0, gw=172.16.3.3
  719 07:30:10.072885  <6>[    6.808347]      host=172.16.3.191, domain=denx.de, nis-domain=(none)
  720 07:30:10.077600  <6>[    6.815184]      bootserver=172.16.3.33, rootserver=172.16.3.3, rootpath=
  721 07:30:10.082621  <6>[    6.815222]      nameserver0=172.16.3.3
  722 07:30:10.089960  <6>[    6.826533]      ntpserver0=172.16.3.3
  723 07:30:10.096111  <6>[    6.832096] clk: Disabling unused clocks
  724 07:30:10.096491  <6>[    6.836714] PM: genpd: Disabling unused power domains
  725 07:30:10.124515  <6>[    6.853243] Freeing unused kernel image (initmem) memory: 2048K
  726 07:30:10.124930  <6>[    6.863166] Run /init as init process
  727 07:30:10.148306  Loading, please wait...
  728 07:30:10.226239  Starting systemd-udevd version 252.22-1~deb12u1
  729 07:30:13.302368  <4>[   10.035129] am335x-phy-driver 47401300.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
  730 07:30:13.435910  <4>[   10.168842] am335x-phy-driver 47401b00.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
  731 07:30:13.572278  <6>[   10.312757] musb-hdrc musb-hdrc.1: MUSB HDRC host driver
  732 07:30:13.582665  <6>[   10.318433] musb-hdrc musb-hdrc.1: new USB bus registered, assigned bus number 1
  733 07:30:13.849499  <6>[   10.587834] hub 1-0:1.0: USB hub found
  734 07:30:13.923453  <6>[   10.660666] hub 1-0:1.0: 1 port detected
  735 07:30:14.016924  <6>[   10.755413] tda998x 0-0070: found TDA19988
  736 07:30:16.785937  Begin: Loading essential drivers ... done.
  737 07:30:16.791969  Begin: Running /scripts/init-premount ... done.
  738 07:30:16.798033  Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
  739 07:30:16.810920  Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
  740 07:30:16.811304  Device /sys/class/net/eth0 found
  741 07:30:16.811610  done.
  742 07:30:16.883146  Begin: Waiting up to 180 secs for any network device to become available ... done.
  743 07:30:16.964579  IP-Config: eth0 hardware address 04:79:b7:e7:06:e0 mtu 1500 DHCP
  744 07:30:17.022463  IP-Config: eth0 complete (dhcp from 172.16.3.3):
  745 07:30:17.033408   address: 172.16.3.191     broadcast: 172.16.3.255     netmask: 255.255.255.0   
  746 07:30:17.036981   gateway: 172.16.3.3       dns0     : 172.16.3.3       dns1   : 0.0.0.0         
  747 07:30:17.041895   domain : denx.de                                                         
  748 07:30:17.048037   rootserver: 172.16.3.33 rootpath: 
  749 07:30:17.052402   filename  : this-host-is-not-configured.kpxe
  750 07:30:17.106529  done.
  751 07:30:17.120283  Begin: Running /scripts/nfs-bottom ... done.
  752 07:30:17.189374  Begin: Running /scripts/init-bottom ... done.
  753 07:30:18.708181  <30>[   15.444352] systemd[1]: System time before build time, advancing clock.
  754 07:30:18.956623  <30>[   15.666866] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
  755 07:30:18.966032  <30>[   15.703615] systemd[1]: Detected architecture arm.
  756 07:30:18.978503  
  757 07:30:18.978891  Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
  758 07:30:18.979203  
  759 07:30:19.006056  <30>[   15.742638] systemd[1]: Hostname set to <debian-bookworm-armhf>.
  760 07:30:21.331773  <30>[   18.067533] systemd[1]: Queued start job for default target graphical.target.
  761 07:30:21.348520  <30>[   18.082659] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
  762 07:30:21.356405  [[0;32m  OK  [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
  763 07:30:21.381483  <30>[   18.115670] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
  764 07:30:21.389537  [[0;32m  OK  [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
  765 07:30:21.410430  <30>[   18.144818] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
  766 07:30:21.418753  [[0;32m  OK  [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
  767 07:30:21.439397  <30>[   18.173830] systemd[1]: Created slice user.slice - User and Session Slice.
  768 07:30:21.446185  [[0;32m  OK  [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
  769 07:30:21.474525  <30>[   18.203194] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
  770 07:30:21.481249  [[0;32m  OK  [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
  771 07:30:21.499113  <30>[   18.233085] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
  772 07:30:21.507561  [[0;32m  OK  [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
  773 07:30:21.536815  <30>[   18.262789] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
  774 07:30:21.549216  <30>[   18.283225] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
  775 07:30:21.553596           Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
  776 07:30:21.577827  <30>[   18.312345] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
  777 07:30:21.585774  [[0;32m  OK  [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
  778 07:30:21.609187  <30>[   18.342715] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
  779 07:30:21.616282  [[0;32m  OK  [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
  780 07:30:21.639355  <30>[   18.372843] systemd[1]: Reached target paths.target - Path Units.
  781 07:30:21.643664  [[0;32m  OK  [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
  782 07:30:21.667926  <30>[   18.402482] systemd[1]: Reached target remote-fs.target - Remote File Systems.
  783 07:30:21.674651  [[0;32m  OK  [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
  784 07:30:21.697580  <30>[   18.432486] systemd[1]: Reached target slices.target - Slice Units.
  785 07:30:21.703549  [[0;32m  OK  [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
  786 07:30:21.728428  <30>[   18.462621] systemd[1]: Reached target swap.target - Swaps.
  787 07:30:21.732665  [[0;32m  OK  [0m] Reached target [0;1;39mswap.target[0m - Swaps.
  788 07:30:21.759068  <30>[   18.492688] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
  789 07:30:21.766184  [[0;32m  OK  [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
  790 07:30:21.789154  <30>[   18.523396] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
  791 07:30:21.799571  [[0;32m  OK  [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
  792 07:30:21.883959  <30>[   18.612931] systemd[1]: systemd-journald-audit.socket - Journal Audit Socket was skipped because of an unmet condition check (ConditionSecurity=audit).
  793 07:30:21.896552  <30>[   18.630564] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
  794 07:30:21.904815  [[0;32m  OK  [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
  795 07:30:21.931255  <30>[   18.666272] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
  796 07:30:21.943087  [[0;32m  OK  [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
  797 07:30:21.972509  <30>[   18.704732] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
  798 07:30:21.978786  [[0;32m  OK  [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
  799 07:30:22.003686  <30>[   18.737209] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
  800 07:30:22.009737  [[0;32m  OK  [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
  801 07:30:22.042423  <30>[   18.775234] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
  802 07:30:22.049694  [[0;32m  OK  [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
  803 07:30:22.075558  <30>[   18.803481] systemd[1]: dev-hugepages.mount - Huge Pages File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/mm/hugepages).
  804 07:30:22.092304  <30>[   18.819953] systemd[1]: dev-mqueue.mount - POSIX Message Queue File System was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/mqueue).
  805 07:30:22.143999  <30>[   18.878724] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
  806 07:30:22.167565           Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
  807 07:30:22.230033  <30>[   18.964937] systemd[1]: Mounting sys-kernel-tracing.mount - Kernel Trace File System...
  808 07:30:22.250420           Mounting [0;1;39msys-kernel-tracin…[0m - Kernel Trace File System...
  809 07:30:22.359637  <30>[   19.093209] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
  810 07:30:22.374699           Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
  811 07:30:22.408649  <30>[   19.142964] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
  812 07:30:22.419592           Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
  813 07:30:22.457807  <30>[   19.193468] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
  814 07:30:22.479271           Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
  815 07:30:22.511208  <30>[   19.246902] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
  816 07:30:22.533632           Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
  817 07:30:22.588943  <30>[   19.323073] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
  818 07:30:22.607021           Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
  819 07:30:22.668384  <30>[   19.403305] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
  820 07:30:22.678256           Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
  821 07:30:22.718088  <30>[   19.452670] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
  822 07:30:22.724814           Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
  823 07:30:22.756399  <28>[   19.486407] systemd[1]: systemd-journald.service: unit configures an IP firewall, but the local system does not support BPF/cgroup firewalling.
  824 07:30:22.782165  <28>[   19.516138] systemd[1]: (This warning is only shown for the first unit using IP firewalling.)
  825 07:30:22.828777  <30>[   19.565167] systemd[1]: Starting systemd-journald.service - Journal Service...
  826 07:30:22.847846           Starting [0;1;39msystemd-journald.service[0m - Journal Service...
  827 07:30:22.918073  <30>[   19.654028] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
  828 07:30:22.943972           Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
  829 07:30:23.000254  <30>[   19.734955] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
  830 07:30:23.038511           Starting [0;1;39msystemd-network-g… units from Kernel command line...
  831 07:30:23.123375  <30>[   19.856362] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
  832 07:30:23.167843           Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
  833 07:30:23.240253  <30>[   19.974596] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
  834 07:30:23.282785           Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
  835 07:30:23.350436  <30>[   20.085043] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
  836 07:30:23.400083  [[0;32m  OK  [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
  837 07:30:23.407318  <30>[   20.143844] systemd[1]: Mounted sys-kernel-tracing.mount - Kernel Trace File System.
  838 07:30:23.441378  [[0;32m  OK  [0m] Mounted [0;1;39msys-kernel-tracing…nt[0m - Kernel Trace File System.
  839 07:30:23.475745  <30>[   20.209933] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
  840 07:30:23.502369  [[0;32m  OK  [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
  841 07:30:23.651534  <30>[   20.388116] systemd[1]: modprobe@configfs.service: Deactivated successfully.
  842 07:30:23.688882  <30>[   20.423768] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
  843 07:30:23.716735  [[0;32m  OK  [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
  844 07:30:23.738767  <30>[   20.473620] systemd[1]: Started systemd-journald.service - Journal Service.
  845 07:30:23.745638  [[0;32m  OK  [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
  846 07:30:23.778755  [[0;32m  OK  [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
  847 07:30:23.808553  [[0;32m  OK  [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
  848 07:30:23.840637  [[0;32m  OK  [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
  849 07:30:23.869386  [[0;32m  OK  [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
  850 07:30:23.893882  [[0;32m  OK  [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
  851 07:30:23.928066  [[0;32m  OK  [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
  852 07:30:23.950552  [[0;32m  OK  [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
  853 07:30:23.980377  [[0;32m  OK  [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
  854 07:30:24.002379  [[0;32m  OK  [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
  855 07:30:24.068632           Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
  856 07:30:24.142916           Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
  857 07:30:24.220307           Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
  858 07:30:24.309180           Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
  859 07:30:24.367499           Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
  860 07:30:24.520371  [[0;32m  OK  [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
  861 07:30:24.527424  <46>[   21.263489] systemd-journald[163]: Received client request to flush runtime journal.
  862 07:30:24.740808  [[0;32m  OK  [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
  863 07:30:24.786808  [[0;32m  OK  [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
  864 07:30:24.849175           Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
  865 07:30:24.907465  [[0;32m  OK  [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
  866 07:30:25.859444  [[0;32m  OK  [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
  867 07:30:25.878661  [[0;32m  OK  [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
  868 07:30:25.896559  [[0;32m  OK  [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
  869 07:30:25.978130           Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
  870 07:30:26.629534  [[0;32m  OK  [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
  871 07:30:26.697567           Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
  872 07:30:28.476924  [[0;32m  OK  [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
  873 07:30:29.101846  <5>[   25.837358] cfg80211: Loading compiled-in X.509 certificates for regulatory database
  874 07:30:29.809222  [[0;32m  OK  [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
  875 07:30:30.463057  [[0;32m  OK  [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
  876 07:30:30.535608  <5>[   27.274355] Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
  877 07:30:30.596907  <5>[   27.332748] Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
  878 07:30:30.609326  <4>[   27.344327] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
  879 07:30:30.614888  <6>[   27.353415] cfg80211: failed to load regulatory.db
  880 07:30:32.043211  [[0;32m  OK  [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
  881 07:30:39.302507  [[0;32m  OK  [0m] Reached target [0;1;39mnetwork.target[0m - Network.
  882 07:30:39.332242  [[0;32m  OK  [0m] Reached target [0;1;39musb-gadget.…m - Hardware activated USB gadget.
  883 07:30:39.359238  [[0;32m  OK  [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
  884 07:30:39.417585           Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
  885 07:30:39.465382           Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
  886 07:30:39.530045           Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
  887 07:30:39.569262           Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
  888 07:30:39.629544           Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
  889 07:30:39.708977  [[0;32m  OK  [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
  890 07:30:39.736872  [[0;32m  OK  [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
  891 07:30:39.766604  [[0;32m  OK  [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
  892 07:30:39.796386  [[0;32m  OK  [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
  893 07:30:40.301280  [[0;32m  OK  [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
  894 07:30:40.477758           Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
  895 07:30:40.506634           Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
  896 07:30:40.821918  [[0;32m  OK  [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
  897 07:30:41.201603  [[0;32m  OK  [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
  898 07:30:41.227200  [[0;32m  OK  [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
  899 07:30:41.248850  [[0;32m  OK  [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
  900 07:30:41.267868  [[0;32m  OK  [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
  901 07:30:41.390665  [[0;32m  OK  [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
  902 07:30:41.497570  [[0;32m  OK  [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
  903 07:30:41.527498  [[0;32m  OK  [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
  904 07:30:41.688371  [[0;32m  OK  [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
  905 07:30:41.775130  [[0;32m  OK  [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
  906 07:30:41.797474  [[0;32m  OK  [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
  907 07:30:41.830881  [[0;32m  OK  [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
  908 07:30:41.857419  [[0;32m  OK  [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
  909 07:30:41.879686  [[0;32m  OK  [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
  910 07:30:41.967602           Starting [0;1;39malsa-restore.serv…- Save/Restore Sound Card State...
  911 07:30:41.993212           Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
  912 07:30:42.206408           Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
  913 07:30:42.369142           Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
  914 07:30:42.408647           Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
  915 07:30:42.438486  [[0;32m  OK  [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
  916 07:30:42.547334  [[0;32m  OK  [0m] Finished [0;1;39malsa-restore.serv…m - Save/Restore Sound Card State.
  917 07:30:42.567493  [[0;32m  OK  [0m] Reached target [0;1;39msound.target[0m - Sound Card.
  918 07:30:42.776810           Starting [0;1;39msystemd-hostnamed.service[0m - Hostname Service...
  919 07:30:42.790895  [[0;32m  OK  [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
  920 07:30:42.839640  [[0;32m  OK  [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
  921 07:30:42.908341  [[0;32m  OK  [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
  922 07:30:42.938287  [[0;32m  OK  [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
  923 07:30:43.128568  [[0;32m  OK  [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
  924 07:30:43.479101  [[0;32m  OK  [0m] Started [0;1;39msystemd-hostnamed.service[0m - Hostname Service.
  925 07:30:43.774014  [[0;32m  OK  [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
  926 07:30:43.822738  [[0;32m  OK  [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
  927 07:30:43.852539  [[0;32m  OK  [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
  928 07:30:43.940369           Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
  929 07:30:44.156952  [[0;32m  OK  [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
  930 07:30:44.393322  
  931 07:30:44.393704  Debian GNU/Linux 12 debian-bookworm-armh
  932 07:30:44.400005  debian-bookworm-armhf login: root (automatic login)
  933 07:30:44.400384  
  934 07:30:44.808310  Linux debian-bookworm-armhf 6.12.0-rc5-next-20241104 #1 SMP Mon Nov  4 07:04:33 UTC 2024 armv7l
  935 07:30:44.808695  
  936 07:30:44.813113  The programs included with the Debian GNU/Linux system are free software;
  937 07:30:44.821748  the exact distribution terms for each program are described in the
  938 07:30:44.827923  individual files in /usr/share/doc/*/copyright.
  939 07:30:44.828301  
  940 07:30:44.833550  Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
  941 07:30:44.833929  permitted by applicable law.
  942 07:30:49.655113  Unable to match end of the kernel message
  944 07:30:49.656199  Setting prompt string to ['/ #']
  945 07:30:49.656617  end: 2.4.4.1 login-action (duration 00:00:47) [common]
  947 07:30:49.657580  end: 2.4.4 auto-login-action (duration 00:00:48) [common]
  948 07:30:49.658000  start: 2.4.5 expect-shell-connection (timeout 00:03:12) [common]
  949 07:30:49.658335  Setting prompt string to ['/ #']
  950 07:30:49.658629  Forcing a shell prompt, looking for ['/ #']
  952 07:30:49.709380  / # 
  953 07:30:49.709880  expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
  954 07:30:49.710242  Waiting using forced prompt support (timeout 00:02:30)
  955 07:30:49.719753  
  956 07:30:49.720452  end: 2.4.5 expect-shell-connection (duration 00:00:00) [common]
  957 07:30:49.720914  start: 2.4.6 export-device-env (timeout 00:03:12) [common]
  958 07:30:49.721302  Sending with 10 millisecond of delay
  960 07:30:54.777968  / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/1216189/extract-nfsrootfs-fliunf5j'
  961 07:30:54.788670  export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/1216189/extract-nfsrootfs-fliunf5j'
  962 07:30:54.792365  Sending with 10 millisecond of delay
  964 07:30:56.832317  / # export NFS_SERVER_IP='172.16.3.3'
  965 07:30:56.842990  export NFS_SERVER_IP='172.16.3.3'
  966 07:30:56.846309  end: 2.4.6 export-device-env (duration 00:00:07) [common]
  967 07:30:56.846812  end: 2.4 uboot-commands (duration 00:01:55) [common]
  968 07:30:56.847281  end: 2 uboot-action (duration 00:01:55) [common]
  969 07:30:56.847724  start: 3 lava-test-retry (timeout 00:05:55) [common]
  970 07:30:56.848182  start: 3.1 lava-test-shell (timeout 00:05:55) [common]
  971 07:30:56.848554  Using namespace: common
  973 07:30:56.949555  / # #
  974 07:30:56.950073  lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
  975 07:30:56.957384  #
  976 07:30:56.963152  Using /lava-1216189
  978 07:30:57.064140  / # export SHELL=/bin/bash
  979 07:30:57.070139  export SHELL=/bin/bash
  981 07:30:57.176709  / # . /lava-1216189/environment
  982 07:30:57.184310  . /lava-1216189/environment
  984 07:30:57.296160  / # /lava-1216189/bin/lava-test-runner /lava-1216189/0
  985 07:30:57.296669  Test shell timeout: 10s (minimum of the action and connection timeout)
  986 07:30:57.303938  /lava-1216189/bin/lava-test-runner /lava-1216189/0
  987 07:30:57.837792  + export TESTRUN_ID=0_timesync-off
  988 07:30:57.845946  + TESTRUN_ID=0_timesync-off
  989 07:30:57.846333  + cd /lava-1216189/0/tests/0_timesync-off
  990 07:30:57.846647  ++ cat uuid
  991 07:30:57.865152  + UUID=1216189_1.6.2.4.1
  992 07:30:57.865535  + set +x
  993 07:30:57.870169  <LAVA_SIGNAL_STARTRUN 0_timesync-off 1216189_1.6.2.4.1>
  994 07:30:57.870821  Received signal: <STARTRUN> 0_timesync-off 1216189_1.6.2.4.1
  995 07:30:57.871162  Starting test lava.0_timesync-off (1216189_1.6.2.4.1)
  996 07:30:57.871563  Skipping test definition patterns.
  997 07:30:57.873377  + systemctl stop systemd-timesyncd
  998 07:30:58.207641  + set +x
  999 07:30:58.208261  Received signal: <ENDRUN> 0_timesync-off 1216189_1.6.2.4.1
 1000 07:30:58.208663  Ending use of test pattern.
 1001 07:30:58.209024  Ending test lava.0_timesync-off (1216189_1.6.2.4.1), duration 0.34
 1003 07:30:58.211955  <LAVA_SIGNAL_ENDRUN 0_timesync-off 1216189_1.6.2.4.1>
 1004 07:30:58.562233  + export TESTRUN_ID=1_kselftest-dt
 1005 07:30:58.570243  + TESTRUN_ID=1_kselftest-dt
 1006 07:30:58.570625  + cd /lava-1216189/0/tests/1_kselftest-dt
 1007 07:30:58.570938  ++ cat uuid
 1008 07:30:58.588426  + UUID=1216189_1.6.2.4.5
 1009 07:30:58.588838  + set +x
 1010 07:30:58.594505  <LAVA_SIGNAL_STARTRUN 1_kselftest-dt 1216189_1.6.2.4.5>
 1011 07:30:58.594890  + cd ./automated/linux/kselftest/
 1012 07:30:58.595443  Received signal: <STARTRUN> 1_kselftest-dt 1216189_1.6.2.4.5
 1013 07:30:58.595757  Starting test lava.1_kselftest-dt (1216189_1.6.2.4.5)
 1014 07:30:58.596113  Skipping test definition patterns.
 1015 07:30:58.620894  + ./kselftest.sh -c dt -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/next/master/next-20241104/arm/multi_v7_defconfig/clang-17/kselftest.tar.xz -L '' -S /dev/null -b beaglebone-black -g next -e '' -p /opt/kselftests/mainline/ -n 1 -i 1 -E ''
 1016 07:30:58.781816  INFO: install_deps skipped
 1017 07:30:59.351297  --2024-01-26 21:49:16--  http://storage.kernelci.org/next/master/next-20241104/arm/multi_v7_defconfig/clang-17/kselftest.tar.xz
 1018 07:30:59.403057  Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
 1019 07:30:59.562358  Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
 1020 07:30:59.722667  HTTP request sent, awaiting response... 200 OK
 1021 07:30:59.723049  Length: 2744232 (2.6M) [application/octet-stream]
 1022 07:30:59.727516  Saving to: 'kselftest_armhf.tar.gz'
 1023 07:30:59.727895  
 1024 07:31:01.327039  kselftest_armhf.tar   0%[                    ]       0  --.-KB/s               kselftest_armhf.tar   1%[                    ]  49.92K   161KB/s               kselftest_armhf.tar   8%[>                   ] 218.67K   347KB/s               kselftest_armhf.tar  24%[===>                ] 643.35K   667KB/s               kselftest_armhf.tar  57%[==========>         ]   1.52M  1.30MB/s               kselftest_armhf.tar  80%[===============>    ]   2.10M  1.50MB/s               kselftest_armhf.tar 100%[===================>]   2.62M  1.64MB/s    in 1.6s    
 1025 07:31:01.327449  
 1026 07:31:01.827566  2024-01-26 21:49:18 (1.64 MB/s) - 'kselftest_armhf.tar.gz' saved [2744232/2744232]
 1027 07:31:01.827988  
 1028 07:31:02.095910  tar: ./nsfs/pidns: time stamp 2024-11-04 07:24:19 is 24399299.612553079 s in the future
 1029 07:31:02.330509  tar: ./nsfs/config: time stamp 2024-10-28 11:31:42 is 23809342.376204287 s in the future
 1030 07:31:02.469075  tar: ./nsfs/owner: time stamp 2024-11-04 07:24:19 is 24399299.23703387 s in the future
 1031 07:31:02.538942  tar: ./nsfs: time stamp 2024-11-04 07:25:01 is 24399341.167687329 s in the future
 1032 07:31:02.721862  tar: ./cachestat/test_cachestat: time stamp 2024-11-04 07:22:19 is 24399178.986915745 s in the future
 1033 07:31:02.779090  tar: ./cachestat: time stamp 2024-11-04 07:24:51 is 24399330.92838412 s in the future
 1034 07:31:02.925204  tar: ./kselftest/prefix.pl: time stamp 2024-11-04 07:24:51 is 24399330.782172787 s in the future
 1035 07:31:03.054582  tar: ./kselftest/ktap_helpers.sh: time stamp 2024-10-28 11:31:42 is 23809341.653960829 s in the future
 1036 07:31:03.220567  tar: ./kselftest/runner.sh: time stamp 2024-11-04 07:24:51 is 24399330.486913037 s in the future
 1037 07:31:03.341161  tar: ./kselftest/ksft.py: time stamp 2024-11-04 07:24:51 is 24399330.365436912 s in the future
 1038 07:31:03.467292  tar: ./kselftest/module.sh: time stamp 2024-11-04 07:24:51 is 24399330.240280787 s in the future
 1039 07:31:03.524275  tar: ./kselftest: time stamp 2024-10-28 11:31:42 is 23809341.181872287 s in the future
 1040 07:31:03.678668  tar: ./cpufreq/governor.sh: time stamp 2024-10-28 11:31:42 is 23809341.028439537 s in the future
 1041 07:31:03.804479  tar: ./cpufreq/config: time stamp 2024-10-28 11:31:42 is 23809340.902583287 s in the future
 1042 07:31:03.943308  tar: ./cpufreq/cpufreq.sh: time stamp 2024-10-28 11:31:42 is 23809340.764877703 s in the future
 1043 07:31:04.100925  tar: ./cpufreq/special-tests.sh: time stamp 2024-10-28 11:31:42 is 23809340.607676162 s in the future
 1044 07:31:04.245889  tar: ./cpufreq/module.sh: time stamp 2024-10-28 11:31:42 is 23809340.462453912 s in the future
 1045 07:31:04.362217  tar: ./cpufreq/cpu.sh: time stamp 2024-10-28 11:31:42 is 23809340.343751537 s in the future
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 1048 07:31:04.683681  tar: ./kvm/config: time stamp 2024-10-28 11:31:42 is 23809340.023567995 s in the future
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 1051 07:31:05.006287  tar: ./amd-pstate/gitsource.sh: time stamp 2024-10-28 11:31:42 is 23809339.701325453 s in the future
 1052 07:31:05.131164  tar: ./amd-pstate/run.sh: time stamp 2024-10-28 11:31:42 is 23809339.576889203 s in the future
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 1054 07:31:05.392622  tar: ./amd-pstate/config: time stamp 2024-10-28 11:31:42 is 23809339.314606662 s in the future
 1055 07:31:05.510520  tar: ./amd-pstate/tbench.sh: time stamp 2024-10-28 11:31:42 is 23809339.196772495 s in the future
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 1057 07:31:05.723181  tar: ./pidfd/pidfd_poll_test: time stamp 2024-11-04 07:24:20 is 24399296.984241828 s in the future
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 1059 07:31:06.006983  tar: ./pidfd/config: time stamp 2024-10-28 11:31:42 is 23809338.700630495 s in the future
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 1063 07:31:06.632453  tar: ./pidfd/pidfd_fdinfo_test: time stamp 2024-11-04 07:24:20 is 24399296.075107745 s in the future
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 1065 07:31:06.827329  tar: ./pidfd: time stamp 2024-11-04 07:25:01 is 24399336.878946036 s in the future
 1066 07:31:06.990191  tar: ./alsa/utimer-test: time stamp 2024-11-04 07:22:19 is 24399174.716951328 s in the future
 1067 07:31:07.127482  tar: ./alsa/pcm-test.conf: time stamp 2024-10-28 11:31:42 is 23809337.579885453 s in the future
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 1069 07:31:07.460987  tar: ./alsa/mixer-test: time stamp 2024-11-04 07:22:18 is 24399173.246339745 s in the future
 1070 07:31:07.590175  tar: ./alsa/libatest.so: time stamp 2024-11-04 07:22:18 is 24399173.116497745 s in the future
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 1073 07:31:08.077167  tar: ./alsa/conf.d/Lenovo_ThinkPad_P1_Gen2.conf: time stamp 2024-10-28 11:31:42 is 23809336.632939328 s in the future
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 1075 07:31:08.188381  tar: ./alsa: time stamp 2024-11-04 07:24:51 is 24399325.516899578 s in the future
 1076 07:31:08.351385  tar: ./rust/test_probe_samples.sh: time stamp 2024-10-28 11:31:42 is 23809336.356917161 s in the future
 1077 07:31:08.474236  tar: ./rust/config: time stamp 2024-10-28 11:31:42 is 23809336.23259687 s in the future
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 1082 07:31:09.066591  tar: ./net/net_helper.sh: time stamp 2024-10-28 11:31:42 is 23809335.639692536 s in the future
 1083 07:31:09.190440  tar: ./net/lib.sh: time stamp 2024-10-28 11:31:42 is 23809335.515311203 s in the future
 1084 07:31:09.363056  tar: ./net/netfilter/nft_tproxy_tcp.sh: time stamp 2024-10-28 11:31:42 is 23809335.344430994 s in the future
 1085 07:31:09.507002  tar: ./net/netfilter/nf_nat_edemux.sh: time stamp 2024-10-28 11:31:42 is 23809335.201788244 s in the future
 1086 07:31:09.639389  tar: ./net/netfilter/conntrack_sctp_collision.sh: time stamp 2024-10-28 11:31:42 is 23809335.069264244 s in the future
 1087 07:31:09.777079  tar: ./net/netfilter/audit_logread: time stamp 2024-11-04 07:24:11 is 24399283.931273703 s in the future
 1088 07:31:09.927436  tar: ./net/netfilter/br_netfilter.sh: time stamp 2024-10-28 11:31:42 is 23809334.780603203 s in the future
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 1092 07:31:10.465528  tar: ./net/netfilter/nft_concat_range.sh: time stamp 2024-10-28 11:31:42 is 23809334.243492994 s in the future
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 1094 07:31:10.748349  tar: ./net/netfilter/nft_queue.sh: time stamp 2024-10-28 11:31:42 is 23809333.959845411 s in the future
 1095 07:31:10.870264  tar: ./net/netfilter/vxlan_mtu_frag.sh: time stamp 2024-10-28 11:31:42 is 23809333.838791578 s in the future
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 1097 07:31:11.133179  tar: ./net/netfilter/nft_synproxy.sh: time stamp 2024-10-28 11:31:42 is 23809333.575215619 s in the future
 1098 07:31:11.265536  tar: ./net/netfilter/conntrack_reverse_clash: time stamp 2024-11-04 07:24:11 is 24399282.442908744 s in the future
 1099 07:31:11.411585  tar: ./net/netfilter/nft_nat_zones.sh: time stamp 2024-10-28 11:31:42 is 23809333.296594786 s in the future
 1100 07:31:11.532379  tar: ./net/netfilter/nft_tproxy_udp.sh: time stamp 2024-10-28 11:31:42 is 23809333.175840828 s in the future
 1101 07:31:11.675254  tar: ./net/netfilter/nft_audit.sh: time stamp 2024-10-28 11:31:42 is 23809333.033042453 s in the future
 1102 07:31:11.807662  tar: ./net/netfilter/sctp_collision: time stamp 2024-11-04 07:24:11 is 24399281.900643453 s in the future
 1103 07:31:11.928251  tar: ./net/netfilter/nft_meta.sh: time stamp 2024-10-28 11:31:42 is 23809332.779622411 s in the future
 1104 07:31:12.048941  tar: ./net/netfilter/config: time stamp 2024-10-28 11:31:42 is 23809332.658930327 s in the future
 1105 07:31:12.213314  tar: ./net/netfilter/packetdrill/conntrack_syn_challenge_ack.pkt: time stamp 2024-10-28 11:31:42 is 23809332.496968286 s in the future
 1106 07:31:12.384332  tar: ./net/netfilter/packetdrill/conntrack_rst_invalid.pkt: time stamp 2024-10-28 11:31:42 is 23809332.325124286 s in the future
 1107 07:31:12.604519  tar: ./net/netfilter/packetdrill/conntrack_synack_old.pkt: time stamp 2024-10-28 11:31:42 is 23809332.105000994 s in the future
 1108 07:31:12.723538  tar: ./net/netfilter/packetdrill/conntrack_synack_reuse.pkt: time stamp 2024-10-28 11:31:42 is 23809331.986609619 s in the future
 1109 07:31:12.845716  tar: ./net/netfilter/packetdrill/common.sh: time stamp 2024-10-28 11:31:42 is 23809331.863091036 s in the future
 1110 07:31:12.998657  tar: ./net/netfilter/packetdrill/conntrack_ack_loss_stall.pkt: time stamp 2024-10-28 11:31:42 is 23809331.711841744 s in the future
 1111 07:31:13.138914  tar: ./net/netfilter/packetdrill/conntrack_inexact_rst.pkt: time stamp 2024-10-28 11:31:42 is 23809331.571168077 s in the future
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 1113 07:31:13.320130  tar: ./net/netfilter/rpath.sh: time stamp 2024-10-28 11:31:42 is 23809331.386332786 s in the future
 1114 07:31:13.451423  tar: ./net/netfilter/xt_string.sh: time stamp 2024-10-28 11:31:42 is 23809331.256702952 s in the future
 1115 07:31:13.660842  tar: ./net/netfilter/bridge_brouter.sh: time stamp 2024-10-28 11:31:42 is 23809331.047063369 s in the future
 1116 07:31:13.827143  tar: ./net/netfilter/nft_nat.sh: time stamp 2024-10-28 11:31:42 is 23809330.881285286 s in the future
 1117 07:31:13.993201  tar: ./net/netfilter/nf_conntrack_packetdrill.sh: time stamp 2024-10-28 11:31:42 is 23809330.714904702 s in the future
 1118 07:31:14.163760  tar: ./net/netfilter/nft_fib.sh: time stamp 2024-10-28 11:31:42 is 23809330.544220786 s in the future
 1119 07:31:14.306985  tar: ./net/netfilter/conntrack_ipip_mtu.sh: time stamp 2024-10-28 11:31:42 is 23809330.402034869 s in the future
 1120 07:31:14.445009  tar: ./net/netfilter/conntrack_tcp_unreplied.sh: time stamp 2024-10-28 11:31:42 is 23809330.264240369 s in the future
 1121 07:31:14.602924  tar: ./net/netfilter/conntrack_dump_flush: time stamp 2024-11-04 07:24:10 is 24399278.106227827 s in the future
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 1127 07:31:15.407521  tar: ./net/netfilter/conntrack_vrf.sh: time stamp 2024-10-28 11:31:42 is 23809329.300717619 s in the future
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 1137 07:31:17.148069  tar: ./net/tcp_ao/icmps-discard_ipv4: time stamp 2024-11-04 07:24:14 is 24399279.558951744 s in the future
 1138 07:31:17.346058  tar: ./net/tcp_ao/self-connect_ipv6: time stamp 2024-11-04 07:24:18 is 24399283.362570202 s in the future
 1139 07:31:17.499579  tar: ./net/tcp_ao/config: time stamp 2024-10-28 11:31:42 is 23809327.207711077 s in the future
 1140 07:31:17.716362  tar: ./net/tcp_ao/seq-ext_ipv4: time stamp 2024-11-04 07:24:15 is 24399279.990869993 s in the future
 1141 07:31:17.898529  tar: ./net/tcp_ao/connect_ipv4: time stamp 2024-11-04 07:24:13 is 24399277.808497743 s in the future
 1142 07:31:18.104336  tar: ./net/tcp_ao/unsigned-md5_ipv6: time stamp 2024-11-04 07:24:19 is 24399283.603577368 s in the future
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 1144 07:31:18.542136  tar: ./net/tcp_ao/key-management_ipv4: time stamp 2024-11-04 07:24:14 is 24399278.165723577 s in the future
 1145 07:31:18.731642  tar: ./net/tcp_ao/restore_ipv6: time stamp 2024-11-04 07:24:18 is 24399281.974658618 s in the future
 1146 07:31:18.928138  tar: ./net/tcp_ao/seq-ext_ipv6: time stamp 2024-11-04 07:24:18 is 24399281.778154202 s in the future
 1147 07:31:19.134539  tar: ./net/tcp_ao/setsockopt-closed_ipv4: time stamp 2024-11-04 07:24:16 is 24399279.573824785 s in the future
 1148 07:31:19.333147  tar: ./net/tcp_ao/connect_ipv6: time stamp 2024-11-04 07:24:16 is 24399279.373490035 s in the future
 1149 07:31:19.509867  tar: ./net/tcp_ao/rst_ipv6: time stamp 2024-11-04 07:24:18 is 24399281.19936216 s in the future
 1150 07:31:19.694960  tar: ./net/tcp_ao/rst_ipv4: time stamp 2024-11-04 07:24:15 is 24399278.011062743 s in the future
 1151 07:31:19.934934  tar: ./net/tcp_ao/icmps-accept_ipv4: time stamp 2024-11-04 07:24:14 is 24399276.773016618 s in the future
 1152 07:31:20.133891  tar: ./net/tcp_ao/setsockopt-closed_ipv6: time stamp 2024-11-04 07:24:19 is 24399281.573229243 s in the future
 1153 07:31:20.258813  tar: ./net/tcp_ao/settings: time stamp 2024-10-28 11:31:42 is 23809324.448683576 s in the future
 1154 07:31:20.458875  tar: ./net/tcp_ao/icmps-accept_ipv6: time stamp 2024-11-04 07:24:17 is 24399279.248601035 s in the future
 1155 07:31:20.659899  tar: ./net/tcp_ao/unsigned-md5_ipv4: time stamp 2024-11-04 07:24:16 is 24399278.047893618 s in the future
 1156 07:31:20.918124  tar: ./net/tcp_ao/key-management_ipv6: time stamp 2024-11-04 07:24:17 is 24399278.789394576 s in the future
 1157 07:31:20.978476  tar: ./net/tcp_ao: time stamp 2024-11-04 07:25:01 is 24399322.727036493 s in the future
 1158 07:31:21.126873  tar: ./net/packetdrill/tcp_inq_server.pkt: time stamp 2024-10-28 11:31:42 is 23809323.581354743 s in the future
 1159 07:31:21.270506  tar: ./net/packetdrill/tcp_slow_start_slow-start-ack-per-2pkt-send-5pkt.pkt: time stamp 2024-10-28 11:31:42 is 23809323.440382076 s in the future
 1160 07:31:21.415808  tar: ./net/packetdrill/tcp_zerocopy_client.pkt: time stamp 2024-10-28 11:31:42 is 23809323.293151785 s in the future
 1161 07:31:21.550570  tar: ./net/packetdrill/tcp_zerocopy_fastopen-client.pkt: time stamp 2024-10-28 11:31:42 is 23809323.159638951 s in the future
 1162 07:31:21.676531  tar: ./net/packetdrill/defaults.sh: time stamp 2024-10-28 11:31:42 is 23809323.030985035 s in the future
 1163 07:31:21.813670  tar: ./net/packetdrill/tcp_slow_start_slow-start-ack-per-2pkt-send-6pkt.pkt: time stamp 2024-10-28 11:31:42 is 23809322.89759741 s in the future
 1164 07:31:21.921196  tar: ./net/packetdrill/tcp_slow_start_slow-start-ack-per-4pkt.pkt: time stamp 2024-10-28 11:31:42 is 23809322.788386743 s in the future
 1165 07:31:22.054987  tar: ./net/packetdrill/tcp_zerocopy_epoll_oneshot.pkt: time stamp 2024-10-28 11:31:42 is 23809322.654852493 s in the future
 1166 07:31:22.167713  tar: ./net/packetdrill/tcp_md5_md5-only-on-client-ack.pkt: time stamp 2024-10-28 11:31:42 is 23809322.53887491 s in the future
 1167 07:31:22.290078  tar: ./net/packetdrill/tcp_slow_start_slow-start-app-limited-9-packets-out.pkt: time stamp 2024-10-28 11:31:42 is 23809322.421910993 s in the future
 1168 07:31:22.397335  tar: ./net/packetdrill/tcp_slow_start_slow-start-fq-ack-per-2pkt.pkt: time stamp 2024-10-28 11:31:42 is 23809322.312856243 s in the future
 1169 07:31:22.525617  tar: ./net/packetdrill/tcp_zerocopy_maxfrags.pkt: time stamp 2024-10-28 11:31:42 is 23809322.183508826 s in the future
 1170 07:31:22.649354  tar: ./net/packetdrill/config: time stamp 2024-10-28 11:31:42 is 23809322.05698866 s in the future
 1171 07:31:22.855269  tar: ./net/packetdrill/tcp_slow_start_slow-start-ack-per-1pkt.pkt: time stamp 2024-10-28 11:31:42 is 23809321.854689618 s in the future
 1172 07:31:22.962741  tar: ./net/packetdrill/tcp_zerocopy_fastopen-server.pkt: time stamp 2024-10-28 11:31:42 is 23809321.745735826 s in the future
 1173 07:31:23.090152  tar: ./net/packetdrill/tcp_slow_start_slow-start-after-win-update.pkt: time stamp 2024-10-28 11:31:42 is 23809321.620514409 s in the future
 1174 07:31:23.251133  tar: ./net/packetdrill/tcp_slow_start_slow-start-ack-per-2pkt.pkt: time stamp 2024-10-28 11:31:42 is 23809321.458274993 s in the future
 1175 07:31:23.369364  tar: ./net/packetdrill/tcp_zerocopy_closed.pkt: time stamp 2024-10-28 11:31:42 is 23809321.337596743 s in the future
 1176 07:31:23.498780  tar: ./net/packetdrill/set_sysctls.py: time stamp 2024-10-28 11:31:42 is 23809321.207986743 s in the future
 1177 07:31:23.652432  tar: ./net/packetdrill/tcp_slow_start_slow-start-after-idle.pkt: time stamp 2024-10-28 11:31:42 is 23809321.057655826 s in the future
 1178 07:31:23.795394  tar: ./net/packetdrill/ksft_runner.sh: time stamp 2024-10-28 11:31:42 is 23809320.912109284 s in the future
 1179 07:31:23.911641  tar: ./net/packetdrill/tcp_slow_start_slow-start-app-limited.pkt: time stamp 2024-10-28 11:31:42 is 23809320.795412284 s in the future
 1180 07:31:24.030501  tar: ./net/packetdrill/tcp_zerocopy_small.pkt: time stamp 2024-10-28 11:31:42 is 23809320.678218409 s in the future
 1181 07:31:24.171230  tar: ./net/packetdrill/tcp_zerocopy_batch.pkt: time stamp 2024-10-28 11:31:42 is 23809320.536410618 s in the future
 1182 07:31:24.296491  tar: ./net/packetdrill/tcp_inq_client.pkt: time stamp 2024-10-28 11:31:42 is 23809320.411687076 s in the future
 1183 07:31:24.412362  tar: ./net/packetdrill/tcp_zerocopy_epoll_edge.pkt: time stamp 2024-10-28 11:31:42 is 23809320.295044409 s in the future
 1184 07:31:24.531309  tar: ./net/packetdrill/tcp_zerocopy_epoll_exclusive.pkt: time stamp 2024-10-28 11:31:42 is 23809320.177780409 s in the future
 1185 07:31:24.664580  tar: ./net/packetdrill/tcp_zerocopy_basic.pkt: time stamp 2024-10-28 11:31:42 is 23809320.044177784 s in the future
 1186 07:31:24.726987  tar: ./net/packetdrill: time stamp 2024-10-28 11:31:42 is 23809319.978579368 s in the future
 1187 07:31:24.870044  tar: ./net/hsr/hsr_ping.sh: time stamp 2024-10-28 11:31:42 is 23809319.835605326 s in the future
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 1189 07:31:25.129227  tar: ./net/hsr/hsr_redbox.sh: time stamp 2024-10-28 11:31:42 is 23809319.577099743 s in the future
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 1937 07:34:10.455659  tar: ./timers/nsleep-lat: time stamp 2024-11-04 07:24:33 is 24399125.242832056 s in the future
 1938 07:34:10.717674  tar: ./timers/change_skew: time stamp 2024-11-04 07:24:34 is 24399125.97930664 s in the future
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 1960 07:34:17.240513  tar: ./ir: time stamp 2024-11-04 07:24:56 is 24399141.456292639 s in the future
 1961 07:34:17.608233  tar: ./membarrier/membarrier_test_single_thread: time stamp 2024-11-04 07:23:57 is 24399082.090701722 s in the future
 1962 07:34:17.910510  tar: ./membarrier/membarrier_test_multi_thread: time stamp 2024-11-04 07:23:57 is 24399081.787885722 s in the future
 1963 07:34:18.078102  tar: ./membarrier: time stamp 2024-11-04 07:24:58 is 24399142.617267889 s in the future
 1964 07:34:18.436223  tar: ./power_supply/test_power_supply_properties.sh: time stamp 2024-10-28 11:31:42 is 23809146.263197472 s in the future
 1965 07:34:18.734192  tar: ./power_supply/helpers.sh: time stamp 2024-10-28 11:31:42 is 23809145.963717347 s in the future
 1966 07:34:18.901368  tar: ./power_supply: time stamp 2024-11-04 07:25:01 is 24399144.796143347 s in the future
 1967 07:34:19.255301  tar: ./timens/vfork_exec: time stamp 2024-11-04 07:24:32 is 24399115.441783347 s in the future
 1968 07:34:19.501529  tar: ./timens/clock_nanosleep: time stamp 2024-11-04 07:24:32 is 24399115.195164472 s in the future
 1969 07:34:19.821802  tar: ./timens/timer: time stamp 2024-11-04 07:24:32 is 24399114.878350513 s in the future
 1970 07:34:20.161008  tar: ./timens/gettime_perf: time stamp 2024-11-04 07:24:32 is 24399114.536074972 s in the future
 1971 07:34:20.489967  tar: ./timens/config: time stamp 2024-10-28 11:31:42 is 23809144.206556888 s in the future
 1972 07:34:20.819236  tar: ./timens/exec: time stamp 2024-11-04 07:24:32 is 24399113.876420847 s in the future
 1973 07:34:21.136940  tar: ./timens/timens: time stamp 2024-11-04 07:24:31 is 24399112.559381347 s in the future
 1974 07:34:21.455904  tar: ./timens/timerfd: time stamp 2024-11-04 07:24:31 is 24399112.240579013 s in the future
 1975 07:34:21.771679  tar: ./timens/procfs: time stamp 2024-11-04 07:24:32 is 24399112.925027722 s in the future
 1976 07:34:22.122225  tar: ./timens/futex: time stamp 2024-11-04 07:24:32 is 24399112.57446868 s in the future
 1977 07:34:22.259560  tar: ./timens: time stamp 2024-11-04 07:25:04 is 24399144.435776305 s in the future
 1978 07:34:22.736092  tar: ./perf_events/remove_on_exec: time stamp 2024-11-04 07:24:20 is 24399099.96147418 s in the future
 1979 07:34:23.048994  tar: ./perf_events/sigtrap_threads: time stamp 2024-11-04 07:24:19 is 24399098.64836543 s in the future
 1980 07:34:23.383590  tar: ./perf_events/watermark_signal: time stamp 2024-11-04 07:24:20 is 24399099.314235471 s in the future
 1981 07:34:23.699675  tar: ./perf_events/config: time stamp 2024-10-28 11:31:42 is 23809140.997053555 s in the future
 1982 07:34:24.057268  tar: ./perf_events/settings: time stamp 2024-10-28 11:31:42 is 23809140.640120346 s in the future
 1983 07:34:24.174621  tar: ./perf_events: time stamp 2024-11-04 07:25:01 is 24399139.521400971 s in the future
 1984 07:34:24.589893  tar: ./iommu/iommufd_fail_nth: time stamp 2024-11-04 07:23:48 is 24399066.107325305 s in the future
 1985 07:34:25.010426  tar: ./iommu/iommufd: time stamp 2024-11-04 07:23:47 is 24399064.686714721 s in the future
 1986 07:34:25.306362  tar: ./iommu/config: time stamp 2024-10-28 11:31:42 is 23809139.389411471 s in the future
 1987 07:34:25.451226  tar: ./iommu: time stamp 2024-11-04 07:24:56 is 24399133.244507179 s in the future
 1988 07:34:25.794347  tar: ./sysctl/config: time stamp 2024-10-28 11:31:42 is 23809138.902189221 s in the future
 1989 07:34:26.078545  tar: ./sysctl/sysctl.sh: time stamp 2024-10-28 11:31:42 is 23809138.617663513 s in the future
 1990 07:34:26.236222  tar: ./sysctl: time stamp 2024-11-04 07:25:04 is 24399140.459882513 s in the future
 1991 07:34:26.600491  tar: ./efivarfs/config: time stamp 2024-10-28 11:31:42 is 23809138.095540763 s in the future
 1992 07:34:26.935519  tar: ./efivarfs/open-unlink: time stamp 2024-11-04 07:23:39 is 24399054.761715221 s in the future
 1993 07:34:27.245325  tar: ./efivarfs/create-read: time stamp 2024-11-04 07:23:39 is 24399054.452218846 s in the future
 1994 07:34:27.520290  tar: ./efivarfs/efivarfs.sh: time stamp 2024-10-28 11:31:42 is 23809137.177359888 s in the future
 1995 07:34:27.658887  tar: ./efivarfs: time stamp 2024-11-04 07:24:54 is 24399129.036887429 s in the future
 1996 07:34:28.064434  tar: ./intel_pstate/run.sh: time stamp 2024-10-30 10:28:17 is 23978131.631901221 s in the future
 1997 07:34:28.185003  tar: ./intel_pstate: time stamp 2024-11-04 07:24:56 is 24399130.510772762 s in the future
 1998 07:34:28.608370  tar: ./filesystems/file_stressor: time stamp 2024-11-04 07:23:40 is 24399054.089455512 s in the future
 1999 07:34:28.942166  tar: ./filesystems/fat/config: time stamp 2024-10-28 11:31:42 is 23809135.755412387 s in the future
 2000 07:34:29.271860  tar: ./filesystems/fat/rename_exchange: time stamp 2024-11-04 07:23:41 is 24399054.426043304 s in the future
 2001 07:34:29.570345  tar: ./filesystems/fat/run_fat_tests.sh: time stamp 2024-10-28 11:31:42 is 23809135.129464429 s in the future
 2002 07:34:29.688894  tar: ./filesystems/fat: time stamp 2024-11-04 07:24:54 is 24399127.007049762 s in the future
 2003 07:34:30.008191  tar: ./filesystems/dnotify_test: time stamp 2024-11-04 07:23:40 is 24399052.688951137 s in the future
 2004 07:34:30.476442  tar: ./filesystems/epoll/epoll_wakeup_test: time stamp 2024-11-04 07:23:41 is 24399053.22213447 s in the future
 2005 07:34:30.591603  tar: ./filesystems/epoll: time stamp 2024-11-04 07:24:54 is 24399126.104663679 s in the future
 2006 07:34:30.967844  tar: ./filesystems/binderfs/config: time stamp 2024-10-28 11:31:42 is 23809133.729805012 s in the future
 2007 07:34:31.269349  tar: ./filesystems/binderfs/binderfs_test: time stamp 2024-11-04 07:23:41 is 24399052.428839554 s in the future
 2008 07:34:31.442354  tar: ./filesystems/binderfs: time stamp 2024-11-04 07:24:54 is 24399125.25434072 s in the future
 2009 07:34:31.720945  tar: ./filesystems/devpts_pts: time stamp 2024-11-04 07:23:40 is 24399050.976314054 s in the future
 2010 07:34:32.089072  tar: ./filesystems/overlayfs/dev_in_maps: time stamp 2024-11-04 07:23:42 is 24399052.609104595 s in the future
 2011 07:34:32.394920  tar: ./filesystems/overlayfs/set_layers_via_fds: time stamp 2024-11-04 07:23:42 is 24399052.302471845 s in the future
 2012 07:34:32.524961  tar: ./filesystems/overlayfs: time stamp 2024-11-04 07:24:55 is 24399125.171646345 s in the future
 2013 07:34:32.934298  tar: ./filesystems/statmount/statmount_test: time stamp 2024-11-04 07:23:42 is 24399051.764642637 s in the future
 2014 07:34:33.298053  tar: ./filesystems/statmount/statmount_test_ns: time stamp 2024-11-04 07:23:42 is 24399051.40074722 s in the future
 2015 07:34:33.476097  tar: ./filesystems/statmount: time stamp 2024-11-04 07:24:55 is 24399124.22081347 s in the future
 2016 07:34:33.599596  tar: ./filesystems: time stamp 2024-11-04 07:24:55 is 24399124.095426845 s in the future
 2017 07:34:33.980063  tar: ./firmware/fw_upload.sh: time stamp 2024-10-28 11:31:42 is 23809130.716425387 s in the future
 2018 07:34:34.278267  tar: ./firmware/fw_run_tests.sh: time stamp 2024-10-28 11:31:42 is 23809130.419148845 s in the future
 2019 07:34:34.551877  tar: ./firmware/fw_lib.sh: time stamp 2024-10-28 11:31:42 is 23809130.144066595 s in the future
 2020 07:34:34.888889  tar: ./firmware/config: time stamp 2024-10-28 11:31:42 is 23809129.80728322 s in the future
 2021 07:34:35.212265  tar: ./firmware/fw_filesystem.sh: time stamp 2024-10-28 11:31:42 is 23809129.48450172 s in the future
 2022 07:34:35.486386  tar: ./firmware/fw_namespace: time stamp 2024-11-04 07:23:42 is 24399049.21096972 s in the future
 2023 07:34:35.801460  tar: ./firmware/fw_fallback.sh: time stamp 2024-10-28 11:31:42 is 23809128.89494272 s in the future
 2024 07:34:36.134214  tar: ./firmware/settings: time stamp 2024-10-28 11:31:42 is 23809128.561084011 s in the future
 2025 07:34:36.262259  tar: ./firmware: time stamp 2024-11-04 07:24:55 is 24399121.433003886 s in the future
 2026 07:34:36.628937  tar: ./memfd/memfd_test: time stamp 2024-11-04 07:23:58 is 24399064.067021011 s in the future
 2027 07:34:36.957669  tar: ./memfd/config: time stamp 2024-10-28 11:31:42 is 23809127.738218803 s in the future
 2028 07:34:37.291412  tar: ./memfd/run_fuse_test.sh: time stamp 2024-10-28 11:31:42 is 23809127.404606595 s in the future
 2029 07:34:37.659061  tar: ./memfd/fuse_test: time stamp 2024-11-04 07:23:58 is 24399063.036886428 s in the future
 2030 07:34:37.982583  tar: ./memfd/fuse_mnt: time stamp 2024-11-04 07:23:58 is 24399062.71294522 s in the future
 2031 07:34:38.487686  tar: ./memfd/run_hugetlbfs_test.sh: time stamp 2024-10-28 11:31:42 is 23809126.209060386 s in the future
 2032 07:34:38.653519  tar: ./memfd: time stamp 2024-11-04 07:24:58 is 24399122.040970928 s in the future
 2033 07:34:39.047498  tar: ./gpio/gpio-chip-info: time stamp 2024-11-04 07:23:45 is 24399048.648640011 s in the future
 2034 07:34:39.347778  tar: ./gpio/gpio-mockup-sysfs.sh: time stamp 2024-10-28 11:31:42 is 23809125.349323803 s in the future
 2035 07:34:39.646792  tar: ./gpio/config: time stamp 2024-10-28 11:31:42 is 23809125.048759011 s in the future
 2036 07:34:39.969157  tar: ./gpio/gpio-line-name: time stamp 2024-11-04 07:23:45 is 24399047.726178553 s in the future
 2037 07:34:40.248463  tar: ./gpio/gpio-sim.sh: time stamp 2024-10-28 11:31:42 is 23809124.446695136 s in the future
 2038 07:34:40.540939  tar: ./gpio/gpio-mockup.sh: time stamp 2024-10-28 11:31:42 is 23809124.154740928 s in the future
 2039 07:34:40.833600  tar: ./gpio/gpio-mockup-cdev: time stamp 2024-11-04 07:23:44 is 24399045.862220844 s in the future
 2040 07:34:41.001484  tar: ./gpio: time stamp 2024-11-04 07:24:56 is 24399117.692788636 s in the future
 2041 07:34:41.316277  tar: ./kselftest-list.txt: time stamp 2024-11-04 07:25:08 is 24399129.379267803 s in the future
 2042 07:34:41.675816  tar: ./pstore/pstore_tests: time stamp 2024-10-28 11:31:42 is 23809123.020295636 s in the future
 2043 07:34:41.950561  tar: ./pstore/config: time stamp 2024-10-28 11:31:42 is 23809122.744973802 s in the future
 2044 07:34:42.220406  tar: ./pstore/pstore_crash_test: time stamp 2024-10-28 11:31:42 is 23809122.477069469 s in the future
 2045 07:34:42.495385  tar: ./pstore/pstore_post_reboot_tests: time stamp 2024-10-28 11:31:42 is 23809122.201643177 s in the future
 2046 07:34:42.777431  tar: ./pstore/common_tests: time stamp 2024-10-28 11:31:42 is 23809121.917874011 s in the future
 2047 07:34:42.951987  tar: ./pstore: time stamp 2024-11-04 07:25:02 is 24399121.742952636 s in the future
 2048 07:34:43.314842  tar: ./signal/mangle_uc_sigmask: time stamp 2024-11-04 07:24:30 is 24399089.383842386 s in the future
 2049 07:34:43.594260  tar: ./signal/sas: time stamp 2024-11-04 07:24:30 is 24399089.100253761 s in the future
 2050 07:34:43.761276  tar: ./signal: time stamp 2024-11-04 07:25:03 is 24399121.932851219 s in the future
 2051 07:34:44.135220  tar: ./vDSO/vdso_test_gettimeofday: time stamp 2024-11-04 07:24:37 is 24399095.560500136 s in the future
 2052 07:34:44.411085  tar: ./vDSO/vdso_test_getcpu: time stamp 2024-11-04 07:24:37 is 24399095.285055802 s in the future
 2053 07:34:44.735544  tar: ./vDSO/vdso_test_clock_getres: time stamp 2024-11-04 07:24:37 is 24399094.961064219 s in the future
 2054 07:34:45.041003  tar: ./vDSO/vdso_test_correctness: time stamp 2024-11-04 07:24:37 is 24399094.655636677 s in the future
 2055 07:34:45.357934  tar: ./vDSO/vdso_test_abi: time stamp 2024-11-04 07:24:37 is 24399094.338515719 s in the future
 2056 07:34:45.704527  tar: ./vDSO/vdso_test_getrandom: time stamp 2024-11-04 07:24:38 is 24399094.991357719 s in the future
 2057 07:34:46.006788  tar: ./vDSO/vdso_test_chacha: time stamp 2024-11-04 07:24:38 is 24399094.689564677 s in the future
 2058 07:34:46.149349  tar: ./vDSO: time stamp 2024-11-04 07:25:05 is 24399121.545702552 s in the future
 2059 07:34:46.482189  tar: ./mqueue/mq_open_tests: time stamp 2024-11-04 07:24:00 is 24399056.214154135 s in the future
 2060 07:34:46.781233  tar: ./mqueue/mq_perf_tests: time stamp 2024-11-04 07:24:01 is 24399056.913636802 s in the future
 2061 07:34:46.946141  tar: ./mqueue: time stamp 2024-11-04 07:24:59 is 24399114.74783301 s in the future
 2062 07:34:47.336108  tar: ./sync/sync_test: time stamp 2024-11-04 07:24:31 is 24399086.358263177 s in the future
 2063 07:34:47.638340  tar: ./sync/config: time stamp 2024-10-28 11:31:42 is 23809117.057672593 s in the future
 2064 07:34:47.776775  tar: ./sync: time stamp 2024-11-04 07:25:04 is 24399118.918077927 s in the future
 2065 07:34:48.162274  tar: ./ipc/msgque: time stamp 2024-11-04 07:23:48 is 24399042.532121593 s in the future
 2066 07:34:48.469767  tar: ./ipc/config: time stamp 2024-10-28 11:31:42 is 23809116.22540126 s in the future
 2067 07:34:48.596449  tar: ./ipc: time stamp 2024-11-04 07:24:56 is 24399110.097720718 s in the future
 2068 07:34:49.097936  tar: ./tdx/tdx_guest_test: time stamp 2024-11-04 07:24:31 is 24399084.597394593 s in the future
 2069 07:34:49.417984  tar: ./tdx/config: time stamp 2024-10-28 11:31:42 is 23809115.277360593 s in the future
 2070 07:34:49.539433  tar: ./tdx: time stamp 2024-11-04 07:25:04 is 24399117.154620718 s in the future
 2071 07:34:49.914471  tar: ./tpm2/test_async.sh: time stamp 2024-10-28 11:31:42 is 23809114.78066651 s in the future
 2072 07:34:50.261955  tar: ./tpm2/tpm2.py: time stamp 2024-10-28 11:31:42 is 23809114.432879385 s in the future
 2073 07:34:50.641232  tar: ./tpm2/tpm2_tests.py: time stamp 2024-10-28 11:31:42 is 23809114.054555676 s in the future
 2074 07:34:50.944527  tar: ./tpm2/test_smoke.sh: time stamp 2024-10-28 11:31:42 is 23809113.750432385 s in the future
 2075 07:34:51.236106  tar: ./tpm2/settings: time stamp 2024-10-28 11:31:42 is 23809113.458226885 s in the future
 2076 07:34:51.542365  tar: ./tpm2/test_space.sh: time stamp 2024-10-28 11:31:42 is 23809113.153112468 s in the future
 2077 07:34:51.696446  tar: ./tpm2: time stamp 2024-11-04 07:25:05 is 24399115.997238718 s in the future
 2078 07:34:52.085189  tar: ./ptrace/vmaccess: time stamp 2024-11-04 07:24:24 is 24399074.609445718 s in the future
 2079 07:34:52.388321  tar: ./ptrace/get_set_sud: time stamp 2024-11-04 07:24:24 is 24399074.306920635 s in the future
 2080 07:34:52.688474  tar: ./ptrace/peeksiginfo: time stamp 2024-11-04 07:24:24 is 24399074.00677401 s in the future
 2081 07:34:53.023361  tar: ./ptrace/get_syscall_info: time stamp 2024-11-04 07:24:24 is 24399073.673018176 s in the future
 2082 07:34:53.194502  tar: ./ptrace: time stamp 2024-11-04 07:25:02 is 24399111.499419009 s in the future
 2083 07:34:53.568590  tar: ./syscall_user_dispatch/sud_benchmark: time stamp 2024-11-04 07:24:31 is 24399080.127643759 s in the future
 2084 07:34:53.894213  tar: ./syscall_user_dispatch/config: time stamp 2024-10-28 11:31:42 is 23809110.801924384 s in the future
 2085 07:34:54.205858  tar: ./syscall_user_dispatch/sud_test: time stamp 2024-11-04 07:24:31 is 24399079.490222718 s in the future
 2086 07:34:54.358228  tar: ./syscall_user_dispatch: time stamp 2024-11-04 07:25:04 is 24399112.336973093 s in the future
 2087 07:34:54.734371  tar: ./resctrl/resctrl_tests: time stamp 2024-11-04 07:24:26 is 24399073.961405051 s in the future
 2088 07:34:55.017545  tar: ./resctrl/config: time stamp 2024-10-28 11:31:42 is 23809109.677702884 s in the future
 2089 07:34:55.356847  tar: ./resctrl/settings: time stamp 2024-10-28 11:31:42 is 23809109.338777468 s in the future
 2090 07:34:55.533690  tar: ./resctrl: time stamp 2024-11-04 07:25:02 is 24399109.160323009 s in the future
 2091 07:34:55.891323  tar: ./proc/setns-sysvipc: time stamp 2024-11-04 07:24:23 is 24399069.803096301 s in the future
 2092 07:34:56.210354  tar: ./proc/read: time stamp 2024-11-04 07:24:23 is 24399069.484283509 s in the future
 2093 07:34:56.509774  tar: ./proc/proc-subset-pid: time stamp 2024-11-04 07:24:23 is 24399069.185874217 s in the future
 2094 07:34:56.836345  tar: ./proc/proc-loadavg-001: time stamp 2024-11-04 07:24:22 is 24399067.858525592 s in the future
 2095 07:34:57.268505  tar: ./proc/proc-self-map-files-002: time stamp 2024-11-04 07:24:22 is 24399067.426834926 s in the future
 2096 07:34:57.644675  tar: ./proc/proc-empty-vm: time stamp 2024-11-04 07:24:22 is 24399067.050705759 s in the future
 2097 07:34:58.028121  tar: ./proc/proc-tid0: time stamp 2024-11-04 07:24:23 is 24399067.666615634 s in the future
 2098 07:34:58.364517  tar: ./proc/proc-pid-vm: time stamp 2024-11-04 07:24:22 is 24399066.3299368 s in the future
 2099 07:34:58.639352  tar: ./proc/proc-self-isnt-kthread: time stamp 2024-11-04 07:24:22 is 24399066.055688842 s in the future
 2100 07:34:59.068509  tar: ./proc/proc-2-is-kthread: time stamp 2024-11-04 07:24:22 is 24399065.625958217 s in the future
 2101 07:34:59.447978  tar: ./proc/proc-uptime-001: time stamp 2024-11-04 07:24:23 is 24399066.246827467 s in the future
 2102 07:34:59.688374  tar: ./proc/proc-uptime-002: time stamp 2024-11-04 07:24:23 is 24399066.006499259 s in the future
 2103 07:34:59.922206  tar: ./proc/proc-self-syscall: time stamp 2024-11-04 07:24:22 is 24399064.772897259 s in the future
 2104 07:35:00.189869  tar: ./proc/proc-multiple-procfs: time stamp 2024-11-04 07:24:24 is 24399066.50442405 s in the future
 2105 07:35:00.487463  tar: ./proc/config: time stamp 2024-10-28 11:31:42 is 23809104.20619955 s in the future
 2106 07:35:00.749569  tar: ./proc/thread-self: time stamp 2024-11-04 07:24:23 is 24399064.945501509 s in the future
 2107 07:35:01.004474  tar: ./proc/setns-dcache: time stamp 2024-11-04 07:24:23 is 24399064.689828717 s in the future
 2108 07:35:01.257321  tar: ./proc/proc-self-map-files-001: time stamp 2024-11-04 07:24:22 is 24399063.438031008 s in the future
 2109 07:35:01.523775  tar: ./proc/proc-self-wchan: time stamp 2024-11-04 07:24:22 is 24399063.17165805 s in the future
 2110 07:35:01.799672  tar: ./proc/proc-fsconfig-hidepid: time stamp 2024-11-04 07:24:24 is 24399064.895583133 s in the future
 2111 07:35:02.125229  tar: ./proc/fd-002-posix-eq: time stamp 2024-11-04 07:24:21 is 24399061.569139425 s in the future
 2112 07:35:02.401056  tar: ./proc/fd-001-lookup: time stamp 2024-11-04 07:24:21 is 24399061.293810883 s in the future
 2113 07:35:02.716936  tar: ./proc/fd-003-kthread: time stamp 2024-11-04 07:24:21 is 24399060.97684855 s in the future
 2114 07:35:03.034083  tar: ./proc/self: time stamp 2024-11-04 07:24:23 is 24399062.65997905 s in the future
 2115 07:35:03.173667  tar: ./proc: time stamp 2024-11-04 07:25:02 is 24399101.519903133 s in the future
 2116 07:35:03.610041  tar: ./core/close_range_test: time stamp 2024-11-04 07:22:23 is 24398942.085325508 s in the future
 2117 07:35:03.965167  tar: ./core/unshare_test: time stamp 2024-11-04 07:22:23 is 24398941.728915008 s in the future
 2118 07:35:04.067690  tar: ./core: time stamp 2024-11-04 07:24:52 is 24399090.625675425 s in the future
 2119 07:35:04.490447  tar: ./run_kselftest.sh: time stamp 2024-11-04 07:24:51 is 24399089.2040308 s in the future
 2120 07:35:04.874027  tar: ./futex/functional/futex_wait: time stamp 2024-11-04 07:23:44 is 24399021.820808633 s in the future
 2121 07:35:05.117162  tar: ./futex/functional/run.sh: time stamp 2024-10-28 11:31:42 is 23809099.577233925 s in the future
 2122 07:35:05.420698  tar: ./futex/functional/futex_wait_private_mapped_file: time stamp 2024-11-04 07:23:44 is 24399021.276232175 s in the future
 2123 07:35:05.663954  tar: ./futex/functional/futex_wait_wouldblock: time stamp 2024-11-04 07:23:43 is 24399020.0329083 s in the future
 2124 07:35:05.922000  tar: ./futex/functional/futex_wait_timeout: time stamp 2024-11-04 07:23:43 is 24399019.7739718 s in the future
 2125 07:35:06.164350  tar: ./futex/functional/futex_wait_uninitialized_heap: time stamp 2024-11-04 07:23:44 is 24399020.532325883 s in the future
 2126 07:35:06.448008  tar: ./futex/functional/futex_requeue: time stamp 2024-11-04 07:23:44 is 24399020.248454508 s in the future
 2127 07:35:06.824594  tar: ./futex/functional/futex_requeue_pi_signal_restart: time stamp 2024-11-04 07:23:43 is 24399018.872974674 s in the future
 2128 07:35:07.105969  tar: ./futex/functional/futex_waitv: time stamp 2024-11-04 07:23:44 is 24399019.589399883 s in the future
 2129 07:35:07.398181  tar: ./futex/functional/futex_requeue_pi_mismatched_ops: time stamp 2024-11-04 07:23:43 is 24399018.299404966 s in the future
 2130 07:35:07.648970  tar: ./futex/functional/futex_requeue_pi: time stamp 2024-11-04 07:23:43 is 24399018.047613133 s in the future
 2131 07:35:07.754948  tar: ./futex/functional: time stamp 2024-11-04 07:24:55 is 24399089.938845758 s in the future
 2132 07:35:08.030700  tar: ./futex/run.sh: time stamp 2024-11-04 07:24:55 is 24399089.663518883 s in the future
 2133 07:35:08.144051  tar: ./futex: time stamp 2024-11-04 07:24:55 is 24399089.550016633 s in the future
 2134 07:35:08.276288  tar: .: time stamp 2024-11-04 07:25:08 is 24399102.416527466 s in the future
 2135 07:35:08.618142  skiplist:
 2136 07:35:08.618528  ========================================
 2137 07:35:08.624883  ========================================
 2138 07:35:09.154169  dt:test_unprobed_devices.sh
 2139 07:35:09.332169  ============== Tests to run ===============
 2140 07:35:09.342029  dt:test_unprobed_devices.sh
 2141 07:35:09.345151  ===========End Tests to run ===============
 2142 07:35:09.388445  shardfile-dt pass
 2143 07:35:09.810202  <12>[  306.563580] kselftest: Running tests in dt
 2144 07:35:09.841103  TAP version 13
 2145 07:35:09.864698  1..1
 2146 07:35:09.921700  # timeout set to 45
 2147 07:35:09.922094  # selftests: dt: test_unprobed_devices.sh
 2148 07:35:10.743398  # TAP version 13
 2149 07:35:36.512900  # 1..257
 2150 07:35:36.702470  # ok 1 / # SKIP
 2151 07:35:36.719830  # ok 2 /clk_mcasp0
 2152 07:35:36.795320  # ok 3 /clk_mcasp0_fixed # SKIP
 2153 07:35:36.872227  # ok 4 /cpus/cpu@0 # SKIP
 2154 07:35:36.944770  # ok 5 /cpus/idle-states/mpu_gate # SKIP
 2155 07:35:36.970729  # ok 6 /fixedregulator0
 2156 07:35:36.991426  # ok 7 /leds
 2157 07:35:37.008868  # ok 8 /ocp
 2158 07:35:37.033785  # ok 9 /ocp/interconnect@44c00000
 2159 07:35:37.062252  # ok 10 /ocp/interconnect@44c00000/segment@0
 2160 07:35:37.081980  # ok 11 /ocp/interconnect@44c00000/segment@100000
 2161 07:35:37.112063  # ok 12 /ocp/interconnect@44c00000/segment@100000/target-module@0
 2162 07:35:37.183036  # not ok 13 /ocp/interconnect@44c00000/segment@100000/target-module@0/cpu@0
 2163 07:35:37.206414  # ok 14 /ocp/interconnect@44c00000/segment@200000
 2164 07:35:37.231087  # ok 15 /ocp/interconnect@44c00000/segment@200000/target-module@0
 2165 07:35:37.347473  # not ok 16 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0
 2166 07:35:37.427085  # ok 17 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0 # SKIP
 2167 07:35:37.500213  # ok 18 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@0 # SKIP
 2168 07:35:37.573583  # ok 19 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@120 # SKIP
 2169 07:35:37.649183  # ok 20 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@14c # SKIP
 2170 07:35:37.724694  # ok 21 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@18 # SKIP
 2171 07:35:37.804877  # ok 22 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@1c # SKIP
 2172 07:35:37.877383  # ok 23 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@24 # SKIP
 2173 07:35:37.952608  # ok 24 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@38 # SKIP
 2174 07:35:38.028282  # ok 25 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@e8 # SKIP
 2175 07:35:38.102638  # ok 26 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400 # SKIP
 2176 07:35:38.179633  # ok 27 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@0 # SKIP
 2177 07:35:38.255161  # ok 28 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@14 # SKIP
 2178 07:35:38.331999  # ok 29 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@b0 # SKIP
 2179 07:35:38.406454  # ok 30 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600 # SKIP
 2180 07:35:38.482864  # ok 31 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600/clock@0 # SKIP
 2181 07:35:38.557147  # ok 32 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800 # SKIP
 2182 07:35:38.634907  # ok 33 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800/clock@0 # SKIP
 2183 07:35:38.711711  # ok 34 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900 # SKIP
 2184 07:35:38.785822  # ok 35 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900/clock@0 # SKIP
 2185 07:35:38.862159  # ok 36 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00 # SKIP
 2186 07:35:38.938834  # ok 37 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00/clock@0 # SKIP
 2187 07:35:39.015627  # ok 38 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-24mhz # SKIP
 2188 07:35:39.095846  # ok 39 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-32768 # SKIP
 2189 07:35:39.168360  # ok 40 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-rc32k # SKIP
 2190 07:35:39.244025  # ok 41 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clkdiv32k # SKIP
 2191 07:35:39.319947  # ok 42 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-125mhz-gclk # SKIP
 2192 07:35:39.396526  # ok 43 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-cpts-rft@520 # SKIP
 2193 07:35:39.476838  # ok 44 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4-div2 # SKIP
 2194 07:35:39.548271  # ok 45 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4@480 # SKIP
 2195 07:35:39.623756  # ok 46 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m5@484 # SKIP
 2196 07:35:39.700677  # ok 47 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m6@4d8 # SKIP
 2197 07:35:39.776292  # ok 48 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-x2 # SKIP
 2198 07:35:39.857242  # ok 49 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2-div2 # SKIP
 2199 07:35:39.930774  # ok 50 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2@4a0 # SKIP
 2200 07:35:40.006634  # ok 51 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-disp-m2@4a4 # SKIP
 2201 07:35:40.082324  # ok 52 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-mpu-m2@4a8 # SKIP
 2202 07:35:40.158070  # ok 53 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4 # SKIP
 2203 07:35:40.239008  # ok 54 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4-wkupdm # SKIP
 2204 07:35:40.315794  # ok 55 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2@4ac # SKIP
 2205 07:35:40.387060  # ok 56 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-gpio0-dbclk-mux@53c # SKIP
 2206 07:35:40.464828  # ok 57 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-ieee5000-fck-1@e4 # SKIP
 2207 07:35:40.539402  # ok 58 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3-gclk # SKIP
 2208 07:35:40.614988  # ok 59 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3s-gclk # SKIP
 2209 07:35:40.691805  # ok 60 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4-rtc-gclk # SKIP
 2210 07:35:40.768641  # ok 61 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4fw-gclk # SKIP
 2211 07:35:40.844447  # ok 62 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4hs-gclk # SKIP
 2212 07:35:40.920152  # ok 63 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4ls-gclk # SKIP
 2213 07:35:40.995844  # ok 64 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-lcd-gclk@534 # SKIP
 2214 07:35:41.074845  # ok 65 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmc # SKIP
 2215 07:35:41.151564  # ok 66 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmu-fck-1@914 # SKIP
 2216 07:35:41.224045  # ok 67 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-pruss-ocp-gclk@530 # SKIP
 2217 07:35:41.300763  # ok 68 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-sysclk-div # SKIP
 2218 07:35:41.378827  # ok 69 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-tclkin # SKIP
 2219 07:35:41.454316  # ok 70 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer1-fck@528 # SKIP
 2220 07:35:41.529069  # ok 71 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer2-fck@508 # SKIP
 2221 07:35:41.606062  # ok 72 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer3-fck@50c # SKIP
 2222 07:35:41.687532  # ok 73 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer4-fck@510 # SKIP
 2223 07:35:41.758987  # ok 74 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer5-fck@518 # SKIP
 2224 07:35:41.833682  # ok 75 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer6-fck@51c # SKIP
 2225 07:35:41.910547  # ok 76 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer7-fck@504 # SKIP
 2226 07:35:41.987043  # ok 77 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-usbotg-fck-8@47c # SKIP
 2227 07:35:42.067226  # ok 78 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-19200000 # SKIP
 2228 07:35:42.141106  # ok 79 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-24000000 # SKIP
 2229 07:35:42.214812  # ok 80 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-25000000 # SKIP
 2230 07:35:42.294723  # ok 81 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-26000000 # SKIP
 2231 07:35:42.368111  # ok 82 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-wdt1-fck@538 # SKIP
 2232 07:35:42.442903  # ok 83 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@488 # SKIP
 2233 07:35:42.519451  # ok 84 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@48c # SKIP
 2234 07:35:42.600603  # ok 85 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@490 # SKIP
 2235 07:35:42.671929  # ok 86 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@494 # SKIP
 2236 07:35:42.748577  # ok 87 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@498 # SKIP
 2237 07:35:42.825067  # ok 88 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c # SKIP
 2238 07:35:42.908246  # ok 89 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fck-div@0 # SKIP
 2239 07:35:42.982233  # ok 90 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fclk-clksel@1 # SKIP
 2240 07:35:43.059991  # ok 91 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700 # SKIP
 2241 07:35:43.136131  # ok 92 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2-div@3 # SKIP
 2242 07:35:43.209846  # ok 93 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2@7 # SKIP
 2243 07:35:43.286900  # ok 94 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-sysclkout-pre@0 # SKIP
 2244 07:35:43.313883  # ok 95 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1000
 2245 07:35:43.335430  # ok 96 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1100
 2246 07:35:43.360234  # ok 97 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1200
 2247 07:35:43.388316  # ok 98 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@c00
 2248 07:35:43.414551  # ok 99 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@d00
 2249 07:35:43.439229  # ok 100 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@e00
 2250 07:35:43.461791  # ok 101 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@f00
 2251 07:35:43.484314  # ok 102 /ocp/interconnect@44c00000/segment@200000/target-module@10000
 2252 07:35:43.594870  # not ok 103 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0
 2253 07:35:43.621330  # ok 104 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/control@620
 2254 07:35:43.647316  # ok 105 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/dma-router@f90
 2255 07:35:43.672098  # ok 106 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800
 2256 07:35:43.783881  # not ok 107 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0
 2257 07:35:43.862793  # ok 108 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-adc-tsc-fck # SKIP
 2258 07:35:43.939650  # ok 109 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-aes0-fck # SKIP
 2259 07:35:44.016819  # ok 110 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan0-fck # SKIP
 2260 07:35:44.097176  # ok 111 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan1-fck # SKIP
 2261 07:35:44.172336  # ok 112 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp0-fck # SKIP
 2262 07:35:44.247174  # ok 113 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp1-fck # SKIP
 2263 07:35:44.323350  # ok 114 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-rng-fck # SKIP
 2264 07:35:44.399035  # ok 115 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sha0-fck # SKIP
 2265 07:35:44.476716  # ok 116 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex0-fck # SKIP
 2266 07:35:44.555328  # ok 117 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex1-fck # SKIP
 2267 07:35:44.631385  # ok 118 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sys-clkin-22@40 # SKIP
 2268 07:35:44.707048  # ok 119 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664 # SKIP
 2269 07:35:44.785739  # ok 120 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm0-tbclk@0 # SKIP
 2270 07:35:44.863556  # ok 121 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm1-tbclk@1 # SKIP
 2271 07:35:44.941066  # ok 122 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm2-tbclk@2 # SKIP
 2272 07:35:44.964967  # ok 123 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/phy-gmii-sel
 2273 07:35:45.039618  # not ok 124 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/wkup_m3_ipc@1324
 2274 07:35:45.113473  # not ok 125 /ocp/interconnect@44c00000/segment@200000/target-module@31000
 2275 07:35:45.196016  # ok 126 /ocp/interconnect@44c00000/segment@200000/target-module@31000/timer@0 # SKIP
 2276 07:35:45.217522  # ok 127 /ocp/interconnect@44c00000/segment@200000/target-module@35000
 2277 07:35:45.291864  # not ok 128 /ocp/interconnect@44c00000/segment@200000/target-module@35000/wdt@0
 2278 07:35:45.313969  # ok 129 /ocp/interconnect@44c00000/segment@200000/target-module@3e000
 2279 07:35:45.389188  # not ok 130 /ocp/interconnect@44c00000/segment@200000/target-module@3e000/rtc@0
 2280 07:35:45.412937  # ok 131 /ocp/interconnect@44c00000/segment@200000/target-module@7000
 2281 07:35:45.438097  # ok 132 /ocp/interconnect@44c00000/segment@200000/target-module@7000/gpio@0
 2282 07:35:45.467735  # ok 133 /ocp/interconnect@44c00000/segment@200000/target-module@9000
 2283 07:35:45.492388  # ok 134 /ocp/interconnect@44c00000/segment@200000/target-module@9000/serial@0
 2284 07:35:45.511610  # ok 135 /ocp/interconnect@44c00000/segment@200000/target-module@b000
 2285 07:35:45.537000  # ok 136 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0
 2286 07:35:45.562828  # ok 137 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/eeprom@50
 2287 07:35:45.647012  # ok 138 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/eeprom@50/nvmem-layout # SKIP
 2288 07:35:45.669768  # ok 139 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
 2289 07:35:45.691257  # ok 140 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24
 2290 07:35:45.767856  # not ok 141 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/charger
 2291 07:35:45.844771  # not ok 142 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/pwrbutton
 2292 07:35:45.866315  # ok 143 /ocp/interconnect@44c00000/segment@200000/target-module@d000
 2293 07:35:45.973806  # not ok 144 /ocp/interconnect@47c00000
 2294 07:35:46.050115  # not ok 145 /ocp/interconnect@47c00000/segment@0
 2295 07:35:46.074394  # ok 146 /ocp/interconnect@48000000
 2296 07:35:46.105203  # ok 147 /ocp/interconnect@48000000/segment@0
 2297 07:35:46.124632  # ok 148 /ocp/interconnect@48000000/segment@0/target-module@22000
 2298 07:35:46.153536  # ok 149 /ocp/interconnect@48000000/segment@0/target-module@24000
 2299 07:35:46.177285  # ok 150 /ocp/interconnect@48000000/segment@0/target-module@2a000
 2300 07:35:46.201918  # ok 151 /ocp/interconnect@48000000/segment@0/target-module@30000
 2301 07:35:46.224087  # ok 152 /ocp/interconnect@48000000/segment@0/target-module@38000
 2302 07:35:46.254347  # ok 153 /ocp/interconnect@48000000/segment@0/target-module@38000/mcasp@0
 2303 07:35:46.276996  # ok 154 /ocp/interconnect@48000000/segment@0/target-module@3c000
 2304 07:35:46.350091  # not ok 155 /ocp/interconnect@48000000/segment@0/target-module@40000
 2305 07:35:46.426460  # ok 156 /ocp/interconnect@48000000/segment@0/target-module@40000/timer@0 # SKIP
 2306 07:35:46.449986  # ok 157 /ocp/interconnect@48000000/segment@0/target-module@42000
 2307 07:35:46.475682  # ok 158 /ocp/interconnect@48000000/segment@0/target-module@42000/timer@0
 2308 07:35:46.499363  # ok 159 /ocp/interconnect@48000000/segment@0/target-module@44000
 2309 07:35:46.528098  # ok 160 /ocp/interconnect@48000000/segment@0/target-module@44000/timer@0
 2310 07:35:46.555125  # ok 161 /ocp/interconnect@48000000/segment@0/target-module@46000
 2311 07:35:46.577883  # ok 162 /ocp/interconnect@48000000/segment@0/target-module@46000/timer@0
 2312 07:35:46.599926  # ok 163 /ocp/interconnect@48000000/segment@0/target-module@48000
 2313 07:35:46.623748  # ok 164 /ocp/interconnect@48000000/segment@0/target-module@48000/timer@0
 2314 07:35:46.648174  # ok 165 /ocp/interconnect@48000000/segment@0/target-module@4a000
 2315 07:35:46.677965  # ok 166 /ocp/interconnect@48000000/segment@0/target-module@4a000/timer@0
 2316 07:35:46.703835  # ok 167 /ocp/interconnect@48000000/segment@0/target-module@4c000
 2317 07:35:46.728584  # ok 168 /ocp/interconnect@48000000/segment@0/target-module@4c000/gpio@0
 2318 07:35:46.753227  # ok 169 /ocp/interconnect@48000000/segment@0/target-module@60000
 2319 07:35:46.777972  # ok 170 /ocp/interconnect@48000000/segment@0/target-module@60000/mmc@0
 2320 07:35:46.798309  # ok 171 /ocp/interconnect@48000000/segment@0/target-module@c8000
 2321 07:35:46.822998  # ok 172 /ocp/interconnect@48000000/segment@0/target-module@c8000/mailbox@0
 2322 07:35:46.847425  # ok 173 /ocp/interconnect@48000000/segment@0/target-module@ca000
 2323 07:35:46.877603  # ok 174 /ocp/interconnect@48000000/segment@0/target-module@ca000/spinlock@0
 2324 07:35:46.896874  # ok 175 /ocp/interconnect@48000000/segment@100000
 2325 07:35:46.921693  # ok 176 /ocp/interconnect@48000000/segment@100000/target-module@9c000
 2326 07:35:46.947908  # ok 177 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0
 2327 07:35:47.023095  # not ok 178 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/eeprom@54
 2328 07:35:47.107462  # ok 179 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/eeprom@54/nvmem-layout # SKIP
 2329 07:35:47.176703  # not ok 180 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/eeprom@55
 2330 07:35:47.253920  # ok 181 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/eeprom@55/nvmem-layout # SKIP
 2331 07:35:47.328049  # not ok 182 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/eeprom@56
 2332 07:35:47.407223  # ok 183 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/eeprom@56/nvmem-layout # SKIP
 2333 07:35:47.481425  # not ok 184 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/eeprom@57
 2334 07:35:47.559476  # ok 185 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/eeprom@57/nvmem-layout # SKIP
 2335 07:35:47.580026  # ok 186 /ocp/interconnect@48000000/segment@100000/target-module@a0000
 2336 07:35:47.605844  # ok 187 /ocp/interconnect@48000000/segment@100000/target-module@a6000
 2337 07:35:47.630119  # ok 188 /ocp/interconnect@48000000/segment@100000/target-module@a8000
 2338 07:35:47.654498  # ok 189 /ocp/interconnect@48000000/segment@100000/target-module@aa000
 2339 07:35:47.677978  # ok 190 /ocp/interconnect@48000000/segment@100000/target-module@ac000
 2340 07:35:47.708061  # ok 191 /ocp/interconnect@48000000/segment@100000/target-module@ac000/gpio@0
 2341 07:35:47.728248  # ok 192 /ocp/interconnect@48000000/segment@100000/target-module@ae000
 2342 07:35:47.752970  # ok 193 /ocp/interconnect@48000000/segment@100000/target-module@ae000/gpio@0
 2343 07:35:47.780729  # ok 194 /ocp/interconnect@48000000/segment@100000/target-module@cc000
 2344 07:35:47.800897  # ok 195 /ocp/interconnect@48000000/segment@100000/target-module@d0000
 2345 07:35:47.826581  # ok 196 /ocp/interconnect@48000000/segment@100000/target-module@d8000
 2346 07:35:47.852318  # ok 197 /ocp/interconnect@48000000/segment@100000/target-module@d8000/mmc@0
 2347 07:35:47.873574  # ok 198 /ocp/interconnect@48000000/segment@200000
 2348 07:35:47.899323  # ok 199 /ocp/interconnect@48000000/segment@200000/target-module@0
 2349 07:35:47.978759  # ok 200 /ocp/interconnect@48000000/segment@200000/target-module@0/mpu@0 # SKIP
 2350 07:35:47.997832  # ok 201 /ocp/interconnect@48000000/segment@300000
 2351 07:35:48.024702  # ok 202 /ocp/interconnect@48000000/segment@300000/target-module@0
 2352 07:35:48.050336  # ok 203 /ocp/interconnect@48000000/segment@300000/target-module@10000
 2353 07:35:48.074903  # ok 204 /ocp/interconnect@48000000/segment@300000/target-module@10000/rng@0
 2354 07:35:48.098267  # ok 205 /ocp/interconnect@48000000/segment@300000/target-module@2000
 2355 07:35:48.127381  # ok 206 /ocp/interconnect@48000000/segment@300000/target-module@4000
 2356 07:35:48.148802  # ok 207 /ocp/interconnect@48000000/segment@300000/target-module@e000
 2357 07:35:48.228623  # not ok 208 /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
 2358 07:35:48.243004  # ok 209 /ocp/interconnect@4a000000
 2359 07:35:48.268002  # ok 210 /ocp/interconnect@4a000000/segment@0
 2360 07:35:48.296989  # ok 211 /ocp/interconnect@4a000000/segment@0/target-module@100000
 2361 07:35:48.320254  # ok 212 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0
 2362 07:35:48.346223  # ok 213 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0/mdio@1000
 2363 07:35:48.372870  # ok 214 /ocp/interconnect@4a000000/segment@0/target-module@300000
 2364 07:35:48.448385  # not ok 215 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0
 2365 07:35:48.557858  # ok 216 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/cfg@26000 # SKIP
 2366 07:35:48.635658  # not ok 217 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/interrupt-controller@20000
 2367 07:35:48.746054  # ok 218 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/mii-rt@32000 # SKIP
 2368 07:35:48.824846  # not ok 219 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@34000
 2369 07:35:48.899412  # not ok 220 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@38000
 2370 07:35:49.002829  # not ok 221 /ocp/interconnect@4b140000
 2371 07:35:49.078845  # not ok 222 /ocp/interconnect@4b140000/segment@0
 2372 07:35:49.153787  # ok 223 /ocp/interrupt-controller@48200000 # SKIP
 2373 07:35:49.176581  # ok 224 /ocp/target-module@40300000
 2374 07:35:49.200848  # ok 225 /ocp/target-module@40300000/sram@0
 2375 07:35:49.283513  # ok 226 /ocp/target-module@40300000/sram@0/pm-code-sram@0 # SKIP
 2376 07:35:49.357584  # ok 227 /ocp/target-module@40300000/sram@0/pm-data-sram@1000 # SKIP
 2377 07:35:49.375319  # ok 228 /ocp/target-module@47400000
 2378 07:35:49.405004  # ok 229 /ocp/target-module@47400000/dma-controller@2000
 2379 07:35:49.426206  # ok 230 /ocp/target-module@47400000/usb-phy@1300
 2380 07:35:49.452847  # ok 231 /ocp/target-module@47400000/usb-phy@1b00
 2381 07:35:49.471633  # ok 232 /ocp/target-module@47400000/usb@1400
 2382 07:35:49.500260  # ok 233 /ocp/target-module@47400000/usb@1800
 2383 07:35:49.522401  # ok 234 /ocp/target-module@47810000
 2384 07:35:49.541113  # ok 235 /ocp/target-module@49000000
 2385 07:35:49.565427  # ok 236 /ocp/target-module@49000000/dma@0
 2386 07:35:49.592750  # ok 237 /ocp/target-module@49800000
 2387 07:35:49.615145  # ok 238 /ocp/target-module@49800000/dma@0
 2388 07:35:49.640428  # ok 239 /ocp/target-module@49900000
 2389 07:35:49.660211  # ok 240 /ocp/target-module@49900000/dma@0
 2390 07:35:49.683809  # ok 241 /ocp/target-module@49a00000
 2391 07:35:49.707574  # ok 242 /ocp/target-module@49a00000/dma@0
 2392 07:35:49.729403  # ok 243 /ocp/target-module@4c000000
 2393 07:35:49.806817  # not ok 244 /ocp/target-module@4c000000/emif@0
 2394 07:35:49.833231  # ok 245 /ocp/target-module@50000000
 2395 07:35:49.856353  # ok 246 /ocp/target-module@53100000
 2396 07:35:49.926811  # not ok 247 /ocp/target-module@53100000/sham@0
 2397 07:35:49.949791  # ok 248 /ocp/target-module@53500000
 2398 07:35:50.031064  # not ok 249 /ocp/target-module@53500000/aes@0
 2399 07:35:50.050912  # ok 250 /ocp/target-module@56000000
 2400 07:35:50.165119  # ok 251 /ocp/target-module@56000000/gpu@0 # SKIP
 2401 07:35:50.238790  # ok 252 /opp-table # SKIP
 2402 07:35:50.313231  # ok 253 /soc # SKIP
 2403 07:35:50.332882  # ok 254 /sound
 2404 07:35:50.357098  # ok 255 /target-module@4b000000
 2405 07:35:50.382304  # ok 256 /target-module@4b000000/target-module@140000
 2406 07:35:50.403715  # ok 257 /target-module@4b000000/target-module@140000/pmu@0
 2407 07:35:50.412952  # # Totals: pass:117 fail:27 xfail:0 xpass:0 skip:113 error:0
 2408 07:35:50.421698  not ok 1 selftests: dt: test_unprobed_devices.sh # exit=1
 2409 07:35:52.861115  dt_test_unprobed_devices_sh_ skip
 2410 07:35:52.865966  dt_test_unprobed_devices_sh_clk_mcasp0 pass
 2411 07:35:52.872187  dt_test_unprobed_devices_sh_clk_mcasp0_fixed skip
 2412 07:35:52.872566  dt_test_unprobed_devices_sh_cpus_cpu_0 skip
 2413 07:35:52.880878  dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate skip
 2414 07:35:52.881259  dt_test_unprobed_devices_sh_fixedregulator0 pass
 2415 07:35:52.887004  dt_test_unprobed_devices_sh_leds pass
 2416 07:35:52.891877  dt_test_unprobed_devices_sh_ocp pass
 2417 07:35:52.892262  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 pass
 2418 07:35:52.901870  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 pass
 2419 07:35:52.908060  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 pass
 2420 07:35:52.913076  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 pass
 2421 07:35:52.922910  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 fail
 2422 07:35:52.929014  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 pass
 2423 07:35:52.938848  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 pass
 2424 07:35:52.950202  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 fail
 2425 07:35:52.955105  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 skip
 2426 07:35:52.965078  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 skip
 2427 07:35:52.976370  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 skip
 2428 07:35:52.986168  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c skip
 2429 07:35:52.997256  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 skip
 2430 07:35:53.007214  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c skip
 2431 07:35:53.018303  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 skip
 2432 07:35:53.029680  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 skip
 2433 07:35:53.035840  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 skip
 2434 07:35:53.045833  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 skip
 2435 07:35:53.058232  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 skip
 2436 07:35:53.069216  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 skip
 2437 07:35:53.080583  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 skip
 2438 07:35:53.085562  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 skip
 2439 07:35:53.096934  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 skip
 2440 07:35:53.107948  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 skip
 2441 07:35:53.118914  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 skip
 2442 07:35:53.125027  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 skip
 2443 07:35:53.136436  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 skip
 2444 07:35:53.147554  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 skip
 2445 07:35:53.158673  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 skip
 2446 07:35:53.168429  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz skip
 2447 07:35:53.179517  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 skip
 2448 07:35:53.189364  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k skip
 2449 07:35:53.200546  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k skip
 2450 07:35:53.210390  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk skip
 2451 07:35:53.221513  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 skip
 2452 07:35:53.231299  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 skip
 2453 07:35:53.241518  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 skip
 2454 07:35:53.252527  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 skip
 2455 07:35:53.263641  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 skip
 2456 07:35:53.279551  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 skip
 2457 07:35:53.289219  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 skip
 2458 07:35:53.300667  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 skip
 2459 07:35:53.310354  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 skip
 2460 07:35:53.321598  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 skip
 2461 07:35:53.331291  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 skip
 2462 07:35:53.341492  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm skip
 2463 07:35:53.357367  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac skip
 2464 07:35:53.368423  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c skip
 2465 07:35:53.378392  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 skip
 2466 07:35:53.389482  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk skip
 2467 07:35:53.399544  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk skip
 2468 07:35:53.410769  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk skip
 2469 07:35:53.420646  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk skip
 2470 07:35:53.430757  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk skip
 2471 07:35:53.439449  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk skip
 2472 07:35:53.451798  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 skip
 2473 07:35:53.461594  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc skip
 2474 07:35:53.471637  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 skip
 2475 07:35:53.482739  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 skip
 2476 07:35:53.493902  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div skip
 2477 07:35:53.503627  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin skip
 2478 07:35:53.514580  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 skip
 2479 07:35:53.524751  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 skip
 2480 07:35:53.535962  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c skip
 2481 07:35:53.552171  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 skip
 2482 07:35:53.561994  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 skip
 2483 07:35:53.573230  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c skip
 2484 07:35:53.582875  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 skip
 2485 07:35:53.594054  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c skip
 2486 07:35:53.603811  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 skip
 2487 07:35:53.617185  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 skip
 2488 07:35:53.627549  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 skip
 2489 07:35:53.638823  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 skip
 2490 07:35:53.649793  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 skip
 2491 07:35:53.655870  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 skip
 2492 07:35:53.666991  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c skip
 2493 07:35:53.678211  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 skip
 2494 07:35:53.689214  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 skip
 2495 07:35:53.701545  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 skip
 2496 07:35:53.706424  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c skip
 2497 07:35:53.717412  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 skip
 2498 07:35:53.734831  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 skip
 2499 07:35:53.739686  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 skip
 2500 07:35:53.757269  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 skip
 2501 07:35:53.766065  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 skip
 2502 07:35:53.778534  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 skip
 2503 07:35:53.788338  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 pass
 2504 07:35:53.799664  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 pass
 2505 07:35:53.804532  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 pass
 2506 07:35:53.814323  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 pass
 2507 07:35:53.825222  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 pass
 2508 07:35:53.835353  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 pass
 2509 07:35:53.841676  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 pass
 2510 07:35:53.850583  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 pass
 2511 07:35:53.862830  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 fail
 2512 07:35:53.872719  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 pass
 2513 07:35:53.877730  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 pass
 2514 07:35:53.888834  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 pass
 2515 07:35:53.898911  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 fail
 2516 07:35:53.909937  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck skip
 2517 07:35:53.924748  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck skip
 2518 07:35:53.935693  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck skip
 2519 07:35:53.945631  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck skip
 2520 07:35:53.961525  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck skip
 2521 07:35:53.971524  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck skip
 2522 07:35:53.982582  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck skip
 2523 07:35:53.993559  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck skip
 2524 07:35:54.009568  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck skip
 2525 07:35:54.019326  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck skip
 2526 07:35:54.030555  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 skip
 2527 07:35:54.045150  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 skip
 2528 07:35:54.056583  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 skip
 2529 07:35:54.072549  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 skip
 2530 07:35:54.082294  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 skip
 2531 07:35:54.093257  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel pass
 2532 07:35:54.102965  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 fail
 2533 07:35:54.114127  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 fail
 2534 07:35:54.119068  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 skip
 2535 07:35:54.128920  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 pass
 2536 07:35:54.139898  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 fail
 2537 07:35:54.144767  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 pass
 2538 07:35:54.156205  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 fail
 2539 07:35:54.161205  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 pass
 2540 07:35:54.171193  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 pass
 2541 07:35:54.182575  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 pass
 2542 07:35:54.188665  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 pass
 2543 07:35:54.198825  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 pass
 2544 07:35:54.204945  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 pass
 2545 07:35:54.215903  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_eeprom_50 pass
 2546 07:35:54.226947  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_eeprom_50_nvmem-layout skip
 2547 07:35:54.238023  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 pass
 2548 07:35:54.244175  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 pass
 2549 07:35:54.255459  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger fail
 2550 07:35:54.266453  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton fail
 2551 07:35:54.276305  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 pass
 2552 07:35:54.282650  dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 fail
 2553 07:35:54.287604  dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 fail
 2554 07:35:54.292727  dt_test_unprobed_devices_sh_ocp_interconnect_48000000 pass
 2555 07:35:54.297675  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 pass
 2556 07:35:54.303797  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 pass
 2557 07:35:54.314853  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 pass
 2558 07:35:54.321170  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 pass
 2559 07:35:54.326186  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 pass
 2560 07:35:54.338443  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 pass
 2561 07:35:54.343451  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 pass
 2562 07:35:54.354676  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 pass
 2563 07:35:54.360849  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 fail
 2564 07:35:54.370695  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 skip
 2565 07:35:54.376952  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 pass
 2566 07:35:54.388014  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 pass
 2567 07:35:54.394163  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 pass
 2568 07:35:54.403885  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 pass
 2569 07:35:54.408944  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 pass
 2570 07:35:54.420187  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 pass
 2571 07:35:54.424981  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 pass
 2572 07:35:54.436457  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 pass
 2573 07:35:54.441271  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 pass
 2574 07:35:54.451570  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 pass
 2575 07:35:54.460185  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 pass
 2576 07:35:54.466305  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 pass
 2577 07:35:54.477258  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 pass
 2578 07:35:54.482371  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 pass
 2579 07:35:54.493540  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 pass
 2580 07:35:54.503438  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 pass
 2581 07:35:54.509552  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 pass
 2582 07:35:54.519187  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 pass
 2583 07:35:54.524227  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 pass
 2584 07:35:54.535568  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 pass
 2585 07:35:54.540256  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 pass
 2586 07:35:54.550440  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_54 fail
 2587 07:35:54.561713  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_54_nvmem-layout skip
 2588 07:35:54.572728  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_55 fail
 2589 07:35:54.584059  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_55_nvmem-layout skip
 2590 07:35:54.590180  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_56 fail
 2591 07:35:54.601201  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_56_nvmem-layout skip
 2592 07:35:54.613682  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_57 fail
 2593 07:35:54.624924  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_57_nvmem-layout skip
 2594 07:35:54.630905  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 pass
 2595 07:35:54.642161  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 pass
 2596 07:35:54.647019  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 pass
 2597 07:35:54.656938  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 pass
 2598 07:35:54.663205  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 pass
 2599 07:35:54.672917  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 pass
 2600 07:35:54.684189  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 pass
 2601 07:35:54.689267  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 pass
 2602 07:35:54.699072  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 pass
 2603 07:35:54.710103  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 pass
 2604 07:35:54.714822  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 pass
 2605 07:35:54.726080  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 pass
 2606 07:35:54.731188  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 pass
 2607 07:35:54.741186  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 pass
 2608 07:35:54.747082  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 skip
 2609 07:35:54.752015  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 pass
 2610 07:35:54.761786  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 pass
 2611 07:35:54.772670  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 pass
 2612 07:35:54.777587  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 pass
 2613 07:35:54.788677  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 pass
 2614 07:35:54.793668  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 pass
 2615 07:35:54.803372  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 pass
 2616 07:35:54.814347  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 fail
 2617 07:35:54.819095  dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 pass
 2618 07:35:54.824124  dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 pass
 2619 07:35:54.830175  dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 pass
 2620 07:35:54.839896  dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 pass
 2621 07:35:54.850988  dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 pass
 2622 07:35:54.855902  dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 pass
 2623 07:35:54.865610  dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 fail
 2624 07:35:54.876698  dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 skip
 2625 07:35:54.886479  dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 fail
 2626 07:35:54.897470  dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 skip
 2627 07:35:54.907148  dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 fail
 2628 07:35:54.918266  dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 fail
 2629 07:35:54.923013  dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 fail
 2630 07:35:54.928062  dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 fail
 2631 07:35:54.934192  dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 skip
 2632 07:35:54.939110  dt_test_unprobed_devices_sh_ocp_target-module_40300000 pass
 2633 07:35:54.943909  dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 pass
 2634 07:35:54.955069  dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 skip
 2635 07:35:54.959906  dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 skip
 2636 07:35:54.964639  dt_test_unprobed_devices_sh_ocp_target-module_47400000 pass
 2637 07:35:54.975743  dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 pass
 2638 07:35:54.980521  dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 pass
 2639 07:35:54.985528  dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 pass
 2640 07:35:54.990612  dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 pass
 2641 07:35:54.996636  dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 pass
 2642 07:35:55.001646  dt_test_unprobed_devices_sh_ocp_target-module_47810000 pass
 2643 07:35:55.011503  dt_test_unprobed_devices_sh_ocp_target-module_49000000 pass
 2644 07:35:55.017704  dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 pass
 2645 07:35:55.022529  dt_test_unprobed_devices_sh_ocp_target-module_49800000 pass
 2646 07:35:55.027124  dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 pass
 2647 07:35:55.032124  dt_test_unprobed_devices_sh_ocp_target-module_49900000 pass
 2648 07:35:55.038357  dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 pass
 2649 07:35:55.043228  dt_test_unprobed_devices_sh_ocp_target-module_49a00000 pass
 2650 07:35:55.047966  dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 pass
 2651 07:35:55.052963  dt_test_unprobed_devices_sh_ocp_target-module_4c000000 pass
 2652 07:35:55.059145  dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 fail
 2653 07:35:55.064079  dt_test_unprobed_devices_sh_ocp_target-module_50000000 pass
 2654 07:35:55.070228  dt_test_unprobed_devices_sh_ocp_target-module_53100000 pass
 2655 07:35:55.076213  dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 fail
 2656 07:35:55.081103  dt_test_unprobed_devices_sh_ocp_target-module_53500000 pass
 2657 07:35:55.086006  dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 fail
 2658 07:35:55.090937  dt_test_unprobed_devices_sh_ocp_target-module_56000000 pass
 2659 07:35:55.097017  dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 skip
 2660 07:35:55.102010  dt_test_unprobed_devices_sh_opp-table skip
 2661 07:35:55.106757  dt_test_unprobed_devices_sh_soc skip
 2662 07:35:55.111695  dt_test_unprobed_devices_sh_sound pass
 2663 07:35:55.112079  dt_test_unprobed_devices_sh_target-module_4b000000 pass
 2664 07:35:55.122767  dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 pass
 2665 07:35:55.127588  dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 pass
 2666 07:35:55.132599  dt_test_unprobed_devices_sh fail
 2667 07:35:55.135848  + ../../utils/send-to-lava.sh ./output/result.txt
 2668 07:35:55.309757  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-dt RESULT=pass>
 2669 07:35:55.310731  Received signal: <TESTCASE> TEST_CASE_ID=shardfile-dt RESULT=pass
 2671 07:35:55.521953  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip>
 2672 07:35:55.522577  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip
 2674 07:35:55.786933  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass>
 2675 07:35:55.787569  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass
 2677 07:35:56.033135  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip>
 2678 07:35:56.033762  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip
 2680 07:35:56.273976  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip>
 2681 07:35:56.274604  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip
 2683 07:35:56.525543  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip>
 2684 07:35:56.526171  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip
 2686 07:35:56.789703  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass>
 2687 07:35:56.790326  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass
 2689 07:35:57.026612  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass>
 2690 07:35:57.027235  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass
 2692 07:35:57.248289  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass>
 2693 07:35:57.248893  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass
 2695 07:35:57.485926  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass>
 2696 07:35:57.486552  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass
 2698 07:35:57.723908  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass>
 2699 07:35:57.724543  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass
 2701 07:35:57.976600  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass>
 2702 07:35:57.977322  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass
 2704 07:35:58.213793  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass>
 2705 07:35:58.214413  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass
 2707 07:35:58.428749  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail>
 2708 07:35:58.429392  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail
 2710 07:35:58.664714  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass>
 2711 07:35:58.665368  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass
 2713 07:35:58.907166  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass>
 2714 07:35:58.907799  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass
 2716 07:35:59.165777  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail>
 2717 07:35:59.166412  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail
 2719 07:35:59.416384  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip>
 2720 07:35:59.417014  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip
 2722 07:35:59.708420  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip>
 2723 07:35:59.709076  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip
 2725 07:35:59.947446  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip>
 2726 07:35:59.948077  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip
 2728 07:36:00.216827  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip>
 2729 07:36:00.217467  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip
 2731 07:36:00.452209  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip>
 2732 07:36:00.452862  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip
 2734 07:36:00.685557  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip>
 2735 07:36:00.686186  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip
 2737 07:36:00.943244  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip>
 2738 07:36:00.943874  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip
 2740 07:36:01.194690  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip>
 2741 07:36:01.195318  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip
 2743 07:36:01.442645  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip>
 2744 07:36:01.443278  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip
 2746 07:36:01.685395  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip>
 2747 07:36:01.686027  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip
 2749 07:36:01.918581  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip>
 2750 07:36:01.919211  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip
 2752 07:36:02.146653  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip>
 2753 07:36:02.147289  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip
 2755 07:36:02.378045  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip>
 2756 07:36:02.378677  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip
 2758 07:36:02.577459  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip>
 2759 07:36:02.578087  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip
 2761 07:36:02.805343  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip>
 2762 07:36:02.805972  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip
 2764 07:36:03.045875  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip>
 2765 07:36:03.046534  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip
 2767 07:36:03.305552  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip>
 2768 07:36:03.306173  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip
 2770 07:36:03.529355  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip>
 2771 07:36:03.529986  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip
 2773 07:36:03.747632  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip>
 2774 07:36:03.748262  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip
 2776 07:36:03.987123  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip>
 2777 07:36:03.987745  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip
 2779 07:36:04.240688  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip>
 2780 07:36:04.241345  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip
 2782 07:36:04.464558  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip>
 2783 07:36:04.465215  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip
 2785 07:36:04.697887  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip>
 2786 07:36:04.698509  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip
 2788 07:36:04.950356  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip>
 2789 07:36:04.950975  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip
 2791 07:36:05.207880  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip>
 2792 07:36:05.208502  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip
 2794 07:36:05.466542  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip>
 2795 07:36:05.467162  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip
 2797 07:36:05.699098  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip>
 2798 07:36:05.699719  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip
 2800 07:36:05.931500  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip>
 2801 07:36:05.932118  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip
 2803 07:36:06.183098  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip>
 2804 07:36:06.183714  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip
 2806 07:36:06.425777  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip>
 2807 07:36:06.426400  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip
 2809 07:36:06.678199  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip>
 2810 07:36:06.678817  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip
 2812 07:36:06.925483  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip>
 2813 07:36:06.926101  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip
 2815 07:36:07.152583  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip>
 2816 07:36:07.153241  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip
 2818 07:36:07.399940  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip>
 2819 07:36:07.400564  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip
 2821 07:36:07.678765  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip>
 2822 07:36:07.679384  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip
 2824 07:36:07.918530  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip>
 2825 07:36:07.919148  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip
 2827 07:36:08.183580  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip>
 2828 07:36:08.184198  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip
 2830 07:36:08.437153  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip>
 2831 07:36:08.437775  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip
 2833 07:36:08.694710  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip>
 2834 07:36:08.695328  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip
 2836 07:36:08.938985  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip>
 2837 07:36:08.939606  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip
 2839 07:36:09.195817  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip>
 2840 07:36:09.196442  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip
 2842 07:36:09.458717  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip>
 2843 07:36:09.459340  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip
 2845 07:36:09.687693  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip>
 2846 07:36:09.688316  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip
 2848 07:36:09.927501  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip>
 2849 07:36:09.928119  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip
 2851 07:36:10.173669  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip>
 2852 07:36:10.174298  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip
 2854 07:36:10.412314  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip>
 2855 07:36:10.412930  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip
 2857 07:36:10.627804  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip>
 2858 07:36:10.628427  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip
 2860 07:36:10.887567  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip>
 2861 07:36:10.888186  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip
 2863 07:36:11.170466  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip>
 2864 07:36:11.171090  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip
 2866 07:36:11.513608  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip>
 2867 07:36:11.514240  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip
 2869 07:36:11.756596  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip>
 2870 07:36:11.757255  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip
 2872 07:36:12.022809  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip>
 2873 07:36:12.023433  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip
 2875 07:36:12.273153  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip>
 2876 07:36:12.273768  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip
 2878 07:36:12.516016  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip>
 2879 07:36:12.516636  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip
 2881 07:36:12.767598  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip>
 2882 07:36:12.768229  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip
 2884 07:36:13.022995  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip>
 2885 07:36:13.023615  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip
 2887 07:36:13.290620  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip>
 2888 07:36:13.291247  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip
 2890 07:36:13.515540  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip>
 2891 07:36:13.516157  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip
 2893 07:36:13.763999  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip>
 2894 07:36:13.764617  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip
 2896 07:36:13.999865  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip>
 2897 07:36:14.000488  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip
 2899 07:36:14.241506  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip>
 2900 07:36:14.242125  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip
 2902 07:36:14.473767  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip>
 2903 07:36:14.474394  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip
 2905 07:36:14.732818  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip>
 2906 07:36:14.733443  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip
 2908 07:36:14.975734  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip>
 2909 07:36:14.976353  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip
 2911 07:36:15.235606  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip>
 2912 07:36:15.236247  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip
 2914 07:36:15.572706  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip>
 2915 07:36:15.573370  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip
 2917 07:36:15.775641  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip>
 2918 07:36:15.776262  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip
 2920 07:36:16.000519  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip>
 2921 07:36:16.001183  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip
 2923 07:36:16.276305  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip>
 2924 07:36:16.276923  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip
 2926 07:36:16.532909  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip>
 2927 07:36:16.533526  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip
 2929 07:36:16.783346  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip>
 2930 07:36:16.783963  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip
 2932 07:36:17.068304  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip>
 2933 07:36:17.068921  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip
 2935 07:36:17.301073  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip>
 2936 07:36:17.301698  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip
 2938 07:36:17.580192  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip>
 2939 07:36:17.580846  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip
 2941 07:36:17.872909  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip>
 2942 07:36:17.873531  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip
 2944 07:36:18.104642  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip>
 2945 07:36:18.105321  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip
 2947 07:36:18.329746  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip>
 2948 07:36:18.330388  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip
 2950 07:36:18.569752  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip>
 2951 07:36:18.570373  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip
 2953 07:36:18.785515  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass>
 2954 07:36:18.786136  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass
 2956 07:36:19.046259  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass>
 2957 07:36:19.046882  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass
 2959 07:36:19.303707  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass>
 2960 07:36:19.304330  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass
 2962 07:36:19.532917  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass>
 2963 07:36:19.533536  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass
 2965 07:36:19.795604  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass>
 2966 07:36:19.796226  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass
 2968 07:36:20.030428  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass>
 2969 07:36:20.031048  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass
 2971 07:36:20.261787  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass>
 2972 07:36:20.262415  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass
 2974 07:36:20.578653  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass>
 2975 07:36:20.579277  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass
 2977 07:36:20.833596  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail>
 2978 07:36:20.834215  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail
 2980 07:36:21.121954  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass>
 2981 07:36:21.122574  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass
 2983 07:36:21.387346  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass>
 2984 07:36:21.387964  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass
 2986 07:36:21.619461  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass>
 2987 07:36:21.620079  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass
 2989 07:36:21.836912  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail>
 2990 07:36:21.837533  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail
 2992 07:36:22.081961  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip>
 2993 07:36:22.082582  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip
 2995 07:36:22.316901  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip>
 2996 07:36:22.317523  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip
 2998 07:36:22.552536  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip>
 2999 07:36:22.553194  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip
 3001 07:36:22.768957  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip>
 3002 07:36:22.769584  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip
 3004 07:36:23.016888  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip>
 3005 07:36:23.017505  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip
 3007 07:36:23.252076  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip>
 3008 07:36:23.252695  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip
 3010 07:36:23.493077  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip>
 3011 07:36:23.493696  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip
 3013 07:36:23.742785  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip>
 3014 07:36:23.743406  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip
 3016 07:36:23.981456  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip>
 3017 07:36:23.982074  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip
 3019 07:36:24.213108  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip>
 3020 07:36:24.213727  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip
 3022 07:36:24.462560  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip>
 3023 07:36:24.463178  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip
 3025 07:36:24.717134  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip>
 3026 07:36:24.717753  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip
 3028 07:36:24.926801  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip
 3030 07:36:24.929737  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip>
 3031 07:36:25.174224  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip
 3033 07:36:25.177200  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip>
 3034 07:36:25.395525  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip
 3036 07:36:25.397566  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip>
 3037 07:36:25.696151  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass>
 3038 07:36:25.696866  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass
 3040 07:36:25.954915  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail>
 3041 07:36:25.955555  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail
 3043 07:36:26.176507  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail>
 3044 07:36:26.177162  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail
 3046 07:36:26.436949  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip>
 3047 07:36:26.437568  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip
 3049 07:36:26.684820  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass>
 3050 07:36:26.685324  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass
 3052 07:36:26.919847  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail>
 3053 07:36:26.920483  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail
 3055 07:36:27.153193  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass>
 3056 07:36:27.153784  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass
 3058 07:36:27.402214  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail>
 3059 07:36:27.402812  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail
 3061 07:36:27.619500  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass>
 3062 07:36:27.620130  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass
 3064 07:36:27.928454  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass>
 3065 07:36:27.929104  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass
 3067 07:36:28.156378  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass>
 3068 07:36:28.156994  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass
 3070 07:36:28.405133  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass>
 3071 07:36:28.405751  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass
 3073 07:36:28.655196  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass>
 3074 07:36:28.655812  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass
 3076 07:36:28.894661  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass>
 3077 07:36:28.895279  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass
 3079 07:36:29.139351  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_eeprom_50 RESULT=pass>
 3080 07:36:29.139972  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_eeprom_50 RESULT=pass
 3082 07:36:29.382096  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_eeprom_50_nvmem-layout RESULT=skip>
 3083 07:36:29.382717  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_eeprom_50_nvmem-layout RESULT=skip
 3085 07:36:29.598334  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass>
 3086 07:36:29.598956  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass
 3088 07:36:29.808213  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass>
 3089 07:36:29.808859  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass
 3091 07:36:30.072233  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail>
 3092 07:36:30.072878  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail
 3094 07:36:30.340440  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail>
 3095 07:36:30.341095  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail
 3097 07:36:30.570556  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass>
 3098 07:36:30.571177  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass
 3100 07:36:30.887372  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail>
 3101 07:36:30.888005  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail
 3103 07:36:31.187971  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail>
 3104 07:36:31.188592  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail
 3106 07:36:31.483898  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass>
 3107 07:36:31.484515  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass
 3109 07:36:31.758061  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass>
 3110 07:36:31.758679  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass
 3112 07:36:32.011371  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass>
 3113 07:36:32.011990  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass
 3115 07:36:32.275051  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass>
 3116 07:36:32.275672  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass
 3118 07:36:32.550169  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass>
 3119 07:36:32.550786  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass
 3121 07:36:32.833794  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass>
 3122 07:36:32.834413  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass
 3124 07:36:33.092312  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass>
 3125 07:36:33.092935  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass
 3127 07:36:33.364504  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass>
 3128 07:36:33.365165  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass
 3130 07:36:33.625864  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass>
 3131 07:36:33.626487  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass
 3133 07:36:33.917890  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail>
 3134 07:36:33.918505  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail
 3136 07:36:34.179534  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip>
 3137 07:36:34.180160  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip
 3139 07:36:34.462247  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass>
 3140 07:36:34.462863  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass
 3142 07:36:34.729091  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass>
 3143 07:36:34.729707  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass
 3145 07:36:34.991645  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass>
 3146 07:36:34.992263  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass
 3148 07:36:35.273101  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass>
 3149 07:36:35.273723  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass
 3151 07:36:35.562149  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass>
 3152 07:36:35.562749  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass
 3154 07:36:35.838922  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass>
 3155 07:36:35.839537  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass
 3157 07:36:36.112371  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass>
 3158 07:36:36.112986  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass
 3160 07:36:36.387480  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass>
 3161 07:36:36.388099  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass
 3163 07:36:36.659600  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass>
 3164 07:36:36.660215  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass
 3166 07:36:36.969401  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass>
 3167 07:36:36.970017  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass
 3169 07:36:37.273138  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass>
 3170 07:36:37.273754  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass
 3172 07:36:37.578492  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass>
 3173 07:36:37.579110  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass
 3175 07:36:37.842086  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass>
 3176 07:36:37.842703  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass
 3178 07:36:38.102366  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass>
 3179 07:36:38.102979  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass
 3181 07:36:38.405783  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass>
 3182 07:36:38.406397  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass
 3184 07:36:38.687042  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass>
 3185 07:36:38.687661  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass
 3187 07:36:38.964481  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass>
 3188 07:36:38.965137  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass
 3190 07:36:39.249302  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass>
 3191 07:36:39.249918  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass
 3193 07:36:39.520257  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass>
 3194 07:36:39.520879  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass
 3196 07:36:39.798449  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass>
 3197 07:36:39.799068  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass
 3199 07:36:40.065326  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass>
 3200 07:36:40.065928  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass
 3202 07:36:40.335378  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_54 RESULT=fail>
 3203 07:36:40.335997  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_54 RESULT=fail
 3205 07:36:40.597337  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_54_nvmem-layout RESULT=skip>
 3206 07:36:40.597958  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_54_nvmem-layout RESULT=skip
 3208 07:36:40.867654  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_55 RESULT=fail>
 3209 07:36:40.868275  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_55 RESULT=fail
 3211 07:36:41.181188  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_55_nvmem-layout RESULT=skip>
 3212 07:36:41.181808  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_55_nvmem-layout RESULT=skip
 3214 07:36:41.443051  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_56 RESULT=fail>
 3215 07:36:41.443669  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_56 RESULT=fail
 3217 07:36:41.711328  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_56_nvmem-layout RESULT=skip>
 3218 07:36:41.711956  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_56_nvmem-layout RESULT=skip
 3220 07:36:41.968702  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_57 RESULT=fail>
 3221 07:36:41.969357  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_57 RESULT=fail
 3223 07:36:42.245200  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_57_nvmem-layout RESULT=skip>
 3224 07:36:42.245823  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_57_nvmem-layout RESULT=skip
 3226 07:36:42.516426  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass>
 3227 07:36:42.517086  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass
 3229 07:36:42.771643  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass>
 3230 07:36:42.772260  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass
 3232 07:36:42.997349  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass>
 3233 07:36:42.997962  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass
 3235 07:36:43.275623  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass>
 3236 07:36:43.276239  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass
 3238 07:36:43.586855  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass>
 3239 07:36:43.587472  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass
 3241 07:36:43.841070  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass>
 3242 07:36:43.841693  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass
 3244 07:36:44.118366  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass>
 3245 07:36:44.118990  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass
 3247 07:36:44.403098  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass>
 3248 07:36:44.403712  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass
 3250 07:36:44.653225  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass>
 3251 07:36:44.653843  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass
 3253 07:36:44.906288  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass>
 3254 07:36:44.906909  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass
 3256 07:36:45.168402  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass>
 3257 07:36:45.169047  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass
 3259 07:36:45.413798  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass>
 3260 07:36:45.414417  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass
 3262 07:36:45.667758  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass>
 3263 07:36:45.668393  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass
 3265 07:36:45.893752  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass>
 3266 07:36:45.894371  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass
 3268 07:36:46.233187  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip>
 3269 07:36:46.233801  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip
 3271 07:36:46.477470  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass>
 3272 07:36:46.478083  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass
 3274 07:36:46.702098  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass>
 3275 07:36:46.702718  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass
 3277 07:36:46.928945  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass>
 3278 07:36:46.929563  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass
 3280 07:36:47.171601  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass>
 3281 07:36:47.172215  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass
 3283 07:36:47.428846  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass>
 3284 07:36:47.429473  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass
 3286 07:36:47.668390  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass>
 3287 07:36:47.669010  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass
 3289 07:36:47.892745  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass>
 3290 07:36:47.893404  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass
 3292 07:36:48.123567  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail>
 3293 07:36:48.124185  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail
 3295 07:36:48.345779  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass>
 3296 07:36:48.346394  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass
 3298 07:36:48.582844  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass>
 3299 07:36:48.583460  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass
 3301 07:36:48.836940  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass>
 3302 07:36:48.837557  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass
 3304 07:36:49.086087  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass>
 3305 07:36:49.086701  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass
 3307 07:36:49.359460  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass>
 3308 07:36:49.360078  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass
 3310 07:36:49.621142  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass>
 3311 07:36:49.621757  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass
 3313 07:36:49.874248  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail>
 3314 07:36:49.874866  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail
 3316 07:36:50.129893  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip>
 3317 07:36:50.130515  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip
 3319 07:36:50.367250  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail>
 3320 07:36:50.367872  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail
 3322 07:36:50.591679  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip>
 3323 07:36:50.592297  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip
 3325 07:36:50.816614  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail>
 3326 07:36:50.817277  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail
 3328 07:36:51.053163  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail>
 3329 07:36:51.053778  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail
 3331 07:36:51.315285  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail>
 3332 07:36:51.315908  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail
 3334 07:36:51.523781  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail>
 3335 07:36:51.524403  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail
 3337 07:36:51.765188  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip>
 3338 07:36:51.765800  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip
 3340 07:36:51.848492  Marking unfinished test run as failed
 3343 07:36:51.849834  end: 3.1 lava-test-shell (duration 00:05:55) [common]
 3345 07:36:51.850708  lava-test-retry failed: 1 of 1 attempts. 'lava-test-shell timed out after 355 seconds'
 3347 07:36:51.851470  end: 3 lava-test-retry (duration 00:05:55) [common]
 3349 07:36:51.852521  Cleaning after the job
 3350 07:36:51.853025  Cleaning up download directory: /var/lib/lava/dispatcher/tmp/1216189/tftp-deploy-s4rhchl0/ramdisk
 3351 07:36:51.859159  Cleaning up download directory: /var/lib/lava/dispatcher/tmp/1216189/tftp-deploy-s4rhchl0/kernel
 3352 07:36:51.873098  Cleaning up download directory: /var/lib/lava/dispatcher/tmp/1216189/tftp-deploy-s4rhchl0/dtb
 3353 07:36:51.873871  Cleaning up download directory: /var/lib/lava/dispatcher/tmp/1216189/tftp-deploy-s4rhchl0/nfsrootfs
 3354 07:36:51.986581  Cleaning up download directory: /var/lib/lava/dispatcher/tmp/1216189/tftp-deploy-s4rhchl0/modules
 3355 07:36:51.992643  start: 4.1 power-off (timeout 00:00:30) [common]
 3356 07:36:51.993001  Calling: 'drpm' 'lf-bbb-02' 'off'
 3357 07:36:52.283016  >> OFF

 3358 07:36:52.283708  Returned 0 in 0 seconds
 3359 07:36:52.384265  end: 4.1 power-off (duration 00:00:00) [common]
 3361 07:36:52.384932  start: 4.2 read-feedback (timeout 00:10:00) [common]
 3362 07:36:52.385438  Listened to connection for namespace 'common' for up to 1s
 3365 07:36:52.386335  Listened to connection for namespace 'common' for up to 1s
 3366 07:36:52.454463  Listened to connection for namespace 'common' for up to 1s
 3368 07:36:52.463012  Listened to connection for namespace 'common' for up to 1s
 3369 07:36:52.711855  Listened to connection for namespace 'common' for up to 1s
 3370 07:36:52.716679  Listened to connection for namespace 'common' for up to 1s
 3372 07:36:53.386035  Finalising connection for namespace 'common'
 3373 07:36:53.386557  Disconnecting from shell: Finalise
 3374 07:36:53.386940  
 3375 07:36:53.487645  end: 4.2 read-feedback (duration 00:00:01) [common]
 3376 07:36:53.488084  Override tmp directory removed at /var/lib/lava/dispatcher/tmp/1216189
 3377 07:36:54.980504  Root tmp directory removed at /var/lib/lava/dispatcher/tmp/1216189
 3378 07:36:54.980897  TestError: A test failed to run, look at the error message.