Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: FAIL
- Kernel Errors: 0
1 07:40:06.515434 lava-dispatcher, installed at version: 2024.01
2 07:40:06.516238 start: 0 validate
3 07:40:06.516721 Start time: 2024-11-04 07:40:06.516688+00:00 (UTC)
4 07:40:06.517268 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 07:40:06.517813 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230703.0%2Farm64%2Frootfs.cpio.gz exists
6 07:40:06.554755 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 07:40:06.555343 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241104%2Farm64%2Fdefconfig%2BCONFIG_ARM64_16K_PAGES%3Dy%2Fgcc-12%2Fkernel%2FImage exists
8 07:40:06.588354 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 07:40:06.588982 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241104%2Farm64%2Fdefconfig%2BCONFIG_ARM64_16K_PAGES%3Dy%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 07:40:12.654519 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 07:40:12.655036 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241104%2Farm64%2Fdefconfig%2BCONFIG_ARM64_16K_PAGES%3Dy%2Fgcc-12%2Fmodules.tar.xz exists
12 07:40:13.711891 validate duration: 7.20
14 07:40:13.712801 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 07:40:13.713161 start: 1.1 download-retry (timeout 00:10:00) [common]
16 07:40:13.713498 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 07:40:13.714096 Not decompressing ramdisk as can be used compressed.
18 07:40:13.714543 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230703.0/arm64/rootfs.cpio.gz
19 07:40:13.714800 saving as /var/lib/lava/dispatcher/tmp/933335/tftp-deploy-ew_58eu0/ramdisk/rootfs.cpio.gz
20 07:40:13.715067 total size: 8181887 (7 MB)
21 07:40:13.756440 progress 0 % (0 MB)
22 07:40:13.767427 progress 5 % (0 MB)
23 07:40:13.778109 progress 10 % (0 MB)
24 07:40:13.789402 progress 15 % (1 MB)
25 07:40:13.796255 progress 20 % (1 MB)
26 07:40:13.802035 progress 25 % (1 MB)
27 07:40:13.807401 progress 30 % (2 MB)
28 07:40:13.813205 progress 35 % (2 MB)
29 07:40:13.818670 progress 40 % (3 MB)
30 07:40:13.824479 progress 45 % (3 MB)
31 07:40:13.829817 progress 50 % (3 MB)
32 07:40:13.835490 progress 55 % (4 MB)
33 07:40:13.840958 progress 60 % (4 MB)
34 07:40:13.846734 progress 65 % (5 MB)
35 07:40:13.852104 progress 70 % (5 MB)
36 07:40:13.857823 progress 75 % (5 MB)
37 07:40:13.863180 progress 80 % (6 MB)
38 07:40:13.868944 progress 85 % (6 MB)
39 07:40:13.874298 progress 90 % (7 MB)
40 07:40:13.880005 progress 95 % (7 MB)
41 07:40:13.884878 progress 100 % (7 MB)
42 07:40:13.885514 7 MB downloaded in 0.17 s (45.78 MB/s)
43 07:40:13.886061 end: 1.1.1 http-download (duration 00:00:00) [common]
45 07:40:13.886945 end: 1.1 download-retry (duration 00:00:00) [common]
46 07:40:13.887238 start: 1.2 download-retry (timeout 00:10:00) [common]
47 07:40:13.887509 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 07:40:13.888014 downloading http://storage.kernelci.org/next/master/next-20241104/arm64/defconfig+CONFIG_ARM64_16K_PAGES=y/gcc-12/kernel/Image
49 07:40:13.888263 saving as /var/lib/lava/dispatcher/tmp/933335/tftp-deploy-ew_58eu0/kernel/Image
50 07:40:13.888473 total size: 46260736 (44 MB)
51 07:40:13.888686 No compression specified
52 07:40:13.923228 progress 0 % (0 MB)
53 07:40:13.952619 progress 5 % (2 MB)
54 07:40:13.981963 progress 10 % (4 MB)
55 07:40:14.010947 progress 15 % (6 MB)
56 07:40:14.040931 progress 20 % (8 MB)
57 07:40:14.069910 progress 25 % (11 MB)
58 07:40:14.099100 progress 30 % (13 MB)
59 07:40:14.128246 progress 35 % (15 MB)
60 07:40:14.157398 progress 40 % (17 MB)
61 07:40:14.186511 progress 45 % (19 MB)
62 07:40:14.215333 progress 50 % (22 MB)
63 07:40:14.245030 progress 55 % (24 MB)
64 07:40:14.275055 progress 60 % (26 MB)
65 07:40:14.303958 progress 65 % (28 MB)
66 07:40:14.333465 progress 70 % (30 MB)
67 07:40:14.362559 progress 75 % (33 MB)
68 07:40:14.391728 progress 80 % (35 MB)
69 07:40:14.421015 progress 85 % (37 MB)
70 07:40:14.449755 progress 90 % (39 MB)
71 07:40:14.479162 progress 95 % (41 MB)
72 07:40:14.507547 progress 100 % (44 MB)
73 07:40:14.508291 44 MB downloaded in 0.62 s (71.18 MB/s)
74 07:40:14.508786 end: 1.2.1 http-download (duration 00:00:01) [common]
76 07:40:14.509605 end: 1.2 download-retry (duration 00:00:01) [common]
77 07:40:14.509880 start: 1.3 download-retry (timeout 00:09:59) [common]
78 07:40:14.510145 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 07:40:14.510626 downloading http://storage.kernelci.org/next/master/next-20241104/arm64/defconfig+CONFIG_ARM64_16K_PAGES=y/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
80 07:40:14.510898 saving as /var/lib/lava/dispatcher/tmp/933335/tftp-deploy-ew_58eu0/dtb/meson-g12b-a311d-libretech-cc.dtb
81 07:40:14.511110 total size: 54703 (0 MB)
82 07:40:14.511321 No compression specified
83 07:40:14.544995 progress 59 % (0 MB)
84 07:40:14.545832 progress 100 % (0 MB)
85 07:40:14.546383 0 MB downloaded in 0.04 s (1.48 MB/s)
86 07:40:14.546841 end: 1.3.1 http-download (duration 00:00:00) [common]
88 07:40:14.547660 end: 1.3 download-retry (duration 00:00:00) [common]
89 07:40:14.547920 start: 1.4 download-retry (timeout 00:09:59) [common]
90 07:40:14.548242 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 07:40:14.548743 downloading http://storage.kernelci.org/next/master/next-20241104/arm64/defconfig+CONFIG_ARM64_16K_PAGES=y/gcc-12/modules.tar.xz
92 07:40:14.548993 saving as /var/lib/lava/dispatcher/tmp/933335/tftp-deploy-ew_58eu0/modules/modules.tar
93 07:40:14.549203 total size: 11667732 (11 MB)
94 07:40:14.549415 Using unxz to decompress xz
95 07:40:14.585598 progress 0 % (0 MB)
96 07:40:14.652823 progress 5 % (0 MB)
97 07:40:14.726991 progress 10 % (1 MB)
98 07:40:14.823071 progress 15 % (1 MB)
99 07:40:14.919320 progress 20 % (2 MB)
100 07:40:14.999400 progress 25 % (2 MB)
101 07:40:15.070058 progress 30 % (3 MB)
102 07:40:15.148212 progress 35 % (3 MB)
103 07:40:15.224380 progress 40 % (4 MB)
104 07:40:15.299826 progress 45 % (5 MB)
105 07:40:15.384694 progress 50 % (5 MB)
106 07:40:15.461961 progress 55 % (6 MB)
107 07:40:15.547994 progress 60 % (6 MB)
108 07:40:15.628643 progress 65 % (7 MB)
109 07:40:15.709800 progress 70 % (7 MB)
110 07:40:15.791643 progress 75 % (8 MB)
111 07:40:15.870364 progress 80 % (8 MB)
112 07:40:15.951563 progress 85 % (9 MB)
113 07:40:16.035316 progress 90 % (10 MB)
114 07:40:16.112603 progress 95 % (10 MB)
115 07:40:16.189491 progress 100 % (11 MB)
116 07:40:16.199752 11 MB downloaded in 1.65 s (6.74 MB/s)
117 07:40:16.200592 end: 1.4.1 http-download (duration 00:00:02) [common]
119 07:40:16.202201 end: 1.4 download-retry (duration 00:00:02) [common]
120 07:40:16.202725 start: 1.5 prepare-tftp-overlay (timeout 00:09:58) [common]
121 07:40:16.203242 start: 1.5.1 extract-nfsrootfs (timeout 00:09:58) [common]
122 07:40:16.203734 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 07:40:16.204266 start: 1.5.2 lava-overlay (timeout 00:09:58) [common]
124 07:40:16.205255 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/933335/lava-overlay-wem4t2ty
125 07:40:16.206170 makedir: /var/lib/lava/dispatcher/tmp/933335/lava-overlay-wem4t2ty/lava-933335/bin
126 07:40:16.206833 makedir: /var/lib/lava/dispatcher/tmp/933335/lava-overlay-wem4t2ty/lava-933335/tests
127 07:40:16.207446 makedir: /var/lib/lava/dispatcher/tmp/933335/lava-overlay-wem4t2ty/lava-933335/results
128 07:40:16.208094 Creating /var/lib/lava/dispatcher/tmp/933335/lava-overlay-wem4t2ty/lava-933335/bin/lava-add-keys
129 07:40:16.209058 Creating /var/lib/lava/dispatcher/tmp/933335/lava-overlay-wem4t2ty/lava-933335/bin/lava-add-sources
130 07:40:16.209971 Creating /var/lib/lava/dispatcher/tmp/933335/lava-overlay-wem4t2ty/lava-933335/bin/lava-background-process-start
131 07:40:16.210897 Creating /var/lib/lava/dispatcher/tmp/933335/lava-overlay-wem4t2ty/lava-933335/bin/lava-background-process-stop
132 07:40:16.211869 Creating /var/lib/lava/dispatcher/tmp/933335/lava-overlay-wem4t2ty/lava-933335/bin/lava-common-functions
133 07:40:16.212826 Creating /var/lib/lava/dispatcher/tmp/933335/lava-overlay-wem4t2ty/lava-933335/bin/lava-echo-ipv4
134 07:40:16.213724 Creating /var/lib/lava/dispatcher/tmp/933335/lava-overlay-wem4t2ty/lava-933335/bin/lava-install-packages
135 07:40:16.214653 Creating /var/lib/lava/dispatcher/tmp/933335/lava-overlay-wem4t2ty/lava-933335/bin/lava-installed-packages
136 07:40:16.215632 Creating /var/lib/lava/dispatcher/tmp/933335/lava-overlay-wem4t2ty/lava-933335/bin/lava-os-build
137 07:40:16.216576 Creating /var/lib/lava/dispatcher/tmp/933335/lava-overlay-wem4t2ty/lava-933335/bin/lava-probe-channel
138 07:40:16.217463 Creating /var/lib/lava/dispatcher/tmp/933335/lava-overlay-wem4t2ty/lava-933335/bin/lava-probe-ip
139 07:40:16.218344 Creating /var/lib/lava/dispatcher/tmp/933335/lava-overlay-wem4t2ty/lava-933335/bin/lava-target-ip
140 07:40:16.219228 Creating /var/lib/lava/dispatcher/tmp/933335/lava-overlay-wem4t2ty/lava-933335/bin/lava-target-mac
141 07:40:16.220169 Creating /var/lib/lava/dispatcher/tmp/933335/lava-overlay-wem4t2ty/lava-933335/bin/lava-target-storage
142 07:40:16.221092 Creating /var/lib/lava/dispatcher/tmp/933335/lava-overlay-wem4t2ty/lava-933335/bin/lava-test-case
143 07:40:16.221983 Creating /var/lib/lava/dispatcher/tmp/933335/lava-overlay-wem4t2ty/lava-933335/bin/lava-test-event
144 07:40:16.222869 Creating /var/lib/lava/dispatcher/tmp/933335/lava-overlay-wem4t2ty/lava-933335/bin/lava-test-feedback
145 07:40:16.223823 Creating /var/lib/lava/dispatcher/tmp/933335/lava-overlay-wem4t2ty/lava-933335/bin/lava-test-raise
146 07:40:16.224800 Creating /var/lib/lava/dispatcher/tmp/933335/lava-overlay-wem4t2ty/lava-933335/bin/lava-test-reference
147 07:40:16.225700 Creating /var/lib/lava/dispatcher/tmp/933335/lava-overlay-wem4t2ty/lava-933335/bin/lava-test-runner
148 07:40:16.226590 Creating /var/lib/lava/dispatcher/tmp/933335/lava-overlay-wem4t2ty/lava-933335/bin/lava-test-set
149 07:40:16.227479 Creating /var/lib/lava/dispatcher/tmp/933335/lava-overlay-wem4t2ty/lava-933335/bin/lava-test-shell
150 07:40:16.228422 Updating /var/lib/lava/dispatcher/tmp/933335/lava-overlay-wem4t2ty/lava-933335/bin/lava-install-packages (oe)
151 07:40:16.229387 Updating /var/lib/lava/dispatcher/tmp/933335/lava-overlay-wem4t2ty/lava-933335/bin/lava-installed-packages (oe)
152 07:40:16.230207 Creating /var/lib/lava/dispatcher/tmp/933335/lava-overlay-wem4t2ty/lava-933335/environment
153 07:40:16.230920 LAVA metadata
154 07:40:16.231406 - LAVA_JOB_ID=933335
155 07:40:16.231834 - LAVA_DISPATCHER_IP=192.168.6.2
156 07:40:16.232531 start: 1.5.2.1 ssh-authorize (timeout 00:09:57) [common]
157 07:40:16.234318 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 07:40:16.234906 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:57) [common]
159 07:40:16.235320 skipped lava-vland-overlay
160 07:40:16.235806 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 07:40:16.236364 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:57) [common]
162 07:40:16.236795 skipped lava-multinode-overlay
163 07:40:16.237284 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 07:40:16.237786 start: 1.5.2.4 test-definition (timeout 00:09:57) [common]
165 07:40:16.238260 Loading test definitions
166 07:40:16.238803 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:57) [common]
167 07:40:16.239245 Using /lava-933335 at stage 0
168 07:40:16.240880 uuid=933335_1.5.2.4.1 testdef=None
169 07:40:16.241217 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 07:40:16.241489 start: 1.5.2.4.2 test-overlay (timeout 00:09:57) [common]
171 07:40:16.243362 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 07:40:16.244220 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:57) [common]
174 07:40:16.246524 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 07:40:16.247373 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:57) [common]
177 07:40:16.249588 runner path: /var/lib/lava/dispatcher/tmp/933335/lava-overlay-wem4t2ty/lava-933335/0/tests/0_dmesg test_uuid 933335_1.5.2.4.1
178 07:40:16.250164 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 07:40:16.250952 Creating lava-test-runner.conf files
181 07:40:16.251159 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/933335/lava-overlay-wem4t2ty/lava-933335/0 for stage 0
182 07:40:16.251503 - 0_dmesg
183 07:40:16.251855 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 07:40:16.252174 start: 1.5.2.5 compress-overlay (timeout 00:09:57) [common]
185 07:40:16.275659 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 07:40:16.276122 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:57) [common]
187 07:40:16.276402 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 07:40:16.276674 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 07:40:16.276938 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:57) [common]
190 07:40:17.212758 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
191 07:40:17.213215 start: 1.5.4 extract-modules (timeout 00:09:56) [common]
192 07:40:17.213468 extracting modules file /var/lib/lava/dispatcher/tmp/933335/tftp-deploy-ew_58eu0/modules/modules.tar to /var/lib/lava/dispatcher/tmp/933335/extract-overlay-ramdisk-meff9k2s/ramdisk
193 07:40:18.573537 end: 1.5.4 extract-modules (duration 00:00:01) [common]
194 07:40:18.574013 start: 1.5.5 apply-overlay-tftp (timeout 00:09:55) [common]
195 07:40:18.574294 [common] Applying overlay /var/lib/lava/dispatcher/tmp/933335/compress-overlay-0ypn8atp/overlay-1.5.2.5.tar.gz to ramdisk
196 07:40:18.574512 [common] Applying overlay /var/lib/lava/dispatcher/tmp/933335/compress-overlay-0ypn8atp/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/933335/extract-overlay-ramdisk-meff9k2s/ramdisk
197 07:40:18.605142 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 07:40:18.605558 start: 1.5.6 prepare-kernel (timeout 00:09:55) [common]
199 07:40:18.605834 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:55) [common]
200 07:40:18.606083 Converting downloaded kernel to a uImage
201 07:40:18.606397 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/933335/tftp-deploy-ew_58eu0/kernel/Image /var/lib/lava/dispatcher/tmp/933335/tftp-deploy-ew_58eu0/kernel/uImage
202 07:40:19.061204 output: Image Name:
203 07:40:19.061623 output: Created: Mon Nov 4 07:40:18 2024
204 07:40:19.061834 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 07:40:19.062041 output: Data Size: 46260736 Bytes = 45176.50 KiB = 44.12 MiB
206 07:40:19.062245 output: Load Address: 01080000
207 07:40:19.062444 output: Entry Point: 01080000
208 07:40:19.062641 output:
209 07:40:19.062977 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
210 07:40:19.063243 end: 1.5.6 prepare-kernel (duration 00:00:00) [common]
211 07:40:19.063516 start: 1.5.7 configure-preseed-file (timeout 00:09:55) [common]
212 07:40:19.063771 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 07:40:19.064072 start: 1.5.8 compress-ramdisk (timeout 00:09:55) [common]
214 07:40:19.064346 Building ramdisk /var/lib/lava/dispatcher/tmp/933335/extract-overlay-ramdisk-meff9k2s/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/933335/extract-overlay-ramdisk-meff9k2s/ramdisk
215 07:40:21.524950 >> 182740 blocks
216 07:40:29.961214 Adding RAMdisk u-boot header.
217 07:40:29.961743 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/933335/extract-overlay-ramdisk-meff9k2s/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/933335/extract-overlay-ramdisk-meff9k2s/ramdisk.cpio.gz.uboot
218 07:40:30.238302 output: Image Name:
219 07:40:30.238723 output: Created: Mon Nov 4 07:40:29 2024
220 07:40:30.238933 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 07:40:30.239141 output: Data Size: 26159668 Bytes = 25546.55 KiB = 24.95 MiB
222 07:40:30.239343 output: Load Address: 00000000
223 07:40:30.239541 output: Entry Point: 00000000
224 07:40:30.239737 output:
225 07:40:30.240622 rename /var/lib/lava/dispatcher/tmp/933335/extract-overlay-ramdisk-meff9k2s/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/933335/tftp-deploy-ew_58eu0/ramdisk/ramdisk.cpio.gz.uboot
226 07:40:30.241353 end: 1.5.8 compress-ramdisk (duration 00:00:11) [common]
227 07:40:30.241897 end: 1.5 prepare-tftp-overlay (duration 00:00:14) [common]
228 07:40:30.242417 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:43) [common]
229 07:40:30.242867 No LXC device requested
230 07:40:30.243360 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 07:40:30.243862 start: 1.7 deploy-device-env (timeout 00:09:43) [common]
232 07:40:30.244396 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 07:40:30.244811 Checking files for TFTP limit of 4294967296 bytes.
234 07:40:30.247425 end: 1 tftp-deploy (duration 00:00:17) [common]
235 07:40:30.248023 start: 2 uboot-action (timeout 00:05:00) [common]
236 07:40:30.248623 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 07:40:30.249156 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 07:40:30.249659 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 07:40:30.250193 Using kernel file from prepare-kernel: 933335/tftp-deploy-ew_58eu0/kernel/uImage
240 07:40:30.250816 substitutions:
241 07:40:30.251226 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 07:40:30.251627 - {DTB_ADDR}: 0x01070000
243 07:40:30.252057 - {DTB}: 933335/tftp-deploy-ew_58eu0/dtb/meson-g12b-a311d-libretech-cc.dtb
244 07:40:30.252464 - {INITRD}: 933335/tftp-deploy-ew_58eu0/ramdisk/ramdisk.cpio.gz.uboot
245 07:40:30.252863 - {KERNEL_ADDR}: 0x01080000
246 07:40:30.253255 - {KERNEL}: 933335/tftp-deploy-ew_58eu0/kernel/uImage
247 07:40:30.253652 - {LAVA_MAC}: None
248 07:40:30.254087 - {PRESEED_CONFIG}: None
249 07:40:30.254484 - {PRESEED_LOCAL}: None
250 07:40:30.254875 - {RAMDISK_ADDR}: 0x08000000
251 07:40:30.255265 - {RAMDISK}: 933335/tftp-deploy-ew_58eu0/ramdisk/ramdisk.cpio.gz.uboot
252 07:40:30.255661 - {ROOT_PART}: None
253 07:40:30.256076 - {ROOT}: None
254 07:40:30.256468 - {SERVER_IP}: 192.168.6.2
255 07:40:30.256861 - {TEE_ADDR}: 0x83000000
256 07:40:30.257251 - {TEE}: None
257 07:40:30.257640 Parsed boot commands:
258 07:40:30.258019 - setenv autoload no
259 07:40:30.258410 - setenv initrd_high 0xffffffff
260 07:40:30.258796 - setenv fdt_high 0xffffffff
261 07:40:30.259181 - dhcp
262 07:40:30.259569 - setenv serverip 192.168.6.2
263 07:40:30.259956 - tftpboot 0x01080000 933335/tftp-deploy-ew_58eu0/kernel/uImage
264 07:40:30.260403 - tftpboot 0x08000000 933335/tftp-deploy-ew_58eu0/ramdisk/ramdisk.cpio.gz.uboot
265 07:40:30.260795 - tftpboot 0x01070000 933335/tftp-deploy-ew_58eu0/dtb/meson-g12b-a311d-libretech-cc.dtb
266 07:40:30.261184 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 07:40:30.261576 - bootm 0x01080000 0x08000000 0x01070000
268 07:40:30.262069 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 07:40:30.263558 start: 2.3 connect-device (timeout 00:05:00) [common]
271 07:40:30.264029 [common] connect-device Connecting to device using 'telnet conserv1 3007'
272 07:40:30.278503 Setting prompt string to ['lava-test: # ']
273 07:40:30.280020 end: 2.3 connect-device (duration 00:00:00) [common]
274 07:40:30.280622 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 07:40:30.281164 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 07:40:30.281686 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 07:40:30.282940 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
278 07:40:30.320269 >> OK - accepted request
279 07:40:30.322328 Returned 0 in 0 seconds
280 07:40:30.423440 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
282 07:40:30.425202 end: 2.4.1 reset-device (duration 00:00:00) [common]
283 07:40:30.425797 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
284 07:40:30.426321 Setting prompt string to ['Hit any key to stop autoboot']
285 07:40:30.426789 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 07:40:30.428433 Trying 192.168.56.21...
287 07:40:30.428916 Connected to conserv1.
288 07:40:30.429336 Escape character is '^]'.
289 07:40:30.429766
290 07:40:30.430191 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
291 07:40:30.430623
292 07:40:42.401746 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
293 07:40:42.402386 bl2_stage_init 0x01
294 07:40:42.402851 bl2_stage_init 0x81
295 07:40:42.407335 hw id: 0x0000 - pwm id 0x01
296 07:40:42.407900 bl2_stage_init 0xc1
297 07:40:42.408411 bl2_stage_init 0x02
298 07:40:42.408821
299 07:40:42.412980 L0:00000000
300 07:40:42.413434 L1:20000703
301 07:40:42.413849 L2:00008067
302 07:40:42.414247 L3:14000000
303 07:40:42.418384 B2:00402000
304 07:40:42.418855 B1:e0f83180
305 07:40:42.419246
306 07:40:42.419635 TE: 58124
307 07:40:42.420061
308 07:40:42.424074 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
309 07:40:42.424510
310 07:40:42.424900 Board ID = 1
311 07:40:42.429559 Set A53 clk to 24M
312 07:40:42.429984 Set A73 clk to 24M
313 07:40:42.430373 Set clk81 to 24M
314 07:40:42.435214 A53 clk: 1200 MHz
315 07:40:42.435630 A73 clk: 1200 MHz
316 07:40:42.436043 CLK81: 166.6M
317 07:40:42.436431 smccc: 00012a92
318 07:40:42.440834 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
319 07:40:42.446455 board id: 1
320 07:40:42.452321 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
321 07:40:42.463022 fw parse done
322 07:40:42.469090 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
323 07:40:42.511529 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
324 07:40:42.522384 PIEI prepare done
325 07:40:42.522805 fastboot data load
326 07:40:42.523197 fastboot data verify
327 07:40:42.528106 verify result: 266
328 07:40:42.533770 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
329 07:40:42.534186 LPDDR4 probe
330 07:40:42.534572 ddr clk to 1584MHz
331 07:40:42.541660 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
332 07:40:42.578928
333 07:40:42.579440 dmc_version 0001
334 07:40:42.585617 Check phy result
335 07:40:42.591502 INFO : End of CA training
336 07:40:42.591940 INFO : End of initialization
337 07:40:42.597032 INFO : Training has run successfully!
338 07:40:42.597459 Check phy result
339 07:40:42.602656 INFO : End of initialization
340 07:40:42.603087 INFO : End of read enable training
341 07:40:42.608228 INFO : End of fine write leveling
342 07:40:42.613838 INFO : End of Write leveling coarse delay
343 07:40:42.614260 INFO : Training has run successfully!
344 07:40:42.614662 Check phy result
345 07:40:42.619439 INFO : End of initialization
346 07:40:42.619871 INFO : End of read dq deskew training
347 07:40:42.625089 INFO : End of MPR read delay center optimization
348 07:40:42.630596 INFO : End of write delay center optimization
349 07:40:42.636249 INFO : End of read delay center optimization
350 07:40:42.636673 INFO : End of max read latency training
351 07:40:42.641836 INFO : Training has run successfully!
352 07:40:42.642261 1D training succeed
353 07:40:42.651035 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
354 07:40:42.698614 Check phy result
355 07:40:42.699057 INFO : End of initialization
356 07:40:42.721216 INFO : End of 2D read delay Voltage center optimization
357 07:40:42.741485 INFO : End of 2D read delay Voltage center optimization
358 07:40:42.793469 INFO : End of 2D write delay Voltage center optimization
359 07:40:42.842897 INFO : End of 2D write delay Voltage center optimization
360 07:40:42.848475 INFO : Training has run successfully!
361 07:40:42.848904
362 07:40:42.849311 channel==0
363 07:40:42.854034 RxClkDly_Margin_A0==88 ps 9
364 07:40:42.854465 TxDqDly_Margin_A0==98 ps 10
365 07:40:42.859715 RxClkDly_Margin_A1==88 ps 9
366 07:40:42.860177 TxDqDly_Margin_A1==98 ps 10
367 07:40:42.860583 TrainedVREFDQ_A0==74
368 07:40:42.865378 TrainedVREFDQ_A1==74
369 07:40:42.865806 VrefDac_Margin_A0==24
370 07:40:42.866207 DeviceVref_Margin_A0==40
371 07:40:42.870802 VrefDac_Margin_A1==25
372 07:40:42.871229 DeviceVref_Margin_A1==40
373 07:40:42.871632
374 07:40:42.872063
375 07:40:42.876438 channel==1
376 07:40:42.876857 RxClkDly_Margin_A0==88 ps 9
377 07:40:42.877257 TxDqDly_Margin_A0==98 ps 10
378 07:40:42.882025 RxClkDly_Margin_A1==88 ps 9
379 07:40:42.882453 TxDqDly_Margin_A1==88 ps 9
380 07:40:42.887674 TrainedVREFDQ_A0==77
381 07:40:42.888130 TrainedVREFDQ_A1==77
382 07:40:42.888538 VrefDac_Margin_A0==22
383 07:40:42.893285 DeviceVref_Margin_A0==37
384 07:40:42.893711 VrefDac_Margin_A1==24
385 07:40:42.898808 DeviceVref_Margin_A1==37
386 07:40:42.899253
387 07:40:42.899666 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
388 07:40:42.900098
389 07:40:42.932440 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000018 00000018 00000017 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000017 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
390 07:40:42.932959 2D training succeed
391 07:40:42.938013 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
392 07:40:42.943561 auto size-- 65535DDR cs0 size: 2048MB
393 07:40:42.944012 DDR cs1 size: 2048MB
394 07:40:42.949167 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
395 07:40:42.949592 cs0 DataBus test pass
396 07:40:42.954754 cs1 DataBus test pass
397 07:40:42.955175 cs0 AddrBus test pass
398 07:40:42.955572 cs1 AddrBus test pass
399 07:40:42.955968
400 07:40:42.960356 100bdlr_step_size ps== 420
401 07:40:42.960798 result report
402 07:40:42.965917 boot times 0Enable ddr reg access
403 07:40:42.971192 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
404 07:40:42.984692 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
405 07:40:43.558402 0.0;M3 CHK:0;cm4_sp_mode 0
406 07:40:43.558907 MVN_1=0x00000000
407 07:40:43.563851 MVN_2=0x00000000
408 07:40:43.569627 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
409 07:40:43.570095 OPS=0x10
410 07:40:43.570545 ring efuse init
411 07:40:43.570960 chipver efuse init
412 07:40:43.575239 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
413 07:40:43.580838 [0.018961 Inits done]
414 07:40:43.581272 secure task start!
415 07:40:43.581682 high task start!
416 07:40:43.585411 low task start!
417 07:40:43.585857 run into bl31
418 07:40:43.592064 NOTICE: BL31: v1.3(release):4fc40b1
419 07:40:43.599834 NOTICE: BL31: Built : 15:58:17, May 22 2019
420 07:40:43.600298 NOTICE: BL31: G12A normal boot!
421 07:40:43.625204 NOTICE: BL31: BL33 decompress pass
422 07:40:43.630966 ERROR: Error initializing runtime service opteed_fast
423 07:40:44.863763
424 07:40:44.864348
425 07:40:44.872114 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
426 07:40:44.872550
427 07:40:44.872961 Model: Libre Computer AML-A311D-CC Alta
428 07:40:45.080644 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
429 07:40:45.103950 DRAM: 2 GiB (effective 3.8 GiB)
430 07:40:45.246967 Core: 408 devices, 31 uclasses, devicetree: separate
431 07:40:45.252790 WDT: Not starting watchdog@f0d0
432 07:40:45.285059 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
433 07:40:45.297528 Loading Environment from FAT... Card did not respond to voltage select! : -110
434 07:40:45.302504 ** Bad device specification mmc 0 **
435 07:40:45.312849 Card did not respond to voltage select! : -110
436 07:40:45.320514 ** Bad device specification mmc 0 **
437 07:40:45.320962 Couldn't find partition mmc 0
438 07:40:45.328817 Card did not respond to voltage select! : -110
439 07:40:46.570693 ** Bad device specification mmc 0 **
G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
440 07:40:46.571324 bl2_stage_init 0x01
441 07:40:46.571589 bl2_stage_init 0x81
442 07:40:46.576166 hw id: 0x0000 - pwm id 0x01
443 07:40:46.576582 bl2_stage_init 0xc1
444 07:40:46.576942 bl2_stage_init 0x02
445 07:40:46.577291
446 07:40:46.581811 L0:00000000
447 07:40:46.582359 L1:20000703
448 07:40:46.582827 L2:00008067
449 07:40:46.583286 L3:14000000
450 07:40:46.587399 B2:00402000
451 07:40:46.587896 B1:e0f83180
452 07:40:46.588386
453 07:40:46.588838 TE: 58124
454 07:40:46.589285
455 07:40:46.593010 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
456 07:40:46.593505
457 07:40:46.593965 Board ID = 1
458 07:40:46.598582 Set A53 clk to 24M
459 07:40:46.599075 Set A73 clk to 24M
460 07:40:46.599527 Set clk81 to 24M
461 07:40:46.604202 A53 clk: 1200 MHz
462 07:40:46.604696 A73 clk: 1200 MHz
463 07:40:46.605150 CLK81: 166.6M
464 07:40:46.605595 smccc: 00012a92
465 07:40:46.609775 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
466 07:40:46.615391 board id: 1
467 07:40:46.621282 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
468 07:40:46.631932 fw parse done
469 07:40:46.637883 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
470 07:40:46.680495 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
471 07:40:46.691404 PIEI prepare done
472 07:40:46.691913 fastboot data load
473 07:40:46.692426 fastboot data verify
474 07:40:46.697176 verify result: 266
475 07:40:46.702747 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
476 07:40:46.703281 LPDDR4 probe
477 07:40:46.703739 ddr clk to 1584MHz
478 07:40:46.710727 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
479 07:40:46.748032
480 07:40:46.748593 dmc_version 0001
481 07:40:46.754676 Check phy result
482 07:40:46.760545 INFO : End of CA training
483 07:40:46.761083 INFO : End of initialization
484 07:40:46.766113 INFO : Training has run successfully!
485 07:40:46.766658 Check phy result
486 07:40:46.771731 INFO : End of initialization
487 07:40:46.772308 INFO : End of read enable training
488 07:40:46.777301 INFO : End of fine write leveling
489 07:40:46.782918 INFO : End of Write leveling coarse delay
490 07:40:46.783458 INFO : Training has run successfully!
491 07:40:46.783930 Check phy result
492 07:40:46.788540 INFO : End of initialization
493 07:40:46.789079 INFO : End of read dq deskew training
494 07:40:46.794111 INFO : End of MPR read delay center optimization
495 07:40:46.799734 INFO : End of write delay center optimization
496 07:40:46.805334 INFO : End of read delay center optimization
497 07:40:46.805874 INFO : End of max read latency training
498 07:40:46.810937 INFO : Training has run successfully!
499 07:40:46.811486 1D training succeed
500 07:40:46.820051 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
501 07:40:46.867725 Check phy result
502 07:40:46.868356 INFO : End of initialization
503 07:40:46.889322 INFO : End of 2D read delay Voltage center optimization
504 07:40:46.909428 INFO : End of 2D read delay Voltage center optimization
505 07:40:46.960557 INFO : End of 2D write delay Voltage center optimization
506 07:40:47.010627 INFO : End of 2D write delay Voltage center optimization
507 07:40:47.016057 INFO : Training has run successfully!
508 07:40:47.016585
509 07:40:47.017061 channel==0
510 07:40:47.021612 RxClkDly_Margin_A0==88 ps 9
511 07:40:47.022110 TxDqDly_Margin_A0==98 ps 10
512 07:40:47.027194 RxClkDly_Margin_A1==88 ps 9
513 07:40:47.027689 TxDqDly_Margin_A1==98 ps 10
514 07:40:47.028192 TrainedVREFDQ_A0==74
515 07:40:47.032825 TrainedVREFDQ_A1==74
516 07:40:47.033334 VrefDac_Margin_A0==25
517 07:40:47.033793 DeviceVref_Margin_A0==40
518 07:40:47.038473 VrefDac_Margin_A1==25
519 07:40:47.038970 DeviceVref_Margin_A1==40
520 07:40:47.039430
521 07:40:47.039884
522 07:40:47.044013 channel==1
523 07:40:47.044515 RxClkDly_Margin_A0==98 ps 10
524 07:40:47.044971 TxDqDly_Margin_A0==98 ps 10
525 07:40:47.049586 RxClkDly_Margin_A1==88 ps 9
526 07:40:47.050085 TxDqDly_Margin_A1==88 ps 9
527 07:40:47.055192 TrainedVREFDQ_A0==76
528 07:40:47.055692 TrainedVREFDQ_A1==77
529 07:40:47.056184 VrefDac_Margin_A0==22
530 07:40:47.060830 DeviceVref_Margin_A0==38
531 07:40:47.061319 VrefDac_Margin_A1==24
532 07:40:47.066406 DeviceVref_Margin_A1==37
533 07:40:47.066900
534 07:40:47.067354 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
535 07:40:47.067807
536 07:40:47.100018 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000018 00000019 00000017 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
537 07:40:47.100595 2D training succeed
538 07:40:47.105621 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
539 07:40:47.111232 auto size-- 65535DDR cs0 size: 2048MB
540 07:40:47.111738 DDR cs1 size: 2048MB
541 07:40:47.116831 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
542 07:40:47.117347 cs0 DataBus test pass
543 07:40:47.122494 cs1 DataBus test pass
544 07:40:47.123000 cs0 AddrBus test pass
545 07:40:47.123461 cs1 AddrBus test pass
546 07:40:47.123912
547 07:40:47.128035 100bdlr_step_size ps== 420
548 07:40:47.128550 result report
549 07:40:47.133618 boot times 0Enable ddr reg access
550 07:40:47.138952 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
551 07:40:47.152457 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
552 07:40:47.724471 0.0;M3 CHK:0;cm4_sp_mode 0
553 07:40:47.725109 MVN_1=0x00000000
554 07:40:47.729929 MVN_2=0x00000000
555 07:40:47.735688 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
556 07:40:47.736331 OPS=0x10
557 07:40:47.736808 ring efuse init
558 07:40:47.737307 chipver efuse init
559 07:40:47.741311 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
560 07:40:47.746863 [0.018961 Inits done]
561 07:40:47.747353 secure task start!
562 07:40:47.747785 high task start!
563 07:40:47.751459 low task start!
564 07:40:47.751940 run into bl31
565 07:40:47.758101 NOTICE: BL31: v1.3(release):4fc40b1
566 07:40:47.765904 NOTICE: BL31: Built : 15:58:17, May 22 2019
567 07:40:47.766395 NOTICE: BL31: G12A normal boot!
568 07:40:47.791250 NOTICE: BL31: BL33 decompress pass
569 07:40:47.796939 ERROR: Error initializing runtime service opteed_fast
570 07:40:49.030038
571 07:40:49.030713
572 07:40:49.038435 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
573 07:40:49.038950
574 07:40:49.039417 Model: Libre Computer AML-A311D-CC Alta
575 07:40:49.246929 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
576 07:40:49.270189 DRAM: 2 GiB (effective 3.8 GiB)
577 07:40:49.413147 Core: 408 devices, 31 uclasses, devicetree: separate
578 07:40:49.419028 WDT: Not starting watchdog@f0d0
579 07:40:49.451273 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
580 07:40:49.463715 Loading Environment from FAT... Card did not respond to voltage select! : -110
581 07:40:49.468829 ** Bad device specification mmc 0 **
582 07:40:49.479066 Card did not respond to voltage select! : -110
583 07:40:49.486670 ** Bad device specification mmc 0 **
584 07:40:49.487158 Couldn't find partition mmc 0
585 07:40:49.494978 Card did not respond to voltage select! : -110
586 07:40:49.500398 ** Bad device specification mmc 0 **
587 07:40:49.500888 Couldn't find partition mmc 0
588 07:40:49.505570 Error: could not access storage.
589 07:40:49.849167 Net: eth0: ethernet@ff3f0000
590 07:40:49.849700 starting USB...
591 07:40:50.100935 Bus usb@ff500000: Register 3000140 NbrPorts 3
592 07:40:50.101564 Starting the controller
593 07:40:50.107964 USB XHCI 1.10
594 07:40:51.821028 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
595 07:40:51.821674 bl2_stage_init 0x01
596 07:40:51.822149 bl2_stage_init 0x81
597 07:40:51.826571 hw id: 0x0000 - pwm id 0x01
598 07:40:51.827069 bl2_stage_init 0xc1
599 07:40:51.827531 bl2_stage_init 0x02
600 07:40:51.828024
601 07:40:51.832078 L0:00000000
602 07:40:51.832570 L1:20000703
603 07:40:51.833026 L2:00008067
604 07:40:51.833475 L3:14000000
605 07:40:51.835033 B2:00402000
606 07:40:51.835516 B1:e0f83180
607 07:40:51.835965
608 07:40:51.836454 TE: 58124
609 07:40:51.836902
610 07:40:51.846169 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
611 07:40:51.846688
612 07:40:51.847148 Board ID = 1
613 07:40:51.847594 Set A53 clk to 24M
614 07:40:51.848079 Set A73 clk to 24M
615 07:40:51.851776 Set clk81 to 24M
616 07:40:51.852289 A53 clk: 1200 MHz
617 07:40:51.852746 A73 clk: 1200 MHz
618 07:40:51.857425 CLK81: 166.6M
619 07:40:51.857908 smccc: 00012a92
620 07:40:51.863033 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
621 07:40:51.863524 board id: 1
622 07:40:51.871622 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
623 07:40:51.882179 fw parse done
624 07:40:51.888204 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
625 07:40:51.930790 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
626 07:40:51.941634 PIEI prepare done
627 07:40:51.942121 fastboot data load
628 07:40:51.942577 fastboot data verify
629 07:40:51.947240 verify result: 266
630 07:40:51.952824 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
631 07:40:51.953332 LPDDR4 probe
632 07:40:51.953788 ddr clk to 1584MHz
633 07:40:51.960811 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
634 07:40:51.998448
635 07:40:51.999012 dmc_version 0001
636 07:40:52.004765 Check phy result
637 07:40:52.010611 INFO : End of CA training
638 07:40:52.011099 INFO : End of initialization
639 07:40:52.016258 INFO : Training has run successfully!
640 07:40:52.016746 Check phy result
641 07:40:52.021826 INFO : End of initialization
642 07:40:52.022312 INFO : End of read enable training
643 07:40:52.025208 INFO : End of fine write leveling
644 07:40:52.030777 INFO : End of Write leveling coarse delay
645 07:40:52.036372 INFO : Training has run successfully!
646 07:40:52.036852 Check phy result
647 07:40:52.037304 INFO : End of initialization
648 07:40:52.041958 INFO : End of read dq deskew training
649 07:40:52.047589 INFO : End of MPR read delay center optimization
650 07:40:52.048114 INFO : End of write delay center optimization
651 07:40:52.053173 INFO : End of read delay center optimization
652 07:40:52.058753 INFO : End of max read latency training
653 07:40:52.059231 INFO : Training has run successfully!
654 07:40:52.064347 1D training succeed
655 07:40:52.070261 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
656 07:40:52.117850 Check phy result
657 07:40:52.118338 INFO : End of initialization
658 07:40:52.139552 INFO : End of 2D read delay Voltage center optimization
659 07:40:52.159799 INFO : End of 2D read delay Voltage center optimization
660 07:40:52.211855 INFO : End of 2D write delay Voltage center optimization
661 07:40:52.261307 INFO : End of 2D write delay Voltage center optimization
662 07:40:52.266820 INFO : Training has run successfully!
663 07:40:52.267334
664 07:40:52.267804 channel==0
665 07:40:52.272421 RxClkDly_Margin_A0==78 ps 8
666 07:40:52.272939 TxDqDly_Margin_A0==98 ps 10
667 07:40:52.278012 RxClkDly_Margin_A1==88 ps 9
668 07:40:52.278554 TxDqDly_Margin_A1==98 ps 10
669 07:40:52.279031 TrainedVREFDQ_A0==74
670 07:40:52.283549 TrainedVREFDQ_A1==74
671 07:40:52.284134 VrefDac_Margin_A0==25
672 07:40:52.284612 DeviceVref_Margin_A0==40
673 07:40:52.289128 VrefDac_Margin_A1==25
674 07:40:52.289628 DeviceVref_Margin_A1==40
675 07:40:52.290084
676 07:40:52.290535
677 07:40:52.294724 channel==1
678 07:40:52.295219 RxClkDly_Margin_A0==98 ps 10
679 07:40:52.295678 TxDqDly_Margin_A0==98 ps 10
680 07:40:52.300383 RxClkDly_Margin_A1==98 ps 10
681 07:40:52.300877 TxDqDly_Margin_A1==88 ps 9
682 07:40:52.306004 TrainedVREFDQ_A0==77
683 07:40:52.306511 TrainedVREFDQ_A1==77
684 07:40:52.306972 VrefDac_Margin_A0==22
685 07:40:52.311501 DeviceVref_Margin_A0==37
686 07:40:52.312024 VrefDac_Margin_A1==22
687 07:40:52.317281 DeviceVref_Margin_A1==37
688 07:40:52.317777
689 07:40:52.318236 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
690 07:40:52.322819
691 07:40:52.350680 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000018 00000018 00000016 00000017 00000016 00000018 00000019 00000018 00000019 00000018 0000001a 0000001a 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
692 07:40:52.351216 2D training succeed
693 07:40:52.356297 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
694 07:40:52.361865 auto size-- 65535DDR cs0 size: 2048MB
695 07:40:52.362363 DDR cs1 size: 2048MB
696 07:40:52.367455 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
697 07:40:52.367957 cs0 DataBus test pass
698 07:40:52.373164 cs1 DataBus test pass
699 07:40:52.373662 cs0 AddrBus test pass
700 07:40:52.374113 cs1 AddrBus test pass
701 07:40:52.374564
702 07:40:52.378653 100bdlr_step_size ps== 420
703 07:40:52.379169 result report
704 07:40:52.384282 boot times 0Enable ddr reg access
705 07:40:52.389706 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
706 07:40:52.403219 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
707 07:40:52.976968 0.0;M3 CHK:0;cm4_sp_mode 0
708 07:40:52.977615 MVN_1=0x00000000
709 07:40:52.982469 MVN_2=0x00000000
710 07:40:52.988281 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
711 07:40:52.988872 OPS=0x10
712 07:40:52.989317 ring efuse init
713 07:40:52.989750 chipver efuse init
714 07:40:52.993778 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
715 07:40:52.999363 [0.018961 Inits done]
716 07:40:52.999855 secure task start!
717 07:40:53.000344 high task start!
718 07:40:53.003963 low task start!
719 07:40:53.004473 run into bl31
720 07:40:53.010570 NOTICE: BL31: v1.3(release):4fc40b1
721 07:40:53.018434 NOTICE: BL31: Built : 15:58:17, May 22 2019
722 07:40:53.018920 NOTICE: BL31: G12A normal boot!
723 07:40:53.043807 NOTICE: BL31: BL33 decompress pass
724 07:40:53.049476 ERROR: Error initializing runtime service opteed_fast
725 07:40:54.282380
726 07:40:54.283059
727 07:40:54.290960 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
728 07:40:54.291540
729 07:40:54.292079 Model: Libre Computer AML-A311D-CC Alta
730 07:40:54.499271 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
731 07:40:54.522763 DRAM: 2 GiB (effective 3.8 GiB)
732 07:40:54.665654 Core: 408 devices, 31 uclasses, devicetree: separate
733 07:40:54.671655 WDT: Not starting watchdog@f0d0
734 07:40:54.703877 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
735 07:40:54.716273 Loading Environment from FAT... Card did not respond to voltage select! : -110
736 07:40:54.721245 ** Bad device specification mmc 0 **
737 07:40:54.731626 Card did not respond to voltage select! : -110
738 07:40:54.739303 ** Bad device specification mmc 0 **
739 07:40:54.739879 Couldn't find partition mmc 0
740 07:40:54.747682 Card did not respond to voltage select! : -110
741 07:40:54.753164 ** Bad device specification mmc 0 **
742 07:40:54.753735 Couldn't find partition mmc 0
743 07:40:54.758191 Error: could not access storage.
744 07:40:55.100637 Net: eth0: ethernet@ff3f0000
745 07:40:55.101296 starting USB...
746 07:40:55.352381 Bus usb@ff500000: Register 3000140 NbrPorts 3
747 07:40:55.353011 Starting the controller
748 07:40:55.359477 USB XHCI 1.10
749 07:40:57.523840 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
750 07:40:57.524550 bl2_stage_init 0x01
751 07:40:57.525033 bl2_stage_init 0x81
752 07:40:57.528115 hw id: 0x0000 - pwm id 0x01
753 07:40:57.528658 bl2_stage_init 0xc1
754 07:40:57.529127 bl2_stage_init 0x02
755 07:40:57.529582
756 07:40:57.535374 L0:00000000
757 07:40:57.535921 L1:20000703
758 07:40:57.536634 L2:00008067
759 07:40:57.537140 L3:14000000
760 07:40:57.537962 B2:00402000
761 07:40:57.538436 B1:e0f83180
762 07:40:57.538882
763 07:40:57.539323 TE: 58159
764 07:40:57.539764
765 07:40:57.548201 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
766 07:40:57.548784
767 07:40:57.549254 Board ID = 1
768 07:40:57.549710 Set A53 clk to 24M
769 07:40:57.550155 Set A73 clk to 24M
770 07:40:57.553711 Set clk81 to 24M
771 07:40:57.554257 A53 clk: 1200 MHz
772 07:40:57.554717 A73 clk: 1200 MHz
773 07:40:57.557430 CLK81: 166.6M
774 07:40:57.557964 smccc: 00012ab5
775 07:40:57.562901 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
776 07:40:57.568281 board id: 1
777 07:40:57.573120 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
778 07:40:57.583645 fw parse done
779 07:40:57.589662 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
780 07:40:57.632215 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
781 07:40:57.643298 PIEI prepare done
782 07:40:57.643851 fastboot data load
783 07:40:57.644374 fastboot data verify
784 07:40:57.648878 verify result: 266
785 07:40:57.654461 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
786 07:40:57.655011 LPDDR4 probe
787 07:40:57.655471 ddr clk to 1584MHz
788 07:40:57.662356 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
789 07:40:57.699737
790 07:40:57.700345 dmc_version 0001
791 07:40:57.706409 Check phy result
792 07:40:57.712316 INFO : End of CA training
793 07:40:57.712870 INFO : End of initialization
794 07:40:57.717939 INFO : Training has run successfully!
795 07:40:57.718470 Check phy result
796 07:40:57.723477 INFO : End of initialization
797 07:40:57.724045 INFO : End of read enable training
798 07:40:57.729160 INFO : End of fine write leveling
799 07:40:57.734740 INFO : End of Write leveling coarse delay
800 07:40:57.735280 INFO : Training has run successfully!
801 07:40:57.735741 Check phy result
802 07:40:57.740297 INFO : End of initialization
803 07:40:57.740830 INFO : End of read dq deskew training
804 07:40:57.745932 INFO : End of MPR read delay center optimization
805 07:40:57.751452 INFO : End of write delay center optimization
806 07:40:57.757175 INFO : End of read delay center optimization
807 07:40:57.757715 INFO : End of max read latency training
808 07:40:57.762675 INFO : Training has run successfully!
809 07:40:57.763209 1D training succeed
810 07:40:57.771775 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
811 07:40:57.819335 Check phy result
812 07:40:57.819888 INFO : End of initialization
813 07:40:57.841132 INFO : End of 2D read delay Voltage center optimization
814 07:40:57.861352 INFO : End of 2D read delay Voltage center optimization
815 07:40:57.913352 INFO : End of 2D write delay Voltage center optimization
816 07:40:57.962740 INFO : End of 2D write delay Voltage center optimization
817 07:40:57.968305 INFO : Training has run successfully!
818 07:40:57.968832
819 07:40:57.969291 channel==0
820 07:40:57.973927 RxClkDly_Margin_A0==88 ps 9
821 07:40:57.974466 TxDqDly_Margin_A0==98 ps 10
822 07:40:57.979543 RxClkDly_Margin_A1==88 ps 9
823 07:40:57.980108 TxDqDly_Margin_A1==98 ps 10
824 07:40:57.980589 TrainedVREFDQ_A0==74
825 07:40:57.985225 TrainedVREFDQ_A1==76
826 07:40:57.985770 VrefDac_Margin_A0==25
827 07:40:57.986235 DeviceVref_Margin_A0==40
828 07:40:57.990691 VrefDac_Margin_A1==25
829 07:40:57.991227 DeviceVref_Margin_A1==38
830 07:40:57.991661
831 07:40:57.992137
832 07:40:57.996259 channel==1
833 07:40:57.996774 RxClkDly_Margin_A0==98 ps 10
834 07:40:57.997205 TxDqDly_Margin_A0==88 ps 9
835 07:40:58.001874 RxClkDly_Margin_A1==98 ps 10
836 07:40:58.002379 TxDqDly_Margin_A1==88 ps 9
837 07:40:58.007542 TrainedVREFDQ_A0==76
838 07:40:58.008082 TrainedVREFDQ_A1==77
839 07:40:58.008526 VrefDac_Margin_A0==22
840 07:40:58.013127 DeviceVref_Margin_A0==38
841 07:40:58.013632 VrefDac_Margin_A1==24
842 07:40:58.018674 DeviceVref_Margin_A1==37
843 07:40:58.019177
844 07:40:58.019613 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
845 07:40:58.020078
846 07:40:58.052265 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000018 00000018 00000019 00000018 00000019 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
847 07:40:58.052846 2D training succeed
848 07:40:58.057890 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
849 07:40:58.063511 auto size-- 65535DDR cs0 size: 2048MB
850 07:40:58.064044 DDR cs1 size: 2048MB
851 07:40:58.069154 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
852 07:40:58.069654 cs0 DataBus test pass
853 07:40:58.074677 cs1 DataBus test pass
854 07:40:58.075177 cs0 AddrBus test pass
855 07:40:58.075610 cs1 AddrBus test pass
856 07:40:58.076068
857 07:40:58.080298 100bdlr_step_size ps== 420
858 07:40:58.080813 result report
859 07:40:58.085866 boot times 0Enable ddr reg access
860 07:40:58.091239 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
861 07:40:58.104470 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
862 07:40:58.678259 0.0;M3 CHK:0;cm4_sp_mode 0
863 07:40:58.678929 MVN_1=0x00000000
864 07:40:58.683752 MVN_2=0x00000000
865 07:40:58.689517 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
866 07:40:58.690057 OPS=0x10
867 07:40:58.690523 ring efuse init
868 07:40:58.690968 chipver efuse init
869 07:40:58.697653 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
870 07:40:58.698244 [0.018960 Inits done]
871 07:40:58.705266 secure task start!
872 07:40:58.705805 high task start!
873 07:40:58.706273 low task start!
874 07:40:58.706726 run into bl31
875 07:40:58.711827 NOTICE: BL31: v1.3(release):4fc40b1
876 07:40:58.719633 NOTICE: BL31: Built : 15:58:17, May 22 2019
877 07:40:58.719941 NOTICE: BL31: G12A normal boot!
878 07:40:58.745259 NOTICE: BL31: BL33 decompress pass
879 07:40:58.750867 ERROR: Error initializing runtime service opteed_fast
880 07:40:59.983630
881 07:40:59.984358
882 07:40:59.992115 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
883 07:40:59.992673
884 07:40:59.993147 Model: Libre Computer AML-A311D-CC Alta
885 07:41:00.200389 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
886 07:41:00.223891 DRAM: 2 GiB (effective 3.8 GiB)
887 07:41:00.366961 Core: 408 devices, 31 uclasses, devicetree: separate
888 07:41:00.372833 WDT: Not starting watchdog@f0d0
889 07:41:00.405119 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
890 07:41:00.417735 Loading Environment from FAT... Card did not respond to voltage select! : -110
891 07:41:00.421747 ** Bad device specification mmc 0 **
892 07:41:00.432869 Card did not respond to voltage select! : -110
893 07:41:00.440500 ** Bad device specification mmc 0 **
894 07:41:00.440863 Couldn't find partition mmc 0
895 07:41:00.448752 Card did not respond to voltage select! : -110
896 07:41:00.454199 ** Bad device specification mmc 0 **
897 07:41:00.454504 Couldn't find partition mmc 0
898 07:41:00.459338 Error: could not access storage.
899 07:41:00.801799 Net: eth0: ethernet@ff3f0000
900 07:41:00.802457 starting USB...
901 07:41:01.053636 Bus usb@ff500000: Register 3000140 NbrPorts 3
902 07:41:01.054287 Starting the controller
903 07:41:01.060666 USB XHCI 1.10
904 07:41:02.922663 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
905 07:41:02.923333 bl2_stage_init 0x01
906 07:41:02.923817 bl2_stage_init 0x81
907 07:41:02.928241 hw id: 0x0000 - pwm id 0x01
908 07:41:02.928797 bl2_stage_init 0xc1
909 07:41:02.929268 bl2_stage_init 0x02
910 07:41:02.929724
911 07:41:02.933743 L0:00000000
912 07:41:02.934288 L1:20000703
913 07:41:02.934754 L2:00008067
914 07:41:02.935209 L3:14000000
915 07:41:02.939496 B2:00402000
916 07:41:02.940069 B1:e0f83180
917 07:41:02.940543
918 07:41:02.940999 TE: 58159
919 07:41:02.941457
920 07:41:02.944698 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
921 07:41:02.945261
922 07:41:02.945731 Board ID = 1
923 07:41:02.950329 Set A53 clk to 24M
924 07:41:02.950875 Set A73 clk to 24M
925 07:41:02.951342 Set clk81 to 24M
926 07:41:02.955897 A53 clk: 1200 MHz
927 07:41:02.956472 A73 clk: 1200 MHz
928 07:41:02.956931 CLK81: 166.6M
929 07:41:02.957378 smccc: 00012ab4
930 07:41:02.961578 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
931 07:41:02.967156 board id: 1
932 07:41:02.973072 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
933 07:41:02.983671 fw parse done
934 07:41:02.992191 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
935 07:41:03.032216 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
936 07:41:03.043090 PIEI prepare done
937 07:41:03.043620 fastboot data load
938 07:41:03.044108 fastboot data verify
939 07:41:03.048710 verify result: 266
940 07:41:03.054286 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
941 07:41:03.054821 LPDDR4 probe
942 07:41:03.055257 ddr clk to 1584MHz
943 07:41:03.062296 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
944 07:41:03.099580
945 07:41:03.100169 dmc_version 0001
946 07:41:03.106248 Check phy result
947 07:41:03.112097 INFO : End of CA training
948 07:41:03.112625 INFO : End of initialization
949 07:41:03.117766 INFO : Training has run successfully!
950 07:41:03.118327 Check phy result
951 07:41:03.123307 INFO : End of initialization
952 07:41:03.123861 INFO : End of read enable training
953 07:41:03.126630 INFO : End of fine write leveling
954 07:41:03.132199 INFO : End of Write leveling coarse delay
955 07:41:03.137735 INFO : Training has run successfully!
956 07:41:03.138283 Check phy result
957 07:41:03.138743 INFO : End of initialization
958 07:41:03.143337 INFO : End of read dq deskew training
959 07:41:03.146756 INFO : End of MPR read delay center optimization
960 07:41:03.152272 INFO : End of write delay center optimization
961 07:41:03.157897 INFO : End of read delay center optimization
962 07:41:03.158441 INFO : End of max read latency training
963 07:41:03.163480 INFO : Training has run successfully!
964 07:41:03.164050 1D training succeed
965 07:41:03.171755 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
966 07:41:03.219388 Check phy result
967 07:41:03.219973 INFO : End of initialization
968 07:41:03.241771 INFO : End of 2D read delay Voltage center optimization
969 07:41:03.261864 INFO : End of 2D read delay Voltage center optimization
970 07:41:03.313772 INFO : End of 2D write delay Voltage center optimization
971 07:41:03.363105 INFO : End of 2D write delay Voltage center optimization
972 07:41:03.368656 INFO : Training has run successfully!
973 07:41:03.369204
974 07:41:03.369665 channel==0
975 07:41:03.374306 RxClkDly_Margin_A0==88 ps 9
976 07:41:03.374846 TxDqDly_Margin_A0==98 ps 10
977 07:41:03.377523 RxClkDly_Margin_A1==98 ps 10
978 07:41:03.378062 TxDqDly_Margin_A1==98 ps 10
979 07:41:03.382996 TrainedVREFDQ_A0==74
980 07:41:03.383536 TrainedVREFDQ_A1==74
981 07:41:03.388673 VrefDac_Margin_A0==24
982 07:41:03.389213 DeviceVref_Margin_A0==40
983 07:41:03.389674 VrefDac_Margin_A1==24
984 07:41:03.394268 DeviceVref_Margin_A1==40
985 07:41:03.394799
986 07:41:03.395260
987 07:41:03.395707 channel==1
988 07:41:03.396191 RxClkDly_Margin_A0==98 ps 10
989 07:41:03.399767 TxDqDly_Margin_A0==98 ps 10
990 07:41:03.400337 RxClkDly_Margin_A1==88 ps 9
991 07:41:03.405399 TxDqDly_Margin_A1==88 ps 9
992 07:41:03.405957 TrainedVREFDQ_A0==77
993 07:41:03.406419 TrainedVREFDQ_A1==77
994 07:41:03.411053 VrefDac_Margin_A0==22
995 07:41:03.411586 DeviceVref_Margin_A0==37
996 07:41:03.416627 VrefDac_Margin_A1==24
997 07:41:03.417172 DeviceVref_Margin_A1==37
998 07:41:03.417635
999 07:41:03.422177 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
1000 07:41:03.422721
1001 07:41:03.450184 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000017 00000018 00000019 00000017 00000018 00000016 00000018 00000015 00000017 00000019 00000017 00000019 00000018 00000019 00000019 00000018 00000017 00000018 00000017 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 0000005f
1002 07:41:03.455887 2D training succeed
1003 07:41:03.461333 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
1004 07:41:03.461876 auto size-- 65535DDR cs0 size: 2048MB
1005 07:41:03.466954 DDR cs1 size: 2048MB
1006 07:41:03.467490 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
1007 07:41:03.472539 cs0 DataBus test pass
1008 07:41:03.473085 cs1 DataBus test pass
1009 07:41:03.473545 cs0 AddrBus test pass
1010 07:41:03.478128 cs1 AddrBus test pass
1011 07:41:03.478669
1012 07:41:03.479133 100bdlr_step_size ps== 420
1013 07:41:03.479592 result report
1014 07:41:03.483735 boot times 0Enable ddr reg access
1015 07:41:03.491515 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
1016 07:41:03.504942 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
1017 07:41:04.077074 0.0;M3 CHK:0;cm4_sp_mode 0
1018 07:41:04.077725 MVN_1=0x00000000
1019 07:41:04.082525 MVN_2=0x00000000
1020 07:41:04.088253 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
1021 07:41:04.088809 OPS=0x10
1022 07:41:04.089284 ring efuse init
1023 07:41:04.089736 chipver efuse init
1024 07:41:04.096425 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
1025 07:41:04.096985 [0.018960 Inits done]
1026 07:41:04.104107 secure task start!
1027 07:41:04.104651 high task start!
1028 07:41:04.105114 low task start!
1029 07:41:04.105559 run into bl31
1030 07:41:04.110722 NOTICE: BL31: v1.3(release):4fc40b1
1031 07:41:04.118543 NOTICE: BL31: Built : 15:58:17, May 22 2019
1032 07:41:04.119089 NOTICE: BL31: G12A normal boot!
1033 07:41:04.143974 NOTICE: BL31: BL33 decompress pass
1034 07:41:04.149562 ERROR: Error initializing runtime service opteed_fast
1035 07:41:05.382287
1036 07:41:05.382716
1037 07:41:05.390709 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
1038 07:41:05.391071
1039 07:41:05.391338 Model: Libre Computer AML-A311D-CC Alta
1040 07:41:05.599284 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
1041 07:41:05.622644 DRAM: 2 GiB (effective 3.8 GiB)
1042 07:41:05.765591 Core: 408 devices, 31 uclasses, devicetree: separate
1043 07:41:05.771469 WDT: Not starting watchdog@f0d0
1044 07:41:05.803767 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
1045 07:41:05.816207 Loading Environment from FAT... Card did not respond to voltage select! : -110
1046 07:41:05.821216 ** Bad device specification mmc 0 **
1047 07:41:05.831497 Card did not respond to voltage select! : -110
1048 07:41:05.839215 ** Bad device specification mmc 0 **
1049 07:41:05.839768 Couldn't find partition mmc 0
1050 07:41:05.847494 Card did not respond to voltage select! : -110
1051 07:41:05.852995 ** Bad device specification mmc 0 **
1052 07:41:05.853521 Couldn't find partition mmc 0
1053 07:41:05.857118 Error: could not access storage.
1054 07:41:06.200538 Net: eth0: ethernet@ff3f0000
1055 07:41:06.201191 starting USB...
1056 07:41:06.452292 Bus usb@ff500000: Register 3000140 NbrPorts 3
1057 07:41:06.452896 Starting the controller
1058 07:41:06.459301 USB XHCI 1.10
1059 07:41:08.013311 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
1060 07:41:08.021670 scanning usb for storage devices... 0 Storage Device(s) found
1062 07:41:08.073413 Hit any key to stop autoboot: 1
1063 07:41:08.074427 end: 2.4.2 bootloader-interrupt (duration 00:00:38) [common]
1064 07:41:08.075137 start: 2.4.3 bootloader-commands (timeout 00:04:22) [common]
1065 07:41:08.075653 Setting prompt string to ['=>']
1066 07:41:08.076231 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:22)
1067 07:41:08.089119 0
1068 07:41:08.090071 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1069 07:41:08.090603 Sending with 10 millisecond of delay
1071 07:41:09.225575 => setenv autoload no
1072 07:41:09.236427 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:21)
1073 07:41:09.241887 setenv autoload no
1074 07:41:09.242689 Sending with 10 millisecond of delay
1076 07:41:11.039785 => setenv initrd_high 0xffffffff
1077 07:41:11.050668 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:19)
1078 07:41:11.051594 setenv initrd_high 0xffffffff
1079 07:41:11.052402 Sending with 10 millisecond of delay
1081 07:41:12.668781 => setenv fdt_high 0xffffffff
1082 07:41:12.679617 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1083 07:41:12.680567 setenv fdt_high 0xffffffff
1084 07:41:12.681332 Sending with 10 millisecond of delay
1086 07:41:12.973256 => dhcp
1087 07:41:12.984062 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:17)
1088 07:41:12.984968 dhcp
1089 07:41:12.985451 Speed: 1000, full duplex
1090 07:41:12.985908 BOOTP broadcast 1
1091 07:41:13.177125 DHCP client bound to address 192.168.6.27 (192 ms)
1092 07:41:13.178023 Sending with 10 millisecond of delay
1094 07:41:14.855033 => setenv serverip 192.168.6.2
1095 07:41:14.865899 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:15)
1096 07:41:14.866844 setenv serverip 192.168.6.2
1097 07:41:14.867607 Sending with 10 millisecond of delay
1099 07:41:18.591031 => tftpboot 0x01080000 933335/tftp-deploy-ew_58eu0/kernel/uImage
1100 07:41:18.601860 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:12)
1101 07:41:18.602779 tftpboot 0x01080000 933335/tftp-deploy-ew_58eu0/kernel/uImage
1102 07:41:18.603253 Speed: 1000, full duplex
1103 07:41:18.603693 Using ethernet@ff3f0000 device
1104 07:41:18.604664 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1105 07:41:18.610179 Filename '933335/tftp-deploy-ew_58eu0/kernel/uImage'.
1106 07:41:18.613440 Load address: 0x1080000
1107 07:41:21.529613 Loading: *################################################## 44.1 MiB
1108 07:41:21.530291 15.1 MiB/s
1109 07:41:21.530765 done
1110 07:41:21.534245 Bytes transferred = 46260800 (2c1e240 hex)
1111 07:41:21.535059 Sending with 10 millisecond of delay
1113 07:41:26.222363 => tftpboot 0x08000000 933335/tftp-deploy-ew_58eu0/ramdisk/ramdisk.cpio.gz.uboot
1114 07:41:26.232889 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:04)
1115 07:41:26.233373 tftpboot 0x08000000 933335/tftp-deploy-ew_58eu0/ramdisk/ramdisk.cpio.gz.uboot
1116 07:41:26.233616 Speed: 1000, full duplex
1117 07:41:26.233830 Using ethernet@ff3f0000 device
1118 07:41:26.235509 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1119 07:41:26.244221 Filename '933335/tftp-deploy-ew_58eu0/ramdisk/ramdisk.cpio.gz.uboot'.
1120 07:41:26.244507 Load address: 0x8000000
1121 07:41:33.045360 Loading: *#################T ################################# 24.9 MiB
1122 07:41:33.046032 3.7 MiB/s
1123 07:41:33.046512 done
1124 07:41:33.049743 Bytes transferred = 26159732 (18f2a74 hex)
1125 07:41:33.050559 Sending with 10 millisecond of delay
1127 07:41:38.219726 => tftpboot 0x01070000 933335/tftp-deploy-ew_58eu0/dtb/meson-g12b-a311d-libretech-cc.dtb
1128 07:41:38.230572 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:03:52)
1129 07:41:38.231418 tftpboot 0x01070000 933335/tftp-deploy-ew_58eu0/dtb/meson-g12b-a311d-libretech-cc.dtb
1130 07:41:38.231905 Speed: 1000, full duplex
1131 07:41:38.232404 Using ethernet@ff3f0000 device
1132 07:41:38.235339 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1133 07:41:38.248539 Filename '933335/tftp-deploy-ew_58eu0/dtb/meson-g12b-a311d-libretech-cc.dtb'.
1134 07:41:38.249073 Load address: 0x1070000
1135 07:41:38.264893 Loading: *################################################## 53.4 KiB
1136 07:41:38.265388 2.9 MiB/s
1137 07:41:38.265847 done
1138 07:41:38.271299 Bytes transferred = 54703 (d5af hex)
1139 07:41:38.272086 Sending with 10 millisecond of delay
1141 07:41:45.909104 => setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
1142 07:41:45.919942 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:03:44)
1143 07:41:45.920833 setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
1144 07:41:45.921604 Sending with 10 millisecond of delay
1146 07:41:48.260417 => bootm 0x01080000 0x08000000 0x01070000
1147 07:41:48.271290 Setting prompt string to ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1148 07:41:48.271856 bootloader-commands: Wait for prompt ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:03:42)
1149 07:41:48.273012 bootm 0x01080000 0x08000000 0x01070000
1150 07:41:48.273503 ## Booting kernel from Legacy Image at 01080000 ...
1151 07:41:48.276569 Image Name:
1152 07:41:48.282126 Image Type: AArch64 Linux Kernel Image (uncompressed)
1153 07:41:48.282608 Data Size: 46260736 Bytes = 44.1 MiB
1154 07:41:48.284282 Load Address: 01080000
1155 07:41:48.290564 Entry Point: 01080000
1156 07:41:48.484803 Verifying Checksum ... OK
1157 07:41:48.485333 ## Loading init Ramdisk from Legacy Image at 08000000 ...
1158 07:41:48.490247 Image Name:
1159 07:41:48.495768 Image Type: AArch64 Linux RAMDisk Image (uncompressed)
1160 07:41:48.496288 Data Size: 26159668 Bytes = 24.9 MiB
1161 07:41:48.501230 Load Address: 00000000
1162 07:41:48.501699 Entry Point: 00000000
1163 07:41:48.614946 Verifying Checksum ... OK
1164 07:41:48.615433 ## Flattened Device Tree blob at 01070000
1165 07:41:48.620338 Booting using the fdt blob at 0x1070000
1166 07:41:48.620814 Working FDT set to 1070000
1167 07:41:48.624902 Loading Kernel Image
1168 07:41:48.789976 Loading Ramdisk to 7e70d000, end 7ffffa34 ... OK
1169 07:41:48.798230 Loading Device Tree to 000000007e6fc000, end 000000007e70c5ae ... OK
1170 07:41:48.798699 Working FDT set to 7e6fc000
1171 07:41:48.799152
1172 07:41:48.800117 end: 2.4.3 bootloader-commands (duration 00:00:41) [common]
1173 07:41:48.800744 start: 2.4.4 auto-login-action (timeout 00:03:41) [common]
1174 07:41:48.801246 Setting prompt string to ['Linux version [0-9]']
1175 07:41:48.801745 Setting prompt string to ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1176 07:41:48.802260 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:05:00)
1177 07:41:48.803345 Starting kernel ...
1178 07:41:48.803818
1180 07:45:29.801449 end: 2.4.4 auto-login-action (duration 00:03:41) [common]
1183 07:45:29.802444 end: 2.4 uboot-commands (duration 00:05:00) [common]
1185 07:45:29.803134 uboot-action failed: 1 of 1 attempts. 'auto-login-action timed out after 221 seconds'
1187 07:45:29.803700 end: 2 uboot-action (duration 00:05:00) [common]
1189 07:45:29.804574 Cleaning after the job
1190 07:45:29.804883 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/933335/tftp-deploy-ew_58eu0/ramdisk
1191 07:45:29.812299 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/933335/tftp-deploy-ew_58eu0/kernel
1192 07:45:29.839174 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/933335/tftp-deploy-ew_58eu0/dtb
1193 07:45:29.840016 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/933335/tftp-deploy-ew_58eu0/modules
1194 07:45:29.859873 start: 4.1 power-off (timeout 00:00:30) [common]
1195 07:45:29.860553 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1196 07:45:29.893922 >> OK - accepted request
1197 07:45:29.895960 Returned 0 in 0 seconds
1198 07:45:29.996731 end: 4.1 power-off (duration 00:00:00) [common]
1200 07:45:29.997709 start: 4.2 read-feedback (timeout 00:10:00) [common]
1201 07:45:29.998350 Listened to connection for namespace 'common' for up to 1s
1202 07:45:30.998731 Finalising connection for namespace 'common'
1203 07:45:30.999222 Disconnecting from shell: Finalise
1204 07:45:30.999558
1205 07:45:31.100251 end: 4.2 read-feedback (duration 00:00:01) [common]
1206 07:45:31.100755 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/933335
1207 07:45:31.435850 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/933335
1208 07:45:31.437046 JobError: Your job cannot terminate cleanly.