Boot log: meson-sm1-s905d3-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 07:43:26.376707 lava-dispatcher, installed at version: 2024.01
2 07:43:26.377514 start: 0 validate
3 07:43:26.377990 Start time: 2024-11-04 07:43:26.377959+00:00 (UTC)
4 07:43:26.378551 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 07:43:26.379099 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230703.0%2Farm64%2Frootfs.cpio.gz exists
6 07:43:26.418047 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 07:43:26.418646 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241104%2Farm64%2Fdefconfig%2BCONFIG_ARM64_64K_PAGES%3Dy%2Fgcc-12%2Fkernel%2FImage exists
8 07:43:26.454048 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 07:43:26.454707 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241104%2Farm64%2Fdefconfig%2BCONFIG_ARM64_64K_PAGES%3Dy%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-sm1-s905d3-libretech-cc.dtb exists
10 07:43:27.521488 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 07:43:27.521985 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241104%2Farm64%2Fdefconfig%2BCONFIG_ARM64_64K_PAGES%3Dy%2Fgcc-12%2Fmodules.tar.xz exists
12 07:43:27.561780 validate duration: 1.18
14 07:43:27.563069 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 07:43:27.563675 start: 1.1 download-retry (timeout 00:10:00) [common]
16 07:43:27.564287 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 07:43:27.565272 Not decompressing ramdisk as can be used compressed.
18 07:43:27.565996 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230703.0/arm64/rootfs.cpio.gz
19 07:43:27.566490 saving as /var/lib/lava/dispatcher/tmp/933357/tftp-deploy-f5hzme5r/ramdisk/rootfs.cpio.gz
20 07:43:27.566996 total size: 8181887 (7 MB)
21 07:43:27.609273 progress 0 % (0 MB)
22 07:43:27.623831 progress 5 % (0 MB)
23 07:43:27.636517 progress 10 % (0 MB)
24 07:43:27.647108 progress 15 % (1 MB)
25 07:43:27.653249 progress 20 % (1 MB)
26 07:43:27.659831 progress 25 % (1 MB)
27 07:43:27.666096 progress 30 % (2 MB)
28 07:43:27.672772 progress 35 % (2 MB)
29 07:43:27.678802 progress 40 % (3 MB)
30 07:43:27.685384 progress 45 % (3 MB)
31 07:43:27.691385 progress 50 % (3 MB)
32 07:43:27.697923 progress 55 % (4 MB)
33 07:43:27.703891 progress 60 % (4 MB)
34 07:43:27.710405 progress 65 % (5 MB)
35 07:43:27.716474 progress 70 % (5 MB)
36 07:43:27.722846 progress 75 % (5 MB)
37 07:43:27.728854 progress 80 % (6 MB)
38 07:43:27.735400 progress 85 % (6 MB)
39 07:43:27.741106 progress 90 % (7 MB)
40 07:43:27.747091 progress 95 % (7 MB)
41 07:43:27.752815 progress 100 % (7 MB)
42 07:43:27.753604 7 MB downloaded in 0.19 s (41.82 MB/s)
43 07:43:27.754285 end: 1.1.1 http-download (duration 00:00:00) [common]
45 07:43:27.755391 end: 1.1 download-retry (duration 00:00:00) [common]
46 07:43:27.755770 start: 1.2 download-retry (timeout 00:10:00) [common]
47 07:43:27.756155 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 07:43:27.756757 downloading http://storage.kernelci.org/next/master/next-20241104/arm64/defconfig+CONFIG_ARM64_64K_PAGES=y/gcc-12/kernel/Image
49 07:43:27.757063 saving as /var/lib/lava/dispatcher/tmp/933357/tftp-deploy-f5hzme5r/kernel/Image
50 07:43:27.757326 total size: 47653376 (45 MB)
51 07:43:27.757596 No compression specified
52 07:43:27.792788 progress 0 % (0 MB)
53 07:43:27.821197 progress 5 % (2 MB)
54 07:43:27.849512 progress 10 % (4 MB)
55 07:43:27.877864 progress 15 % (6 MB)
56 07:43:27.905758 progress 20 % (9 MB)
57 07:43:27.933910 progress 25 % (11 MB)
58 07:43:27.962152 progress 30 % (13 MB)
59 07:43:27.990346 progress 35 % (15 MB)
60 07:43:28.018506 progress 40 % (18 MB)
61 07:43:28.046800 progress 45 % (20 MB)
62 07:43:28.075110 progress 50 % (22 MB)
63 07:43:28.102851 progress 55 % (25 MB)
64 07:43:28.131106 progress 60 % (27 MB)
65 07:43:28.159153 progress 65 % (29 MB)
66 07:43:28.187358 progress 70 % (31 MB)
67 07:43:28.215929 progress 75 % (34 MB)
68 07:43:28.244240 progress 80 % (36 MB)
69 07:43:28.272759 progress 85 % (38 MB)
70 07:43:28.300778 progress 90 % (40 MB)
71 07:43:28.329182 progress 95 % (43 MB)
72 07:43:28.356664 progress 100 % (45 MB)
73 07:43:28.357253 45 MB downloaded in 0.60 s (75.75 MB/s)
74 07:43:28.357744 end: 1.2.1 http-download (duration 00:00:01) [common]
76 07:43:28.358559 end: 1.2 download-retry (duration 00:00:01) [common]
77 07:43:28.358836 start: 1.3 download-retry (timeout 00:09:59) [common]
78 07:43:28.359098 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 07:43:28.359566 downloading http://storage.kernelci.org/next/master/next-20241104/arm64/defconfig+CONFIG_ARM64_64K_PAGES=y/gcc-12/dtbs/amlogic/meson-sm1-s905d3-libretech-cc.dtb
80 07:43:28.359843 saving as /var/lib/lava/dispatcher/tmp/933357/tftp-deploy-f5hzme5r/dtb/meson-sm1-s905d3-libretech-cc.dtb
81 07:43:28.360072 total size: 53209 (0 MB)
82 07:43:28.360283 No compression specified
83 07:43:28.396268 progress 61 % (0 MB)
84 07:43:28.397123 progress 100 % (0 MB)
85 07:43:28.397665 0 MB downloaded in 0.04 s (1.35 MB/s)
86 07:43:28.398124 end: 1.3.1 http-download (duration 00:00:00) [common]
88 07:43:28.398939 end: 1.3 download-retry (duration 00:00:00) [common]
89 07:43:28.399203 start: 1.4 download-retry (timeout 00:09:59) [common]
90 07:43:28.399467 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 07:43:28.400012 downloading http://storage.kernelci.org/next/master/next-20241104/arm64/defconfig+CONFIG_ARM64_64K_PAGES=y/gcc-12/modules.tar.xz
92 07:43:28.400280 saving as /var/lib/lava/dispatcher/tmp/933357/tftp-deploy-f5hzme5r/modules/modules.tar
93 07:43:28.400485 total size: 11668280 (11 MB)
94 07:43:28.400696 Using unxz to decompress xz
95 07:43:28.439374 progress 0 % (0 MB)
96 07:43:28.505004 progress 5 % (0 MB)
97 07:43:28.579174 progress 10 % (1 MB)
98 07:43:28.674911 progress 15 % (1 MB)
99 07:43:28.771811 progress 20 % (2 MB)
100 07:43:28.850994 progress 25 % (2 MB)
101 07:43:28.922164 progress 30 % (3 MB)
102 07:43:29.000598 progress 35 % (3 MB)
103 07:43:29.078201 progress 40 % (4 MB)
104 07:43:29.153380 progress 45 % (5 MB)
105 07:43:29.237736 progress 50 % (5 MB)
106 07:43:29.315448 progress 55 % (6 MB)
107 07:43:29.400961 progress 60 % (6 MB)
108 07:43:29.482540 progress 65 % (7 MB)
109 07:43:29.562966 progress 70 % (7 MB)
110 07:43:29.644890 progress 75 % (8 MB)
111 07:43:29.722777 progress 80 % (8 MB)
112 07:43:29.802631 progress 85 % (9 MB)
113 07:43:29.885122 progress 90 % (10 MB)
114 07:43:29.962050 progress 95 % (10 MB)
115 07:43:30.038807 progress 100 % (11 MB)
116 07:43:30.049105 11 MB downloaded in 1.65 s (6.75 MB/s)
117 07:43:30.049671 end: 1.4.1 http-download (duration 00:00:02) [common]
119 07:43:30.050504 end: 1.4 download-retry (duration 00:00:02) [common]
120 07:43:30.050775 start: 1.5 prepare-tftp-overlay (timeout 00:09:58) [common]
121 07:43:30.051043 start: 1.5.1 extract-nfsrootfs (timeout 00:09:58) [common]
122 07:43:30.051291 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 07:43:30.051544 start: 1.5.2 lava-overlay (timeout 00:09:58) [common]
124 07:43:30.052377 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/933357/lava-overlay-kd6jsyzk
125 07:43:30.053313 makedir: /var/lib/lava/dispatcher/tmp/933357/lava-overlay-kd6jsyzk/lava-933357/bin
126 07:43:30.053952 makedir: /var/lib/lava/dispatcher/tmp/933357/lava-overlay-kd6jsyzk/lava-933357/tests
127 07:43:30.054564 makedir: /var/lib/lava/dispatcher/tmp/933357/lava-overlay-kd6jsyzk/lava-933357/results
128 07:43:30.055179 Creating /var/lib/lava/dispatcher/tmp/933357/lava-overlay-kd6jsyzk/lava-933357/bin/lava-add-keys
129 07:43:30.056164 Creating /var/lib/lava/dispatcher/tmp/933357/lava-overlay-kd6jsyzk/lava-933357/bin/lava-add-sources
130 07:43:30.057093 Creating /var/lib/lava/dispatcher/tmp/933357/lava-overlay-kd6jsyzk/lava-933357/bin/lava-background-process-start
131 07:43:30.058021 Creating /var/lib/lava/dispatcher/tmp/933357/lava-overlay-kd6jsyzk/lava-933357/bin/lava-background-process-stop
132 07:43:30.058985 Creating /var/lib/lava/dispatcher/tmp/933357/lava-overlay-kd6jsyzk/lava-933357/bin/lava-common-functions
133 07:43:30.059906 Creating /var/lib/lava/dispatcher/tmp/933357/lava-overlay-kd6jsyzk/lava-933357/bin/lava-echo-ipv4
134 07:43:30.060839 Creating /var/lib/lava/dispatcher/tmp/933357/lava-overlay-kd6jsyzk/lava-933357/bin/lava-install-packages
135 07:43:30.061753 Creating /var/lib/lava/dispatcher/tmp/933357/lava-overlay-kd6jsyzk/lava-933357/bin/lava-installed-packages
136 07:43:30.062626 Creating /var/lib/lava/dispatcher/tmp/933357/lava-overlay-kd6jsyzk/lava-933357/bin/lava-os-build
137 07:43:30.063498 Creating /var/lib/lava/dispatcher/tmp/933357/lava-overlay-kd6jsyzk/lava-933357/bin/lava-probe-channel
138 07:43:30.064411 Creating /var/lib/lava/dispatcher/tmp/933357/lava-overlay-kd6jsyzk/lava-933357/bin/lava-probe-ip
139 07:43:30.065304 Creating /var/lib/lava/dispatcher/tmp/933357/lava-overlay-kd6jsyzk/lava-933357/bin/lava-target-ip
140 07:43:30.066180 Creating /var/lib/lava/dispatcher/tmp/933357/lava-overlay-kd6jsyzk/lava-933357/bin/lava-target-mac
141 07:43:30.067053 Creating /var/lib/lava/dispatcher/tmp/933357/lava-overlay-kd6jsyzk/lava-933357/bin/lava-target-storage
142 07:43:30.067945 Creating /var/lib/lava/dispatcher/tmp/933357/lava-overlay-kd6jsyzk/lava-933357/bin/lava-test-case
143 07:43:30.068867 Creating /var/lib/lava/dispatcher/tmp/933357/lava-overlay-kd6jsyzk/lava-933357/bin/lava-test-event
144 07:43:30.069746 Creating /var/lib/lava/dispatcher/tmp/933357/lava-overlay-kd6jsyzk/lava-933357/bin/lava-test-feedback
145 07:43:30.070621 Creating /var/lib/lava/dispatcher/tmp/933357/lava-overlay-kd6jsyzk/lava-933357/bin/lava-test-raise
146 07:43:30.071493 Creating /var/lib/lava/dispatcher/tmp/933357/lava-overlay-kd6jsyzk/lava-933357/bin/lava-test-reference
147 07:43:30.072408 Creating /var/lib/lava/dispatcher/tmp/933357/lava-overlay-kd6jsyzk/lava-933357/bin/lava-test-runner
148 07:43:30.073307 Creating /var/lib/lava/dispatcher/tmp/933357/lava-overlay-kd6jsyzk/lava-933357/bin/lava-test-set
149 07:43:30.074193 Creating /var/lib/lava/dispatcher/tmp/933357/lava-overlay-kd6jsyzk/lava-933357/bin/lava-test-shell
150 07:43:30.075093 Updating /var/lib/lava/dispatcher/tmp/933357/lava-overlay-kd6jsyzk/lava-933357/bin/lava-install-packages (oe)
151 07:43:30.076105 Updating /var/lib/lava/dispatcher/tmp/933357/lava-overlay-kd6jsyzk/lava-933357/bin/lava-installed-packages (oe)
152 07:43:30.076951 Creating /var/lib/lava/dispatcher/tmp/933357/lava-overlay-kd6jsyzk/lava-933357/environment
153 07:43:30.077704 LAVA metadata
154 07:43:30.078202 - LAVA_JOB_ID=933357
155 07:43:30.078628 - LAVA_DISPATCHER_IP=192.168.6.2
156 07:43:30.079283 start: 1.5.2.1 ssh-authorize (timeout 00:09:57) [common]
157 07:43:30.081102 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 07:43:30.081722 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:57) [common]
159 07:43:30.082139 skipped lava-vland-overlay
160 07:43:30.082626 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 07:43:30.083130 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:57) [common]
162 07:43:30.083552 skipped lava-multinode-overlay
163 07:43:30.084071 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 07:43:30.084586 start: 1.5.2.4 test-definition (timeout 00:09:57) [common]
165 07:43:30.085066 Loading test definitions
166 07:43:30.085612 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:57) [common]
167 07:43:30.086056 Using /lava-933357 at stage 0
168 07:43:30.088204 uuid=933357_1.5.2.4.1 testdef=None
169 07:43:30.088557 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 07:43:30.088836 start: 1.5.2.4.2 test-overlay (timeout 00:09:57) [common]
171 07:43:30.090699 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 07:43:30.091530 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:57) [common]
174 07:43:30.093849 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 07:43:30.094751 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:57) [common]
177 07:43:30.097006 runner path: /var/lib/lava/dispatcher/tmp/933357/lava-overlay-kd6jsyzk/lava-933357/0/tests/0_dmesg test_uuid 933357_1.5.2.4.1
178 07:43:30.097607 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 07:43:30.098410 Creating lava-test-runner.conf files
181 07:43:30.098617 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/933357/lava-overlay-kd6jsyzk/lava-933357/0 for stage 0
182 07:43:30.098954 - 0_dmesg
183 07:43:30.099326 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 07:43:30.099622 start: 1.5.2.5 compress-overlay (timeout 00:09:57) [common]
185 07:43:30.123370 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 07:43:30.123812 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:57) [common]
187 07:43:30.124116 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 07:43:30.124401 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 07:43:30.124674 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:57) [common]
190 07:43:31.023816 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
191 07:43:31.024325 start: 1.5.4 extract-modules (timeout 00:09:57) [common]
192 07:43:31.024581 extracting modules file /var/lib/lava/dispatcher/tmp/933357/tftp-deploy-f5hzme5r/modules/modules.tar to /var/lib/lava/dispatcher/tmp/933357/extract-overlay-ramdisk-bw_l89p4/ramdisk
193 07:43:32.348390 end: 1.5.4 extract-modules (duration 00:00:01) [common]
194 07:43:32.348879 start: 1.5.5 apply-overlay-tftp (timeout 00:09:55) [common]
195 07:43:32.349155 [common] Applying overlay /var/lib/lava/dispatcher/tmp/933357/compress-overlay-mpjvtnce/overlay-1.5.2.5.tar.gz to ramdisk
196 07:43:32.349367 [common] Applying overlay /var/lib/lava/dispatcher/tmp/933357/compress-overlay-mpjvtnce/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/933357/extract-overlay-ramdisk-bw_l89p4/ramdisk
197 07:43:32.379419 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 07:43:32.379845 start: 1.5.6 prepare-kernel (timeout 00:09:55) [common]
199 07:43:32.380143 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:55) [common]
200 07:43:32.380373 Converting downloaded kernel to a uImage
201 07:43:32.380677 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/933357/tftp-deploy-f5hzme5r/kernel/Image /var/lib/lava/dispatcher/tmp/933357/tftp-deploy-f5hzme5r/kernel/uImage
202 07:43:32.849566 output: Image Name:
203 07:43:32.849947 output: Created: Mon Nov 4 07:43:32 2024
204 07:43:32.850151 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 07:43:32.850352 output: Data Size: 47653376 Bytes = 46536.50 KiB = 45.45 MiB
206 07:43:32.850551 output: Load Address: 01080000
207 07:43:32.850746 output: Entry Point: 01080000
208 07:43:32.850939 output:
209 07:43:32.851265 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
210 07:43:32.851526 end: 1.5.6 prepare-kernel (duration 00:00:00) [common]
211 07:43:32.851789 start: 1.5.7 configure-preseed-file (timeout 00:09:55) [common]
212 07:43:32.852073 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 07:43:32.852340 start: 1.5.8 compress-ramdisk (timeout 00:09:55) [common]
214 07:43:32.852592 Building ramdisk /var/lib/lava/dispatcher/tmp/933357/extract-overlay-ramdisk-bw_l89p4/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/933357/extract-overlay-ramdisk-bw_l89p4/ramdisk
215 07:43:35.233371 >> 182823 blocks
216 07:43:43.657391 Adding RAMdisk u-boot header.
217 07:43:43.658015 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/933357/extract-overlay-ramdisk-bw_l89p4/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/933357/extract-overlay-ramdisk-bw_l89p4/ramdisk.cpio.gz.uboot
218 07:43:43.972365 output: Image Name:
219 07:43:43.972741 output: Created: Mon Nov 4 07:43:43 2024
220 07:43:43.972947 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 07:43:43.973148 output: Data Size: 26152085 Bytes = 25539.15 KiB = 24.94 MiB
222 07:43:43.973349 output: Load Address: 00000000
223 07:43:43.973544 output: Entry Point: 00000000
224 07:43:43.973738 output:
225 07:43:43.974470 rename /var/lib/lava/dispatcher/tmp/933357/extract-overlay-ramdisk-bw_l89p4/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/933357/tftp-deploy-f5hzme5r/ramdisk/ramdisk.cpio.gz.uboot
226 07:43:43.974888 end: 1.5.8 compress-ramdisk (duration 00:00:11) [common]
227 07:43:43.975169 end: 1.5 prepare-tftp-overlay (duration 00:00:14) [common]
228 07:43:43.975438 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:44) [common]
229 07:43:43.975678 No LXC device requested
230 07:43:43.975928 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 07:43:43.976468 start: 1.7 deploy-device-env (timeout 00:09:44) [common]
232 07:43:43.977010 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 07:43:43.977460 Checking files for TFTP limit of 4294967296 bytes.
234 07:43:43.980396 end: 1 tftp-deploy (duration 00:00:16) [common]
235 07:43:43.981022 start: 2 uboot-action (timeout 00:05:00) [common]
236 07:43:43.981596 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 07:43:43.982141 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 07:43:43.982689 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 07:43:43.983263 Using kernel file from prepare-kernel: 933357/tftp-deploy-f5hzme5r/kernel/uImage
240 07:43:43.983942 substitutions:
241 07:43:43.984430 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 07:43:43.984875 - {DTB_ADDR}: 0x01070000
243 07:43:43.985307 - {DTB}: 933357/tftp-deploy-f5hzme5r/dtb/meson-sm1-s905d3-libretech-cc.dtb
244 07:43:43.985740 - {INITRD}: 933357/tftp-deploy-f5hzme5r/ramdisk/ramdisk.cpio.gz.uboot
245 07:43:43.986172 - {KERNEL_ADDR}: 0x01080000
246 07:43:43.986600 - {KERNEL}: 933357/tftp-deploy-f5hzme5r/kernel/uImage
247 07:43:43.987031 - {LAVA_MAC}: None
248 07:43:43.987496 - {PRESEED_CONFIG}: None
249 07:43:43.987927 - {PRESEED_LOCAL}: None
250 07:43:43.988382 - {RAMDISK_ADDR}: 0x08000000
251 07:43:43.988808 - {RAMDISK}: 933357/tftp-deploy-f5hzme5r/ramdisk/ramdisk.cpio.gz.uboot
252 07:43:43.989269 - {ROOT_PART}: None
253 07:43:43.989708 - {ROOT}: None
254 07:43:43.990134 - {SERVER_IP}: 192.168.6.2
255 07:43:43.990563 - {TEE_ADDR}: 0x83000000
256 07:43:43.990989 - {TEE}: None
257 07:43:43.991415 Parsed boot commands:
258 07:43:43.991829 - setenv autoload no
259 07:43:43.992292 - setenv initrd_high 0xffffffff
260 07:43:43.992722 - setenv fdt_high 0xffffffff
261 07:43:43.993146 - dhcp
262 07:43:43.993572 - setenv serverip 192.168.6.2
263 07:43:43.994000 - tftpboot 0x01080000 933357/tftp-deploy-f5hzme5r/kernel/uImage
264 07:43:43.994428 - tftpboot 0x08000000 933357/tftp-deploy-f5hzme5r/ramdisk/ramdisk.cpio.gz.uboot
265 07:43:43.994853 - tftpboot 0x01070000 933357/tftp-deploy-f5hzme5r/dtb/meson-sm1-s905d3-libretech-cc.dtb
266 07:43:43.995275 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 07:43:43.995702 - bootm 0x01080000 0x08000000 0x01070000
268 07:43:43.996264 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 07:43:43.997879 start: 2.3 connect-device (timeout 00:05:00) [common]
271 07:43:43.998360 [common] connect-device Connecting to device using 'telnet conserv1 3008'
272 07:43:44.013449 Setting prompt string to ['lava-test: # ']
273 07:43:44.015021 end: 2.3 connect-device (duration 00:00:00) [common]
274 07:43:44.015665 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 07:43:44.016305 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 07:43:44.016866 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 07:43:44.018108 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=solitude-01'
278 07:43:44.055109 >> OK - accepted request
279 07:43:44.057177 Returned 0 in 0 seconds
280 07:43:44.158311 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
282 07:43:44.160023 end: 2.4.1 reset-device (duration 00:00:00) [common]
283 07:43:44.160654 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
284 07:43:44.161209 Setting prompt string to ['Hit any key to stop autoboot']
285 07:43:44.161702 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 07:43:44.163417 Trying 192.168.56.21...
287 07:43:44.163942 Connected to conserv1.
288 07:43:44.164439 Escape character is '^]'.
289 07:43:44.164904
290 07:43:44.165370 ser2net port telnet,3008 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.3.3:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
291 07:43:44.165833
292 07:43:52.329592 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
293 07:43:52.330278 bl2_stage_init 0x01
294 07:43:52.330743 bl2_stage_init 0x81
295 07:43:52.335135 hw id: 0x0000 - pwm id 0x01
296 07:43:52.335682 bl2_stage_init 0xc1
297 07:43:52.339346 bl2_stage_init 0x02
298 07:43:52.339843
299 07:43:52.340344 L0:00000000
300 07:43:52.340784 L1:00000703
301 07:43:52.341212 L2:00008067
302 07:43:52.344907 L3:15000000
303 07:43:52.345377 S1:00000000
304 07:43:52.345813 B2:20282000
305 07:43:52.346244 B1:a0f83180
306 07:43:52.346667
307 07:43:52.347093 TE: 72152
308 07:43:52.350531
309 07:43:52.356159 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
310 07:43:52.356663
311 07:43:52.357100 Board ID = 1
312 07:43:52.357533 Set cpu clk to 24M
313 07:43:52.359789 Set clk81 to 24M
314 07:43:52.360288 Use GP1_pll as DSU clk.
315 07:43:52.365412 DSU clk: 1200 Mhz
316 07:43:52.365893 CPU clk: 1200 MHz
317 07:43:52.366331 Set clk81 to 166.6M
318 07:43:52.370812 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
319 07:43:52.376620 board id: 1
320 07:43:52.380464 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
321 07:43:52.392303 fw parse done
322 07:43:52.398075 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
323 07:43:52.440662 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
324 07:43:52.451528 PIEI prepare done
325 07:43:52.452097 fastboot data load
326 07:43:52.452550 fastboot data verify
327 07:43:52.457100 verify result: 266
328 07:43:52.462687 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
329 07:43:52.463190 LPDDR4 probe
330 07:43:52.463627 ddr clk to 1584MHz
331 07:43:52.470660 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
332 07:43:52.507971
333 07:43:52.508593 dmc_version 0001
334 07:43:52.514595 Check phy result
335 07:43:52.520454 INFO : End of CA training
336 07:43:52.520925 INFO : End of initialization
337 07:43:52.526105 INFO : Training has run successfully!
338 07:43:52.526565 Check phy result
339 07:43:52.531675 INFO : End of initialization
340 07:43:52.532161 INFO : End of read enable training
341 07:43:52.534998 INFO : End of fine write leveling
342 07:43:52.540552 INFO : End of Write leveling coarse delay
343 07:43:52.546143 INFO : Training has run successfully!
344 07:43:52.546603 Check phy result
345 07:43:52.547040 INFO : End of initialization
346 07:43:52.551747 INFO : End of read dq deskew training
347 07:43:52.557398 INFO : End of MPR read delay center optimization
348 07:43:52.557911 INFO : End of write delay center optimization
349 07:43:52.562990 INFO : End of read delay center optimization
350 07:43:52.568548 INFO : End of max read latency training
351 07:43:52.569014 INFO : Training has run successfully!
352 07:43:52.574155 1D training succeed
353 07:43:52.580201 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
354 07:43:52.627702 Check phy result
355 07:43:52.628304 INFO : End of initialization
356 07:43:52.650068 INFO : End of 2D read delay Voltage center optimization
357 07:43:52.669227 INFO : End of 2D read delay Voltage center optimization
358 07:43:52.721042 INFO : End of 2D write delay Voltage center optimization
359 07:43:52.770225 INFO : End of 2D write delay Voltage center optimization
360 07:43:52.775757 INFO : Training has run successfully!
361 07:43:52.776080
362 07:43:52.776310 channel==0
363 07:43:52.781370 RxClkDly_Margin_A0==88 ps 9
364 07:43:52.781655 TxDqDly_Margin_A0==98 ps 10
365 07:43:52.787007 RxClkDly_Margin_A1==88 ps 9
366 07:43:52.787312 TxDqDly_Margin_A1==98 ps 10
367 07:43:52.787538 TrainedVREFDQ_A0==74
368 07:43:52.792559 TrainedVREFDQ_A1==74
369 07:43:52.792867 VrefDac_Margin_A0==23
370 07:43:52.793091 DeviceVref_Margin_A0==40
371 07:43:52.798158 VrefDac_Margin_A1==22
372 07:43:52.798445 DeviceVref_Margin_A1==40
373 07:43:52.798670
374 07:43:52.798898
375 07:43:52.803744 channel==1
376 07:43:52.804037 RxClkDly_Margin_A0==88 ps 9
377 07:43:52.804267 TxDqDly_Margin_A0==98 ps 10
378 07:43:52.809334 RxClkDly_Margin_A1==78 ps 8
379 07:43:52.809612 TxDqDly_Margin_A1==88 ps 9
380 07:43:52.815009 TrainedVREFDQ_A0==78
381 07:43:52.815297 TrainedVREFDQ_A1==75
382 07:43:52.815524 VrefDac_Margin_A0==22
383 07:43:52.820552 DeviceVref_Margin_A0==36
384 07:43:52.820837 VrefDac_Margin_A1==22
385 07:43:52.826142 DeviceVref_Margin_A1==38
386 07:43:52.826412
387 07:43:52.826632 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
388 07:43:52.826844
389 07:43:52.859774 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000018 00000017 00000018 00000018 00000017 00000019 00000015 00000018 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001c 00000017 00000016 00000017 dram_vref_reg_value 0x 00000061
390 07:43:52.860191 2D training succeed
391 07:43:52.865362 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
392 07:43:52.871013 auto size-- 65535DDR cs0 size: 2048MB
393 07:43:52.871300 DDR cs1 size: 2048MB
394 07:43:52.876564 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
395 07:43:52.876844 cs0 DataBus test pass
396 07:43:52.882162 cs1 DataBus test pass
397 07:43:52.882463 cs0 AddrBus test pass
398 07:43:52.882689 cs1 AddrBus test pass
399 07:43:52.882899
400 07:43:52.887743 100bdlr_step_size ps== 478
401 07:43:52.888061 result report
402 07:43:52.893396 boot times 0Enable ddr reg access
403 07:43:52.898632 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
404 07:43:52.912473 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
405 07:43:53.567434 bl2z: ptr: 05129330, size: 00001e40
406 07:43:53.572932 0.0;M3 CHK:0;cm4_sp_mode 0
407 07:43:53.573260 MVN_1=0x00000000
408 07:43:53.573494 MVN_2=0x00000000
409 07:43:53.584435 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
410 07:43:53.584772 OPS=0x04
411 07:43:53.585003 ring efuse init
412 07:43:53.590041 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
413 07:43:53.590353 [0.017318 Inits done]
414 07:43:53.590584 secure task start!
415 07:43:53.597606 high task start!
416 07:43:53.598045 low task start!
417 07:43:53.598407 run into bl31
418 07:43:53.606223 NOTICE: BL31: v1.3(release):4fc40b1
419 07:43:53.614030 NOTICE: BL31: Built : 15:57:33, May 22 2019
420 07:43:53.614344 NOTICE: BL31: G12A normal boot!
421 07:43:53.629699 NOTICE: BL31: BL33 decompress pass
422 07:43:53.635420 ERROR: Error initializing runtime service opteed_fast
423 07:43:56.376084 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0; SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
424 07:43:56.376744 bl2_stage_init 0x01
425 07:43:56.377226 bl2_stage_init 0x81
426 07:43:56.381633 hw id: 0x0000 - pwm id 0x01
427 07:43:56.382165 bl2_stage_init 0xc1
428 07:43:56.386543 bl2_stage_init 0x02
429 07:43:56.387099
430 07:43:56.387547 L0:00000000
431 07:43:56.387976 L1:00000703
432 07:43:56.388454 L2:00008067
433 07:43:56.392132 L3:15000000
434 07:43:56.392605 S1:00000000
435 07:43:56.393038 B2:20282000
436 07:43:56.393463 B1:a0f83180
437 07:43:56.393883
438 07:43:56.394308 TE: 67628
439 07:43:56.394731
440 07:43:56.403300 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
441 07:43:56.403772
442 07:43:56.404250 Board ID = 1
443 07:43:56.404685 Set cpu clk to 24M
444 07:43:56.405106 Set clk81 to 24M
445 07:43:56.408922 Use GP1_pll as DSU clk.
446 07:43:56.409388 DSU clk: 1200 Mhz
447 07:43:56.409811 CPU clk: 1200 MHz
448 07:43:56.414479 Set clk81 to 166.6M
449 07:43:56.420117 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
450 07:43:56.420582 board id: 1
451 07:43:56.428008 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
452 07:43:56.438924 fw parse done
453 07:43:56.444876 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
454 07:43:56.488036 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
455 07:43:56.499179 PIEI prepare done
456 07:43:56.499643 fastboot data load
457 07:43:56.500112 fastboot data verify
458 07:43:56.504749 verify result: 266
459 07:43:56.510362 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
460 07:43:56.510823 LPDDR4 probe
461 07:43:56.511252 ddr clk to 1584MHz
462 07:43:56.518318 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
463 07:43:56.556174
464 07:43:56.556705 dmc_version 0001
465 07:43:56.563177 Check phy result
466 07:43:56.569083 INFO : End of CA training
467 07:43:56.569550 INFO : End of initialization
468 07:43:56.574711 INFO : Training has run successfully!
469 07:43:56.575247 Check phy result
470 07:43:56.580372 INFO : End of initialization
471 07:43:56.580878 INFO : End of read enable training
472 07:43:56.583551 INFO : End of fine write leveling
473 07:43:56.589103 INFO : End of Write leveling coarse delay
474 07:43:56.594709 INFO : Training has run successfully!
475 07:43:56.595193 Check phy result
476 07:43:56.595637 INFO : End of initialization
477 07:43:56.600323 INFO : End of read dq deskew training
478 07:43:56.603750 INFO : End of MPR read delay center optimization
479 07:43:56.609265 INFO : End of write delay center optimization
480 07:43:56.614854 INFO : End of read delay center optimization
481 07:43:56.615332 INFO : End of max read latency training
482 07:43:56.620491 INFO : Training has run successfully!
483 07:43:56.620974 1D training succeed
484 07:43:56.628849 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
485 07:43:56.677028 Check phy result
486 07:43:56.677549 INFO : End of initialization
487 07:43:56.704415 INFO : End of 2D read delay Voltage center optimization
488 07:43:56.728494 INFO : End of 2D read delay Voltage center optimization
489 07:43:56.785220 INFO : End of 2D write delay Voltage center optimization
490 07:43:56.839159 INFO : End of 2D write delay Voltage center optimization
491 07:43:56.844643 INFO : Training has run successfully!
492 07:43:56.845147
493 07:43:56.845604 channel==0
494 07:43:56.850220 RxClkDly_Margin_A0==88 ps 9
495 07:43:56.850698 TxDqDly_Margin_A0==98 ps 10
496 07:43:56.853570 RxClkDly_Margin_A1==88 ps 9
497 07:43:56.854045 TxDqDly_Margin_A1==98 ps 10
498 07:43:56.859160 TrainedVREFDQ_A0==74
499 07:43:56.859651 TrainedVREFDQ_A1==75
500 07:43:56.860133 VrefDac_Margin_A0==24
501 07:43:56.864764 DeviceVref_Margin_A0==40
502 07:43:56.865237 VrefDac_Margin_A1==23
503 07:43:56.870382 DeviceVref_Margin_A1==39
504 07:43:56.870877
505 07:43:56.871325
506 07:43:56.871766 channel==1
507 07:43:56.872239 RxClkDly_Margin_A0==78 ps 8
508 07:43:56.873630 TxDqDly_Margin_A0==98 ps 10
509 07:43:56.879192 RxClkDly_Margin_A1==78 ps 8
510 07:43:56.879674 TxDqDly_Margin_A1==88 ps 9
511 07:43:56.880172 TrainedVREFDQ_A0==78
512 07:43:56.884822 TrainedVREFDQ_A1==78
513 07:43:56.885307 VrefDac_Margin_A0==22
514 07:43:56.890402 DeviceVref_Margin_A0==36
515 07:43:56.890873 VrefDac_Margin_A1==22
516 07:43:56.891316 DeviceVref_Margin_A1==36
517 07:43:56.891751
518 07:43:56.895977 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
519 07:43:56.896495
520 07:43:56.929656 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000018 00000017 00000019 00000018 00000017 00000018 00000015 00000018 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001c 00000018 00000016 00000017 dram_vref_reg_value 0x 00000061
521 07:43:56.930198 2D training succeed
522 07:43:56.935160 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
523 07:43:56.940823 auto size-- 65535DDR cs0 size: 2048MB
524 07:43:56.941318 DDR cs1 size: 2048MB
525 07:43:56.946373 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
526 07:43:56.946885 cs0 DataBus test pass
527 07:43:56.947389 cs1 DataBus test pass
528 07:43:56.962088 cs0 AddrBus test pass
529 07:43:56.962633 cs1 AddrBus test pass
530 07:43:56.963083
531 07:43:56.963526 100bdlr_step_size ps== 478
532 07:43:56.963974 result report
533 07:43:56.964468 boot times 0Enable ddr reg access
534 07:43:56.967516 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
535 07:43:56.981364 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
536 07:43:57.640505 bl2z: ptr: 05129330, size: 00001e40
537 07:43:57.648797 0.0;M3 CHK:0;cm4_sp_mode 0
538 07:43:57.649457 MVN_1=0x00000000
539 07:43:57.649949 MVN_2=0x00000000
540 07:43:57.660335 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
541 07:43:57.660967 OPS=0x04
542 07:43:57.661405 ring efuse init
543 07:43:57.663326 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
544 07:43:57.669399 [0.017354 Inits done]
545 07:43:57.669954 secure task start!
546 07:43:57.670377 high task start!
547 07:43:57.670790 low task start!
548 07:43:57.673743 run into bl31
549 07:43:57.682392 NOTICE: BL31: v1.3(release):4fc40b1
550 07:43:57.690184 NOTICE: BL31: Built : 15:57:33, May 22 2019
551 07:43:57.690744 NOTICE: BL31: G12A normal boot!
552 07:43:57.705754 NOTICE: BL31: BL33 decompress pass
553 07:43:57.711459 ERROR: Error initializing runtime service opteed_fast
554 07:43:59.076434 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
555 07:43:59.077049 bl2_stage_init 0x01
556 07:43:59.077475 bl2_stage_init 0x81
557 07:43:59.081881 hw id: 0x0000 - pwm id 0x01
558 07:43:59.082381 bl2_stage_init 0xc1
559 07:43:59.087457 bl2_stage_init 0x02
560 07:43:59.087938
561 07:43:59.088410 L0:00000000
562 07:43:59.088817 L1:00000703
563 07:43:59.089214 L2:00008067
564 07:43:59.089612 L3:15000000
565 07:43:59.092968 S1:00000000
566 07:43:59.093436 B2:20282000
567 07:43:59.093844 B1:a0f83180
568 07:43:59.094244
569 07:43:59.094648 TE: 68587
570 07:43:59.095043
571 07:43:59.098542 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
572 07:43:59.099013
573 07:43:59.104388 Board ID = 1
574 07:43:59.104862 Set cpu clk to 24M
575 07:43:59.105271 Set clk81 to 24M
576 07:43:59.109826 Use GP1_pll as DSU clk.
577 07:43:59.110292 DSU clk: 1200 Mhz
578 07:43:59.110700 CPU clk: 1200 MHz
579 07:43:59.115397 Set clk81 to 166.6M
580 07:43:59.121192 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
581 07:43:59.121658 board id: 1
582 07:43:59.128360 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
583 07:43:59.139069 fw parse done
584 07:43:59.145087 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
585 07:43:59.188081 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
586 07:43:59.199145 PIEI prepare done
587 07:43:59.199625 fastboot data load
588 07:43:59.200076 fastboot data verify
589 07:43:59.204769 verify result: 266
590 07:43:59.210369 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
591 07:43:59.210839 LPDDR4 probe
592 07:43:59.211251 ddr clk to 1584MHz
593 07:43:59.218335 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
594 07:43:59.256197
595 07:43:59.256706 dmc_version 0001
596 07:43:59.263376 Check phy result
597 07:43:59.270047 INFO : End of CA training
598 07:43:59.270517 INFO : End of initialization
599 07:43:59.274753 INFO : Training has run successfully!
600 07:43:59.275220 Check phy result
601 07:43:59.280363 INFO : End of initialization
602 07:43:59.280822 INFO : End of read enable training
603 07:43:59.285922 INFO : End of fine write leveling
604 07:43:59.291495 INFO : End of Write leveling coarse delay
605 07:43:59.291965 INFO : Training has run successfully!
606 07:43:59.292422 Check phy result
607 07:43:59.297203 INFO : End of initialization
608 07:43:59.297669 INFO : End of read dq deskew training
609 07:43:59.302667 INFO : End of MPR read delay center optimization
610 07:43:59.308294 INFO : End of write delay center optimization
611 07:43:59.313866 INFO : End of read delay center optimization
612 07:43:59.314352 INFO : End of max read latency training
613 07:43:59.319518 INFO : Training has run successfully!
614 07:43:59.320010 1D training succeed
615 07:43:59.328685 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
616 07:43:59.376969 Check phy result
617 07:43:59.377490 INFO : End of initialization
618 07:43:59.404379 INFO : End of 2D read delay Voltage center optimization
619 07:43:59.428482 INFO : End of 2D read delay Voltage center optimization
620 07:43:59.485339 INFO : End of 2D write delay Voltage center optimization
621 07:43:59.539296 INFO : End of 2D write delay Voltage center optimization
622 07:43:59.544807 INFO : Training has run successfully!
623 07:43:59.545343
624 07:43:59.545781 channel==0
625 07:43:59.550389 RxClkDly_Margin_A0==78 ps 8
626 07:43:59.550911 TxDqDly_Margin_A0==88 ps 9
627 07:43:59.556053 RxClkDly_Margin_A1==88 ps 9
628 07:43:59.556575 TxDqDly_Margin_A1==98 ps 10
629 07:43:59.556999 TrainedVREFDQ_A0==74
630 07:43:59.561592 TrainedVREFDQ_A1==75
631 07:43:59.562108 VrefDac_Margin_A0==24
632 07:43:59.562524 DeviceVref_Margin_A0==40
633 07:43:59.567235 VrefDac_Margin_A1==23
634 07:43:59.567752 DeviceVref_Margin_A1==39
635 07:43:59.568202
636 07:43:59.568612
637 07:43:59.569012 channel==1
638 07:43:59.572792 RxClkDly_Margin_A0==78 ps 8
639 07:43:59.573307 TxDqDly_Margin_A0==98 ps 10
640 07:43:59.578341 RxClkDly_Margin_A1==88 ps 9
641 07:43:59.578818 TxDqDly_Margin_A1==88 ps 9
642 07:43:59.583916 TrainedVREFDQ_A0==78
643 07:43:59.584410 TrainedVREFDQ_A1==75
644 07:43:59.584819 VrefDac_Margin_A0==22
645 07:43:59.589507 DeviceVref_Margin_A0==36
646 07:43:59.589962 VrefDac_Margin_A1==23
647 07:43:59.595164 DeviceVref_Margin_A1==39
648 07:43:59.595623
649 07:43:59.596065 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
650 07:43:59.596469
651 07:43:59.628675 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000018 00000018 00000018 00000018 00000017 00000019 00000015 00000018 00000015 00000016 00000017 00000018 00000019 00000018 00000018 0000001c 00000018 00000016 00000016 dram_vref_reg_value 0x 00000061
652 07:43:59.629202 2D training succeed
653 07:43:59.634298 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
654 07:43:59.639903 auto size-- 65535DDR cs0 size: 2048MB
655 07:43:59.640390 DDR cs1 size: 2048MB
656 07:43:59.645500 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
657 07:43:59.645951 cs0 DataBus test pass
658 07:43:59.651130 cs1 DataBus test pass
659 07:43:59.651580 cs0 AddrBus test pass
660 07:43:59.652009 cs1 AddrBus test pass
661 07:43:59.652421
662 07:43:59.656722 100bdlr_step_size ps== 478
663 07:43:59.657191 result report
664 07:43:59.662284 boot times 0Enable ddr reg access
665 07:43:59.667457 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
666 07:43:59.681310 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
667 07:44:00.341243 bl2z: ptr: 05129330, size: 00001e40
668 07:44:00.349976 0.0;M3 CHK:0;cm4_sp_mode 0
669 07:44:00.350468 MVN_1=0x00000000
670 07:44:00.350881 MVN_2=0x00000000
671 07:44:00.361405 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
672 07:44:00.361893 OPS=0x04
673 07:44:00.362308 ring efuse init
674 07:44:00.367066 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
675 07:44:00.367533 [0.017355 Inits done]
676 07:44:00.367942 secure task start!
677 07:44:00.374947 high task start!
678 07:44:00.375414 low task start!
679 07:44:00.375825 run into bl31
680 07:44:00.383555 NOTICE: BL31: v1.3(release):4fc40b1
681 07:44:00.391358 NOTICE: BL31: Built : 15:57:33, May 22 2019
682 07:44:00.391825 NOTICE: BL31: G12A normal boot!
683 07:44:00.406984 NOTICE: BL31: BL33 decompress pass
684 07:44:00.412661 ERROR: Error initializing runtime service opteed_fast
685 07:44:01.208202
686 07:44:01.208833
687 07:44:01.213466 U-Boot 2024.01-rc4+ (Dec 14 2023 - 02:26:00 -0500) Libre Computer AML-S905D3-CC
688 07:44:01.213949
689 07:44:01.216972 Model: Libre Computer AML-S905D3-CC Solitude
690 07:44:01.364111 SoC: Amlogic Meson SM1 (S905D3) Revision 2b:c (4:2)
691 07:44:01.379467 DRAM: 2 GiB (effective 3.8 GiB)
692 07:44:01.480493 Core: 406 devices, 33 uclasses, devicetree: separate
693 07:44:01.486216 WDT: Not starting watchdog@f0d0
694 07:44:01.511252 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
695 07:44:01.523548 Loading Environment from FAT... Card did not respond to voltage select! : -110
696 07:44:01.528496 ** Bad device specification mmc 0 **
697 07:44:01.538550 Card did not respond to voltage select! : -110
698 07:44:01.546228 ** Bad device specification mmc 0 **
699 07:44:01.546691 Couldn't find partition mmc 0
700 07:44:01.554520 Card did not respond to voltage select! : -110
701 07:44:01.560036 ** Bad device specification mmc 0 **
702 07:44:01.560504 Couldn't find partition mmc 0
703 07:44:01.565097 Error: could not access storage.
704 07:44:01.862654 Net: eth0: ethernet@ff3f0000
705 07:44:01.863233 starting USB...
706 07:44:02.107387 Bus usb@ff500000: Register 3000140 NbrPorts 3
707 07:44:02.107962 Starting the controller
708 07:44:02.114330 USB XHCI 1.10
709 07:44:03.668346 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
710 07:44:03.676069 scanning usb for storage devices... 0 Storawe Device(s) found
712 07:44:03.727539 Hit any key to stop autoboot: 1
713 07:44:03.728364 end: 2.4.2 bootloader-interrupt (duration 00:00:20) [common]
714 07:44:03.729007 start: 2.4.3 bootloader-commands (timeout 00:04:40) [common]
715 07:44:03.729492 Setting prompt string to ['=>']
716 07:44:03.729972 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:40)
717 07:44:03.742725 0
718 07:44:03.743603 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
720 07:44:03.844827 => setenv autoload no
721 07:44:03.845716 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
722 07:44:03.850728 setenv autoload no
724 07:44:03.952165 => setenv initrd_high 0xffffffff
725 07:44:03.953008 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
726 07:44:03.957258 setenv initrd_high 0xffffffff
728 07:44:04.058654 => setenv fdt_high 0xffffffff
729 07:44:04.059460 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
730 07:44:04.063745 setenv fdt_high 0xffffffff
732 07:44:04.165202 => dhcp
733 07:44:04.165987 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
734 07:44:04.169987 dhcp
735 07:44:05.125941 ethernet@ff3f0000 Waiting for PHY auto negotiation to complete.. done
736 07:44:05.126506 Speed: 1000, full duplex
737 07:44:05.126928 BOOTP broadcast 1
738 07:44:05.374032 BOOTP broadcast 2
739 07:44:05.388040 DHCP client bound to address 192.168.6.21 (261 ms)
741 07:44:05.489234 => setenv serverip 192.168.6.2
742 07:44:05.489881 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:38)
743 07:44:05.494432 setenv serverip 192.168.6.2
745 07:44:05.595572 => tftpboot 0x01080000 933357/tftp-deploy-f5hzme5r/kernel/uImage
746 07:44:05.596204 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:38)
747 07:44:05.603217 tftpboot 0x01080000 933357/tftp-deploy-f5hzme5r/kernel/uImage
748 07:44:05.603578 Speed: 1000, full duplex
749 07:44:05.603815 Using ethernet@ff3f0000 device
750 07:44:05.608640 TFTP from server 192.168.6.2; our IP address is 192.168.6.21
751 07:44:05.614421 Filename '933357/tftp-deploy-f5hzme5r/kernel/uImage'.
752 07:44:05.618265 Load address: 0x1080000
753 07:44:08.540475 Loading: *################################################## 45.4 MiB
754 07:44:08.541136 15.5 MiB/s
755 07:44:08.541616 done
756 07:44:08.544894 Bytes transferred = 47653440 (2d72240 hex)
758 07:44:08.646575 => tftpboot 0x08000000 933357/tftp-deploy-f5hzme5r/ramdisk/ramdisk.cpio.gz.uboot
759 07:44:08.647392 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:35)
760 07:44:08.654267 tftpboot 0x08000000 933357/tftp-deploy-f5hzme5r/ramdisk/ramdisk.cpio.gz.uboot
761 07:44:08.654806 Speed: 1000, full duplex
762 07:44:08.655246 Using ethernet@ff3f0000 device
763 07:44:08.659924 TFTP from server 192.168.6.2; our IP address is 192.168.6.21
764 07:44:08.669560 Filename '933357/tftp-deploy-f5hzme5r/ramdisk/ramdisk.cpio.gz.uboot'.
765 07:44:08.670503 Load address: 0x8000000
766 07:44:15.843113 Loading: *#############################################T #### UDP wrong checksum 00000005 00009bf3
767 07:44:20.843936 T UDP wrong checksum 00000005 00009bf3
768 07:44:23.443081 UDP wrong checksum 00000005 000016c8
769 07:44:30.844964 T T UDP wrong checksum 00000005 00009bf3
770 07:44:33.958294 UDP wrong checksum 000000ff 00003d10
771 07:44:33.978506 UDP wrong checksum 000000ff 0000d202
772 07:44:36.288717 T UDP wrong checksum 000000ff 00007f9b
773 07:44:36.306977 UDP wrong checksum 000000ff 0000138e
774 07:44:50.850129 T T T UDP wrong checksum 00000005 00009bf3
775 07:45:05.853885 T T
776 07:45:05.854516 Retry count exceeded; starting again
778 07:45:05.855958 end: 2.4.3 bootloader-commands (duration 00:01:02) [common]
781 07:45:05.857905 end: 2.4 uboot-commands (duration 00:01:22) [common]
783 07:45:05.859306 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
785 07:45:05.860390 end: 2 uboot-action (duration 00:01:22) [common]
787 07:45:05.861889 Cleaning after the job
788 07:45:05.862442 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/933357/tftp-deploy-f5hzme5r/ramdisk
789 07:45:05.863579 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/933357/tftp-deploy-f5hzme5r/kernel
790 07:45:05.908955 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/933357/tftp-deploy-f5hzme5r/dtb
791 07:45:05.909837 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/933357/tftp-deploy-f5hzme5r/modules
792 07:45:05.931578 start: 4.1 power-off (timeout 00:00:30) [common]
793 07:45:05.932285 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=solitude-01'
794 07:45:05.965770 >> OK - accepted request
795 07:45:05.967651 Returned 0 in 0 seconds
796 07:45:06.068557 end: 4.1 power-off (duration 00:00:00) [common]
798 07:45:06.069873 start: 4.2 read-feedback (timeout 00:10:00) [common]
799 07:45:06.070603 Listened to connection for namespace 'common' for up to 1s
800 07:45:07.071292 Finalising connection for namespace 'common'
801 07:45:07.071882 Disconnecting from shell: Finalise
802 07:45:07.072297 =>
803 07:45:07.173114 end: 4.2 read-feedback (duration 00:00:01) [common]
804 07:45:07.173866 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/933357
805 07:45:07.445489 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/933357
806 07:45:07.446140 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.