Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 07:19:05.095052 lava-dispatcher, installed at version: 2024.01
2 07:19:05.095853 start: 0 validate
3 07:19:05.096362 Start time: 2024-11-04 07:19:05.096331+00:00 (UTC)
4 07:19:05.096907 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 07:19:05.097442 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230703.0%2Farm64%2Frootfs.cpio.gz exists
6 07:19:05.136669 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 07:19:05.137237 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241104%2Farm64%2Fdefconfig%2BCONFIG_RANDOMIZE_BASE%3Dy%2Fgcc-12%2Fkernel%2FImage exists
8 07:19:05.165099 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 07:19:05.165752 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241104%2Farm64%2Fdefconfig%2BCONFIG_RANDOMIZE_BASE%3Dy%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 07:19:06.214063 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 07:19:06.214891 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241104%2Farm64%2Fdefconfig%2BCONFIG_RANDOMIZE_BASE%3Dy%2Fgcc-12%2Fmodules.tar.xz exists
12 07:19:06.252431 validate duration: 1.16
14 07:19:06.253283 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 07:19:06.253626 start: 1.1 download-retry (timeout 00:10:00) [common]
16 07:19:06.253935 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 07:19:06.254508 Not decompressing ramdisk as can be used compressed.
18 07:19:06.254930 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230703.0/arm64/rootfs.cpio.gz
19 07:19:06.255178 saving as /var/lib/lava/dispatcher/tmp/933026/tftp-deploy-2pddd2tu/ramdisk/rootfs.cpio.gz
20 07:19:06.255442 total size: 8181887 (7 MB)
21 07:19:06.294391 progress 0 % (0 MB)
22 07:19:06.305558 progress 5 % (0 MB)
23 07:19:06.316342 progress 10 % (0 MB)
24 07:19:06.327438 progress 15 % (1 MB)
25 07:19:06.333047 progress 20 % (1 MB)
26 07:19:06.338762 progress 25 % (1 MB)
27 07:19:06.344130 progress 30 % (2 MB)
28 07:19:06.349938 progress 35 % (2 MB)
29 07:19:06.355267 progress 40 % (3 MB)
30 07:19:06.361086 progress 45 % (3 MB)
31 07:19:06.366378 progress 50 % (3 MB)
32 07:19:06.372333 progress 55 % (4 MB)
33 07:19:06.377985 progress 60 % (4 MB)
34 07:19:06.383735 progress 65 % (5 MB)
35 07:19:06.389059 progress 70 % (5 MB)
36 07:19:06.394696 progress 75 % (5 MB)
37 07:19:06.399954 progress 80 % (6 MB)
38 07:19:06.405758 progress 85 % (6 MB)
39 07:19:06.411209 progress 90 % (7 MB)
40 07:19:06.417112 progress 95 % (7 MB)
41 07:19:06.422088 progress 100 % (7 MB)
42 07:19:06.422758 7 MB downloaded in 0.17 s (46.64 MB/s)
43 07:19:06.423341 end: 1.1.1 http-download (duration 00:00:00) [common]
45 07:19:06.424318 end: 1.1 download-retry (duration 00:00:00) [common]
46 07:19:06.424643 start: 1.2 download-retry (timeout 00:10:00) [common]
47 07:19:06.424936 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 07:19:06.425424 downloading http://storage.kernelci.org/next/master/next-20241104/arm64/defconfig+CONFIG_RANDOMIZE_BASE=y/gcc-12/kernel/Image
49 07:19:06.425685 saving as /var/lib/lava/dispatcher/tmp/933026/tftp-deploy-2pddd2tu/kernel/Image
50 07:19:06.425905 total size: 46041600 (43 MB)
51 07:19:06.426126 No compression specified
52 07:19:06.461469 progress 0 % (0 MB)
53 07:19:06.490003 progress 5 % (2 MB)
54 07:19:06.519403 progress 10 % (4 MB)
55 07:19:06.548484 progress 15 % (6 MB)
56 07:19:06.578660 progress 20 % (8 MB)
57 07:19:06.610353 progress 25 % (11 MB)
58 07:19:06.638866 progress 30 % (13 MB)
59 07:19:06.668685 progress 35 % (15 MB)
60 07:19:06.697859 progress 40 % (17 MB)
61 07:19:06.728330 progress 45 % (19 MB)
62 07:19:06.758135 progress 50 % (21 MB)
63 07:19:06.787467 progress 55 % (24 MB)
64 07:19:06.818030 progress 60 % (26 MB)
65 07:19:06.846974 progress 65 % (28 MB)
66 07:19:06.876109 progress 70 % (30 MB)
67 07:19:06.905332 progress 75 % (32 MB)
68 07:19:06.935030 progress 80 % (35 MB)
69 07:19:06.964652 progress 85 % (37 MB)
70 07:19:06.993391 progress 90 % (39 MB)
71 07:19:07.022573 progress 95 % (41 MB)
72 07:19:07.052074 progress 100 % (43 MB)
73 07:19:07.052597 43 MB downloaded in 0.63 s (70.07 MB/s)
74 07:19:07.053091 end: 1.2.1 http-download (duration 00:00:01) [common]
76 07:19:07.053924 end: 1.2 download-retry (duration 00:00:01) [common]
77 07:19:07.054203 start: 1.3 download-retry (timeout 00:09:59) [common]
78 07:19:07.054471 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 07:19:07.054948 downloading http://storage.kernelci.org/next/master/next-20241104/arm64/defconfig+CONFIG_RANDOMIZE_BASE=y/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
80 07:19:07.055228 saving as /var/lib/lava/dispatcher/tmp/933026/tftp-deploy-2pddd2tu/dtb/meson-g12b-a311d-libretech-cc.dtb
81 07:19:07.055440 total size: 54703 (0 MB)
82 07:19:07.055652 No compression specified
83 07:19:07.093933 progress 59 % (0 MB)
84 07:19:07.094775 progress 100 % (0 MB)
85 07:19:07.095331 0 MB downloaded in 0.04 s (1.31 MB/s)
86 07:19:07.095794 end: 1.3.1 http-download (duration 00:00:00) [common]
88 07:19:07.096654 end: 1.3 download-retry (duration 00:00:00) [common]
89 07:19:07.096922 start: 1.4 download-retry (timeout 00:09:59) [common]
90 07:19:07.097187 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 07:19:07.097646 downloading http://storage.kernelci.org/next/master/next-20241104/arm64/defconfig+CONFIG_RANDOMIZE_BASE=y/gcc-12/modules.tar.xz
92 07:19:07.097890 saving as /var/lib/lava/dispatcher/tmp/933026/tftp-deploy-2pddd2tu/modules/modules.tar
93 07:19:07.098096 total size: 11679760 (11 MB)
94 07:19:07.098308 Using unxz to decompress xz
95 07:19:07.134264 progress 0 % (0 MB)
96 07:19:07.200998 progress 5 % (0 MB)
97 07:19:07.277127 progress 10 % (1 MB)
98 07:19:07.387773 progress 15 % (1 MB)
99 07:19:07.502974 progress 20 % (2 MB)
100 07:19:07.597271 progress 25 % (2 MB)
101 07:19:07.669056 progress 30 % (3 MB)
102 07:19:07.748165 progress 35 % (3 MB)
103 07:19:07.825418 progress 40 % (4 MB)
104 07:19:07.901432 progress 45 % (5 MB)
105 07:19:07.987652 progress 50 % (5 MB)
106 07:19:08.069629 progress 55 % (6 MB)
107 07:19:08.151075 progress 60 % (6 MB)
108 07:19:08.231598 progress 65 % (7 MB)
109 07:19:08.312514 progress 70 % (7 MB)
110 07:19:08.396058 progress 75 % (8 MB)
111 07:19:08.479867 progress 80 % (8 MB)
112 07:19:08.556248 progress 85 % (9 MB)
113 07:19:08.639079 progress 90 % (10 MB)
114 07:19:08.717218 progress 95 % (10 MB)
115 07:19:08.795845 progress 100 % (11 MB)
116 07:19:08.808785 11 MB downloaded in 1.71 s (6.51 MB/s)
117 07:19:08.809527 end: 1.4.1 http-download (duration 00:00:02) [common]
119 07:19:08.811388 end: 1.4 download-retry (duration 00:00:02) [common]
120 07:19:08.812036 start: 1.5 prepare-tftp-overlay (timeout 00:09:57) [common]
121 07:19:08.812652 start: 1.5.1 extract-nfsrootfs (timeout 00:09:57) [common]
122 07:19:08.813227 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 07:19:08.813804 start: 1.5.2 lava-overlay (timeout 00:09:57) [common]
124 07:19:08.814882 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/933026/lava-overlay-2k18kd5e
125 07:19:08.815820 makedir: /var/lib/lava/dispatcher/tmp/933026/lava-overlay-2k18kd5e/lava-933026/bin
126 07:19:08.816597 makedir: /var/lib/lava/dispatcher/tmp/933026/lava-overlay-2k18kd5e/lava-933026/tests
127 07:19:08.817307 makedir: /var/lib/lava/dispatcher/tmp/933026/lava-overlay-2k18kd5e/lava-933026/results
128 07:19:08.818008 Creating /var/lib/lava/dispatcher/tmp/933026/lava-overlay-2k18kd5e/lava-933026/bin/lava-add-keys
129 07:19:08.819056 Creating /var/lib/lava/dispatcher/tmp/933026/lava-overlay-2k18kd5e/lava-933026/bin/lava-add-sources
130 07:19:08.820128 Creating /var/lib/lava/dispatcher/tmp/933026/lava-overlay-2k18kd5e/lava-933026/bin/lava-background-process-start
131 07:19:08.821221 Creating /var/lib/lava/dispatcher/tmp/933026/lava-overlay-2k18kd5e/lava-933026/bin/lava-background-process-stop
132 07:19:08.822343 Creating /var/lib/lava/dispatcher/tmp/933026/lava-overlay-2k18kd5e/lava-933026/bin/lava-common-functions
133 07:19:08.823377 Creating /var/lib/lava/dispatcher/tmp/933026/lava-overlay-2k18kd5e/lava-933026/bin/lava-echo-ipv4
134 07:19:08.824452 Creating /var/lib/lava/dispatcher/tmp/933026/lava-overlay-2k18kd5e/lava-933026/bin/lava-install-packages
135 07:19:08.825476 Creating /var/lib/lava/dispatcher/tmp/933026/lava-overlay-2k18kd5e/lava-933026/bin/lava-installed-packages
136 07:19:08.826487 Creating /var/lib/lava/dispatcher/tmp/933026/lava-overlay-2k18kd5e/lava-933026/bin/lava-os-build
137 07:19:08.827519 Creating /var/lib/lava/dispatcher/tmp/933026/lava-overlay-2k18kd5e/lava-933026/bin/lava-probe-channel
138 07:19:08.828578 Creating /var/lib/lava/dispatcher/tmp/933026/lava-overlay-2k18kd5e/lava-933026/bin/lava-probe-ip
139 07:19:08.829588 Creating /var/lib/lava/dispatcher/tmp/933026/lava-overlay-2k18kd5e/lava-933026/bin/lava-target-ip
140 07:19:08.830594 Creating /var/lib/lava/dispatcher/tmp/933026/lava-overlay-2k18kd5e/lava-933026/bin/lava-target-mac
141 07:19:08.831601 Creating /var/lib/lava/dispatcher/tmp/933026/lava-overlay-2k18kd5e/lava-933026/bin/lava-target-storage
142 07:19:08.832670 Creating /var/lib/lava/dispatcher/tmp/933026/lava-overlay-2k18kd5e/lava-933026/bin/lava-test-case
143 07:19:08.833701 Creating /var/lib/lava/dispatcher/tmp/933026/lava-overlay-2k18kd5e/lava-933026/bin/lava-test-event
144 07:19:08.834702 Creating /var/lib/lava/dispatcher/tmp/933026/lava-overlay-2k18kd5e/lava-933026/bin/lava-test-feedback
145 07:19:08.835705 Creating /var/lib/lava/dispatcher/tmp/933026/lava-overlay-2k18kd5e/lava-933026/bin/lava-test-raise
146 07:19:08.836799 Creating /var/lib/lava/dispatcher/tmp/933026/lava-overlay-2k18kd5e/lava-933026/bin/lava-test-reference
147 07:19:08.837821 Creating /var/lib/lava/dispatcher/tmp/933026/lava-overlay-2k18kd5e/lava-933026/bin/lava-test-runner
148 07:19:08.838864 Creating /var/lib/lava/dispatcher/tmp/933026/lava-overlay-2k18kd5e/lava-933026/bin/lava-test-set
149 07:19:08.839876 Creating /var/lib/lava/dispatcher/tmp/933026/lava-overlay-2k18kd5e/lava-933026/bin/lava-test-shell
150 07:19:08.840955 Updating /var/lib/lava/dispatcher/tmp/933026/lava-overlay-2k18kd5e/lava-933026/bin/lava-install-packages (oe)
151 07:19:08.842057 Updating /var/lib/lava/dispatcher/tmp/933026/lava-overlay-2k18kd5e/lava-933026/bin/lava-installed-packages (oe)
152 07:19:08.843000 Creating /var/lib/lava/dispatcher/tmp/933026/lava-overlay-2k18kd5e/lava-933026/environment
153 07:19:08.843809 LAVA metadata
154 07:19:08.844398 - LAVA_JOB_ID=933026
155 07:19:08.844899 - LAVA_DISPATCHER_IP=192.168.6.2
156 07:19:08.845636 start: 1.5.2.1 ssh-authorize (timeout 00:09:57) [common]
157 07:19:08.847721 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 07:19:08.848408 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:57) [common]
159 07:19:08.848847 skipped lava-vland-overlay
160 07:19:08.849359 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 07:19:08.849898 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:57) [common]
162 07:19:08.850344 skipped lava-multinode-overlay
163 07:19:08.850846 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 07:19:08.851366 start: 1.5.2.4 test-definition (timeout 00:09:57) [common]
165 07:19:08.851856 Loading test definitions
166 07:19:08.852460 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:57) [common]
167 07:19:08.852925 Using /lava-933026 at stage 0
168 07:19:08.855121 uuid=933026_1.5.2.4.1 testdef=None
169 07:19:08.855706 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 07:19:08.856201 start: 1.5.2.4.2 test-overlay (timeout 00:09:57) [common]
171 07:19:08.858049 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 07:19:08.858893 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:57) [common]
174 07:19:08.861199 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 07:19:08.862074 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:57) [common]
177 07:19:08.864312 runner path: /var/lib/lava/dispatcher/tmp/933026/lava-overlay-2k18kd5e/lava-933026/0/tests/0_dmesg test_uuid 933026_1.5.2.4.1
178 07:19:08.864894 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 07:19:08.865708 Creating lava-test-runner.conf files
181 07:19:08.865933 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/933026/lava-overlay-2k18kd5e/lava-933026/0 for stage 0
182 07:19:08.866294 - 0_dmesg
183 07:19:08.866673 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 07:19:08.866977 start: 1.5.2.5 compress-overlay (timeout 00:09:57) [common]
185 07:19:08.890529 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 07:19:08.890926 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:57) [common]
187 07:19:08.891226 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 07:19:08.891521 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 07:19:08.891811 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:57) [common]
190 07:19:09.802336 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
191 07:19:09.802811 start: 1.5.4 extract-modules (timeout 00:09:56) [common]
192 07:19:09.803061 extracting modules file /var/lib/lava/dispatcher/tmp/933026/tftp-deploy-2pddd2tu/modules/modules.tar to /var/lib/lava/dispatcher/tmp/933026/extract-overlay-ramdisk-8biad_me/ramdisk
193 07:19:11.151634 end: 1.5.4 extract-modules (duration 00:00:01) [common]
194 07:19:11.152138 start: 1.5.5 apply-overlay-tftp (timeout 00:09:55) [common]
195 07:19:11.152415 [common] Applying overlay /var/lib/lava/dispatcher/tmp/933026/compress-overlay-3du4lmby/overlay-1.5.2.5.tar.gz to ramdisk
196 07:19:11.152630 [common] Applying overlay /var/lib/lava/dispatcher/tmp/933026/compress-overlay-3du4lmby/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/933026/extract-overlay-ramdisk-8biad_me/ramdisk
197 07:19:11.182349 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 07:19:11.182745 start: 1.5.6 prepare-kernel (timeout 00:09:55) [common]
199 07:19:11.183014 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:55) [common]
200 07:19:11.183239 Converting downloaded kernel to a uImage
201 07:19:11.183541 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/933026/tftp-deploy-2pddd2tu/kernel/Image /var/lib/lava/dispatcher/tmp/933026/tftp-deploy-2pddd2tu/kernel/uImage
202 07:19:11.629324 output: Image Name:
203 07:19:11.629752 output: Created: Mon Nov 4 07:19:11 2024
204 07:19:11.629965 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 07:19:11.630174 output: Data Size: 46041600 Bytes = 44962.50 KiB = 43.91 MiB
206 07:19:11.630378 output: Load Address: 01080000
207 07:19:11.630578 output: Entry Point: 01080000
208 07:19:11.630775 output:
209 07:19:11.631109 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
210 07:19:11.631379 end: 1.5.6 prepare-kernel (duration 00:00:00) [common]
211 07:19:11.631649 start: 1.5.7 configure-preseed-file (timeout 00:09:55) [common]
212 07:19:11.631903 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 07:19:11.632206 start: 1.5.8 compress-ramdisk (timeout 00:09:55) [common]
214 07:19:11.632468 Building ramdisk /var/lib/lava/dispatcher/tmp/933026/extract-overlay-ramdisk-8biad_me/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/933026/extract-overlay-ramdisk-8biad_me/ramdisk
215 07:19:14.022942 >> 182797 blocks
216 07:19:22.464756 Adding RAMdisk u-boot header.
217 07:19:22.465206 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/933026/extract-overlay-ramdisk-8biad_me/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/933026/extract-overlay-ramdisk-8biad_me/ramdisk.cpio.gz.uboot
218 07:19:22.734363 output: Image Name:
219 07:19:22.734965 output: Created: Mon Nov 4 07:19:22 2024
220 07:19:22.735376 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 07:19:22.735778 output: Data Size: 26169249 Bytes = 25555.91 KiB = 24.96 MiB
222 07:19:22.736231 output: Load Address: 00000000
223 07:19:22.736628 output: Entry Point: 00000000
224 07:19:22.737017 output:
225 07:19:22.737963 rename /var/lib/lava/dispatcher/tmp/933026/extract-overlay-ramdisk-8biad_me/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/933026/tftp-deploy-2pddd2tu/ramdisk/ramdisk.cpio.gz.uboot
226 07:19:22.738649 end: 1.5.8 compress-ramdisk (duration 00:00:11) [common]
227 07:19:22.739194 end: 1.5 prepare-tftp-overlay (duration 00:00:14) [common]
228 07:19:22.739760 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:44) [common]
229 07:19:22.740254 No LXC device requested
230 07:19:22.740756 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 07:19:22.741262 start: 1.7 deploy-device-env (timeout 00:09:44) [common]
232 07:19:22.741749 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 07:19:22.742155 Checking files for TFTP limit of 4294967296 bytes.
234 07:19:22.744805 end: 1 tftp-deploy (duration 00:00:16) [common]
235 07:19:22.745372 start: 2 uboot-action (timeout 00:05:00) [common]
236 07:19:22.745894 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 07:19:22.746388 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 07:19:22.746883 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 07:19:22.747406 Using kernel file from prepare-kernel: 933026/tftp-deploy-2pddd2tu/kernel/uImage
240 07:19:22.748033 substitutions:
241 07:19:22.748444 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 07:19:22.748845 - {DTB_ADDR}: 0x01070000
243 07:19:22.749242 - {DTB}: 933026/tftp-deploy-2pddd2tu/dtb/meson-g12b-a311d-libretech-cc.dtb
244 07:19:22.749637 - {INITRD}: 933026/tftp-deploy-2pddd2tu/ramdisk/ramdisk.cpio.gz.uboot
245 07:19:22.750029 - {KERNEL_ADDR}: 0x01080000
246 07:19:22.750416 - {KERNEL}: 933026/tftp-deploy-2pddd2tu/kernel/uImage
247 07:19:22.750807 - {LAVA_MAC}: None
248 07:19:22.751236 - {PRESEED_CONFIG}: None
249 07:19:22.751629 - {PRESEED_LOCAL}: None
250 07:19:22.752041 - {RAMDISK_ADDR}: 0x08000000
251 07:19:22.752437 - {RAMDISK}: 933026/tftp-deploy-2pddd2tu/ramdisk/ramdisk.cpio.gz.uboot
252 07:19:22.752830 - {ROOT_PART}: None
253 07:19:22.753218 - {ROOT}: None
254 07:19:22.753604 - {SERVER_IP}: 192.168.6.2
255 07:19:22.753999 - {TEE_ADDR}: 0x83000000
256 07:19:22.754387 - {TEE}: None
257 07:19:22.754776 Parsed boot commands:
258 07:19:22.755152 - setenv autoload no
259 07:19:22.755540 - setenv initrd_high 0xffffffff
260 07:19:22.755927 - setenv fdt_high 0xffffffff
261 07:19:22.756339 - dhcp
262 07:19:22.756724 - setenv serverip 192.168.6.2
263 07:19:22.757109 - tftpboot 0x01080000 933026/tftp-deploy-2pddd2tu/kernel/uImage
264 07:19:22.757496 - tftpboot 0x08000000 933026/tftp-deploy-2pddd2tu/ramdisk/ramdisk.cpio.gz.uboot
265 07:19:22.757881 - tftpboot 0x01070000 933026/tftp-deploy-2pddd2tu/dtb/meson-g12b-a311d-libretech-cc.dtb
266 07:19:22.758265 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 07:19:22.758655 - bootm 0x01080000 0x08000000 0x01070000
268 07:19:22.759138 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 07:19:22.760782 start: 2.3 connect-device (timeout 00:05:00) [common]
271 07:19:22.761235 [common] connect-device Connecting to device using 'telnet conserv1 3007'
272 07:19:22.775599 Setting prompt string to ['lava-test: # ']
273 07:19:22.777107 end: 2.3 connect-device (duration 00:00:00) [common]
274 07:19:22.777693 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 07:19:22.778240 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 07:19:22.778771 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 07:19:22.779921 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
278 07:19:22.814260 >> OK - accepted request
279 07:19:22.816385 Returned 0 in 0 seconds
280 07:19:22.917477 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
282 07:19:22.919046 end: 2.4.1 reset-device (duration 00:00:00) [common]
283 07:19:22.919592 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
284 07:19:22.920137 Setting prompt string to ['Hit any key to stop autoboot']
285 07:19:22.920598 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 07:19:22.922148 Trying 192.168.56.21...
287 07:19:22.922624 Connected to conserv1.
288 07:19:22.923045 Escape character is '^]'.
289 07:19:22.923467
290 07:19:22.923892 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
291 07:19:22.924377
292 07:19:34.281862 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
293 07:19:34.282523 bl2_stage_init 0x01
294 07:19:34.283028 bl2_stage_init 0x81
295 07:19:34.287276 hw id: 0x0000 - pwm id 0x01
296 07:19:34.287840 bl2_stage_init 0xc1
297 07:19:34.288372 bl2_stage_init 0x02
298 07:19:34.288854
299 07:19:34.292741 L0:00000000
300 07:19:34.293259 L1:20000703
301 07:19:34.293700 L2:00008067
302 07:19:34.294130 L3:14000000
303 07:19:34.298446 B2:00402000
304 07:19:34.298942 B1:e0f83180
305 07:19:34.299375
306 07:19:34.299807 TE: 58124
307 07:19:34.300289
308 07:19:34.304033 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
309 07:19:34.304534
310 07:19:34.304975 Board ID = 1
311 07:19:34.309700 Set A53 clk to 24M
312 07:19:34.310192 Set A73 clk to 24M
313 07:19:34.310626 Set clk81 to 24M
314 07:19:34.315242 A53 clk: 1200 MHz
315 07:19:34.315732 A73 clk: 1200 MHz
316 07:19:34.316210 CLK81: 166.6M
317 07:19:34.316640 smccc: 00012a91
318 07:19:34.320800 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
319 07:19:34.326405 board id: 1
320 07:19:34.331697 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
321 07:19:34.342813 fw parse done
322 07:19:34.348829 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
323 07:19:34.391419 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
324 07:19:34.402369 PIEI prepare done
325 07:19:34.402860 fastboot data load
326 07:19:34.403300 fastboot data verify
327 07:19:34.407947 verify result: 266
328 07:19:34.413758 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
329 07:19:34.414285 LPDDR4 probe
330 07:19:34.414753 ddr clk to 1584MHz
331 07:19:34.421585 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
332 07:19:34.458825
333 07:19:34.459350 dmc_version 0001
334 07:19:34.465553 Check phy result
335 07:19:34.471381 INFO : End of CA training
336 07:19:34.471886 INFO : End of initialization
337 07:19:34.476953 INFO : Training has run successfully!
338 07:19:34.477460 Check phy result
339 07:19:34.482659 INFO : End of initialization
340 07:19:34.483159 INFO : End of read enable training
341 07:19:34.485837 INFO : End of fine write leveling
342 07:19:34.491427 INFO : End of Write leveling coarse delay
343 07:19:34.497059 INFO : Training has run successfully!
344 07:19:34.497558 Check phy result
345 07:19:34.498014 INFO : End of initialization
346 07:19:34.502717 INFO : End of read dq deskew training
347 07:19:34.508258 INFO : End of MPR read delay center optimization
348 07:19:34.508764 INFO : End of write delay center optimization
349 07:19:34.513843 INFO : End of read delay center optimization
350 07:19:34.519463 INFO : End of max read latency training
351 07:19:34.519959 INFO : Training has run successfully!
352 07:19:34.525053 1D training succeed
353 07:19:34.531010 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
354 07:19:34.578540 Check phy result
355 07:19:34.579055 INFO : End of initialization
356 07:19:34.600270 INFO : End of 2D read delay Voltage center optimization
357 07:19:34.620535 INFO : End of 2D read delay Voltage center optimization
358 07:19:34.672702 INFO : End of 2D write delay Voltage center optimization
359 07:19:34.721968 INFO : End of 2D write delay Voltage center optimization
360 07:19:34.727483 INFO : Training has run successfully!
361 07:19:34.728037
362 07:19:34.728512 channel==0
363 07:19:34.733195 RxClkDly_Margin_A0==88 ps 9
364 07:19:34.733698 TxDqDly_Margin_A0==98 ps 10
365 07:19:34.738860 RxClkDly_Margin_A1==88 ps 9
366 07:19:34.739361 TxDqDly_Margin_A1==88 ps 9
367 07:19:34.739822 TrainedVREFDQ_A0==74
368 07:19:34.744391 TrainedVREFDQ_A1==74
369 07:19:34.744894 VrefDac_Margin_A0==25
370 07:19:34.745347 DeviceVref_Margin_A0==40
371 07:19:34.749938 VrefDac_Margin_A1==25
372 07:19:34.750438 DeviceVref_Margin_A1==40
373 07:19:34.750896
374 07:19:34.751344
375 07:19:34.751791 channel==1
376 07:19:34.755574 RxClkDly_Margin_A0==98 ps 10
377 07:19:34.756103 TxDqDly_Margin_A0==98 ps 10
378 07:19:34.761156 RxClkDly_Margin_A1==98 ps 10
379 07:19:34.761670 TxDqDly_Margin_A1==88 ps 9
380 07:19:34.766780 TrainedVREFDQ_A0==77
381 07:19:34.767283 TrainedVREFDQ_A1==77
382 07:19:34.767738 VrefDac_Margin_A0==22
383 07:19:34.772298 DeviceVref_Margin_A0==37
384 07:19:34.772804 VrefDac_Margin_A1==24
385 07:19:34.777912 DeviceVref_Margin_A1==37
386 07:19:34.778414
387 07:19:34.778871 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
388 07:19:34.779321
389 07:19:34.811393 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000019 00000018 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
390 07:19:34.811976 2D training succeed
391 07:19:34.817107 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
392 07:19:34.822620 auto size-- 65535DDR cs0 size: 2048MB
393 07:19:34.823069 DDR cs1 size: 2048MB
394 07:19:34.828188 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
395 07:19:34.828636 cs0 DataBus test pass
396 07:19:34.833762 cs1 DataBus test pass
397 07:19:34.834244 cs0 AddrBus test pass
398 07:19:34.834688 cs1 AddrBus test pass
399 07:19:34.835097
400 07:19:34.839358 100bdlr_step_size ps== 420
401 07:19:34.839814 result report
402 07:19:34.844944 boot times 0Enable ddr reg access
403 07:19:34.850329 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
404 07:19:34.863810 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
405 07:19:35.437588 0.0;M3 CHK:0;cm4_sp_mode 0
406 07:19:35.438284 MVN_1=0x00000000
407 07:19:35.442994 MVN_2=0x00000000
408 07:19:35.448734 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
409 07:19:35.449259 OPS=0x10
410 07:19:35.449699 ring efuse init
411 07:19:35.450116 chipver efuse init
412 07:19:35.456960 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
413 07:19:35.457488 [0.018961 Inits done]
414 07:19:35.464519 secure task start!
415 07:19:35.465018 high task start!
416 07:19:35.465444 low task start!
417 07:19:35.465857 run into bl31
418 07:19:35.471163 NOTICE: BL31: v1.3(release):4fc40b1
419 07:19:35.479031 NOTICE: BL31: Built : 15:58:17, May 22 2019
420 07:19:35.479616 NOTICE: BL31: G12A normal boot!
421 07:19:35.504425 NOTICE: BL31: BL33 decompress pass
422 07:19:35.510071 ERROR: Error initializing runtime service opteed_fast
423 07:19:36.743024
424 07:19:36.743632
425 07:19:37.024164 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
426 07:19:37.024755
427 07:19:37.025190 Model: Libre Computer AML-A311D-CC Alta
428 07:19:37.025604 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
429 07:19:37.027215 DRAM: 2 GiB (effective 3.8 GiB)
430 07:19:37.126187 Core: 408 devices, 31 uclasses, devicetree: separate
431 07:19:37.132065 WDT: Not starting watchdog@f0d0
432 07:19:37.164310 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
433 07:19:37.176758 Loading Environment from FAT... Card did not respond to voltage select! : -110
434 07:19:37.181829 ** Bad device specification mmc 0 **
435 07:19:37.192065 Card did not respond to voltage select! : -110
436 07:19:37.199707 ** Bad device specification mmc 0 **
437 07:19:37.200189 Couldn't find partition mmc 0
438 07:19:37.208072 Card did not respond to voltage select! : -110
439 07:19:37.213626 ** Bad device specification mmc 0 **
440 07:19:37.214082 Couldn't find partition mmc 0
441 07:19:37.218631 Error: could not access storage.
442 07:19:38.481988 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
443 07:19:38.482620 bl2_stage_init 0x01
444 07:19:38.483057 bl2_stage_init 0x81
445 07:19:38.487367 hw id: 0x0000 - pwm id 0x01
446 07:19:38.487824 bl2_stage_init 0xc1
447 07:19:38.488291 bl2_stage_init 0x02
448 07:19:38.488701
449 07:19:38.493020 L0:00000000
450 07:19:38.493462 L1:20000703
451 07:19:38.493876 L2:00008067
452 07:19:38.494279 L3:14000000
453 07:19:38.498555 B2:00402000
454 07:19:38.499002 B1:e0f83180
455 07:19:38.499411
456 07:19:38.499819 TE: 58124
457 07:19:38.500270
458 07:19:38.504166 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
459 07:19:38.504609
460 07:19:38.505020 Board ID = 1
461 07:19:38.509884 Set A53 clk to 24M
462 07:19:38.510329 Set A73 clk to 24M
463 07:19:38.510736 Set clk81 to 24M
464 07:19:38.515440 A53 clk: 1200 MHz
465 07:19:38.515876 A73 clk: 1200 MHz
466 07:19:38.516318 CLK81: 166.6M
467 07:19:38.516721 smccc: 00012a92
468 07:19:38.520961 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
469 07:19:38.526546 board id: 1
470 07:19:38.532419 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
471 07:19:38.543113 fw parse done
472 07:19:38.549087 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
473 07:19:38.591673 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
474 07:19:38.602543 PIEI prepare done
475 07:19:38.602993 fastboot data load
476 07:19:38.603408 fastboot data verify
477 07:19:38.608190 verify result: 266
478 07:19:38.613973 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
479 07:19:38.614405 LPDDR4 probe
480 07:19:38.614814 ddr clk to 1584MHz
481 07:19:38.621941 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
482 07:19:38.659181
483 07:19:38.659698 dmc_version 0001
484 07:19:38.665813 Check phy result
485 07:19:38.671723 INFO : End of CA training
486 07:19:38.672231 INFO : End of initialization
487 07:19:38.677358 INFO : Training has run successfully!
488 07:19:38.677828 Check phy result
489 07:19:38.682951 INFO : End of initialization
490 07:19:38.683415 INFO : End of read enable training
491 07:19:38.688521 INFO : End of fine write leveling
492 07:19:38.694135 INFO : End of Write leveling coarse delay
493 07:19:38.694603 INFO : Training has run successfully!
494 07:19:38.695014 Check phy result
495 07:19:38.699753 INFO : End of initialization
496 07:19:38.700263 INFO : End of read dq deskew training
497 07:19:38.705355 INFO : End of MPR read delay center optimization
498 07:19:38.710942 INFO : End of write delay center optimization
499 07:19:38.716526 INFO : End of read delay center optimization
500 07:19:38.716994 INFO : End of max read latency training
501 07:19:38.722124 INFO : Training has run successfully!
502 07:19:38.722589 1D training succeed
503 07:19:38.731277 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
504 07:19:38.778949 Check phy result
505 07:19:38.779531 INFO : End of initialization
506 07:19:38.801375 INFO : End of 2D read delay Voltage center optimization
507 07:19:38.821404 INFO : End of 2D read delay Voltage center optimization
508 07:19:38.873311 INFO : End of 2D write delay Voltage center optimization
509 07:19:38.922518 INFO : End of 2D write delay Voltage center optimization
510 07:19:38.928095 INFO : Training has run successfully!
511 07:19:38.928530
512 07:19:38.928941 channel==0
513 07:19:38.933719 RxClkDly_Margin_A0==88 ps 9
514 07:19:38.934183 TxDqDly_Margin_A0==98 ps 10
515 07:19:38.939302 RxClkDly_Margin_A1==88 ps 9
516 07:19:38.939757 TxDqDly_Margin_A1==98 ps 10
517 07:19:38.940218 TrainedVREFDQ_A0==74
518 07:19:38.944895 TrainedVREFDQ_A1==74
519 07:19:38.945348 VrefDac_Margin_A0==25
520 07:19:38.945758 DeviceVref_Margin_A0==40
521 07:19:38.950509 VrefDac_Margin_A1==25
522 07:19:38.950950 DeviceVref_Margin_A1==40
523 07:19:38.951356
524 07:19:38.951757
525 07:19:38.956127 channel==1
526 07:19:38.956602 RxClkDly_Margin_A0==98 ps 10
527 07:19:38.957016 TxDqDly_Margin_A0==98 ps 10
528 07:19:38.961698 RxClkDly_Margin_A1==88 ps 9
529 07:19:38.962133 TxDqDly_Margin_A1==88 ps 9
530 07:19:38.967272 TrainedVREFDQ_A0==77
531 07:19:38.967724 TrainedVREFDQ_A1==77
532 07:19:38.968161 VrefDac_Margin_A0==22
533 07:19:38.972895 DeviceVref_Margin_A0==37
534 07:19:38.973326 VrefDac_Margin_A1==24
535 07:19:38.978493 DeviceVref_Margin_A1==37
536 07:19:38.978925
537 07:19:38.979330 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
538 07:19:38.979729
539 07:19:39.012108 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000018 00000019 00000017 00000019 00000018 00000019 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
540 07:19:39.012581 2D training succeed
541 07:19:39.017692 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
542 07:19:39.023277 auto size-- 65535DDR cs0 size: 2048MB
543 07:19:39.023714 DDR cs1 size: 2048MB
544 07:19:39.028896 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
545 07:19:39.029330 cs0 DataBus test pass
546 07:19:39.034490 cs1 DataBus test pass
547 07:19:39.034930 cs0 AddrBus test pass
548 07:19:39.035337 cs1 AddrBus test pass
549 07:19:39.035738
550 07:19:39.040102 100bdlr_step_size ps== 420
551 07:19:39.040550 result report
552 07:19:39.045699 boot times 0Enable ddr reg access
553 07:19:39.051110 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
554 07:19:39.064499 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
555 07:19:39.636490 0.0;M3 CHK:0;cm4_sp_mode 0
556 07:19:39.637063 MVN_1=0x00000000
557 07:19:39.642107 MVN_2=0x00000000
558 07:19:39.647776 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
559 07:19:39.648340 OPS=0x10
560 07:19:39.648782 ring efuse init
561 07:19:39.649171 chipver efuse init
562 07:19:39.653367 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
563 07:19:39.659069 [0.018961 Inits done]
564 07:19:39.659538 secure task start!
565 07:19:39.659931 high task start!
566 07:19:39.663499 low task start!
567 07:19:39.663915 run into bl31
568 07:19:39.670179 NOTICE: BL31: v1.3(release):4fc40b1
569 07:19:39.678000 NOTICE: BL31: Built : 15:58:17, May 22 2019
570 07:19:39.678429 NOTICE: BL31: G12A normal boot!
571 07:19:39.703326 NOTICE: BL31: BL33 decompress pass
572 07:19:39.709004 ERROR: Error initializing runtime service opteed_fast
573 07:19:40.942131
574 07:19:40.942756
575 07:19:40.950559 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
576 07:19:40.951016
577 07:19:40.951437 Model: Libre Computer AML-A311D-CC Alta
578 07:19:41.158893 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
579 07:19:41.182362 DRAM: 2 GiB (effective 3.8 GiB)
580 07:19:41.325171 Core: 408 devices, 31 uclasses, devicetree: separate
581 07:19:41.331184 WDT: Not starting watchdog@f0d0
582 07:19:41.363536 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
583 07:19:41.375776 Loading Environment from FAT... Card did not respond to voltage select! : -110
584 07:19:41.380801 ** Bad device specification mmc 0 **
585 07:19:41.391084 Card did not respond to voltage select! : -110
586 07:19:41.398784 ** Bad device specification mmc 0 **
587 07:19:41.399225 Couldn't find partition mmc 0
588 07:19:41.407171 Card did not respond to voltage select! : -110
589 07:19:41.412590 ** Bad device specification mmc 0 **
590 07:19:41.413032 Couldn't find partition mmc 0
591 07:19:41.417790 Error: could not access storage.
592 07:19:41.760280 Net: eth0: ethernet@ff3f0000
593 07:19:41.760877 starting USB...
594 07:19:42.011919 Bus usb@ff500000: Register 3000140 NbrPorts 3
595 07:19:42.012529 Starting the controller
596 07:19:42.019020 USB XHCI 1.10
597 07:19:43.732156 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
598 07:19:43.732562 bl2_stage_init 0x01
599 07:19:43.732789 bl2_stage_init 0x81
600 07:19:43.737750 hw id: 0x0000 - pwm id 0x01
601 07:19:43.738120 bl2_stage_init 0xc1
602 07:19:43.738432 bl2_stage_init 0x02
603 07:19:43.738736
604 07:19:43.743292 L0:00000000
605 07:19:43.743643 L1:20000703
606 07:19:43.743873 L2:00008067
607 07:19:43.744117 L3:14000000
608 07:19:43.748935 B2:00402000
609 07:19:43.749198 B1:e0f83180
610 07:19:43.749406
611 07:19:43.749610 TE: 58124
612 07:19:43.749811
613 07:19:43.754512 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
614 07:19:43.754876
615 07:19:43.755194 Board ID = 1
616 07:19:43.760140 Set A53 clk to 24M
617 07:19:43.760521 Set A73 clk to 24M
618 07:19:43.760847 Set clk81 to 24M
619 07:19:43.765825 A53 clk: 1200 MHz
620 07:19:43.766208 A73 clk: 1200 MHz
621 07:19:43.766536 CLK81: 166.6M
622 07:19:43.766845 smccc: 00012a92
623 07:19:43.771277 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
624 07:19:43.776951 board id: 1
625 07:19:43.782889 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
626 07:19:43.793465 fw parse done
627 07:19:43.799506 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
628 07:19:43.841924 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
629 07:19:43.852807 PIEI prepare done
630 07:19:43.853101 fastboot data load
631 07:19:43.853319 fastboot data verify
632 07:19:43.858493 verify result: 266
633 07:19:43.864109 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
634 07:19:43.864518 LPDDR4 probe
635 07:19:43.864849 ddr clk to 1584MHz
636 07:19:43.872146 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
637 07:19:43.909308
638 07:19:43.909786 dmc_version 0001
639 07:19:43.916019 Check phy result
640 07:19:43.921873 INFO : End of CA training
641 07:19:43.922322 INFO : End of initialization
642 07:19:43.927464 INFO : Training has run successfully!
643 07:19:43.927912 Check phy result
644 07:19:43.933080 INFO : End of initialization
645 07:19:43.933524 INFO : End of read enable training
646 07:19:43.938706 INFO : End of fine write leveling
647 07:19:43.944281 INFO : End of Write leveling coarse delay
648 07:19:43.944729 INFO : Training has run successfully!
649 07:19:43.945142 Check phy result
650 07:19:43.949863 INFO : End of initialization
651 07:19:43.950308 INFO : End of read dq deskew training
652 07:19:43.955472 INFO : End of MPR read delay center optimization
653 07:19:43.961084 INFO : End of write delay center optimization
654 07:19:43.966708 INFO : End of read delay center optimization
655 07:19:43.967157 INFO : End of max read latency training
656 07:19:43.972272 INFO : Training has run successfully!
657 07:19:43.972725 1D training succeed
658 07:19:43.981439 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
659 07:19:44.029021 Check phy result
660 07:19:44.029477 INFO : End of initialization
661 07:19:44.050856 INFO : End of 2D read delay Voltage center optimization
662 07:19:44.071056 INFO : End of 2D read delay Voltage center optimization
663 07:19:44.123095 INFO : End of 2D write delay Voltage center optimization
664 07:19:44.172480 INFO : End of 2D write delay Voltage center optimization
665 07:19:44.178011 INFO : Training has run successfully!
666 07:19:44.178486
667 07:19:44.178912 channel==0
668 07:19:44.183619 RxClkDly_Margin_A0==88 ps 9
669 07:19:44.184140 TxDqDly_Margin_A0==98 ps 10
670 07:19:44.189242 RxClkDly_Margin_A1==88 ps 9
671 07:19:44.189709 TxDqDly_Margin_A1==98 ps 10
672 07:19:44.190137 TrainedVREFDQ_A0==74
673 07:19:44.194840 TrainedVREFDQ_A1==74
674 07:19:44.195348 VrefDac_Margin_A0==25
675 07:19:44.195775 DeviceVref_Margin_A0==40
676 07:19:44.200471 VrefDac_Margin_A1==25
677 07:19:44.200936 DeviceVref_Margin_A1==40
678 07:19:44.201347
679 07:19:44.201764
680 07:19:44.206024 channel==1
681 07:19:44.206514 RxClkDly_Margin_A0==98 ps 10
682 07:19:44.206940 TxDqDly_Margin_A0==88 ps 9
683 07:19:44.211618 RxClkDly_Margin_A1==98 ps 10
684 07:19:44.212110 TxDqDly_Margin_A1==88 ps 9
685 07:19:44.217198 TrainedVREFDQ_A0==77
686 07:19:44.217659 TrainedVREFDQ_A1==77
687 07:19:44.218079 VrefDac_Margin_A0==22
688 07:19:44.222787 DeviceVref_Margin_A0==37
689 07:19:44.223240 VrefDac_Margin_A1==22
690 07:19:44.228401 DeviceVref_Margin_A1==37
691 07:19:44.228852
692 07:19:44.229264 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
693 07:19:44.229672
694 07:19:44.261998 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000019 00000018 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
695 07:19:44.262488 2D training succeed
696 07:19:44.267619 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
697 07:19:44.273191 auto size-- 65535DDR cs0 size: 2048MB
698 07:19:44.273654 DDR cs1 size: 2048MB
699 07:19:44.278792 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
700 07:19:44.279250 cs0 DataBus test pass
701 07:19:44.284401 cs1 DataBus test pass
702 07:19:44.284865 cs0 AddrBus test pass
703 07:19:44.285284 cs1 AddrBus test pass
704 07:19:44.285693
705 07:19:44.289983 100bdlr_step_size ps== 420
706 07:19:44.290444 result report
707 07:19:44.295602 boot times 0Enable ddr reg access
708 07:19:44.300952 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
709 07:19:44.314432 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
710 07:19:44.888118 0.0;M3 CHK:0;cm4_sp_mode 0
711 07:19:44.888669 MVN_1=0x00000000
712 07:19:44.893725 MVN_2=0x00000000
713 07:19:44.899440 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
714 07:19:44.899975 OPS=0x10
715 07:19:44.900443 ring efuse init
716 07:19:44.900835 chipver efuse init
717 07:19:44.904990 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
718 07:19:44.910605 [0.018961 Inits done]
719 07:19:44.911091 secure task start!
720 07:19:44.911483 high task start!
721 07:19:44.915175 low task start!
722 07:19:44.915614 run into bl31
723 07:19:44.921828 NOTICE: BL31: v1.3(release):4fc40b1
724 07:19:44.929608 NOTICE: BL31: Built : 15:58:17, May 22 2019
725 07:19:44.930078 NOTICE: BL31: G12A normal boot!
726 07:19:44.955009 NOTICE: BL31: BL33 decompress pass
727 07:19:44.960650 ERROR: Error initializing runtime service opteed_fast
728 07:19:46.193630
729 07:19:46.194260
730 07:19:46.201898 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
731 07:19:46.202365
732 07:19:46.202785 Model: Libre Computer AML-A311D-CC Alta
733 07:19:46.410254 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
734 07:19:46.433684 DRAM: 2 GiB (effective 3.8 GiB)
735 07:19:46.576655 Core: 408 devices, 31 uclasses, devicetree: separate
736 07:19:46.582563 WDT: Not starting watchdog@f0d0
737 07:19:46.614815 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
738 07:19:46.627291 Loading Environment from FAT... Card did not respond to voltage select! : -110
739 07:19:46.632276 ** Bad device specification mmc 0 **
740 07:19:46.642600 Card did not respond to voltage select! : -110
741 07:19:46.650256 ** Bad device specification mmc 0 **
742 07:19:46.650705 Couldn't find partition mmc 0
743 07:19:46.658585 Card did not respond to voltage select! : -110
744 07:19:46.664139 ** Bad device specification mmc 0 **
745 07:19:46.664599 Couldn't find partition mmc 0
746 07:19:46.669188 Error: could not access storage.
747 07:19:47.012670 Net: eth0: ethernet@ff3f0000
748 07:19:47.013178 starting USB...
749 07:19:47.264503 Bus usb@ff500000: Register 3000140 NbrPorts 3
750 07:19:47.265051 Starting the controller
751 07:19:47.271440 USB XHCI 1.10
752 07:19:49.433837 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
753 07:19:49.434414 bl2_stage_init 0x01
754 07:19:49.434846 bl2_stage_init 0x81
755 07:19:49.439310 hw id: 0x0000 - pwm id 0x01
756 07:19:49.439766 bl2_stage_init 0xc1
757 07:19:49.440277 bl2_stage_init 0x02
758 07:19:49.440698
759 07:19:49.444953 L0:00000000
760 07:19:49.445404 L1:20000703
761 07:19:49.445814 L2:00008067
762 07:19:49.446216 L3:14000000
763 07:19:49.450577 B2:00402000
764 07:19:49.451019 B1:e0f83180
765 07:19:49.451429
766 07:19:49.451835 TE: 58159
767 07:19:49.452276
768 07:19:49.456174 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
769 07:19:49.456634
770 07:19:49.457047 Board ID = 1
771 07:19:49.461759 Set A53 clk to 24M
772 07:19:49.462203 Set A73 clk to 24M
773 07:19:49.462613 Set clk81 to 24M
774 07:19:49.467398 A53 clk: 1200 MHz
775 07:19:49.467838 A73 clk: 1200 MHz
776 07:19:49.468276 CLK81: 166.6M
777 07:19:49.468678 smccc: 00012ab4
778 07:19:49.472883 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
779 07:19:49.478554 board id: 1
780 07:19:49.484472 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
781 07:19:49.495102 fw parse done
782 07:19:49.501093 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
783 07:19:49.543809 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
784 07:19:49.554726 PIEI prepare done
785 07:19:49.555290 fastboot data load
786 07:19:49.555784 fastboot data verify
787 07:19:49.560299 verify result: 266
788 07:19:49.565842 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
789 07:19:49.566379 LPDDR4 probe
790 07:19:49.566847 ddr clk to 1584MHz
791 07:19:49.573831 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
792 07:19:49.611116
793 07:19:49.611687 dmc_version 0001
794 07:19:49.617794 Check phy result
795 07:19:49.623628 INFO : End of CA training
796 07:19:49.624200 INFO : End of initialization
797 07:19:49.629252 INFO : Training has run successfully!
798 07:19:49.629796 Check phy result
799 07:19:49.634853 INFO : End of initialization
800 07:19:49.635396 INFO : End of read enable training
801 07:19:49.638162 INFO : End of fine write leveling
802 07:19:49.643770 INFO : End of Write leveling coarse delay
803 07:19:49.649377 INFO : Training has run successfully!
804 07:19:49.649922 Check phy result
805 07:19:49.650391 INFO : End of initialization
806 07:19:49.654973 INFO : End of read dq deskew training
807 07:19:49.660644 INFO : End of MPR read delay center optimization
808 07:19:49.661190 INFO : End of write delay center optimization
809 07:19:49.666155 INFO : End of read delay center optimization
810 07:19:49.671806 INFO : End of max read latency training
811 07:19:49.672380 INFO : Training has run successfully!
812 07:19:49.677338 1D training succeed
813 07:19:49.683249 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
814 07:19:49.730831 Check phy result
815 07:19:49.731377 INFO : End of initialization
816 07:19:49.753432 INFO : End of 2D read delay Voltage center optimization
817 07:19:49.773651 INFO : End of 2D read delay Voltage center optimization
818 07:19:49.825722 INFO : End of 2D write delay Voltage center optimization
819 07:19:49.875180 INFO : End of 2D write delay Voltage center optimization
820 07:19:49.882824 INFO : Training has run successfully!
821 07:19:49.883457
822 07:19:49.883935 channel==0
823 07:19:49.884647 RxClkDly_Margin_A0==88 ps 9
824 07:19:49.888391 TxDqDly_Margin_A0==98 ps 10
825 07:19:49.888969 RxClkDly_Margin_A1==88 ps 9
826 07:19:49.893993 TxDqDly_Margin_A1==98 ps 10
827 07:19:49.894592 TrainedVREFDQ_A0==74
828 07:19:49.895111 TrainedVREFDQ_A1==74
829 07:19:49.899491 VrefDac_Margin_A0==24
830 07:19:49.900205 DeviceVref_Margin_A0==40
831 07:19:49.900674 VrefDac_Margin_A1==25
832 07:19:49.905737 DeviceVref_Margin_A1==40
833 07:19:49.906289
834 07:19:49.906741
835 07:19:49.907185 channel==1
836 07:19:49.911186 RxClkDly_Margin_A0==98 ps 10
837 07:19:49.911721 TxDqDly_Margin_A0==98 ps 10
838 07:19:49.912210 RxClkDly_Margin_A1==88 ps 9
839 07:19:49.916938 TxDqDly_Margin_A1==88 ps 9
840 07:19:49.917480 TrainedVREFDQ_A0==77
841 07:19:49.920350 TrainedVREFDQ_A1==77
842 07:19:49.920882 VrefDac_Margin_A0==22
843 07:19:49.925909 DeviceVref_Margin_A0==37
844 07:19:49.926438 VrefDac_Margin_A1==24
845 07:19:49.926877 DeviceVref_Margin_A1==37
846 07:19:49.927302
847 07:19:49.931471 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
848 07:19:49.932029
849 07:19:49.962928 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000019 00000018 00000018 00000016 00000018 00000015 00000017 00000018 00000017 00000019 00000018 00000019 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
850 07:19:49.963503 2D training succeed
851 07:19:49.974013 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
852 07:19:49.974554 auto size-- 65535DDR cs0 size: 2048MB
853 07:19:49.979671 DDR cs1 size: 2048MB
854 07:19:49.980237 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
855 07:19:49.985255 cs0 DataBus test pass
856 07:19:49.985778 cs1 DataBus test pass
857 07:19:49.986215 cs0 AddrBus test pass
858 07:19:49.990849 cs1 AddrBus test pass
859 07:19:49.991372
860 07:19:49.991809 100bdlr_step_size ps== 420
861 07:19:49.992299 result report
862 07:19:49.996508 boot times 0Enable ddr reg access
863 07:19:50.003468 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
864 07:19:50.016925 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
865 07:19:50.590575 0.0;M3 CHK:0;cm4_sp_mode 0
866 07:19:50.591211 MVN_1=0x00000000
867 07:19:50.596116 MVN_2=0x00000000
868 07:19:50.601867 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
869 07:19:50.602410 OPS=0x10
870 07:19:50.602882 ring efuse init
871 07:19:50.603340 chipver efuse init
872 07:19:50.607511 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
873 07:19:50.613055 [0.018961 Inits done]
874 07:19:50.613582 secure task start!
875 07:19:50.614042 high task start!
876 07:19:50.617722 low task start!
877 07:19:50.618255 run into bl31
878 07:19:50.624250 NOTICE: BL31: v1.3(release):4fc40b1
879 07:19:50.632083 NOTICE: BL31: Built : 15:58:17, May 22 2019
880 07:19:50.632631 NOTICE: BL31: G12A normal boot!
881 07:19:50.657425 NOTICE: BL31: BL33 decompress pass
882 07:19:50.663116 ERROR: Error initializing runtime service opteed_fast
883 07:19:51.895933
884 07:19:51.896621
885 07:19:51.904371 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
886 07:19:51.904916
887 07:19:51.905388 Model: Libre Computer AML-A311D-CC Alta
888 07:19:52.112759 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
889 07:19:52.136226 DRAM: 2 GiB (effective 3.8 GiB)
890 07:19:52.279108 Core: 408 devices, 31 uclasses, devicetree: separate
891 07:19:52.285023 WDT: Not starting watchdog@f0d0
892 07:19:52.317255 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
893 07:19:52.329699 Loading Environment from FAT... Card did not respond to voltage select! : -110
894 07:19:52.334725 ** Bad device specification mmc 0 **
895 07:19:52.345048 Card did not respond to voltage select! : -110
896 07:19:52.352709 ** Bad device specification mmc 0 **
897 07:19:52.353232 Couldn't find partition mmc 0
898 07:19:52.361037 Card did not respond to voltage select! : -110
899 07:19:52.366543 ** Bad device specification mmc 0 **
900 07:19:52.367068 Couldn't find partition mmc 0
901 07:19:52.371617 Error: could not access storage.
902 07:19:52.715075 Net: eth0: ethernet@ff3f0000
903 07:19:52.715681 starting USB...
904 07:19:52.967024 Bus usb@ff500000: Register 3000140 NbrPorts 3
905 07:19:52.967589 Starting the controller
906 07:19:52.973928 USB XHCI 1.10
907 07:19:54.833508 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
908 07:19:54.834132 bl2_stage_init 0x01
909 07:19:54.834611 bl2_stage_init 0x81
910 07:19:54.839243 hw id: 0x0000 - pwm id 0x01
911 07:19:54.839769 bl2_stage_init 0xc1
912 07:19:54.840291 bl2_stage_init 0x02
913 07:19:54.840755
914 07:19:54.844735 L0:00000000
915 07:19:54.845253 L1:20000703
916 07:19:54.845711 L2:00008067
917 07:19:54.846159 L3:14000000
918 07:19:54.850341 B2:00402000
919 07:19:54.850854 B1:e0f83180
920 07:19:54.851305
921 07:19:54.851754 TE: 58124
922 07:19:54.852248
923 07:19:54.855935 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
924 07:19:54.856502
925 07:19:54.856971 Board ID = 1
926 07:19:54.861513 Set A53 clk to 24M
927 07:19:54.862027 Set A73 clk to 24M
928 07:19:54.862480 Set clk81 to 24M
929 07:19:54.867217 A53 clk: 1200 MHz
930 07:19:54.867729 A73 clk: 1200 MHz
931 07:19:54.868231 CLK81: 166.6M
932 07:19:54.868680 smccc: 00012a91
933 07:19:54.872721 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
934 07:19:54.878307 board id: 1
935 07:19:54.884296 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
936 07:19:54.894858 fw parse done
937 07:19:54.900859 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
938 07:19:54.943444 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
939 07:19:54.954305 PIEI prepare done
940 07:19:54.954814 fastboot data load
941 07:19:54.955257 fastboot data verify
942 07:19:54.960003 verify result: 266
943 07:19:54.965628 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
944 07:19:54.966137 LPDDR4 probe
945 07:19:54.966570 ddr clk to 1584MHz
946 07:19:54.973695 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
947 07:19:55.010962
948 07:19:55.011483 dmc_version 0001
949 07:19:55.017737 Check phy result
950 07:19:55.023482 INFO : End of CA training
951 07:19:55.024035 INFO : End of initialization
952 07:19:55.029145 INFO : Training has run successfully!
953 07:19:55.029659 Check phy result
954 07:19:55.034831 INFO : End of initialization
955 07:19:55.035405 INFO : End of read enable training
956 07:19:55.040596 INFO : End of fine write leveling
957 07:19:55.045984 INFO : End of Write leveling coarse delay
958 07:19:55.046514 INFO : Training has run successfully!
959 07:19:55.046980 Check phy result
960 07:19:55.051528 INFO : End of initialization
961 07:19:55.052102 INFO : End of read dq deskew training
962 07:19:55.057189 INFO : End of MPR read delay center optimization
963 07:19:55.062794 INFO : End of write delay center optimization
964 07:19:55.068505 INFO : End of read delay center optimization
965 07:19:55.069023 INFO : End of max read latency training
966 07:19:55.073991 INFO : Training has run successfully!
967 07:19:55.074504 1D training succeed
968 07:19:55.083000 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
969 07:19:55.130582 Check phy result
970 07:19:55.131132 INFO : End of initialization
971 07:19:55.152415 INFO : End of 2D read delay Voltage center optimization
972 07:19:55.172543 INFO : End of 2D read delay Voltage center optimization
973 07:19:55.224646 INFO : End of 2D write delay Voltage center optimization
974 07:19:55.273995 INFO : End of 2D write delay Voltage center optimization
975 07:19:55.279548 INFO : Training has run successfully!
976 07:19:55.280133
977 07:19:55.280612 channel==0
978 07:19:55.285150 RxClkDly_Margin_A0==88 ps 9
979 07:19:55.285682 TxDqDly_Margin_A0==98 ps 10
980 07:19:55.290764 RxClkDly_Margin_A1==88 ps 9
981 07:19:55.291297 TxDqDly_Margin_A1==98 ps 10
982 07:19:55.291766 TrainedVREFDQ_A0==74
983 07:19:55.296435 TrainedVREFDQ_A1==74
984 07:19:55.296978 VrefDac_Margin_A0==25
985 07:19:55.297448 DeviceVref_Margin_A0==40
986 07:19:55.301959 VrefDac_Margin_A1==25
987 07:19:55.302477 DeviceVref_Margin_A1==40
988 07:19:55.302938
989 07:19:55.303392
990 07:19:55.307554 channel==1
991 07:19:55.308106 RxClkDly_Margin_A0==98 ps 10
992 07:19:55.308569 TxDqDly_Margin_A0==98 ps 10
993 07:19:55.313154 RxClkDly_Margin_A1==98 ps 10
994 07:19:55.313671 TxDqDly_Margin_A1==88 ps 9
995 07:19:55.318754 TrainedVREFDQ_A0==77
996 07:19:55.319276 TrainedVREFDQ_A1==77
997 07:19:55.319738 VrefDac_Margin_A0==22
998 07:19:55.324381 DeviceVref_Margin_A0==37
999 07:19:55.324893 VrefDac_Margin_A1==22
1000 07:19:55.329935 DeviceVref_Margin_A1==37
1001 07:19:55.330451
1002 07:19:55.330904 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
1003 07:19:55.335531
1004 07:19:55.363528 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000017 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
1005 07:19:55.364111 2D training succeed
1006 07:19:55.369173 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
1007 07:19:55.374766 auto size-- 65535DDR cs0 size: 2048MB
1008 07:19:55.375284 DDR cs1 size: 2048MB
1009 07:19:55.380386 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
1010 07:19:55.380900 cs0 DataBus test pass
1011 07:19:55.385977 cs1 DataBus test pass
1012 07:19:55.386489 cs0 AddrBus test pass
1013 07:19:55.386941 cs1 AddrBus test pass
1014 07:19:55.387385
1015 07:19:55.391665 100bdlr_step_size ps== 420
1016 07:19:55.392295 result report
1017 07:19:55.397091 boot times 0Enable ddr reg access
1018 07:19:55.402491 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
1019 07:19:55.416035 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
1020 07:19:55.989616 0.0;M3 CHK:0;cm4_sp_mode 0
1021 07:19:55.990234 MVN_1=0x00000000
1022 07:19:55.995085 MVN_2=0x00000000
1023 07:19:56.000849 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
1024 07:19:56.001324 OPS=0x10
1025 07:19:56.001753 ring efuse init
1026 07:19:56.002166 chipver efuse init
1027 07:19:56.006437 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
1028 07:19:56.012082 [0.018961 Inits done]
1029 07:19:56.012551 secure task start!
1030 07:19:56.012969 high task start!
1031 07:19:56.016628 low task start!
1032 07:19:56.017092 run into bl31
1033 07:19:56.023306 NOTICE: BL31: v1.3(release):4fc40b1
1034 07:19:56.031086 NOTICE: BL31: Built : 15:58:17, May 22 2019
1035 07:19:56.031550 NOTICE: BL31: G12A normal boot!
1036 07:19:56.056460 NOTICE: BL31: BL33 decompress pass
1037 07:19:56.062125 ERROR: Error initializing runtime service opteed_fast
1038 07:19:57.295061
1039 07:19:57.295655
1040 07:19:57.303565 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
1041 07:19:57.304068
1042 07:19:57.304500 Model: Libre Computer AML-A311D-CC Alta
1043 07:19:57.511892 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
1044 07:19:57.535277 DRAM: 2 GiB (effective 3.8 GiB)
1045 07:19:57.678299 Core: 408 devices, 31 uclasses, devicetree: separate
1046 07:19:57.684162 WDT: Not starting watchdog@f0d0
1047 07:19:57.716408 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
1048 07:19:57.728880 Loading Environment from FAT... Card did not respond to voltage select! : -110
1049 07:19:57.733871 ** Bad device specification mmc 0 **
1050 07:19:57.744212 Card did not respond to voltage select! : -110
1051 07:19:57.751865 ** Bad device specification mmc 0 **
1052 07:19:57.752376 Couldn't find partition mmc 0
1053 07:19:57.760194 Card did not respond to voltage select! : -110
1054 07:19:57.765720 ** Bad device specification mmc 0 **
1055 07:19:57.766178 Couldn't find partition mmc 0
1056 07:19:57.770794 Error: could not access storage.
1057 07:19:58.113235 Net: eth0: ethernet@ff3f0000
1058 07:19:58.113783 starting USB...
1059 07:19:58.364980 Bus usb@ff500000: Register 3000140 NbrPorts 3
1060 07:19:58.365517 Starting the controller
1061 07:19:58.372042 USB XHCI 1.10
1062 07:19:59.929147 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
1063 07:19:59.937490 scanning usb for storage devices... 0 Storage Device(s) found
1065 07:19:59.989067 Hit any key to stop autoboot: 1
1066 07:19:59.989812 end: 2.4.2 bootloader-interrupt (duration 00:00:37) [common]
1067 07:19:59.990387 start: 2.4.3 bootloader-commands (timeout 00:04:23) [common]
1068 07:19:59.990838 Setting prompt string to ['=>']
1069 07:19:59.991296 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:23)
1070 07:20:00.004947 0
1071 07:20:00.005798 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1072 07:20:00.006294 Sending with 10 millisecond of delay
1074 07:20:01.140923 => setenv autoload no
1075 07:20:01.151660 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:22)
1076 07:20:01.156476 setenv autoload no
1077 07:20:01.157233 Sending with 10 millisecond of delay
1079 07:20:02.953825 => setenv initrd_high 0xffffffff
1080 07:20:02.964563 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:20)
1081 07:20:02.965398 setenv initrd_high 0xffffffff
1082 07:20:02.966126 Sending with 10 millisecond of delay
1084 07:20:04.582396 => setenv fdt_high 0xffffffff
1085 07:20:04.593186 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1086 07:20:04.594026 setenv fdt_high 0xffffffff
1087 07:20:04.594757 Sending with 10 millisecond of delay
1089 07:20:04.886570 => dhcp
1090 07:20:04.897304 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1091 07:20:04.898121 dhcp
1092 07:20:04.898573 Speed: 1000, full duplex
1093 07:20:04.898987 BOOTP broadcast 1
1094 07:20:04.909747 DHCP client bound to address 192.168.6.27 (13 ms)
1095 07:20:04.910473 Sending with 10 millisecond of delay
1097 07:20:06.588150 => setenv serverip 192.168.6.2
1098 07:20:06.598890 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:16)
1099 07:20:06.599463 setenv serverip 192.168.6.2
1100 07:20:06.599926 Sending with 10 millisecond of delay
1102 07:20:10.325955 => tftpboot 0x01080000 933026/tftp-deploy-2pddd2tu/kernel/uImage
1103 07:20:10.336797 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:12)
1104 07:20:10.337727 tftpboot 0x01080000 933026/tftp-deploy-2pddd2tu/kernel/uImage
1105 07:20:10.338209 Speed: 1000, full duplex
1106 07:20:10.338638 Using ethernet@ff3f0000 device
1107 07:20:10.339384 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1108 07:20:10.344830 Filename '933026/tftp-deploy-2pddd2tu/kernel/uImage'.
1109 07:20:10.348599 Load address: 0x1080000
1110 07:20:13.255391 Loading: *################################################## 43.9 MiB
1111 07:20:13.255811 15.1 MiB/s
1112 07:20:13.256098 done
1113 07:20:13.259848 Bytes transferred = 46041664 (2be8a40 hex)
1114 07:20:13.260377 Sending with 10 millisecond of delay
1116 07:20:17.945877 => tftpboot 0x08000000 933026/tftp-deploy-2pddd2tu/ramdisk/ramdisk.cpio.gz.uboot
1117 07:20:17.956627 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:05)
1118 07:20:17.957151 tftpboot 0x08000000 933026/tftp-deploy-2pddd2tu/ramdisk/ramdisk.cpio.gz.uboot
1119 07:20:17.957377 Speed: 1000, full duplex
1120 07:20:17.957579 Using ethernet@ff3f0000 device
1121 07:20:17.959320 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1122 07:20:17.967878 Filename '933026/tftp-deploy-2pddd2tu/ramdisk/ramdisk.cpio.gz.uboot'.
1123 07:20:17.968351 Load address: 0x8000000
1124 07:20:24.853109 Loading: *###################T ############################## UDP wrong checksum 00000005 00007c40
1125 07:20:29.853976 T UDP wrong checksum 00000005 00007c40
1126 07:20:39.857146 T T UDP wrong checksum 00000005 00007c40
1127 07:20:59.861074 T T T T UDP wrong checksum 00000005 00007c40
1128 07:21:14.865198 T T
1129 07:21:14.865632 Retry count exceeded; starting again
1131 07:21:14.868611 end: 2.4.3 bootloader-commands (duration 00:01:15) [common]
1134 07:21:14.869582 end: 2.4 uboot-commands (duration 00:01:52) [common]
1136 07:21:14.870314 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
1138 07:21:14.870900 end: 2 uboot-action (duration 00:01:52) [common]
1140 07:21:14.871744 Cleaning after the job
1141 07:21:14.872110 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/933026/tftp-deploy-2pddd2tu/ramdisk
1142 07:21:14.872830 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/933026/tftp-deploy-2pddd2tu/kernel
1143 07:21:14.900353 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/933026/tftp-deploy-2pddd2tu/dtb
1144 07:21:14.901637 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/933026/tftp-deploy-2pddd2tu/modules
1145 07:21:14.926080 start: 4.1 power-off (timeout 00:00:30) [common]
1146 07:21:14.926908 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1147 07:21:14.961241 >> OK - accepted request
1148 07:21:14.963612 Returned 0 in 0 seconds
1149 07:21:15.064486 end: 4.1 power-off (duration 00:00:00) [common]
1151 07:21:15.065602 start: 4.2 read-feedback (timeout 00:10:00) [common]
1152 07:21:15.066374 Listened to connection for namespace 'common' for up to 1s
1153 07:21:16.066851 Finalising connection for namespace 'common'
1154 07:21:16.067443 Disconnecting from shell: Finalise
1155 07:21:16.068360 =>
1156 07:21:16.169638 end: 4.2 read-feedback (duration 00:00:01) [common]
1157 07:21:16.170190 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/933026
1158 07:21:16.506041 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/933026
1159 07:21:16.506767 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.