Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 07:17:25.564049 lava-dispatcher, installed at version: 2024.01
2 07:17:25.564822 start: 0 validate
3 07:17:25.565299 Start time: 2024-11-04 07:17:25.565268+00:00 (UTC)
4 07:17:25.565850 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 07:17:25.566402 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230703.0%2Farm64%2Frootfs.cpio.gz exists
6 07:17:25.606370 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 07:17:25.606920 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241104%2Farm64%2Fdefconfig%2Bkselftest%2Fgcc-12%2Fkernel%2FImage exists
8 07:17:25.639728 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 07:17:25.640403 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241104%2Farm64%2Fdefconfig%2Bkselftest%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 07:17:25.674546 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 07:17:25.675062 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241104%2Farm64%2Fdefconfig%2Bkselftest%2Fgcc-12%2Fmodules.tar.xz exists
12 07:17:25.716697 validate duration: 0.15
14 07:17:25.717531 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 07:17:25.717854 start: 1.1 download-retry (timeout 00:10:00) [common]
16 07:17:25.718142 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 07:17:25.718713 Not decompressing ramdisk as can be used compressed.
18 07:17:25.719098 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230703.0/arm64/rootfs.cpio.gz
19 07:17:25.719328 saving as /var/lib/lava/dispatcher/tmp/932994/tftp-deploy-s4om3thx/ramdisk/rootfs.cpio.gz
20 07:17:25.719577 total size: 8181887 (7 MB)
21 07:17:25.756888 progress 0 % (0 MB)
22 07:17:25.763031 progress 5 % (0 MB)
23 07:17:25.768526 progress 10 % (0 MB)
24 07:17:25.774322 progress 15 % (1 MB)
25 07:17:25.779853 progress 20 % (1 MB)
26 07:17:25.785747 progress 25 % (1 MB)
27 07:17:25.791009 progress 30 % (2 MB)
28 07:17:25.796713 progress 35 % (2 MB)
29 07:17:25.802091 progress 40 % (3 MB)
30 07:17:25.807834 progress 45 % (3 MB)
31 07:17:25.813186 progress 50 % (3 MB)
32 07:17:25.818848 progress 55 % (4 MB)
33 07:17:25.824160 progress 60 % (4 MB)
34 07:17:25.829994 progress 65 % (5 MB)
35 07:17:25.835302 progress 70 % (5 MB)
36 07:17:25.841014 progress 75 % (5 MB)
37 07:17:25.846536 progress 80 % (6 MB)
38 07:17:25.852576 progress 85 % (6 MB)
39 07:17:25.857946 progress 90 % (7 MB)
40 07:17:25.863778 progress 95 % (7 MB)
41 07:17:25.868745 progress 100 % (7 MB)
42 07:17:25.869428 7 MB downloaded in 0.15 s (52.08 MB/s)
43 07:17:25.869981 end: 1.1.1 http-download (duration 00:00:00) [common]
45 07:17:25.870871 end: 1.1 download-retry (duration 00:00:00) [common]
46 07:17:25.871164 start: 1.2 download-retry (timeout 00:10:00) [common]
47 07:17:25.871435 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 07:17:25.871891 downloading http://storage.kernelci.org/next/master/next-20241104/arm64/defconfig+kselftest/gcc-12/kernel/Image
49 07:17:25.872182 saving as /var/lib/lava/dispatcher/tmp/932994/tftp-deploy-s4om3thx/kernel/Image
50 07:17:25.872393 total size: 66830848 (63 MB)
51 07:17:25.872603 No compression specified
52 07:17:25.906977 progress 0 % (0 MB)
53 07:17:25.947617 progress 5 % (3 MB)
54 07:17:25.987356 progress 10 % (6 MB)
55 07:17:26.027178 progress 15 % (9 MB)
56 07:17:26.067455 progress 20 % (12 MB)
57 07:17:26.107838 progress 25 % (15 MB)
58 07:17:26.148666 progress 30 % (19 MB)
59 07:17:26.189112 progress 35 % (22 MB)
60 07:17:26.229355 progress 40 % (25 MB)
61 07:17:26.269826 progress 45 % (28 MB)
62 07:17:26.309900 progress 50 % (31 MB)
63 07:17:26.350289 progress 55 % (35 MB)
64 07:17:26.390079 progress 60 % (38 MB)
65 07:17:26.431643 progress 65 % (41 MB)
66 07:17:26.472001 progress 70 % (44 MB)
67 07:17:26.511933 progress 75 % (47 MB)
68 07:17:26.552185 progress 80 % (51 MB)
69 07:17:26.592423 progress 85 % (54 MB)
70 07:17:26.632538 progress 90 % (57 MB)
71 07:17:26.672520 progress 95 % (60 MB)
72 07:17:26.712543 progress 100 % (63 MB)
73 07:17:26.713202 63 MB downloaded in 0.84 s (75.80 MB/s)
74 07:17:26.713680 end: 1.2.1 http-download (duration 00:00:01) [common]
76 07:17:26.714502 end: 1.2 download-retry (duration 00:00:01) [common]
77 07:17:26.714776 start: 1.3 download-retry (timeout 00:09:59) [common]
78 07:17:26.715038 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 07:17:26.715491 downloading http://storage.kernelci.org/next/master/next-20241104/arm64/defconfig+kselftest/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
80 07:17:26.715760 saving as /var/lib/lava/dispatcher/tmp/932994/tftp-deploy-s4om3thx/dtb/meson-g12b-a311d-libretech-cc.dtb
81 07:17:26.715968 total size: 54703 (0 MB)
82 07:17:26.716203 No compression specified
83 07:17:26.758797 progress 59 % (0 MB)
84 07:17:26.759646 progress 100 % (0 MB)
85 07:17:26.760258 0 MB downloaded in 0.04 s (1.18 MB/s)
86 07:17:26.760768 end: 1.3.1 http-download (duration 00:00:00) [common]
88 07:17:26.761646 end: 1.3 download-retry (duration 00:00:00) [common]
89 07:17:26.761933 start: 1.4 download-retry (timeout 00:09:59) [common]
90 07:17:26.762219 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 07:17:26.762697 downloading http://storage.kernelci.org/next/master/next-20241104/arm64/defconfig+kselftest/gcc-12/modules.tar.xz
92 07:17:26.762965 saving as /var/lib/lava/dispatcher/tmp/932994/tftp-deploy-s4om3thx/modules/modules.tar
93 07:17:26.763180 total size: 16280944 (15 MB)
94 07:17:26.763403 Using unxz to decompress xz
95 07:17:26.803552 progress 0 % (0 MB)
96 07:17:26.903063 progress 5 % (0 MB)
97 07:17:27.016566 progress 10 % (1 MB)
98 07:17:27.138374 progress 15 % (2 MB)
99 07:17:27.268933 progress 20 % (3 MB)
100 07:17:27.413542 progress 25 % (3 MB)
101 07:17:27.525349 progress 30 % (4 MB)
102 07:17:27.631615 progress 35 % (5 MB)
103 07:17:27.746407 progress 40 % (6 MB)
104 07:17:27.857291 progress 45 % (7 MB)
105 07:17:27.973829 progress 50 % (7 MB)
106 07:17:28.086882 progress 55 % (8 MB)
107 07:17:28.204185 progress 60 % (9 MB)
108 07:17:28.315870 progress 65 % (10 MB)
109 07:17:28.429696 progress 70 % (10 MB)
110 07:17:28.546699 progress 75 % (11 MB)
111 07:17:28.663180 progress 80 % (12 MB)
112 07:17:28.778317 progress 85 % (13 MB)
113 07:17:28.891856 progress 90 % (14 MB)
114 07:17:28.996490 progress 95 % (14 MB)
115 07:17:29.112325 progress 100 % (15 MB)
116 07:17:29.126056 15 MB downloaded in 2.36 s (6.57 MB/s)
117 07:17:29.126705 end: 1.4.1 http-download (duration 00:00:02) [common]
119 07:17:29.127558 end: 1.4 download-retry (duration 00:00:02) [common]
120 07:17:29.127832 start: 1.5 prepare-tftp-overlay (timeout 00:09:57) [common]
121 07:17:29.128308 start: 1.5.1 extract-nfsrootfs (timeout 00:09:57) [common]
122 07:17:29.128820 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 07:17:29.129348 start: 1.5.2 lava-overlay (timeout 00:09:57) [common]
124 07:17:29.130317 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/932994/lava-overlay-qqm9n3ad
125 07:17:29.131175 makedir: /var/lib/lava/dispatcher/tmp/932994/lava-overlay-qqm9n3ad/lava-932994/bin
126 07:17:29.131820 makedir: /var/lib/lava/dispatcher/tmp/932994/lava-overlay-qqm9n3ad/lava-932994/tests
127 07:17:29.132487 makedir: /var/lib/lava/dispatcher/tmp/932994/lava-overlay-qqm9n3ad/lava-932994/results
128 07:17:29.133105 Creating /var/lib/lava/dispatcher/tmp/932994/lava-overlay-qqm9n3ad/lava-932994/bin/lava-add-keys
129 07:17:29.134063 Creating /var/lib/lava/dispatcher/tmp/932994/lava-overlay-qqm9n3ad/lava-932994/bin/lava-add-sources
130 07:17:29.135009 Creating /var/lib/lava/dispatcher/tmp/932994/lava-overlay-qqm9n3ad/lava-932994/bin/lava-background-process-start
131 07:17:29.135958 Creating /var/lib/lava/dispatcher/tmp/932994/lava-overlay-qqm9n3ad/lava-932994/bin/lava-background-process-stop
132 07:17:29.137059 Creating /var/lib/lava/dispatcher/tmp/932994/lava-overlay-qqm9n3ad/lava-932994/bin/lava-common-functions
133 07:17:29.138034 Creating /var/lib/lava/dispatcher/tmp/932994/lava-overlay-qqm9n3ad/lava-932994/bin/lava-echo-ipv4
134 07:17:29.138987 Creating /var/lib/lava/dispatcher/tmp/932994/lava-overlay-qqm9n3ad/lava-932994/bin/lava-install-packages
135 07:17:29.139896 Creating /var/lib/lava/dispatcher/tmp/932994/lava-overlay-qqm9n3ad/lava-932994/bin/lava-installed-packages
136 07:17:29.140857 Creating /var/lib/lava/dispatcher/tmp/932994/lava-overlay-qqm9n3ad/lava-932994/bin/lava-os-build
137 07:17:29.141772 Creating /var/lib/lava/dispatcher/tmp/932994/lava-overlay-qqm9n3ad/lava-932994/bin/lava-probe-channel
138 07:17:29.142694 Creating /var/lib/lava/dispatcher/tmp/932994/lava-overlay-qqm9n3ad/lava-932994/bin/lava-probe-ip
139 07:17:29.143610 Creating /var/lib/lava/dispatcher/tmp/932994/lava-overlay-qqm9n3ad/lava-932994/bin/lava-target-ip
140 07:17:29.144608 Creating /var/lib/lava/dispatcher/tmp/932994/lava-overlay-qqm9n3ad/lava-932994/bin/lava-target-mac
141 07:17:29.145564 Creating /var/lib/lava/dispatcher/tmp/932994/lava-overlay-qqm9n3ad/lava-932994/bin/lava-target-storage
142 07:17:29.146488 Creating /var/lib/lava/dispatcher/tmp/932994/lava-overlay-qqm9n3ad/lava-932994/bin/lava-test-case
143 07:17:29.147531 Creating /var/lib/lava/dispatcher/tmp/932994/lava-overlay-qqm9n3ad/lava-932994/bin/lava-test-event
144 07:17:29.148574 Creating /var/lib/lava/dispatcher/tmp/932994/lava-overlay-qqm9n3ad/lava-932994/bin/lava-test-feedback
145 07:17:29.149507 Creating /var/lib/lava/dispatcher/tmp/932994/lava-overlay-qqm9n3ad/lava-932994/bin/lava-test-raise
146 07:17:29.150448 Creating /var/lib/lava/dispatcher/tmp/932994/lava-overlay-qqm9n3ad/lava-932994/bin/lava-test-reference
147 07:17:29.151358 Creating /var/lib/lava/dispatcher/tmp/932994/lava-overlay-qqm9n3ad/lava-932994/bin/lava-test-runner
148 07:17:29.152303 Creating /var/lib/lava/dispatcher/tmp/932994/lava-overlay-qqm9n3ad/lava-932994/bin/lava-test-set
149 07:17:29.153333 Creating /var/lib/lava/dispatcher/tmp/932994/lava-overlay-qqm9n3ad/lava-932994/bin/lava-test-shell
150 07:17:29.154278 Updating /var/lib/lava/dispatcher/tmp/932994/lava-overlay-qqm9n3ad/lava-932994/bin/lava-install-packages (oe)
151 07:17:29.155355 Updating /var/lib/lava/dispatcher/tmp/932994/lava-overlay-qqm9n3ad/lava-932994/bin/lava-installed-packages (oe)
152 07:17:29.156313 Creating /var/lib/lava/dispatcher/tmp/932994/lava-overlay-qqm9n3ad/lava-932994/environment
153 07:17:29.157073 LAVA metadata
154 07:17:29.157576 - LAVA_JOB_ID=932994
155 07:17:29.158008 - LAVA_DISPATCHER_IP=192.168.6.2
156 07:17:29.158688 start: 1.5.2.1 ssh-authorize (timeout 00:09:57) [common]
157 07:17:29.160564 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 07:17:29.161188 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:57) [common]
159 07:17:29.161608 skipped lava-vland-overlay
160 07:17:29.162103 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 07:17:29.162612 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:57) [common]
162 07:17:29.163041 skipped lava-multinode-overlay
163 07:17:29.163528 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 07:17:29.164060 start: 1.5.2.4 test-definition (timeout 00:09:57) [common]
165 07:17:29.164553 Loading test definitions
166 07:17:29.165105 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:57) [common]
167 07:17:29.165545 Using /lava-932994 at stage 0
168 07:17:29.167855 uuid=932994_1.5.2.4.1 testdef=None
169 07:17:29.168490 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 07:17:29.169016 start: 1.5.2.4.2 test-overlay (timeout 00:09:57) [common]
171 07:17:29.172485 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 07:17:29.174062 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:57) [common]
174 07:17:29.177394 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 07:17:29.178304 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:57) [common]
177 07:17:29.180616 runner path: /var/lib/lava/dispatcher/tmp/932994/lava-overlay-qqm9n3ad/lava-932994/0/tests/0_dmesg test_uuid 932994_1.5.2.4.1
178 07:17:29.181232 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 07:17:29.182036 Creating lava-test-runner.conf files
181 07:17:29.182243 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/932994/lava-overlay-qqm9n3ad/lava-932994/0 for stage 0
182 07:17:29.182595 - 0_dmesg
183 07:17:29.182956 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 07:17:29.183248 start: 1.5.2.5 compress-overlay (timeout 00:09:57) [common]
185 07:17:29.207500 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 07:17:29.207949 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:57) [common]
187 07:17:29.208251 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 07:17:29.208528 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 07:17:29.208799 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:57) [common]
190 07:17:30.242525 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
191 07:17:30.243246 start: 1.5.4 extract-modules (timeout 00:09:55) [common]
192 07:17:30.243718 extracting modules file /var/lib/lava/dispatcher/tmp/932994/tftp-deploy-s4om3thx/modules/modules.tar to /var/lib/lava/dispatcher/tmp/932994/extract-overlay-ramdisk-g_cjubdt/ramdisk
193 07:17:31.813750 end: 1.5.4 extract-modules (duration 00:00:02) [common]
194 07:17:31.814250 start: 1.5.5 apply-overlay-tftp (timeout 00:09:54) [common]
195 07:17:31.814529 [common] Applying overlay /var/lib/lava/dispatcher/tmp/932994/compress-overlay-2n90pdh4/overlay-1.5.2.5.tar.gz to ramdisk
196 07:17:31.814746 [common] Applying overlay /var/lib/lava/dispatcher/tmp/932994/compress-overlay-2n90pdh4/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/932994/extract-overlay-ramdisk-g_cjubdt/ramdisk
197 07:17:31.845348 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 07:17:31.845788 start: 1.5.6 prepare-kernel (timeout 00:09:54) [common]
199 07:17:31.846062 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:54) [common]
200 07:17:31.846290 Converting downloaded kernel to a uImage
201 07:17:31.846592 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/932994/tftp-deploy-s4om3thx/kernel/Image /var/lib/lava/dispatcher/tmp/932994/tftp-deploy-s4om3thx/kernel/uImage
202 07:17:32.526448 output: Image Name:
203 07:17:32.526868 output: Created: Mon Nov 4 07:17:31 2024
204 07:17:32.527084 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 07:17:32.527293 output: Data Size: 66830848 Bytes = 65264.50 KiB = 63.73 MiB
206 07:17:32.527497 output: Load Address: 01080000
207 07:17:32.527699 output: Entry Point: 01080000
208 07:17:32.527901 output:
209 07:17:32.528306 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:01) [common]
210 07:17:32.528582 end: 1.5.6 prepare-kernel (duration 00:00:01) [common]
211 07:17:32.528852 start: 1.5.7 configure-preseed-file (timeout 00:09:53) [common]
212 07:17:32.529106 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 07:17:32.529364 start: 1.5.8 compress-ramdisk (timeout 00:09:53) [common]
214 07:17:32.529628 Building ramdisk /var/lib/lava/dispatcher/tmp/932994/extract-overlay-ramdisk-g_cjubdt/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/932994/extract-overlay-ramdisk-g_cjubdt/ramdisk
215 07:17:36.126137 >> 258174 blocks
216 07:17:47.143440 Adding RAMdisk u-boot header.
217 07:17:47.144195 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/932994/extract-overlay-ramdisk-g_cjubdt/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/932994/extract-overlay-ramdisk-g_cjubdt/ramdisk.cpio.gz.uboot
218 07:17:47.508197 output: Image Name:
219 07:17:47.508823 output: Created: Mon Nov 4 07:17:47 2024
220 07:17:47.509257 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 07:17:47.509662 output: Data Size: 33938571 Bytes = 33143.14 KiB = 32.37 MiB
222 07:17:47.510059 output: Load Address: 00000000
223 07:17:47.510453 output: Entry Point: 00000000
224 07:17:47.510844 output:
225 07:17:47.511901 rename /var/lib/lava/dispatcher/tmp/932994/extract-overlay-ramdisk-g_cjubdt/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/932994/tftp-deploy-s4om3thx/ramdisk/ramdisk.cpio.gz.uboot
226 07:17:47.512650 end: 1.5.8 compress-ramdisk (duration 00:00:15) [common]
227 07:17:47.513187 end: 1.5 prepare-tftp-overlay (duration 00:00:18) [common]
228 07:17:47.513706 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:38) [common]
229 07:17:47.514157 No LXC device requested
230 07:17:47.514648 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 07:17:47.515148 start: 1.7 deploy-device-env (timeout 00:09:38) [common]
232 07:17:47.515635 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 07:17:47.516069 Checking files for TFTP limit of 4294967296 bytes.
234 07:17:47.518688 end: 1 tftp-deploy (duration 00:00:22) [common]
235 07:17:47.519266 start: 2 uboot-action (timeout 00:05:00) [common]
236 07:17:47.519784 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 07:17:47.520317 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 07:17:47.520818 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 07:17:47.521345 Using kernel file from prepare-kernel: 932994/tftp-deploy-s4om3thx/kernel/uImage
240 07:17:47.521963 substitutions:
241 07:17:47.522373 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 07:17:47.522774 - {DTB_ADDR}: 0x01070000
243 07:17:47.523171 - {DTB}: 932994/tftp-deploy-s4om3thx/dtb/meson-g12b-a311d-libretech-cc.dtb
244 07:17:47.523570 - {INITRD}: 932994/tftp-deploy-s4om3thx/ramdisk/ramdisk.cpio.gz.uboot
245 07:17:47.523966 - {KERNEL_ADDR}: 0x01080000
246 07:17:47.524393 - {KERNEL}: 932994/tftp-deploy-s4om3thx/kernel/uImage
247 07:17:47.524789 - {LAVA_MAC}: None
248 07:17:47.525219 - {PRESEED_CONFIG}: None
249 07:17:47.525616 - {PRESEED_LOCAL}: None
250 07:17:47.526004 - {RAMDISK_ADDR}: 0x08000000
251 07:17:47.526390 - {RAMDISK}: 932994/tftp-deploy-s4om3thx/ramdisk/ramdisk.cpio.gz.uboot
252 07:17:47.526782 - {ROOT_PART}: None
253 07:17:47.527173 - {ROOT}: None
254 07:17:47.527564 - {SERVER_IP}: 192.168.6.2
255 07:17:47.527956 - {TEE_ADDR}: 0x83000000
256 07:17:47.528369 - {TEE}: None
257 07:17:47.528761 Parsed boot commands:
258 07:17:47.529139 - setenv autoload no
259 07:17:47.529526 - setenv initrd_high 0xffffffff
260 07:17:47.529912 - setenv fdt_high 0xffffffff
261 07:17:47.530298 - dhcp
262 07:17:47.530687 - setenv serverip 192.168.6.2
263 07:17:47.531073 - tftpboot 0x01080000 932994/tftp-deploy-s4om3thx/kernel/uImage
264 07:17:47.531460 - tftpboot 0x08000000 932994/tftp-deploy-s4om3thx/ramdisk/ramdisk.cpio.gz.uboot
265 07:17:47.531846 - tftpboot 0x01070000 932994/tftp-deploy-s4om3thx/dtb/meson-g12b-a311d-libretech-cc.dtb
266 07:17:47.532253 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 07:17:47.532648 - bootm 0x01080000 0x08000000 0x01070000
268 07:17:47.533144 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 07:17:47.534623 start: 2.3 connect-device (timeout 00:05:00) [common]
271 07:17:47.535065 [common] connect-device Connecting to device using 'telnet conserv1 3007'
272 07:17:47.550098 Setting prompt string to ['lava-test: # ']
273 07:17:47.551554 end: 2.3 connect-device (duration 00:00:00) [common]
274 07:17:47.552185 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 07:17:47.552733 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 07:17:47.553242 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 07:17:47.554419 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
278 07:17:47.592700 >> OK - accepted request
279 07:17:47.595126 Returned 0 in 0 seconds
280 07:17:47.696232 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
282 07:17:47.697813 end: 2.4.1 reset-device (duration 00:00:00) [common]
283 07:17:47.698367 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
284 07:17:47.698866 Setting prompt string to ['Hit any key to stop autoboot']
285 07:17:47.699302 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 07:17:47.700893 Trying 192.168.56.21...
287 07:17:47.701369 Connected to conserv1.
288 07:17:47.701788 Escape character is '^]'.
289 07:17:47.702212
290 07:17:47.702628 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
291 07:17:47.703052
292 07:17:58.800731 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
293 07:17:58.801168 bl2_stage_init 0x01
294 07:17:58.801402 bl2_stage_init 0x81
295 07:17:58.806195 hw id: 0x0000 - pwm id 0x01
296 07:17:58.806539 bl2_stage_init 0xc1
297 07:17:58.806763 bl2_stage_init 0x02
298 07:17:58.806981
299 07:17:58.811829 L0:00000000
300 07:17:58.812142 L1:20000703
301 07:17:58.812370 L2:00008067
302 07:17:58.812582 L3:14000000
303 07:17:58.817461 B2:00402000
304 07:17:58.817748 B1:e0f83180
305 07:17:58.817960
306 07:17:58.818164 TE: 58124
307 07:17:58.818366
308 07:17:58.823026 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
309 07:17:58.823290
310 07:17:58.823498 Board ID = 1
311 07:17:58.828716 Set A53 clk to 24M
312 07:17:58.828973 Set A73 clk to 24M
313 07:17:58.829176 Set clk81 to 24M
314 07:17:58.834105 A53 clk: 1200 MHz
315 07:17:58.834368 A73 clk: 1200 MHz
316 07:17:58.834577 CLK81: 166.6M
317 07:17:58.834782 smccc: 00012a92
318 07:17:58.839711 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
319 07:17:58.845280 board id: 1
320 07:17:58.851181 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
321 07:17:58.861889 fw parse done
322 07:17:58.867798 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
323 07:17:58.910469 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
324 07:17:58.921309 PIEI prepare done
325 07:17:58.921603 fastboot data load
326 07:17:58.921815 fastboot data verify
327 07:17:58.927213 verify result: 266
328 07:17:58.932673 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
329 07:17:58.932961 LPDDR4 probe
330 07:17:58.933174 ddr clk to 1584MHz
331 07:17:58.940590 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
332 07:17:58.977952
333 07:17:58.978448 dmc_version 0001
334 07:17:58.984606 Check phy result
335 07:17:58.990447 INFO : End of CA training
336 07:17:58.990757 INFO : End of initialization
337 07:17:58.996053 INFO : Training has run successfully!
338 07:17:58.996550 Check phy result
339 07:17:59.001594 INFO : End of initialization
340 07:17:59.001896 INFO : End of read enable training
341 07:17:59.007193 INFO : End of fine write leveling
342 07:17:59.012787 INFO : End of Write leveling coarse delay
343 07:17:59.013200 INFO : Training has run successfully!
344 07:17:59.013534 Check phy result
345 07:17:59.018419 INFO : End of initialization
346 07:17:59.018723 INFO : End of read dq deskew training
347 07:17:59.024011 INFO : End of MPR read delay center optimization
348 07:17:59.029595 INFO : End of write delay center optimization
349 07:17:59.035249 INFO : End of read delay center optimization
350 07:17:59.035669 INFO : End of max read latency training
351 07:17:59.040864 INFO : Training has run successfully!
352 07:17:59.041168 1D training succeed
353 07:17:59.050052 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
354 07:17:59.097696 Check phy result
355 07:17:59.098233 INFO : End of initialization
356 07:17:59.120326 INFO : End of 2D read delay Voltage center optimization
357 07:17:59.140574 INFO : End of 2D read delay Voltage center optimization
358 07:17:59.192596 INFO : End of 2D write delay Voltage center optimization
359 07:17:59.241945 INFO : End of 2D write delay Voltage center optimization
360 07:17:59.247626 INFO : Training has run successfully!
361 07:17:59.247960
362 07:17:59.248209 channel==0
363 07:17:59.253086 RxClkDly_Margin_A0==88 ps 9
364 07:17:59.253521 TxDqDly_Margin_A0==108 ps 11
365 07:17:59.258686 RxClkDly_Margin_A1==88 ps 9
366 07:17:59.259109 TxDqDly_Margin_A1==98 ps 10
367 07:17:59.259453 TrainedVREFDQ_A0==74
368 07:17:59.264343 TrainedVREFDQ_A1==74
369 07:17:59.264646 VrefDac_Margin_A0==24
370 07:17:59.269947 DeviceVref_Margin_A0==40
371 07:17:59.270455 VrefDac_Margin_A1==25
372 07:17:59.270813 DeviceVref_Margin_A1==40
373 07:17:59.271062
374 07:17:59.271279
375 07:17:59.275612 channel==1
376 07:17:59.276125 RxClkDly_Margin_A0==98 ps 10
377 07:17:59.276701 TxDqDly_Margin_A0==98 ps 10
378 07:17:59.281073 RxClkDly_Margin_A1==88 ps 9
379 07:17:59.281552 TxDqDly_Margin_A1==88 ps 9
380 07:17:59.286661 TrainedVREFDQ_A0==77
381 07:17:59.287135 TrainedVREFDQ_A1==77
382 07:17:59.287566 VrefDac_Margin_A0==23
383 07:17:59.292290 DeviceVref_Margin_A0==37
384 07:17:59.292767 VrefDac_Margin_A1==24
385 07:17:59.297945 DeviceVref_Margin_A1==37
386 07:17:59.298421
387 07:17:59.298850 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
388 07:17:59.303644
389 07:17:59.331639 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000017 00000019 00000017 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
390 07:17:59.332230 2D training succeed
391 07:17:59.337232 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
392 07:17:59.342557 auto size-- 65535DDR cs0 size: 2048MB
393 07:17:59.343025 DDR cs1 size: 2048MB
394 07:17:59.348213 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
395 07:17:59.348676 cs0 DataBus test pass
396 07:17:59.353767 cs1 DataBus test pass
397 07:17:59.354222 cs0 AddrBus test pass
398 07:17:59.354635 cs1 AddrBus test pass
399 07:17:59.355038
400 07:17:59.359446 100bdlr_step_size ps== 420
401 07:17:59.359923 result report
402 07:17:59.364937 boot times 0Enable ddr reg access
403 07:17:59.370532 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
404 07:17:59.383890 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
405 07:17:59.957571 0.0;M3 CHK:0;cm4_sp_mode 0
406 07:17:59.958144 MVN_1=0x00000000
407 07:17:59.963060 MVN_2=0x00000000
408 07:17:59.968803 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
409 07:17:59.969260 OPS=0x10
410 07:17:59.969686 ring efuse init
411 07:17:59.970099 chipver efuse init
412 07:17:59.974473 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
413 07:17:59.980042 [0.018961 Inits done]
414 07:17:59.980510 secure task start!
415 07:17:59.980934 high task start!
416 07:17:59.984580 low task start!
417 07:17:59.985034 run into bl31
418 07:17:59.991246 NOTICE: BL31: v1.3(release):4fc40b1
419 07:17:59.999050 NOTICE: BL31: Built : 15:58:17, May 22 2019
420 07:17:59.999519 NOTICE: BL31: G12A normal boot!
421 07:18:00.024459 NOTICE: BL31: BL33 decompress pass
422 07:18:00.030069 ERROR: Error initializing runtime service opteed_fast
423 07:18:01.262956
424 07:18:01.263592
425 07:18:01.271348 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
426 07:18:01.271813
427 07:18:01.272266 Model: Libre Computer AML-A311D-CC Alta
428 07:18:01.479883 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
429 07:18:01.503342 DRAM: 2 GiB (effective 3.8 GiB)
430 07:18:01.646206 Core: 408 devices, 31 uclasses, devicetree: separate
431 07:18:01.652011 WDT: Not starting watchdog@f0d0
432 07:18:01.684249 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
433 07:18:01.696707 Loading Environment from FAT... Card did not respond to voltage select! : -110
434 07:18:01.701807 ** Bad device specification mmc 0 **
435 07:18:01.712082 Card did not respond to voltage select! : -110
436 07:18:01.719789 ** Bad device specification mmc 0 **
437 07:18:01.720136 Couldn't find partition mmc 0
438 07:18:01.728162 Card did not respond to voltage select! : -110
439 07:18:01.733668 ** Bad device specification mmc 0 **
440 07:18:01.734227 Couldn't find partition mmc 0
441 07:18:01.738715 Error: could not access storage.
442 07:18:03.001230 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.�!,K��х��}���с0x01
443 07:18:03.001940 bl2_stage_init 0x81
444 07:18:03.006696 hw id: 0x0000 - pwm id 0x01
445 07:18:03.007268 bl2_stage_init 0xc1
446 07:18:03.007747 bl2_stage_init 0x02
447 07:18:03.008271
448 07:18:03.012399 L0:00000000
449 07:18:03.012961 L1:20000703
450 07:18:03.013425 L2:00008067
451 07:18:03.013878 L3:14000000
452 07:18:03.014327 B2:00402000
453 07:18:03.017959 B1:e0f83180
454 07:18:03.018292
455 07:18:03.018524 TE: 58150
456 07:18:03.018739
457 07:18:03.023409 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
458 07:18:03.023723
459 07:18:03.024236 Board ID = 1
460 07:18:03.029146 Set A53 clk to 24M
461 07:18:03.029686 Set A73 clk to 24M
462 07:18:03.030150 Set clk81 to 24M
463 07:18:03.034748 A53 clk: 1200 MHz
464 07:18:03.035192 A73 clk: 1200 MHz
465 07:18:03.035441 CLK81: 166.6M
466 07:18:03.035672 smccc: 00012aab
467 07:18:03.040304 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
468 07:18:03.045968 board id: 1
469 07:18:03.051814 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
470 07:18:03.062370 fw parse done
471 07:18:03.068339 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
472 07:18:03.110955 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
473 07:18:03.121864 PIEI prepare done
474 07:18:03.122185 fastboot data load
475 07:18:03.122426 fastboot data verify
476 07:18:03.127494 verify result: 266
477 07:18:03.133091 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
478 07:18:03.133455 LPDDR4 probe
479 07:18:03.133675 ddr clk to 1584MHz
480 07:18:03.141060 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
481 07:18:03.178328
482 07:18:03.178716 dmc_version 0001
483 07:18:03.185026 Check phy result
484 07:18:03.191015 INFO : End of CA training
485 07:18:03.191545 INFO : End of initialization
486 07:18:03.196523 INFO : Training has run successfully!
487 07:18:03.196914 Check phy result
488 07:18:03.202090 INFO : End of initialization
489 07:18:03.202586 INFO : End of read enable training
490 07:18:03.207765 INFO : End of fine write leveling
491 07:18:03.213275 INFO : End of Write leveling coarse delay
492 07:18:03.213625 INFO : Training has run successfully!
493 07:18:03.213858 Check phy result
494 07:18:03.218913 INFO : End of initialization
495 07:18:03.219265 INFO : End of read dq deskew training
496 07:18:03.224491 INFO : End of MPR read delay center optimization
497 07:18:03.230041 INFO : End of write delay center optimization
498 07:18:03.235702 INFO : End of read delay center optimization
499 07:18:03.236024 INFO : End of max read latency training
500 07:18:03.241259 INFO : Training has run successfully!
501 07:18:03.241596 1D training succeed
502 07:18:03.250469 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
503 07:18:03.298107 Check phy result
504 07:18:03.298679 INFO : End of initialization
505 07:18:03.320725 INFO : End of 2D read delay Voltage center optimization
506 07:18:03.340773 INFO : End of 2D read delay Voltage center optimization
507 07:18:03.392970 INFO : End of 2D write delay Voltage center optimization
508 07:18:03.442265 INFO : End of 2D write delay Voltage center optimization
509 07:18:03.447767 INFO : Training has run successfully!
510 07:18:03.448079
511 07:18:03.448310 channel==0
512 07:18:03.453365 RxClkDly_Margin_A0==88 ps 9
513 07:18:03.453646 TxDqDly_Margin_A0==98 ps 10
514 07:18:03.456670 RxClkDly_Margin_A1==88 ps 9
515 07:18:03.456962 TxDqDly_Margin_A1==98 ps 10
516 07:18:03.462255 TrainedVREFDQ_A0==74
517 07:18:03.462548 TrainedVREFDQ_A1==74
518 07:18:03.462782 VrefDac_Margin_A0==25
519 07:18:03.467942 DeviceVref_Margin_A0==40
520 07:18:03.468242 VrefDac_Margin_A1==25
521 07:18:03.473491 DeviceVref_Margin_A1==40
522 07:18:03.473783
523 07:18:03.474011
524 07:18:03.474226 channel==1
525 07:18:03.474454 RxClkDly_Margin_A0==98 ps 10
526 07:18:03.479076 TxDqDly_Margin_A0==88 ps 9
527 07:18:03.479361 RxClkDly_Margin_A1==88 ps 9
528 07:18:03.484860 TxDqDly_Margin_A1==88 ps 9
529 07:18:03.485417 TrainedVREFDQ_A0==77
530 07:18:03.485879 TrainedVREFDQ_A1==77
531 07:18:03.490447 VrefDac_Margin_A0==23
532 07:18:03.490962 DeviceVref_Margin_A0==37
533 07:18:03.496153 VrefDac_Margin_A1==24
534 07:18:03.496668 DeviceVref_Margin_A1==37
535 07:18:03.497121
536 07:18:03.501633 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
537 07:18:03.502158
538 07:18:03.529658 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000019 00000017 00000018 00000016 00000018 00000015 00000017 00000019 00000018 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
539 07:18:03.535364 2D training succeed
540 07:18:03.540918 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
541 07:18:03.541484 auto size-- 65535DDR cs0 size: 2048MB
542 07:18:03.546506 DDR cs1 size: 2048MB
543 07:18:03.547058 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
544 07:18:03.552228 cs0 DataBus test pass
545 07:18:03.552827 cs1 DataBus test pass
546 07:18:03.553306 cs0 AddrBus test pass
547 07:18:03.557701 cs1 AddrBus test pass
548 07:18:03.558262
549 07:18:03.558731 100bdlr_step_size ps== 420
550 07:18:03.559197 result report
551 07:18:03.563220 boot times 0Enable ddr reg access
552 07:18:03.570811 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
553 07:18:03.584227 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
554 07:18:04.158088 0.0;M3 CHK:0;cm4_sp_mode 0
555 07:18:04.158775 MVN_1=0x00000000
556 07:18:04.163606 MVN_2=0x00000000
557 07:18:04.169333 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
558 07:18:04.169876 OPS=0x10
559 07:18:04.170343 ring efuse init
560 07:18:04.170823 chipver efuse init
561 07:18:04.177389 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
562 07:18:04.177967 [0.018961 Inits done]
563 07:18:04.184924 secure task start!
564 07:18:04.185451 high task start!
565 07:18:04.185899 low task start!
566 07:18:04.186330 run into bl31
567 07:18:04.191615 NOTICE: BL31: v1.3(release):4fc40b1
568 07:18:04.199431 NOTICE: BL31: Built : 15:58:17, May 22 2019
569 07:18:04.199949 NOTICE: BL31: G12A normal boot!
570 07:18:04.224912 NOTICE: BL31: BL33 decompress pass
571 07:18:04.230483 ERROR: Error initializing runtime service opteed_fast
572 07:18:05.463660
573 07:18:05.464352
574 07:18:05.472018 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
575 07:18:05.472572
576 07:18:05.473046 Model: Libre Computer AML-A311D-CC Alta
577 07:18:05.679565 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
578 07:18:05.703785 DRAM: 2 GiB (effective 3.8 GiB)
579 07:18:05.846707 Core: 408 devices, 31 uclasses, devicetree: separate
580 07:18:05.852682 WDT: Not starting watchdog@f0d0
581 07:18:05.884890 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
582 07:18:05.897280 Loading Environment from FAT... Card did not respond to voltage select! : -110
583 07:18:05.902412 ** Bad device specification mmc 0 **
584 07:18:05.912703 Card did not respond to voltage select! : -110
585 07:18:05.920435 ** Bad device specification mmc 0 **
586 07:18:05.920973 Couldn't find partition mmc 0
587 07:18:05.928635 Card did not respond to voltage select! : -110
588 07:18:05.934191 ** Bad device specification mmc 0 **
589 07:18:05.934725 Couldn't find partition mmc 0
590 07:18:05.939200 Error: could not access storage.
591 07:18:06.281718 Net: eth0: ethernet@ff3f0000
592 07:18:06.282125 starting USB...
593 07:18:06.533367 Bus usb@ff500000: Register 3000140 NbrPorts 3
594 07:18:06.534030 Starting the controller
595 07:18:06.540463 USB XHCI 1.10
596 07:18:08.251291 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
597 07:18:08.251921 bl2_stage_init 0x01
598 07:18:08.252436 bl2_stage_init 0x81
599 07:18:08.256982 hw id: 0x0000 - pwm id 0x01
600 07:18:08.257437 bl2_stage_init 0xc1
601 07:18:08.257854 bl2_stage_init 0x02
602 07:18:08.258262
603 07:18:08.262512 L0:00000000
604 07:18:08.262969 L1:20000703
605 07:18:08.263384 L2:00008067
606 07:18:08.263791 L3:14000000
607 07:18:08.268187 B2:00402000
608 07:18:08.268639 B1:e0f83180
609 07:18:08.269045
610 07:18:08.269451 TE: 58159
611 07:18:08.269853
612 07:18:08.273726 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
613 07:18:08.274180
614 07:18:08.274591 Board ID = 1
615 07:18:08.279612 Set A53 clk to 24M
616 07:18:08.280084 Set A73 clk to 24M
617 07:18:08.280497 Set clk81 to 24M
618 07:18:08.285266 A53 clk: 1200 MHz
619 07:18:08.285719 A73 clk: 1200 MHz
620 07:18:08.286127 CLK81: 166.6M
621 07:18:08.286525 smccc: 00012ab5
622 07:18:08.290443 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
623 07:18:08.296149 board id: 1
624 07:18:08.300051 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
625 07:18:08.312869 fw parse done
626 07:18:08.318477 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
627 07:18:08.361130 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
628 07:18:08.372033 PIEI prepare done
629 07:18:08.372497 fastboot data load
630 07:18:08.372909 fastboot data verify
631 07:18:08.377699 verify result: 266
632 07:18:08.383352 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
633 07:18:08.383802 LPDDR4 probe
634 07:18:08.384246 ddr clk to 1584MHz
635 07:18:08.391234 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
636 07:18:08.428614
637 07:18:08.429088 dmc_version 0001
638 07:18:08.435129 Check phy result
639 07:18:08.441043 INFO : End of CA training
640 07:18:08.441477 INFO : End of initialization
641 07:18:08.446706 INFO : Training has run successfully!
642 07:18:08.447146 Check phy result
643 07:18:08.452258 INFO : End of initialization
644 07:18:08.452701 INFO : End of read enable training
645 07:18:08.457823 INFO : End of fine write leveling
646 07:18:08.463483 INFO : End of Write leveling coarse delay
647 07:18:08.463933 INFO : Training has run successfully!
648 07:18:08.464383 Check phy result
649 07:18:08.469073 INFO : End of initialization
650 07:18:08.469521 INFO : End of read dq deskew training
651 07:18:08.474723 INFO : End of MPR read delay center optimization
652 07:18:08.480229 INFO : End of write delay center optimization
653 07:18:08.485838 INFO : End of read delay center optimization
654 07:18:08.486272 INFO : End of max read latency training
655 07:18:08.491446 INFO : Training has run successfully!
656 07:18:08.491886 1D training succeed
657 07:18:08.500630 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
658 07:18:08.548241 Check phy result
659 07:18:08.548718 INFO : End of initialization
660 07:18:08.570631 INFO : End of 2D read delay Voltage center optimization
661 07:18:08.590821 INFO : End of 2D read delay Voltage center optimization
662 07:18:08.642730 INFO : End of 2D write delay Voltage center optimization
663 07:18:08.692660 INFO : End of 2D write delay Voltage center optimization
664 07:18:08.697483 INFO : Training has run successfully!
665 07:18:08.697918
666 07:18:08.698329 channel==0
667 07:18:08.703033 RxClkDly_Margin_A0==88 ps 9
668 07:18:08.703463 TxDqDly_Margin_A0==98 ps 10
669 07:18:08.706392 RxClkDly_Margin_A1==88 ps 9
670 07:18:08.706818 TxDqDly_Margin_A1==98 ps 10
671 07:18:08.711954 TrainedVREFDQ_A0==74
672 07:18:08.712443 TrainedVREFDQ_A1==74
673 07:18:08.712859 VrefDac_Margin_A0==25
674 07:18:08.717594 DeviceVref_Margin_A0==40
675 07:18:08.718032 VrefDac_Margin_A1==24
676 07:18:08.723220 DeviceVref_Margin_A1==40
677 07:18:08.723650
678 07:18:08.724088
679 07:18:08.724497 channel==1
680 07:18:08.724896 RxClkDly_Margin_A0==98 ps 10
681 07:18:08.728779 TxDqDly_Margin_A0==98 ps 10
682 07:18:08.729218 RxClkDly_Margin_A1==98 ps 10
683 07:18:08.734448 TxDqDly_Margin_A1==88 ps 9
684 07:18:08.734888 TrainedVREFDQ_A0==77
685 07:18:08.735299 TrainedVREFDQ_A1==77
686 07:18:08.740073 VrefDac_Margin_A0==22
687 07:18:08.740508 DeviceVref_Margin_A0==37
688 07:18:08.745584 VrefDac_Margin_A1==23
689 07:18:08.746012 DeviceVref_Margin_A1==37
690 07:18:08.746416
691 07:18:08.751141 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
692 07:18:08.751570
693 07:18:08.779175 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000017 00000019 00000018 0000001a 0000001a 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
694 07:18:08.784754 2D training succeed
695 07:18:08.790320 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
696 07:18:08.790758 auto size-- 65535DDR cs0 size: 2048MB
697 07:18:08.795950 DDR cs1 size: 2048MB
698 07:18:08.796405 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
699 07:18:08.801503 cs0 DataBus test pass
700 07:18:08.801933 cs1 DataBus test pass
701 07:18:08.802340 cs0 AddrBus test pass
702 07:18:08.807141 cs1 AddrBus test pass
703 07:18:08.807578
704 07:18:08.808006 100bdlr_step_size ps== 420
705 07:18:08.808426 result report
706 07:18:08.812731 boot times 0Enable ddr reg access
707 07:18:08.820459 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
708 07:18:08.833931 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
709 07:18:09.405880 0.0;M3 CHK:0;cm4_sp_mode 0
710 07:18:09.406491 MVN_1=0x00000000
711 07:18:09.411502 MVN_2=0x00000000
712 07:18:09.417145 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
713 07:18:09.417648 OPS=0x10
714 07:18:09.418055 ring efuse init
715 07:18:09.418450 chipver efuse init
716 07:18:09.422773 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
717 07:18:09.428360 [0.018960 Inits done]
718 07:18:09.428795 secure task start!
719 07:18:09.429190 high task start!
720 07:18:09.432927 low task start!
721 07:18:09.433354 run into bl31
722 07:18:09.439726 NOTICE: BL31: v1.3(release):4fc40b1
723 07:18:09.447389 NOTICE: BL31: Built : 15:58:17, May 22 2019
724 07:18:09.447827 NOTICE: BL31: G12A normal boot!
725 07:18:09.472834 NOTICE: BL31: BL33 decompress pass
726 07:18:09.478424 ERROR: Error initializing runtime service opteed_fast
727 07:18:10.711309
728 07:18:10.711732
729 07:18:10.719755 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
730 07:18:10.720095
731 07:18:10.720326 Model: Libre Computer AML-A311D-CC Alta
732 07:18:10.928368 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
733 07:18:10.951545 DRAM: 2 GiB (effective 3.8 GiB)
734 07:18:11.094563 Core: 408 devices, 31 uclasses, devicetree: separate
735 07:18:11.100425 WDT: Not starting watchdog@f0d0
736 07:18:11.132809 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
737 07:18:11.145238 Loading Environment from FAT... Card did not respond to voltage select! : -110
738 07:18:11.150240 ** Bad device specification mmc 0 **
739 07:18:11.160600 Card did not respond to voltage select! : -110
740 07:18:11.168205 ** Bad device specification mmc 0 **
741 07:18:11.168595 Couldn't find partition mmc 0
742 07:18:11.176594 Card did not respond to voltage select! : -110
743 07:18:11.182078 ** Bad device specification mmc 0 **
744 07:18:11.182649 Couldn't find partition mmc 0
745 07:18:11.187130 Error: could not access storage.
746 07:18:11.529562 Net: eth0: ethernet@ff3f0000
747 07:18:11.529980 starting USB...
748 07:18:11.781318 Bus usb@ff500000: Register 3000140 NbrPorts 3
749 07:18:11.781864 Starting the controller
750 07:18:11.788321 USB XHCI 1.10
751 07:18:13.952936 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
752 07:18:13.953365 bl2_stage_init 0x01
753 07:18:13.953580 bl2_stage_init 0x81
754 07:18:13.958348 hw id: 0x0000 - pwm id 0x01
755 07:18:13.958648 bl2_stage_init 0xc1
756 07:18:13.958873 bl2_stage_init 0x02
757 07:18:13.959087
758 07:18:13.963965 L0:00000000
759 07:18:13.964281 L1:20000703
760 07:18:13.964506 L2:00008067
761 07:18:13.964708 L3:14000000
762 07:18:13.966802 B2:00402000
763 07:18:13.967185 B1:e0f83180
764 07:18:13.967504
765 07:18:13.967821 TE: 58167
766 07:18:13.968153
767 07:18:13.977892 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
768 07:18:13.978200
769 07:18:13.978411 Board ID = 1
770 07:18:13.978614 Set A53 clk to 24M
771 07:18:13.978816 Set A73 clk to 24M
772 07:18:13.983441 Set clk81 to 24M
773 07:18:13.984010 A53 clk: 1200 MHz
774 07:18:13.984768 A73 clk: 1200 MHz
775 07:18:13.989123 CLK81: 166.6M
776 07:18:13.989546 smccc: 00012abe
777 07:18:13.994809 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
778 07:18:13.995229 board id: 1
779 07:18:14.000282 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
780 07:18:14.013986 fw parse done
781 07:18:14.019136 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
782 07:18:14.062409 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
783 07:18:14.073512 PIEI prepare done
784 07:18:14.073865 fastboot data load
785 07:18:14.074091 fastboot data verify
786 07:18:14.079143 verify result: 266
787 07:18:14.084744 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
788 07:18:14.085091 LPDDR4 probe
789 07:18:14.085327 ddr clk to 1584MHz
790 07:18:14.092068 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
791 07:18:14.129172
792 07:18:14.129554 dmc_version 0001
793 07:18:14.135851 Check phy result
794 07:18:14.142535 INFO : End of CA training
795 07:18:14.142901 INFO : End of initialization
796 07:18:14.148212 INFO : Training has run successfully!
797 07:18:14.148597 Check phy result
798 07:18:14.153729 INFO : End of initialization
799 07:18:14.154084 INFO : End of read enable training
800 07:18:14.157048 INFO : End of fine write leveling
801 07:18:14.162588 INFO : End of Write leveling coarse delay
802 07:18:14.168245 INFO : Training has run successfully!
803 07:18:14.168597 Check phy result
804 07:18:14.168823 INFO : End of initialization
805 07:18:14.173834 INFO : End of read dq deskew training
806 07:18:14.179549 INFO : End of MPR read delay center optimization
807 07:18:14.179912 INFO : End of write delay center optimization
808 07:18:14.185021 INFO : End of read delay center optimization
809 07:18:14.190650 INFO : End of max read latency training
810 07:18:14.191007 INFO : Training has run successfully!
811 07:18:14.196210 1D training succeed
812 07:18:14.201572 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
813 07:18:14.249155 Check phy result
814 07:18:14.249549 INFO : End of initialization
815 07:18:14.271421 INFO : End of 2D read delay Voltage center optimization
816 07:18:14.291755 INFO : End of 2D read delay Voltage center optimization
817 07:18:14.342963 INFO : End of 2D write delay Voltage center optimization
818 07:18:14.393214 INFO : End of 2D write delay Voltage center optimization
819 07:18:14.398799 INFO : Training has run successfully!
820 07:18:14.399148
821 07:18:14.399373 channel==0
822 07:18:14.404383 RxClkDly_Margin_A0==88 ps 9
823 07:18:14.404722 TxDqDly_Margin_A0==98 ps 10
824 07:18:14.407661 RxClkDly_Margin_A1==88 ps 9
825 07:18:14.408018 TxDqDly_Margin_A1==98 ps 10
826 07:18:14.413276 TrainedVREFDQ_A0==74
827 07:18:14.413624 TrainedVREFDQ_A1==75
828 07:18:14.418791 VrefDac_Margin_A0==25
829 07:18:14.419116 DeviceVref_Margin_A0==40
830 07:18:14.419334 VrefDac_Margin_A1==25
831 07:18:14.424497 DeviceVref_Margin_A1==39
832 07:18:14.424857
833 07:18:14.425072
834 07:18:14.425281 channel==1
835 07:18:14.425486 RxClkDly_Margin_A0==88 ps 9
836 07:18:14.429988 TxDqDly_Margin_A0==88 ps 9
837 07:18:14.430359 RxClkDly_Margin_A1==88 ps 9
838 07:18:14.435634 TxDqDly_Margin_A1==88 ps 9
839 07:18:14.435976 TrainedVREFDQ_A0==75
840 07:18:14.436235 TrainedVREFDQ_A1==77
841 07:18:14.441246 VrefDac_Margin_A0==22
842 07:18:14.441575 DeviceVref_Margin_A0==38
843 07:18:14.446793 VrefDac_Margin_A1==24
844 07:18:14.447135 DeviceVref_Margin_A1==37
845 07:18:14.447354
846 07:18:14.452363 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
847 07:18:14.452726
848 07:18:14.480309 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000018 00000019 00000018 00000019 00000018 00000019 0000001a 00000018 00000017 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
849 07:18:14.485872 2D training succeed
850 07:18:14.491485 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
851 07:18:14.491799 auto size-- 65535DDR cs0 size: 2048MB
852 07:18:14.497076 DDR cs1 size: 2048MB
853 07:18:14.497415 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
854 07:18:14.502664 cs0 DataBus test pass
855 07:18:14.502974 cs1 DataBus test pass
856 07:18:14.503187 cs0 AddrBus test pass
857 07:18:14.508324 cs1 AddrBus test pass
858 07:18:14.508632
859 07:18:14.508846 100bdlr_step_size ps== 420
860 07:18:14.509055 result report
861 07:18:14.513856 boot times 0Enable ddr reg access
862 07:18:14.521390 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
863 07:18:14.534251 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
864 07:18:15.108661 0.0;M3 CHK:0;cm4_sp_mode 0
865 07:18:15.109089 MVN_1=0x00000000
866 07:18:15.114003 MVN_2=0x00000000
867 07:18:15.119756 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
868 07:18:15.120091 OPS=0x10
869 07:18:15.120320 ring efuse init
870 07:18:15.120543 chipver efuse init
871 07:18:15.128098 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
872 07:18:15.128450 [0.018961 Inits done]
873 07:18:15.128667 secure task start!
874 07:18:15.135600 high task start!
875 07:18:15.135952 low task start!
876 07:18:15.136205 run into bl31
877 07:18:15.142348 NOTICE: BL31: v1.3(release):4fc40b1
878 07:18:15.150044 NOTICE: BL31: Built : 15:58:17, May 22 2019
879 07:18:15.150369 NOTICE: BL31: G12A normal boot!
880 07:18:15.175571 NOTICE: BL31: BL33 decompress pass
881 07:18:15.181082 ERROR: Error initializing runtime service opteed_fast
882 07:18:16.413921
883 07:18:16.414362
884 07:18:16.423601 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
885 07:18:16.425045
886 07:18:16.425907 Model: Libre Computer AML-A311D-CC Alta
887 07:18:16.630739 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
888 07:18:16.653577 DRAM: 2 GiB (effective 3.8 GiB)
889 07:18:16.797843 Core: 408 devices, 31 uclasses, devicetree: separate
890 07:18:16.802890 WDT: Not starting watchdog@f0d0
891 07:18:16.836241 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
892 07:18:16.847922 Loading Environment from FAT... Card did not respond to voltage select! : -110
893 07:18:16.853186 ** Bad device specification mmc 0 **
894 07:18:16.863365 Card did not respond to voltage select! : -110
895 07:18:16.870043 ** Bad device specification mmc 0 **
896 07:18:16.870596 Couldn't find partition mmc 0
897 07:18:16.879241 Card did not respond to voltage select! : -110
898 07:18:16.885152 ** Bad device specification mmc 0 **
899 07:18:16.885452 Couldn't find partition mmc 0
900 07:18:16.889371 Error: could not access storage.
901 07:18:17.232796 Net: eth0: ethernet@ff3f0000
902 07:18:17.233671 starting USB...
903 07:18:17.486728 Bus usb@ff500000: Register 3000140 NbrPorts 3
904 07:18:17.487747 Starting the controller
905 07:18:17.493505 USB XHCI 1.10
906 07:18:19.352751 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
907 07:18:19.353432 bl2_stage_init 0x01
908 07:18:19.353907 bl2_stage_init 0x81
909 07:18:19.358375 hw id: 0x0000 - pwm id 0x01
910 07:18:19.358902 bl2_stage_init 0xc1
911 07:18:19.359367 bl2_stage_init 0x02
912 07:18:19.359822
913 07:18:19.364040 L0:00000000
914 07:18:19.364587 L1:20000703
915 07:18:19.365049 L2:00008067
916 07:18:19.365497 L3:14000000
917 07:18:19.369554 B2:00402000
918 07:18:19.370068 B1:e0f83180
919 07:18:19.370528
920 07:18:19.370977 TE: 58124
921 07:18:19.371422
922 07:18:19.375220 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
923 07:18:19.375738
924 07:18:19.376247 Board ID = 1
925 07:18:19.380726 Set A53 clk to 24M
926 07:18:19.381237 Set A73 clk to 24M
927 07:18:19.381693 Set clk81 to 24M
928 07:18:19.386352 A53 clk: 1200 MHz
929 07:18:19.386863 A73 clk: 1200 MHz
930 07:18:19.387313 CLK81: 166.6M
931 07:18:19.387754 smccc: 00012a91
932 07:18:19.392054 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
933 07:18:19.397559 board id: 1
934 07:18:19.403460 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
935 07:18:19.414197 fw parse done
936 07:18:19.420247 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
937 07:18:19.462862 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
938 07:18:19.473714 PIEI prepare done
939 07:18:19.474214 fastboot data load
940 07:18:19.474653 fastboot data verify
941 07:18:19.479479 verify result: 266
942 07:18:19.484884 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
943 07:18:19.485379 LPDDR4 probe
944 07:18:19.485814 ddr clk to 1584MHz
945 07:18:19.492988 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
946 07:18:19.530181
947 07:18:19.530688 dmc_version 0001
948 07:18:19.536949 Check phy result
949 07:18:19.542786 INFO : End of CA training
950 07:18:19.543288 INFO : End of initialization
951 07:18:19.548530 INFO : Training has run successfully!
952 07:18:19.549062 Check phy result
953 07:18:19.553917 INFO : End of initialization
954 07:18:19.554421 INFO : End of read enable training
955 07:18:19.559468 INFO : End of fine write leveling
956 07:18:19.565124 INFO : End of Write leveling coarse delay
957 07:18:19.565624 INFO : Training has run successfully!
958 07:18:19.566071 Check phy result
959 07:18:19.570676 INFO : End of initialization
960 07:18:19.571178 INFO : End of read dq deskew training
961 07:18:19.576393 INFO : End of MPR read delay center optimization
962 07:18:19.581911 INFO : End of write delay center optimization
963 07:18:19.587535 INFO : End of read delay center optimization
964 07:18:19.588083 INFO : End of max read latency training
965 07:18:19.593124 INFO : Training has run successfully!
966 07:18:19.593627 1D training succeed
967 07:18:19.602258 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
968 07:18:19.649910 Check phy result
969 07:18:19.650443 INFO : End of initialization
970 07:18:19.672523 INFO : End of 2D read delay Voltage center optimization
971 07:18:19.692722 INFO : End of 2D read delay Voltage center optimization
972 07:18:19.744776 INFO : End of 2D write delay Voltage center optimization
973 07:18:19.794239 INFO : End of 2D write delay Voltage center optimization
974 07:18:19.799693 INFO : Training has run successfully!
975 07:18:19.800253
976 07:18:19.800718 channel==0
977 07:18:19.805414 RxClkDly_Margin_A0==88 ps 9
978 07:18:19.805917 TxDqDly_Margin_A0==98 ps 10
979 07:18:19.810930 RxClkDly_Margin_A1==78 ps 8
980 07:18:19.811428 TxDqDly_Margin_A1==98 ps 10
981 07:18:19.811883 TrainedVREFDQ_A0==74
982 07:18:19.816460 TrainedVREFDQ_A1==74
983 07:18:19.816959 VrefDac_Margin_A0==24
984 07:18:19.817414 DeviceVref_Margin_A0==40
985 07:18:19.822158 VrefDac_Margin_A1==25
986 07:18:19.822653 DeviceVref_Margin_A1==40
987 07:18:19.823101
988 07:18:19.823548
989 07:18:19.827654 channel==1
990 07:18:19.828184 RxClkDly_Margin_A0==98 ps 10
991 07:18:19.828642 TxDqDly_Margin_A0==88 ps 9
992 07:18:19.833269 RxClkDly_Margin_A1==98 ps 10
993 07:18:19.833770 TxDqDly_Margin_A1==88 ps 9
994 07:18:19.839204 TrainedVREFDQ_A0==76
995 07:18:19.839720 TrainedVREFDQ_A1==77
996 07:18:19.840218 VrefDac_Margin_A0==22
997 07:18:19.844480 DeviceVref_Margin_A0==38
998 07:18:19.845005 VrefDac_Margin_A1==24
999 07:18:19.850159 DeviceVref_Margin_A1==37
1000 07:18:19.850424
1001 07:18:19.850645 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
1002 07:18:19.850864
1003 07:18:19.883731 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000018 00000017 00000016 00000018 00000015 00000017 00000019 00000018 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
1004 07:18:19.884376 2D training succeed
1005 07:18:19.889367 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
1006 07:18:19.894828 auto size-- 65535DDR cs0 size: 2048MB
1007 07:18:19.895347 DDR cs1 size: 2048MB
1008 07:18:19.900440 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
1009 07:18:19.900951 cs0 DataBus test pass
1010 07:18:19.906030 cs1 DataBus test pass
1011 07:18:19.906534 cs0 AddrBus test pass
1012 07:18:19.906995 cs1 AddrBus test pass
1013 07:18:19.907445
1014 07:18:19.911632 100bdlr_step_size ps== 420
1015 07:18:19.912192 result report
1016 07:18:19.917163 boot times 0Enable ddr reg access
1017 07:18:19.922582 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
1018 07:18:19.936060 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
1019 07:18:20.509620 0.0;M3 CHK:0;cm4_sp_mode 0
1020 07:18:20.510299 MVN_1=0x00000000
1021 07:18:20.515157 MVN_2=0x00000000
1022 07:18:20.520887 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
1023 07:18:20.521415 OPS=0x10
1024 07:18:20.521887 ring efuse init
1025 07:18:20.522348 chipver efuse init
1026 07:18:20.526468 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
1027 07:18:20.532083 [0.018961 Inits done]
1028 07:18:20.532595 secure task start!
1029 07:18:20.533057 high task start!
1030 07:18:20.536663 low task start!
1031 07:18:20.537171 run into bl31
1032 07:18:20.543360 NOTICE: BL31: v1.3(release):4fc40b1
1033 07:18:20.551316 NOTICE: BL31: Built : 15:58:17, May 22 2019
1034 07:18:20.551843 NOTICE: BL31: G12A normal boot!
1035 07:18:20.576496 NOTICE: BL31: BL33 decompress pass
1036 07:18:20.582239 ERROR: Error initializing runtime service opteed_fast
1037 07:18:21.814959
1038 07:18:21.815406
1039 07:18:21.823820 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
1040 07:18:21.824339
1041 07:18:21.824567 Model: Libre Computer AML-A311D-CC Alta
1042 07:18:22.031925 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
1043 07:18:22.056354 DRAM: 2 GiB (effective 3.8 GiB)
1044 07:18:22.198410 Core: 408 devices, 31 uclasses, devicetree: separate
1045 07:18:22.204082 WDT: Not starting watchdog@f0d0
1046 07:18:22.236340 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
1047 07:18:22.248839 Loading Environment from FAT... Card did not respond to voltage select! : -110
1048 07:18:22.253761 ** Bad device specification mmc 0 **
1049 07:18:22.264093 Card did not respond to voltage select! : -110
1050 07:18:22.271794 ** Bad device specification mmc 0 **
1051 07:18:22.272141 Couldn't find partition mmc 0
1052 07:18:22.280101 Card did not respond to voltage select! : -110
1053 07:18:22.285598 ** Bad device specification mmc 0 **
1054 07:18:22.286017 Couldn't find partition mmc 0
1055 07:18:22.290699 Error: could not access storage.
1056 07:18:22.633200 Net: eth0: ethernet@ff3f0000
1057 07:18:22.633626 starting USB...
1058 07:18:22.885012 Bus usb@ff500000: Register 3000140 NbrPorts 3
1059 07:18:22.885657 Starting the controller
1060 07:18:22.891977 USB XHCI 1.10
1061 07:18:24.449059 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
1062 07:18:24.457569 scanning usb for storage devices... 0 Storage Device(s) found
1064 07:18:24.508701 Hit any key to stop autoboot: 1
1065 07:18:24.509401 end: 2.4.2 bootloader-interrupt (duration 00:00:37) [common]
1066 07:18:24.509785 start: 2.4.3 bootloader-commands (timeout 00:04:23) [common]
1067 07:18:24.510082 Setting prompt string to ['=>']
1068 07:18:24.510367 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:23)
1069 07:18:24.515028 0
1070 07:18:24.516143 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1071 07:18:24.516742 Sending with 10 millisecond of delay
1073 07:18:25.654467 => setenv autoload no
1074 07:18:25.665322 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:22)
1075 07:18:25.670839 setenv autoload no
1076 07:18:25.671693 Sending with 10 millisecond of delay
1078 07:18:27.470806 => setenv initrd_high 0xffffffff
1079 07:18:27.481856 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:20)
1080 07:18:27.482897 setenv initrd_high 0xffffffff
1081 07:18:27.483621 Sending with 10 millisecond of delay
1083 07:18:29.103627 => setenv fdt_high 0xffffffff
1084 07:18:29.114508 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1085 07:18:29.115602 setenv fdt_high 0xffffffff
1086 07:18:29.116090 Sending with 10 millisecond of delay
1088 07:18:29.408740 => dhcp
1089 07:18:29.419366 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1090 07:18:29.420084 dhcp
1091 07:18:29.420386 Speed: 1000, full duplex
1092 07:18:29.420642 BOOTP broadcast 1
1093 07:18:29.428374 DHCP client bound to address 192.168.6.27 (9 ms)
1094 07:18:29.428973 Sending with 10 millisecond of delay
1096 07:18:31.105035 => setenv serverip 192.168.6.2
1097 07:18:31.115608 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:16)
1098 07:18:31.116227 setenv serverip 192.168.6.2
1099 07:18:31.116704 Sending with 10 millisecond of delay
1101 07:18:34.841082 => tftpboot 0x01080000 932994/tftp-deploy-s4om3thx/kernel/uImage
1102 07:18:34.851919 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:13)
1103 07:18:34.852849 tftpboot 0x01080000 932994/tftp-deploy-s4om3thx/kernel/uImage
1104 07:18:34.853303 Speed: 1000, full duplex
1105 07:18:34.853717 Using ethernet@ff3f0000 device
1106 07:18:34.854547 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1107 07:18:34.860068 Filename '932994/tftp-deploy-s4om3thx/kernel/uImage'.
1108 07:18:34.864089 Load address: 0x1080000
1109 07:18:39.074184 Loading: *#################################################
1110 07:18:39.074592 TFTP error: trying to overwrite reserved memory...
1112 07:18:39.075464 end: 2.4.3 bootloader-commands (duration 00:00:15) [common]
1115 07:18:39.076484 end: 2.4 uboot-commands (duration 00:00:52) [common]
1117 07:18:39.077252 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'TFTP error: trying to overwrite reserved memory' (12)'
1119 07:18:39.077827 end: 2 uboot-action (duration 00:00:52) [common]
1121 07:18:39.078626 Cleaning after the job
1122 07:18:39.078958 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/932994/tftp-deploy-s4om3thx/ramdisk
1123 07:18:39.087771 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/932994/tftp-deploy-s4om3thx/kernel
1124 07:18:39.116840 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/932994/tftp-deploy-s4om3thx/dtb
1125 07:18:39.117692 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/932994/tftp-deploy-s4om3thx/modules
1126 07:18:39.147716 start: 4.1 power-off (timeout 00:00:30) [common]
1127 07:18:39.148400 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1128 07:18:39.182022 >> OK - accepted request
1129 07:18:39.184010 Returned 0 in 0 seconds
1130 07:18:39.284780 end: 4.1 power-off (duration 00:00:00) [common]
1132 07:18:39.285741 start: 4.2 read-feedback (timeout 00:10:00) [common]
1133 07:18:39.286407 Listened to connection for namespace 'common' for up to 1s
1134 07:18:40.287347 Finalising connection for namespace 'common'
1135 07:18:40.287853 Disconnecting from shell: Finalise
1136 07:18:40.288175 =>
1137 07:18:40.388846 end: 4.2 read-feedback (duration 00:00:01) [common]
1138 07:18:40.389475 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/932994
1139 07:18:40.705784 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/932994
1140 07:18:40.706372 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.