Boot log: meson-sm1-s905d3-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 07:15:05.692028 lava-dispatcher, installed at version: 2024.01
2 07:15:05.692746 start: 0 validate
3 07:15:05.693200 Start time: 2024-11-04 07:15:05.693170+00:00 (UTC)
4 07:15:05.693744 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 07:15:05.694263 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230703.0%2Farm64%2Frootfs.cpio.gz exists
6 07:15:05.729489 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 07:15:05.730046 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241104%2Farm64%2Fdefconfig%2Bkselftest%2Fgcc-12%2Fkernel%2FImage exists
8 07:15:06.765305 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 07:15:06.766012 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241104%2Farm64%2Fdefconfig%2Bkselftest%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-sm1-s905d3-libretech-cc.dtb exists
10 07:15:15.853899 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 07:15:15.854408 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241104%2Farm64%2Fdefconfig%2Bkselftest%2Fgcc-12%2Fmodules.tar.xz exists
12 07:15:15.900676 validate duration: 10.21
14 07:15:15.902140 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 07:15:15.902743 start: 1.1 download-retry (timeout 00:10:00) [common]
16 07:15:15.903317 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 07:15:15.904287 Not decompressing ramdisk as can be used compressed.
18 07:15:15.904993 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230703.0/arm64/rootfs.cpio.gz
19 07:15:15.905482 saving as /var/lib/lava/dispatcher/tmp/932978/tftp-deploy-1aqzywbl/ramdisk/rootfs.cpio.gz
20 07:15:15.905988 total size: 8181887 (7 MB)
21 07:15:15.945642 progress 0 % (0 MB)
22 07:15:15.956092 progress 5 % (0 MB)
23 07:15:15.966072 progress 10 % (0 MB)
24 07:15:15.976902 progress 15 % (1 MB)
25 07:15:15.985464 progress 20 % (1 MB)
26 07:15:15.991052 progress 25 % (1 MB)
27 07:15:15.996208 progress 30 % (2 MB)
28 07:15:16.001720 progress 35 % (2 MB)
29 07:15:16.006762 progress 40 % (3 MB)
30 07:15:16.012171 progress 45 % (3 MB)
31 07:15:16.017315 progress 50 % (3 MB)
32 07:15:16.022713 progress 55 % (4 MB)
33 07:15:16.027722 progress 60 % (4 MB)
34 07:15:16.033203 progress 65 % (5 MB)
35 07:15:16.038220 progress 70 % (5 MB)
36 07:15:16.043605 progress 75 % (5 MB)
37 07:15:16.048609 progress 80 % (6 MB)
38 07:15:16.053989 progress 85 % (6 MB)
39 07:15:16.059026 progress 90 % (7 MB)
40 07:15:16.064390 progress 95 % (7 MB)
41 07:15:16.069109 progress 100 % (7 MB)
42 07:15:16.069721 7 MB downloaded in 0.16 s (47.66 MB/s)
43 07:15:16.070256 end: 1.1.1 http-download (duration 00:00:00) [common]
45 07:15:16.071140 end: 1.1 download-retry (duration 00:00:00) [common]
46 07:15:16.071429 start: 1.2 download-retry (timeout 00:10:00) [common]
47 07:15:16.071697 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 07:15:16.072186 downloading http://storage.kernelci.org/next/master/next-20241104/arm64/defconfig+kselftest/gcc-12/kernel/Image
49 07:15:16.072427 saving as /var/lib/lava/dispatcher/tmp/932978/tftp-deploy-1aqzywbl/kernel/Image
50 07:15:16.072634 total size: 66830848 (63 MB)
51 07:15:16.072842 No compression specified
52 07:15:16.110370 progress 0 % (0 MB)
53 07:15:16.149615 progress 5 % (3 MB)
54 07:15:16.189742 progress 10 % (6 MB)
55 07:15:16.229697 progress 15 % (9 MB)
56 07:15:16.270007 progress 20 % (12 MB)
57 07:15:16.309734 progress 25 % (15 MB)
58 07:15:16.349198 progress 30 % (19 MB)
59 07:15:16.389319 progress 35 % (22 MB)
60 07:15:16.429369 progress 40 % (25 MB)
61 07:15:16.469070 progress 45 % (28 MB)
62 07:15:16.509310 progress 50 % (31 MB)
63 07:15:16.550587 progress 55 % (35 MB)
64 07:15:16.590021 progress 60 % (38 MB)
65 07:15:16.629536 progress 65 % (41 MB)
66 07:15:16.668940 progress 70 % (44 MB)
67 07:15:16.708670 progress 75 % (47 MB)
68 07:15:16.748184 progress 80 % (51 MB)
69 07:15:16.787956 progress 85 % (54 MB)
70 07:15:16.828742 progress 90 % (57 MB)
71 07:15:16.868688 progress 95 % (60 MB)
72 07:15:16.908179 progress 100 % (63 MB)
73 07:15:16.908943 63 MB downloaded in 0.84 s (76.21 MB/s)
74 07:15:16.909444 end: 1.2.1 http-download (duration 00:00:01) [common]
76 07:15:16.910273 end: 1.2 download-retry (duration 00:00:01) [common]
77 07:15:16.910552 start: 1.3 download-retry (timeout 00:09:59) [common]
78 07:15:16.910814 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 07:15:16.911447 downloading http://storage.kernelci.org/next/master/next-20241104/arm64/defconfig+kselftest/gcc-12/dtbs/amlogic/meson-sm1-s905d3-libretech-cc.dtb
80 07:15:16.911761 saving as /var/lib/lava/dispatcher/tmp/932978/tftp-deploy-1aqzywbl/dtb/meson-sm1-s905d3-libretech-cc.dtb
81 07:15:16.912005 total size: 53209 (0 MB)
82 07:15:16.912241 No compression specified
83 07:15:16.950792 progress 61 % (0 MB)
84 07:15:16.951665 progress 100 % (0 MB)
85 07:15:16.952252 0 MB downloaded in 0.04 s (1.26 MB/s)
86 07:15:16.952770 end: 1.3.1 http-download (duration 00:00:00) [common]
88 07:15:16.953606 end: 1.3 download-retry (duration 00:00:00) [common]
89 07:15:16.953871 start: 1.4 download-retry (timeout 00:09:59) [common]
90 07:15:16.954140 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 07:15:16.954815 downloading http://storage.kernelci.org/next/master/next-20241104/arm64/defconfig+kselftest/gcc-12/modules.tar.xz
92 07:15:16.955100 saving as /var/lib/lava/dispatcher/tmp/932978/tftp-deploy-1aqzywbl/modules/modules.tar
93 07:15:16.955320 total size: 16280944 (15 MB)
94 07:15:16.955544 Using unxz to decompress xz
95 07:15:16.997866 progress 0 % (0 MB)
96 07:15:17.122641 progress 5 % (0 MB)
97 07:15:17.236928 progress 10 % (1 MB)
98 07:15:17.360470 progress 15 % (2 MB)
99 07:15:17.497016 progress 20 % (3 MB)
100 07:15:18.029870 progress 25 % (3 MB)
101 07:15:18.144681 progress 30 % (4 MB)
102 07:15:18.251543 progress 35 % (5 MB)
103 07:15:18.366605 progress 40 % (6 MB)
104 07:15:18.474593 progress 45 % (7 MB)
105 07:15:18.591555 progress 50 % (7 MB)
106 07:15:18.707012 progress 55 % (8 MB)
107 07:15:18.826790 progress 60 % (9 MB)
108 07:15:18.938542 progress 65 % (10 MB)
109 07:15:19.053540 progress 70 % (10 MB)
110 07:15:19.172319 progress 75 % (11 MB)
111 07:15:19.289257 progress 80 % (12 MB)
112 07:15:19.404883 progress 85 % (13 MB)
113 07:15:19.519368 progress 90 % (14 MB)
114 07:15:19.626037 progress 95 % (14 MB)
115 07:15:19.740353 progress 100 % (15 MB)
116 07:15:19.754036 15 MB downloaded in 2.80 s (5.55 MB/s)
117 07:15:19.755015 end: 1.4.1 http-download (duration 00:00:03) [common]
119 07:15:19.756847 end: 1.4 download-retry (duration 00:00:03) [common]
120 07:15:19.757435 start: 1.5 prepare-tftp-overlay (timeout 00:09:56) [common]
121 07:15:19.758005 start: 1.5.1 extract-nfsrootfs (timeout 00:09:56) [common]
122 07:15:19.758548 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 07:15:19.759101 start: 1.5.2 lava-overlay (timeout 00:09:56) [common]
124 07:15:19.760201 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/932978/lava-overlay-8ew8ye6b
125 07:15:19.761123 makedir: /var/lib/lava/dispatcher/tmp/932978/lava-overlay-8ew8ye6b/lava-932978/bin
126 07:15:19.761803 makedir: /var/lib/lava/dispatcher/tmp/932978/lava-overlay-8ew8ye6b/lava-932978/tests
127 07:15:19.762463 makedir: /var/lib/lava/dispatcher/tmp/932978/lava-overlay-8ew8ye6b/lava-932978/results
128 07:15:19.763130 Creating /var/lib/lava/dispatcher/tmp/932978/lava-overlay-8ew8ye6b/lava-932978/bin/lava-add-keys
129 07:15:19.764186 Creating /var/lib/lava/dispatcher/tmp/932978/lava-overlay-8ew8ye6b/lava-932978/bin/lava-add-sources
130 07:15:19.765250 Creating /var/lib/lava/dispatcher/tmp/932978/lava-overlay-8ew8ye6b/lava-932978/bin/lava-background-process-start
131 07:15:19.766358 Creating /var/lib/lava/dispatcher/tmp/932978/lava-overlay-8ew8ye6b/lava-932978/bin/lava-background-process-stop
132 07:15:19.767449 Creating /var/lib/lava/dispatcher/tmp/932978/lava-overlay-8ew8ye6b/lava-932978/bin/lava-common-functions
133 07:15:19.768500 Creating /var/lib/lava/dispatcher/tmp/932978/lava-overlay-8ew8ye6b/lava-932978/bin/lava-echo-ipv4
134 07:15:19.769631 Creating /var/lib/lava/dispatcher/tmp/932978/lava-overlay-8ew8ye6b/lava-932978/bin/lava-install-packages
135 07:15:19.770613 Creating /var/lib/lava/dispatcher/tmp/932978/lava-overlay-8ew8ye6b/lava-932978/bin/lava-installed-packages
136 07:15:19.771567 Creating /var/lib/lava/dispatcher/tmp/932978/lava-overlay-8ew8ye6b/lava-932978/bin/lava-os-build
137 07:15:19.772602 Creating /var/lib/lava/dispatcher/tmp/932978/lava-overlay-8ew8ye6b/lava-932978/bin/lava-probe-channel
138 07:15:19.773585 Creating /var/lib/lava/dispatcher/tmp/932978/lava-overlay-8ew8ye6b/lava-932978/bin/lava-probe-ip
139 07:15:19.774591 Creating /var/lib/lava/dispatcher/tmp/932978/lava-overlay-8ew8ye6b/lava-932978/bin/lava-target-ip
140 07:15:19.775581 Creating /var/lib/lava/dispatcher/tmp/932978/lava-overlay-8ew8ye6b/lava-932978/bin/lava-target-mac
141 07:15:19.776633 Creating /var/lib/lava/dispatcher/tmp/932978/lava-overlay-8ew8ye6b/lava-932978/bin/lava-target-storage
142 07:15:19.777640 Creating /var/lib/lava/dispatcher/tmp/932978/lava-overlay-8ew8ye6b/lava-932978/bin/lava-test-case
143 07:15:19.778610 Creating /var/lib/lava/dispatcher/tmp/932978/lava-overlay-8ew8ye6b/lava-932978/bin/lava-test-event
144 07:15:19.779556 Creating /var/lib/lava/dispatcher/tmp/932978/lava-overlay-8ew8ye6b/lava-932978/bin/lava-test-feedback
145 07:15:19.780559 Creating /var/lib/lava/dispatcher/tmp/932978/lava-overlay-8ew8ye6b/lava-932978/bin/lava-test-raise
146 07:15:19.781552 Creating /var/lib/lava/dispatcher/tmp/932978/lava-overlay-8ew8ye6b/lava-932978/bin/lava-test-reference
147 07:15:19.782563 Creating /var/lib/lava/dispatcher/tmp/932978/lava-overlay-8ew8ye6b/lava-932978/bin/lava-test-runner
148 07:15:19.783597 Creating /var/lib/lava/dispatcher/tmp/932978/lava-overlay-8ew8ye6b/lava-932978/bin/lava-test-set
149 07:15:19.784640 Creating /var/lib/lava/dispatcher/tmp/932978/lava-overlay-8ew8ye6b/lava-932978/bin/lava-test-shell
150 07:15:19.785643 Updating /var/lib/lava/dispatcher/tmp/932978/lava-overlay-8ew8ye6b/lava-932978/bin/lava-install-packages (oe)
151 07:15:19.786747 Updating /var/lib/lava/dispatcher/tmp/932978/lava-overlay-8ew8ye6b/lava-932978/bin/lava-installed-packages (oe)
152 07:15:19.787689 Creating /var/lib/lava/dispatcher/tmp/932978/lava-overlay-8ew8ye6b/lava-932978/environment
153 07:15:19.788547 LAVA metadata
154 07:15:19.789103 - LAVA_JOB_ID=932978
155 07:15:19.789590 - LAVA_DISPATCHER_IP=192.168.6.2
156 07:15:19.790346 start: 1.5.2.1 ssh-authorize (timeout 00:09:56) [common]
157 07:15:19.792422 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 07:15:19.793090 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:56) [common]
159 07:15:19.793547 skipped lava-vland-overlay
160 07:15:19.794088 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 07:15:19.794647 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:56) [common]
162 07:15:19.795117 skipped lava-multinode-overlay
163 07:15:19.795669 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 07:15:19.796270 start: 1.5.2.4 test-definition (timeout 00:09:56) [common]
165 07:15:19.796763 Loading test definitions
166 07:15:19.797322 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:56) [common]
167 07:15:19.797773 Using /lava-932978 at stage 0
168 07:15:19.800136 uuid=932978_1.5.2.4.1 testdef=None
169 07:15:19.800770 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 07:15:19.801299 start: 1.5.2.4.2 test-overlay (timeout 00:09:56) [common]
171 07:15:19.804458 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 07:15:19.805317 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:56) [common]
174 07:15:19.807679 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 07:15:19.808633 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:56) [common]
177 07:15:19.811060 runner path: /var/lib/lava/dispatcher/tmp/932978/lava-overlay-8ew8ye6b/lava-932978/0/tests/0_dmesg test_uuid 932978_1.5.2.4.1
178 07:15:19.811692 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 07:15:19.812529 Creating lava-test-runner.conf files
181 07:15:19.812757 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/932978/lava-overlay-8ew8ye6b/lava-932978/0 for stage 0
182 07:15:19.813139 - 0_dmesg
183 07:15:19.813510 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 07:15:19.813819 start: 1.5.2.5 compress-overlay (timeout 00:09:56) [common]
185 07:15:19.838509 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 07:15:19.838961 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:56) [common]
187 07:15:19.839230 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 07:15:19.839504 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 07:15:19.839769 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:56) [common]
190 07:15:20.834695 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
191 07:15:20.835167 start: 1.5.4 extract-modules (timeout 00:09:55) [common]
192 07:15:20.835414 extracting modules file /var/lib/lava/dispatcher/tmp/932978/tftp-deploy-1aqzywbl/modules/modules.tar to /var/lib/lava/dispatcher/tmp/932978/extract-overlay-ramdisk-3dwx9pg8/ramdisk
193 07:15:22.370735 end: 1.5.4 extract-modules (duration 00:00:02) [common]
194 07:15:22.371220 start: 1.5.5 apply-overlay-tftp (timeout 00:09:54) [common]
195 07:15:22.371498 [common] Applying overlay /var/lib/lava/dispatcher/tmp/932978/compress-overlay-zh_rz0ls/overlay-1.5.2.5.tar.gz to ramdisk
196 07:15:22.371713 [common] Applying overlay /var/lib/lava/dispatcher/tmp/932978/compress-overlay-zh_rz0ls/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/932978/extract-overlay-ramdisk-3dwx9pg8/ramdisk
197 07:15:22.403334 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 07:15:22.403771 start: 1.5.6 prepare-kernel (timeout 00:09:53) [common]
199 07:15:22.404067 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:53) [common]
200 07:15:22.404299 Converting downloaded kernel to a uImage
201 07:15:22.404628 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/932978/tftp-deploy-1aqzywbl/kernel/Image /var/lib/lava/dispatcher/tmp/932978/tftp-deploy-1aqzywbl/kernel/uImage
202 07:15:23.076264 output: Image Name:
203 07:15:23.076691 output: Created: Mon Nov 4 07:15:22 2024
204 07:15:23.076902 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 07:15:23.077109 output: Data Size: 66830848 Bytes = 65264.50 KiB = 63.73 MiB
206 07:15:23.077311 output: Load Address: 01080000
207 07:15:23.077513 output: Entry Point: 01080000
208 07:15:23.077712 output:
209 07:15:23.078048 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:01) [common]
210 07:15:23.078317 end: 1.5.6 prepare-kernel (duration 00:00:01) [common]
211 07:15:23.078589 start: 1.5.7 configure-preseed-file (timeout 00:09:53) [common]
212 07:15:23.078844 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 07:15:23.079100 start: 1.5.8 compress-ramdisk (timeout 00:09:53) [common]
214 07:15:23.079374 Building ramdisk /var/lib/lava/dispatcher/tmp/932978/extract-overlay-ramdisk-3dwx9pg8/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/932978/extract-overlay-ramdisk-3dwx9pg8/ramdisk
215 07:15:26.878204 >> 258174 blocks
216 07:15:38.109194 Adding RAMdisk u-boot header.
217 07:15:38.109637 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/932978/extract-overlay-ramdisk-3dwx9pg8/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/932978/extract-overlay-ramdisk-3dwx9pg8/ramdisk.cpio.gz.uboot
218 07:15:38.472765 output: Image Name:
219 07:15:38.473194 output: Created: Mon Nov 4 07:15:38 2024
220 07:15:38.473714 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 07:15:38.474174 output: Data Size: 33937959 Bytes = 33142.54 KiB = 32.37 MiB
222 07:15:38.474648 output: Load Address: 00000000
223 07:15:38.475096 output: Entry Point: 00000000
224 07:15:38.475535 output:
225 07:15:38.476660 rename /var/lib/lava/dispatcher/tmp/932978/extract-overlay-ramdisk-3dwx9pg8/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/932978/tftp-deploy-1aqzywbl/ramdisk/ramdisk.cpio.gz.uboot
226 07:15:38.477449 end: 1.5.8 compress-ramdisk (duration 00:00:15) [common]
227 07:15:38.478058 end: 1.5 prepare-tftp-overlay (duration 00:00:19) [common]
228 07:15:38.478652 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:37) [common]
229 07:15:38.479170 No LXC device requested
230 07:15:38.479734 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 07:15:38.480357 start: 1.7 deploy-device-env (timeout 00:09:37) [common]
232 07:15:38.480918 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 07:15:38.481386 Checking files for TFTP limit of 4294967296 bytes.
234 07:15:38.484360 end: 1 tftp-deploy (duration 00:00:23) [common]
235 07:15:38.485008 start: 2 uboot-action (timeout 00:05:00) [common]
236 07:15:38.485594 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 07:15:38.486156 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 07:15:38.486721 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 07:15:38.487309 Using kernel file from prepare-kernel: 932978/tftp-deploy-1aqzywbl/kernel/uImage
240 07:15:38.488010 substitutions:
241 07:15:38.488483 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 07:15:38.488939 - {DTB_ADDR}: 0x01070000
243 07:15:38.489387 - {DTB}: 932978/tftp-deploy-1aqzywbl/dtb/meson-sm1-s905d3-libretech-cc.dtb
244 07:15:38.489833 - {INITRD}: 932978/tftp-deploy-1aqzywbl/ramdisk/ramdisk.cpio.gz.uboot
245 07:15:38.490277 - {KERNEL_ADDR}: 0x01080000
246 07:15:38.490717 - {KERNEL}: 932978/tftp-deploy-1aqzywbl/kernel/uImage
247 07:15:38.491162 - {LAVA_MAC}: None
248 07:15:38.491646 - {PRESEED_CONFIG}: None
249 07:15:38.492153 - {PRESEED_LOCAL}: None
250 07:15:38.492611 - {RAMDISK_ADDR}: 0x08000000
251 07:15:38.493052 - {RAMDISK}: 932978/tftp-deploy-1aqzywbl/ramdisk/ramdisk.cpio.gz.uboot
252 07:15:38.493497 - {ROOT_PART}: None
253 07:15:38.493940 - {ROOT}: None
254 07:15:38.494381 - {SERVER_IP}: 192.168.6.2
255 07:15:38.494824 - {TEE_ADDR}: 0x83000000
256 07:15:38.495263 - {TEE}: None
257 07:15:38.495699 Parsed boot commands:
258 07:15:38.496162 - setenv autoload no
259 07:15:38.496609 - setenv initrd_high 0xffffffff
260 07:15:38.497050 - setenv fdt_high 0xffffffff
261 07:15:38.497486 - dhcp
262 07:15:38.497927 - setenv serverip 192.168.6.2
263 07:15:38.498365 - tftpboot 0x01080000 932978/tftp-deploy-1aqzywbl/kernel/uImage
264 07:15:38.498804 - tftpboot 0x08000000 932978/tftp-deploy-1aqzywbl/ramdisk/ramdisk.cpio.gz.uboot
265 07:15:38.499240 - tftpboot 0x01070000 932978/tftp-deploy-1aqzywbl/dtb/meson-sm1-s905d3-libretech-cc.dtb
266 07:15:38.499677 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 07:15:38.500184 - bootm 0x01080000 0x08000000 0x01070000
268 07:15:38.500766 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 07:15:38.502433 start: 2.3 connect-device (timeout 00:05:00) [common]
271 07:15:38.502936 [common] connect-device Connecting to device using 'telnet conserv1 3008'
272 07:15:38.516884 Setting prompt string to ['lava-test: # ']
273 07:15:38.518498 end: 2.3 connect-device (duration 00:00:00) [common]
274 07:15:38.519178 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 07:15:38.519800 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 07:15:38.520449 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 07:15:38.521704 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=solitude-01'
278 07:15:38.573570 >> OK - accepted request
279 07:15:38.575918 Returned 0 in 0 seconds
280 07:15:38.677259 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
282 07:15:38.679150 end: 2.4.1 reset-device (duration 00:00:00) [common]
283 07:15:38.679804 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
284 07:15:38.680429 Setting prompt string to ['Hit any key to stop autoboot']
285 07:15:38.680953 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 07:15:38.682711 Trying 192.168.56.21...
287 07:15:38.683253 Connected to conserv1.
288 07:15:38.683737 Escape character is '^]'.
289 07:15:38.684259
290 07:15:38.684753 ser2net port telnet,3008 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.3.3:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
291 07:15:38.685243
292 07:15:45.907726 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
293 07:15:45.908199 bl2_stage_init 0x01
294 07:15:45.908450 bl2_stage_init 0x81
295 07:15:45.913274 hw id: 0x0000 - pwm id 0x01
296 07:15:45.913587 bl2_stage_init 0xc1
297 07:15:45.918209 bl2_stage_init 0x02
298 07:15:45.918511
299 07:15:45.918746 L0:00000000
300 07:15:45.918961 L1:00000703
301 07:15:45.919169 L2:00008067
302 07:15:45.923701 L3:15000000
303 07:15:45.924031 S1:00000000
304 07:15:45.924258 B2:20282000
305 07:15:45.924470 B1:a0f83180
306 07:15:45.924675
307 07:15:45.924884 TE: 71639
308 07:15:45.925092
309 07:15:45.934982 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
310 07:15:45.935318
311 07:15:45.935539 Board ID = 1
312 07:15:45.935753 Set cpu clk to 24M
313 07:15:45.935963 Set clk81 to 24M
314 07:15:45.938583 Use GP1_pll as DSU clk.
315 07:15:45.938873 DSU clk: 1200 Mhz
316 07:15:45.944119 CPU clk: 1200 MHz
317 07:15:45.944432 Set clk81 to 166.6M
318 07:15:45.949671 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
319 07:15:45.949969 board id: 1
320 07:15:45.959522 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
321 07:15:45.970222 fw parse done
322 07:15:45.976203 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
323 07:15:46.018969 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
324 07:15:46.029828 PIEI prepare done
325 07:15:46.030180 fastboot data load
326 07:15:46.030405 fastboot data verify
327 07:15:46.035360 verify result: 266
328 07:15:46.040977 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
329 07:15:46.041303 LPDDR4 probe
330 07:15:46.041524 ddr clk to 1584MHz
331 07:15:46.048981 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
332 07:15:46.086335
333 07:15:46.086685 dmc_version 0001
334 07:15:46.092958 Check phy result
335 07:15:46.098813 INFO : End of CA training
336 07:15:46.099110 INFO : End of initialization
337 07:15:46.104477 INFO : Training has run successfully!
338 07:15:46.104777 Check phy result
339 07:15:46.110078 INFO : End of initialization
340 07:15:46.110377 INFO : End of read enable training
341 07:15:46.113325 INFO : End of fine write leveling
342 07:15:46.118900 INFO : End of Write leveling coarse delay
343 07:15:46.124499 INFO : Training has run successfully!
344 07:15:46.124802 Check phy result
345 07:15:46.125025 INFO : End of initialization
346 07:15:46.130096 INFO : End of read dq deskew training
347 07:15:46.135705 INFO : End of MPR read delay center optimization
348 07:15:46.136032 INFO : End of write delay center optimization
349 07:15:46.141305 INFO : End of read delay center optimization
350 07:15:46.146923 INFO : End of max read latency training
351 07:15:46.147242 INFO : Training has run successfully!
352 07:15:46.152508 1D training succeed
353 07:15:46.158474 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
354 07:15:46.206021 Check phy result
355 07:15:46.206364 INFO : End of initialization
356 07:15:46.228357 INFO : End of 2D read delay Voltage center optimization
357 07:15:46.247555 INFO : End of 2D read delay Voltage center optimization
358 07:15:46.299477 INFO : End of 2D write delay Voltage center optimization
359 07:15:46.348667 INFO : End of 2D write delay Voltage center optimization
360 07:15:46.354198 INFO : Training has run successfully!
361 07:15:46.354472
362 07:15:46.354688 channel==0
363 07:15:46.359827 RxClkDly_Margin_A0==78 ps 8
364 07:15:46.360444 TxDqDly_Margin_A0==88 ps 9
365 07:15:46.365400 RxClkDly_Margin_A1==88 ps 9
366 07:15:46.365666 TxDqDly_Margin_A1==98 ps 10
367 07:15:46.365883 TrainedVREFDQ_A0==74
368 07:15:46.370969 TrainedVREFDQ_A1==75
369 07:15:46.371239 VrefDac_Margin_A0==24
370 07:15:46.371454 DeviceVref_Margin_A0==40
371 07:15:46.376522 VrefDac_Margin_A1==23
372 07:15:46.376787 DeviceVref_Margin_A1==39
373 07:15:46.377003
374 07:15:46.377210
375 07:15:46.377419 channel==1
376 07:15:46.382204 RxClkDly_Margin_A0==78 ps 8
377 07:15:46.382473 TxDqDly_Margin_A0==88 ps 9
378 07:15:46.387811 RxClkDly_Margin_A1==88 ps 9
379 07:15:46.388097 TxDqDly_Margin_A1==88 ps 9
380 07:15:46.395255 TrainedVREFDQ_A0==75
381 07:15:46.395530 TrainedVREFDQ_A1==77
382 07:15:46.395745 VrefDac_Margin_A0==22
383 07:15:46.398577 DeviceVref_Margin_A0==38
384 07:15:46.398839 VrefDac_Margin_A1==22
385 07:15:46.404194 DeviceVref_Margin_A1==37
386 07:15:46.404464
387 07:15:46.404682 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
388 07:15:46.409701
389 07:15:46.437733 soc_vref_reg_value 0x 0000001a 00000019 00000019 00000017 00000019 00000016 00000018 00000016 00000018 00000017 00000017 00000018 00000018 00000018 00000018 00000019 00000018 00000018 00000018 00000015 00000018 00000015 00000015 00000017 00000019 00000019 00000018 00000019 0000001c 00000018 00000016 00000017 dram_vref_reg_value 0x 00000061
390 07:15:46.438185 2D training succeed
391 07:15:46.443385 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
392 07:15:46.449000 auto size-- 65535DDR cs0 size: 2048MB
393 07:15:46.449358 DDR cs1 size: 2048MB
394 07:15:46.454600 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
395 07:15:46.454939 cs0 DataBus test pass
396 07:15:46.460202 cs1 DataBus test pass
397 07:15:46.460536 cs0 AddrBus test pass
398 07:15:46.460759 cs1 AddrBus test pass
399 07:15:46.460972
400 07:15:46.465777 100bdlr_step_size ps== 478
401 07:15:46.466135 result report
402 07:15:46.471376 boot times 0Enable ddr reg access
403 07:15:46.476922 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
404 07:15:46.490665 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
405 07:15:47.145781 bl2z: ptr: 05129330, size: 00001e40
406 07:15:47.153241 0.0;M3 CHK:0;cm4_sp_mode 0
407 07:15:47.153669 MVN_1=0x00000000
408 07:15:47.153914 MVN_2=0x00000000
409 07:15:47.164564 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
410 07:15:47.164971 OPS=0x04
411 07:15:47.165203 ring efuse init
412 07:15:47.170296 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
413 07:15:47.170647 [0.017319 Inits done]
414 07:15:47.170870 secure task start!
415 07:15:47.178034 high task start!
416 07:15:47.178373 low task start!
417 07:15:47.178593 run into bl31
418 07:15:47.186675 NOTICE: BL31: v1.3(release):4fc40b1
419 07:15:47.194462 NOTICE: BL31: Built : 15:57:33, May 22 2019
420 07:15:47.194827 NOTICE: BL31: G12A normal boot!
421 07:15:47.209930 NOTICE: BL31: BL33 decompress pass
422 07:15:47.215590 ERROR: Error initializing runtime service opteed_fast
423 07:15:49.866789 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
424 07:15:49.867223 bl2_stage_init 0x01
425 07:15:49.867454 bl2_stage_init 0x81
426 07:15:49.872573 hw id: 0x0000 - pwm id 0x01
427 07:15:49.872994 bl2_stage_init 0xc1
428 07:15:49.878059 bl2_stage_init 0x02
429 07:15:49.878641
430 07:15:49.878880 L0:00000000
431 07:15:49.879106 L1:00000703
432 07:15:49.879329 L2:00008067
433 07:15:49.879534 L3:15000000
434 07:15:49.884342 S1:00000000
435 07:15:49.886490 B2:20282000
436 07:15:49.886737 B1:a0f83180
437 07:15:49.886952
438 07:15:49.887166 TE: 70678
439 07:15:49.887377
440 07:15:49.889090 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
441 07:15:49.889441
442 07:15:49.894887 Board ID = 1
443 07:15:49.895272 Set cpu clk to 24M
444 07:15:49.895480 Set clk81 to 24M
445 07:15:49.900394 Use GP1_pll as DSU clk.
446 07:15:49.900733 DSU clk: 1200 Mhz
447 07:15:49.900939 CPU clk: 1200 MHz
448 07:15:49.905814 Set clk81 to 166.6M
449 07:15:49.911399 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
450 07:15:49.911725 board id: 1
451 07:15:49.918783 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
452 07:15:49.929321 fw parse done
453 07:15:49.935313 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
454 07:15:49.977850 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
455 07:15:49.988895 PIEI prepare done
456 07:15:49.989501 fastboot data load
457 07:15:49.989961 fastboot data verify
458 07:15:49.994566 verify result: 266
459 07:15:50.000149 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
460 07:15:50.000933 LPDDR4 probe
461 07:15:50.001560 ddr clk to 1584MHz
462 07:15:50.007941 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
463 07:15:50.045308
464 07:15:50.045963 dmc_version 0001
465 07:15:50.051833 Check phy result
466 07:15:50.057732 INFO : End of CA training
467 07:15:50.058234 INFO : End of initialization
468 07:15:50.063405 INFO : Training has run successfully!
469 07:15:50.063938 Check phy result
470 07:15:50.068914 INFO : End of initialization
471 07:15:50.069439 INFO : End of read enable training
472 07:15:50.074518 INFO : End of fine write leveling
473 07:15:50.080137 INFO : End of Write leveling coarse delay
474 07:15:50.080640 INFO : Training has run successfully!
475 07:15:50.081106 Check phy result
476 07:15:50.085715 INFO : End of initialization
477 07:15:50.086217 INFO : End of read dq deskew training
478 07:15:50.091359 INFO : End of MPR read delay center optimization
479 07:15:50.096906 INFO : End of write delay center optimization
480 07:15:50.102500 INFO : End of read delay center optimization
481 07:15:50.102993 INFO : End of max read latency training
482 07:15:50.108126 INFO : Training has run successfully!
483 07:15:50.108625 1D training succeed
484 07:15:50.117304 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
485 07:15:50.164920 Check phy result
486 07:15:50.165458 INFO : End of initialization
487 07:15:50.187258 INFO : End of 2D read delay Voltage center optimization
488 07:15:50.206521 INFO : End of 2D read delay Voltage center optimization
489 07:15:50.258332 INFO : End of 2D write delay Voltage center optimization
490 07:15:50.307592 INFO : End of 2D write delay Voltage center optimization
491 07:15:50.313053 INFO : Training has run successfully!
492 07:15:50.313570
493 07:15:50.314040 channel==0
494 07:15:50.318647 RxClkDly_Margin_A0==78 ps 8
495 07:15:50.319141 TxDqDly_Margin_A0==98 ps 10
496 07:15:50.324253 RxClkDly_Margin_A1==88 ps 9
497 07:15:50.324746 TxDqDly_Margin_A1==98 ps 10
498 07:15:50.325211 TrainedVREFDQ_A0==74
499 07:15:50.329861 TrainedVREFDQ_A1==74
500 07:15:50.330361 VrefDac_Margin_A0==23
501 07:15:50.330825 DeviceVref_Margin_A0==40
502 07:15:50.335440 VrefDac_Margin_A1==23
503 07:15:50.335932 DeviceVref_Margin_A1==40
504 07:15:50.336438
505 07:15:50.336898
506 07:15:50.341038 channel==1
507 07:15:50.341531 RxClkDly_Margin_A0==88 ps 9
508 07:15:50.341994 TxDqDly_Margin_A0==88 ps 9
509 07:15:50.346662 RxClkDly_Margin_A1==88 ps 9
510 07:15:50.347174 TxDqDly_Margin_A1==88 ps 9
511 07:15:50.352234 TrainedVREFDQ_A0==77
512 07:15:50.352730 TrainedVREFDQ_A1==75
513 07:15:50.353192 VrefDac_Margin_A0==23
514 07:15:50.357834 DeviceVref_Margin_A0==37
515 07:15:50.358329 VrefDac_Margin_A1==22
516 07:15:50.363436 DeviceVref_Margin_A1==39
517 07:15:50.363930
518 07:15:50.364434 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
519 07:15:50.364895
520 07:15:50.397052 soc_vref_reg_value 0x 0000001a 00000019 00000018 00000017 00000018 00000015 00000019 00000016 00000018 00000017 00000017 00000018 00000017 00000018 00000018 00000019 00000018 00000017 00000018 00000015 00000018 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001c 00000017 00000016 00000017 dram_vref_reg_value 0x 00000061
521 07:15:50.397617 2D training succeed
522 07:15:50.402661 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
523 07:15:50.408268 auto size-- 65535DDR cs0 size: 2048MB
524 07:15:50.408764 DDR cs1 size: 2048MB
525 07:15:50.413847 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
526 07:15:50.414343 cs0 DataBus test pass
527 07:15:50.419480 cs1 DataBus test pass
528 07:15:50.419976 cs0 AddrBus test pass
529 07:15:50.420488 cs1 AddrBus test pass
530 07:15:50.420943
531 07:15:50.425053 100bdlr_step_size ps== 478
532 07:15:50.425563 result report
533 07:15:50.430662 boot times 0Enable ddr reg access
534 07:15:50.435820 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
535 07:15:50.448696 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
536 07:15:51.104818 bl2z: ptr: 05129330, size: 00001e40
537 07:15:51.111038 0.0;M3 CHK:0;cm4_sp_mode 0
538 07:15:51.111573 MVN_1=0x00000000
539 07:15:51.112095 MVN_2=0x00000000
540 07:15:51.122500 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
541 07:15:51.123042 OPS=0x04
542 07:15:51.123509 ring efuse init
543 07:15:51.125514 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
544 07:15:51.131649 [0.017310 Inits done]
545 07:15:51.132198 secure task start!
546 07:15:51.132663 high task start!
547 07:15:51.133115 low task start!
548 07:15:51.135832 run into bl31
549 07:15:51.144511 NOTICE: BL31: v1.3(release):4fc40b1
550 07:15:51.152275 NOTICE: BL31: Built : 15:57:33, May 22 2019
551 07:15:51.152788 NOTICE: BL31: G12A normal boot!
552 07:15:51.167879 NOTICE: BL31: BL33 decompress pass
553 07:15:51.173584 ERROR: Error initializing runtime service opteed_fast
554 07:15:52.569776 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
555 07:15:52.570220 bl2_stage_init 0x01
556 07:15:52.570453 bl2_stage_init 0x81
557 07:15:52.575390 hw id: 0x0000 - pwm id 0x01
558 07:15:52.575874 bl2_stage_init 0xc1
559 07:15:52.580823 bl2_stage_init 0x02
560 07:15:52.581399
561 07:15:52.581872 L0:00000000
562 07:15:52.582330 L1:00000703
563 07:15:52.582778 L2:00008067
564 07:15:52.583231 L3:15000000
565 07:15:52.586365 S1:00000000
566 07:15:52.586924 B2:20282000
567 07:15:52.587388 B1:a0f83180
568 07:15:52.587842
569 07:15:52.588342 TE: 72273
570 07:15:52.588796
571 07:15:52.591951 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
572 07:15:52.597549
573 07:15:52.598117 Board ID = 1
574 07:15:52.598585 Set cpu clk to 24M
575 07:15:52.599039 Set clk81 to 24M
576 07:15:52.603178 Use GP1_pll as DSU clk.
577 07:15:52.603738 DSU clk: 1200 Mhz
578 07:15:52.604244 CPU clk: 1200 MHz
579 07:15:52.608752 Set clk81 to 166.6M
580 07:15:52.614366 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
581 07:15:52.614929 board id: 1
582 07:15:52.621926 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
583 07:15:52.632826 fw parse done
584 07:15:52.638886 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
585 07:15:52.681860 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
586 07:15:52.693021 PIEI prepare done
587 07:15:52.693609 fastboot data load
588 07:15:52.694086 fastboot data verify
589 07:15:52.698605 verify result: 266
590 07:15:52.704218 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
591 07:15:52.704782 LPDDR4 probe
592 07:15:52.705247 ddr clk to 1584MHz
593 07:15:52.712230 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
594 07:15:52.749820
595 07:15:52.750391 dmc_version 0001
596 07:15:52.756882 Check phy result
597 07:15:52.762869 INFO : End of CA training
598 07:15:52.763396 INFO : End of initialization
599 07:15:52.768479 INFO : Training has run successfully!
600 07:15:52.769000 Check phy result
601 07:15:52.774066 INFO : End of initialization
602 07:15:52.774580 INFO : End of read enable training
603 07:15:52.779678 INFO : End of fine write leveling
604 07:15:52.785265 INFO : End of Write leveling coarse delay
605 07:15:52.785792 INFO : Training has run successfully!
606 07:15:52.786256 Check phy result
607 07:15:52.790833 INFO : End of initialization
608 07:15:52.791351 INFO : End of read dq deskew training
609 07:15:52.796447 INFO : End of MPR read delay center optimization
610 07:15:52.802056 INFO : End of write delay center optimization
611 07:15:52.807706 INFO : End of read delay center optimization
612 07:15:52.808274 INFO : End of max read latency training
613 07:15:52.813256 INFO : Training has run successfully!
614 07:15:52.813774 1D training succeed
615 07:15:52.822419 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
616 07:15:52.870776 Check phy result
617 07:15:52.871316 INFO : End of initialization
618 07:15:52.898184 INFO : End of 2D read delay Voltage center optimization
619 07:15:52.921425 INFO : End of 2D read delay Voltage center optimization
620 07:15:52.979077 INFO : End of 2D write delay Voltage center optimization
621 07:15:53.032985 INFO : End of 2D write delay Voltage center optimization
622 07:15:53.038624 INFO : Training has run successfully!
623 07:15:53.039145
624 07:15:53.039607 channel==0
625 07:15:53.044245 RxClkDly_Margin_A0==78 ps 8
626 07:15:53.044768 TxDqDly_Margin_A0==98 ps 10
627 07:15:53.049828 RxClkDly_Margin_A1==88 ps 9
628 07:15:53.050354 TxDqDly_Margin_A1==98 ps 10
629 07:15:53.050818 TrainedVREFDQ_A0==74
630 07:15:53.055410 TrainedVREFDQ_A1==74
631 07:15:53.055929 VrefDac_Margin_A0==25
632 07:15:53.056429 DeviceVref_Margin_A0==40
633 07:15:53.061014 VrefDac_Margin_A1==23
634 07:15:53.061532 DeviceVref_Margin_A1==40
635 07:15:53.061983
636 07:15:53.062433
637 07:15:53.066604 channel==1
638 07:15:53.067123 RxClkDly_Margin_A0==78 ps 8
639 07:15:53.067586 TxDqDly_Margin_A0==88 ps 9
640 07:15:53.072240 RxClkDly_Margin_A1==88 ps 9
641 07:15:53.072762 TxDqDly_Margin_A1==88 ps 9
642 07:15:53.077824 TrainedVREFDQ_A0==77
643 07:15:53.078345 TrainedVREFDQ_A1==78
644 07:15:53.078802 VrefDac_Margin_A0==22
645 07:15:53.083407 DeviceVref_Margin_A0==37
646 07:15:53.083947 VrefDac_Margin_A1==21
647 07:15:53.089013 DeviceVref_Margin_A1==36
648 07:15:53.089538
649 07:15:53.089996 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
650 07:15:53.090451
651 07:15:53.122577 soc_vref_reg_value 0x 00000019 00000019 00000018 00000017 00000018 00000016 00000018 00000016 00000018 00000017 00000017 00000017 00000017 00000018 00000018 00000019 00000018 00000017 00000019 00000014 00000017 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001b 00000017 00000016 00000016 dram_vref_reg_value 0x 00000062
652 07:15:53.123174 2D training succeed
653 07:15:53.128262 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
654 07:15:53.133816 auto size-- 65535DDR cs0 size: 2048MB
655 07:15:53.134338 DDR cs1 size: 2048MB
656 07:15:53.139415 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
657 07:15:53.139934 cs0 DataBus test pass
658 07:15:53.145021 cs1 DataBus test pass
659 07:15:53.145538 cs0 AddrBus test pass
660 07:15:53.145998 cs1 AddrBus test pass
661 07:15:53.146445
662 07:15:53.150619 100bdlr_step_size ps== 478
663 07:15:53.151154 result report
664 07:15:53.156275 boot times 0Enable ddr reg access
665 07:15:53.161389 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
666 07:15:53.175196 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
667 07:15:53.834744 bl2z: ptr: 05129330, size: 00001e40
668 07:15:53.843546 0.0;M3 CHK:0;cm4_sp_mode 0
669 07:15:53.844118 MVN_1=0x00000000
670 07:15:53.844579 MVN_2=0x00000000
671 07:15:53.854969 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
672 07:15:53.855495 OPS=0x04
673 07:15:53.855960 ring efuse init
674 07:15:53.860635 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
675 07:15:53.861158 [0.017354 Inits done]
676 07:15:53.861616 secure task start!
677 07:15:53.867847 high task start!
678 07:15:53.868385 low task start!
679 07:15:53.868842 run into bl31
680 07:15:53.876487 NOTICE: BL31: v1.3(release):4fc40b1
681 07:15:53.884288 NOTICE: BL31: Built : 15:57:33, May 22 2019
682 07:15:53.884812 NOTICE: BL31: G12A normal boot!
683 07:15:53.899893 NOTICE: BL31: BL33 decompress pass
684 07:15:53.905579 ERROR: Error initializing runtime service opteed_fast
685 07:15:54.701086
686 07:15:54.701710
687 07:15:54.706471 U-Boot 2024.01-rc4+ (Dec 14 2023 - 02:26:00 -0500) Libre Computer AML-S905D3-CC
688 07:15:54.707006
689 07:15:54.709956 Model: Libre Computer AML-S905D3-CC Solitude
690 07:15:54.856999 SoC: Amlogic Meson SM1 (S905D3) Revision 2b:c (4:2)
691 07:15:54.872402 DRAM: 2 GiB (effective 3.8 GiB)
692 07:15:54.973472 Core: 406 devices, 33 uclasses, devicetree: separate
693 07:15:54.979421 WDT: Not starting watchdog@f0d0
694 07:15:55.004317 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
695 07:15:55.016472 Loading Environment from FAT... Card did not respond to voltage select! : -110
696 07:15:55.021501 ** Bad device specification mmc 0 **
697 07:15:55.031741 Card did not respond to voltage select! : -110
698 07:15:55.039389 ** Bad device specification mmc 0 **
699 07:15:55.039960 Couldn't find partition mmc 0
700 07:15:55.047728 Card did not respond to voltage select! : -110
701 07:15:55.053180 ** Bad device specification mmc 0 **
702 07:15:55.053714 Couldn't find partition mmc 0
703 07:15:55.058289 Error: could not access storage.
704 07:15:55.354672 Net: eth0: ethernet@ff3f0000
705 07:15:55.355274 starting USB...
706 07:15:55.599460 Bus usb@ff500000: Register 3000140 NbrPorts 3
707 07:15:55.600084 Starting the controller
708 07:15:55.606378 USB XHCI 1.10
709 07:15:57.160225 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
710 07:15:57.168392 scanning usb for storage devices... 0 Storage Device(s) found
712 07:15:57.219453 Hit any key to stop autoboot: 1
713 07:15:57.220249 end: 2.4.2 bootloader-interrupt (duration 00:00:19) [common]
714 07:15:57.220981 start: 2.4.3 bootloader-commands (timeout 00:04:41) [common]
715 07:15:57.221532 Setting prompt string to ['=>']
716 07:15:57.222074 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:41)
717 07:15:57.234429 0
718 07:15:57.235385 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
720 07:15:57.336840 => setenv autoload no
721 07:15:57.337690 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
722 07:15:57.343114 setenv autoload no
724 07:15:57.444821 => setenv initrd_high 0xffffffff
725 07:15:57.445611 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
726 07:15:57.450238 setenv initrd_high 0xffffffff
728 07:15:57.551827 => setenv fdt_high 0xffffffff
729 07:15:57.552667 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
730 07:15:57.557269 setenv fdt_high 0xffffffff
732 07:15:57.658908 => dhcp
733 07:15:57.659705 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
734 07:15:57.663025 dhcp
735 07:15:58.770086 ethernet@ff3f0000 Waiting for PHY auto negotiation to complete.. done
736 07:15:58.770764 Speed: 1000, full duplex
737 07:15:58.771260 BOOTP broadcast 1
738 07:15:58.793968 DHCP client bound to address 192.168.6.21 (24 ms)
740 07:15:58.895588 => setenv serverip 192.168.6.2
741 07:15:58.896625 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
742 07:15:58.901325 setenv serverip 192.168.6.2
744 07:15:59.003217 => tftpboot 0x01080000 932978/tftp-deploy-1aqzywbl/kernel/uImage
745 07:15:59.004072 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:39)
746 07:15:59.010785 tftpboot 0x01080000 932978/tftp-deploy-1aqzywbl/kernel/uImage
747 07:15:59.011381 Speed: 1000, full duplex
748 07:15:59.011861 Using ethernet@ff3f0000 device
749 07:15:59.016287 TFTP from server 192.168.6.2; our IP address is 192.168.6.21
750 07:15:59.021785 Filename '932978/tftp-deploy-1aqzywbl/kernel/uImage'.
751 07:15:59.025786 Load address: 0x1080000
752 07:16:03.656605 Loading: *#################################################
753 07:16:03.657061 TFTP error: trying to overwrite reserved memory...
755 07:16:03.658504 end: 2.4.3 bootloader-commands (duration 00:00:06) [common]
758 07:16:03.660364 end: 2.4 uboot-commands (duration 00:00:25) [common]
760 07:16:03.661716 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'TFTP error: trying to overwrite reserved memory' (12)'
762 07:16:03.662780 end: 2 uboot-action (duration 00:00:25) [common]
764 07:16:03.664490 Cleaning after the job
765 07:16:03.665108 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/932978/tftp-deploy-1aqzywbl/ramdisk
766 07:16:03.682412 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/932978/tftp-deploy-1aqzywbl/kernel
767 07:16:03.716031 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/932978/tftp-deploy-1aqzywbl/dtb
768 07:16:03.716863 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/932978/tftp-deploy-1aqzywbl/modules
769 07:16:03.749659 start: 4.1 power-off (timeout 00:00:30) [common]
770 07:16:03.750348 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=solitude-01'
771 07:16:03.782856 >> OK - accepted request
772 07:16:03.785061 Returned 0 in 0 seconds
773 07:16:03.885871 end: 4.1 power-off (duration 00:00:00) [common]
775 07:16:03.886939 start: 4.2 read-feedback (timeout 00:10:00) [common]
776 07:16:03.887642 Listened to connection for namespace 'common' for up to 1s
777 07:16:04.888680 Finalising connection for namespace 'common'
778 07:16:04.889432 Disconnecting from shell: Finalise
779 07:16:04.889939 =>
780 07:16:04.990871 end: 4.2 read-feedback (duration 00:00:01) [common]
781 07:16:04.991522 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/932978
782 07:16:05.389994 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/932978
783 07:16:05.390603 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.