Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 07:15:05.501710 lava-dispatcher, installed at version: 2024.01
2 07:15:05.502484 start: 0 validate
3 07:15:05.502960 Start time: 2024-11-04 07:15:05.502931+00:00 (UTC)
4 07:15:05.503511 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 07:15:05.504063 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 07:15:05.542463 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 07:15:05.543018 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241104%2Farm64%2Fdefconfig%2Bkselftest%2Fgcc-12%2Fkernel%2FImage exists
8 07:15:06.579033 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 07:15:06.579668 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241104%2Farm64%2Fdefconfig%2Bkselftest%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 07:15:14.664707 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 07:15:14.665225 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 07:15:14.700214 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 07:15:14.701006 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241104%2Farm64%2Fdefconfig%2Bkselftest%2Fgcc-12%2Fmodules.tar.xz exists
14 07:15:16.753811 validate duration: 11.25
16 07:15:16.754758 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 07:15:16.755123 start: 1.1 download-retry (timeout 00:10:00) [common]
18 07:15:16.755470 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 07:15:16.756120 Not decompressing ramdisk as can be used compressed.
20 07:15:16.756623 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm/20240313.0/arm64/initrd.cpio.gz
21 07:15:16.756932 saving as /var/lib/lava/dispatcher/tmp/932973/tftp-deploy-evtse3a3/ramdisk/initrd.cpio.gz
22 07:15:16.757286 total size: 5628182 (5 MB)
23 07:15:16.810764 progress 0 % (0 MB)
24 07:15:16.815057 progress 5 % (0 MB)
25 07:15:16.819513 progress 10 % (0 MB)
26 07:15:16.823508 progress 15 % (0 MB)
27 07:15:16.827918 progress 20 % (1 MB)
28 07:15:16.831911 progress 25 % (1 MB)
29 07:15:16.836292 progress 30 % (1 MB)
30 07:15:16.840598 progress 35 % (1 MB)
31 07:15:16.844534 progress 40 % (2 MB)
32 07:15:16.848908 progress 45 % (2 MB)
33 07:15:16.852714 progress 50 % (2 MB)
34 07:15:16.856941 progress 55 % (2 MB)
35 07:15:16.861202 progress 60 % (3 MB)
36 07:15:16.864963 progress 65 % (3 MB)
37 07:15:16.869110 progress 70 % (3 MB)
38 07:15:16.872890 progress 75 % (4 MB)
39 07:15:16.877121 progress 80 % (4 MB)
40 07:15:16.880773 progress 85 % (4 MB)
41 07:15:16.884841 progress 90 % (4 MB)
42 07:15:16.888865 progress 95 % (5 MB)
43 07:15:16.892509 progress 100 % (5 MB)
44 07:15:16.893282 5 MB downloaded in 0.14 s (39.46 MB/s)
45 07:15:16.893926 end: 1.1.1 http-download (duration 00:00:00) [common]
47 07:15:16.894915 end: 1.1 download-retry (duration 00:00:00) [common]
48 07:15:16.895259 start: 1.2 download-retry (timeout 00:10:00) [common]
49 07:15:16.895572 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 07:15:16.896688 downloading http://storage.kernelci.org/next/master/next-20241104/arm64/defconfig+kselftest/gcc-12/kernel/Image
51 07:15:16.897034 saving as /var/lib/lava/dispatcher/tmp/932973/tftp-deploy-evtse3a3/kernel/Image
52 07:15:16.897285 total size: 66830848 (63 MB)
53 07:15:16.897521 No compression specified
54 07:15:16.944794 progress 0 % (0 MB)
55 07:15:16.987380 progress 5 % (3 MB)
56 07:15:17.033789 progress 10 % (6 MB)
57 07:15:17.086906 progress 15 % (9 MB)
58 07:15:17.131238 progress 20 % (12 MB)
59 07:15:17.173779 progress 25 % (15 MB)
60 07:15:17.223172 progress 30 % (19 MB)
61 07:15:17.268263 progress 35 % (22 MB)
62 07:15:17.313075 progress 40 % (25 MB)
63 07:15:17.356620 progress 45 % (28 MB)
64 07:15:17.400625 progress 50 % (31 MB)
65 07:15:17.445139 progress 55 % (35 MB)
66 07:15:17.490113 progress 60 % (38 MB)
67 07:15:17.537773 progress 65 % (41 MB)
68 07:15:17.580824 progress 70 % (44 MB)
69 07:15:17.622664 progress 75 % (47 MB)
70 07:15:17.666172 progress 80 % (51 MB)
71 07:15:17.711228 progress 85 % (54 MB)
72 07:15:17.755599 progress 90 % (57 MB)
73 07:15:17.800489 progress 95 % (60 MB)
74 07:15:17.842769 progress 100 % (63 MB)
75 07:15:17.843475 63 MB downloaded in 0.95 s (67.36 MB/s)
76 07:15:17.843955 end: 1.2.1 http-download (duration 00:00:01) [common]
78 07:15:17.844816 end: 1.2 download-retry (duration 00:00:01) [common]
79 07:15:17.845095 start: 1.3 download-retry (timeout 00:09:59) [common]
80 07:15:17.845363 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 07:15:17.846093 downloading http://storage.kernelci.org/next/master/next-20241104/arm64/defconfig+kselftest/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
82 07:15:17.846407 saving as /var/lib/lava/dispatcher/tmp/932973/tftp-deploy-evtse3a3/dtb/meson-g12b-a311d-libretech-cc.dtb
83 07:15:17.846627 total size: 54703 (0 MB)
84 07:15:17.846847 No compression specified
85 07:15:17.899445 progress 59 % (0 MB)
86 07:15:17.900349 progress 100 % (0 MB)
87 07:15:17.900910 0 MB downloaded in 0.05 s (0.96 MB/s)
88 07:15:17.901418 end: 1.3.1 http-download (duration 00:00:00) [common]
90 07:15:17.902239 end: 1.3 download-retry (duration 00:00:00) [common]
91 07:15:17.902507 start: 1.4 download-retry (timeout 00:09:59) [common]
92 07:15:17.902768 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 07:15:17.903404 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm/20240313.0/arm64/full.rootfs.tar.xz
94 07:15:17.903679 saving as /var/lib/lava/dispatcher/tmp/932973/tftp-deploy-evtse3a3/nfsrootfs/full.rootfs.tar
95 07:15:17.903903 total size: 107552908 (102 MB)
96 07:15:17.904158 Using unxz to decompress xz
97 07:15:17.945201 progress 0 % (0 MB)
98 07:15:18.625165 progress 5 % (5 MB)
99 07:15:19.354934 progress 10 % (10 MB)
100 07:15:20.080007 progress 15 % (15 MB)
101 07:15:20.835306 progress 20 % (20 MB)
102 07:15:21.405888 progress 25 % (25 MB)
103 07:15:22.027872 progress 30 % (30 MB)
104 07:15:22.770969 progress 35 % (35 MB)
105 07:15:23.115965 progress 40 % (41 MB)
106 07:15:23.541036 progress 45 % (46 MB)
107 07:15:24.238771 progress 50 % (51 MB)
108 07:15:24.933627 progress 55 % (56 MB)
109 07:15:25.691973 progress 60 % (61 MB)
110 07:15:26.461597 progress 65 % (66 MB)
111 07:15:27.201979 progress 70 % (71 MB)
112 07:15:27.972162 progress 75 % (76 MB)
113 07:15:28.659667 progress 80 % (82 MB)
114 07:15:29.371844 progress 85 % (87 MB)
115 07:15:30.119646 progress 90 % (92 MB)
116 07:15:30.906051 progress 95 % (97 MB)
117 07:15:31.662686 progress 100 % (102 MB)
118 07:15:31.675576 102 MB downloaded in 13.77 s (7.45 MB/s)
119 07:15:31.676221 end: 1.4.1 http-download (duration 00:00:14) [common]
121 07:15:31.677126 end: 1.4 download-retry (duration 00:00:14) [common]
122 07:15:31.677417 start: 1.5 download-retry (timeout 00:09:45) [common]
123 07:15:31.677712 start: 1.5.1 http-download (timeout 00:09:45) [common]
124 07:15:31.678245 downloading http://storage.kernelci.org/next/master/next-20241104/arm64/defconfig+kselftest/gcc-12/modules.tar.xz
125 07:15:31.678511 saving as /var/lib/lava/dispatcher/tmp/932973/tftp-deploy-evtse3a3/modules/modules.tar
126 07:15:31.678727 total size: 16280944 (15 MB)
127 07:15:31.678955 Using unxz to decompress xz
128 07:15:31.715338 progress 0 % (0 MB)
129 07:15:31.821165 progress 5 % (0 MB)
130 07:15:31.941823 progress 10 % (1 MB)
131 07:15:32.067196 progress 15 % (2 MB)
132 07:15:32.198565 progress 20 % (3 MB)
133 07:15:32.341844 progress 25 % (3 MB)
134 07:15:32.454588 progress 30 % (4 MB)
135 07:15:32.561398 progress 35 % (5 MB)
136 07:15:32.677650 progress 40 % (6 MB)
137 07:15:32.785225 progress 45 % (7 MB)
138 07:15:32.902060 progress 50 % (7 MB)
139 07:15:33.016167 progress 55 % (8 MB)
140 07:15:33.134665 progress 60 % (9 MB)
141 07:15:33.256250 progress 65 % (10 MB)
142 07:15:33.380050 progress 70 % (10 MB)
143 07:15:33.504646 progress 75 % (11 MB)
144 07:15:33.626129 progress 80 % (12 MB)
145 07:15:33.741647 progress 85 % (13 MB)
146 07:15:33.854863 progress 90 % (14 MB)
147 07:15:33.959860 progress 95 % (14 MB)
148 07:15:34.076252 progress 100 % (15 MB)
149 07:15:34.089920 15 MB downloaded in 2.41 s (6.44 MB/s)
150 07:15:34.090535 end: 1.5.1 http-download (duration 00:00:02) [common]
152 07:15:34.091953 end: 1.5 download-retry (duration 00:00:02) [common]
153 07:15:34.092636 start: 1.6 prepare-tftp-overlay (timeout 00:09:43) [common]
154 07:15:34.093214 start: 1.6.1 extract-nfsrootfs (timeout 00:09:43) [common]
155 07:15:44.064916 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/932973/extract-nfsrootfs-ncczzenc
156 07:15:44.065523 end: 1.6.1 extract-nfsrootfs (duration 00:00:10) [common]
157 07:15:44.065838 start: 1.6.2 lava-overlay (timeout 00:09:33) [common]
158 07:15:44.066483 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/932973/lava-overlay-yvyhnixt
159 07:15:44.066951 makedir: /var/lib/lava/dispatcher/tmp/932973/lava-overlay-yvyhnixt/lava-932973/bin
160 07:15:44.067311 makedir: /var/lib/lava/dispatcher/tmp/932973/lava-overlay-yvyhnixt/lava-932973/tests
161 07:15:44.067663 makedir: /var/lib/lava/dispatcher/tmp/932973/lava-overlay-yvyhnixt/lava-932973/results
162 07:15:44.068050 Creating /var/lib/lava/dispatcher/tmp/932973/lava-overlay-yvyhnixt/lava-932973/bin/lava-add-keys
163 07:15:44.068644 Creating /var/lib/lava/dispatcher/tmp/932973/lava-overlay-yvyhnixt/lava-932973/bin/lava-add-sources
164 07:15:44.069201 Creating /var/lib/lava/dispatcher/tmp/932973/lava-overlay-yvyhnixt/lava-932973/bin/lava-background-process-start
165 07:15:44.069782 Creating /var/lib/lava/dispatcher/tmp/932973/lava-overlay-yvyhnixt/lava-932973/bin/lava-background-process-stop
166 07:15:44.070379 Creating /var/lib/lava/dispatcher/tmp/932973/lava-overlay-yvyhnixt/lava-932973/bin/lava-common-functions
167 07:15:44.070954 Creating /var/lib/lava/dispatcher/tmp/932973/lava-overlay-yvyhnixt/lava-932973/bin/lava-echo-ipv4
168 07:15:44.071493 Creating /var/lib/lava/dispatcher/tmp/932973/lava-overlay-yvyhnixt/lava-932973/bin/lava-install-packages
169 07:15:44.072057 Creating /var/lib/lava/dispatcher/tmp/932973/lava-overlay-yvyhnixt/lava-932973/bin/lava-installed-packages
170 07:15:44.072588 Creating /var/lib/lava/dispatcher/tmp/932973/lava-overlay-yvyhnixt/lava-932973/bin/lava-os-build
171 07:15:44.073138 Creating /var/lib/lava/dispatcher/tmp/932973/lava-overlay-yvyhnixt/lava-932973/bin/lava-probe-channel
172 07:15:44.073669 Creating /var/lib/lava/dispatcher/tmp/932973/lava-overlay-yvyhnixt/lava-932973/bin/lava-probe-ip
173 07:15:44.074208 Creating /var/lib/lava/dispatcher/tmp/932973/lava-overlay-yvyhnixt/lava-932973/bin/lava-target-ip
174 07:15:44.074744 Creating /var/lib/lava/dispatcher/tmp/932973/lava-overlay-yvyhnixt/lava-932973/bin/lava-target-mac
175 07:15:44.075264 Creating /var/lib/lava/dispatcher/tmp/932973/lava-overlay-yvyhnixt/lava-932973/bin/lava-target-storage
176 07:15:44.075788 Creating /var/lib/lava/dispatcher/tmp/932973/lava-overlay-yvyhnixt/lava-932973/bin/lava-test-case
177 07:15:44.076358 Creating /var/lib/lava/dispatcher/tmp/932973/lava-overlay-yvyhnixt/lava-932973/bin/lava-test-event
178 07:15:44.076957 Creating /var/lib/lava/dispatcher/tmp/932973/lava-overlay-yvyhnixt/lava-932973/bin/lava-test-feedback
179 07:15:44.077493 Creating /var/lib/lava/dispatcher/tmp/932973/lava-overlay-yvyhnixt/lava-932973/bin/lava-test-raise
180 07:15:44.078017 Creating /var/lib/lava/dispatcher/tmp/932973/lava-overlay-yvyhnixt/lava-932973/bin/lava-test-reference
181 07:15:44.078554 Creating /var/lib/lava/dispatcher/tmp/932973/lava-overlay-yvyhnixt/lava-932973/bin/lava-test-runner
182 07:15:44.079089 Creating /var/lib/lava/dispatcher/tmp/932973/lava-overlay-yvyhnixt/lava-932973/bin/lava-test-set
183 07:15:44.079606 Creating /var/lib/lava/dispatcher/tmp/932973/lava-overlay-yvyhnixt/lava-932973/bin/lava-test-shell
184 07:15:44.080159 Updating /var/lib/lava/dispatcher/tmp/932973/lava-overlay-yvyhnixt/lava-932973/bin/lava-install-packages (oe)
185 07:15:44.080745 Updating /var/lib/lava/dispatcher/tmp/932973/lava-overlay-yvyhnixt/lava-932973/bin/lava-installed-packages (oe)
186 07:15:44.081226 Creating /var/lib/lava/dispatcher/tmp/932973/lava-overlay-yvyhnixt/lava-932973/environment
187 07:15:44.081625 LAVA metadata
188 07:15:44.081901 - LAVA_JOB_ID=932973
189 07:15:44.082133 - LAVA_DISPATCHER_IP=192.168.6.2
190 07:15:44.082509 start: 1.6.2.1 ssh-authorize (timeout 00:09:33) [common]
191 07:15:44.083495 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
192 07:15:44.083822 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:33) [common]
193 07:15:44.084074 skipped lava-vland-overlay
194 07:15:44.084342 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
195 07:15:44.084618 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:33) [common]
196 07:15:44.084855 skipped lava-multinode-overlay
197 07:15:44.085114 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
198 07:15:44.085379 start: 1.6.2.4 test-definition (timeout 00:09:33) [common]
199 07:15:44.085647 Loading test definitions
200 07:15:44.085936 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:33) [common]
201 07:15:44.086170 Using /lava-932973 at stage 0
202 07:15:44.087404 uuid=932973_1.6.2.4.1 testdef=None
203 07:15:44.087723 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
204 07:15:44.088033 start: 1.6.2.4.2 test-overlay (timeout 00:09:33) [common]
205 07:15:44.089890 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
207 07:15:44.090701 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:33) [common]
208 07:15:44.093053 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
210 07:15:44.093916 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:33) [common]
211 07:15:44.096168 runner path: /var/lib/lava/dispatcher/tmp/932973/lava-overlay-yvyhnixt/lava-932973/0/tests/0_dmesg test_uuid 932973_1.6.2.4.1
212 07:15:44.096798 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
214 07:15:44.097622 Creating lava-test-runner.conf files
215 07:15:44.097833 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/932973/lava-overlay-yvyhnixt/lava-932973/0 for stage 0
216 07:15:44.098204 - 0_dmesg
217 07:15:44.098572 end: 1.6.2.4 test-definition (duration 00:00:00) [common]
218 07:15:44.098879 start: 1.6.2.5 compress-overlay (timeout 00:09:33) [common]
219 07:15:44.121157 end: 1.6.2.5 compress-overlay (duration 00:00:00) [common]
220 07:15:44.121555 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:09:33) [common]
221 07:15:44.121814 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
222 07:15:44.122081 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
223 07:15:44.122341 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:33) [common]
224 07:15:44.742434 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:01) [common]
225 07:15:44.742907 start: 1.6.4 extract-modules (timeout 00:09:32) [common]
226 07:15:44.743175 extracting modules file /var/lib/lava/dispatcher/tmp/932973/tftp-deploy-evtse3a3/modules/modules.tar to /var/lib/lava/dispatcher/tmp/932973/extract-nfsrootfs-ncczzenc
227 07:15:46.323417 extracting modules file /var/lib/lava/dispatcher/tmp/932973/tftp-deploy-evtse3a3/modules/modules.tar to /var/lib/lava/dispatcher/tmp/932973/extract-overlay-ramdisk-3osj89pf/ramdisk
228 07:15:47.959961 end: 1.6.4 extract-modules (duration 00:00:03) [common]
229 07:15:47.960502 start: 1.6.5 apply-overlay-tftp (timeout 00:09:29) [common]
230 07:15:47.960814 [common] Applying overlay to NFS
231 07:15:47.961049 [common] Applying overlay /var/lib/lava/dispatcher/tmp/932973/compress-overlay-8i9znzcu/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/932973/extract-nfsrootfs-ncczzenc
232 07:15:47.993011 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
233 07:15:47.993484 start: 1.6.6 prepare-kernel (timeout 00:09:29) [common]
234 07:15:47.993783 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:09:29) [common]
235 07:15:47.994027 Converting downloaded kernel to a uImage
236 07:15:47.994352 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/932973/tftp-deploy-evtse3a3/kernel/Image /var/lib/lava/dispatcher/tmp/932973/tftp-deploy-evtse3a3/kernel/uImage
237 07:15:48.727285 output: Image Name:
238 07:15:48.727722 output: Created: Mon Nov 4 07:15:47 2024
239 07:15:48.727953 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
240 07:15:48.728207 output: Data Size: 66830848 Bytes = 65264.50 KiB = 63.73 MiB
241 07:15:48.728422 output: Load Address: 01080000
242 07:15:48.728633 output: Entry Point: 01080000
243 07:15:48.728844 output:
244 07:15:48.729189 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:01) [common]
245 07:15:48.729469 end: 1.6.6 prepare-kernel (duration 00:00:01) [common]
246 07:15:48.729753 start: 1.6.7 configure-preseed-file (timeout 00:09:28) [common]
247 07:15:48.730022 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
248 07:15:48.730297 start: 1.6.8 compress-ramdisk (timeout 00:09:28) [common]
249 07:15:48.730671 Building ramdisk /var/lib/lava/dispatcher/tmp/932973/extract-overlay-ramdisk-3osj89pf/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/932973/extract-overlay-ramdisk-3osj89pf/ramdisk
250 07:15:52.220962 >> 243392 blocks
251 07:16:02.586803 Adding RAMdisk u-boot header.
252 07:16:02.587274 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/932973/extract-overlay-ramdisk-3osj89pf/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/932973/extract-overlay-ramdisk-3osj89pf/ramdisk.cpio.gz.uboot
253 07:16:02.918883 output: Image Name:
254 07:16:02.919320 output: Created: Mon Nov 4 07:16:02 2024
255 07:16:02.919534 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
256 07:16:02.919738 output: Data Size: 31309918 Bytes = 30576.09 KiB = 29.86 MiB
257 07:16:02.919938 output: Load Address: 00000000
258 07:16:02.920325 output: Entry Point: 00000000
259 07:16:02.920746 output:
260 07:16:02.921865 rename /var/lib/lava/dispatcher/tmp/932973/extract-overlay-ramdisk-3osj89pf/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/932973/tftp-deploy-evtse3a3/ramdisk/ramdisk.cpio.gz.uboot
261 07:16:02.922606 end: 1.6.8 compress-ramdisk (duration 00:00:14) [common]
262 07:16:02.923173 end: 1.6 prepare-tftp-overlay (duration 00:00:29) [common]
263 07:16:02.923719 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:14) [common]
264 07:16:02.924224 No LXC device requested
265 07:16:02.924755 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
266 07:16:02.925288 start: 1.8 deploy-device-env (timeout 00:09:14) [common]
267 07:16:02.925799 end: 1.8 deploy-device-env (duration 00:00:00) [common]
268 07:16:02.926222 Checking files for TFTP limit of 4294967296 bytes.
269 07:16:02.928923 end: 1 tftp-deploy (duration 00:00:46) [common]
270 07:16:02.929529 start: 2 uboot-action (timeout 00:05:00) [common]
271 07:16:02.930076 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
272 07:16:02.930589 end: 2.1 uboot-from-media (duration 00:00:00) [common]
273 07:16:02.931109 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
274 07:16:02.931645 Using kernel file from prepare-kernel: 932973/tftp-deploy-evtse3a3/kernel/uImage
275 07:16:02.932321 substitutions:
276 07:16:02.932747 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
277 07:16:02.933160 - {DTB_ADDR}: 0x01070000
278 07:16:02.933566 - {DTB}: 932973/tftp-deploy-evtse3a3/dtb/meson-g12b-a311d-libretech-cc.dtb
279 07:16:02.933970 - {INITRD}: 932973/tftp-deploy-evtse3a3/ramdisk/ramdisk.cpio.gz.uboot
280 07:16:02.934370 - {KERNEL_ADDR}: 0x01080000
281 07:16:02.934765 - {KERNEL}: 932973/tftp-deploy-evtse3a3/kernel/uImage
282 07:16:02.935164 - {LAVA_MAC}: None
283 07:16:02.935606 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/932973/extract-nfsrootfs-ncczzenc
284 07:16:02.936041 - {NFS_SERVER_IP}: 192.168.6.2
285 07:16:02.936446 - {PRESEED_CONFIG}: None
286 07:16:02.936847 - {PRESEED_LOCAL}: None
287 07:16:02.937244 - {RAMDISK_ADDR}: 0x08000000
288 07:16:02.937635 - {RAMDISK}: 932973/tftp-deploy-evtse3a3/ramdisk/ramdisk.cpio.gz.uboot
289 07:16:02.938030 - {ROOT_PART}: None
290 07:16:02.938426 - {ROOT}: None
291 07:16:02.938821 - {SERVER_IP}: 192.168.6.2
292 07:16:02.939217 - {TEE_ADDR}: 0x83000000
293 07:16:02.939608 - {TEE}: None
294 07:16:02.940022 Parsed boot commands:
295 07:16:02.940414 - setenv autoload no
296 07:16:02.940809 - setenv initrd_high 0xffffffff
297 07:16:02.941201 - setenv fdt_high 0xffffffff
298 07:16:02.941590 - dhcp
299 07:16:02.941984 - setenv serverip 192.168.6.2
300 07:16:02.942371 - tftpboot 0x01080000 932973/tftp-deploy-evtse3a3/kernel/uImage
301 07:16:02.942760 - tftpboot 0x08000000 932973/tftp-deploy-evtse3a3/ramdisk/ramdisk.cpio.gz.uboot
302 07:16:02.943155 - tftpboot 0x01070000 932973/tftp-deploy-evtse3a3/dtb/meson-g12b-a311d-libretech-cc.dtb
303 07:16:02.943783 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/932973/extract-nfsrootfs-ncczzenc,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
304 07:16:02.944312 - bootm 0x01080000 0x08000000 0x01070000
305 07:16:02.944861 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
307 07:16:02.946384 start: 2.3 connect-device (timeout 00:05:00) [common]
308 07:16:02.946811 [common] connect-device Connecting to device using 'telnet conserv1 3007'
309 07:16:02.960223 Setting prompt string to ['lava-test: # ']
310 07:16:02.961737 end: 2.3 connect-device (duration 00:00:00) [common]
311 07:16:02.962354 start: 2.4 uboot-commands (timeout 00:05:00) [common]
312 07:16:02.962921 start: 2.4.1 reset-device (timeout 00:05:00) [common]
313 07:16:02.963452 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
314 07:16:02.964613 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
315 07:16:02.999500 >> OK - accepted request
316 07:16:03.001803 Returned 0 in 0 seconds
317 07:16:03.102960 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
319 07:16:03.104726 end: 2.4.1 reset-device (duration 00:00:00) [common]
320 07:16:03.105330 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
321 07:16:03.105856 Setting prompt string to ['Hit any key to stop autoboot']
322 07:16:03.106334 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
323 07:16:03.107914 Trying 192.168.56.21...
324 07:16:03.108433 Connected to conserv1.
325 07:16:03.108863 Escape character is '^]'.
326 07:16:03.109287
327 07:16:03.109713 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
328 07:16:03.110143
329 07:16:15.191556 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
330 07:16:15.191974 bl2_stage_init 0x01
331 07:16:15.192234 bl2_stage_init 0x81
332 07:16:15.197181 hw id: 0x0000 - pwm id 0x01
333 07:16:15.197470 bl2_stage_init 0xc1
334 07:16:15.197676 bl2_stage_init 0x02
335 07:16:15.197879
336 07:16:15.202738 L0:00000000
337 07:16:15.202993 L1:20000703
338 07:16:15.203202 L2:00008067
339 07:16:15.203417 L3:14000000
340 07:16:15.205795 B2:00402000
341 07:16:15.206047 B1:e0f83180
342 07:16:15.206252
343 07:16:15.206454 TE: 58159
344 07:16:15.206657
345 07:16:15.216956 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
346 07:16:15.217224
347 07:16:15.217435 Board ID = 1
348 07:16:15.217637 Set A53 clk to 24M
349 07:16:15.217846 Set A73 clk to 24M
350 07:16:15.222412 Set clk81 to 24M
351 07:16:15.222660 A53 clk: 1200 MHz
352 07:16:15.222864 A73 clk: 1200 MHz
353 07:16:15.226025 CLK81: 166.6M
354 07:16:15.226264 smccc: 00012ab5
355 07:16:15.231543 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
356 07:16:15.237185 board id: 1
357 07:16:15.242323 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
358 07:16:15.252992 fw parse done
359 07:16:15.258898 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
360 07:16:15.301403 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
361 07:16:15.312346 PIEI prepare done
362 07:16:15.312588 fastboot data load
363 07:16:15.312790 fastboot data verify
364 07:16:15.317893 verify result: 266
365 07:16:15.323558 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
366 07:16:15.323834 LPDDR4 probe
367 07:16:15.324097 ddr clk to 1584MHz
368 07:16:15.331505 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
369 07:16:15.368817
370 07:16:15.369122 dmc_version 0001
371 07:16:15.375406 Check phy result
372 07:16:15.381320 INFO : End of CA training
373 07:16:15.381559 INFO : End of initialization
374 07:16:15.386867 INFO : Training has run successfully!
375 07:16:15.387110 Check phy result
376 07:16:15.392520 INFO : End of initialization
377 07:16:15.392758 INFO : End of read enable training
378 07:16:15.398170 INFO : End of fine write leveling
379 07:16:15.403705 INFO : End of Write leveling coarse delay
380 07:16:15.403948 INFO : Training has run successfully!
381 07:16:15.404178 Check phy result
382 07:16:15.409354 INFO : End of initialization
383 07:16:15.409614 INFO : End of read dq deskew training
384 07:16:15.414944 INFO : End of MPR read delay center optimization
385 07:16:15.420511 INFO : End of write delay center optimization
386 07:16:15.426130 INFO : End of read delay center optimization
387 07:16:15.426398 INFO : End of max read latency training
388 07:16:15.431673 INFO : Training has run successfully!
389 07:16:15.431909 1D training succeed
390 07:16:15.440989 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
391 07:16:15.488603 Check phy result
392 07:16:15.488888 INFO : End of initialization
393 07:16:15.510311 INFO : End of 2D read delay Voltage center optimization
394 07:16:15.530566 INFO : End of 2D read delay Voltage center optimization
395 07:16:15.582690 INFO : End of 2D write delay Voltage center optimization
396 07:16:15.632192 INFO : End of 2D write delay Voltage center optimization
397 07:16:15.637577 INFO : Training has run successfully!
398 07:16:15.637815
399 07:16:15.638018 channel==0
400 07:16:15.643348 RxClkDly_Margin_A0==78 ps 8
401 07:16:15.643575 TxDqDly_Margin_A0==98 ps 10
402 07:16:15.646484 RxClkDly_Margin_A1==88 ps 9
403 07:16:15.646725 TxDqDly_Margin_A1==98 ps 10
404 07:16:15.652021 TrainedVREFDQ_A0==74
405 07:16:15.652260 TrainedVREFDQ_A1==74
406 07:16:15.657634 VrefDac_Margin_A0==25
407 07:16:15.657862 DeviceVref_Margin_A0==40
408 07:16:15.658062 VrefDac_Margin_A1==25
409 07:16:15.663355 DeviceVref_Margin_A1==40
410 07:16:15.663596
411 07:16:15.663799
412 07:16:15.664015 channel==1
413 07:16:15.664216 RxClkDly_Margin_A0==98 ps 10
414 07:16:15.666783 TxDqDly_Margin_A0==98 ps 10
415 07:16:15.672247 RxClkDly_Margin_A1==98 ps 10
416 07:16:15.672476 TxDqDly_Margin_A1==88 ps 9
417 07:16:15.672678 TrainedVREFDQ_A0==77
418 07:16:15.677920 TrainedVREFDQ_A1==77
419 07:16:15.678152 VrefDac_Margin_A0==22
420 07:16:15.683486 DeviceVref_Margin_A0==37
421 07:16:15.683717 VrefDac_Margin_A1==24
422 07:16:15.683917 DeviceVref_Margin_A1==37
423 07:16:15.684135
424 07:16:15.689165 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
425 07:16:15.689395
426 07:16:15.722589 soc_vref_reg_value 0x 00000019 0000001a 00000018 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000017 00000019 00000017 00000019 00000018 00000019 0000001a 00000018 00000016 00000018 00000017 0000001a 00000018 00000017 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
427 07:16:15.722910 2D training succeed
428 07:16:15.728259 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
429 07:16:15.733846 auto size-- 65535DDR cs0 size: 2048MB
430 07:16:15.734075 DDR cs1 size: 2048MB
431 07:16:15.739406 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
432 07:16:15.739634 cs0 DataBus test pass
433 07:16:15.739833 cs1 DataBus test pass
434 07:16:15.744996 cs0 AddrBus test pass
435 07:16:15.745244 cs1 AddrBus test pass
436 07:16:15.745444
437 07:16:15.750608 100bdlr_step_size ps== 420
438 07:16:15.750885 result report
439 07:16:15.751090 boot times 0Enable ddr reg access
440 07:16:15.760470 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
441 07:16:15.774130 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
442 07:16:16.347653 0.0;M3 CHK:0;cm4_sp_mode 0
443 07:16:16.348086 MVN_1=0x00000000
444 07:16:16.353087 MVN_2=0x00000000
445 07:16:16.358774 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
446 07:16:16.359050 OPS=0x10
447 07:16:16.359265 ring efuse init
448 07:16:16.359481 chipver efuse init
449 07:16:16.364398 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
450 07:16:16.369982 [0.018960 Inits done]
451 07:16:16.370255 secure task start!
452 07:16:16.370478 high task start!
453 07:16:16.374610 low task start!
454 07:16:16.374877 run into bl31
455 07:16:16.381238 NOTICE: BL31: v1.3(release):4fc40b1
456 07:16:16.389072 NOTICE: BL31: Built : 15:58:17, May 22 2019
457 07:16:16.389370 NOTICE: BL31: G12A normal boot!
458 07:16:16.414396 NOTICE: BL31: BL33 decompress pass
459 07:16:16.420087 ERROR: Error initializing runtime service opteed_fast
460 07:16:17.653032
461 07:16:17.653429
462 07:16:17.661431 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
463 07:16:17.661834
464 07:16:17.662151 Model: Libre Computer AML-A311D-CC Alta
465 07:16:17.869787 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
466 07:16:17.893223 DRAM: 2 GiB (effective 3.8 GiB)
467 07:16:18.036225 Core: 408 devices, 31 uclasses, devicetree: separate
468 07:16:18.042009 WDT: Not starting watchdog@f0d0
469 07:16:18.074279 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
470 07:16:18.086742 Loading Environment from FAT... Card did not respond to voltage select! : -110
471 07:16:18.091713 ** Bad device specification mmc 0 **
472 07:16:18.102049 Card did not respond to voltage select! : -110
473 07:16:18.109708 ** Bad device specification mmc 0 **
474 07:16:18.109983 Couldn't find partition mmc 0
475 07:16:18.118049 Card did not respond to voltage select! : -110
476 07:16:18.123548 ** Bad device specification mmc 0 **
477 07:16:18.123964 Couldn't find partition mmc 0
478 07:16:18.128615 Error: could not access storage.
479 07:16:19.391844 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
480 07:16:19.392487 bl2_stage_init 0x01
481 07:16:19.392908 bl2_stage_init 0x81
482 07:16:19.397399 hw id: 0x0000 - pwm id 0x01
483 07:16:19.397832 bl2_stage_init 0xc1
484 07:16:19.398237 bl2_stage_init 0x02
485 07:16:19.398634
486 07:16:19.402961 L0:00000000
487 07:16:19.403401 L1:20000703
488 07:16:19.403804 L2:00008067
489 07:16:19.404241 L3:14000000
490 07:16:19.408649 B2:00402000
491 07:16:19.409072 B1:e0f83180
492 07:16:19.409468
493 07:16:19.409864 TE: 58159
494 07:16:19.410260
495 07:16:19.414148 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
496 07:16:19.414580
497 07:16:19.414985 Board ID = 1
498 07:16:19.419764 Set A53 clk to 24M
499 07:16:19.420218 Set A73 clk to 24M
500 07:16:19.420621 Set clk81 to 24M
501 07:16:19.425379 A53 clk: 1200 MHz
502 07:16:19.425803 A73 clk: 1200 MHz
503 07:16:19.426204 CLK81: 166.6M
504 07:16:19.426604 smccc: 00012ab5
505 07:16:19.430922 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
506 07:16:19.436636 board id: 1
507 07:16:19.442437 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
508 07:16:19.453106 fw parse done
509 07:16:19.459081 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
510 07:16:19.501715 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
511 07:16:19.512656 PIEI prepare done
512 07:16:19.513081 fastboot data load
513 07:16:19.513486 fastboot data verify
514 07:16:19.518297 verify result: 266
515 07:16:19.523845 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
516 07:16:19.524303 LPDDR4 probe
517 07:16:19.524702 ddr clk to 1584MHz
518 07:16:19.531831 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
519 07:16:19.569076
520 07:16:19.569516 dmc_version 0001
521 07:16:19.575791 Check phy result
522 07:16:19.581731 INFO : End of CA training
523 07:16:19.582163 INFO : End of initialization
524 07:16:19.587215 INFO : Training has run successfully!
525 07:16:19.587635 Check phy result
526 07:16:19.592832 INFO : End of initialization
527 07:16:19.593254 INFO : End of read enable training
528 07:16:19.598455 INFO : End of fine write leveling
529 07:16:19.604043 INFO : End of Write leveling coarse delay
530 07:16:19.604468 INFO : Training has run successfully!
531 07:16:19.604870 Check phy result
532 07:16:19.609731 INFO : End of initialization
533 07:16:19.610151 INFO : End of read dq deskew training
534 07:16:19.615226 INFO : End of MPR read delay center optimization
535 07:16:19.620821 INFO : End of write delay center optimization
536 07:16:19.626449 INFO : End of read delay center optimization
537 07:16:19.626869 INFO : End of max read latency training
538 07:16:19.632055 INFO : Training has run successfully!
539 07:16:19.632484 1D training succeed
540 07:16:19.641201 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
541 07:16:19.688805 Check phy result
542 07:16:19.689231 INFO : End of initialization
543 07:16:19.711334 INFO : End of 2D read delay Voltage center optimization
544 07:16:19.731602 INFO : End of 2D read delay Voltage center optimization
545 07:16:19.783625 INFO : End of 2D write delay Voltage center optimization
546 07:16:19.832955 INFO : End of 2D write delay Voltage center optimization
547 07:16:19.838545 INFO : Training has run successfully!
548 07:16:19.838971
549 07:16:19.839390 channel==0
550 07:16:19.844157 RxClkDly_Margin_A0==88 ps 9
551 07:16:19.844586 TxDqDly_Margin_A0==98 ps 10
552 07:16:19.847489 RxClkDly_Margin_A1==78 ps 8
553 07:16:19.847909 TxDqDly_Margin_A1==98 ps 10
554 07:16:19.853096 TrainedVREFDQ_A0==74
555 07:16:19.853520 TrainedVREFDQ_A1==74
556 07:16:19.853922 VrefDac_Margin_A0==24
557 07:16:19.858762 DeviceVref_Margin_A0==40
558 07:16:19.859180 VrefDac_Margin_A1==25
559 07:16:19.864269 DeviceVref_Margin_A1==40
560 07:16:19.864699
561 07:16:19.865101
562 07:16:19.865496 channel==1
563 07:16:19.865885 RxClkDly_Margin_A0==98 ps 10
564 07:16:19.867564 TxDqDly_Margin_A0==98 ps 10
565 07:16:19.873113 RxClkDly_Margin_A1==88 ps 9
566 07:16:19.873538 TxDqDly_Margin_A1==88 ps 9
567 07:16:19.873942 TrainedVREFDQ_A0==77
568 07:16:19.878765 TrainedVREFDQ_A1==77
569 07:16:19.879190 VrefDac_Margin_A0==22
570 07:16:19.884311 DeviceVref_Margin_A0==37
571 07:16:19.884724 VrefDac_Margin_A1==24
572 07:16:19.885119 DeviceVref_Margin_A1==37
573 07:16:19.885512
574 07:16:19.889904 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
575 07:16:19.890325
576 07:16:19.923507 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000018 00000018 00000016 00000018 00000015 00000018 00000019 00000017 00000019 00000018 0000001a 0000001a 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
577 07:16:19.923968 2D training succeed
578 07:16:19.929114 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
579 07:16:19.934773 auto size-- 65535DDR cs0 size: 2048MB
580 07:16:19.935197 DDR cs1 size: 2048MB
581 07:16:19.940310 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
582 07:16:19.940737 cs0 DataBus test pass
583 07:16:19.941134 cs1 DataBus test pass
584 07:16:19.945890 cs0 AddrBus test pass
585 07:16:19.946314 cs1 AddrBus test pass
586 07:16:19.946709
587 07:16:19.951474 100bdlr_step_size ps== 420
588 07:16:19.951913 result report
589 07:16:19.952352 boot times 0Enable ddr reg access
590 07:16:19.961493 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
591 07:16:19.974989 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
592 07:16:20.548692 0.0;M3 CHK:0;cm4_sp_mode 0
593 07:16:20.549242 MVN_1=0x00000000
594 07:16:20.554165 MVN_2=0x00000000
595 07:16:20.559951 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
596 07:16:20.560486 OPS=0x10
597 07:16:20.560921 ring efuse init
598 07:16:20.561328 chipver efuse init
599 07:16:20.565543 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
600 07:16:20.571126 [0.018961 Inits done]
601 07:16:20.571557 secure task start!
602 07:16:20.571946 high task start!
603 07:16:20.575747 low task start!
604 07:16:20.576234 run into bl31
605 07:16:20.582345 NOTICE: BL31: v1.3(release):4fc40b1
606 07:16:20.590163 NOTICE: BL31: Built : 15:58:17, May 22 2019
607 07:16:20.590589 NOTICE: BL31: G12A normal boot!
608 07:16:20.615550 NOTICE: BL31: BL33 decompress pass
609 07:16:20.621193 ERROR: Error initializing runtime service opteed_fast
610 07:16:21.854251
611 07:16:21.854651
612 07:16:21.862613 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
613 07:16:21.863016
614 07:16:21.863339 Model: Libre Computer AML-A311D-CC Alta
615 07:16:22.070981 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
616 07:16:22.094471 DRAM: 2 GiB (effective 3.8 GiB)
617 07:16:22.237393 Core: 408 devices, 31 uclasses, devicetree: separate
618 07:16:22.243307 WDT: Not starting watchdog@f0d0
619 07:16:22.275570 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
620 07:16:22.287937 Loading Environment from FAT... Card did not respond to voltage select! : -110
621 07:16:22.292960 ** Bad device specification mmc 0 **
622 07:16:22.303240 Card did not respond to voltage select! : -110
623 07:16:22.310908 ** Bad device specification mmc 0 **
624 07:16:22.311156 Couldn't find partition mmc 0
625 07:16:22.319256 Card did not respond to voltage select! : -110
626 07:16:22.324695 ** Bad device specification mmc 0 **
627 07:16:22.324945 Couldn't find partition mmc 0
628 07:16:22.329811 Error: could not access storage.
629 07:16:22.673373 Net: eth0: ethernet@ff3f0000
630 07:16:22.673725 starting USB...
631 07:16:22.925202 Bus usb@ff500000: Register 3000140 NbrPorts 3
632 07:16:22.925634 Starting the controller
633 07:16:22.932117 USB XHCI 1.10
634 07:16:24.640712 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
635 07:16:24.641138 bl2_stage_init 0x01
636 07:16:24.641364 bl2_stage_init 0x81
637 07:16:24.646209 hw id: 0x0000 - pwm id 0x01
638 07:16:24.646532 bl2_stage_init 0xc1
639 07:16:24.646752 bl2_stage_init 0x02
640 07:16:24.646955
641 07:16:24.651724 L0:00000000
642 07:16:24.652140 L1:20000703
643 07:16:24.652478 L2:00008067
644 07:16:24.652826 L3:14000000
645 07:16:24.657487 B2:00402000
646 07:16:24.657876 B1:e0f83180
647 07:16:24.658200
648 07:16:24.658431 TE: 58124
649 07:16:24.658638
650 07:16:24.662946 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
651 07:16:24.663348
652 07:16:24.663679 Board ID = 1
653 07:16:24.668581 Set A53 clk to 24M
654 07:16:24.669015 Set A73 clk to 24M
655 07:16:24.669256 Set clk81 to 24M
656 07:16:24.674272 A53 clk: 1200 MHz
657 07:16:24.674559 A73 clk: 1200 MHz
658 07:16:24.674779 CLK81: 166.6M
659 07:16:24.674980 smccc: 00012a92
660 07:16:24.679630 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
661 07:16:24.685370 board id: 1
662 07:16:24.691236 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
663 07:16:24.701811 fw parse done
664 07:16:24.707783 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
665 07:16:24.750476 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
666 07:16:24.761420 PIEI prepare done
667 07:16:24.761697 fastboot data load
668 07:16:24.761905 fastboot data verify
669 07:16:24.766984 verify result: 266
670 07:16:24.772537 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
671 07:16:24.772918 LPDDR4 probe
672 07:16:24.773244 ddr clk to 1584MHz
673 07:16:24.780615 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
674 07:16:24.817842
675 07:16:24.818382 dmc_version 0001
676 07:16:24.824579 Check phy result
677 07:16:24.830350 INFO : End of CA training
678 07:16:24.830842 INFO : End of initialization
679 07:16:24.835958 INFO : Training has run successfully!
680 07:16:24.836503 Check phy result
681 07:16:24.841560 INFO : End of initialization
682 07:16:24.842061 INFO : End of read enable training
683 07:16:24.844861 INFO : End of fine write leveling
684 07:16:24.850504 INFO : End of Write leveling coarse delay
685 07:16:24.856033 INFO : Training has run successfully!
686 07:16:24.856534 Check phy result
687 07:16:24.856997 INFO : End of initialization
688 07:16:24.861644 INFO : End of read dq deskew training
689 07:16:24.867242 INFO : End of MPR read delay center optimization
690 07:16:24.867727 INFO : End of write delay center optimization
691 07:16:24.872778 INFO : End of read delay center optimization
692 07:16:24.878508 INFO : End of max read latency training
693 07:16:24.878995 INFO : Training has run successfully!
694 07:16:24.884019 1D training succeed
695 07:16:24.889979 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
696 07:16:24.937647 Check phy result
697 07:16:24.938167 INFO : End of initialization
698 07:16:24.960184 INFO : End of 2D read delay Voltage center optimization
699 07:16:24.980440 INFO : End of 2D read delay Voltage center optimization
700 07:16:25.032575 INFO : End of 2D write delay Voltage center optimization
701 07:16:25.081926 INFO : End of 2D write delay Voltage center optimization
702 07:16:25.087374 INFO : Training has run successfully!
703 07:16:25.087913
704 07:16:25.088438 channel==0
705 07:16:25.092978 RxClkDly_Margin_A0==88 ps 9
706 07:16:25.093502 TxDqDly_Margin_A0==98 ps 10
707 07:16:25.096332 RxClkDly_Margin_A1==88 ps 9
708 07:16:25.096839 TxDqDly_Margin_A1==98 ps 10
709 07:16:25.102008 TrainedVREFDQ_A0==74
710 07:16:25.102512 TrainedVREFDQ_A1==74
711 07:16:25.102975 VrefDac_Margin_A0==24
712 07:16:25.107602 DeviceVref_Margin_A0==40
713 07:16:25.108314 VrefDac_Margin_A1==24
714 07:16:25.113210 DeviceVref_Margin_A1==40
715 07:16:25.113707
716 07:16:25.114171
717 07:16:25.114625 channel==1
718 07:16:25.115065 RxClkDly_Margin_A0==98 ps 10
719 07:16:25.118755 TxDqDly_Margin_A0==98 ps 10
720 07:16:25.119375 RxClkDly_Margin_A1==88 ps 9
721 07:16:25.124473 TxDqDly_Margin_A1==88 ps 9
722 07:16:25.125062 TrainedVREFDQ_A0==77
723 07:16:25.125530 TrainedVREFDQ_A1==77
724 07:16:25.129964 VrefDac_Margin_A0==22
725 07:16:25.130747 DeviceVref_Margin_A0==37
726 07:16:25.135579 VrefDac_Margin_A1==24
727 07:16:25.136153 DeviceVref_Margin_A1==37
728 07:16:25.136616
729 07:16:25.141145 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
730 07:16:25.141638
731 07:16:25.169196 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000017 00000018 00000016 00000017 00000019 00000017 00000019 00000018 0000001a 0000001a 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
732 07:16:25.174816 2D training succeed
733 07:16:25.180290 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
734 07:16:25.180774 auto size-- 65535DDR cs0 size: 2048MB
735 07:16:25.185871 DDR cs1 size: 2048MB
736 07:16:25.186347 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
737 07:16:25.191499 cs0 DataBus test pass
738 07:16:25.192023 cs1 DataBus test pass
739 07:16:25.192486 cs0 AddrBus test pass
740 07:16:25.197088 cs1 AddrBus test pass
741 07:16:25.197573
742 07:16:25.198023 100bdlr_step_size ps== 420
743 07:16:25.198473 result report
744 07:16:25.202679 boot times 0Enable ddr reg access
745 07:16:25.210204 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
746 07:16:25.223689 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
747 07:16:25.797480 0.0;M3 CHK:0;cm4_sp_mode 0
748 07:16:25.798038 MVN_1=0x00000000
749 07:16:25.802976 MVN_2=0x00000000
750 07:16:25.808745 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
751 07:16:25.809299 OPS=0x10
752 07:16:25.809738 ring efuse init
753 07:16:25.810164 chipver efuse init
754 07:16:25.814318 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
755 07:16:25.819903 [0.018961 Inits done]
756 07:16:25.820422 secure task start!
757 07:16:25.820853 high task start!
758 07:16:25.824477 low task start!
759 07:16:25.824942 run into bl31
760 07:16:25.831122 NOTICE: BL31: v1.3(release):4fc40b1
761 07:16:25.838909 NOTICE: BL31: Built : 15:58:17, May 22 2019
762 07:16:25.839374 NOTICE: BL31: G12A normal boot!
763 07:16:25.864331 NOTICE: BL31: BL33 decompress pass
764 07:16:25.870022 ERROR: Error initializing runtime service opteed_fast
765 07:16:27.102906
766 07:16:27.103575
767 07:16:27.111263 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
768 07:16:27.111790
769 07:16:27.112298 Model: Libre Computer AML-A311D-CC Alta
770 07:16:27.319651 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
771 07:16:27.343080 DRAM: 2 GiB (effective 3.8 GiB)
772 07:16:27.486025 Core: 408 devices, 31 uclasses, devicetree: separate
773 07:16:27.491931 WDT: Not starting watchdog@f0d0
774 07:16:27.524176 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
775 07:16:27.536633 Loading Environment from FAT... Card did not respond to voltage select! : -110
776 07:16:27.541622 ** Bad device specification mmc 0 **
777 07:16:27.551954 Card did not respond to voltage select! : -110
778 07:16:27.559635 ** Bad device specification mmc 0 **
779 07:16:27.560164 Couldn't find partition mmc 0
780 07:16:27.567958 Card did not respond to voltage select! : -110
781 07:16:27.573454 ** Bad device specification mmc 0 **
782 07:16:27.573939 Couldn't find partition mmc 0
783 07:16:27.578533 Error: could not access storage.
784 07:16:27.920998 Net: eth0: ethernet@ff3f0000
785 07:16:27.921555 starting USB...
786 07:16:28.172791 Bus usb@ff500000: Register 3000140 NbrPorts 3
787 07:16:28.173370 Starting the controller
788 07:16:28.179792 USB XHCI 1.10
789 07:16:30.340760 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
790 07:16:30.341406 bl2_stage_init 0x01
791 07:16:30.341874 bl2_stage_init 0x81
792 07:16:30.346308 hw id: 0x0000 - pwm id 0x01
793 07:16:30.346800 bl2_stage_init 0xc1
794 07:16:30.347254 bl2_stage_init 0x02
795 07:16:30.347698
796 07:16:30.352054 L0:00000000
797 07:16:30.352548 L1:20000703
798 07:16:30.353002 L2:00008067
799 07:16:30.353444 L3:14000000
800 07:16:30.357533 B2:00402000
801 07:16:30.358061 B1:e0f83180
802 07:16:30.358515
803 07:16:30.358962 TE: 58159
804 07:16:30.359403
805 07:16:30.363338 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
806 07:16:30.363829
807 07:16:30.364316 Board ID = 1
808 07:16:30.368946 Set A53 clk to 24M
809 07:16:30.369429 Set A73 clk to 24M
810 07:16:30.369876 Set clk81 to 24M
811 07:16:30.374264 A53 clk: 1200 MHz
812 07:16:30.374749 A73 clk: 1200 MHz
813 07:16:30.375193 CLK81: 166.6M
814 07:16:30.375631 smccc: 00012ab5
815 07:16:30.379968 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
816 07:16:30.385505 board id: 1
817 07:16:30.390462 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
818 07:16:30.402007 fw parse done
819 07:16:30.407722 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
820 07:16:30.450620 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
821 07:16:30.461474 PIEI prepare done
822 07:16:30.461958 fastboot data load
823 07:16:30.462409 fastboot data verify
824 07:16:30.467186 verify result: 266
825 07:16:30.472768 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
826 07:16:30.473258 LPDDR4 probe
827 07:16:30.473704 ddr clk to 1584MHz
828 07:16:30.480043 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
829 07:16:30.517735
830 07:16:30.518252 dmc_version 0001
831 07:16:30.524108 Check phy result
832 07:16:30.530509 INFO : End of CA training
833 07:16:30.530986 INFO : End of initialization
834 07:16:30.536223 INFO : Training has run successfully!
835 07:16:30.536702 Check phy result
836 07:16:30.541686 INFO : End of initialization
837 07:16:30.542165 INFO : End of read enable training
838 07:16:30.544983 INFO : End of fine write leveling
839 07:16:30.550526 INFO : End of Write leveling coarse delay
840 07:16:30.556212 INFO : Training has run successfully!
841 07:16:30.556692 Check phy result
842 07:16:30.557137 INFO : End of initialization
843 07:16:30.561753 INFO : End of read dq deskew training
844 07:16:30.567608 INFO : End of MPR read delay center optimization
845 07:16:30.568128 INFO : End of write delay center optimization
846 07:16:30.573173 INFO : End of read delay center optimization
847 07:16:30.578567 INFO : End of max read latency training
848 07:16:30.579046 INFO : Training has run successfully!
849 07:16:30.584168 1D training succeed
850 07:16:30.589168 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
851 07:16:30.637454 Check phy result
852 07:16:30.637951 INFO : End of initialization
853 07:16:30.658827 INFO : End of 2D read delay Voltage center optimization
854 07:16:30.679118 INFO : End of 2D read delay Voltage center optimization
855 07:16:30.730995 INFO : End of 2D write delay Voltage center optimization
856 07:16:30.781276 INFO : End of 2D write delay Voltage center optimization
857 07:16:30.786738 INFO : Training has run successfully!
858 07:16:30.787199
859 07:16:30.787779 channel==0
860 07:16:30.792358 RxClkDly_Margin_A0==88 ps 9
861 07:16:30.792859 TxDqDly_Margin_A0==108 ps 11
862 07:16:30.798055 RxClkDly_Margin_A1==88 ps 9
863 07:16:30.798434 TxDqDly_Margin_A1==98 ps 10
864 07:16:30.798663 TrainedVREFDQ_A0==74
865 07:16:30.803641 TrainedVREFDQ_A1==74
866 07:16:30.804099 VrefDac_Margin_A0==25
867 07:16:30.809507 DeviceVref_Margin_A0==40
868 07:16:30.809978 VrefDac_Margin_A1==25
869 07:16:30.810340 DeviceVref_Margin_A1==40
870 07:16:30.810666
871 07:16:30.811012
872 07:16:30.814797 channel==1
873 07:16:30.815269 RxClkDly_Margin_A0==98 ps 10
874 07:16:30.815605 TxDqDly_Margin_A0==98 ps 10
875 07:16:30.820411 RxClkDly_Margin_A1==98 ps 10
876 07:16:30.820913 TxDqDly_Margin_A1==88 ps 9
877 07:16:30.826092 TrainedVREFDQ_A0==77
878 07:16:30.826603 TrainedVREFDQ_A1==77
879 07:16:30.826930 VrefDac_Margin_A0==22
880 07:16:30.831663 DeviceVref_Margin_A0==37
881 07:16:30.832189 VrefDac_Margin_A1==22
882 07:16:30.837231 DeviceVref_Margin_A1==37
883 07:16:30.837754
884 07:16:30.838118 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
885 07:16:30.842860
886 07:16:30.870921 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000018 00000018 00000017 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
887 07:16:30.871541 2D training succeed
888 07:16:30.876444 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
889 07:16:30.881998 auto size-- 65535DDR cs0 size: 2048MB
890 07:16:30.882507 DDR cs1 size: 2048MB
891 07:16:30.887531 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
892 07:16:30.888075 cs0 DataBus test pass
893 07:16:30.893127 cs1 DataBus test pass
894 07:16:30.893658 cs0 AddrBus test pass
895 07:16:30.894021 cs1 AddrBus test pass
896 07:16:30.894375
897 07:16:30.898748 100bdlr_step_size ps== 420
898 07:16:30.899263 result report
899 07:16:30.904366 boot times 0Enable ddr reg access
900 07:16:30.909591 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
901 07:16:30.922512 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
902 07:16:31.497259 0.0;M3 CHK:0;cm4_sp_mode 0
903 07:16:31.497881 MVN_1=0x00000000
904 07:16:31.502562 MVN_2=0x00000000
905 07:16:31.508310 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
906 07:16:31.509119 OPS=0x10
907 07:16:31.510840 ring efuse init
908 07:16:31.511482 chipver efuse init
909 07:16:31.516395 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
910 07:16:31.517217 [0.018961 Inits done]
911 07:16:31.523667 secure task start!
912 07:16:31.524552 high task start!
913 07:16:31.525197 low task start!
914 07:16:31.525876 run into bl31
915 07:16:31.530629 NOTICE: BL31: v1.3(release):4fc40b1
916 07:16:31.538123 NOTICE: BL31: Built : 15:58:17, May 22 2019
917 07:16:31.538954 NOTICE: BL31: G12A normal boot!
918 07:16:31.563858 NOTICE: BL31: BL33 decompress pass
919 07:16:31.568512 ERROR: Error initializing runtime service opteed_fast
920 07:16:32.802399
921 07:16:32.803304
922 07:16:32.810703 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
923 07:16:32.811549
924 07:16:32.812292 Model: Libre Computer AML-A311D-CC Alta
925 07:16:33.018680 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
926 07:16:33.042504 DRAM: 2 GiB (effective 3.8 GiB)
927 07:16:33.185817 Core: 408 devices, 31 uclasses, devicetree: separate
928 07:16:33.191587 WDT: Not starting watchdog@f0d0
929 07:16:33.223741 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
930 07:16:33.236398 Loading Environment from FAT... Card did not respond to voltage select! : -110
931 07:16:33.240933 ** Bad device specification mmc 0 **
932 07:16:33.251522 Card did not respond to voltage select! : -110
933 07:16:33.258232 ** Bad device specification mmc 0 **
934 07:16:33.258845 Couldn't find partition mmc 0
935 07:16:33.267464 Card did not respond to voltage select! : -110
936 07:16:33.272977 ** Bad device specification mmc 0 **
937 07:16:33.273520 Couldn't find partition mmc 0
938 07:16:33.277120 Error: could not access storage.
939 07:16:33.621425 Net: eth0: ethernet@ff3f0000
940 07:16:33.622127 starting USB...
941 07:16:33.873423 Bus usb@ff500000: Register 3000140 NbrPorts 3
942 07:16:33.874094 Starting the controller
943 07:16:33.880146 USB XHCI 1.10
944 07:16:35.740639 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.�!,K��х��}���с0x01
945 07:16:35.741656 bl2_stage_init 0x81
946 07:16:35.746236 hw id: 0x0000 - pwm id 0x01
947 07:16:35.747045 bl2_stage_init 0xc1
948 07:16:35.747778 bl2_stage_init 0x02
949 07:16:35.748601
950 07:16:35.751826 L0:00000000
951 07:16:35.752647 L1:20000703
952 07:16:35.753361 L2:00008067
953 07:16:35.754013 L3:14000000
954 07:16:35.754725 B2:00402000
955 07:16:35.757661 B1:e0f83180
956 07:16:35.758260
957 07:16:35.759014 TE: 58150
958 07:16:35.759675
959 07:16:35.763075 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
960 07:16:35.763623
961 07:16:35.764148 Board ID = 1
962 07:16:35.768435 Set A53 clk to 24M
963 07:16:35.769028 Set A73 clk to 24M
964 07:16:35.769554 Set clk81 to 24M
965 07:16:35.774084 A53 clk: 1200 MHz
966 07:16:35.774669 A73 clk: 1200 MHz
967 07:16:35.775188 CLK81: 166.6M
968 07:16:35.775688 smccc: 00012aab
969 07:16:35.779847 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
970 07:16:35.785351 board id: 1
971 07:16:35.790405 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
972 07:16:35.801680 fw parse done
973 07:16:35.807198 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
974 07:16:35.849907 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
975 07:16:35.861384 PIEI prepare done
976 07:16:35.862203 fastboot data load
977 07:16:35.862898 fastboot data verify
978 07:16:35.866950 verify result: 266
979 07:16:35.872502 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
980 07:16:35.873078 LPDDR4 probe
981 07:16:35.873570 ddr clk to 1584MHz
982 07:16:35.880313 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
983 07:16:35.917617
984 07:16:35.918223 dmc_version 0001
985 07:16:35.924356 Check phy result
986 07:16:35.930560 INFO : End of CA training
987 07:16:35.931119 INFO : End of initialization
988 07:16:35.936025 INFO : Training has run successfully!
989 07:16:35.936594 Check phy result
990 07:16:35.941605 INFO : End of initialization
991 07:16:35.942169 INFO : End of read enable training
992 07:16:35.945166 INFO : End of fine write leveling
993 07:16:35.950512 INFO : End of Write leveling coarse delay
994 07:16:35.956327 INFO : Training has run successfully!
995 07:16:35.957123 Check phy result
996 07:16:35.957791 INFO : End of initialization
997 07:16:35.961858 INFO : End of read dq deskew training
998 07:16:35.965329 INFO : End of MPR read delay center optimization
999 07:16:35.970964 INFO : End of write delay center optimization
1000 07:16:35.976510 INFO : End of read delay center optimization
1001 07:16:35.977303 INFO : End of max read latency training
1002 07:16:35.982070 INFO : Training has run successfully!
1003 07:16:35.982642 1D training succeed
1004 07:16:35.989116 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
1005 07:16:36.037450 Check phy result
1006 07:16:36.038005 INFO : End of initialization
1007 07:16:36.059231 INFO : End of 2D read delay Voltage center optimization
1008 07:16:36.079471 INFO : End of 2D read delay Voltage center optimization
1009 07:16:36.131521 INFO : End of 2D write delay Voltage center optimization
1010 07:16:36.180901 INFO : End of 2D write delay Voltage center optimization
1011 07:16:36.186473 INFO : Training has run successfully!
1012 07:16:36.187008
1013 07:16:36.187461 channel==0
1014 07:16:36.192124 RxClkDly_Margin_A0==88 ps 9
1015 07:16:36.192664 TxDqDly_Margin_A0==98 ps 10
1016 07:16:36.197729 RxClkDly_Margin_A1==88 ps 9
1017 07:16:36.198293 TxDqDly_Margin_A1==98 ps 10
1018 07:16:36.198758 TrainedVREFDQ_A0==74
1019 07:16:36.203284 TrainedVREFDQ_A1==74
1020 07:16:36.203839 VrefDac_Margin_A0==25
1021 07:16:36.204364 DeviceVref_Margin_A0==40
1022 07:16:36.208878 VrefDac_Margin_A1==25
1023 07:16:36.209408 DeviceVref_Margin_A1==40
1024 07:16:36.209844
1025 07:16:36.210278
1026 07:16:36.214454 channel==1
1027 07:16:36.215006 RxClkDly_Margin_A0==98 ps 10
1028 07:16:36.215450 TxDqDly_Margin_A0==98 ps 10
1029 07:16:36.220127 RxClkDly_Margin_A1==98 ps 10
1030 07:16:36.220659 TxDqDly_Margin_A1==88 ps 9
1031 07:16:36.225667 TrainedVREFDQ_A0==77
1032 07:16:36.226196 TrainedVREFDQ_A1==77
1033 07:16:36.226640 VrefDac_Margin_A0==22
1034 07:16:36.231257 DeviceVref_Margin_A0==37
1035 07:16:36.231778 VrefDac_Margin_A1==22
1036 07:16:36.236866 DeviceVref_Margin_A1==37
1037 07:16:36.237389
1038 07:16:36.237828 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
1039 07:16:36.242458
1040 07:16:36.270439 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000015 00000018 00000015 00000017 00000019 00000018 00000019 00000018 0000001a 0000001a 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
1041 07:16:36.271030 2D training succeed
1042 07:16:36.276122 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
1043 07:16:36.281680 auto size-- 65535DDR cs0 size: 2048MB
1044 07:16:36.282215 DDR cs1 size: 2048MB
1045 07:16:36.287258 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
1046 07:16:36.287782 cs0 DataBus test pass
1047 07:16:36.292882 cs1 DataBus test pass
1048 07:16:36.293414 cs0 AddrBus test pass
1049 07:16:36.293852 cs1 AddrBus test pass
1050 07:16:36.294287
1051 07:16:36.298455 100bdlr_step_size ps== 420
1052 07:16:36.299000 result report
1053 07:16:36.304116 boot times 0Enable ddr reg access
1054 07:16:36.309980 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
1055 07:16:36.322299 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
1056 07:16:36.896521 0.0;M3 CHK:0;cm4_sp_mode 0
1057 07:16:36.897143 MVN_1=0x00000000
1058 07:16:36.902226 MVN_2=0x00000000
1059 07:16:36.907953 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
1060 07:16:36.908528 OPS=0x10
1061 07:16:36.908972 ring efuse init
1062 07:16:36.909401 chipver efuse init
1063 07:16:36.913445 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
1064 07:16:36.919210 [0.018961 Inits done]
1065 07:16:36.919747 secure task start!
1066 07:16:36.920219 high task start!
1067 07:16:36.923728 low task start!
1068 07:16:36.924284 run into bl31
1069 07:16:36.930302 NOTICE: BL31: v1.3(release):4fc40b1
1070 07:16:36.937933 NOTICE: BL31: Built : 15:58:17, May 22 2019
1071 07:16:36.938474 NOTICE: BL31: G12A normal boot!
1072 07:16:36.963397 NOTICE: BL31: BL33 decompress pass
1073 07:16:36.968568 ERROR: Error initializing runtime service opteed_fast
1074 07:16:38.201860
1075 07:16:38.202498
1076 07:16:38.209385 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
1077 07:16:38.209924
1078 07:16:38.210387 Model: Libre Computer AML-A311D-CC Alta
1079 07:16:38.418076 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
1080 07:16:38.441698 DRAM: 2 GiB (effective 3.8 GiB)
1081 07:16:38.585118 Core: 408 devices, 31 uclasses, devicetree: separate
1082 07:16:38.590586 WDT: Not starting watchdog@f0d0
1083 07:16:38.623232 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
1084 07:16:38.635652 Loading Environment from FAT... Card did not respond to voltage select! : -110
1085 07:16:38.640199 ** Bad device specification mmc 0 **
1086 07:16:38.651026 Card did not respond to voltage select! : -110
1087 07:16:38.658623 ** Bad device specification mmc 0 **
1088 07:16:38.659153 Couldn't find partition mmc 0
1089 07:16:38.667069 Card did not respond to voltage select! : -110
1090 07:16:38.672551 ** Bad device specification mmc 0 **
1091 07:16:38.673077 Couldn't find partition mmc 0
1092 07:16:38.677298 Error: could not access storage.
1093 07:16:39.019379 Net: eth0: ethernet@ff3f0000
1094 07:16:39.020111 starting USB...
1095 07:16:39.271790 Bus usb@ff500000: Register 3000140 NbrPorts 3
1096 07:16:39.272518 Starting the controller
1097 07:16:39.278432 USB XHCI 1.10
1098 07:16:40.832911 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
1099 07:16:40.841044 scanning usb for storage devices... 0 Storage Device(s) found
1101 07:16:40.892845 Hit any key to stop autoboot: 1
1102 07:16:40.893695 end: 2.4.2 bootloader-interrupt (duration 00:00:38) [common]
1103 07:16:40.894395 start: 2.4.3 bootloader-commands (timeout 00:04:22) [common]
1104 07:16:40.894902 Setting prompt string to ['=>']
1105 07:16:40.895419 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:22)
1106 07:16:40.907948 0
1107 07:16:40.908926 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1108 07:16:40.909449 Sending with 10 millisecond of delay
1110 07:16:42.044290 => setenv autoload no
1111 07:16:42.055116 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:21)
1112 07:16:42.060484 setenv autoload no
1113 07:16:42.061276 Sending with 10 millisecond of delay
1115 07:16:43.858130 => setenv initrd_high 0xffffffff
1116 07:16:43.868922 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:19)
1117 07:16:43.869833 setenv initrd_high 0xffffffff
1118 07:16:43.870606 Sending with 10 millisecond of delay
1120 07:16:45.487658 => setenv fdt_high 0xffffffff
1121 07:16:45.498275 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:17)
1122 07:16:45.498823 setenv fdt_high 0xffffffff
1123 07:16:45.499305 Sending with 10 millisecond of delay
1125 07:16:45.790971 => dhcp
1126 07:16:45.801751 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:17)
1127 07:16:45.802588 dhcp
1128 07:16:45.803013 Speed: 1000, full duplex
1129 07:16:45.803416 BOOTP broadcast 1
1130 07:16:45.814519 DHCP client bound to address 192.168.6.27 (13 ms)
1131 07:16:45.815277 Sending with 10 millisecond of delay
1133 07:16:47.492260 => setenv serverip 192.168.6.2
1134 07:16:47.503045 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:15)
1135 07:16:47.503923 setenv serverip 192.168.6.2
1136 07:16:47.504661 Sending with 10 millisecond of delay
1138 07:16:51.231450 => tftpboot 0x01080000 932973/tftp-deploy-evtse3a3/kernel/uImage
1139 07:16:51.242527 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:12)
1140 07:16:51.243926 tftpboot 0x01080000 932973/tftp-deploy-evtse3a3/kernel/uImage
1141 07:16:51.244676 Speed: 1000, full duplex
1142 07:16:51.245330 Using ethernet@ff3f0000 device
1143 07:16:51.246309 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1144 07:16:51.250676 Filename '932973/tftp-deploy-evtse3a3/kernel/uImage'.
1145 07:16:51.254063 Load address: 0x1080000
1146 07:16:55.430761 Loading: *#################################################
1147 07:16:55.431149 TFTP error: trying to overwrite reserved memory...
1149 07:16:55.432059 end: 2.4.3 bootloader-commands (duration 00:00:15) [common]
1152 07:16:55.433035 end: 2.4 uboot-commands (duration 00:00:52) [common]
1154 07:16:55.433813 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'TFTP error: trying to overwrite reserved memory' (12)'
1156 07:16:55.434374 end: 2 uboot-action (duration 00:00:53) [common]
1158 07:16:55.435154 Cleaning after the job
1159 07:16:55.435503 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/932973/tftp-deploy-evtse3a3/ramdisk
1160 07:16:55.444918 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/932973/tftp-deploy-evtse3a3/kernel
1161 07:16:55.462271 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/932973/tftp-deploy-evtse3a3/dtb
1162 07:16:55.463079 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/932973/tftp-deploy-evtse3a3/nfsrootfs
1163 07:16:55.605081 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/932973/tftp-deploy-evtse3a3/modules
1164 07:16:55.634276 start: 4.1 power-off (timeout 00:00:30) [common]
1165 07:16:55.634945 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1166 07:16:55.665757 >> OK - accepted request
1167 07:16:55.667773 Returned 0 in 0 seconds
1168 07:16:55.768628 end: 4.1 power-off (duration 00:00:00) [common]
1170 07:16:55.770269 start: 4.2 read-feedback (timeout 00:10:00) [common]
1171 07:16:55.771369 Listened to connection for namespace 'common' for up to 1s
1172 07:16:56.772126 Finalising connection for namespace 'common'
1173 07:16:56.772560 Disconnecting from shell: Finalise
1174 07:16:56.772813 =>
1175 07:16:56.873394 end: 4.2 read-feedback (duration 00:00:01) [common]
1176 07:16:56.873755 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/932973
1177 07:16:58.779780 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/932973
1178 07:16:58.780392 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.