Boot log: meson-sm1-s905d3-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 07:27:05.557978 lava-dispatcher, installed at version: 2024.01
2 07:27:05.558763 start: 0 validate
3 07:27:05.559226 Start time: 2024-11-04 07:27:05.559195+00:00 (UTC)
4 07:27:05.559747 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 07:27:05.560306 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230703.0%2Farm64%2Frootfs.cpio.gz exists
6 07:27:05.593299 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 07:27:05.593870 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241104%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 07:27:06.628300 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 07:27:06.628965 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241104%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-sm1-s905d3-libretech-cc.dtb exists
10 07:27:12.697582 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 07:27:12.698121 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241104%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
12 07:27:12.740084 validate duration: 7.18
14 07:27:12.740977 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 07:27:12.741326 start: 1.1 download-retry (timeout 00:10:00) [common]
16 07:27:12.741637 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 07:27:12.742271 Not decompressing ramdisk as can be used compressed.
18 07:27:12.742732 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230703.0/arm64/rootfs.cpio.gz
19 07:27:12.743008 saving as /var/lib/lava/dispatcher/tmp/933151/tftp-deploy-jqv6xjhh/ramdisk/rootfs.cpio.gz
20 07:27:12.743295 total size: 8181887 (7 MB)
21 07:27:12.788253 progress 0 % (0 MB)
22 07:27:12.799627 progress 5 % (0 MB)
23 07:27:12.806530 progress 10 % (0 MB)
24 07:27:12.813898 progress 15 % (1 MB)
25 07:27:12.819947 progress 20 % (1 MB)
26 07:27:12.826466 progress 25 % (1 MB)
27 07:27:12.832372 progress 30 % (2 MB)
28 07:27:12.838499 progress 35 % (2 MB)
29 07:27:12.844347 progress 40 % (3 MB)
30 07:27:12.850253 progress 45 % (3 MB)
31 07:27:12.856055 progress 50 % (3 MB)
32 07:27:12.861945 progress 55 % (4 MB)
33 07:27:12.867533 progress 60 % (4 MB)
34 07:27:12.873549 progress 65 % (5 MB)
35 07:27:12.879036 progress 70 % (5 MB)
36 07:27:12.885055 progress 75 % (5 MB)
37 07:27:12.890652 progress 80 % (6 MB)
38 07:27:12.896602 progress 85 % (6 MB)
39 07:27:12.902131 progress 90 % (7 MB)
40 07:27:12.908256 progress 95 % (7 MB)
41 07:27:12.913679 progress 100 % (7 MB)
42 07:27:12.914479 7 MB downloaded in 0.17 s (45.59 MB/s)
43 07:27:12.915449 end: 1.1.1 http-download (duration 00:00:00) [common]
45 07:27:12.916842 end: 1.1 download-retry (duration 00:00:00) [common]
46 07:27:12.917287 start: 1.2 download-retry (timeout 00:10:00) [common]
47 07:27:12.917589 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 07:27:12.918122 downloading http://storage.kernelci.org/next/master/next-20241104/arm64/defconfig/gcc-12/kernel/Image
49 07:27:12.918400 saving as /var/lib/lava/dispatcher/tmp/933151/tftp-deploy-jqv6xjhh/kernel/Image
50 07:27:12.918610 total size: 46041600 (43 MB)
51 07:27:12.918824 No compression specified
52 07:27:12.960965 progress 0 % (0 MB)
53 07:27:12.991154 progress 5 % (2 MB)
54 07:27:13.020918 progress 10 % (4 MB)
55 07:27:13.050835 progress 15 % (6 MB)
56 07:27:13.082090 progress 20 % (8 MB)
57 07:27:13.113826 progress 25 % (11 MB)
58 07:27:13.144648 progress 30 % (13 MB)
59 07:27:13.178667 progress 35 % (15 MB)
60 07:27:13.216860 progress 40 % (17 MB)
61 07:27:13.254639 progress 45 % (19 MB)
62 07:27:13.291331 progress 50 % (21 MB)
63 07:27:13.326160 progress 55 % (24 MB)
64 07:27:13.361522 progress 60 % (26 MB)
65 07:27:13.392644 progress 65 % (28 MB)
66 07:27:13.424634 progress 70 % (30 MB)
67 07:27:13.458564 progress 75 % (32 MB)
68 07:27:13.489993 progress 80 % (35 MB)
69 07:27:13.520232 progress 85 % (37 MB)
70 07:27:13.550401 progress 90 % (39 MB)
71 07:27:13.580502 progress 95 % (41 MB)
72 07:27:13.610163 progress 100 % (43 MB)
73 07:27:13.610784 43 MB downloaded in 0.69 s (63.44 MB/s)
74 07:27:13.611307 end: 1.2.1 http-download (duration 00:00:01) [common]
76 07:27:13.612230 end: 1.2 download-retry (duration 00:00:01) [common]
77 07:27:13.612557 start: 1.3 download-retry (timeout 00:09:59) [common]
78 07:27:13.612829 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 07:27:13.613317 downloading http://storage.kernelci.org/next/master/next-20241104/arm64/defconfig/gcc-12/dtbs/amlogic/meson-sm1-s905d3-libretech-cc.dtb
80 07:27:13.613581 saving as /var/lib/lava/dispatcher/tmp/933151/tftp-deploy-jqv6xjhh/dtb/meson-sm1-s905d3-libretech-cc.dtb
81 07:27:13.613789 total size: 53209 (0 MB)
82 07:27:13.614003 No compression specified
83 07:27:13.652523 progress 61 % (0 MB)
84 07:27:13.653524 progress 100 % (0 MB)
85 07:27:13.654193 0 MB downloaded in 0.04 s (1.26 MB/s)
86 07:27:13.654723 end: 1.3.1 http-download (duration 00:00:00) [common]
88 07:27:13.655570 end: 1.3 download-retry (duration 00:00:00) [common]
89 07:27:13.655840 start: 1.4 download-retry (timeout 00:09:59) [common]
90 07:27:13.656155 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 07:27:13.656671 downloading http://storage.kernelci.org/next/master/next-20241104/arm64/defconfig/gcc-12/modules.tar.xz
92 07:27:13.656950 saving as /var/lib/lava/dispatcher/tmp/933151/tftp-deploy-jqv6xjhh/modules/modules.tar
93 07:27:13.657165 total size: 11673844 (11 MB)
94 07:27:13.657380 Using unxz to decompress xz
95 07:27:13.700380 progress 0 % (0 MB)
96 07:27:13.777174 progress 5 % (0 MB)
97 07:27:13.858437 progress 10 % (1 MB)
98 07:27:13.962467 progress 15 % (1 MB)
99 07:27:14.063865 progress 20 % (2 MB)
100 07:27:14.147543 progress 25 % (2 MB)
101 07:27:14.227123 progress 30 % (3 MB)
102 07:27:14.311330 progress 35 % (3 MB)
103 07:27:14.393107 progress 40 % (4 MB)
104 07:27:14.471392 progress 45 % (5 MB)
105 07:27:14.558027 progress 50 % (5 MB)
106 07:27:14.637468 progress 55 % (6 MB)
107 07:27:14.726700 progress 60 % (6 MB)
108 07:27:14.814702 progress 65 % (7 MB)
109 07:27:14.896835 progress 70 % (7 MB)
110 07:27:14.979313 progress 75 % (8 MB)
111 07:27:15.063041 progress 80 % (8 MB)
112 07:27:15.139607 progress 85 % (9 MB)
113 07:27:15.222881 progress 90 % (10 MB)
114 07:27:15.301963 progress 95 % (10 MB)
115 07:27:15.379488 progress 100 % (11 MB)
116 07:27:15.390918 11 MB downloaded in 1.73 s (6.42 MB/s)
117 07:27:15.391604 end: 1.4.1 http-download (duration 00:00:02) [common]
119 07:27:15.392604 end: 1.4 download-retry (duration 00:00:02) [common]
120 07:27:15.392932 start: 1.5 prepare-tftp-overlay (timeout 00:09:57) [common]
121 07:27:15.393236 start: 1.5.1 extract-nfsrootfs (timeout 00:09:57) [common]
122 07:27:15.393516 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 07:27:15.393799 start: 1.5.2 lava-overlay (timeout 00:09:57) [common]
124 07:27:15.394584 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/933151/lava-overlay-lcbu_t8i
125 07:27:15.395139 makedir: /var/lib/lava/dispatcher/tmp/933151/lava-overlay-lcbu_t8i/lava-933151/bin
126 07:27:15.395543 makedir: /var/lib/lava/dispatcher/tmp/933151/lava-overlay-lcbu_t8i/lava-933151/tests
127 07:27:15.395949 makedir: /var/lib/lava/dispatcher/tmp/933151/lava-overlay-lcbu_t8i/lava-933151/results
128 07:27:15.396385 Creating /var/lib/lava/dispatcher/tmp/933151/lava-overlay-lcbu_t8i/lava-933151/bin/lava-add-keys
129 07:27:15.397024 Creating /var/lib/lava/dispatcher/tmp/933151/lava-overlay-lcbu_t8i/lava-933151/bin/lava-add-sources
130 07:27:15.397616 Creating /var/lib/lava/dispatcher/tmp/933151/lava-overlay-lcbu_t8i/lava-933151/bin/lava-background-process-start
131 07:27:15.398201 Creating /var/lib/lava/dispatcher/tmp/933151/lava-overlay-lcbu_t8i/lava-933151/bin/lava-background-process-stop
132 07:27:15.398815 Creating /var/lib/lava/dispatcher/tmp/933151/lava-overlay-lcbu_t8i/lava-933151/bin/lava-common-functions
133 07:27:15.399396 Creating /var/lib/lava/dispatcher/tmp/933151/lava-overlay-lcbu_t8i/lava-933151/bin/lava-echo-ipv4
134 07:27:15.400421 Creating /var/lib/lava/dispatcher/tmp/933151/lava-overlay-lcbu_t8i/lava-933151/bin/lava-install-packages
135 07:27:15.401024 Creating /var/lib/lava/dispatcher/tmp/933151/lava-overlay-lcbu_t8i/lava-933151/bin/lava-installed-packages
136 07:27:15.401560 Creating /var/lib/lava/dispatcher/tmp/933151/lava-overlay-lcbu_t8i/lava-933151/bin/lava-os-build
137 07:27:15.402105 Creating /var/lib/lava/dispatcher/tmp/933151/lava-overlay-lcbu_t8i/lava-933151/bin/lava-probe-channel
138 07:27:15.402651 Creating /var/lib/lava/dispatcher/tmp/933151/lava-overlay-lcbu_t8i/lava-933151/bin/lava-probe-ip
139 07:27:15.403190 Creating /var/lib/lava/dispatcher/tmp/933151/lava-overlay-lcbu_t8i/lava-933151/bin/lava-target-ip
140 07:27:15.403725 Creating /var/lib/lava/dispatcher/tmp/933151/lava-overlay-lcbu_t8i/lava-933151/bin/lava-target-mac
141 07:27:15.404318 Creating /var/lib/lava/dispatcher/tmp/933151/lava-overlay-lcbu_t8i/lava-933151/bin/lava-target-storage
142 07:27:15.404899 Creating /var/lib/lava/dispatcher/tmp/933151/lava-overlay-lcbu_t8i/lava-933151/bin/lava-test-case
143 07:27:15.405464 Creating /var/lib/lava/dispatcher/tmp/933151/lava-overlay-lcbu_t8i/lava-933151/bin/lava-test-event
144 07:27:15.405998 Creating /var/lib/lava/dispatcher/tmp/933151/lava-overlay-lcbu_t8i/lava-933151/bin/lava-test-feedback
145 07:27:15.406522 Creating /var/lib/lava/dispatcher/tmp/933151/lava-overlay-lcbu_t8i/lava-933151/bin/lava-test-raise
146 07:27:15.407061 Creating /var/lib/lava/dispatcher/tmp/933151/lava-overlay-lcbu_t8i/lava-933151/bin/lava-test-reference
147 07:27:15.407591 Creating /var/lib/lava/dispatcher/tmp/933151/lava-overlay-lcbu_t8i/lava-933151/bin/lava-test-runner
148 07:27:15.408153 Creating /var/lib/lava/dispatcher/tmp/933151/lava-overlay-lcbu_t8i/lava-933151/bin/lava-test-set
149 07:27:15.408703 Creating /var/lib/lava/dispatcher/tmp/933151/lava-overlay-lcbu_t8i/lava-933151/bin/lava-test-shell
150 07:27:15.409260 Updating /var/lib/lava/dispatcher/tmp/933151/lava-overlay-lcbu_t8i/lava-933151/bin/lava-install-packages (oe)
151 07:27:15.409862 Updating /var/lib/lava/dispatcher/tmp/933151/lava-overlay-lcbu_t8i/lava-933151/bin/lava-installed-packages (oe)
152 07:27:15.410372 Creating /var/lib/lava/dispatcher/tmp/933151/lava-overlay-lcbu_t8i/lava-933151/environment
153 07:27:15.410815 LAVA metadata
154 07:27:15.411101 - LAVA_JOB_ID=933151
155 07:27:15.411339 - LAVA_DISPATCHER_IP=192.168.6.2
156 07:27:15.411730 start: 1.5.2.1 ssh-authorize (timeout 00:09:57) [common]
157 07:27:15.412857 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 07:27:15.413204 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:57) [common]
159 07:27:15.413428 skipped lava-vland-overlay
160 07:27:15.413688 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 07:27:15.413961 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:57) [common]
162 07:27:15.414195 skipped lava-multinode-overlay
163 07:27:15.414464 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 07:27:15.414737 start: 1.5.2.4 test-definition (timeout 00:09:57) [common]
165 07:27:15.415008 Loading test definitions
166 07:27:15.415308 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:57) [common]
167 07:27:15.415545 Using /lava-933151 at stage 0
168 07:27:15.416810 uuid=933151_1.5.2.4.1 testdef=None
169 07:27:15.417140 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 07:27:15.417432 start: 1.5.2.4.2 test-overlay (timeout 00:09:57) [common]
171 07:27:15.419391 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 07:27:15.420277 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:57) [common]
174 07:27:15.422711 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 07:27:15.423618 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:57) [common]
177 07:27:15.426722 runner path: /var/lib/lava/dispatcher/tmp/933151/lava-overlay-lcbu_t8i/lava-933151/0/tests/0_dmesg test_uuid 933151_1.5.2.4.1
178 07:27:15.427325 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 07:27:15.428154 Creating lava-test-runner.conf files
181 07:27:15.428368 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/933151/lava-overlay-lcbu_t8i/lava-933151/0 for stage 0
182 07:27:15.428740 - 0_dmesg
183 07:27:15.429106 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 07:27:15.429397 start: 1.5.2.5 compress-overlay (timeout 00:09:57) [common]
185 07:27:15.454703 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 07:27:15.455122 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:57) [common]
187 07:27:15.455382 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 07:27:15.455648 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 07:27:15.455909 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:57) [common]
190 07:27:16.393522 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
191 07:27:16.393990 start: 1.5.4 extract-modules (timeout 00:09:56) [common]
192 07:27:16.394237 extracting modules file /var/lib/lava/dispatcher/tmp/933151/tftp-deploy-jqv6xjhh/modules/modules.tar to /var/lib/lava/dispatcher/tmp/933151/extract-overlay-ramdisk-w8r0017o/ramdisk
193 07:27:17.741400 end: 1.5.4 extract-modules (duration 00:00:01) [common]
194 07:27:17.741850 start: 1.5.5 apply-overlay-tftp (timeout 00:09:55) [common]
195 07:27:17.742123 [common] Applying overlay /var/lib/lava/dispatcher/tmp/933151/compress-overlay-kom0u1iq/overlay-1.5.2.5.tar.gz to ramdisk
196 07:27:17.742335 [common] Applying overlay /var/lib/lava/dispatcher/tmp/933151/compress-overlay-kom0u1iq/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/933151/extract-overlay-ramdisk-w8r0017o/ramdisk
197 07:27:17.772924 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 07:27:17.773384 start: 1.5.6 prepare-kernel (timeout 00:09:55) [common]
199 07:27:17.773654 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:55) [common]
200 07:27:17.773883 Converting downloaded kernel to a uImage
201 07:27:17.774207 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/933151/tftp-deploy-jqv6xjhh/kernel/Image /var/lib/lava/dispatcher/tmp/933151/tftp-deploy-jqv6xjhh/kernel/uImage
202 07:27:18.285311 output: Image Name:
203 07:27:18.285741 output: Created: Mon Nov 4 07:27:17 2024
204 07:27:18.285989 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 07:27:18.286224 output: Data Size: 46041600 Bytes = 44962.50 KiB = 43.91 MiB
206 07:27:18.286458 output: Load Address: 01080000
207 07:27:18.286688 output: Entry Point: 01080000
208 07:27:18.286915 output:
209 07:27:18.287280 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:01) [common]
210 07:27:18.287597 end: 1.5.6 prepare-kernel (duration 00:00:01) [common]
211 07:27:18.287919 start: 1.5.7 configure-preseed-file (timeout 00:09:54) [common]
212 07:27:18.288265 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 07:27:18.288568 start: 1.5.8 compress-ramdisk (timeout 00:09:54) [common]
214 07:27:18.288856 Building ramdisk /var/lib/lava/dispatcher/tmp/933151/extract-overlay-ramdisk-w8r0017o/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/933151/extract-overlay-ramdisk-w8r0017o/ramdisk
215 07:27:20.668177 >> 182797 blocks
216 07:27:29.182325 Adding RAMdisk u-boot header.
217 07:27:29.183264 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/933151/extract-overlay-ramdisk-w8r0017o/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/933151/extract-overlay-ramdisk-w8r0017o/ramdisk.cpio.gz.uboot
218 07:27:29.493494 output: Image Name:
219 07:27:29.494156 output: Created: Mon Nov 4 07:27:29 2024
220 07:27:29.494611 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 07:27:29.495059 output: Data Size: 26168259 Bytes = 25554.94 KiB = 24.96 MiB
222 07:27:29.495498 output: Load Address: 00000000
223 07:27:29.495936 output: Entry Point: 00000000
224 07:27:29.496426 output:
225 07:27:29.497701 rename /var/lib/lava/dispatcher/tmp/933151/extract-overlay-ramdisk-w8r0017o/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/933151/tftp-deploy-jqv6xjhh/ramdisk/ramdisk.cpio.gz.uboot
226 07:27:29.498484 end: 1.5.8 compress-ramdisk (duration 00:00:11) [common]
227 07:27:29.499074 end: 1.5 prepare-tftp-overlay (duration 00:00:14) [common]
228 07:27:29.499652 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:43) [common]
229 07:27:29.500190 No LXC device requested
230 07:27:29.500741 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 07:27:29.501295 start: 1.7 deploy-device-env (timeout 00:09:43) [common]
232 07:27:29.501833 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 07:27:29.502283 Checking files for TFTP limit of 4294967296 bytes.
234 07:27:29.505200 end: 1 tftp-deploy (duration 00:00:17) [common]
235 07:27:29.505829 start: 2 uboot-action (timeout 00:05:00) [common]
236 07:27:29.506401 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 07:27:29.506947 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 07:27:29.507518 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 07:27:29.508135 Using kernel file from prepare-kernel: 933151/tftp-deploy-jqv6xjhh/kernel/uImage
240 07:27:29.508830 substitutions:
241 07:27:29.509285 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 07:27:29.509730 - {DTB_ADDR}: 0x01070000
243 07:27:29.510173 - {DTB}: 933151/tftp-deploy-jqv6xjhh/dtb/meson-sm1-s905d3-libretech-cc.dtb
244 07:27:29.510614 - {INITRD}: 933151/tftp-deploy-jqv6xjhh/ramdisk/ramdisk.cpio.gz.uboot
245 07:27:29.511052 - {KERNEL_ADDR}: 0x01080000
246 07:27:29.511482 - {KERNEL}: 933151/tftp-deploy-jqv6xjhh/kernel/uImage
247 07:27:29.511917 - {LAVA_MAC}: None
248 07:27:29.512423 - {PRESEED_CONFIG}: None
249 07:27:29.512860 - {PRESEED_LOCAL}: None
250 07:27:29.513289 - {RAMDISK_ADDR}: 0x08000000
251 07:27:29.513719 - {RAMDISK}: 933151/tftp-deploy-jqv6xjhh/ramdisk/ramdisk.cpio.gz.uboot
252 07:27:29.514154 - {ROOT_PART}: None
253 07:27:29.514583 - {ROOT}: None
254 07:27:29.515012 - {SERVER_IP}: 192.168.6.2
255 07:27:29.515445 - {TEE_ADDR}: 0x83000000
256 07:27:29.515871 - {TEE}: None
257 07:27:29.516328 Parsed boot commands:
258 07:27:29.516747 - setenv autoload no
259 07:27:29.517175 - setenv initrd_high 0xffffffff
260 07:27:29.517609 - setenv fdt_high 0xffffffff
261 07:27:29.518041 - dhcp
262 07:27:29.518469 - setenv serverip 192.168.6.2
263 07:27:29.518893 - tftpboot 0x01080000 933151/tftp-deploy-jqv6xjhh/kernel/uImage
264 07:27:29.519317 - tftpboot 0x08000000 933151/tftp-deploy-jqv6xjhh/ramdisk/ramdisk.cpio.gz.uboot
265 07:27:29.519743 - tftpboot 0x01070000 933151/tftp-deploy-jqv6xjhh/dtb/meson-sm1-s905d3-libretech-cc.dtb
266 07:27:29.520217 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 07:27:29.520658 - bootm 0x01080000 0x08000000 0x01070000
268 07:27:29.521207 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 07:27:29.522830 start: 2.3 connect-device (timeout 00:05:00) [common]
271 07:27:29.523313 [common] connect-device Connecting to device using 'telnet conserv1 3008'
272 07:27:29.538360 Setting prompt string to ['lava-test: # ']
273 07:27:29.539934 end: 2.3 connect-device (duration 00:00:00) [common]
274 07:27:29.540619 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 07:27:29.541201 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 07:27:29.541853 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 07:27:29.543384 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=solitude-01'
278 07:27:29.580194 >> OK - accepted request
279 07:27:29.582583 Returned 0 in 0 seconds
280 07:27:29.683757 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
282 07:27:29.685567 end: 2.4.1 reset-device (duration 00:00:00) [common]
283 07:27:29.686187 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
284 07:27:29.686737 Setting prompt string to ['Hit any key to stop autoboot']
285 07:27:29.687232 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 07:27:29.688996 Trying 192.168.56.21...
287 07:27:29.689540 Connected to conserv1.
288 07:27:29.689995 Escape character is '^]'.
289 07:27:29.690440
290 07:27:29.690903 ser2net port telnet,3008 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.3.3:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
291 07:27:29.691375
292 07:27:36.860451 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
293 07:27:36.861288 bl2_stage_init 0x01
294 07:27:36.861932 bl2_stage_init 0x81
295 07:27:36.866089 hw id: 0x0000 - pwm id 0x01
296 07:27:36.866778 bl2_stage_init 0xc1
297 07:27:36.871742 bl2_stage_init 0x02
298 07:27:36.872460
299 07:27:36.873086 L0:00000000
300 07:27:36.873679 L1:00000703
301 07:27:36.874260 L2:00008067
302 07:27:36.874842 L3:15000000
303 07:27:36.877140 S1:00000000
304 07:27:36.877777 B2:20282000
305 07:27:36.878384 B1:a0f83180
306 07:27:36.878972
307 07:27:36.879511 TE: 69612
308 07:27:36.880137
309 07:27:36.882636 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
310 07:27:36.883284
311 07:27:36.888346 Board ID = 1
312 07:27:36.888877 Set cpu clk to 24M
313 07:27:36.889326 Set clk81 to 24M
314 07:27:36.894008 Use GP1_pll as DSU clk.
315 07:27:36.894635 DSU clk: 1200 Mhz
316 07:27:36.895200 CPU clk: 1200 MHz
317 07:27:36.899389 Set clk81 to 166.6M
318 07:27:36.905112 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
319 07:27:36.905744 board id: 1
320 07:27:36.912305 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
321 07:27:36.923207 fw parse done
322 07:27:36.929123 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
323 07:27:36.971415 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
324 07:27:36.983377 PIEI prepare done
325 07:27:36.984099 fastboot data load
326 07:27:36.984627 fastboot data verify
327 07:27:36.988983 verify result: 266
328 07:27:36.994558 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
329 07:27:36.995200 LPDDR4 probe
330 07:27:36.995787 ddr clk to 1584MHz
331 07:27:37.002530 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
332 07:27:37.040314
333 07:27:37.040953 dmc_version 0001
334 07:27:37.047293 Check phy result
335 07:27:37.053286 INFO : End of CA training
336 07:27:37.053910 INFO : End of initialization
337 07:27:37.059006 INFO : Training has run successfully!
338 07:27:37.059620 Check phy result
339 07:27:37.064494 INFO : End of initialization
340 07:27:37.065111 INFO : End of read enable training
341 07:27:37.070094 INFO : End of fine write leveling
342 07:27:37.075662 INFO : End of Write leveling coarse delay
343 07:27:37.076352 INFO : Training has run successfully!
344 07:27:37.076962 Check phy result
345 07:27:37.081282 INFO : End of initialization
346 07:27:37.081997 INFO : End of read dq deskew training
347 07:27:37.087002 INFO : End of MPR read delay center optimization
348 07:27:37.092484 INFO : End of write delay center optimization
349 07:27:37.098151 INFO : End of read delay center optimization
350 07:27:37.098800 INFO : End of max read latency training
351 07:27:37.103696 INFO : Training has run successfully!
352 07:27:37.104370 1D training succeed
353 07:27:37.112985 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
354 07:27:37.161145 Check phy result
355 07:27:37.161821 INFO : End of initialization
356 07:27:37.188513 INFO : End of 2D read delay Voltage center optimization
357 07:27:37.212790 INFO : End of 2D read delay Voltage center optimization
358 07:27:37.269380 INFO : End of 2D write delay Voltage center optimization
359 07:27:37.323499 INFO : End of 2D write delay Voltage center optimization
360 07:27:37.329068 INFO : Training has run successfully!
361 07:27:37.329734
362 07:27:37.330344 channel==0
363 07:27:37.334601 RxClkDly_Margin_A0==88 ps 9
364 07:27:37.335249 TxDqDly_Margin_A0==98 ps 10
365 07:27:37.337899 RxClkDly_Margin_A1==88 ps 9
366 07:27:37.338543 TxDqDly_Margin_A1==98 ps 10
367 07:27:37.343686 TrainedVREFDQ_A0==74
368 07:27:37.344335 TrainedVREFDQ_A1==74
369 07:27:37.349107 VrefDac_Margin_A0==24
370 07:27:37.349751 DeviceVref_Margin_A0==40
371 07:27:37.350265 VrefDac_Margin_A1==23
372 07:27:37.354624 DeviceVref_Margin_A1==40
373 07:27:37.355255
374 07:27:37.355820
375 07:27:37.356456 channel==1
376 07:27:37.357015 RxClkDly_Margin_A0==78 ps 8
377 07:27:37.360270 TxDqDly_Margin_A0==98 ps 10
378 07:27:37.360894 RxClkDly_Margin_A1==88 ps 9
379 07:27:37.365851 TxDqDly_Margin_A1==88 ps 9
380 07:27:37.366509 TrainedVREFDQ_A0==78
381 07:27:37.367077 TrainedVREFDQ_A1==75
382 07:27:37.371487 VrefDac_Margin_A0==22
383 07:27:37.372137 DeviceVref_Margin_A0==36
384 07:27:37.377097 VrefDac_Margin_A1==22
385 07:27:37.377740 DeviceVref_Margin_A1==39
386 07:27:37.378257
387 07:27:37.382708 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
388 07:27:37.383326
389 07:27:37.410657 soc_vref_reg_value 0x 00000019 00000019 00000018 00000017 00000018 00000015 00000018 00000016 00000017 00000018 00000017 00000017 00000017 00000018 00000017 00000019 00000018 00000017 00000018 00000015 00000018 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001c 00000017 00000016 00000017 dram_vref_reg_value 0x 00000061
390 07:27:37.416233 2D training succeed
391 07:27:37.421821 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
392 07:27:37.422470 auto size-- 65535DDR cs0 size: 2048MB
393 07:27:37.427409 DDR cs1 size: 2048MB
394 07:27:37.428076 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
395 07:27:37.433056 cs0 DataBus test pass
396 07:27:37.433672 cs1 DataBus test pass
397 07:27:37.434183 cs0 AddrBus test pass
398 07:27:37.438671 cs1 AddrBus test pass
399 07:27:37.439298
400 07:27:37.439865 100bdlr_step_size ps== 471
401 07:27:37.440474 result report
402 07:27:37.444288 boot times 0Enable ddr reg access
403 07:27:37.451870 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
404 07:27:37.465728 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
405 07:27:38.125685 bl2z: ptr: 05129330, size: 00001e40
406 07:27:38.134068 0.0;M3 CHK:0;cm4_sp_mode 0
407 07:27:38.134745 MVN_1=0x00000000
408 07:27:38.135317 MVN_2=0x00000000
409 07:27:38.145609 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
410 07:27:38.146271 OPS=0x04
411 07:27:38.146878 ring efuse init
412 07:27:38.148532 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
413 07:27:38.155047 [0.017354 Inits done]
414 07:27:38.155686 secure task start!
415 07:27:38.156370 high task start!
416 07:27:38.156887 low task start!
417 07:27:38.159274 run into bl31
418 07:27:38.167926 NOTICE: BL31: v1.3(release):4fc40b1
419 07:27:38.175677 NOTICE: BL31: Built : 15:57:33, May 22 2019
420 07:27:38.176345 NOTICE: BL31: G12A normal boot!
421 07:27:38.191357 NOTICE: BL31: BL33 decompress pass
422 07:27:38.197000 ERROR: Error initializing runtime service opteed_fast
423 07:27:40.910419 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0; SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
424 07:27:40.911346 bl2_stage_init 0x01
425 07:27:40.912070 bl2_stage_init 0x81
426 07:27:40.915901 hw id: 0x0000 - pwm id 0x01
427 07:27:40.916717 bl2_stage_init 0xc1
428 07:27:40.920308 bl2_stage_init 0x02
429 07:27:40.921079
430 07:27:40.921746 L0:00000000
431 07:27:40.922435 L1:00000703
432 07:27:40.923066 L2:00008067
433 07:27:40.925828 L3:15000000
434 07:27:40.926561 S1:00000000
435 07:27:40.927195 B2:20282000
436 07:27:40.927873 B1:a0f83180
437 07:27:40.928617
438 07:27:40.929263 TE: 69790
439 07:27:40.931460
440 07:27:40.937010 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
441 07:27:40.937744
442 07:27:40.938385 Board ID = 1
443 07:27:40.939080 Set cpu clk to 24M
444 07:27:40.939764 Set clk81 to 24M
445 07:27:40.940808 Use GP1_pll as DSU clk.
446 07:27:40.945903 DSU clk: 1200 Mhz
447 07:27:40.946571 CPU clk: 1200 MHz
448 07:27:40.947290 Set clk81 to 166.6M
449 07:27:40.951486 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
450 07:27:40.957099 board id: 1
451 07:27:40.961296 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
452 07:27:40.973204 fw parse done
453 07:27:40.979150 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
454 07:27:41.022288 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
455 07:27:41.033616 PIEI prepare done
456 07:27:41.034177 fastboot data load
457 07:27:41.034661 fastboot data verify
458 07:27:41.039005 verify result: 266
459 07:27:41.044673 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
460 07:27:41.045237 LPDDR4 probe
461 07:27:41.045714 ddr clk to 1584MHz
462 07:27:41.052784 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
463 07:27:41.090464
464 07:27:41.091332 dmc_version 0001
465 07:27:41.097431 Check phy result
466 07:27:41.103473 INFO : End of CA training
467 07:27:41.104286 INFO : End of initialization
468 07:27:41.108955 INFO : Training has run successfully!
469 07:27:41.109504 Check phy result
470 07:27:41.114630 INFO : End of initialization
471 07:27:41.115202 INFO : End of read enable training
472 07:27:41.120345 INFO : End of fine write leveling
473 07:27:41.131025 INFO : End of Write leveling coarse delay
474 07:27:41.131810 INFO : Training has run successfully!
475 07:27:41.132553 Check phy result
476 07:27:41.133579 INFO : End of initialization
477 07:27:41.134301 INFO : End of read dq deskew training
478 07:27:41.139017 INFO : End of MPR read delay center optimization
479 07:27:41.144573 INFO : End of write delay center optimization
480 07:27:41.145116 INFO : End of read delay center optimization
481 07:27:41.150149 INFO : End of max read latency training
482 07:27:41.155756 INFO : Training has run successfully!
483 07:27:41.156331 1D training succeed
484 07:27:41.163041 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
485 07:27:41.211316 Check phy result
486 07:27:41.211891 INFO : End of initialization
487 07:27:41.238684 INFO : End of 2D read delay Voltage center optimization
488 07:27:41.262889 INFO : End of 2D read delay Voltage center optimization
489 07:27:41.319643 INFO : End of 2D write delay Voltage center optimization
490 07:27:41.373739 INFO : End of 2D write delay Voltage center optimization
491 07:27:41.379057 INFO : Training has run successfully!
492 07:27:41.379365
493 07:27:41.379607 channel==0
494 07:27:41.384619 RxClkDly_Margin_A0==78 ps 8
495 07:27:41.385027 TxDqDly_Margin_A0==88 ps 9
496 07:27:41.390261 RxClkDly_Margin_A1==88 ps 9
497 07:27:41.390559 TxDqDly_Margin_A1==98 ps 10
498 07:27:41.390795 TrainedVREFDQ_A0==74
499 07:27:41.395783 TrainedVREFDQ_A1==74
500 07:27:41.396210 VrefDac_Margin_A0==24
501 07:27:41.396491 DeviceVref_Margin_A0==40
502 07:27:41.401503 VrefDac_Margin_A1==23
503 07:27:41.401919 DeviceVref_Margin_A1==40
504 07:27:41.402279
505 07:27:41.402597
506 07:27:41.402960 channel==1
507 07:27:41.406967 RxClkDly_Margin_A0==88 ps 9
508 07:27:41.407272 TxDqDly_Margin_A0==88 ps 9
509 07:27:41.412508 RxClkDly_Margin_A1==78 ps 8
510 07:27:41.412816 TxDqDly_Margin_A1==88 ps 9
511 07:27:41.418127 TrainedVREFDQ_A0==75
512 07:27:41.418426 TrainedVREFDQ_A1==75
513 07:27:41.418767 VrefDac_Margin_A0==22
514 07:27:41.423729 DeviceVref_Margin_A0==38
515 07:27:41.424054 VrefDac_Margin_A1==22
516 07:27:41.424298 DeviceVref_Margin_A1==39
517 07:27:41.429396
518 07:27:41.429685 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
519 07:27:41.429922
520 07:27:41.463107 soc_vref_reg_value 0x 0000001a 00000019 00000019 00000017 00000019 00000016 00000018 00000016 00000018 00000017 00000017 00000018 00000017 00000018 00000018 00000019 00000018 00000017 00000018 00000015 00000018 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001c 00000017 00000016 00000017 dram_vref_reg_value 0x 00000061
521 07:27:41.463731 2D training succeed
522 07:27:41.468729 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
523 07:27:41.474110 auto size-- 65535DDR cs0 size: 2048MB
524 07:27:41.474435 DDR cs1 size: 2048MB
525 07:27:41.479706 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
526 07:27:41.480027 cs0 DataBus test pass
527 07:27:41.485429 cs1 DataBus test pass
528 07:27:41.485718 cs0 AddrBus test pass
529 07:27:41.485944 cs1 AddrBus test pass
530 07:27:41.486163
531 07:27:41.490887 100bdlr_step_size ps== 485
532 07:27:41.491164 result report
533 07:27:41.496494 boot times 0Enable ddr reg access
534 07:27:41.501579 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
535 07:27:41.515496 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
536 07:27:42.174916 bl2z: ptr: 05129330, size: 00001e40
537 07:27:42.182104 0.0;M3 CHK:0;cm4_sp_mode 0
538 07:27:42.182492 MVN_1=0x00000000
539 07:27:42.182828 MVN_2=0x00000000
540 07:27:42.193673 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
541 07:27:42.194102 OPS=0x04
542 07:27:42.194403 ring efuse init
543 07:27:42.196629 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
544 07:27:42.203008 [0.017354 Inits done]
545 07:27:42.203363 secure task start!
546 07:27:42.203686 high task start!
547 07:27:42.203953 low task start!
548 07:27:42.207151 run into bl31
549 07:27:42.215762 NOTICE: BL31: v1.3(release):4fc40b1
550 07:27:42.223722 NOTICE: BL31: Built : 15:57:33, May 22 2019
551 07:27:42.224271 NOTICE: BL31: G12A normal boot!
552 07:27:42.239207 NOTICE: BL31: BL33 decompress pass
553 07:27:42.244957 ERROR: Error initializing runtime service opteed_fast
554 07:27:43.612029 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
555 07:27:43.612414 bl2_stage_init 0x01
556 07:27:43.612628 bl2_stage_init 0x81
557 07:27:43.617552 hw id: 0x0000 - pwm id 0x01
558 07:27:43.617825 bl2_stage_init 0xc1
559 07:27:43.623170 bl2_stage_init 0x02
560 07:27:43.623449
561 07:27:43.623656 L0:00000000
562 07:27:43.623856 L1:00000703
563 07:27:43.624082 L2:00008067
564 07:27:43.624284 L3:15000000
565 07:27:43.628712 S1:00000000
566 07:27:43.628974 B2:20282000
567 07:27:43.629184 B1:a0f83180
568 07:27:43.629384
569 07:27:43.629584 TE: 69745
570 07:27:43.629782
571 07:27:43.634267 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
572 07:27:43.634533
573 07:27:43.639898 Board ID = 1
574 07:27:43.640181 Set cpu clk to 24M
575 07:27:43.640386 Set clk81 to 24M
576 07:27:43.645518 Use GP1_pll as DSU clk.
577 07:27:43.645792 DSU clk: 1200 Mhz
578 07:27:43.645998 CPU clk: 1200 MHz
579 07:27:43.651063 Set clk81 to 166.6M
580 07:27:43.656736 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
581 07:27:43.657022 board id: 1
582 07:27:43.663933 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
583 07:27:43.674914 fw parse done
584 07:27:43.680695 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
585 07:27:43.723757 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
586 07:27:43.734799 PIEI prepare done
587 07:27:43.735078 fastboot data load
588 07:27:43.735294 fastboot data verify
589 07:27:43.740408 verify result: 266
590 07:27:43.746025 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
591 07:27:43.746317 LPDDR4 probe
592 07:27:43.746609 ddr clk to 1584MHz
593 07:27:43.754024 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
594 07:27:43.791838
595 07:27:43.792186 dmc_version 0001
596 07:27:43.798849 Check phy result
597 07:27:43.804811 INFO : End of CA training
598 07:27:43.805089 INFO : End of initialization
599 07:27:43.810365 INFO : Training has run successfully!
600 07:27:43.810633 Check phy result
601 07:27:43.816000 INFO : End of initialization
602 07:27:43.816495 INFO : End of read enable training
603 07:27:43.821813 INFO : End of fine write leveling
604 07:27:43.827322 INFO : End of Write leveling coarse delay
605 07:27:43.827826 INFO : Training has run successfully!
606 07:27:43.828315 Check phy result
607 07:27:43.832917 INFO : End of initialization
608 07:27:43.833426 INFO : End of read dq deskew training
609 07:27:43.838526 INFO : End of MPR read delay center optimization
610 07:27:43.844117 INFO : End of write delay center optimization
611 07:27:43.849733 INFO : End of read delay center optimization
612 07:27:43.850236 INFO : End of max read latency training
613 07:27:43.855292 INFO : Training has run successfully!
614 07:27:43.855799 1D training succeed
615 07:27:43.864443 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
616 07:27:43.912804 Check phy result
617 07:27:43.913336 INFO : End of initialization
618 07:27:43.940202 INFO : End of 2D read delay Voltage center optimization
619 07:27:43.964301 INFO : End of 2D read delay Voltage center optimization
620 07:27:44.021022 INFO : End of 2D write delay Voltage center optimization
621 07:27:44.074971 INFO : End of 2D write delay Voltage center optimization
622 07:27:44.080497 INFO : Training has run successfully!
623 07:27:44.081009
624 07:27:44.081468 channel==0
625 07:27:44.086130 RxClkDly_Margin_A0==88 ps 9
626 07:27:44.086641 TxDqDly_Margin_A0==98 ps 10
627 07:27:44.091733 RxClkDly_Margin_A1==88 ps 9
628 07:27:44.092280 TxDqDly_Margin_A1==88 ps 9
629 07:27:44.092727 TrainedVREFDQ_A0==74
630 07:27:44.097337 TrainedVREFDQ_A1==74
631 07:27:44.097843 VrefDac_Margin_A0==24
632 07:27:44.098280 DeviceVref_Margin_A0==40
633 07:27:44.102978 VrefDac_Margin_A1==23
634 07:27:44.103479 DeviceVref_Margin_A1==40
635 07:27:44.103915
636 07:27:44.104394
637 07:27:44.104830 channel==1
638 07:27:44.108528 RxClkDly_Margin_A0==78 ps 8
639 07:27:44.109035 TxDqDly_Margin_A0==98 ps 10
640 07:27:44.114151 RxClkDly_Margin_A1==88 ps 9
641 07:27:44.114661 TxDqDly_Margin_A1==88 ps 9
642 07:27:44.119731 TrainedVREFDQ_A0==75
643 07:27:44.120272 TrainedVREFDQ_A1==75
644 07:27:44.120716 VrefDac_Margin_A0==22
645 07:27:44.125347 DeviceVref_Margin_A0==39
646 07:27:44.125854 VrefDac_Margin_A1==22
647 07:27:44.130968 DeviceVref_Margin_A1==39
648 07:27:44.131470
649 07:27:44.131908 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
650 07:27:44.132381
651 07:27:44.164480 soc_vref_reg_value 0x 00000019 00000019 00000019 00000017 00000019 00000015 00000018 00000016 00000018 00000017 00000017 00000017 00000017 00000018 00000018 00000019 00000018 00000017 00000018 00000015 00000017 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001c 00000017 00000016 00000017 dram_vref_reg_value 0x 00000061
652 07:27:44.165064 2D training succeed
653 07:27:44.170133 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
654 07:27:44.175692 auto size-- 65535DDR cs0 size: 2048MB
655 07:27:44.176230 DDR cs1 size: 2048MB
656 07:27:44.181324 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
657 07:27:44.181833 cs0 DataBus test pass
658 07:27:44.186954 cs1 DataBus test pass
659 07:27:44.187458 cs0 AddrBus test pass
660 07:27:44.187895 cs1 AddrBus test pass
661 07:27:44.188368
662 07:27:44.192558 100bdlr_step_size ps== 464
663 07:27:44.193081 result report
664 07:27:44.198128 boot times 0Enable ddr reg access
665 07:27:44.203301 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
666 07:27:44.217128 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
667 07:27:44.877155 bl2z: ptr: 05129330, size: 00001e40
668 07:27:44.885912 0.0;M3 CHK:0;cm4_sp_mode 0
669 07:27:44.886315 MVN_1=0x00000000
670 07:27:44.886561 MVN_2=0x00000000
671 07:27:44.897364 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
672 07:27:44.897770 OPS=0x04
673 07:27:44.898019 ring efuse init
674 07:27:44.900243 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
675 07:27:44.906440 [0.017355 Inits done]
676 07:27:44.906806 secure task start!
677 07:27:44.907047 high task start!
678 07:27:44.907275 low task start!
679 07:27:44.910728 run into bl31
680 07:27:44.919357 NOTICE: BL31: v1.3(release):4fc40b1
681 07:27:44.927168 NOTICE: BL31: Built : 15:57:33, May 22 2019
682 07:27:44.927546 NOTICE: BL31: G12A normal boot!
683 07:27:44.942729 NOTICE: BL31: BL33 decompress pass
684 07:27:44.948405 ERROR: Error initializing runtime service opteed_fast
685 07:27:45.743283
686 07:27:45.743890
687 07:27:45.748084 U-Boot 2024.01-rc4+ (Dec 14 2023 - 02:26:00 -0500) Libre Computer AML-S905D3-CC
688 07:27:45.748633
689 07:27:45.751494 Model: Libre Computer AML-S905D3-CC Solitude
690 07:27:45.898425 SoC: Amlogic Meson SM1 (S905D3) Revision 2b:c (4:2)
691 07:27:45.913759 DRAM: 2 GiB (effective 3.8 GiB)
692 07:27:46.014646 Core: 406 devices, 33 uclasses, devicetree: separate
693 07:27:46.020504 WDT: Not starting watchdog@f0d0
694 07:27:46.045646 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
695 07:27:46.057919 Loading Environment from FAT... Card did not respond to voltage select! : -110
696 07:27:46.062865 ** Bad device specification mmc 0 **
697 07:27:46.072963 Card did not respond to voltage select! : -110
698 07:27:46.080574 ** Bad device specification mmc 0 **
699 07:27:46.081090 Couldn't find partition mmc 0
700 07:27:46.088916 Card did not respond to voltage select! : -110
701 07:27:46.094441 ** Bad device specification mmc 0 **
702 07:27:46.094976 Couldn't find partition mmc 0
703 07:27:46.099478 Error: could not access storage.
704 07:27:46.395967 Net: eth0: ethernet@ff3f0000
705 07:27:46.396595 starting USB...
706 07:27:46.640490 Bus usb@ff500000: Register 3000140 NbrPorts 3
707 07:27:46.640906 Starting the controller
708 07:27:46.647398 USB XHCI 1.10
709 07:27:48.200979 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
710 07:27:48.209322 scanning usb for storage devices... 0 Storage Device(s) found
712 07:27:48.260873 Hit any key to stop autoboot: 1
713 07:27:48.261791 end: 2.4.2 bootloader-interrupt (duration 00:00:19) [common]
714 07:27:48.262448 start: 2.4.3 bootloader-commands (timeout 00:04:41) [common]
715 07:27:48.262772 Setting prompt string to ['=>']
716 07:27:48.263045 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:41)
717 07:27:48.275431 0
718 07:27:48.276495 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
720 07:27:48.377793 => setenv autoload no
721 07:27:48.378942 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
722 07:27:48.383167 setenv autoload no
724 07:27:48.484586 => setenv initrd_high 0xffffffff
725 07:27:48.485379 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
726 07:27:48.489744 setenv initrd_high 0xffffffff
728 07:27:48.591211 => setenv fdt_high 0xffffffff
729 07:27:48.592044 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
730 07:27:48.596424 setenv fdt_high 0xffffffff
732 07:27:48.697852 => dhcp
733 07:27:48.698598 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
734 07:27:48.702210 dhcp
735 07:27:49.258307 ethernet@ff3f0000 Waiting for PHY auto negotiation to complete. done
736 07:27:49.258734 Speed: 1000, full duplex
737 07:27:49.258965 BOOTP broadcast 1
738 07:27:49.506691 BOOTP broadcast 2
739 07:27:49.531945 DHCP client bound to address 192.168.6.21 (273 ms)
741 07:27:49.633352 => setenv serverip 192.168.6.2
742 07:27:49.634052 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
743 07:27:49.638679 setenv serverip 192.168.6.2
745 07:27:49.739820 => tftpboot 0x01080000 933151/tftp-deploy-jqv6xjhh/kernel/uImage
746 07:27:49.740707 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
747 07:27:49.747469 tftpboot 0x01080000 933151/tftp-deploy-jqv6xjhh/kernel/uImage
748 07:27:49.747966 Speed: 1000, full duplex
749 07:27:49.748405 Using ethernet@ff3f0000 device
750 07:27:49.752997 TFTP from server 192.168.6.2; our IP address is 192.168.6.21
751 07:27:49.758546 Filename '933151/tftp-deploy-jqv6xjhh/kernel/uImage'.
752 07:27:49.762382 Load address: 0x1080000
753 07:27:52.620118 Loading: *################################################## 43.9 MiB
754 07:27:52.620538 15.4 MiB/s
755 07:27:52.620751 done
756 07:27:52.624505 Bytes transferred = 46041664 (2be8a40 hex)
758 07:27:52.725603 => tftpboot 0x08000000 933151/tftp-deploy-jqv6xjhh/ramdisk/ramdisk.cpio.gz.uboot
759 07:27:52.726287 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:37)
760 07:27:52.732892 tftpboot 0x08000000 933151/tftp-deploy-jqv6xjhh/ramdisk/ramdisk.cpio.gz.uboot
761 07:27:52.733195 Speed: 1000, full duplex
762 07:27:52.733408 Using ethernet@ff3f0000 device
763 07:27:52.738372 TFTP from server 192.168.6.2; our IP address is 192.168.6.21
764 07:27:52.748242 Filename '933151/tftp-deploy-jqv6xjhh/ramdisk/ramdisk.cpio.gz.uboot'.
765 07:27:52.748566 Load address: 0x8000000
766 07:27:54.381550 Loading: *################################################# UDP wrong checksum 00000005 0000e870
767 07:27:59.382401 T UDP wrong checksum 00000005 0000e870
768 07:28:09.384578 T T UDP wrong checksum 00000005 0000e870
769 07:28:13.346287 UDP wrong checksum 000000ff 000095e1
770 07:28:13.384484 UDP wrong checksum 000000ff 00001ad4
771 07:28:29.388793 T T T T UDP wrong checksum 00000005 0000e870
772 07:28:49.393355 T T T
773 07:28:49.394013 Retry count exceeded; starting again
775 07:28:49.395563 end: 2.4.3 bootloader-commands (duration 00:01:01) [common]
778 07:28:49.397683 end: 2.4 uboot-commands (duration 00:01:20) [common]
780 07:28:49.399278 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
782 07:28:49.400456 end: 2 uboot-action (duration 00:01:20) [common]
784 07:28:49.402099 Cleaning after the job
785 07:28:49.402687 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/933151/tftp-deploy-jqv6xjhh/ramdisk
786 07:28:49.404130 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/933151/tftp-deploy-jqv6xjhh/kernel
787 07:28:49.451281 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/933151/tftp-deploy-jqv6xjhh/dtb
788 07:28:49.452155 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/933151/tftp-deploy-jqv6xjhh/modules
789 07:28:49.470432 start: 4.1 power-off (timeout 00:00:30) [common]
790 07:28:49.471054 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=solitude-01'
791 07:28:49.504781 >> OK - accepted request
792 07:28:49.507264 Returned 0 in 0 seconds
793 07:28:49.608014 end: 4.1 power-off (duration 00:00:00) [common]
795 07:28:49.609097 start: 4.2 read-feedback (timeout 00:10:00) [common]
796 07:28:49.609812 Listened to connection for namespace 'common' for up to 1s
797 07:28:50.610066 Finalising connection for namespace 'common'
798 07:28:50.610715 Disconnecting from shell: Finalise
799 07:28:50.611063 =>
800 07:28:50.712044 end: 4.2 read-feedback (duration 00:00:01) [common]
801 07:28:50.713152 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/933151
802 07:28:51.014913 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/933151
803 07:28:51.015487 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.