Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 07:33:25.844940 lava-dispatcher, installed at version: 2024.01
2 07:33:25.845761 start: 0 validate
3 07:33:25.846221 Start time: 2024-11-04 07:33:25.846191+00:00 (UTC)
4 07:33:25.846759 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 07:33:25.847295 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 07:33:25.887327 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 07:33:25.887838 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241104%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 07:33:25.915085 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 07:33:25.915708 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241104%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 07:33:25.943498 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 07:33:25.944009 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 07:33:25.974427 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 07:33:25.974925 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241104%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
14 07:33:26.010616 validate duration: 0.16
16 07:33:26.011472 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 07:33:26.011799 start: 1.1 download-retry (timeout 00:10:00) [common]
18 07:33:26.012145 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 07:33:26.012723 Not decompressing ramdisk as can be used compressed.
20 07:33:26.013167 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm/20240313.0/arm64/initrd.cpio.gz
21 07:33:26.013450 saving as /var/lib/lava/dispatcher/tmp/933217/tftp-deploy-czzkl2bm/ramdisk/initrd.cpio.gz
22 07:33:26.013721 total size: 5628182 (5 MB)
23 07:33:26.047006 progress 0 % (0 MB)
24 07:33:26.051309 progress 5 % (0 MB)
25 07:33:26.055633 progress 10 % (0 MB)
26 07:33:26.059266 progress 15 % (0 MB)
27 07:33:26.063315 progress 20 % (1 MB)
28 07:33:26.066899 progress 25 % (1 MB)
29 07:33:26.070976 progress 30 % (1 MB)
30 07:33:26.074957 progress 35 % (1 MB)
31 07:33:26.078501 progress 40 % (2 MB)
32 07:33:26.082531 progress 45 % (2 MB)
33 07:33:26.086194 progress 50 % (2 MB)
34 07:33:26.090151 progress 55 % (2 MB)
35 07:33:26.094127 progress 60 % (3 MB)
36 07:33:26.097663 progress 65 % (3 MB)
37 07:33:26.101722 progress 70 % (3 MB)
38 07:33:26.105294 progress 75 % (4 MB)
39 07:33:26.109237 progress 80 % (4 MB)
40 07:33:26.112778 progress 85 % (4 MB)
41 07:33:26.116798 progress 90 % (4 MB)
42 07:33:26.120623 progress 95 % (5 MB)
43 07:33:26.123895 progress 100 % (5 MB)
44 07:33:26.124584 5 MB downloaded in 0.11 s (48.43 MB/s)
45 07:33:26.125140 end: 1.1.1 http-download (duration 00:00:00) [common]
47 07:33:26.126050 end: 1.1 download-retry (duration 00:00:00) [common]
48 07:33:26.126358 start: 1.2 download-retry (timeout 00:10:00) [common]
49 07:33:26.126640 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 07:33:26.127117 downloading http://storage.kernelci.org/next/master/next-20241104/arm64/defconfig/gcc-12/kernel/Image
51 07:33:26.127365 saving as /var/lib/lava/dispatcher/tmp/933217/tftp-deploy-czzkl2bm/kernel/Image
52 07:33:26.127582 total size: 46041600 (43 MB)
53 07:33:26.127797 No compression specified
54 07:33:26.165130 progress 0 % (0 MB)
55 07:33:26.193301 progress 5 % (2 MB)
56 07:33:26.220997 progress 10 % (4 MB)
57 07:33:26.248614 progress 15 % (6 MB)
58 07:33:26.277227 progress 20 % (8 MB)
59 07:33:26.305242 progress 25 % (11 MB)
60 07:33:26.333260 progress 30 % (13 MB)
61 07:33:26.361145 progress 35 % (15 MB)
62 07:33:26.391665 progress 40 % (17 MB)
63 07:33:26.419472 progress 45 % (19 MB)
64 07:33:26.447251 progress 50 % (21 MB)
65 07:33:26.475119 progress 55 % (24 MB)
66 07:33:26.503339 progress 60 % (26 MB)
67 07:33:26.531352 progress 65 % (28 MB)
68 07:33:26.559146 progress 70 % (30 MB)
69 07:33:26.586772 progress 75 % (32 MB)
70 07:33:26.614935 progress 80 % (35 MB)
71 07:33:26.643055 progress 85 % (37 MB)
72 07:33:26.670647 progress 90 % (39 MB)
73 07:33:26.698238 progress 95 % (41 MB)
74 07:33:26.725971 progress 100 % (43 MB)
75 07:33:26.726513 43 MB downloaded in 0.60 s (73.31 MB/s)
76 07:33:26.726994 end: 1.2.1 http-download (duration 00:00:01) [common]
78 07:33:26.727840 end: 1.2 download-retry (duration 00:00:01) [common]
79 07:33:26.728155 start: 1.3 download-retry (timeout 00:09:59) [common]
80 07:33:26.728429 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 07:33:26.728906 downloading http://storage.kernelci.org/next/master/next-20241104/arm64/defconfig/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
82 07:33:26.729154 saving as /var/lib/lava/dispatcher/tmp/933217/tftp-deploy-czzkl2bm/dtb/meson-g12b-a311d-libretech-cc.dtb
83 07:33:26.729361 total size: 54703 (0 MB)
84 07:33:26.729571 No compression specified
85 07:33:26.766583 progress 59 % (0 MB)
86 07:33:26.767448 progress 100 % (0 MB)
87 07:33:26.768019 0 MB downloaded in 0.04 s (1.35 MB/s)
88 07:33:26.768494 end: 1.3.1 http-download (duration 00:00:00) [common]
90 07:33:26.769308 end: 1.3 download-retry (duration 00:00:00) [common]
91 07:33:26.769571 start: 1.4 download-retry (timeout 00:09:59) [common]
92 07:33:26.769834 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 07:33:26.770383 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm/20240313.0/arm64/full.rootfs.tar.xz
94 07:33:26.770641 saving as /var/lib/lava/dispatcher/tmp/933217/tftp-deploy-czzkl2bm/nfsrootfs/full.rootfs.tar
95 07:33:26.770847 total size: 107552908 (102 MB)
96 07:33:26.771057 Using unxz to decompress xz
97 07:33:26.806506 progress 0 % (0 MB)
98 07:33:27.450403 progress 5 % (5 MB)
99 07:33:28.176650 progress 10 % (10 MB)
100 07:33:28.901162 progress 15 % (15 MB)
101 07:33:29.655712 progress 20 % (20 MB)
102 07:33:30.222023 progress 25 % (25 MB)
103 07:33:30.838074 progress 30 % (30 MB)
104 07:33:31.574168 progress 35 % (35 MB)
105 07:33:31.933704 progress 40 % (41 MB)
106 07:33:32.358139 progress 45 % (46 MB)
107 07:33:33.051473 progress 50 % (51 MB)
108 07:33:33.733431 progress 55 % (56 MB)
109 07:33:34.490822 progress 60 % (61 MB)
110 07:33:35.246340 progress 65 % (66 MB)
111 07:33:35.980618 progress 70 % (71 MB)
112 07:33:36.746110 progress 75 % (76 MB)
113 07:33:37.427327 progress 80 % (82 MB)
114 07:33:38.133412 progress 85 % (87 MB)
115 07:33:38.856128 progress 90 % (92 MB)
116 07:33:39.580948 progress 95 % (97 MB)
117 07:33:40.319239 progress 100 % (102 MB)
118 07:33:40.330991 102 MB downloaded in 13.56 s (7.56 MB/s)
119 07:33:40.331934 end: 1.4.1 http-download (duration 00:00:14) [common]
121 07:33:40.333742 end: 1.4 download-retry (duration 00:00:14) [common]
122 07:33:40.334306 start: 1.5 download-retry (timeout 00:09:46) [common]
123 07:33:40.334866 start: 1.5.1 http-download (timeout 00:09:46) [common]
124 07:33:40.335746 downloading http://storage.kernelci.org/next/master/next-20241104/arm64/defconfig/gcc-12/modules.tar.xz
125 07:33:40.336287 saving as /var/lib/lava/dispatcher/tmp/933217/tftp-deploy-czzkl2bm/modules/modules.tar
126 07:33:40.336738 total size: 11673844 (11 MB)
127 07:33:40.337198 Using unxz to decompress xz
128 07:33:40.379065 progress 0 % (0 MB)
129 07:33:40.445707 progress 5 % (0 MB)
130 07:33:40.520547 progress 10 % (1 MB)
131 07:33:40.616232 progress 15 % (1 MB)
132 07:33:40.712293 progress 20 % (2 MB)
133 07:33:40.792663 progress 25 % (2 MB)
134 07:33:40.864865 progress 30 % (3 MB)
135 07:33:40.945620 progress 35 % (3 MB)
136 07:33:41.022892 progress 40 % (4 MB)
137 07:33:41.099417 progress 45 % (5 MB)
138 07:33:41.184665 progress 50 % (5 MB)
139 07:33:41.262263 progress 55 % (6 MB)
140 07:33:41.349807 progress 60 % (6 MB)
141 07:33:41.429568 progress 65 % (7 MB)
142 07:33:41.509926 progress 70 % (7 MB)
143 07:33:41.593777 progress 75 % (8 MB)
144 07:33:41.676423 progress 80 % (8 MB)
145 07:33:41.752293 progress 85 % (9 MB)
146 07:33:41.834838 progress 90 % (10 MB)
147 07:33:41.913329 progress 95 % (10 MB)
148 07:33:41.990160 progress 100 % (11 MB)
149 07:33:42.001150 11 MB downloaded in 1.66 s (6.69 MB/s)
150 07:33:42.001733 end: 1.5.1 http-download (duration 00:00:02) [common]
152 07:33:42.002563 end: 1.5 download-retry (duration 00:00:02) [common]
153 07:33:42.002833 start: 1.6 prepare-tftp-overlay (timeout 00:09:44) [common]
154 07:33:42.003101 start: 1.6.1 extract-nfsrootfs (timeout 00:09:44) [common]
155 07:33:51.947053 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/933217/extract-nfsrootfs-_f5du50_
156 07:33:51.947661 end: 1.6.1 extract-nfsrootfs (duration 00:00:10) [common]
157 07:33:51.947955 start: 1.6.2 lava-overlay (timeout 00:09:34) [common]
158 07:33:51.948618 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/933217/lava-overlay-sgx8t2kw
159 07:33:51.949073 makedir: /var/lib/lava/dispatcher/tmp/933217/lava-overlay-sgx8t2kw/lava-933217/bin
160 07:33:51.949415 makedir: /var/lib/lava/dispatcher/tmp/933217/lava-overlay-sgx8t2kw/lava-933217/tests
161 07:33:51.949741 makedir: /var/lib/lava/dispatcher/tmp/933217/lava-overlay-sgx8t2kw/lava-933217/results
162 07:33:51.950087 Creating /var/lib/lava/dispatcher/tmp/933217/lava-overlay-sgx8t2kw/lava-933217/bin/lava-add-keys
163 07:33:51.950637 Creating /var/lib/lava/dispatcher/tmp/933217/lava-overlay-sgx8t2kw/lava-933217/bin/lava-add-sources
164 07:33:51.951167 Creating /var/lib/lava/dispatcher/tmp/933217/lava-overlay-sgx8t2kw/lava-933217/bin/lava-background-process-start
165 07:33:51.951684 Creating /var/lib/lava/dispatcher/tmp/933217/lava-overlay-sgx8t2kw/lava-933217/bin/lava-background-process-stop
166 07:33:51.952245 Creating /var/lib/lava/dispatcher/tmp/933217/lava-overlay-sgx8t2kw/lava-933217/bin/lava-common-functions
167 07:33:51.952801 Creating /var/lib/lava/dispatcher/tmp/933217/lava-overlay-sgx8t2kw/lava-933217/bin/lava-echo-ipv4
168 07:33:51.953310 Creating /var/lib/lava/dispatcher/tmp/933217/lava-overlay-sgx8t2kw/lava-933217/bin/lava-install-packages
169 07:33:51.953813 Creating /var/lib/lava/dispatcher/tmp/933217/lava-overlay-sgx8t2kw/lava-933217/bin/lava-installed-packages
170 07:33:51.954315 Creating /var/lib/lava/dispatcher/tmp/933217/lava-overlay-sgx8t2kw/lava-933217/bin/lava-os-build
171 07:33:51.954811 Creating /var/lib/lava/dispatcher/tmp/933217/lava-overlay-sgx8t2kw/lava-933217/bin/lava-probe-channel
172 07:33:51.955343 Creating /var/lib/lava/dispatcher/tmp/933217/lava-overlay-sgx8t2kw/lava-933217/bin/lava-probe-ip
173 07:33:51.955847 Creating /var/lib/lava/dispatcher/tmp/933217/lava-overlay-sgx8t2kw/lava-933217/bin/lava-target-ip
174 07:33:51.956387 Creating /var/lib/lava/dispatcher/tmp/933217/lava-overlay-sgx8t2kw/lava-933217/bin/lava-target-mac
175 07:33:51.956896 Creating /var/lib/lava/dispatcher/tmp/933217/lava-overlay-sgx8t2kw/lava-933217/bin/lava-target-storage
176 07:33:51.957405 Creating /var/lib/lava/dispatcher/tmp/933217/lava-overlay-sgx8t2kw/lava-933217/bin/lava-test-case
177 07:33:51.957913 Creating /var/lib/lava/dispatcher/tmp/933217/lava-overlay-sgx8t2kw/lava-933217/bin/lava-test-event
178 07:33:51.958410 Creating /var/lib/lava/dispatcher/tmp/933217/lava-overlay-sgx8t2kw/lava-933217/bin/lava-test-feedback
179 07:33:51.958908 Creating /var/lib/lava/dispatcher/tmp/933217/lava-overlay-sgx8t2kw/lava-933217/bin/lava-test-raise
180 07:33:51.959405 Creating /var/lib/lava/dispatcher/tmp/933217/lava-overlay-sgx8t2kw/lava-933217/bin/lava-test-reference
181 07:33:51.959941 Creating /var/lib/lava/dispatcher/tmp/933217/lava-overlay-sgx8t2kw/lava-933217/bin/lava-test-runner
182 07:33:51.960488 Creating /var/lib/lava/dispatcher/tmp/933217/lava-overlay-sgx8t2kw/lava-933217/bin/lava-test-set
183 07:33:51.961012 Creating /var/lib/lava/dispatcher/tmp/933217/lava-overlay-sgx8t2kw/lava-933217/bin/lava-test-shell
184 07:33:51.961524 Updating /var/lib/lava/dispatcher/tmp/933217/lava-overlay-sgx8t2kw/lava-933217/bin/lava-install-packages (oe)
185 07:33:51.962115 Updating /var/lib/lava/dispatcher/tmp/933217/lava-overlay-sgx8t2kw/lava-933217/bin/lava-installed-packages (oe)
186 07:33:51.962603 Creating /var/lib/lava/dispatcher/tmp/933217/lava-overlay-sgx8t2kw/lava-933217/environment
187 07:33:51.962991 LAVA metadata
188 07:33:51.963256 - LAVA_JOB_ID=933217
189 07:33:51.963478 - LAVA_DISPATCHER_IP=192.168.6.2
190 07:33:51.963855 start: 1.6.2.1 ssh-authorize (timeout 00:09:34) [common]
191 07:33:51.964876 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
192 07:33:51.965206 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:34) [common]
193 07:33:51.965420 skipped lava-vland-overlay
194 07:33:51.965665 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
195 07:33:51.965921 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:34) [common]
196 07:33:51.966143 skipped lava-multinode-overlay
197 07:33:51.966391 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
198 07:33:51.966646 start: 1.6.2.4 test-definition (timeout 00:09:34) [common]
199 07:33:51.966900 Loading test definitions
200 07:33:51.967187 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:34) [common]
201 07:33:51.967412 Using /lava-933217 at stage 0
202 07:33:51.968658 uuid=933217_1.6.2.4.1 testdef=None
203 07:33:51.968984 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
204 07:33:51.969252 start: 1.6.2.4.2 test-overlay (timeout 00:09:34) [common]
205 07:33:51.971168 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
207 07:33:51.971974 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:34) [common]
208 07:33:51.974369 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
210 07:33:51.975213 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:34) [common]
211 07:33:51.977479 runner path: /var/lib/lava/dispatcher/tmp/933217/lava-overlay-sgx8t2kw/lava-933217/0/tests/0_dmesg test_uuid 933217_1.6.2.4.1
212 07:33:51.978109 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
214 07:33:51.978884 Creating lava-test-runner.conf files
215 07:33:51.979089 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/933217/lava-overlay-sgx8t2kw/lava-933217/0 for stage 0
216 07:33:51.979449 - 0_dmesg
217 07:33:51.979807 end: 1.6.2.4 test-definition (duration 00:00:00) [common]
218 07:33:51.980117 start: 1.6.2.5 compress-overlay (timeout 00:09:34) [common]
219 07:33:52.001994 end: 1.6.2.5 compress-overlay (duration 00:00:00) [common]
220 07:33:52.002437 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:09:34) [common]
221 07:33:52.002709 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
222 07:33:52.002981 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
223 07:33:52.003247 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:34) [common]
224 07:33:52.691695 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:01) [common]
225 07:33:52.692202 start: 1.6.4 extract-modules (timeout 00:09:33) [common]
226 07:33:52.692459 extracting modules file /var/lib/lava/dispatcher/tmp/933217/tftp-deploy-czzkl2bm/modules/modules.tar to /var/lib/lava/dispatcher/tmp/933217/extract-nfsrootfs-_f5du50_
227 07:33:54.243354 extracting modules file /var/lib/lava/dispatcher/tmp/933217/tftp-deploy-czzkl2bm/modules/modules.tar to /var/lib/lava/dispatcher/tmp/933217/extract-overlay-ramdisk-c2_upefl/ramdisk
228 07:33:55.665508 end: 1.6.4 extract-modules (duration 00:00:03) [common]
229 07:33:55.666005 start: 1.6.5 apply-overlay-tftp (timeout 00:09:30) [common]
230 07:33:55.666286 [common] Applying overlay to NFS
231 07:33:55.666498 [common] Applying overlay /var/lib/lava/dispatcher/tmp/933217/compress-overlay-3o049jb6/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/933217/extract-nfsrootfs-_f5du50_
232 07:33:55.696311 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
233 07:33:55.696745 start: 1.6.6 prepare-kernel (timeout 00:09:30) [common]
234 07:33:55.697017 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:09:30) [common]
235 07:33:55.697250 Converting downloaded kernel to a uImage
236 07:33:55.697563 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/933217/tftp-deploy-czzkl2bm/kernel/Image /var/lib/lava/dispatcher/tmp/933217/tftp-deploy-czzkl2bm/kernel/uImage
237 07:33:56.171249 output: Image Name:
238 07:33:56.171656 output: Created: Mon Nov 4 07:33:55 2024
239 07:33:56.171869 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
240 07:33:56.172118 output: Data Size: 46041600 Bytes = 44962.50 KiB = 43.91 MiB
241 07:33:56.172326 output: Load Address: 01080000
242 07:33:56.172527 output: Entry Point: 01080000
243 07:33:56.172726 output:
244 07:33:56.173055 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
245 07:33:56.173330 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
246 07:33:56.173612 start: 1.6.7 configure-preseed-file (timeout 00:09:30) [common]
247 07:33:56.173871 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
248 07:33:56.174130 start: 1.6.8 compress-ramdisk (timeout 00:09:30) [common]
249 07:33:56.174393 Building ramdisk /var/lib/lava/dispatcher/tmp/933217/extract-overlay-ramdisk-c2_upefl/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/933217/extract-overlay-ramdisk-c2_upefl/ramdisk
250 07:33:58.359192 >> 168014 blocks
251 07:34:06.208819 Adding RAMdisk u-boot header.
252 07:34:06.209521 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/933217/extract-overlay-ramdisk-c2_upefl/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/933217/extract-overlay-ramdisk-c2_upefl/ramdisk.cpio.gz.uboot
253 07:34:06.518382 output: Image Name:
254 07:34:06.518781 output: Created: Mon Nov 4 07:34:06 2024
255 07:34:06.518995 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
256 07:34:06.519202 output: Data Size: 23544853 Bytes = 22993.02 KiB = 22.45 MiB
257 07:34:06.519403 output: Load Address: 00000000
258 07:34:06.519601 output: Entry Point: 00000000
259 07:34:06.519797 output:
260 07:34:06.520581 rename /var/lib/lava/dispatcher/tmp/933217/extract-overlay-ramdisk-c2_upefl/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/933217/tftp-deploy-czzkl2bm/ramdisk/ramdisk.cpio.gz.uboot
261 07:34:06.521287 end: 1.6.8 compress-ramdisk (duration 00:00:10) [common]
262 07:34:06.521831 end: 1.6 prepare-tftp-overlay (duration 00:00:25) [common]
263 07:34:06.522390 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:19) [common]
264 07:34:06.522844 No LXC device requested
265 07:34:06.523339 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
266 07:34:06.523845 start: 1.8 deploy-device-env (timeout 00:09:19) [common]
267 07:34:06.524380 end: 1.8 deploy-device-env (duration 00:00:00) [common]
268 07:34:06.524791 Checking files for TFTP limit of 4294967296 bytes.
269 07:34:06.527419 end: 1 tftp-deploy (duration 00:00:41) [common]
270 07:34:06.528007 start: 2 uboot-action (timeout 00:05:00) [common]
271 07:34:06.528537 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
272 07:34:06.529034 end: 2.1 uboot-from-media (duration 00:00:00) [common]
273 07:34:06.529528 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
274 07:34:06.530047 Using kernel file from prepare-kernel: 933217/tftp-deploy-czzkl2bm/kernel/uImage
275 07:34:06.530667 substitutions:
276 07:34:06.531067 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
277 07:34:06.531467 - {DTB_ADDR}: 0x01070000
278 07:34:06.531864 - {DTB}: 933217/tftp-deploy-czzkl2bm/dtb/meson-g12b-a311d-libretech-cc.dtb
279 07:34:06.532290 - {INITRD}: 933217/tftp-deploy-czzkl2bm/ramdisk/ramdisk.cpio.gz.uboot
280 07:34:06.532687 - {KERNEL_ADDR}: 0x01080000
281 07:34:06.533077 - {KERNEL}: 933217/tftp-deploy-czzkl2bm/kernel/uImage
282 07:34:06.533465 - {LAVA_MAC}: None
283 07:34:06.533892 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/933217/extract-nfsrootfs-_f5du50_
284 07:34:06.534285 - {NFS_SERVER_IP}: 192.168.6.2
285 07:34:06.534672 - {PRESEED_CONFIG}: None
286 07:34:06.535056 - {PRESEED_LOCAL}: None
287 07:34:06.535442 - {RAMDISK_ADDR}: 0x08000000
288 07:34:06.535824 - {RAMDISK}: 933217/tftp-deploy-czzkl2bm/ramdisk/ramdisk.cpio.gz.uboot
289 07:34:06.536238 - {ROOT_PART}: None
290 07:34:06.536628 - {ROOT}: None
291 07:34:06.537018 - {SERVER_IP}: 192.168.6.2
292 07:34:06.537404 - {TEE_ADDR}: 0x83000000
293 07:34:06.537791 - {TEE}: None
294 07:34:06.538174 Parsed boot commands:
295 07:34:06.538551 - setenv autoload no
296 07:34:06.538935 - setenv initrd_high 0xffffffff
297 07:34:06.539320 - setenv fdt_high 0xffffffff
298 07:34:06.539706 - dhcp
299 07:34:06.540118 - setenv serverip 192.168.6.2
300 07:34:06.540506 - tftpboot 0x01080000 933217/tftp-deploy-czzkl2bm/kernel/uImage
301 07:34:06.540890 - tftpboot 0x08000000 933217/tftp-deploy-czzkl2bm/ramdisk/ramdisk.cpio.gz.uboot
302 07:34:06.541277 - tftpboot 0x01070000 933217/tftp-deploy-czzkl2bm/dtb/meson-g12b-a311d-libretech-cc.dtb
303 07:34:06.541664 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/933217/extract-nfsrootfs-_f5du50_,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
304 07:34:06.542060 - bootm 0x01080000 0x08000000 0x01070000
305 07:34:06.542547 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
307 07:34:06.544032 start: 2.3 connect-device (timeout 00:05:00) [common]
308 07:34:06.544453 [common] connect-device Connecting to device using 'telnet conserv1 3007'
309 07:34:06.560247 Setting prompt string to ['lava-test: # ']
310 07:34:06.561722 end: 2.3 connect-device (duration 00:00:00) [common]
311 07:34:06.562308 start: 2.4 uboot-commands (timeout 00:05:00) [common]
312 07:34:06.562867 start: 2.4.1 reset-device (timeout 00:05:00) [common]
313 07:34:06.563386 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
314 07:34:06.564805 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
315 07:34:06.602042 >> OK - accepted request
316 07:34:06.604397 Returned 0 in 0 seconds
317 07:34:06.705439 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
319 07:34:06.706974 end: 2.4.1 reset-device (duration 00:00:00) [common]
320 07:34:06.707530 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
321 07:34:06.708080 Setting prompt string to ['Hit any key to stop autoboot']
322 07:34:06.708558 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
323 07:34:06.710094 Trying 192.168.56.21...
324 07:34:06.710558 Connected to conserv1.
325 07:34:06.710973 Escape character is '^]'.
326 07:34:06.711387
327 07:34:06.711801 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
328 07:34:06.712260
329 07:34:18.438982 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
330 07:34:18.439608 bl2_stage_init 0x01
331 07:34:18.440055 bl2_stage_init 0x81
332 07:34:18.444622 hw id: 0x0000 - pwm id 0x01
333 07:34:18.445091 bl2_stage_init 0xc1
334 07:34:18.445485 bl2_stage_init 0x02
335 07:34:18.445875
336 07:34:18.450263 L0:00000000
337 07:34:18.450719 L1:20000703
338 07:34:18.451117 L2:00008067
339 07:34:18.451509 L3:14000000
340 07:34:18.455747 B2:00402000
341 07:34:18.456234 B1:e0f83180
342 07:34:18.456642
343 07:34:18.457029 TE: 58167
344 07:34:18.457420
345 07:34:18.461403 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
346 07:34:18.461850
347 07:34:18.462244 Board ID = 1
348 07:34:18.466945 Set A53 clk to 24M
349 07:34:18.467383 Set A73 clk to 24M
350 07:34:18.467772 Set clk81 to 24M
351 07:34:18.472576 A53 clk: 1200 MHz
352 07:34:18.473016 A73 clk: 1200 MHz
353 07:34:18.473401 CLK81: 166.6M
354 07:34:18.473780 smccc: 00012abe
355 07:34:18.478249 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
356 07:34:18.483801 board id: 1
357 07:34:18.489705 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
358 07:34:18.500196 fw parse done
359 07:34:18.506179 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
360 07:34:18.548742 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
361 07:34:18.559603 PIEI prepare done
362 07:34:18.560200 fastboot data load
363 07:34:18.560730 fastboot data verify
364 07:34:18.565318 verify result: 266
365 07:34:18.570902 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
366 07:34:18.571465 LPDDR4 probe
367 07:34:18.571970 ddr clk to 1584MHz
368 07:34:18.578858 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
369 07:34:18.616195
370 07:34:18.616771 dmc_version 0001
371 07:34:18.622820 Check phy result
372 07:34:18.628684 INFO : End of CA training
373 07:34:18.629246 INFO : End of initialization
374 07:34:18.634294 INFO : Training has run successfully!
375 07:34:18.634856 Check phy result
376 07:34:18.639895 INFO : End of initialization
377 07:34:18.640488 INFO : End of read enable training
378 07:34:18.645481 INFO : End of fine write leveling
379 07:34:18.651183 INFO : End of Write leveling coarse delay
380 07:34:18.651746 INFO : Training has run successfully!
381 07:34:18.652317 Check phy result
382 07:34:18.656691 INFO : End of initialization
383 07:34:18.657291 INFO : End of read dq deskew training
384 07:34:18.662291 INFO : End of MPR read delay center optimization
385 07:34:18.667881 INFO : End of write delay center optimization
386 07:34:18.673503 INFO : End of read delay center optimization
387 07:34:18.674077 INFO : End of max read latency training
388 07:34:18.679183 INFO : Training has run successfully!
389 07:34:18.679744 1D training succeed
390 07:34:18.688283 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
391 07:34:18.735852 Check phy result
392 07:34:18.736455 INFO : End of initialization
393 07:34:18.758439 INFO : End of 2D read delay Voltage center optimization
394 07:34:18.778720 INFO : End of 2D read delay Voltage center optimization
395 07:34:18.830759 INFO : End of 2D write delay Voltage center optimization
396 07:34:18.880250 INFO : End of 2D write delay Voltage center optimization
397 07:34:18.885719 INFO : Training has run successfully!
398 07:34:18.886285
399 07:34:18.886824 channel==0
400 07:34:18.891320 RxClkDly_Margin_A0==88 ps 9
401 07:34:18.891887 TxDqDly_Margin_A0==98 ps 10
402 07:34:18.896906 RxClkDly_Margin_A1==88 ps 9
403 07:34:18.897464 TxDqDly_Margin_A1==98 ps 10
404 07:34:18.898004 TrainedVREFDQ_A0==74
405 07:34:18.902522 TrainedVREFDQ_A1==74
406 07:34:18.903116 VrefDac_Margin_A0==24
407 07:34:18.903653 DeviceVref_Margin_A0==40
408 07:34:18.908221 VrefDac_Margin_A1==25
409 07:34:18.908778 DeviceVref_Margin_A1==40
410 07:34:18.909298
411 07:34:18.909821
412 07:34:18.913705 channel==1
413 07:34:18.914266 RxClkDly_Margin_A0==98 ps 10
414 07:34:18.914798 TxDqDly_Margin_A0==98 ps 10
415 07:34:18.919317 RxClkDly_Margin_A1==98 ps 10
416 07:34:18.919876 TxDqDly_Margin_A1==88 ps 9
417 07:34:18.924931 TrainedVREFDQ_A0==77
418 07:34:18.925504 TrainedVREFDQ_A1==77
419 07:34:18.926028 VrefDac_Margin_A0==22
420 07:34:18.930527 DeviceVref_Margin_A0==37
421 07:34:18.931085 VrefDac_Margin_A1==22
422 07:34:18.936224 DeviceVref_Margin_A1==37
423 07:34:18.936792
424 07:34:18.937326 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
425 07:34:18.941714
426 07:34:18.969720 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000018 00000017 00000016 00000017 00000016 00000017 00000019 00000017 00000019 00000018 0000001a 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
427 07:34:18.970371 2D training succeed
428 07:34:18.975286 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
429 07:34:18.980892 auto size-- 65535DDR cs0 size: 2048MB
430 07:34:18.981450 DDR cs1 size: 2048MB
431 07:34:18.986499 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
432 07:34:18.987057 cs0 DataBus test pass
433 07:34:18.992229 cs1 DataBus test pass
434 07:34:18.992791 cs0 AddrBus test pass
435 07:34:18.993321 cs1 AddrBus test pass
436 07:34:18.993830
437 07:34:18.997731 100bdlr_step_size ps== 420
438 07:34:18.998311 result report
439 07:34:19.003319 boot times 0Enable ddr reg access
440 07:34:19.008785 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
441 07:34:19.022277 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
442 07:34:19.595744 0.0;M3 CHK:0;cm4_sp_mode 0
443 07:34:19.596453 MVN_1=0x00000000
444 07:34:19.601259 MVN_2=0x00000000
445 07:34:19.607033 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
446 07:34:19.607606 OPS=0x10
447 07:34:19.608182 ring efuse init
448 07:34:19.608708 chipver efuse init
449 07:34:19.612625 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
450 07:34:19.618254 [0.018961 Inits done]
451 07:34:19.618825 secure task start!
452 07:34:19.619359 high task start!
453 07:34:19.622780 low task start!
454 07:34:19.623345 run into bl31
455 07:34:19.629445 NOTICE: BL31: v1.3(release):4fc40b1
456 07:34:19.637322 NOTICE: BL31: Built : 15:58:17, May 22 2019
457 07:34:19.637906 NOTICE: BL31: G12A normal boot!
458 07:34:19.662585 NOTICE: BL31: BL33 decompress pass
459 07:34:19.668323 ERROR: Error initializing runtime service opteed_fast
460 07:34:20.901104
461 07:34:20.901792
462 07:34:20.908706 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
463 07:34:20.909311
464 07:34:20.909847 Model: Libre Computer AML-A311D-CC Alta
465 07:34:21.117944 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
466 07:34:21.141416 DRAM: 2 GiB (effective 3.8 GiB)
467 07:34:21.284387 Core: 408 devices, 31 uclasses, devicetree: separate
468 07:34:21.290231 WDT: Not starting watchdog@f0d0
469 07:34:21.322513 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
470 07:34:21.334917 Loading Environment from FAT... Card did not respond to voltage select! : -110
471 07:34:21.339908 ** Bad device specification mmc 0 **
472 07:34:21.350247 Card did not respond to voltage select! : -110
473 07:34:21.357903 ** Bad device specification mmc 0 **
474 07:34:21.358473 Couldn't find partition mmc 0
475 07:34:21.366279 Card did not respond to voltage select! : -110
476 07:34:21.371763 ** Bad device specification mmc 0 **
477 07:34:21.372385 Couldn't find partition mmc 0
478 07:34:21.376834 Error: could not access storage.
479 07:34:22.639217 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
480 07:34:22.639962 bl2_stage_init 0x01
481 07:34:22.640575 bl2_stage_init 0x81
482 07:34:22.644846 hw id: 0x0000 - pwm id 0x01
483 07:34:22.645439 bl2_stage_init 0xc1
484 07:34:22.645982 bl2_stage_init 0x02
485 07:34:22.646499
486 07:34:22.650460 L0:00000000
487 07:34:22.651047 L1:20000703
488 07:34:22.651588 L2:00008067
489 07:34:22.652151 L3:14000000
490 07:34:22.656029 B2:00402000
491 07:34:22.656627 B1:e0f83180
492 07:34:22.657165
493 07:34:22.657693 TE: 58124
494 07:34:22.658207
495 07:34:22.661685 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
496 07:34:22.662270
497 07:34:22.662794 Board ID = 1
498 07:34:22.667235 Set A53 clk to 24M
499 07:34:22.667846 Set A73 clk to 24M
500 07:34:22.668413 Set clk81 to 24M
501 07:34:22.672823 A53 clk: 1200 MHz
502 07:34:22.673392 A73 clk: 1200 MHz
503 07:34:22.673928 CLK81: 166.6M
504 07:34:22.674446 smccc: 00012a92
505 07:34:22.678409 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
506 07:34:22.684003 board id: 1
507 07:34:22.689877 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
508 07:34:22.700549 fw parse done
509 07:34:22.706529 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
510 07:34:22.749119 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
511 07:34:22.760079 PIEI prepare done
512 07:34:22.760666 fastboot data load
513 07:34:22.761213 fastboot data verify
514 07:34:22.765768 verify result: 266
515 07:34:22.771312 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
516 07:34:22.771883 LPDDR4 probe
517 07:34:22.772472 ddr clk to 1584MHz
518 07:34:22.778306 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
519 07:34:22.816530
520 07:34:22.817128 dmc_version 0001
521 07:34:22.823212 Check phy result
522 07:34:22.829072 INFO : End of CA training
523 07:34:22.829648 INFO : End of initialization
524 07:34:22.834757 INFO : Training has run successfully!
525 07:34:22.835326 Check phy result
526 07:34:22.840284 INFO : End of initialization
527 07:34:22.840854 INFO : End of read enable training
528 07:34:22.845881 INFO : End of fine write leveling
529 07:34:22.851487 INFO : End of Write leveling coarse delay
530 07:34:22.852074 INFO : Training has run successfully!
531 07:34:22.852609 Check phy result
532 07:34:22.857063 INFO : End of initialization
533 07:34:22.857645 INFO : End of read dq deskew training
534 07:34:22.862787 INFO : End of MPR read delay center optimization
535 07:34:22.868288 INFO : End of write delay center optimization
536 07:34:22.873873 INFO : End of read delay center optimization
537 07:34:22.874451 INFO : End of max read latency training
538 07:34:22.879486 INFO : Training has run successfully!
539 07:34:22.880087 1D training succeed
540 07:34:22.888671 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
541 07:34:22.936255 Check phy result
542 07:34:22.936852 INFO : End of initialization
543 07:34:22.957878 INFO : End of 2D read delay Voltage center optimization
544 07:34:22.978232 INFO : End of 2D read delay Voltage center optimization
545 07:34:23.030239 INFO : End of 2D write delay Voltage center optimization
546 07:34:23.079666 INFO : End of 2D write delay Voltage center optimization
547 07:34:23.085240 INFO : Training has run successfully!
548 07:34:23.085804
549 07:34:23.086342 channel==0
550 07:34:23.090842 RxClkDly_Margin_A0==88 ps 9
551 07:34:23.091401 TxDqDly_Margin_A0==98 ps 10
552 07:34:23.096442 RxClkDly_Margin_A1==88 ps 9
553 07:34:23.097008 TxDqDly_Margin_A1==98 ps 10
554 07:34:23.097543 TrainedVREFDQ_A0==74
555 07:34:23.102033 TrainedVREFDQ_A1==74
556 07:34:23.102608 VrefDac_Margin_A0==25
557 07:34:23.103141 DeviceVref_Margin_A0==40
558 07:34:23.107670 VrefDac_Margin_A1==26
559 07:34:23.108273 DeviceVref_Margin_A1==40
560 07:34:23.108814
561 07:34:23.109337
562 07:34:23.113239 channel==1
563 07:34:23.113804 RxClkDly_Margin_A0==98 ps 10
564 07:34:23.114338 TxDqDly_Margin_A0==98 ps 10
565 07:34:23.118801 RxClkDly_Margin_A1==98 ps 10
566 07:34:23.119358 TxDqDly_Margin_A1==88 ps 9
567 07:34:23.124417 TrainedVREFDQ_A0==77
568 07:34:23.125009 TrainedVREFDQ_A1==77
569 07:34:23.125545 VrefDac_Margin_A0==22
570 07:34:23.130041 DeviceVref_Margin_A0==37
571 07:34:23.130619 VrefDac_Margin_A1==22
572 07:34:23.135668 DeviceVref_Margin_A1==37
573 07:34:23.136261
574 07:34:23.136787 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
575 07:34:23.141216
576 07:34:23.169199 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000017 00000019 00000017 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000017 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
577 07:34:23.169806 2D training succeed
578 07:34:23.174819 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
579 07:34:23.180440 auto size-- 65535DDR cs0 size: 2048MB
580 07:34:23.181015 DDR cs1 size: 2048MB
581 07:34:23.186021 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
582 07:34:23.186580 cs0 DataBus test pass
583 07:34:23.191673 cs1 DataBus test pass
584 07:34:23.192277 cs0 AddrBus test pass
585 07:34:23.192811 cs1 AddrBus test pass
586 07:34:23.193321
587 07:34:23.197238 100bdlr_step_size ps== 420
588 07:34:23.197825 result report
589 07:34:23.202846 boot times 0Enable ddr reg access
590 07:34:23.208250 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
591 07:34:23.221732 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
592 07:34:23.794815 0.0;M3 CHK:0;cm4_sp_mode 0
593 07:34:23.795512 MVN_1=0x00000000
594 07:34:23.800536 MVN_2=0x00000000
595 07:34:23.806235 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
596 07:34:23.806719 OPS=0x10
597 07:34:23.807162 ring efuse init
598 07:34:23.807596 chipver efuse init
599 07:34:23.811647 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
600 07:34:23.817258 [0.018961 Inits done]
601 07:34:23.817742 secure task start!
602 07:34:23.818179 high task start!
603 07:34:23.822003 low task start!
604 07:34:23.822465 run into bl31
605 07:34:23.828487 NOTICE: BL31: v1.3(release):4fc40b1
606 07:34:23.836270 NOTICE: BL31: Built : 15:58:17, May 22 2019
607 07:34:23.836744 NOTICE: BL31: G12A normal boot!
608 07:34:23.862119 NOTICE: BL31: BL33 decompress pass
609 07:34:23.867856 ERROR: Error initializing runtime service opteed_fast
610 07:34:25.100977
611 07:34:25.101639
612 07:34:25.109284 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
613 07:34:25.109802
614 07:34:25.110275 Model: Libre Computer AML-A311D-CC Alta
615 07:34:25.317766 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
616 07:34:25.341081 DRAM: 2 GiB (effective 3.8 GiB)
617 07:34:25.484096 Core: 408 devices, 31 uclasses, devicetree: separate
618 07:34:25.489970 WDT: Not starting watchdog@f0d0
619 07:34:25.522293 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
620 07:34:25.534550 Loading Environment from FAT... Card did not respond to voltage select! : -110
621 07:34:25.539676 ** Bad device specification mmc 0 **
622 07:34:25.549926 Card did not respond to voltage select! : -110
623 07:34:25.557653 ** Bad device specification mmc 0 **
624 07:34:25.558209 Couldn't find partition mmc 0
625 07:34:25.565878 Card did not respond to voltage select! : -110
626 07:34:25.571406 ** Bad device specification mmc 0 **
627 07:34:25.571965 Couldn't find partition mmc 0
628 07:34:25.576612 Error: could not access storage.
629 07:34:25.919140 Net: eth0: ethernet@ff3f0000
630 07:34:25.919827 starting USB...
631 07:34:26.170884 Bus usb@ff500000: Register 3000140 NbrPorts 3
632 07:34:26.171562 Starting the controller
633 07:34:26.177692 USB XHCI 1.10
634 07:34:27.888277 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
635 07:34:27.888967 bl2_stage_init 0x01
636 07:34:27.889444 bl2_stage_init 0x81
637 07:34:27.893765 hw id: 0x0000 - pwm id 0x01
638 07:34:27.894261 bl2_stage_init 0xc1
639 07:34:27.894715 bl2_stage_init 0x02
640 07:34:27.895164
641 07:34:27.899459 L0:00000000
642 07:34:27.899942 L1:20000703
643 07:34:27.900447 L2:00008067
644 07:34:27.900890 L3:14000000
645 07:34:27.902286 B2:00402000
646 07:34:27.902759 B1:e0f83180
647 07:34:27.903198
648 07:34:27.903634 TE: 58167
649 07:34:27.904119
650 07:34:27.913533 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
651 07:34:27.914036
652 07:34:27.914485 Board ID = 1
653 07:34:27.914920 Set A53 clk to 24M
654 07:34:27.915353 Set A73 clk to 24M
655 07:34:27.919066 Set clk81 to 24M
656 07:34:27.919550 A53 clk: 1200 MHz
657 07:34:27.920028 A73 clk: 1200 MHz
658 07:34:27.924691 CLK81: 166.6M
659 07:34:27.925169 smccc: 00012abe
660 07:34:27.930249 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
661 07:34:27.930733 board id: 1
662 07:34:27.939003 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
663 07:34:27.949411 fw parse done
664 07:34:27.955365 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
665 07:34:27.997990 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
666 07:34:28.008855 PIEI prepare done
667 07:34:28.009348 fastboot data load
668 07:34:28.009799 fastboot data verify
669 07:34:28.014608 verify result: 266
670 07:34:28.020130 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
671 07:34:28.020642 LPDDR4 probe
672 07:34:28.021097 ddr clk to 1584MHz
673 07:34:28.028117 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
674 07:34:28.065403
675 07:34:28.065916 dmc_version 0001
676 07:34:28.072135 Check phy result
677 07:34:28.077974 INFO : End of CA training
678 07:34:28.078531 INFO : End of initialization
679 07:34:28.083529 INFO : Training has run successfully!
680 07:34:28.084072 Check phy result
681 07:34:28.089193 INFO : End of initialization
682 07:34:28.089677 INFO : End of read enable training
683 07:34:28.092572 INFO : End of fine write leveling
684 07:34:28.098146 INFO : End of Write leveling coarse delay
685 07:34:28.103782 INFO : Training has run successfully!
686 07:34:28.104301 Check phy result
687 07:34:28.104750 INFO : End of initialization
688 07:34:28.109382 INFO : End of read dq deskew training
689 07:34:28.114955 INFO : End of MPR read delay center optimization
690 07:34:28.115429 INFO : End of write delay center optimization
691 07:34:28.120539 INFO : End of read delay center optimization
692 07:34:28.126191 INFO : End of max read latency training
693 07:34:28.126666 INFO : Training has run successfully!
694 07:34:28.131811 1D training succeed
695 07:34:28.137626 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
696 07:34:28.185108 Check phy result
697 07:34:28.185660 INFO : End of initialization
698 07:34:28.205928 INFO : End of 2D read delay Voltage center optimization
699 07:34:28.227107 INFO : End of 2D read delay Voltage center optimization
700 07:34:28.279219 INFO : End of 2D write delay Voltage center optimization
701 07:34:28.328656 INFO : End of 2D write delay Voltage center optimization
702 07:34:28.334150 INFO : Training has run successfully!
703 07:34:28.334633
704 07:34:28.335084 channel==0
705 07:34:28.339826 RxClkDly_Margin_A0==88 ps 9
706 07:34:28.340332 TxDqDly_Margin_A0==98 ps 10
707 07:34:28.345339 RxClkDly_Margin_A1==88 ps 9
708 07:34:28.345816 TxDqDly_Margin_A1==98 ps 10
709 07:34:28.346264 TrainedVREFDQ_A0==74
710 07:34:28.350930 TrainedVREFDQ_A1==74
711 07:34:28.351407 VrefDac_Margin_A0==25
712 07:34:28.351851 DeviceVref_Margin_A0==40
713 07:34:28.356649 VrefDac_Margin_A1==25
714 07:34:28.357120 DeviceVref_Margin_A1==40
715 07:34:28.357557
716 07:34:28.357999
717 07:34:28.362132 channel==1
718 07:34:28.362609 RxClkDly_Margin_A0==98 ps 10
719 07:34:28.363058 TxDqDly_Margin_A0==98 ps 10
720 07:34:28.367735 RxClkDly_Margin_A1==88 ps 9
721 07:34:28.368239 TxDqDly_Margin_A1==88 ps 9
722 07:34:28.373303 TrainedVREFDQ_A0==77
723 07:34:28.373777 TrainedVREFDQ_A1==77
724 07:34:28.374224 VrefDac_Margin_A0==22
725 07:34:28.378961 DeviceVref_Margin_A0==37
726 07:34:28.379464 VrefDac_Margin_A1==24
727 07:34:28.384552 DeviceVref_Margin_A1==37
728 07:34:28.385031
729 07:34:28.385477 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
730 07:34:28.385919
731 07:34:28.418064 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000018 00000015 00000017 00000018 00000017 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
732 07:34:28.418602 2D training succeed
733 07:34:28.423638 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
734 07:34:28.429278 auto size-- 65535DDR cs0 size: 2048MB
735 07:34:28.429757 DDR cs1 size: 2048MB
736 07:34:28.434881 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
737 07:34:28.435356 cs0 DataBus test pass
738 07:34:28.440554 cs1 DataBus test pass
739 07:34:28.441027 cs0 AddrBus test pass
740 07:34:28.441472 cs1 AddrBus test pass
741 07:34:28.441911
742 07:34:28.446139 100bdlr_step_size ps== 420
743 07:34:28.446633 result report
744 07:34:28.451661 boot times 0Enable ddr reg access
745 07:34:28.457022 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
746 07:34:28.470508 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
747 07:34:29.043434 0.0;M3 CHK:0;cm4_sp_mode 0
748 07:34:29.044131 MVN_1=0x00000000
749 07:34:29.048916 MVN_2=0x00000000
750 07:34:29.054724 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
751 07:34:29.055262 OPS=0x10
752 07:34:29.055696 ring efuse init
753 07:34:29.056161 chipver efuse init
754 07:34:29.060287 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
755 07:34:29.065877 [0.018961 Inits done]
756 07:34:29.066340 secure task start!
757 07:34:29.066763 high task start!
758 07:34:29.070455 low task start!
759 07:34:29.070908 run into bl31
760 07:34:29.077110 NOTICE: BL31: v1.3(release):4fc40b1
761 07:34:29.084941 NOTICE: BL31: Built : 15:58:17, May 22 2019
762 07:34:29.085437 NOTICE: BL31: G12A normal boot!
763 07:34:29.110298 NOTICE: BL31: BL33 decompress pass
764 07:34:29.115965 ERROR: Error initializing runtime service opteed_fast
765 07:34:30.348938
766 07:34:30.349590
767 07:34:30.357274 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
768 07:34:30.357811
769 07:34:30.358287 Model: Libre Computer AML-A311D-CC Alta
770 07:34:30.565776 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
771 07:34:30.589183 DRAM: 2 GiB (effective 3.8 GiB)
772 07:34:30.732185 Core: 408 devices, 31 uclasses, devicetree: separate
773 07:34:30.738144 WDT: Not starting watchdog@f0d0
774 07:34:30.770281 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
775 07:34:30.782773 Loading Environment from FAT... Card did not respond to voltage select! : -110
776 07:34:30.787770 ** Bad device specification mmc 0 **
777 07:34:30.797993 Card did not respond to voltage select! : -110
778 07:34:30.805663 ** Bad device specification mmc 0 **
779 07:34:30.806170 Couldn't find partition mmc 0
780 07:34:30.813985 Card did not respond to voltage select! : -110
781 07:34:30.819501 ** Bad device specification mmc 0 **
782 07:34:30.820037 Couldn't find partition mmc 0
783 07:34:30.824570 Error: could not access storage.
784 07:34:31.167015 Net: eth0: ethernet@ff3f0000
785 07:34:31.167662 starting USB...
786 07:34:31.418871 Bus usb@ff500000: Register 3000140 NbrPorts 3
787 07:34:31.419528 Starting the controller
788 07:34:31.425840 USB XHCI 1.10
789 07:34:33.588236 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
790 07:34:33.588883 bl2_stage_init 0x01
791 07:34:33.589352 bl2_stage_init 0x81
792 07:34:33.593683 hw id: 0x0000 - pwm id 0x01
793 07:34:33.594188 bl2_stage_init 0xc1
794 07:34:33.594644 bl2_stage_init 0x02
795 07:34:33.595089
796 07:34:33.599326 L0:00000000
797 07:34:33.599821 L1:20000703
798 07:34:33.600366 L2:00008067
799 07:34:33.600817 L3:14000000
800 07:34:33.604941 B2:00402000
801 07:34:33.605436 B1:e0f83180
802 07:34:33.605885
803 07:34:33.606332 TE: 58124
804 07:34:33.606772
805 07:34:33.610542 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
806 07:34:33.611036
807 07:34:33.611485 Board ID = 1
808 07:34:33.616174 Set A53 clk to 24M
809 07:34:33.616670 Set A73 clk to 24M
810 07:34:33.617114 Set clk81 to 24M
811 07:34:33.621677 A53 clk: 1200 MHz
812 07:34:33.622173 A73 clk: 1200 MHz
813 07:34:33.622616 CLK81: 166.6M
814 07:34:33.623054 smccc: 00012a92
815 07:34:33.627288 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
816 07:34:33.632907 board id: 1
817 07:34:33.638811 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
818 07:34:33.649449 fw parse done
819 07:34:33.655406 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
820 07:34:33.698041 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
821 07:34:33.708867 PIEI prepare done
822 07:34:33.709373 fastboot data load
823 07:34:33.709829 fastboot data verify
824 07:34:33.714768 verify result: 266
825 07:34:33.720278 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
826 07:34:33.720814 LPDDR4 probe
827 07:34:33.721279 ddr clk to 1584MHz
828 07:34:33.728156 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
829 07:34:33.765480
830 07:34:33.766017 dmc_version 0001
831 07:34:33.772115 Check phy result
832 07:34:33.777991 INFO : End of CA training
833 07:34:33.778491 INFO : End of initialization
834 07:34:33.783580 INFO : Training has run successfully!
835 07:34:33.784117 Check phy result
836 07:34:33.789249 INFO : End of initialization
837 07:34:33.789747 INFO : End of read enable training
838 07:34:33.794770 INFO : End of fine write leveling
839 07:34:33.800399 INFO : End of Write leveling coarse delay
840 07:34:33.800906 INFO : Training has run successfully!
841 07:34:33.801355 Check phy result
842 07:34:33.806000 INFO : End of initialization
843 07:34:33.806497 INFO : End of read dq deskew training
844 07:34:33.811641 INFO : End of MPR read delay center optimization
845 07:34:33.817258 INFO : End of write delay center optimization
846 07:34:33.822807 INFO : End of read delay center optimization
847 07:34:33.823306 INFO : End of max read latency training
848 07:34:33.828400 INFO : Training has run successfully!
849 07:34:33.828898 1D training succeed
850 07:34:33.837586 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
851 07:34:33.885215 Check phy result
852 07:34:33.885761 INFO : End of initialization
853 07:34:33.906972 INFO : End of 2D read delay Voltage center optimization
854 07:34:33.927218 INFO : End of 2D read delay Voltage center optimization
855 07:34:33.979197 INFO : End of 2D write delay Voltage center optimization
856 07:34:34.028674 INFO : End of 2D write delay Voltage center optimization
857 07:34:34.034195 INFO : Training has run successfully!
858 07:34:34.034695
859 07:34:34.035151 channel==0
860 07:34:34.039782 RxClkDly_Margin_A0==88 ps 9
861 07:34:34.040325 TxDqDly_Margin_A0==98 ps 10
862 07:34:34.043095 RxClkDly_Margin_A1==88 ps 9
863 07:34:34.043587 TxDqDly_Margin_A1==98 ps 10
864 07:34:34.048675 TrainedVREFDQ_A0==74
865 07:34:34.049180 TrainedVREFDQ_A1==74
866 07:34:34.054338 VrefDac_Margin_A0==25
867 07:34:34.054867 DeviceVref_Margin_A0==40
868 07:34:34.055317 VrefDac_Margin_A1==25
869 07:34:34.059773 DeviceVref_Margin_A1==40
870 07:34:34.060316
871 07:34:34.060750
872 07:34:34.061176 channel==1
873 07:34:34.061595 RxClkDly_Margin_A0==98 ps 10
874 07:34:34.065549 TxDqDly_Margin_A0==88 ps 9
875 07:34:34.066046 RxClkDly_Margin_A1==88 ps 9
876 07:34:34.070927 TxDqDly_Margin_A1==98 ps 10
877 07:34:34.071417 TrainedVREFDQ_A0==75
878 07:34:34.071849 TrainedVREFDQ_A1==77
879 07:34:34.076633 VrefDac_Margin_A0==22
880 07:34:34.077117 DeviceVref_Margin_A0==39
881 07:34:34.082211 VrefDac_Margin_A1==24
882 07:34:34.082720 DeviceVref_Margin_A1==37
883 07:34:34.083161
884 07:34:34.087740 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
885 07:34:34.088261
886 07:34:34.115698 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000018 00000018 00000017 00000017 00000016 00000017 00000015 00000017 00000019 00000017 00000019 00000018 00000019 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
887 07:34:34.121515 2D training succeed
888 07:34:34.126922 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
889 07:34:34.127449 auto size-- 65535DDR cs0 size: 2048MB
890 07:34:34.132510 DDR cs1 size: 2048MB
891 07:34:34.133003 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
892 07:34:34.138115 cs0 DataBus test pass
893 07:34:34.138598 cs1 DataBus test pass
894 07:34:34.139027 cs0 AddrBus test pass
895 07:34:34.143661 cs1 AddrBus test pass
896 07:34:34.144273
897 07:34:34.144712 100bdlr_step_size ps== 420
898 07:34:34.145145 result report
899 07:34:34.149379 boot times 0Enable ddr reg access
900 07:34:34.157009 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
901 07:34:34.170460 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
902 07:34:34.744204 0.0;M3 CHK:0;cm4_sp_mode 0
903 07:34:34.744897 MVN_1=0x00000000
904 07:34:34.749598 MVN_2=0x00000000
905 07:34:34.755325 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
906 07:34:34.755813 OPS=0x10
907 07:34:34.756313 ring efuse init
908 07:34:34.756768 chipver efuse init
909 07:34:34.760927 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
910 07:34:34.766511 [0.018960 Inits done]
911 07:34:34.766991 secure task start!
912 07:34:34.767439 high task start!
913 07:34:34.771113 low task start!
914 07:34:34.771599 run into bl31
915 07:34:34.777773 NOTICE: BL31: v1.3(release):4fc40b1
916 07:34:34.785559 NOTICE: BL31: Built : 15:58:17, May 22 2019
917 07:34:34.786044 NOTICE: BL31: G12A normal boot!
918 07:34:34.810906 NOTICE: BL31: BL33 decompress pass
919 07:34:34.816608 ERROR: Error initializing runtime service opteed_fast
920 07:34:36.049648
921 07:34:36.050305
922 07:34:36.057958 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
923 07:34:36.058466
924 07:34:36.058931 Model: Libre Computer AML-A311D-CC Alta
925 07:34:36.266376 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
926 07:34:36.289786 DRAM: 2 GiB (effective 3.8 GiB)
927 07:34:36.432825 Core: 408 devices, 31 uclasses, devicetree: separate
928 07:34:36.438655 WDT: Not starting watchdog@f0d0
929 07:34:36.470883 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
930 07:34:36.483413 Loading Environment from FAT... Card did not respond to voltage select! : -110
931 07:34:36.488329 ** Bad device specification mmc 0 **
932 07:34:36.498670 Card did not respond to voltage select! : -110
933 07:34:36.506318 ** Bad device specification mmc 0 **
934 07:34:36.506811 Couldn't find partition mmc 0
935 07:34:36.514699 Card did not respond to voltage select! : -110
936 07:34:36.520211 ** Bad device specification mmc 0 **
937 07:34:36.520718 Couldn't find partition mmc 0
938 07:34:36.524345 Error: could not access storage.
939 07:34:36.868763 Net: eth0: ethernet@ff3f0000
940 07:34:36.869417 starting USB...
941 07:34:37.120579 Bus usb@ff500000: Register 3000140 NbrPorts 3
942 07:34:37.121224 Starting the controller
943 07:34:37.126642 USB XHCI 1.10
944 07:34:38.681569 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
945 07:34:38.689892 scanning usb for storage devices... 0 Storage Device(s) found
947 07:34:38.741579 Hit any key to stop autoboot: 1
948 07:34:38.742563 end: 2.4.2 bootloader-interrupt (duration 00:00:32) [common]
949 07:34:38.743246 start: 2.4.3 bootloader-commands (timeout 00:04:28) [common]
950 07:34:38.743778 Setting prompt string to ['=>']
951 07:34:38.744376 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:28)
952 07:34:38.756397 0
953 07:34:38.757352 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
954 07:34:38.757923 Sending with 10 millisecond of delay
956 07:34:39.893117 => setenv autoload no
957 07:34:39.903951 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:27)
958 07:34:39.908846 setenv autoload no
959 07:34:39.909593 Sending with 10 millisecond of delay
961 07:34:41.706755 => setenv initrd_high 0xffffffff
962 07:34:41.717549 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:25)
963 07:34:41.718413 setenv initrd_high 0xffffffff
964 07:34:41.719124 Sending with 10 millisecond of delay
966 07:34:43.335326 => setenv fdt_high 0xffffffff
967 07:34:43.346146 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:23)
968 07:34:43.346972 setenv fdt_high 0xffffffff
969 07:34:43.347681 Sending with 10 millisecond of delay
971 07:34:43.639661 => dhcp
972 07:34:43.650678 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:23)
973 07:34:43.651732 dhcp
974 07:34:43.652342 Speed: 1000, full duplex
975 07:34:43.652903 BOOTP broadcast 1
976 07:34:43.665866 DHCP client bound to address 192.168.6.27 (15 ms)
977 07:34:43.666736 Sending with 10 millisecond of delay
979 07:34:45.343683 => setenv serverip 192.168.6.2
980 07:34:45.354734 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:21)
981 07:34:45.355877 setenv serverip 192.168.6.2
982 07:34:45.356760 Sending with 10 millisecond of delay
984 07:34:49.080481 => tftpboot 0x01080000 933217/tftp-deploy-czzkl2bm/kernel/uImage
985 07:34:49.091490 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:17)
986 07:34:49.092611 tftpboot 0x01080000 933217/tftp-deploy-czzkl2bm/kernel/uImage
987 07:34:49.093191 Speed: 1000, full duplex
988 07:34:49.093721 Using ethernet@ff3f0000 device
989 07:34:49.094393 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
990 07:34:49.099903 Filename '933217/tftp-deploy-czzkl2bm/kernel/uImage'.
991 07:34:49.103686 Load address: 0x1080000
992 07:34:51.945922 Loading: *################################################## 43.9 MiB
993 07:34:51.946531 15.4 MiB/s
994 07:34:51.946974 done
995 07:34:51.950256 Bytes transferred = 46041664 (2be8a40 hex)
996 07:34:51.951031 Sending with 10 millisecond of delay
998 07:34:56.636897 => tftpboot 0x08000000 933217/tftp-deploy-czzkl2bm/ramdisk/ramdisk.cpio.gz.uboot
999 07:34:56.647681 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:10)
1000 07:34:56.648581 tftpboot 0x08000000 933217/tftp-deploy-czzkl2bm/ramdisk/ramdisk.cpio.gz.uboot
1001 07:34:56.649039 Speed: 1000, full duplex
1002 07:34:56.649452 Using ethernet@ff3f0000 device
1003 07:34:56.650663 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1004 07:34:56.662359 Filename '933217/tftp-deploy-czzkl2bm/ramdisk/ramdisk.cpio.gz.uboot'.
1005 07:34:56.662885 Load address: 0x8000000
1006 07:35:03.251425 Loading: *##################T ############################### UDP wrong checksum 00000005 00006043
1007 07:35:08.252650 T UDP wrong checksum 00000005 00006043
1008 07:35:18.255596 T T UDP wrong checksum 00000005 00006043
1009 07:35:29.117859 T T UDP wrong checksum 000000ff 0000c80f
1010 07:35:29.136448 UDP wrong checksum 000000ff 00005102
1011 07:35:38.259633 T T UDP wrong checksum 00000005 00006043
1012 07:35:53.263744 T T
1013 07:35:53.264619 Retry count exceeded; starting again
1015 07:35:53.266378 end: 2.4.3 bootloader-commands (duration 00:01:15) [common]
1018 07:35:53.268780 end: 2.4 uboot-commands (duration 00:01:47) [common]
1020 07:35:53.270521 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
1022 07:35:53.271841 end: 2 uboot-action (duration 00:01:47) [common]
1024 07:35:53.273950 Cleaning after the job
1025 07:35:53.274651 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/933217/tftp-deploy-czzkl2bm/ramdisk
1026 07:35:53.276330 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/933217/tftp-deploy-czzkl2bm/kernel
1027 07:35:53.322911 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/933217/tftp-deploy-czzkl2bm/dtb
1028 07:35:53.324065 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/933217/tftp-deploy-czzkl2bm/nfsrootfs
1029 07:35:53.482477 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/933217/tftp-deploy-czzkl2bm/modules
1030 07:35:53.503503 start: 4.1 power-off (timeout 00:00:30) [common]
1031 07:35:53.504201 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1032 07:35:53.539038 >> OK - accepted request
1033 07:35:53.541894 Returned 0 in 0 seconds
1034 07:35:53.642870 end: 4.1 power-off (duration 00:00:00) [common]
1036 07:35:53.644120 start: 4.2 read-feedback (timeout 00:10:00) [common]
1037 07:35:53.644910 Listened to connection for namespace 'common' for up to 1s
1038 07:35:54.645808 Finalising connection for namespace 'common'
1039 07:35:54.646327 Disconnecting from shell: Finalise
1040 07:35:54.646629 =>
1041 07:35:54.747326 end: 4.2 read-feedback (duration 00:00:01) [common]
1042 07:35:54.747812 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/933217
1043 07:35:56.449517 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/933217
1044 07:35:56.450135 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.