Boot log: meson-sm1-s905d3-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 07:56:46.471569 lava-dispatcher, installed at version: 2024.01
2 07:56:46.472379 start: 0 validate
3 07:56:46.472846 Start time: 2024-11-04 07:56:46.472815+00:00 (UTC)
4 07:56:46.473381 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 07:56:46.473913 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-igt%2F20240313.0%2Farm64%2Frootfs.cpio.gz exists
6 07:56:46.514933 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 07:56:46.515503 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241104%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 07:56:46.543190 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 07:56:46.543812 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241104%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-sm1-s905d3-libretech-cc.dtb exists
10 07:56:46.575490 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 07:56:46.576020 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241104%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
12 07:56:46.612077 validate duration: 0.14
14 07:56:46.612937 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 07:56:46.613265 start: 1.1 download-retry (timeout 00:10:00) [common]
16 07:56:46.613571 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 07:56:46.614154 Not decompressing ramdisk as can be used compressed.
18 07:56:46.614580 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-igt/20240313.0/arm64/rootfs.cpio.gz
19 07:56:46.614847 saving as /var/lib/lava/dispatcher/tmp/933200/tftp-deploy-u043x1el/ramdisk/rootfs.cpio.gz
20 07:56:46.615118 total size: 47897469 (45 MB)
21 07:56:46.646990 progress 0 % (0 MB)
22 07:56:46.683929 progress 5 % (2 MB)
23 07:56:46.723394 progress 10 % (4 MB)
24 07:56:46.767788 progress 15 % (6 MB)
25 07:56:46.808060 progress 20 % (9 MB)
26 07:56:46.847399 progress 25 % (11 MB)
27 07:56:46.887382 progress 30 % (13 MB)
28 07:56:46.926114 progress 35 % (16 MB)
29 07:56:46.966499 progress 40 % (18 MB)
30 07:56:47.005895 progress 45 % (20 MB)
31 07:56:47.045509 progress 50 % (22 MB)
32 07:56:47.084143 progress 55 % (25 MB)
33 07:56:47.123731 progress 60 % (27 MB)
34 07:56:47.165015 progress 65 % (29 MB)
35 07:56:47.204845 progress 70 % (32 MB)
36 07:56:47.244449 progress 75 % (34 MB)
37 07:56:47.285290 progress 80 % (36 MB)
38 07:56:47.326227 progress 85 % (38 MB)
39 07:56:47.364651 progress 90 % (41 MB)
40 07:56:47.410959 progress 95 % (43 MB)
41 07:56:47.452169 progress 100 % (45 MB)
42 07:56:47.453172 45 MB downloaded in 0.84 s (54.51 MB/s)
43 07:56:47.454090 end: 1.1.1 http-download (duration 00:00:01) [common]
45 07:56:47.455519 end: 1.1 download-retry (duration 00:00:01) [common]
46 07:56:47.456010 start: 1.2 download-retry (timeout 00:09:59) [common]
47 07:56:47.456450 start: 1.2.1 http-download (timeout 00:09:59) [common]
48 07:56:47.457118 downloading http://storage.kernelci.org/next/master/next-20241104/arm64/defconfig/gcc-12/kernel/Image
49 07:56:47.457475 saving as /var/lib/lava/dispatcher/tmp/933200/tftp-deploy-u043x1el/kernel/Image
50 07:56:47.457792 total size: 46041600 (43 MB)
51 07:56:47.458088 No compression specified
52 07:56:47.503362 progress 0 % (0 MB)
53 07:56:47.540111 progress 5 % (2 MB)
54 07:56:47.576958 progress 10 % (4 MB)
55 07:56:47.612999 progress 15 % (6 MB)
56 07:56:47.650149 progress 20 % (8 MB)
57 07:56:47.687434 progress 25 % (11 MB)
58 07:56:47.725511 progress 30 % (13 MB)
59 07:56:47.764341 progress 35 % (15 MB)
60 07:56:47.802141 progress 40 % (17 MB)
61 07:56:47.839301 progress 45 % (19 MB)
62 07:56:47.878288 progress 50 % (21 MB)
63 07:56:47.916916 progress 55 % (24 MB)
64 07:56:47.956235 progress 60 % (26 MB)
65 07:56:47.994568 progress 65 % (28 MB)
66 07:56:48.034647 progress 70 % (30 MB)
67 07:56:48.071789 progress 75 % (32 MB)
68 07:56:48.112061 progress 80 % (35 MB)
69 07:56:48.195444 progress 85 % (37 MB)
70 07:56:48.298997 progress 90 % (39 MB)
71 07:56:48.342932 progress 95 % (41 MB)
72 07:56:48.444638 progress 100 % (43 MB)
73 07:56:48.446957 43 MB downloaded in 0.99 s (44.39 MB/s)
74 07:56:48.447778 end: 1.2.1 http-download (duration 00:00:01) [common]
76 07:56:48.449129 end: 1.2 download-retry (duration 00:00:01) [common]
77 07:56:48.449600 start: 1.3 download-retry (timeout 00:09:58) [common]
78 07:56:48.450048 start: 1.3.1 http-download (timeout 00:09:58) [common]
79 07:56:48.450853 downloading http://storage.kernelci.org/next/master/next-20241104/arm64/defconfig/gcc-12/dtbs/amlogic/meson-sm1-s905d3-libretech-cc.dtb
80 07:56:48.451312 saving as /var/lib/lava/dispatcher/tmp/933200/tftp-deploy-u043x1el/dtb/meson-sm1-s905d3-libretech-cc.dtb
81 07:56:48.451695 total size: 53209 (0 MB)
82 07:56:48.452084 No compression specified
83 07:56:48.498073 progress 61 % (0 MB)
84 07:56:48.499222 progress 100 % (0 MB)
85 07:56:48.500146 0 MB downloaded in 0.05 s (1.05 MB/s)
86 07:56:48.500890 end: 1.3.1 http-download (duration 00:00:00) [common]
88 07:56:48.502165 end: 1.3 download-retry (duration 00:00:00) [common]
89 07:56:48.502638 start: 1.4 download-retry (timeout 00:09:58) [common]
90 07:56:48.503097 start: 1.4.1 http-download (timeout 00:09:58) [common]
91 07:56:48.503824 downloading http://storage.kernelci.org/next/master/next-20241104/arm64/defconfig/gcc-12/modules.tar.xz
92 07:56:48.504216 saving as /var/lib/lava/dispatcher/tmp/933200/tftp-deploy-u043x1el/modules/modules.tar
93 07:56:48.504563 total size: 11673844 (11 MB)
94 07:56:48.504889 Using unxz to decompress xz
95 07:56:48.543731 progress 0 % (0 MB)
96 07:56:48.653985 progress 5 % (0 MB)
97 07:56:48.750224 progress 10 % (1 MB)
98 07:56:48.853445 progress 15 % (1 MB)
99 07:56:48.950408 progress 20 % (2 MB)
100 07:56:49.030184 progress 25 % (2 MB)
101 07:56:49.101908 progress 30 % (3 MB)
102 07:56:49.181761 progress 35 % (3 MB)
103 07:56:49.259427 progress 40 % (4 MB)
104 07:56:49.336170 progress 45 % (5 MB)
105 07:56:49.421532 progress 50 % (5 MB)
106 07:56:49.499853 progress 55 % (6 MB)
107 07:56:49.587492 progress 60 % (6 MB)
108 07:56:49.669667 progress 65 % (7 MB)
109 07:56:49.752319 progress 70 % (7 MB)
110 07:56:49.835327 progress 75 % (8 MB)
111 07:56:49.920418 progress 80 % (8 MB)
112 07:56:49.998002 progress 85 % (9 MB)
113 07:56:50.082166 progress 90 % (10 MB)
114 07:56:50.161582 progress 95 % (10 MB)
115 07:56:50.242917 progress 100 % (11 MB)
116 07:56:50.255249 11 MB downloaded in 1.75 s (6.36 MB/s)
117 07:56:50.255907 end: 1.4.1 http-download (duration 00:00:02) [common]
119 07:56:50.257632 end: 1.4 download-retry (duration 00:00:02) [common]
120 07:56:50.258212 start: 1.5 prepare-tftp-overlay (timeout 00:09:56) [common]
121 07:56:50.258783 start: 1.5.1 extract-nfsrootfs (timeout 00:09:56) [common]
122 07:56:50.259323 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 07:56:50.259878 start: 1.5.2 lava-overlay (timeout 00:09:56) [common]
124 07:56:50.261000 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/933200/lava-overlay-byevfave
125 07:56:50.261951 makedir: /var/lib/lava/dispatcher/tmp/933200/lava-overlay-byevfave/lava-933200/bin
126 07:56:50.262692 makedir: /var/lib/lava/dispatcher/tmp/933200/lava-overlay-byevfave/lava-933200/tests
127 07:56:50.263379 makedir: /var/lib/lava/dispatcher/tmp/933200/lava-overlay-byevfave/lava-933200/results
128 07:56:50.264076 Creating /var/lib/lava/dispatcher/tmp/933200/lava-overlay-byevfave/lava-933200/bin/lava-add-keys
129 07:56:50.265145 Creating /var/lib/lava/dispatcher/tmp/933200/lava-overlay-byevfave/lava-933200/bin/lava-add-sources
130 07:56:50.266186 Creating /var/lib/lava/dispatcher/tmp/933200/lava-overlay-byevfave/lava-933200/bin/lava-background-process-start
131 07:56:50.267235 Creating /var/lib/lava/dispatcher/tmp/933200/lava-overlay-byevfave/lava-933200/bin/lava-background-process-stop
132 07:56:50.268384 Creating /var/lib/lava/dispatcher/tmp/933200/lava-overlay-byevfave/lava-933200/bin/lava-common-functions
133 07:56:50.269430 Creating /var/lib/lava/dispatcher/tmp/933200/lava-overlay-byevfave/lava-933200/bin/lava-echo-ipv4
134 07:56:50.270457 Creating /var/lib/lava/dispatcher/tmp/933200/lava-overlay-byevfave/lava-933200/bin/lava-install-packages
135 07:56:50.271461 Creating /var/lib/lava/dispatcher/tmp/933200/lava-overlay-byevfave/lava-933200/bin/lava-installed-packages
136 07:56:50.272492 Creating /var/lib/lava/dispatcher/tmp/933200/lava-overlay-byevfave/lava-933200/bin/lava-os-build
137 07:56:50.273491 Creating /var/lib/lava/dispatcher/tmp/933200/lava-overlay-byevfave/lava-933200/bin/lava-probe-channel
138 07:56:50.274519 Creating /var/lib/lava/dispatcher/tmp/933200/lava-overlay-byevfave/lava-933200/bin/lava-probe-ip
139 07:56:50.275524 Creating /var/lib/lava/dispatcher/tmp/933200/lava-overlay-byevfave/lava-933200/bin/lava-target-ip
140 07:56:50.276560 Creating /var/lib/lava/dispatcher/tmp/933200/lava-overlay-byevfave/lava-933200/bin/lava-target-mac
141 07:56:50.277692 Creating /var/lib/lava/dispatcher/tmp/933200/lava-overlay-byevfave/lava-933200/bin/lava-target-storage
142 07:56:50.278716 Creating /var/lib/lava/dispatcher/tmp/933200/lava-overlay-byevfave/lava-933200/bin/lava-test-case
143 07:56:50.279712 Creating /var/lib/lava/dispatcher/tmp/933200/lava-overlay-byevfave/lava-933200/bin/lava-test-event
144 07:56:50.280747 Creating /var/lib/lava/dispatcher/tmp/933200/lava-overlay-byevfave/lava-933200/bin/lava-test-feedback
145 07:56:50.281745 Creating /var/lib/lava/dispatcher/tmp/933200/lava-overlay-byevfave/lava-933200/bin/lava-test-raise
146 07:56:50.282759 Creating /var/lib/lava/dispatcher/tmp/933200/lava-overlay-byevfave/lava-933200/bin/lava-test-reference
147 07:56:50.283751 Creating /var/lib/lava/dispatcher/tmp/933200/lava-overlay-byevfave/lava-933200/bin/lava-test-runner
148 07:56:50.284807 Creating /var/lib/lava/dispatcher/tmp/933200/lava-overlay-byevfave/lava-933200/bin/lava-test-set
149 07:56:50.285929 Creating /var/lib/lava/dispatcher/tmp/933200/lava-overlay-byevfave/lava-933200/bin/lava-test-shell
150 07:56:50.286946 Updating /var/lib/lava/dispatcher/tmp/933200/lava-overlay-byevfave/lava-933200/bin/lava-install-packages (oe)
151 07:56:50.288085 Updating /var/lib/lava/dispatcher/tmp/933200/lava-overlay-byevfave/lava-933200/bin/lava-installed-packages (oe)
152 07:56:50.289037 Creating /var/lib/lava/dispatcher/tmp/933200/lava-overlay-byevfave/lava-933200/environment
153 07:56:50.289834 LAVA metadata
154 07:56:50.290377 - LAVA_JOB_ID=933200
155 07:56:50.290850 - LAVA_DISPATCHER_IP=192.168.6.2
156 07:56:50.291589 start: 1.5.2.1 ssh-authorize (timeout 00:09:56) [common]
157 07:56:50.293560 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 07:56:50.294191 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:56) [common]
159 07:56:50.294605 skipped lava-vland-overlay
160 07:56:50.295092 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 07:56:50.295596 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:56) [common]
162 07:56:50.296055 skipped lava-multinode-overlay
163 07:56:50.296591 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 07:56:50.297134 start: 1.5.2.4 test-definition (timeout 00:09:56) [common]
165 07:56:50.297627 Loading test definitions
166 07:56:50.298172 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:56) [common]
167 07:56:50.298606 Using /lava-933200 at stage 0
168 07:56:50.300473 uuid=933200_1.5.2.4.1 testdef=None
169 07:56:50.300809 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 07:56:50.301083 start: 1.5.2.4.2 test-overlay (timeout 00:09:56) [common]
171 07:56:50.302904 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 07:56:50.303739 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:56) [common]
174 07:56:50.305986 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 07:56:50.306876 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:56) [common]
177 07:56:50.309195 runner path: /var/lib/lava/dispatcher/tmp/933200/lava-overlay-byevfave/lava-933200/0/tests/0_igt-gpu-panfrost test_uuid 933200_1.5.2.4.1
178 07:56:50.309823 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 07:56:50.310653 Creating lava-test-runner.conf files
181 07:56:50.310863 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/933200/lava-overlay-byevfave/lava-933200/0 for stage 0
182 07:56:50.311227 - 0_igt-gpu-panfrost
183 07:56:50.311614 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 07:56:50.311905 start: 1.5.2.5 compress-overlay (timeout 00:09:56) [common]
185 07:56:50.337861 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 07:56:50.338320 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:56) [common]
187 07:56:50.338585 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 07:56:50.338854 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 07:56:50.339120 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:56) [common]
190 07:56:58.024235 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:08) [common]
191 07:56:58.024734 start: 1.5.4 extract-modules (timeout 00:09:49) [common]
192 07:56:58.025029 extracting modules file /var/lib/lava/dispatcher/tmp/933200/tftp-deploy-u043x1el/modules/modules.tar to /var/lib/lava/dispatcher/tmp/933200/extract-overlay-ramdisk-lpktmbgq/ramdisk
193 07:56:59.932374 end: 1.5.4 extract-modules (duration 00:00:02) [common]
194 07:56:59.932844 start: 1.5.5 apply-overlay-tftp (timeout 00:09:47) [common]
195 07:56:59.933216 [common] Applying overlay /var/lib/lava/dispatcher/tmp/933200/compress-overlay-uma927zt/overlay-1.5.2.5.tar.gz to ramdisk
196 07:56:59.933491 [common] Applying overlay /var/lib/lava/dispatcher/tmp/933200/compress-overlay-uma927zt/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/933200/extract-overlay-ramdisk-lpktmbgq/ramdisk
197 07:56:59.969260 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 07:56:59.969727 start: 1.5.6 prepare-kernel (timeout 00:09:47) [common]
199 07:56:59.970041 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:47) [common]
200 07:56:59.970283 Converting downloaded kernel to a uImage
201 07:56:59.970671 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/933200/tftp-deploy-u043x1el/kernel/Image /var/lib/lava/dispatcher/tmp/933200/tftp-deploy-u043x1el/kernel/uImage
202 07:57:00.432923 output: Image Name:
203 07:57:00.433342 output: Created: Mon Nov 4 07:56:59 2024
204 07:57:00.433552 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 07:57:00.433755 output: Data Size: 46041600 Bytes = 44962.50 KiB = 43.91 MiB
206 07:57:00.433953 output: Load Address: 01080000
207 07:57:00.434148 output: Entry Point: 01080000
208 07:57:00.434344 output:
209 07:57:00.434669 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
210 07:57:00.434931 end: 1.5.6 prepare-kernel (duration 00:00:00) [common]
211 07:57:00.435197 start: 1.5.7 configure-preseed-file (timeout 00:09:46) [common]
212 07:57:00.435447 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 07:57:00.435701 start: 1.5.8 compress-ramdisk (timeout 00:09:46) [common]
214 07:57:00.435951 Building ramdisk /var/lib/lava/dispatcher/tmp/933200/extract-overlay-ramdisk-lpktmbgq/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/933200/extract-overlay-ramdisk-lpktmbgq/ramdisk
215 07:57:07.592778 >> 503602 blocks
216 07:57:28.223794 Adding RAMdisk u-boot header.
217 07:57:28.224276 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/933200/extract-overlay-ramdisk-lpktmbgq/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/933200/extract-overlay-ramdisk-lpktmbgq/ramdisk.cpio.gz.uboot
218 07:57:28.935139 output: Image Name:
219 07:57:28.935778 output: Created: Mon Nov 4 07:57:28 2024
220 07:57:28.936224 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 07:57:28.936604 output: Data Size: 65828333 Bytes = 64285.48 KiB = 62.78 MiB
222 07:57:28.936975 output: Load Address: 00000000
223 07:57:28.937343 output: Entry Point: 00000000
224 07:57:28.937700 output:
225 07:57:28.938587 rename /var/lib/lava/dispatcher/tmp/933200/extract-overlay-ramdisk-lpktmbgq/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/933200/tftp-deploy-u043x1el/ramdisk/ramdisk.cpio.gz.uboot
226 07:57:28.939268 end: 1.5.8 compress-ramdisk (duration 00:00:29) [common]
227 07:57:28.939781 end: 1.5 prepare-tftp-overlay (duration 00:00:39) [common]
228 07:57:28.940321 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:18) [common]
229 07:57:28.940741 No LXC device requested
230 07:57:28.941206 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 07:57:28.941693 start: 1.7 deploy-device-env (timeout 00:09:18) [common]
232 07:57:28.942211 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 07:57:28.942596 Checking files for TFTP limit of 4294967296 bytes.
234 07:57:28.945080 end: 1 tftp-deploy (duration 00:00:42) [common]
235 07:57:28.945656 start: 2 uboot-action (timeout 00:05:00) [common]
236 07:57:28.946160 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 07:57:28.946637 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 07:57:28.947123 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 07:57:28.947624 Using kernel file from prepare-kernel: 933200/tftp-deploy-u043x1el/kernel/uImage
240 07:57:28.948247 substitutions:
241 07:57:28.948643 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 07:57:28.949015 - {DTB_ADDR}: 0x01070000
243 07:57:28.949388 - {DTB}: 933200/tftp-deploy-u043x1el/dtb/meson-sm1-s905d3-libretech-cc.dtb
244 07:57:28.949757 - {INITRD}: 933200/tftp-deploy-u043x1el/ramdisk/ramdisk.cpio.gz.uboot
245 07:57:28.950131 - {KERNEL_ADDR}: 0x01080000
246 07:57:28.950464 - {KERNEL}: 933200/tftp-deploy-u043x1el/kernel/uImage
247 07:57:28.950855 - {LAVA_MAC}: None
248 07:57:28.951260 - {PRESEED_CONFIG}: None
249 07:57:28.951646 - {PRESEED_LOCAL}: None
250 07:57:28.952026 - {RAMDISK_ADDR}: 0x08000000
251 07:57:28.952411 - {RAMDISK}: 933200/tftp-deploy-u043x1el/ramdisk/ramdisk.cpio.gz.uboot
252 07:57:28.952844 - {ROOT_PART}: None
253 07:57:28.953242 - {ROOT}: None
254 07:57:28.953617 - {SERVER_IP}: 192.168.6.2
255 07:57:28.954001 - {TEE_ADDR}: 0x83000000
256 07:57:28.954364 - {TEE}: None
257 07:57:28.954699 Parsed boot commands:
258 07:57:28.955046 - setenv autoload no
259 07:57:28.955369 - setenv initrd_high 0xffffffff
260 07:57:28.955718 - setenv fdt_high 0xffffffff
261 07:57:28.956096 - dhcp
262 07:57:28.956460 - setenv serverip 192.168.6.2
263 07:57:28.956814 - tftpboot 0x01080000 933200/tftp-deploy-u043x1el/kernel/uImage
264 07:57:28.957154 - tftpboot 0x08000000 933200/tftp-deploy-u043x1el/ramdisk/ramdisk.cpio.gz.uboot
265 07:57:28.957515 - tftpboot 0x01070000 933200/tftp-deploy-u043x1el/dtb/meson-sm1-s905d3-libretech-cc.dtb
266 07:57:28.957871 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 07:57:28.958244 - bootm 0x01080000 0x08000000 0x01070000
268 07:57:28.958821 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 07:57:28.960110 start: 2.3 connect-device (timeout 00:05:00) [common]
271 07:57:28.960553 [common] connect-device Connecting to device using 'telnet conserv1 3008'
272 07:57:28.974765 Setting prompt string to ['lava-test: # ']
273 07:57:28.976175 end: 2.3 connect-device (duration 00:00:00) [common]
274 07:57:28.976765 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 07:57:28.977355 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 07:57:28.977689 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 07:57:28.978330 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=solitude-01'
278 07:57:29.012006 >> OK - accepted request
279 07:57:29.014141 Returned 0 in 0 seconds
280 07:57:29.114903 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
282 07:57:29.115825 end: 2.4.1 reset-device (duration 00:00:00) [common]
283 07:57:29.116202 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
284 07:57:29.116483 Setting prompt string to ['Hit any key to stop autoboot']
285 07:57:29.116714 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 07:57:29.117602 Trying 192.168.56.21...
287 07:57:29.117876 Connected to conserv1.
288 07:57:29.118095 Escape character is '^]'.
289 07:57:29.118304
290 07:57:29.118523 ser2net port telnet,3008 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.3.3:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
291 07:57:29.118744
292 07:57:36.906897 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
293 07:57:36.907590 bl2_stage_init 0x01
294 07:57:36.908109 bl2_stage_init 0x81
295 07:57:36.912436 hw id: 0x0000 - pwm id 0x01
296 07:57:36.912947 bl2_stage_init 0xc1
297 07:57:36.918044 bl2_stage_init 0x02
298 07:57:36.918532
299 07:57:36.918974 L0:00000000
300 07:57:36.919404 L1:00000703
301 07:57:36.919829 L2:00008067
302 07:57:36.920292 L3:15000000
303 07:57:36.923571 S1:00000000
304 07:57:36.924078 B2:20282000
305 07:57:36.924513 B1:a0f83180
306 07:57:36.924944
307 07:57:36.925373 TE: 72879
308 07:57:36.925801
309 07:57:36.929139 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
310 07:57:36.929621
311 07:57:36.934910 Board ID = 1
312 07:57:36.935379 Set cpu clk to 24M
313 07:57:36.935808 Set clk81 to 24M
314 07:57:36.940349 Use GP1_pll as DSU clk.
315 07:57:36.940818 DSU clk: 1200 Mhz
316 07:57:36.941249 CPU clk: 1200 MHz
317 07:57:36.946004 Set clk81 to 166.6M
318 07:57:36.951523 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
319 07:57:36.952026 board id: 1
320 07:57:36.958726 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
321 07:57:36.969621 fw parse done
322 07:57:36.975707 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
323 07:57:37.018623 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
324 07:57:37.029771 PIEI prepare done
325 07:57:37.030231 fastboot data load
326 07:57:37.030670 fastboot data verify
327 07:57:37.035418 verify result: 266
328 07:57:37.040940 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
329 07:57:37.041412 LPDDR4 probe
330 07:57:37.041846 ddr clk to 1584MHz
331 07:57:37.048921 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
332 07:57:37.086647
333 07:57:37.087128 dmc_version 0001
334 07:57:37.093737 Check phy result
335 07:57:37.099751 INFO : End of CA training
336 07:57:37.100260 INFO : End of initialization
337 07:57:37.105277 INFO : Training has run successfully!
338 07:57:37.105736 Check phy result
339 07:57:37.110895 INFO : End of initialization
340 07:57:37.111351 INFO : End of read enable training
341 07:57:37.116513 INFO : End of fine write leveling
342 07:57:37.122055 INFO : End of Write leveling coarse delay
343 07:57:37.122512 INFO : Training has run successfully!
344 07:57:37.122943 Check phy result
345 07:57:37.127740 INFO : End of initialization
346 07:57:37.128231 INFO : End of read dq deskew training
347 07:57:37.133247 INFO : End of MPR read delay center optimization
348 07:57:37.138866 INFO : End of write delay center optimization
349 07:57:37.144514 INFO : End of read delay center optimization
350 07:57:37.144971 INFO : End of max read latency training
351 07:57:37.150059 INFO : Training has run successfully!
352 07:57:37.150513 1D training succeed
353 07:57:37.159253 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
354 07:57:37.207611 Check phy result
355 07:57:37.208119 INFO : End of initialization
356 07:57:37.233978 INFO : End of 2D read delay Voltage center optimization
357 07:57:37.259082 INFO : End of 2D read delay Voltage center optimization
358 07:57:37.316041 INFO : End of 2D write delay Voltage center optimization
359 07:57:37.369813 INFO : End of 2D write delay Voltage center optimization
360 07:57:37.375385 INFO : Training has run successfully!
361 07:57:37.375842
362 07:57:37.376322 channel==0
363 07:57:37.381005 RxClkDly_Margin_A0==78 ps 8
364 07:57:37.381462 TxDqDly_Margin_A0==88 ps 9
365 07:57:37.386540 RxClkDly_Margin_A1==78 ps 8
366 07:57:37.386996 TxDqDly_Margin_A1==98 ps 10
367 07:57:37.387431 TrainedVREFDQ_A0==74
368 07:57:37.392284 TrainedVREFDQ_A1==75
369 07:57:37.392745 VrefDac_Margin_A0==23
370 07:57:37.393172 DeviceVref_Margin_A0==40
371 07:57:37.397842 VrefDac_Margin_A1==23
372 07:57:37.398300 DeviceVref_Margin_A1==39
373 07:57:37.398726
374 07:57:37.399153
375 07:57:37.399579 channel==1
376 07:57:37.403328 RxClkDly_Margin_A0==78 ps 8
377 07:57:37.403786 TxDqDly_Margin_A0==98 ps 10
378 07:57:37.408917 RxClkDly_Margin_A1==78 ps 8
379 07:57:37.409376 TxDqDly_Margin_A1==88 ps 9
380 07:57:37.414534 TrainedVREFDQ_A0==75
381 07:57:37.414990 TrainedVREFDQ_A1==78
382 07:57:37.415422 VrefDac_Margin_A0==22
383 07:57:37.420145 DeviceVref_Margin_A0==39
384 07:57:37.420597 VrefDac_Margin_A1==22
385 07:57:37.425803 DeviceVref_Margin_A1==36
386 07:57:37.426253
387 07:57:37.426686 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
388 07:57:37.427113
389 07:57:37.459328 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000018 00000017 00000018 00000018 00000017 00000018 00000015 00000017 00000014 00000015 00000017 00000018 00000019 00000018 00000018 0000001c 00000017 00000016 00000017 dram_vref_reg_value 0x 00000061
390 07:57:37.459857 2D training succeed
391 07:57:37.464936 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
392 07:57:37.470538 auto size-- 65535DDR cs0 size: 2048MB
393 07:57:37.471006 DDR cs1 size: 2048MB
394 07:57:37.476105 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
395 07:57:37.476565 cs0 DataBus test pass
396 07:57:37.481794 cs1 DataBus test pass
397 07:57:37.482252 cs0 AddrBus test pass
398 07:57:37.482683 cs1 AddrBus test pass
399 07:57:37.483107
400 07:57:37.487311 100bdlr_step_size ps== 478
401 07:57:37.487776 result report
402 07:57:37.492944 boot times 0Enable ddr reg access
403 07:57:37.498098 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
404 07:57:37.512019 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
405 07:57:38.171746 bl2z: ptr: 05129330, size: 00001e40
406 07:57:38.180639 0.0;M3 CHK:0;cm4_sp_mode 0
407 07:57:38.181346 MVN_1=0x00000000
408 07:57:38.181819 MVN_2=0x00000000
409 07:57:38.191908 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
410 07:57:38.192571 OPS=0x04
411 07:57:38.193025 ring efuse init
412 07:57:38.197749 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
413 07:57:38.198263 [0.017354 Inits done]
414 07:57:38.198573 secure task start!
415 07:57:38.204229 high task start!
416 07:57:38.204740 low task start!
417 07:57:38.205030 run into bl31
418 07:57:38.213454 NOTICE: BL31: v1.3(release):4fc40b1
419 07:57:38.221082 NOTICE: BL31: Built : 15:57:33, May 22 2019
420 07:57:38.221606 NOTICE: BL31: G12A normal boot!
421 07:57:38.236894 NOTICE: BL31: BL33 decompress pass
422 07:57:38.242299 ERROR: Error initializing runtime service opteed_fast
423 07:57:40.948814 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0; SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
424 07:57:40.949508 bl2_stage_init 0x01
425 07:57:40.949959 bl2_stage_init 0x81
426 07:57:40.954320 hw id: 0x0000 - pwm id 0x01
427 07:57:40.954799 bl2_stage_init 0xc1
428 07:57:40.959952 bl2_stage_init 0x02
429 07:57:40.960484
430 07:57:40.960924 L0:00000000
431 07:57:40.961353 L1:00000703
432 07:57:40.961779 L2:00008067
433 07:57:40.962202 L3:15000000
434 07:57:40.965497 S1:00000000
435 07:57:40.965962 B2:20282000
436 07:57:40.966392 B1:a0f83180
437 07:57:40.966814
438 07:57:40.967235 TE: 66466
439 07:57:40.967660
440 07:57:40.971102 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
441 07:57:40.971569
442 07:57:40.976675 Board ID = 1
443 07:57:40.977133 Set cpu clk to 24M
444 07:57:40.977561 Set clk81 to 24M
445 07:57:40.982283 Use GP1_pll as DSU clk.
446 07:57:40.982745 DSU clk: 1200 Mhz
447 07:57:40.983171 CPU clk: 1200 MHz
448 07:57:40.987857 Set clk81 to 166.6M
449 07:57:40.993471 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
450 07:57:40.993935 board id: 1
451 07:57:41.000718 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
452 07:57:41.011436 fw parse done
453 07:57:41.017362 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
454 07:57:41.060462 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
455 07:57:41.070874 PIEI prepare done
456 07:57:41.071370 fastboot data load
457 07:57:41.071806 fastboot data verify
458 07:57:41.076463 verify result: 266
459 07:57:41.082069 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
460 07:57:41.082527 LPDDR4 probe
461 07:57:41.082955 ddr clk to 1584MHz
462 07:57:41.090111 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
463 07:57:41.127470
464 07:57:41.128010 dmc_version 0001
465 07:57:41.134013 Check phy result
466 07:57:41.139889 INFO : End of CA training
467 07:57:41.140642 INFO : End of initialization
468 07:57:41.145596 INFO : Training has run successfully!
469 07:57:41.146078 Check phy result
470 07:57:41.151101 INFO : End of initialization
471 07:57:41.151586 INFO : End of read enable training
472 07:57:41.156702 INFO : End of fine write leveling
473 07:57:41.162303 INFO : End of Write leveling coarse delay
474 07:57:41.162794 INFO : Training has run successfully!
475 07:57:41.163235 Check phy result
476 07:57:41.167894 INFO : End of initialization
477 07:57:41.168427 INFO : End of read dq deskew training
478 07:57:41.173540 INFO : End of MPR read delay center optimization
479 07:57:41.179118 INFO : End of write delay center optimization
480 07:57:41.184689 INFO : End of read delay center optimization
481 07:57:41.185171 INFO : End of max read latency training
482 07:57:41.190264 INFO : Training has run successfully!
483 07:57:41.190735 1D training succeed
484 07:57:41.199475 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
485 07:57:41.247222 Check phy result
486 07:57:41.247826 INFO : End of initialization
487 07:57:41.269460 INFO : End of 2D read delay Voltage center optimization
488 07:57:41.288672 INFO : End of 2D read delay Voltage center optimization
489 07:57:41.340477 INFO : End of 2D write delay Voltage center optimization
490 07:57:41.389697 INFO : End of 2D write delay Voltage center optimization
491 07:57:41.395251 INFO : Training has run successfully!
492 07:57:41.395791
493 07:57:41.396300 channel==0
494 07:57:41.400877 RxClkDly_Margin_A0==88 ps 9
495 07:57:41.401419 TxDqDly_Margin_A0==98 ps 10
496 07:57:41.406424 RxClkDly_Margin_A1==69 ps 7
497 07:57:41.406952 TxDqDly_Margin_A1==88 ps 9
498 07:57:41.407396 TrainedVREFDQ_A0==74
499 07:57:41.412137 TrainedVREFDQ_A1==75
500 07:57:41.412712 VrefDac_Margin_A0==24
501 07:57:41.413157 DeviceVref_Margin_A0==40
502 07:57:41.417675 VrefDac_Margin_A1==23
503 07:57:41.418230 DeviceVref_Margin_A1==39
504 07:57:41.418672
505 07:57:41.419107
506 07:57:41.419540 channel==1
507 07:57:41.423270 RxClkDly_Margin_A0==78 ps 8
508 07:57:41.423803 TxDqDly_Margin_A0==98 ps 10
509 07:57:41.428860 RxClkDly_Margin_A1==78 ps 8
510 07:57:41.429393 TxDqDly_Margin_A1==98 ps 10
511 07:57:41.434481 TrainedVREFDQ_A0==78
512 07:57:41.435009 TrainedVREFDQ_A1==78
513 07:57:41.435451 VrefDac_Margin_A0==22
514 07:57:41.440088 DeviceVref_Margin_A0==36
515 07:57:41.440614 VrefDac_Margin_A1==22
516 07:57:41.445665 DeviceVref_Margin_A1==36
517 07:57:41.446207
518 07:57:41.446650 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
519 07:57:41.447082
520 07:57:41.479201 soc_vref_reg_value 0x 00000019 00000018 00000017 00000017 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000017 00000017 00000018 00000018 00000017 00000019 00000015 00000017 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001c 00000017 00000016 00000017 dram_vref_reg_value 0x 00000061
521 07:57:41.479779 2D training succeed
522 07:57:41.484850 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
523 07:57:41.490483 auto size-- 65535DDR cs0 size: 2048MB
524 07:57:41.491016 DDR cs1 size: 2048MB
525 07:57:41.496079 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
526 07:57:41.496608 cs0 DataBus test pass
527 07:57:41.501653 cs1 DataBus test pass
528 07:57:41.502181 cs0 AddrBus test pass
529 07:57:41.502620 cs1 AddrBus test pass
530 07:57:41.503049
531 07:57:41.507244 100bdlr_step_size ps== 478
532 07:57:41.507788 result report
533 07:57:41.512932 boot times 0Enable ddr reg access
534 07:57:41.518139 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
535 07:57:41.531915 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
536 07:57:42.187247 bl2z: ptr: 05129330, size: 00001e40
537 07:57:42.195201 0.0;M3 CHK:0;cm4_sp_mode 0
538 07:57:42.195761 MVN_1=0x00000000
539 07:57:42.196261 MVN_2=0x00000000
540 07:57:42.206890 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
541 07:57:42.207443 OPS=0x04
542 07:57:42.207889 ring efuse init
543 07:57:42.212029 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
544 07:57:42.212577 [0.017310 Inits done]
545 07:57:42.213022 secure task start!
546 07:57:42.219304 high task start!
547 07:57:42.219885 low task start!
548 07:57:42.220377 run into bl31
549 07:57:42.228065 NOTICE: BL31: v1.3(release):4fc40b1
550 07:57:42.235721 NOTICE: BL31: Built : 15:57:33, May 22 2019
551 07:57:42.236299 NOTICE: BL31: G12A normal boot!
552 07:57:42.251227 NOTICE: BL31: BL33 decompress pass
553 07:57:42.256938 ERROR: Error initializing runtime service opteed_fast
554 07:57:43.652640 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
555 07:57:43.653319 bl2_stage_init 0x01
556 07:57:43.653770 bl2_stage_init 0x81
557 07:57:43.657631 hw id: 0x0000 - pwm id 0x01
558 07:57:43.658147 bl2_stage_init 0xc1
559 07:57:43.663106 bl2_stage_init 0x02
560 07:57:43.663612
561 07:57:43.664103 L0:00000000
562 07:57:43.664541 L1:00000703
563 07:57:43.664973 L2:00008067
564 07:57:43.665399 L3:15000000
565 07:57:43.668691 S1:00000000
566 07:57:43.669191 B2:20282000
567 07:57:43.669627 B1:a0f83180
568 07:57:43.670061
569 07:57:43.670488 TE: 69159
570 07:57:43.670918
571 07:57:43.674313 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
572 07:57:43.674818
573 07:57:43.680072 Board ID = 1
574 07:57:43.680570 Set cpu clk to 24M
575 07:57:43.681004 Set clk81 to 24M
576 07:57:43.685368 Use GP1_pll as DSU clk.
577 07:57:43.685868 DSU clk: 1200 Mhz
578 07:57:43.686303 CPU clk: 1200 MHz
579 07:57:43.690972 Set clk81 to 166.6M
580 07:57:43.696588 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
581 07:57:43.697100 board id: 1
582 07:57:43.703854 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
583 07:57:43.714603 fw parse done
584 07:57:43.720394 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
585 07:57:43.763031 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
586 07:57:43.773982 PIEI prepare done
587 07:57:43.774487 fastboot data load
588 07:57:43.774928 fastboot data verify
589 07:57:43.779584 verify result: 266
590 07:57:43.785195 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
591 07:57:43.785701 LPDDR4 probe
592 07:57:43.786138 ddr clk to 1584MHz
593 07:57:43.793155 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
594 07:57:43.830461
595 07:57:43.831010 dmc_version 0001
596 07:57:43.836293 Check phy result
597 07:57:43.842981 INFO : End of CA training
598 07:57:43.843482 INFO : End of initialization
599 07:57:43.848633 INFO : Training has run successfully!
600 07:57:43.849131 Check phy result
601 07:57:43.854193 INFO : End of initialization
602 07:57:43.854688 INFO : End of read enable training
603 07:57:43.859841 INFO : End of fine write leveling
604 07:57:43.865380 INFO : End of Write leveling coarse delay
605 07:57:43.865878 INFO : Training has run successfully!
606 07:57:43.866321 Check phy result
607 07:57:43.870991 INFO : End of initialization
608 07:57:43.871487 INFO : End of read dq deskew training
609 07:57:43.876614 INFO : End of MPR read delay center optimization
610 07:57:43.882200 INFO : End of write delay center optimization
611 07:57:43.887832 INFO : End of read delay center optimization
612 07:57:43.888370 INFO : End of max read latency training
613 07:57:43.893395 INFO : Training has run successfully!
614 07:57:43.893896 1D training succeed
615 07:57:43.902593 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
616 07:57:43.950139 Check phy result
617 07:57:43.950654 INFO : End of initialization
618 07:57:43.972471 INFO : End of 2D read delay Voltage center optimization
619 07:57:43.991701 INFO : End of 2D read delay Voltage center optimization
620 07:57:44.043636 INFO : End of 2D write delay Voltage center optimization
621 07:57:44.092719 INFO : End of 2D write delay Voltage center optimization
622 07:57:44.098365 INFO : Training has run successfully!
623 07:57:44.098857
624 07:57:44.099294 channel==0
625 07:57:44.104052 RxClkDly_Margin_A0==78 ps 8
626 07:57:44.104564 TxDqDly_Margin_A0==98 ps 10
627 07:57:44.109652 RxClkDly_Margin_A1==69 ps 7
628 07:57:44.110150 TxDqDly_Margin_A1==98 ps 10
629 07:57:44.110587 TrainedVREFDQ_A0==74
630 07:57:44.115193 TrainedVREFDQ_A1==74
631 07:57:44.115722 VrefDac_Margin_A0==24
632 07:57:44.116213 DeviceVref_Margin_A0==40
633 07:57:44.120818 VrefDac_Margin_A1==23
634 07:57:44.121315 DeviceVref_Margin_A1==40
635 07:57:44.121749
636 07:57:44.122177
637 07:57:44.126448 channel==1
638 07:57:44.126966 RxClkDly_Margin_A0==78 ps 8
639 07:57:44.127399 TxDqDly_Margin_A0==98 ps 10
640 07:57:44.132023 RxClkDly_Margin_A1==88 ps 9
641 07:57:44.132527 TxDqDly_Margin_A1==88 ps 9
642 07:57:44.137633 TrainedVREFDQ_A0==78
643 07:57:44.138146 TrainedVREFDQ_A1==77
644 07:57:44.138579 VrefDac_Margin_A0==22
645 07:57:44.143149 DeviceVref_Margin_A0==36
646 07:57:44.143646 VrefDac_Margin_A1==22
647 07:57:44.148688 DeviceVref_Margin_A1==37
648 07:57:44.149184
649 07:57:44.149618 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
650 07:57:44.150043
651 07:57:44.182399 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000017 00000017 00000018 00000018 00000017 00000019 00000015 00000018 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001c 00000017 00000015 00000017 dram_vref_reg_value 0x 00000061
652 07:57:44.182974 2D training succeed
653 07:57:44.188070 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
654 07:57:44.193416 auto size-- 65535DDR cs0 size: 2048MB
655 07:57:44.193919 DDR cs1 size: 2048MB
656 07:57:44.199008 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
657 07:57:44.199514 cs0 DataBus test pass
658 07:57:44.204618 cs1 DataBus test pass
659 07:57:44.205144 cs0 AddrBus test pass
660 07:57:44.205579 cs1 AddrBus test pass
661 07:57:44.206007
662 07:57:44.210231 100bdlr_step_size ps== 478
663 07:57:44.210767 result report
664 07:57:44.215842 boot times 0Enable ddr reg access
665 07:57:44.221112 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
666 07:57:44.234938 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
667 07:57:44.889535 bl2z: ptr: 05129330, size: 00001e40
668 07:57:44.898011 0.0;M3 CHK:0;cm4_sp_mode 0
669 07:57:44.898556 MVN_1=0x00000000
670 07:57:44.899014 MVN_2=0x00000000
671 07:57:44.909471 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
672 07:57:44.910002 OPS=0x04
673 07:57:44.910457 ring efuse init
674 07:57:44.915134 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
675 07:57:44.915656 [0.017319 Inits done]
676 07:57:44.916135 secure task start!
677 07:57:44.921895 high task start!
678 07:57:44.922434 low task start!
679 07:57:44.922886 run into bl31
680 07:57:44.931402 NOTICE: BL31: v1.3(release):4fc40b1
681 07:57:44.939193 NOTICE: BL31: Built : 15:57:33, May 22 2019
682 07:57:44.939722 NOTICE: BL31: G12A normal boot!
683 07:57:44.954679 NOTICE: BL31: BL33 decompress pass
684 07:57:44.960302 ERROR: Error initializing runtime service opteed_fast
685 07:57:45.755675
686 07:57:45.756394
687 07:57:45.761069 U-Boot 2024.01-rc4+ (Dec 14 2023 - 02:26:00 -0500) Libre Computer AML-S905D3-CC
688 07:57:45.761615
689 07:57:45.764643 Model: Libre Computer AML-S905D3-CC Solitude
690 07:57:45.911401 SoC: Amlogic Meson SM1 (S905D3) Revision 2b:c (4:2)
691 07:57:45.926800 DRAM: 2 GiB (effective 3.8 GiB)
692 07:57:46.027769 Core: 406 devices, 33 uclasses, devicetree: separate
693 07:57:46.033718 WDT: Not starting watchdog@f0d0
694 07:57:46.058815 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
695 07:57:46.070975 Loading Environment from FAT... Card did not respond to voltage select! : -110
696 07:57:46.076044 ** Bad device specification mmc 0 **
697 07:57:46.086038 Card did not respond to voltage select! : -110
698 07:57:46.093693 ** Bad device specification mmc 0 **
699 07:57:46.094250 Couldn't find partition mmc 0
700 07:57:46.101998 Card did not respond to voltage select! : -110
701 07:57:46.107515 ** Bad device specification mmc 0 **
702 07:57:46.108074 Couldn't find partition mmc 0
703 07:57:46.112583 Error: could not access storage.
704 07:57:46.409105 Net: eth0: ethernet@ff3f0000
705 07:57:46.409767 starting USB...
706 07:57:46.653798 Bus usb@ff500000: Register 3000140 NbrPorts 3
707 07:57:46.654455 Starting the controller
708 07:57:46.660655 USB XHCI 1.10
709 07:57:48.215121 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
710 07:57:48.223376 scanning usb for storage devices... 0 Storage Device(s) found
712 07:57:48.275013 Hit any key to stop autoboot: 1
713 07:57:48.275904 end: 2.4.2 bootloader-interrupt (duration 00:00:19) [common]
714 07:57:48.276590 start: 2.4.3 bootloader-commands (timeout 00:04:41) [common]
715 07:57:48.277115 Setting prompt string to ['=>']
716 07:57:48.277640 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:41)
717 07:57:48.289451 0
718 07:57:48.290410 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
720 07:57:48.391718 => setenv autoload no
721 07:57:48.392536 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
722 07:57:48.397837 setenv autoload no
724 07:57:48.499444 => setenv initrd_high 0xffffffff
725 07:57:48.500226 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
726 07:57:48.504471 setenv initrd_high 0xffffffff
728 07:57:48.605986 => setenv fdt_high 0xffffffff
729 07:57:48.606952 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
730 07:57:48.611123 setenv fdt_high 0xffffffff
732 07:57:48.712773 => dhcp
733 07:57:48.713768 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
734 07:57:48.717624 dhcp
735 07:57:49.273194 ethernet@ff3f0000 Waiting for PHY auto negotiation to complete. done
736 07:57:49.273866 Speed: 1000, full duplex
737 07:57:49.274342 BOOTP broadcast 1
738 07:57:49.521744 BOOTP broadcast 2
739 07:57:49.538439 DHCP client bound to address 192.168.6.21 (264 ms)
741 07:57:49.640100 => setenv serverip 192.168.6.2
742 07:57:49.641119 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:39)
743 07:57:49.645502 setenv serverip 192.168.6.2
745 07:57:49.747038 => tftpboot 0x01080000 933200/tftp-deploy-u043x1el/kernel/uImage
746 07:57:49.748045 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:39)
747 07:57:49.754644 tftpboot 0x01080000 933200/tftp-deploy-u043x1el/kernel/uImage
748 07:57:49.755162 Speed: 1000, full duplex
749 07:57:49.755618 Using ethernet@ff3f0000 device
750 07:57:49.760061 TFTP from server 192.168.6.2; our IP address is 192.168.6.21
751 07:57:49.765657 Filename '933200/tftp-deploy-u043x1el/kernel/uImage'.
752 07:57:49.773859 Load address: 0x1080000
753 07:57:49.774360 Loading: * UDP wrong checksum 00000005 0000b4f3
754 07:57:51.970258 ##################################### UDP wrong checksum 000000ff 000040fa
755 07:57:52.120292 ### UDP wrong checksum 000000ff 0000c5ec
756 07:57:52.680339 ########## 43.9 MiB
757 07:57:52.680769 15.1 MiB/s
758 07:57:52.681003 done
759 07:57:52.684762 Bytes transferred = 46041664 (2be8a40 hex)
761 07:57:52.785887 => tftpboot 0x08000000 933200/tftp-deploy-u043x1el/ramdisk/ramdisk.cpio.gz.uboot
762 07:57:52.786441 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:36)
763 07:57:52.793185 tftpboot 0x08000000 933200/tftp-deploy-u043x1el/ramdisk/ramdisk.cpio.gz.uboot
764 07:57:52.793539 Speed: 1000, full duplex
765 07:57:52.793775 Using ethernet@ff3f0000 device
766 07:57:52.798697 TFTP from server 192.168.6.2; our IP address is 192.168.6.21
767 07:57:52.808417 Filename '933200/tftp-deploy-u043x1el/ramdisk/ramdisk.cpio.gz.uboot'.
768 07:57:52.808792 Load address: 0x8000000
769 07:57:55.731388 Loading: *######################## UDP wrong checksum 000000ff 000084ee
770 07:57:55.746873 UDP wrong checksum 000000ff 00001ae1
771 07:58:02.431326 T ######################### UDP wrong checksum 0000000f 00009580
772 07:58:07.432459 T UDP wrong checksum 0000000f 00009580
773 07:58:09.992293 UDP wrong checksum 000000ff 0000ab23
774 07:58:10.030798 UDP wrong checksum 000000ff 00004716
775 07:58:17.434670 T T UDP wrong checksum 0000000f 00009580
776 07:58:35.738020 T T T UDP wrong checksum 000000ff 00002010
777 07:58:35.752916 UDP wrong checksum 000000ff 0000a902
778 07:58:37.436364 UDP wrong checksum 0000000f 00009580
779 07:58:52.442325 T T T
780 07:58:52.442768 Retry count exceeded; starting again
782 07:58:52.443649 end: 2.4.3 bootloader-commands (duration 00:01:04) [common]
785 07:58:52.444671 end: 2.4 uboot-commands (duration 00:01:23) [common]
787 07:58:52.445377 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
789 07:58:52.445956 end: 2 uboot-action (duration 00:01:24) [common]
791 07:58:52.446964 Cleaning after the job
792 07:58:52.447319 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/933200/tftp-deploy-u043x1el/ramdisk
793 07:58:52.448341 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/933200/tftp-deploy-u043x1el/kernel
794 07:58:52.477387 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/933200/tftp-deploy-u043x1el/dtb
795 07:58:52.478890 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/933200/tftp-deploy-u043x1el/modules
796 07:58:52.502015 start: 4.1 power-off (timeout 00:00:30) [common]
797 07:58:52.502722 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=solitude-01'
798 07:58:52.536662 >> OK - accepted request
799 07:58:52.538905 Returned 0 in 0 seconds
800 07:58:52.639753 end: 4.1 power-off (duration 00:00:00) [common]
802 07:58:52.640876 start: 4.2 read-feedback (timeout 00:10:00) [common]
803 07:58:52.641599 Listened to connection for namespace 'common' for up to 1s
804 07:58:53.642518 Finalising connection for namespace 'common'
805 07:58:53.643034 Disconnecting from shell: Finalise
806 07:58:53.643320 =>
807 07:58:53.744016 end: 4.2 read-feedback (duration 00:00:01) [common]
808 07:58:53.744519 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/933200
809 07:58:54.460920 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/933200
810 07:58:54.461521 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.