Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 09:15:13.014897 lava-dispatcher, installed at version: 2024.01
2 09:15:13.015690 start: 0 validate
3 09:15:13.016213 Start time: 2024-11-06 09:15:13.016182+00:00 (UTC)
4 09:15:13.016771 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 09:15:13.017317 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 09:15:13.055610 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 09:15:13.056153 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241106%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 09:15:13.086396 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 09:15:13.087002 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241106%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 09:15:13.117208 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 09:15:13.117700 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 09:15:13.148544 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 09:15:13.149028 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241106%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
14 09:15:13.186026 validate duration: 0.17
16 09:15:13.186861 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 09:15:13.187172 start: 1.1 download-retry (timeout 00:10:00) [common]
18 09:15:13.187474 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 09:15:13.188058 Not decompressing ramdisk as can be used compressed.
20 09:15:13.188514 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 09:15:13.188793 saving as /var/lib/lava/dispatcher/tmp/944985/tftp-deploy-0hpn_6_b/ramdisk/initrd.cpio.gz
22 09:15:13.189051 total size: 5628169 (5 MB)
23 09:15:13.224562 progress 0 % (0 MB)
24 09:15:13.228963 progress 5 % (0 MB)
25 09:15:13.233186 progress 10 % (0 MB)
26 09:15:13.236946 progress 15 % (0 MB)
27 09:15:13.241076 progress 20 % (1 MB)
28 09:15:13.244743 progress 25 % (1 MB)
29 09:15:13.248774 progress 30 % (1 MB)
30 09:15:13.252903 progress 35 % (1 MB)
31 09:15:13.256584 progress 40 % (2 MB)
32 09:15:13.260687 progress 45 % (2 MB)
33 09:15:13.264405 progress 50 % (2 MB)
34 09:15:13.268454 progress 55 % (2 MB)
35 09:15:13.272550 progress 60 % (3 MB)
36 09:15:13.276134 progress 65 % (3 MB)
37 09:15:13.280521 progress 70 % (3 MB)
38 09:15:13.284173 progress 75 % (4 MB)
39 09:15:13.288190 progress 80 % (4 MB)
40 09:15:13.291670 progress 85 % (4 MB)
41 09:15:13.295366 progress 90 % (4 MB)
42 09:15:13.298986 progress 95 % (5 MB)
43 09:15:13.302296 progress 100 % (5 MB)
44 09:15:13.302945 5 MB downloaded in 0.11 s (47.14 MB/s)
45 09:15:13.303490 end: 1.1.1 http-download (duration 00:00:00) [common]
47 09:15:13.304419 end: 1.1 download-retry (duration 00:00:00) [common]
48 09:15:13.304715 start: 1.2 download-retry (timeout 00:10:00) [common]
49 09:15:13.304986 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 09:15:13.305463 downloading http://storage.kernelci.org/next/master/next-20241106/arm64/defconfig/gcc-12/kernel/Image
51 09:15:13.305708 saving as /var/lib/lava/dispatcher/tmp/944985/tftp-deploy-0hpn_6_b/kernel/Image
52 09:15:13.305916 total size: 46041600 (43 MB)
53 09:15:13.306124 No compression specified
54 09:15:13.341328 progress 0 % (0 MB)
55 09:15:13.376352 progress 5 % (2 MB)
56 09:15:13.405860 progress 10 % (4 MB)
57 09:15:13.434537 progress 15 % (6 MB)
58 09:15:13.463955 progress 20 % (8 MB)
59 09:15:13.493164 progress 25 % (11 MB)
60 09:15:13.522155 progress 30 % (13 MB)
61 09:15:13.550880 progress 35 % (15 MB)
62 09:15:13.580002 progress 40 % (17 MB)
63 09:15:13.609005 progress 45 % (19 MB)
64 09:15:13.637372 progress 50 % (21 MB)
65 09:15:13.666294 progress 55 % (24 MB)
66 09:15:13.695451 progress 60 % (26 MB)
67 09:15:13.724094 progress 65 % (28 MB)
68 09:15:13.752722 progress 70 % (30 MB)
69 09:15:13.781393 progress 75 % (32 MB)
70 09:15:13.810911 progress 80 % (35 MB)
71 09:15:13.839127 progress 85 % (37 MB)
72 09:15:13.867912 progress 90 % (39 MB)
73 09:15:13.896568 progress 95 % (41 MB)
74 09:15:13.925066 progress 100 % (43 MB)
75 09:15:13.925626 43 MB downloaded in 0.62 s (70.86 MB/s)
76 09:15:13.926101 end: 1.2.1 http-download (duration 00:00:01) [common]
78 09:15:13.926916 end: 1.2 download-retry (duration 00:00:01) [common]
79 09:15:13.927188 start: 1.3 download-retry (timeout 00:09:59) [common]
80 09:15:13.927453 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 09:15:13.927914 downloading http://storage.kernelci.org/next/master/next-20241106/arm64/defconfig/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
82 09:15:13.928194 saving as /var/lib/lava/dispatcher/tmp/944985/tftp-deploy-0hpn_6_b/dtb/meson-g12b-a311d-libretech-cc.dtb
83 09:15:13.928404 total size: 54703 (0 MB)
84 09:15:13.928614 No compression specified
85 09:15:13.969889 progress 59 % (0 MB)
86 09:15:13.970763 progress 100 % (0 MB)
87 09:15:13.971319 0 MB downloaded in 0.04 s (1.22 MB/s)
88 09:15:13.971787 end: 1.3.1 http-download (duration 00:00:00) [common]
90 09:15:13.972691 end: 1.3 download-retry (duration 00:00:00) [common]
91 09:15:13.972961 start: 1.4 download-retry (timeout 00:09:59) [common]
92 09:15:13.973229 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 09:15:13.973689 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 09:15:13.973935 saving as /var/lib/lava/dispatcher/tmp/944985/tftp-deploy-0hpn_6_b/nfsrootfs/full.rootfs.tar
95 09:15:13.974140 total size: 120894716 (115 MB)
96 09:15:13.974349 Using unxz to decompress xz
97 09:15:14.015579 progress 0 % (0 MB)
98 09:15:14.809520 progress 5 % (5 MB)
99 09:15:15.650388 progress 10 % (11 MB)
100 09:15:16.448695 progress 15 % (17 MB)
101 09:15:17.182239 progress 20 % (23 MB)
102 09:15:17.777069 progress 25 % (28 MB)
103 09:15:18.610954 progress 30 % (34 MB)
104 09:15:19.409078 progress 35 % (40 MB)
105 09:15:19.775951 progress 40 % (46 MB)
106 09:15:20.160420 progress 45 % (51 MB)
107 09:15:20.886677 progress 50 % (57 MB)
108 09:15:21.778231 progress 55 % (63 MB)
109 09:15:22.563751 progress 60 % (69 MB)
110 09:15:23.320615 progress 65 % (74 MB)
111 09:15:24.105516 progress 70 % (80 MB)
112 09:15:24.934796 progress 75 % (86 MB)
113 09:15:25.728931 progress 80 % (92 MB)
114 09:15:26.501117 progress 85 % (98 MB)
115 09:15:27.362933 progress 90 % (103 MB)
116 09:15:28.148483 progress 95 % (109 MB)
117 09:15:29.060587 progress 100 % (115 MB)
118 09:15:29.073282 115 MB downloaded in 15.10 s (7.64 MB/s)
119 09:15:29.074309 end: 1.4.1 http-download (duration 00:00:15) [common]
121 09:15:29.076165 end: 1.4 download-retry (duration 00:00:15) [common]
122 09:15:29.076746 start: 1.5 download-retry (timeout 00:09:44) [common]
123 09:15:29.077296 start: 1.5.1 http-download (timeout 00:09:44) [common]
124 09:15:29.078137 downloading http://storage.kernelci.org/next/master/next-20241106/arm64/defconfig/gcc-12/modules.tar.xz
125 09:15:29.078633 saving as /var/lib/lava/dispatcher/tmp/944985/tftp-deploy-0hpn_6_b/modules/modules.tar
126 09:15:29.079046 total size: 11681704 (11 MB)
127 09:15:29.079498 Using unxz to decompress xz
128 09:15:29.125104 progress 0 % (0 MB)
129 09:15:29.194641 progress 5 % (0 MB)
130 09:15:29.270787 progress 10 % (1 MB)
131 09:15:29.367605 progress 15 % (1 MB)
132 09:15:29.464188 progress 20 % (2 MB)
133 09:15:29.543446 progress 25 % (2 MB)
134 09:15:29.615098 progress 30 % (3 MB)
135 09:15:29.695478 progress 35 % (3 MB)
136 09:15:29.775221 progress 40 % (4 MB)
137 09:15:29.853028 progress 45 % (5 MB)
138 09:15:29.937504 progress 50 % (5 MB)
139 09:15:30.019558 progress 55 % (6 MB)
140 09:15:30.101067 progress 60 % (6 MB)
141 09:15:30.181565 progress 65 % (7 MB)
142 09:15:30.262379 progress 70 % (7 MB)
143 09:15:30.344240 progress 75 % (8 MB)
144 09:15:30.427454 progress 80 % (8 MB)
145 09:15:30.507447 progress 85 % (9 MB)
146 09:15:30.586076 progress 90 % (10 MB)
147 09:15:30.663673 progress 95 % (10 MB)
148 09:15:30.740421 progress 100 % (11 MB)
149 09:15:30.752646 11 MB downloaded in 1.67 s (6.66 MB/s)
150 09:15:30.753405 end: 1.5.1 http-download (duration 00:00:02) [common]
152 09:15:30.754423 end: 1.5 download-retry (duration 00:00:02) [common]
153 09:15:30.754753 start: 1.6 prepare-tftp-overlay (timeout 00:09:42) [common]
154 09:15:30.755081 start: 1.6.1 extract-nfsrootfs (timeout 00:09:42) [common]
155 09:15:47.904363 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/944985/extract-nfsrootfs-pvv3z1m0
156 09:15:47.904960 end: 1.6.1 extract-nfsrootfs (duration 00:00:17) [common]
157 09:15:47.905262 start: 1.6.2 lava-overlay (timeout 00:09:25) [common]
158 09:15:47.906004 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/944985/lava-overlay-au49kz9i
159 09:15:47.906454 makedir: /var/lib/lava/dispatcher/tmp/944985/lava-overlay-au49kz9i/lava-944985/bin
160 09:15:47.906783 makedir: /var/lib/lava/dispatcher/tmp/944985/lava-overlay-au49kz9i/lava-944985/tests
161 09:15:47.907095 makedir: /var/lib/lava/dispatcher/tmp/944985/lava-overlay-au49kz9i/lava-944985/results
162 09:15:47.907431 Creating /var/lib/lava/dispatcher/tmp/944985/lava-overlay-au49kz9i/lava-944985/bin/lava-add-keys
163 09:15:47.907963 Creating /var/lib/lava/dispatcher/tmp/944985/lava-overlay-au49kz9i/lava-944985/bin/lava-add-sources
164 09:15:47.908506 Creating /var/lib/lava/dispatcher/tmp/944985/lava-overlay-au49kz9i/lava-944985/bin/lava-background-process-start
165 09:15:47.909005 Creating /var/lib/lava/dispatcher/tmp/944985/lava-overlay-au49kz9i/lava-944985/bin/lava-background-process-stop
166 09:15:47.909534 Creating /var/lib/lava/dispatcher/tmp/944985/lava-overlay-au49kz9i/lava-944985/bin/lava-common-functions
167 09:15:47.910032 Creating /var/lib/lava/dispatcher/tmp/944985/lava-overlay-au49kz9i/lava-944985/bin/lava-echo-ipv4
168 09:15:47.910520 Creating /var/lib/lava/dispatcher/tmp/944985/lava-overlay-au49kz9i/lava-944985/bin/lava-install-packages
169 09:15:47.910997 Creating /var/lib/lava/dispatcher/tmp/944985/lava-overlay-au49kz9i/lava-944985/bin/lava-installed-packages
170 09:15:47.911462 Creating /var/lib/lava/dispatcher/tmp/944985/lava-overlay-au49kz9i/lava-944985/bin/lava-os-build
171 09:15:47.911929 Creating /var/lib/lava/dispatcher/tmp/944985/lava-overlay-au49kz9i/lava-944985/bin/lava-probe-channel
172 09:15:47.912603 Creating /var/lib/lava/dispatcher/tmp/944985/lava-overlay-au49kz9i/lava-944985/bin/lava-probe-ip
173 09:15:47.913115 Creating /var/lib/lava/dispatcher/tmp/944985/lava-overlay-au49kz9i/lava-944985/bin/lava-target-ip
174 09:15:47.913614 Creating /var/lib/lava/dispatcher/tmp/944985/lava-overlay-au49kz9i/lava-944985/bin/lava-target-mac
175 09:15:47.914083 Creating /var/lib/lava/dispatcher/tmp/944985/lava-overlay-au49kz9i/lava-944985/bin/lava-target-storage
176 09:15:47.914594 Creating /var/lib/lava/dispatcher/tmp/944985/lava-overlay-au49kz9i/lava-944985/bin/lava-test-case
177 09:15:47.915080 Creating /var/lib/lava/dispatcher/tmp/944985/lava-overlay-au49kz9i/lava-944985/bin/lava-test-event
178 09:15:47.915627 Creating /var/lib/lava/dispatcher/tmp/944985/lava-overlay-au49kz9i/lava-944985/bin/lava-test-feedback
179 09:15:47.916145 Creating /var/lib/lava/dispatcher/tmp/944985/lava-overlay-au49kz9i/lava-944985/bin/lava-test-raise
180 09:15:47.916626 Creating /var/lib/lava/dispatcher/tmp/944985/lava-overlay-au49kz9i/lava-944985/bin/lava-test-reference
181 09:15:47.917119 Creating /var/lib/lava/dispatcher/tmp/944985/lava-overlay-au49kz9i/lava-944985/bin/lava-test-runner
182 09:15:47.917629 Creating /var/lib/lava/dispatcher/tmp/944985/lava-overlay-au49kz9i/lava-944985/bin/lava-test-set
183 09:15:47.918102 Creating /var/lib/lava/dispatcher/tmp/944985/lava-overlay-au49kz9i/lava-944985/bin/lava-test-shell
184 09:15:47.918585 Updating /var/lib/lava/dispatcher/tmp/944985/lava-overlay-au49kz9i/lava-944985/bin/lava-add-keys (debian)
185 09:15:47.919108 Updating /var/lib/lava/dispatcher/tmp/944985/lava-overlay-au49kz9i/lava-944985/bin/lava-add-sources (debian)
186 09:15:47.919604 Updating /var/lib/lava/dispatcher/tmp/944985/lava-overlay-au49kz9i/lava-944985/bin/lava-install-packages (debian)
187 09:15:47.920118 Updating /var/lib/lava/dispatcher/tmp/944985/lava-overlay-au49kz9i/lava-944985/bin/lava-installed-packages (debian)
188 09:15:47.920614 Updating /var/lib/lava/dispatcher/tmp/944985/lava-overlay-au49kz9i/lava-944985/bin/lava-os-build (debian)
189 09:15:47.921045 Creating /var/lib/lava/dispatcher/tmp/944985/lava-overlay-au49kz9i/lava-944985/environment
190 09:15:47.921401 LAVA metadata
191 09:15:47.921660 - LAVA_JOB_ID=944985
192 09:15:47.921874 - LAVA_DISPATCHER_IP=192.168.6.2
193 09:15:47.922237 start: 1.6.2.1 ssh-authorize (timeout 00:09:25) [common]
194 09:15:47.923217 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
195 09:15:47.923532 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:25) [common]
196 09:15:47.923737 skipped lava-vland-overlay
197 09:15:47.923977 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
198 09:15:47.924267 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:25) [common]
199 09:15:47.924489 skipped lava-multinode-overlay
200 09:15:47.924732 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
201 09:15:47.924983 start: 1.6.2.4 test-definition (timeout 00:09:25) [common]
202 09:15:47.925231 Loading test definitions
203 09:15:47.925505 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:25) [common]
204 09:15:47.925724 Using /lava-944985 at stage 0
205 09:15:47.926808 uuid=944985_1.6.2.4.1 testdef=None
206 09:15:47.927113 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
207 09:15:47.927374 start: 1.6.2.4.2 test-overlay (timeout 00:09:25) [common]
208 09:15:47.928931 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
210 09:15:47.929717 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:25) [common]
211 09:15:47.931663 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
213 09:15:47.932561 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:25) [common]
214 09:15:47.934383 runner path: /var/lib/lava/dispatcher/tmp/944985/lava-overlay-au49kz9i/lava-944985/0/tests/0_timesync-off test_uuid 944985_1.6.2.4.1
215 09:15:47.934922 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
217 09:15:47.935732 start: 1.6.2.4.5 git-repo-action (timeout 00:09:25) [common]
218 09:15:47.935954 Using /lava-944985 at stage 0
219 09:15:47.936331 Fetching tests from https://github.com/kernelci/test-definitions.git
220 09:15:47.936623 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/944985/lava-overlay-au49kz9i/lava-944985/0/tests/1_kselftest-dt'
221 09:15:51.300136 Running '/usr/bin/git checkout kernelci.org
222 09:15:51.633973 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/944985/lava-overlay-au49kz9i/lava-944985/0/tests/1_kselftest-dt/automated/linux/kselftest/kselftest.yaml
223 09:15:51.635433 uuid=944985_1.6.2.4.5 testdef=None
224 09:15:51.635831 end: 1.6.2.4.5 git-repo-action (duration 00:00:04) [common]
226 09:15:51.637374 start: 1.6.2.4.6 test-overlay (timeout 00:09:22) [common]
227 09:15:51.642709 end: 1.6.2.4.6 test-overlay (duration 00:00:00) [common]
229 09:15:51.644345 start: 1.6.2.4.7 test-install-overlay (timeout 00:09:22) [common]
230 09:15:51.651448 end: 1.6.2.4.7 test-install-overlay (duration 00:00:00) [common]
232 09:15:51.653163 start: 1.6.2.4.8 test-runscript-overlay (timeout 00:09:22) [common]
233 09:15:51.660208 runner path: /var/lib/lava/dispatcher/tmp/944985/lava-overlay-au49kz9i/lava-944985/0/tests/1_kselftest-dt test_uuid 944985_1.6.2.4.5
234 09:15:51.660762 BOARD='meson-g12b-a311d-libretech-cc'
235 09:15:51.661184 BRANCH='next'
236 09:15:51.661584 SKIPFILE='/dev/null'
237 09:15:51.661980 SKIP_INSTALL='True'
238 09:15:51.662375 TESTPROG_URL='http://storage.kernelci.org/next/master/next-20241106/arm64/defconfig/gcc-12/kselftest.tar.xz'
239 09:15:51.662781 TST_CASENAME=''
240 09:15:51.663178 TST_CMDFILES='dt'
241 09:15:51.664267 end: 1.6.2.4.8 test-runscript-overlay (duration 00:00:00) [common]
243 09:15:51.665858 Creating lava-test-runner.conf files
244 09:15:51.666276 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/944985/lava-overlay-au49kz9i/lava-944985/0 for stage 0
245 09:15:51.666941 - 0_timesync-off
246 09:15:51.667409 - 1_kselftest-dt
247 09:15:51.668082 end: 1.6.2.4 test-definition (duration 00:00:04) [common]
248 09:15:51.668649 start: 1.6.2.5 compress-overlay (timeout 00:09:22) [common]
249 09:16:16.172541 end: 1.6.2.5 compress-overlay (duration 00:00:25) [common]
250 09:16:16.173003 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:08:57) [common]
251 09:16:16.173301 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
252 09:16:16.173613 end: 1.6.2 lava-overlay (duration 00:00:28) [common]
253 09:16:16.173909 start: 1.6.3 extract-overlay-ramdisk (timeout 00:08:57) [common]
254 09:16:16.845875 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:01) [common]
255 09:16:16.846381 start: 1.6.4 extract-modules (timeout 00:08:56) [common]
256 09:16:16.846672 extracting modules file /var/lib/lava/dispatcher/tmp/944985/tftp-deploy-0hpn_6_b/modules/modules.tar to /var/lib/lava/dispatcher/tmp/944985/extract-nfsrootfs-pvv3z1m0
257 09:16:18.333465 extracting modules file /var/lib/lava/dispatcher/tmp/944985/tftp-deploy-0hpn_6_b/modules/modules.tar to /var/lib/lava/dispatcher/tmp/944985/extract-overlay-ramdisk-p8mm2n2u/ramdisk
258 09:16:19.761285 end: 1.6.4 extract-modules (duration 00:00:03) [common]
259 09:16:19.761756 start: 1.6.5 apply-overlay-tftp (timeout 00:08:53) [common]
260 09:16:19.762053 [common] Applying overlay to NFS
261 09:16:19.762282 [common] Applying overlay /var/lib/lava/dispatcher/tmp/944985/compress-overlay-cym2ryf4/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/944985/extract-nfsrootfs-pvv3z1m0
262 09:16:22.674061 end: 1.6.5 apply-overlay-tftp (duration 00:00:03) [common]
263 09:16:22.674552 start: 1.6.6 prepare-kernel (timeout 00:08:51) [common]
264 09:16:22.674859 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:08:51) [common]
265 09:16:22.675124 Converting downloaded kernel to a uImage
266 09:16:22.675458 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/944985/tftp-deploy-0hpn_6_b/kernel/Image /var/lib/lava/dispatcher/tmp/944985/tftp-deploy-0hpn_6_b/kernel/uImage
267 09:16:23.222373 output: Image Name:
268 09:16:23.222805 output: Created: Wed Nov 6 09:16:22 2024
269 09:16:23.223034 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
270 09:16:23.223251 output: Data Size: 46041600 Bytes = 44962.50 KiB = 43.91 MiB
271 09:16:23.223461 output: Load Address: 01080000
272 09:16:23.223672 output: Entry Point: 01080000
273 09:16:23.223877 output:
274 09:16:23.224257 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:01) [common]
275 09:16:23.224540 end: 1.6.6 prepare-kernel (duration 00:00:01) [common]
276 09:16:23.224827 start: 1.6.7 configure-preseed-file (timeout 00:08:50) [common]
277 09:16:23.225098 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
278 09:16:23.225373 start: 1.6.8 compress-ramdisk (timeout 00:08:50) [common]
279 09:16:23.225654 Building ramdisk /var/lib/lava/dispatcher/tmp/944985/extract-overlay-ramdisk-p8mm2n2u/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/944985/extract-overlay-ramdisk-p8mm2n2u/ramdisk
280 09:16:25.614301 >> 168055 blocks
281 09:16:33.405771 Adding RAMdisk u-boot header.
282 09:16:33.406465 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/944985/extract-overlay-ramdisk-p8mm2n2u/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/944985/extract-overlay-ramdisk-p8mm2n2u/ramdisk.cpio.gz.uboot
283 09:16:33.644306 output: Image Name:
284 09:16:33.644792 output: Created: Wed Nov 6 09:16:33 2024
285 09:16:33.645051 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
286 09:16:33.645301 output: Data Size: 23553641 Bytes = 23001.60 KiB = 22.46 MiB
287 09:16:33.645551 output: Load Address: 00000000
288 09:16:33.645795 output: Entry Point: 00000000
289 09:16:33.646041 output:
290 09:16:33.646741 rename /var/lib/lava/dispatcher/tmp/944985/extract-overlay-ramdisk-p8mm2n2u/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/944985/tftp-deploy-0hpn_6_b/ramdisk/ramdisk.cpio.gz.uboot
291 09:16:33.647242 end: 1.6.8 compress-ramdisk (duration 00:00:10) [common]
292 09:16:33.647586 end: 1.6 prepare-tftp-overlay (duration 00:01:03) [common]
293 09:16:33.647918 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:40) [common]
294 09:16:33.648569 No LXC device requested
295 09:16:33.649248 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
296 09:16:33.649916 start: 1.8 deploy-device-env (timeout 00:08:40) [common]
297 09:16:33.650558 end: 1.8 deploy-device-env (duration 00:00:00) [common]
298 09:16:33.651082 Checking files for TFTP limit of 4294967296 bytes.
299 09:16:33.654572 end: 1 tftp-deploy (duration 00:01:20) [common]
300 09:16:33.655320 start: 2 uboot-action (timeout 00:05:00) [common]
301 09:16:33.656018 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
302 09:16:33.656668 end: 2.1 uboot-from-media (duration 00:00:00) [common]
303 09:16:33.657327 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
304 09:16:33.658007 Using kernel file from prepare-kernel: 944985/tftp-deploy-0hpn_6_b/kernel/uImage
305 09:16:33.658812 substitutions:
306 09:16:33.659348 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
307 09:16:33.659867 - {DTB_ADDR}: 0x01070000
308 09:16:33.660465 - {DTB}: 944985/tftp-deploy-0hpn_6_b/dtb/meson-g12b-a311d-libretech-cc.dtb
309 09:16:33.660985 - {INITRD}: 944985/tftp-deploy-0hpn_6_b/ramdisk/ramdisk.cpio.gz.uboot
310 09:16:33.661509 - {KERNEL_ADDR}: 0x01080000
311 09:16:33.662020 - {KERNEL}: 944985/tftp-deploy-0hpn_6_b/kernel/uImage
312 09:16:33.662529 - {LAVA_MAC}: None
313 09:16:33.663084 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/944985/extract-nfsrootfs-pvv3z1m0
314 09:16:33.663598 - {NFS_SERVER_IP}: 192.168.6.2
315 09:16:33.664143 - {PRESEED_CONFIG}: None
316 09:16:33.664655 - {PRESEED_LOCAL}: None
317 09:16:33.665163 - {RAMDISK_ADDR}: 0x08000000
318 09:16:33.665665 - {RAMDISK}: 944985/tftp-deploy-0hpn_6_b/ramdisk/ramdisk.cpio.gz.uboot
319 09:16:33.666171 - {ROOT_PART}: None
320 09:16:33.666680 - {ROOT}: None
321 09:16:33.667182 - {SERVER_IP}: 192.168.6.2
322 09:16:33.667684 - {TEE_ADDR}: 0x83000000
323 09:16:33.668212 - {TEE}: None
324 09:16:33.668718 Parsed boot commands:
325 09:16:33.669214 - setenv autoload no
326 09:16:33.669718 - setenv initrd_high 0xffffffff
327 09:16:33.670219 - setenv fdt_high 0xffffffff
328 09:16:33.670720 - dhcp
329 09:16:33.671211 - setenv serverip 192.168.6.2
330 09:16:33.671718 - tftpboot 0x01080000 944985/tftp-deploy-0hpn_6_b/kernel/uImage
331 09:16:33.672258 - tftpboot 0x08000000 944985/tftp-deploy-0hpn_6_b/ramdisk/ramdisk.cpio.gz.uboot
332 09:16:33.672763 - tftpboot 0x01070000 944985/tftp-deploy-0hpn_6_b/dtb/meson-g12b-a311d-libretech-cc.dtb
333 09:16:33.673269 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/944985/extract-nfsrootfs-pvv3z1m0,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
334 09:16:33.673783 - bootm 0x01080000 0x08000000 0x01070000
335 09:16:33.674435 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
337 09:16:33.676393 start: 2.3 connect-device (timeout 00:05:00) [common]
338 09:16:33.676939 [common] connect-device Connecting to device using 'telnet conserv1 3007'
339 09:16:33.693983 Setting prompt string to ['lava-test: # ']
340 09:16:33.695874 end: 2.3 connect-device (duration 00:00:00) [common]
341 09:16:33.696739 start: 2.4 uboot-commands (timeout 00:05:00) [common]
342 09:16:33.697684 start: 2.4.1 reset-device (timeout 00:05:00) [common]
343 09:16:33.698433 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
344 09:16:33.699881 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
345 09:16:33.735831 >> OK - accepted request
346 09:16:33.737988 Returned 0 in 0 seconds
347 09:16:33.839348 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
349 09:16:33.841451 end: 2.4.1 reset-device (duration 00:00:00) [common]
350 09:16:33.842165 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
351 09:16:33.842807 Setting prompt string to ['Hit any key to stop autoboot']
352 09:16:33.843376 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
353 09:16:33.845429 Trying 192.168.56.21...
354 09:16:33.846045 Connected to conserv1.
355 09:16:33.846583 Escape character is '^]'.
356 09:16:33.847120
357 09:16:33.847650 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
358 09:16:33.848247
359 09:16:44.853572 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
360 09:16:44.854418 bl2_stage_init 0x01
361 09:16:44.855018 bl2_stage_init 0x81
362 09:16:44.859091 hw id: 0x0000 - pwm id 0x01
363 09:16:44.859741 bl2_stage_init 0xc1
364 09:16:44.860387 bl2_stage_init 0x02
365 09:16:44.860993
366 09:16:44.864667 L0:00000000
367 09:16:44.865314 L1:20000703
368 09:16:44.865885 L2:00008067
369 09:16:44.866445 L3:14000000
370 09:16:44.870265 B2:00402000
371 09:16:44.870904 B1:e0f83180
372 09:16:44.871477
373 09:16:44.872066 TE: 58159
374 09:16:44.872624
375 09:16:44.875843 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
376 09:16:44.876498
377 09:16:44.877062 Board ID = 1
378 09:16:44.881491 Set A53 clk to 24M
379 09:16:44.882136 Set A73 clk to 24M
380 09:16:44.882686 Set clk81 to 24M
381 09:16:44.887074 A53 clk: 1200 MHz
382 09:16:44.887681 A73 clk: 1200 MHz
383 09:16:44.888277 CLK81: 166.6M
384 09:16:44.888854 smccc: 00012ab5
385 09:16:44.892649 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
386 09:16:44.898244 board id: 1
387 09:16:44.904193 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
388 09:16:44.914793 fw parse done
389 09:16:44.920785 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
390 09:16:44.963457 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
391 09:16:44.974386 PIEI prepare done
392 09:16:44.975031 fastboot data load
393 09:16:44.975454 fastboot data verify
394 09:16:44.979953 verify result: 266
395 09:16:44.985526 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
396 09:16:44.986114 LPDDR4 probe
397 09:16:44.986523 ddr clk to 1584MHz
398 09:16:44.993635 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
399 09:16:45.030819
400 09:16:45.031246 dmc_version 0001
401 09:16:45.037410 Check phy result
402 09:16:45.043202 INFO : End of CA training
403 09:16:45.043644 INFO : End of initialization
404 09:16:45.048818 INFO : Training has run successfully!
405 09:16:45.049242 Check phy result
406 09:16:45.054417 INFO : End of initialization
407 09:16:45.054833 INFO : End of read enable training
408 09:16:45.060081 INFO : End of fine write leveling
409 09:16:45.065680 INFO : End of Write leveling coarse delay
410 09:16:45.066116 INFO : Training has run successfully!
411 09:16:45.066514 Check phy result
412 09:16:45.071237 INFO : End of initialization
413 09:16:45.071670 INFO : End of read dq deskew training
414 09:16:45.076853 INFO : End of MPR read delay center optimization
415 09:16:45.082449 INFO : End of write delay center optimization
416 09:16:45.088072 INFO : End of read delay center optimization
417 09:16:45.088499 INFO : End of max read latency training
418 09:16:45.093666 INFO : Training has run successfully!
419 09:16:45.094105 1D training succeed
420 09:16:45.102870 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
421 09:16:45.150605 Check phy result
422 09:16:45.151134 INFO : End of initialization
423 09:16:45.172083 INFO : End of 2D read delay Voltage center optimization
424 09:16:45.192220 INFO : End of 2D read delay Voltage center optimization
425 09:16:45.244059 INFO : End of 2D write delay Voltage center optimization
426 09:16:45.293347 INFO : End of 2D write delay Voltage center optimization
427 09:16:45.298867 INFO : Training has run successfully!
428 09:16:45.299318
429 09:16:45.299742 channel==0
430 09:16:45.304538 RxClkDly_Margin_A0==88 ps 9
431 09:16:45.304998 TxDqDly_Margin_A0==98 ps 10
432 09:16:45.310116 RxClkDly_Margin_A1==88 ps 9
433 09:16:45.310617 TxDqDly_Margin_A1==98 ps 10
434 09:16:45.311037 TrainedVREFDQ_A0==74
435 09:16:45.315731 TrainedVREFDQ_A1==74
436 09:16:45.316207 VrefDac_Margin_A0==25
437 09:16:45.316618 DeviceVref_Margin_A0==40
438 09:16:45.321322 VrefDac_Margin_A1==25
439 09:16:45.321757 DeviceVref_Margin_A1==40
440 09:16:45.322166
441 09:16:45.322574
442 09:16:45.326880 channel==1
443 09:16:45.327310 RxClkDly_Margin_A0==98 ps 10
444 09:16:45.327719 TxDqDly_Margin_A0==88 ps 9
445 09:16:45.332551 RxClkDly_Margin_A1==98 ps 10
446 09:16:45.333009 TxDqDly_Margin_A1==88 ps 9
447 09:16:45.337984 TrainedVREFDQ_A0==77
448 09:16:45.338439 TrainedVREFDQ_A1==77
449 09:16:45.338855 VrefDac_Margin_A0==22
450 09:16:45.343847 DeviceVref_Margin_A0==37
451 09:16:45.344332 VrefDac_Margin_A1==22
452 09:16:45.349349 DeviceVref_Margin_A1==37
453 09:16:45.349798
454 09:16:45.350218 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
455 09:16:45.350627
456 09:16:45.385380 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000018 00000019 00000018 0000001a 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
457 09:16:45.387249 2D training succeed
458 09:16:45.389089 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
459 09:16:45.394882 auto size-- 65535DDR cs0 size: 2048MB
460 09:16:45.395458 DDR cs1 size: 2048MB
461 09:16:45.399796 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
462 09:16:45.400427 cs0 DataBus test pass
463 09:16:45.405299 cs1 DataBus test pass
464 09:16:45.405847 cs0 AddrBus test pass
465 09:16:45.406310 cs1 AddrBus test pass
466 09:16:45.406790
467 09:16:45.411019 100bdlr_step_size ps== 420
468 09:16:45.411589 result report
469 09:16:45.416766 boot times 0Enable ddr reg access
470 09:16:45.421896 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
471 09:16:45.435302 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
472 09:16:46.007328 0.0;M3 CHK:0;cm4_sp_mode 0
473 09:16:46.008096 MVN_1=0x00000000
474 09:16:46.012798 MVN_2=0x00000000
475 09:16:46.018577 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
476 09:16:46.018987 OPS=0x10
477 09:16:46.019219 ring efuse init
478 09:16:46.019433 chipver efuse init
479 09:16:46.024208 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
480 09:16:46.029774 [0.018961 Inits done]
481 09:16:46.030420 secure task start!
482 09:16:46.030845 high task start!
483 09:16:46.034285 low task start!
484 09:16:46.034733 run into bl31
485 09:16:46.041000 NOTICE: BL31: v1.3(release):4fc40b1
486 09:16:46.048694 NOTICE: BL31: Built : 15:58:17, May 22 2019
487 09:16:46.049151 NOTICE: BL31: G12A normal boot!
488 09:16:46.074635 NOTICE: BL31: BL33 decompress pass
489 09:16:46.080248 ERROR: Error initializing runtime service opteed_fast
490 09:16:47.313183
491 09:16:47.313618
492 09:16:47.321462 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
493 09:16:47.321765
494 09:16:47.322009 Model: Libre Computer AML-A311D-CC Alta
495 09:16:47.530045 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
496 09:16:47.553304 DRAM: 2 GiB (effective 3.8 GiB)
497 09:16:47.696412 Core: 408 devices, 31 uclasses, devicetree: separate
498 09:16:47.702161 WDT: Not starting watchdog@f0d0
499 09:16:47.734381 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
500 09:16:47.746970 Loading Environment from FAT... Card did not respond to voltage select! : -110
501 09:16:47.751832 ** Bad device specification mmc 0 **
502 09:16:47.762149 Card did not respond to voltage select! : -110
503 09:16:47.769834 ** Bad device specification mmc 0 **
504 09:16:47.770328 Couldn't find partition mmc 0
505 09:16:47.778163 Card did not respond to voltage select! : -110
506 09:16:47.783719 ** Bad device specification mmc 0 **
507 09:16:47.784250 Couldn't find partition mmc 0
508 09:16:47.788774 Error: could not access storage.
509 09:16:49.053753 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
510 09:16:49.054199 bl2_stage_init 0x01
511 09:16:49.054435 bl2_stage_init 0x81
512 09:16:49.059292 hw id: 0x0000 - pwm id 0x01
513 09:16:49.059611 bl2_stage_init 0xc1
514 09:16:49.059830 bl2_stage_init 0x02
515 09:16:49.060086
516 09:16:49.064862 L0:00000000
517 09:16:49.065160 L1:20000703
518 09:16:49.065373 L2:00008067
519 09:16:49.065575 L3:14000000
520 09:16:49.067732 B2:00402000
521 09:16:49.068154 B1:e0f83180
522 09:16:49.068491
523 09:16:49.068864 TE: 58124
524 09:16:49.069198
525 09:16:49.078865 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
526 09:16:49.079332
527 09:16:49.079600 Board ID = 1
528 09:16:49.079816 Set A53 clk to 24M
529 09:16:49.080050 Set A73 clk to 24M
530 09:16:49.084446 Set clk81 to 24M
531 09:16:49.084743 A53 clk: 1200 MHz
532 09:16:49.084958 A73 clk: 1200 MHz
533 09:16:49.090117 CLK81: 166.6M
534 09:16:49.090577 smccc: 00012a91
535 09:16:49.095653 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
536 09:16:49.096127 board id: 1
537 09:16:49.101350 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
538 09:16:49.115248 fw parse done
539 09:16:49.121035 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
540 09:16:49.163736 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
541 09:16:49.174584 PIEI prepare done
542 09:16:49.175131 fastboot data load
543 09:16:49.175611 fastboot data verify
544 09:16:49.180290 verify result: 266
545 09:16:49.185799 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
546 09:16:49.186330 LPDDR4 probe
547 09:16:49.186797 ddr clk to 1584MHz
548 09:16:49.193766 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
549 09:16:49.231103
550 09:16:49.231704 dmc_version 0001
551 09:16:49.237747 Check phy result
552 09:16:49.243592 INFO : End of CA training
553 09:16:49.244159 INFO : End of initialization
554 09:16:49.249309 INFO : Training has run successfully!
555 09:16:49.249847 Check phy result
556 09:16:49.254793 INFO : End of initialization
557 09:16:49.255325 INFO : End of read enable training
558 09:16:49.260413 INFO : End of fine write leveling
559 09:16:49.266032 INFO : End of Write leveling coarse delay
560 09:16:49.266566 INFO : Training has run successfully!
561 09:16:49.267032 Check phy result
562 09:16:49.271602 INFO : End of initialization
563 09:16:49.272185 INFO : End of read dq deskew training
564 09:16:49.277291 INFO : End of MPR read delay center optimization
565 09:16:49.282797 INFO : End of write delay center optimization
566 09:16:49.288432 INFO : End of read delay center optimization
567 09:16:49.288967 INFO : End of max read latency training
568 09:16:49.294020 INFO : Training has run successfully!
569 09:16:49.294558 1D training succeed
570 09:16:49.303174 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
571 09:16:49.350984 Check phy result
572 09:16:49.351635 INFO : End of initialization
573 09:16:49.372639 INFO : End of 2D read delay Voltage center optimization
574 09:16:49.392882 INFO : End of 2D read delay Voltage center optimization
575 09:16:49.444951 INFO : End of 2D write delay Voltage center optimization
576 09:16:49.494298 INFO : End of 2D write delay Voltage center optimization
577 09:16:49.499802 INFO : Training has run successfully!
578 09:16:49.500405
579 09:16:49.500890 channel==0
580 09:16:49.505435 RxClkDly_Margin_A0==88 ps 9
581 09:16:49.505970 TxDqDly_Margin_A0==98 ps 10
582 09:16:49.508769 RxClkDly_Margin_A1==88 ps 9
583 09:16:49.509360 TxDqDly_Margin_A1==98 ps 10
584 09:16:49.514274 TrainedVREFDQ_A0==74
585 09:16:49.514833 TrainedVREFDQ_A1==74
586 09:16:49.519875 VrefDac_Margin_A0==25
587 09:16:49.520498 DeviceVref_Margin_A0==40
588 09:16:49.520972 VrefDac_Margin_A1==25
589 09:16:49.525555 DeviceVref_Margin_A1==40
590 09:16:49.526106
591 09:16:49.526582
592 09:16:49.527047 channel==1
593 09:16:49.527503 RxClkDly_Margin_A0==98 ps 10
594 09:16:49.531046 TxDqDly_Margin_A0==98 ps 10
595 09:16:49.531602 RxClkDly_Margin_A1==98 ps 10
596 09:16:49.536672 TxDqDly_Margin_A1==88 ps 9
597 09:16:49.537249 TrainedVREFDQ_A0==77
598 09:16:49.537724 TrainedVREFDQ_A1==77
599 09:16:49.542433 VrefDac_Margin_A0==22
600 09:16:49.543000 DeviceVref_Margin_A0==37
601 09:16:49.547856 VrefDac_Margin_A1==22
602 09:16:49.548453 DeviceVref_Margin_A1==37
603 09:16:49.548929
604 09:16:49.553464 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
605 09:16:49.554027
606 09:16:49.581472 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000018 00000019 00000018 00000019 00000018 00000019 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
607 09:16:49.587168 2D training succeed
608 09:16:49.592681 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
609 09:16:49.593290 auto size-- 65535DDR cs0 size: 2048MB
610 09:16:49.598291 DDR cs1 size: 2048MB
611 09:16:49.598849 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
612 09:16:49.603851 cs0 DataBus test pass
613 09:16:49.604463 cs1 DataBus test pass
614 09:16:49.604940 cs0 AddrBus test pass
615 09:16:49.609554 cs1 AddrBus test pass
616 09:16:49.610173
617 09:16:49.610653 100bdlr_step_size ps== 420
618 09:16:49.611135 result report
619 09:16:49.615067 boot times 0Enable ddr reg access
620 09:16:49.621999 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
621 09:16:49.635475 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
622 09:16:50.209320 0.0;M3 CHK:0;cm4_sp_mode 0
623 09:16:50.209995 MVN_1=0x00000000
624 09:16:50.214803 MVN_2=0x00000000
625 09:16:50.220585 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
626 09:16:50.221151 OPS=0x10
627 09:16:50.221629 ring efuse init
628 09:16:50.222126 chipver efuse init
629 09:16:50.226147 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
630 09:16:50.231722 [0.018961 Inits done]
631 09:16:50.232287 secure task start!
632 09:16:50.232731 high task start!
633 09:16:50.236410 low task start!
634 09:16:50.236914 run into bl31
635 09:16:50.242990 NOTICE: BL31: v1.3(release):4fc40b1
636 09:16:50.250817 NOTICE: BL31: Built : 15:58:17, May 22 2019
637 09:16:50.251342 NOTICE: BL31: G12A normal boot!
638 09:16:50.276142 NOTICE: BL31: BL33 decompress pass
639 09:16:50.281838 ERROR: Error initializing runtime service opteed_fast
640 09:16:51.514741
641 09:16:51.515379
642 09:16:51.522382 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
643 09:16:51.522968
644 09:16:51.523441 Model: Libre Computer AML-A311D-CC Alta
645 09:16:51.731617 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
646 09:16:51.754674 DRAM: 2 GiB (effective 3.8 GiB)
647 09:16:51.898018 Core: 408 devices, 31 uclasses, devicetree: separate
648 09:16:51.902998 WDT: Not starting watchdog@f0d0
649 09:16:51.936201 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
650 09:16:51.948678 Loading Environment from FAT... Card did not respond to voltage select! : -110
651 09:16:51.953587 ** Bad device specification mmc 0 **
652 09:16:51.963813 Card did not respond to voltage select! : -110
653 09:16:51.971521 ** Bad device specification mmc 0 **
654 09:16:51.972134 Couldn't find partition mmc 0
655 09:16:51.979931 Card did not respond to voltage select! : -110
656 09:16:51.985368 ** Bad device specification mmc 0 **
657 09:16:51.985923 Couldn't find partition mmc 0
658 09:16:51.990399 Error: could not access storage.
659 09:16:52.333166 Net: eth0: ethernet@ff3f0000
660 09:16:52.333802 starting USB...
661 09:16:52.585672 Bus usb@ff500000: Register 3000140 NbrPorts 3
662 09:16:52.586046 Starting the controller
663 09:16:52.592553 USB XHCI 1.10
664 09:16:54.305843 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
665 09:16:54.306231 bl2_stage_init 0x01
666 09:16:54.306459 bl2_stage_init 0x81
667 09:16:54.311384 hw id: 0x0000 - pwm id 0x01
668 09:16:54.311663 bl2_stage_init 0xc1
669 09:16:54.311879 bl2_stage_init 0x02
670 09:16:54.312127
671 09:16:54.316872 L0:00000000
672 09:16:54.317146 L1:20000703
673 09:16:54.317365 L2:00008067
674 09:16:54.317574 L3:14000000
675 09:16:54.319732 B2:00402000
676 09:16:54.320011 B1:e0f83180
677 09:16:54.320229
678 09:16:54.320438 TE: 58159
679 09:16:54.320643
680 09:16:54.330790 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
681 09:16:54.331091
682 09:16:54.331342 Board ID = 1
683 09:16:54.331558 Set A53 clk to 24M
684 09:16:54.331764 Set A73 clk to 24M
685 09:16:54.336559 Set clk81 to 24M
686 09:16:54.336830 A53 clk: 1200 MHz
687 09:16:54.337044 A73 clk: 1200 MHz
688 09:16:54.342010 CLK81: 166.6M
689 09:16:54.342273 smccc: 00012ab5
690 09:16:54.347692 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
691 09:16:54.347958 board id: 1
692 09:16:54.356455 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
693 09:16:54.367095 fw parse done
694 09:16:54.373098 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
695 09:16:54.415626 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
696 09:16:54.426453 PIEI prepare done
697 09:16:54.426971 fastboot data load
698 09:16:54.427435 fastboot data verify
699 09:16:54.432109 verify result: 266
700 09:16:54.437710 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
701 09:16:54.438225 LPDDR4 probe
702 09:16:54.438680 ddr clk to 1584MHz
703 09:16:54.445691 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
704 09:16:54.482876
705 09:16:54.483396 dmc_version 0001
706 09:16:54.489552 Check phy result
707 09:16:54.495443 INFO : End of CA training
708 09:16:54.495952 INFO : End of initialization
709 09:16:54.501066 INFO : Training has run successfully!
710 09:16:54.501575 Check phy result
711 09:16:54.506763 INFO : End of initialization
712 09:16:54.507368 INFO : End of read enable training
713 09:16:54.512345 INFO : End of fine write leveling
714 09:16:54.518068 INFO : End of Write leveling coarse delay
715 09:16:54.518603 INFO : Training has run successfully!
716 09:16:54.519057 Check phy result
717 09:16:54.523480 INFO : End of initialization
718 09:16:54.523829 INFO : End of read dq deskew training
719 09:16:54.529191 INFO : End of MPR read delay center optimization
720 09:16:54.534840 INFO : End of write delay center optimization
721 09:16:54.540337 INFO : End of read delay center optimization
722 09:16:54.540975 INFO : End of max read latency training
723 09:16:54.546007 INFO : Training has run successfully!
724 09:16:54.546455 1D training succeed
725 09:16:54.555097 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
726 09:16:54.602760 Check phy result
727 09:16:54.603403 INFO : End of initialization
728 09:16:54.625316 INFO : End of 2D read delay Voltage center optimization
729 09:16:54.644683 INFO : End of 2D read delay Voltage center optimization
730 09:16:54.696577 INFO : End of 2D write delay Voltage center optimization
731 09:16:54.746002 INFO : End of 2D write delay Voltage center optimization
732 09:16:54.751482 INFO : Training has run successfully!
733 09:16:54.751926
734 09:16:54.752629 channel==0
735 09:16:54.757098 RxClkDly_Margin_A0==88 ps 9
736 09:16:54.757577 TxDqDly_Margin_A0==98 ps 10
737 09:16:54.760442 RxClkDly_Margin_A1==88 ps 9
738 09:16:54.760896 TxDqDly_Margin_A1==98 ps 10
739 09:16:54.765993 TrainedVREFDQ_A0==74
740 09:16:54.766450 TrainedVREFDQ_A1==74
741 09:16:54.766867 VrefDac_Margin_A0==24
742 09:16:54.771591 DeviceVref_Margin_A0==40
743 09:16:54.772098 VrefDac_Margin_A1==25
744 09:16:54.777215 DeviceVref_Margin_A1==40
745 09:16:54.777661
746 09:16:54.778073
747 09:16:54.778482 channel==1
748 09:16:54.778883 RxClkDly_Margin_A0==88 ps 9
749 09:16:54.780498 TxDqDly_Margin_A0==98 ps 10
750 09:16:54.786102 RxClkDly_Margin_A1==88 ps 9
751 09:16:54.786549 TxDqDly_Margin_A1==88 ps 9
752 09:16:54.786964 TrainedVREFDQ_A0==77
753 09:16:54.791711 TrainedVREFDQ_A1==77
754 09:16:54.792193 VrefDac_Margin_A0==23
755 09:16:54.797307 DeviceVref_Margin_A0==37
756 09:16:54.797746 VrefDac_Margin_A1==24
757 09:16:54.798156 DeviceVref_Margin_A1==37
758 09:16:54.798554
759 09:16:54.802916 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
760 09:16:54.803358
761 09:16:54.836612 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000018 00000018 00000016 00000018 00000016 00000017 00000019 00000017 00000019 00000019 00000019 00000019 00000018 00000017 00000018 00000017 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
762 09:16:54.837137 2D training succeed
763 09:16:54.842150 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
764 09:16:54.847728 auto size-- 65535DDR cs0 size: 2048MB
765 09:16:54.848207 DDR cs1 size: 2048MB
766 09:16:54.853323 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
767 09:16:54.853769 cs0 DataBus test pass
768 09:16:54.854182 cs1 DataBus test pass
769 09:16:54.858928 cs0 AddrBus test pass
770 09:16:54.859372 cs1 AddrBus test pass
771 09:16:54.859778
772 09:16:54.864529 100bdlr_step_size ps== 420
773 09:16:54.865008 result report
774 09:16:54.865421 boot times 0Enable ddr reg access
775 09:16:54.874326 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
776 09:16:54.887804 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
777 09:16:55.461523 0.0;M3 CHK:0;cm4_sp_mode 0
778 09:16:55.462039 MVN_1=0x00000000
779 09:16:55.467123 MVN_2=0x00000000
780 09:16:55.472864 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
781 09:16:55.473394 OPS=0x10
782 09:16:55.473792 ring efuse init
783 09:16:55.474177 chipver efuse init
784 09:16:55.478422 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
785 09:16:55.484038 [0.018961 Inits done]
786 09:16:55.484488 secure task start!
787 09:16:55.484878 high task start!
788 09:16:55.488590 low task start!
789 09:16:55.489025 run into bl31
790 09:16:55.495227 NOTICE: BL31: v1.3(release):4fc40b1
791 09:16:55.503024 NOTICE: BL31: Built : 15:58:17, May 22 2019
792 09:16:55.503475 NOTICE: BL31: G12A normal boot!
793 09:16:55.528385 NOTICE: BL31: BL33 decompress pass
794 09:16:55.534026 ERROR: Error initializing runtime service opteed_fast
795 09:16:56.766980
796 09:16:56.767554
797 09:16:56.775369 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
798 09:16:56.775894
799 09:16:56.776380 Model: Libre Computer AML-A311D-CC Alta
800 09:16:56.983841 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
801 09:16:57.007236 DRAM: 2 GiB (effective 3.8 GiB)
802 09:16:57.150265 Core: 408 devices, 31 uclasses, devicetree: separate
803 09:16:57.156050 WDT: Not starting watchdog@f0d0
804 09:16:57.188268 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
805 09:16:57.200747 Loading Environment from FAT... Card did not respond to voltage select! : -110
806 09:16:57.205710 ** Bad device specification mmc 0 **
807 09:16:57.216069 Card did not respond to voltage select! : -110
808 09:16:57.223678 ** Bad device specification mmc 0 **
809 09:16:57.224175 Couldn't find partition mmc 0
810 09:16:57.232060 Card did not respond to voltage select! : -110
811 09:16:57.237561 ** Bad device specification mmc 0 **
812 09:16:57.238032 Couldn't find partition mmc 0
813 09:16:57.242618 Error: could not access storage.
814 09:16:57.586188 Net: eth0: ethernet@ff3f0000
815 09:16:57.586729 starting USB...
816 09:16:57.837955 Bus usb@ff500000: Register 3000140 NbrPorts 3
817 09:16:57.838509 Starting the controller
818 09:16:57.844885 USB XHCI 1.10
819 09:17:00.004173 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
820 09:17:00.004756 bl2_stage_init 0x01
821 09:17:00.005190 bl2_stage_init 0x81
822 09:17:00.009806 hw id: 0x0000 - pwm id 0x01
823 09:17:00.010286 bl2_stage_init 0xc1
824 09:17:00.010706 bl2_stage_init 0x02
825 09:17:00.011115
826 09:17:00.015453 L0:00000000
827 09:17:00.015908 L1:20000703
828 09:17:00.016380 L2:00008067
829 09:17:00.016795 L3:14000000
830 09:17:00.018287 B2:00402000
831 09:17:00.018745 B1:e0f83180
832 09:17:00.019163
833 09:17:00.019571 TE: 58124
834 09:17:00.020010
835 09:17:00.029505 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
836 09:17:00.029978
837 09:17:00.030402 Board ID = 1
838 09:17:00.030817 Set A53 clk to 24M
839 09:17:00.031219 Set A73 clk to 24M
840 09:17:00.034950 Set clk81 to 24M
841 09:17:00.035411 A53 clk: 1200 MHz
842 09:17:00.035827 A73 clk: 1200 MHz
843 09:17:00.040483 CLK81: 166.6M
844 09:17:00.040942 smccc: 00012a92
845 09:17:00.046128 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
846 09:17:00.046590 board id: 1
847 09:17:00.054706 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
848 09:17:00.065417 fw parse done
849 09:17:00.071349 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
850 09:17:00.113996 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
851 09:17:00.124869 PIEI prepare done
852 09:17:00.125332 fastboot data load
853 09:17:00.125755 fastboot data verify
854 09:17:00.130532 verify result: 266
855 09:17:00.136101 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
856 09:17:00.136557 LPDDR4 probe
857 09:17:00.136971 ddr clk to 1584MHz
858 09:17:00.144071 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
859 09:17:00.181336
860 09:17:00.181793 dmc_version 0001
861 09:17:00.188054 Check phy result
862 09:17:00.193864 INFO : End of CA training
863 09:17:00.194327 INFO : End of initialization
864 09:17:00.199507 INFO : Training has run successfully!
865 09:17:00.199961 Check phy result
866 09:17:00.205027 INFO : End of initialization
867 09:17:00.205483 INFO : End of read enable training
868 09:17:00.208338 INFO : End of fine write leveling
869 09:17:00.213932 INFO : End of Write leveling coarse delay
870 09:17:00.219531 INFO : Training has run successfully!
871 09:17:00.220047 Check phy result
872 09:17:00.220476 INFO : End of initialization
873 09:17:00.225099 INFO : End of read dq deskew training
874 09:17:00.230676 INFO : End of MPR read delay center optimization
875 09:17:00.231144 INFO : End of write delay center optimization
876 09:17:00.236296 INFO : End of read delay center optimization
877 09:17:00.241878 INFO : End of max read latency training
878 09:17:00.242333 INFO : Training has run successfully!
879 09:17:00.247488 1D training succeed
880 09:17:00.253422 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
881 09:17:00.301056 Check phy result
882 09:17:00.301527 INFO : End of initialization
883 09:17:00.322624 INFO : End of 2D read delay Voltage center optimization
884 09:17:00.342800 INFO : End of 2D read delay Voltage center optimization
885 09:17:00.394282 INFO : End of 2D write delay Voltage center optimization
886 09:17:00.443936 INFO : End of 2D write delay Voltage center optimization
887 09:17:00.449564 INFO : Training has run successfully!
888 09:17:00.450016
889 09:17:00.450439 channel==0
890 09:17:00.455264 RxClkDly_Margin_A0==88 ps 9
891 09:17:00.455719 TxDqDly_Margin_A0==98 ps 10
892 09:17:00.458635 RxClkDly_Margin_A1==88 ps 9
893 09:17:00.459086 TxDqDly_Margin_A1==88 ps 9
894 09:17:00.464095 TrainedVREFDQ_A0==74
895 09:17:00.464549 TrainedVREFDQ_A1==74
896 09:17:00.464995 VrefDac_Margin_A0==25
897 09:17:00.469625 DeviceVref_Margin_A0==40
898 09:17:00.470140 VrefDac_Margin_A1==25
899 09:17:00.475334 DeviceVref_Margin_A1==40
900 09:17:00.475844
901 09:17:00.476275
902 09:17:00.476663 channel==1
903 09:17:00.477046 RxClkDly_Margin_A0==98 ps 10
904 09:17:00.480936 TxDqDly_Margin_A0==98 ps 10
905 09:17:00.481379 RxClkDly_Margin_A1==98 ps 10
906 09:17:00.486441 TxDqDly_Margin_A1==98 ps 10
907 09:17:00.486899 TrainedVREFDQ_A0==77
908 09:17:00.487292 TrainedVREFDQ_A1==77
909 09:17:00.492009 VrefDac_Margin_A0==22
910 09:17:00.492439 DeviceVref_Margin_A0==37
911 09:17:00.497628 VrefDac_Margin_A1==22
912 09:17:00.498062 DeviceVref_Margin_A1==37
913 09:17:00.498452
914 09:17:00.503204 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
915 09:17:00.503627
916 09:17:00.531257 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000018 00000019 00000018 0000001a 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
917 09:17:00.536813 2D training succeed
918 09:17:00.542305 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
919 09:17:00.542745 auto size-- 65535DDR cs0 size: 2048MB
920 09:17:00.547908 DDR cs1 size: 2048MB
921 09:17:00.548379 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
922 09:17:00.553481 cs0 DataBus test pass
923 09:17:00.553907 cs1 DataBus test pass
924 09:17:00.554292 cs0 AddrBus test pass
925 09:17:00.559177 cs1 AddrBus test pass
926 09:17:00.559618
927 09:17:00.560037 100bdlr_step_size ps== 420
928 09:17:00.560437 result report
929 09:17:00.564711 boot times 0Enable ddr reg access
930 09:17:00.572468 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
931 09:17:00.585902 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
932 09:17:01.157965 0.0;M3 CHK:0;cm4_sp_mode 0
933 09:17:01.158523 MVN_1=0x00000000
934 09:17:01.163505 MVN_2=0x00000000
935 09:17:01.169209 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
936 09:17:01.169697 OPS=0x10
937 09:17:01.170128 ring efuse init
938 09:17:01.170540 chipver efuse init
939 09:17:01.174801 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
940 09:17:01.180397 [0.018960 Inits done]
941 09:17:01.180858 secure task start!
942 09:17:01.181274 high task start!
943 09:17:01.184969 low task start!
944 09:17:01.185422 run into bl31
945 09:17:01.191601 NOTICE: BL31: v1.3(release):4fc40b1
946 09:17:01.199132 NOTICE: BL31: Built : 15:58:17, May 22 2019
947 09:17:01.199599 NOTICE: BL31: G12A normal boot!
948 09:17:01.224857 NOTICE: BL31: BL33 decompress pass
949 09:17:01.229502 ERROR: Error initializing runtime service opteed_fast
950 09:17:02.463380
951 09:17:02.463965
952 09:17:02.471755 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
953 09:17:02.472266
954 09:17:02.472714 Model: Libre Computer AML-A311D-CC Alta
955 09:17:02.680217 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
956 09:17:02.703543 DRAM: 2 GiB (effective 3.8 GiB)
957 09:17:02.846602 Core: 408 devices, 31 uclasses, devicetree: separate
958 09:17:02.852407 WDT: Not starting watchdog@f0d0
959 09:17:02.884706 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
960 09:17:02.897133 Loading Environment from FAT... Card did not respond to voltage select! : -110
961 09:17:02.902082 ** Bad device specification mmc 0 **
962 09:17:02.912463 Card did not respond to voltage select! : -110
963 09:17:02.920093 ** Bad device specification mmc 0 **
964 09:17:02.920551 Couldn't find partition mmc 0
965 09:17:02.928415 Card did not respond to voltage select! : -110
966 09:17:02.933982 ** Bad device specification mmc 0 **
967 09:17:02.934445 Couldn't find partition mmc 0
968 09:17:02.939039 Error: could not access storage.
969 09:17:03.281834 Net: eth0: ethernet@ff3f0000
970 09:17:03.282347 starting USB...
971 09:17:03.533674 Bus usb@ff500000: Register 3000140 NbrPorts 3
972 09:17:03.534198 Starting the controller
973 09:17:03.540606 USB XHCI 1.10
974 09:17:05.313989 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
975 09:17:05.314563 bl2_stage_init 0x01
976 09:17:05.314994 bl2_stage_init 0x81
977 09:17:05.319552 hw id: 0x0000 - pwm id 0x01
978 09:17:05.320040 bl2_stage_init 0xc1
979 09:17:05.320464 bl2_stage_init 0x02
980 09:17:05.320871
981 09:17:05.325171 L0:00000000
982 09:17:05.325618 L1:20000703
983 09:17:05.326029 L2:00008067
984 09:17:05.326432 L3:14000000
985 09:17:05.330728 B2:00402000
986 09:17:05.331168 B1:e0f83180
987 09:17:05.331575
988 09:17:05.332017 TE: 58167
989 09:17:05.332444
990 09:17:05.336422 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
991 09:17:05.336879
992 09:17:05.337290 Board ID = 1
993 09:17:05.342024 Set A53 clk to 24M
994 09:17:05.342471 Set A73 clk to 24M
995 09:17:05.342878 Set clk81 to 24M
996 09:17:05.347671 A53 clk: 1200 MHz
997 09:17:05.348132 A73 clk: 1200 MHz
998 09:17:05.348545 CLK81: 166.6M
999 09:17:05.348954 smccc: 00012abd
1000 09:17:05.353153 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
1001 09:17:05.358772 board id: 1
1002 09:17:05.363717 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
1003 09:17:05.375317 fw parse done
1004 09:17:05.380370 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
1005 09:17:05.423917 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
1006 09:17:05.434783 PIEI prepare done
1007 09:17:05.435291 fastboot data load
1008 09:17:05.435750 fastboot data verify
1009 09:17:05.440387 verify result: 266
1010 09:17:05.445978 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
1011 09:17:05.446435 LPDDR4 probe
1012 09:17:05.446855 ddr clk to 1584MHz
1013 09:17:05.453983 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
1014 09:17:05.491230
1015 09:17:05.491683 dmc_version 0001
1016 09:17:05.496954 Check phy result
1017 09:17:05.503781 INFO : End of CA training
1018 09:17:05.504301 INFO : End of initialization
1019 09:17:05.509368 INFO : Training has run successfully!
1020 09:17:05.509800 Check phy result
1021 09:17:05.514988 INFO : End of initialization
1022 09:17:05.515429 INFO : End of read enable training
1023 09:17:05.520588 INFO : End of fine write leveling
1024 09:17:05.526205 INFO : End of Write leveling coarse delay
1025 09:17:05.526631 INFO : Training has run successfully!
1026 09:17:05.527022 Check phy result
1027 09:17:05.531752 INFO : End of initialization
1028 09:17:05.532215 INFO : End of read dq deskew training
1029 09:17:05.537383 INFO : End of MPR read delay center optimization
1030 09:17:05.543133 INFO : End of write delay center optimization
1031 09:17:05.548617 INFO : End of read delay center optimization
1032 09:17:05.549037 INFO : End of max read latency training
1033 09:17:05.554520 INFO : Training has run successfully!
1034 09:17:05.554958 1D training succeed
1035 09:17:05.563590 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
1036 09:17:05.610310 Check phy result
1037 09:17:05.610739 INFO : End of initialization
1038 09:17:05.632058 INFO : End of 2D read delay Voltage center optimization
1039 09:17:05.651726 INFO : End of 2D read delay Voltage center optimization
1040 09:17:05.703793 INFO : End of 2D write delay Voltage center optimization
1041 09:17:05.753768 INFO : End of 2D write delay Voltage center optimization
1042 09:17:05.759357 INFO : Training has run successfully!
1043 09:17:05.759803
1044 09:17:05.760259 channel==0
1045 09:17:05.764979 RxClkDly_Margin_A0==88 ps 9
1046 09:17:05.765451 TxDqDly_Margin_A0==98 ps 10
1047 09:17:05.770552 RxClkDly_Margin_A1==88 ps 9
1048 09:17:05.771001 TxDqDly_Margin_A1==98 ps 10
1049 09:17:05.771412 TrainedVREFDQ_A0==74
1050 09:17:05.776229 TrainedVREFDQ_A1==74
1051 09:17:05.776665 VrefDac_Margin_A0==25
1052 09:17:05.777073 DeviceVref_Margin_A0==40
1053 09:17:05.781853 VrefDac_Margin_A1==25
1054 09:17:05.782285 DeviceVref_Margin_A1==40
1055 09:17:05.782688
1056 09:17:05.783090
1057 09:17:05.787378 channel==1
1058 09:17:05.787814 RxClkDly_Margin_A0==98 ps 10
1059 09:17:05.788254 TxDqDly_Margin_A0==88 ps 9
1060 09:17:05.792988 RxClkDly_Margin_A1==88 ps 9
1061 09:17:05.793429 TxDqDly_Margin_A1==88 ps 9
1062 09:17:05.798559 TrainedVREFDQ_A0==76
1063 09:17:05.798999 TrainedVREFDQ_A1==77
1064 09:17:05.799409 VrefDac_Margin_A0==22
1065 09:17:05.804220 DeviceVref_Margin_A0==38
1066 09:17:05.804657 VrefDac_Margin_A1==24
1067 09:17:05.809764 DeviceVref_Margin_A1==37
1068 09:17:05.810204
1069 09:17:05.810613 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
1070 09:17:05.811014
1071 09:17:05.843368 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000018 00000017 00000019 00000018 0000001a 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
1072 09:17:05.843877 2D training succeed
1073 09:17:05.848998 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
1074 09:17:05.854576 auto size-- 65535DDR cs0 size: 2048MB
1075 09:17:05.855033 DDR cs1 size: 2048MB
1076 09:17:05.860209 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
1077 09:17:05.860649 cs0 DataBus test pass
1078 09:17:05.865750 cs1 DataBus test pass
1079 09:17:05.866185 cs0 AddrBus test pass
1080 09:17:05.866589 cs1 AddrBus test pass
1081 09:17:05.866989
1082 09:17:05.871345 100bdlr_step_size ps== 420
1083 09:17:05.871794 result report
1084 09:17:05.876964 boot times 0Enable ddr reg access
1085 09:17:05.882433 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
1086 09:17:05.895699 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
1087 09:17:06.467711 0.0;M3 CHK:0;cm4_sp_mode 0
1088 09:17:06.468254 MVN_1=0x00000000
1089 09:17:06.473225 MVN_2=0x00000000
1090 09:17:06.479008 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
1091 09:17:06.479450 OPS=0x10
1092 09:17:06.479863 ring efuse init
1093 09:17:06.480304 chipver efuse init
1094 09:17:06.484639 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
1095 09:17:06.490156 [0.018961 Inits done]
1096 09:17:06.490592 secure task start!
1097 09:17:06.491000 high task start!
1098 09:17:06.494773 low task start!
1099 09:17:06.495201 run into bl31
1100 09:17:06.501460 NOTICE: BL31: v1.3(release):4fc40b1
1101 09:17:06.509255 NOTICE: BL31: Built : 15:58:17, May 22 2019
1102 09:17:06.509706 NOTICE: BL31: G12A normal boot!
1103 09:17:06.534598 NOTICE: BL31: BL33 decompress pass
1104 09:17:06.540394 ERROR: Error initializing runtime service opteed_fast
1105 09:17:07.773259
1106 09:17:07.773787
1107 09:17:07.781734 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
1108 09:17:07.782179
1109 09:17:07.782595 Model: Libre Computer AML-A311D-CC Alta
1110 09:17:07.989133 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
1111 09:17:08.013436 DRAM: 2 GiB (effective 3.8 GiB)
1112 09:17:08.156390 Core: 408 devices, 31 uclasses, devicetree: separate
1113 09:17:08.162292 WDT: Not starting watchdog@f0d0
1114 09:17:08.194531 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
1115 09:17:08.207032 Loading Environment from FAT... Card did not respond to voltage select! : -110
1116 09:17:08.211006 ** Bad device specification mmc 0 **
1117 09:17:08.222287 Card did not respond to voltage select! : -110
1118 09:17:08.229949 ** Bad device specification mmc 0 **
1119 09:17:08.230385 Couldn't find partition mmc 0
1120 09:17:08.238287 Card did not respond to voltage select! : -110
1121 09:17:08.243799 ** Bad device specification mmc 0 **
1122 09:17:08.244288 Couldn't find partition mmc 0
1123 09:17:08.248152 Error: could not access storage.
1124 09:17:08.591356 Net: eth0: ethernet@ff3f0000
1125 09:17:08.591847 starting USB...
1126 09:17:08.843137 Bus usb@ff500000: Register 3000140 NbrPorts 3
1127 09:17:08.843641 Starting the controller
1128 09:17:08.850072 USB XHCI 1.10
1129 09:17:10.404187 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
1130 09:17:10.412475 scanning usb for storage devices... 0 Storage Device(s) found
1132 09:17:10.464134 Hit any key to stop autoboot: 1
1133 09:17:10.465003 end: 2.4.2 bootloader-interrupt (duration 00:00:37) [common]
1134 09:17:10.465643 start: 2.4.3 bootloader-commands (timeout 00:04:23) [common]
1135 09:17:10.466179 Setting prompt string to ['=>']
1136 09:17:10.466734 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:23)
1137 09:17:10.479930 0
1138 09:17:10.480889 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1139 09:17:10.481443 Sending with 10 millisecond of delay
1141 09:17:11.616547 => setenv autoload no
1142 09:17:11.628279 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:22)
1143 09:17:11.634278 setenv autoload no
1144 09:17:11.635169 Sending with 10 millisecond of delay
1146 09:17:13.433214 => setenv initrd_high 0xffffffff
1147 09:17:13.444085 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:20)
1148 09:17:13.445103 setenv initrd_high 0xffffffff
1149 09:17:13.445832 Sending with 10 millisecond of delay
1151 09:17:15.062026 => setenv fdt_high 0xffffffff
1152 09:17:15.072812 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:19)
1153 09:17:15.073607 setenv fdt_high 0xffffffff
1154 09:17:15.074315 Sending with 10 millisecond of delay
1156 09:17:15.366074 => dhcp
1157 09:17:15.376834 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1158 09:17:15.377645 dhcp
1159 09:17:15.378087 Speed: 1000, full duplex
1160 09:17:15.378504 BOOTP broadcast 1
1161 09:17:15.389178 DHCP client bound to address 192.168.6.27 (12 ms)
1162 09:17:15.389894 Sending with 10 millisecond of delay
1164 09:17:17.066229 => setenv serverip 192.168.6.2
1165 09:17:17.077042 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:17)
1166 09:17:17.077932 setenv serverip 192.168.6.2
1167 09:17:17.078624 Sending with 10 millisecond of delay
1169 09:17:20.801383 => tftpboot 0x01080000 944985/tftp-deploy-0hpn_6_b/kernel/uImage
1170 09:17:20.812071 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:13)
1171 09:17:20.812555 tftpboot 0x01080000 944985/tftp-deploy-0hpn_6_b/kernel/uImage
1172 09:17:20.812799 Speed: 1000, full duplex
1173 09:17:20.813004 Using ethernet@ff3f0000 device
1174 09:17:20.814406 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1175 09:17:20.819913 Filename '944985/tftp-deploy-0hpn_6_b/kernel/uImage'.
1176 09:17:20.823771 Load address: 0x1080000
1177 09:17:21.136743 Loading: *##### UDP wrong checksum 000000ff 00003037
1178 09:17:21.284577 ## UDP wrong checksum 000000ff 0000c929
1179 09:17:23.224391 ################################### UDP wrong checksum 000000ff 0000d2a7
1180 09:17:23.274058 # UDP wrong checksum 000000ff 00005d9a
1181 09:17:23.641337 ####### 43.9 MiB
1182 09:17:23.641738 15.6 MiB/s
1183 09:17:23.641954 done
1184 09:17:23.645742 Bytes transferred = 46041664 (2be8a40 hex)
1185 09:17:23.646366 Sending with 10 millisecond of delay
1187 09:17:28.331872 => tftpboot 0x08000000 944985/tftp-deploy-0hpn_6_b/ramdisk/ramdisk.cpio.gz.uboot
1188 09:17:28.342649 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:05)
1189 09:17:28.343449 tftpboot 0x08000000 944985/tftp-deploy-0hpn_6_b/ramdisk/ramdisk.cpio.gz.uboot
1190 09:17:28.343867 Speed: 1000, full duplex
1191 09:17:28.344315 Using ethernet@ff3f0000 device
1192 09:17:28.345453 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1193 09:17:28.354062 Filename '944985/tftp-deploy-0hpn_6_b/ramdisk/ramdisk.cpio.gz.uboot'.
1194 09:17:28.354554 Load address: 0x8000000
1195 09:17:35.052623 Loading: *##########################T ####################### UDP wrong checksum 00000005 0000f726
1196 09:17:36.986811 UDP wrong checksum 000000ff 0000bb40
1197 09:17:37.034803 UDP wrong checksum 000000ff 00004733
1198 09:17:40.051746 T UDP wrong checksum 00000005 0000f726
1199 09:17:43.549717 UDP wrong checksum 000000ff 000045fa
1200 09:17:43.556759 UDP wrong checksum 000000ff 0000d3ec
1201 09:17:50.053101 T UDP wrong checksum 00000005 0000f726
1202 09:17:53.147943 T UDP wrong checksum 000000ff 00000186
1203 09:17:53.194718 UDP wrong checksum 000000ff 00009478
1204 09:18:03.315744 T T UDP wrong checksum 000000ff 0000741c
1205 09:18:03.337236 UDP wrong checksum 000000ff 00000b0f
1206 09:18:10.057050 T UDP wrong checksum 00000005 0000f726
1207 09:18:10.446599 T UDP wrong checksum 000000ff 00001512
1208 09:18:10.493660 UDP wrong checksum 000000ff 00009e04
1209 09:18:25.062184 T T
1210 09:18:25.062775 Retry count exceeded; starting again
1212 09:18:25.064255 end: 2.4.3 bootloader-commands (duration 00:01:15) [common]
1215 09:18:25.066136 end: 2.4 uboot-commands (duration 00:01:51) [common]
1217 09:18:25.067521 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
1219 09:18:25.068617 end: 2 uboot-action (duration 00:01:51) [common]
1221 09:18:25.070117 Cleaning after the job
1222 09:18:25.070653 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/944985/tftp-deploy-0hpn_6_b/ramdisk
1223 09:18:25.071904 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/944985/tftp-deploy-0hpn_6_b/kernel
1224 09:18:25.100877 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/944985/tftp-deploy-0hpn_6_b/dtb
1225 09:18:25.102081 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/944985/tftp-deploy-0hpn_6_b/nfsrootfs
1226 09:18:25.132648 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/944985/tftp-deploy-0hpn_6_b/modules
1227 09:18:25.139340 start: 4.1 power-off (timeout 00:00:30) [common]
1228 09:18:25.139915 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1229 09:18:25.173340 >> OK - accepted request
1230 09:18:25.175120 Returned 0 in 0 seconds
1231 09:18:25.276106 end: 4.1 power-off (duration 00:00:00) [common]
1233 09:18:25.277025 start: 4.2 read-feedback (timeout 00:10:00) [common]
1234 09:18:25.277677 Listened to connection for namespace 'common' for up to 1s
1235 09:18:26.278746 Finalising connection for namespace 'common'
1236 09:18:26.279274 Disconnecting from shell: Finalise
1237 09:18:26.279585 =>
1238 09:18:26.380287 end: 4.2 read-feedback (duration 00:00:01) [common]
1239 09:18:26.380754 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/944985
1240 09:18:30.041687 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/944985
1241 09:18:30.042421 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.