Boot log: beaglebone-black
- Warnings: 2
- Kernel Warnings: 15
- Errors: 0
- Boot result: PASS
- Kernel Errors: 10
1 14:00:32.991485 lava-dispatcher, installed at version: 2024.01
2 14:00:32.992279 start: 0 validate
3 14:00:32.992745 Start time: 2024-11-07 14:00:32.992714+00:00 (UTC)
4 14:00:32.993309 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 14:00:32.993842 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farmhf%2Finitrd.cpio.gz exists
6 14:00:33.030239 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 14:00:33.030775 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241107%2Farm%2Fmulti_v7_defconfig%2Fgcc-12%2Fkernel%2FzImage exists
8 14:00:33.063917 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 14:00:33.064569 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241107%2Farm%2Fmulti_v7_defconfig%2Fgcc-12%2Fdtbs%2Fti%2Fomap%2Fam335x-boneblack.dtb exists
10 14:00:34.111337 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 14:00:34.111871 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farmhf%2Ffull.rootfs.tar.xz exists
12 14:00:34.141790 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 14:00:34.142289 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241107%2Farm%2Fmulti_v7_defconfig%2Fgcc-12%2Fmodules.tar.xz exists
14 14:00:34.183606 validate duration: 1.19
16 14:00:34.185359 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 14:00:34.186028 start: 1.1 download-retry (timeout 00:10:00) [common]
18 14:00:34.186675 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 14:00:34.187756 Not decompressing ramdisk as can be used compressed.
20 14:00:34.188625 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/initrd.cpio.gz
21 14:00:34.189185 saving as /var/lib/lava/dispatcher/tmp/952823/tftp-deploy-qdpf9fzo/ramdisk/initrd.cpio.gz
22 14:00:34.189752 total size: 4775763 (4 MB)
23 14:00:34.228765 progress 0 % (0 MB)
24 14:00:34.236310 progress 5 % (0 MB)
25 14:00:34.243648 progress 10 % (0 MB)
26 14:00:34.250737 progress 15 % (0 MB)
27 14:00:34.258528 progress 20 % (0 MB)
28 14:00:34.264578 progress 25 % (1 MB)
29 14:00:34.267967 progress 30 % (1 MB)
30 14:00:34.271733 progress 35 % (1 MB)
31 14:00:34.275009 progress 40 % (1 MB)
32 14:00:34.278360 progress 45 % (2 MB)
33 14:00:34.281651 progress 50 % (2 MB)
34 14:00:34.285405 progress 55 % (2 MB)
35 14:00:34.288667 progress 60 % (2 MB)
36 14:00:34.291942 progress 65 % (2 MB)
37 14:00:34.295685 progress 70 % (3 MB)
38 14:00:34.298960 progress 75 % (3 MB)
39 14:00:34.302203 progress 80 % (3 MB)
40 14:00:34.305601 progress 85 % (3 MB)
41 14:00:34.309361 progress 90 % (4 MB)
42 14:00:34.312325 progress 95 % (4 MB)
43 14:00:34.315231 progress 100 % (4 MB)
44 14:00:34.315866 4 MB downloaded in 0.13 s (36.12 MB/s)
45 14:00:34.316427 end: 1.1.1 http-download (duration 00:00:00) [common]
47 14:00:34.317316 end: 1.1 download-retry (duration 00:00:00) [common]
48 14:00:34.317602 start: 1.2 download-retry (timeout 00:10:00) [common]
49 14:00:34.317868 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 14:00:34.318379 downloading http://storage.kernelci.org/next/master/next-20241107/arm/multi_v7_defconfig/gcc-12/kernel/zImage
51 14:00:34.318629 saving as /var/lib/lava/dispatcher/tmp/952823/tftp-deploy-qdpf9fzo/kernel/zImage
52 14:00:34.318833 total size: 11510272 (10 MB)
53 14:00:34.319044 No compression specified
54 14:00:34.362645 progress 0 % (0 MB)
55 14:00:34.370351 progress 5 % (0 MB)
56 14:00:34.378229 progress 10 % (1 MB)
57 14:00:34.385591 progress 15 % (1 MB)
58 14:00:34.393469 progress 20 % (2 MB)
59 14:00:34.401070 progress 25 % (2 MB)
60 14:00:34.408874 progress 30 % (3 MB)
61 14:00:34.416153 progress 35 % (3 MB)
62 14:00:34.424068 progress 40 % (4 MB)
63 14:00:34.431852 progress 45 % (4 MB)
64 14:00:34.439221 progress 50 % (5 MB)
65 14:00:34.447103 progress 55 % (6 MB)
66 14:00:34.454499 progress 60 % (6 MB)
67 14:00:34.462242 progress 65 % (7 MB)
68 14:00:34.469601 progress 70 % (7 MB)
69 14:00:34.477318 progress 75 % (8 MB)
70 14:00:34.485092 progress 80 % (8 MB)
71 14:00:34.492476 progress 85 % (9 MB)
72 14:00:34.500429 progress 90 % (9 MB)
73 14:00:34.507773 progress 95 % (10 MB)
74 14:00:34.514887 progress 100 % (10 MB)
75 14:00:34.515411 10 MB downloaded in 0.20 s (55.84 MB/s)
76 14:00:34.515879 end: 1.2.1 http-download (duration 00:00:00) [common]
78 14:00:34.516723 end: 1.2 download-retry (duration 00:00:00) [common]
79 14:00:34.516999 start: 1.3 download-retry (timeout 00:10:00) [common]
80 14:00:34.517262 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 14:00:34.517734 downloading http://storage.kernelci.org/next/master/next-20241107/arm/multi_v7_defconfig/gcc-12/dtbs/ti/omap/am335x-boneblack.dtb
82 14:00:34.517975 saving as /var/lib/lava/dispatcher/tmp/952823/tftp-deploy-qdpf9fzo/dtb/am335x-boneblack.dtb
83 14:00:34.518180 total size: 70544 (0 MB)
84 14:00:34.518389 No compression specified
85 14:00:34.553202 progress 46 % (0 MB)
86 14:00:34.554029 progress 92 % (0 MB)
87 14:00:34.554708 progress 100 % (0 MB)
88 14:00:34.555096 0 MB downloaded in 0.04 s (1.82 MB/s)
89 14:00:34.555550 end: 1.3.1 http-download (duration 00:00:00) [common]
91 14:00:34.556407 end: 1.3 download-retry (duration 00:00:00) [common]
92 14:00:34.556672 start: 1.4 download-retry (timeout 00:10:00) [common]
93 14:00:34.556934 start: 1.4.1 http-download (timeout 00:10:00) [common]
94 14:00:34.557393 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/full.rootfs.tar.xz
95 14:00:34.557628 saving as /var/lib/lava/dispatcher/tmp/952823/tftp-deploy-qdpf9fzo/nfsrootfs/full.rootfs.tar
96 14:00:34.557831 total size: 117747780 (112 MB)
97 14:00:34.558039 Using unxz to decompress xz
98 14:00:34.597784 progress 0 % (0 MB)
99 14:00:35.328142 progress 5 % (5 MB)
100 14:00:36.081476 progress 10 % (11 MB)
101 14:00:36.853339 progress 15 % (16 MB)
102 14:00:37.576886 progress 20 % (22 MB)
103 14:00:38.174380 progress 25 % (28 MB)
104 14:00:38.985383 progress 30 % (33 MB)
105 14:00:39.911273 progress 35 % (39 MB)
106 14:00:40.305402 progress 40 % (44 MB)
107 14:00:40.699664 progress 45 % (50 MB)
108 14:00:41.369678 progress 50 % (56 MB)
109 14:00:42.203337 progress 55 % (61 MB)
110 14:00:42.990963 progress 60 % (67 MB)
111 14:00:43.715512 progress 65 % (73 MB)
112 14:00:44.483607 progress 70 % (78 MB)
113 14:00:45.249614 progress 75 % (84 MB)
114 14:00:45.986621 progress 80 % (89 MB)
115 14:00:46.700326 progress 85 % (95 MB)
116 14:00:47.490680 progress 90 % (101 MB)
117 14:00:48.263446 progress 95 % (106 MB)
118 14:00:49.076845 progress 100 % (112 MB)
119 14:00:49.089215 112 MB downloaded in 14.53 s (7.73 MB/s)
120 14:00:49.089814 end: 1.4.1 http-download (duration 00:00:15) [common]
122 14:00:49.090639 end: 1.4 download-retry (duration 00:00:15) [common]
123 14:00:49.090901 start: 1.5 download-retry (timeout 00:09:45) [common]
124 14:00:49.091158 start: 1.5.1 http-download (timeout 00:09:45) [common]
125 14:00:49.091629 downloading http://storage.kernelci.org/next/master/next-20241107/arm/multi_v7_defconfig/gcc-12/modules.tar.xz
126 14:00:49.091869 saving as /var/lib/lava/dispatcher/tmp/952823/tftp-deploy-qdpf9fzo/modules/modules.tar
127 14:00:49.092243 total size: 6626732 (6 MB)
128 14:00:49.092657 Using unxz to decompress xz
129 14:00:49.140034 progress 0 % (0 MB)
130 14:00:49.175074 progress 5 % (0 MB)
131 14:00:49.217965 progress 10 % (0 MB)
132 14:00:49.261163 progress 15 % (0 MB)
133 14:00:49.304747 progress 20 % (1 MB)
134 14:00:49.352378 progress 25 % (1 MB)
135 14:00:49.396310 progress 30 % (1 MB)
136 14:00:49.439396 progress 35 % (2 MB)
137 14:00:49.483157 progress 40 % (2 MB)
138 14:00:49.531368 progress 45 % (2 MB)
139 14:00:49.575452 progress 50 % (3 MB)
140 14:00:49.618071 progress 55 % (3 MB)
141 14:00:49.663940 progress 60 % (3 MB)
142 14:00:49.706665 progress 65 % (4 MB)
143 14:00:49.749979 progress 70 % (4 MB)
144 14:00:49.795707 progress 75 % (4 MB)
145 14:00:49.838659 progress 80 % (5 MB)
146 14:00:49.881341 progress 85 % (5 MB)
147 14:00:49.928958 progress 90 % (5 MB)
148 14:00:49.972363 progress 95 % (6 MB)
149 14:00:50.016307 progress 100 % (6 MB)
150 14:00:50.027691 6 MB downloaded in 0.94 s (6.76 MB/s)
151 14:00:50.028470 end: 1.5.1 http-download (duration 00:00:01) [common]
153 14:00:50.030072 end: 1.5 download-retry (duration 00:00:01) [common]
154 14:00:50.030587 start: 1.6 prepare-tftp-overlay (timeout 00:09:44) [common]
155 14:00:50.031095 start: 1.6.1 extract-nfsrootfs (timeout 00:09:44) [common]
156 14:01:06.873640 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/952823/extract-nfsrootfs-u9sj1r2q
157 14:01:06.874259 end: 1.6.1 extract-nfsrootfs (duration 00:00:17) [common]
158 14:01:06.874555 start: 1.6.2 lava-overlay (timeout 00:09:27) [common]
159 14:01:06.875264 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/952823/lava-overlay-w_u6u8i6
160 14:01:06.875748 makedir: /var/lib/lava/dispatcher/tmp/952823/lava-overlay-w_u6u8i6/lava-952823/bin
161 14:01:06.876126 makedir: /var/lib/lava/dispatcher/tmp/952823/lava-overlay-w_u6u8i6/lava-952823/tests
162 14:01:06.876535 makedir: /var/lib/lava/dispatcher/tmp/952823/lava-overlay-w_u6u8i6/lava-952823/results
163 14:01:06.876901 Creating /var/lib/lava/dispatcher/tmp/952823/lava-overlay-w_u6u8i6/lava-952823/bin/lava-add-keys
164 14:01:06.877455 Creating /var/lib/lava/dispatcher/tmp/952823/lava-overlay-w_u6u8i6/lava-952823/bin/lava-add-sources
165 14:01:06.877980 Creating /var/lib/lava/dispatcher/tmp/952823/lava-overlay-w_u6u8i6/lava-952823/bin/lava-background-process-start
166 14:01:06.878491 Creating /var/lib/lava/dispatcher/tmp/952823/lava-overlay-w_u6u8i6/lava-952823/bin/lava-background-process-stop
167 14:01:06.879028 Creating /var/lib/lava/dispatcher/tmp/952823/lava-overlay-w_u6u8i6/lava-952823/bin/lava-common-functions
168 14:01:06.879554 Creating /var/lib/lava/dispatcher/tmp/952823/lava-overlay-w_u6u8i6/lava-952823/bin/lava-echo-ipv4
169 14:01:06.880149 Creating /var/lib/lava/dispatcher/tmp/952823/lava-overlay-w_u6u8i6/lava-952823/bin/lava-install-packages
170 14:01:06.880685 Creating /var/lib/lava/dispatcher/tmp/952823/lava-overlay-w_u6u8i6/lava-952823/bin/lava-installed-packages
171 14:01:06.881249 Creating /var/lib/lava/dispatcher/tmp/952823/lava-overlay-w_u6u8i6/lava-952823/bin/lava-os-build
172 14:01:06.881952 Creating /var/lib/lava/dispatcher/tmp/952823/lava-overlay-w_u6u8i6/lava-952823/bin/lava-probe-channel
173 14:01:06.882520 Creating /var/lib/lava/dispatcher/tmp/952823/lava-overlay-w_u6u8i6/lava-952823/bin/lava-probe-ip
174 14:01:06.883026 Creating /var/lib/lava/dispatcher/tmp/952823/lava-overlay-w_u6u8i6/lava-952823/bin/lava-target-ip
175 14:01:06.883543 Creating /var/lib/lava/dispatcher/tmp/952823/lava-overlay-w_u6u8i6/lava-952823/bin/lava-target-mac
176 14:01:06.884260 Creating /var/lib/lava/dispatcher/tmp/952823/lava-overlay-w_u6u8i6/lava-952823/bin/lava-target-storage
177 14:01:06.884805 Creating /var/lib/lava/dispatcher/tmp/952823/lava-overlay-w_u6u8i6/lava-952823/bin/lava-test-case
178 14:01:06.885321 Creating /var/lib/lava/dispatcher/tmp/952823/lava-overlay-w_u6u8i6/lava-952823/bin/lava-test-event
179 14:01:06.885823 Creating /var/lib/lava/dispatcher/tmp/952823/lava-overlay-w_u6u8i6/lava-952823/bin/lava-test-feedback
180 14:01:06.886334 Creating /var/lib/lava/dispatcher/tmp/952823/lava-overlay-w_u6u8i6/lava-952823/bin/lava-test-raise
181 14:01:06.886838 Creating /var/lib/lava/dispatcher/tmp/952823/lava-overlay-w_u6u8i6/lava-952823/bin/lava-test-reference
182 14:01:06.887353 Creating /var/lib/lava/dispatcher/tmp/952823/lava-overlay-w_u6u8i6/lava-952823/bin/lava-test-runner
183 14:01:06.887878 Creating /var/lib/lava/dispatcher/tmp/952823/lava-overlay-w_u6u8i6/lava-952823/bin/lava-test-set
184 14:01:06.888423 Creating /var/lib/lava/dispatcher/tmp/952823/lava-overlay-w_u6u8i6/lava-952823/bin/lava-test-shell
185 14:01:06.888938 Updating /var/lib/lava/dispatcher/tmp/952823/lava-overlay-w_u6u8i6/lava-952823/bin/lava-add-keys (debian)
186 14:01:06.889659 Updating /var/lib/lava/dispatcher/tmp/952823/lava-overlay-w_u6u8i6/lava-952823/bin/lava-add-sources (debian)
187 14:01:06.890275 Updating /var/lib/lava/dispatcher/tmp/952823/lava-overlay-w_u6u8i6/lava-952823/bin/lava-install-packages (debian)
188 14:01:06.890889 Updating /var/lib/lava/dispatcher/tmp/952823/lava-overlay-w_u6u8i6/lava-952823/bin/lava-installed-packages (debian)
189 14:01:06.891432 Updating /var/lib/lava/dispatcher/tmp/952823/lava-overlay-w_u6u8i6/lava-952823/bin/lava-os-build (debian)
190 14:01:06.891891 Creating /var/lib/lava/dispatcher/tmp/952823/lava-overlay-w_u6u8i6/lava-952823/environment
191 14:01:06.892345 LAVA metadata
192 14:01:06.892617 - LAVA_JOB_ID=952823
193 14:01:06.892834 - LAVA_DISPATCHER_IP=192.168.6.2
194 14:01:06.893221 start: 1.6.2.1 ssh-authorize (timeout 00:09:27) [common]
195 14:01:06.894295 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
196 14:01:06.894638 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:27) [common]
197 14:01:06.894848 skipped lava-vland-overlay
198 14:01:06.895089 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
199 14:01:06.895343 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:27) [common]
200 14:01:06.895565 skipped lava-multinode-overlay
201 14:01:06.895808 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
202 14:01:06.896105 start: 1.6.2.4 test-definition (timeout 00:09:27) [common]
203 14:01:06.896373 Loading test definitions
204 14:01:06.896657 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:27) [common]
205 14:01:06.896876 Using /lava-952823 at stage 0
206 14:01:06.898012 uuid=952823_1.6.2.4.1 testdef=None
207 14:01:06.898337 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
208 14:01:06.898604 start: 1.6.2.4.2 test-overlay (timeout 00:09:27) [common]
209 14:01:06.900258 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
211 14:01:06.901076 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:27) [common]
212 14:01:06.903114 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
214 14:01:06.903973 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:27) [common]
215 14:01:06.905931 runner path: /var/lib/lava/dispatcher/tmp/952823/lava-overlay-w_u6u8i6/lava-952823/0/tests/0_timesync-off test_uuid 952823_1.6.2.4.1
216 14:01:06.906577 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
218 14:01:06.907429 start: 1.6.2.4.5 git-repo-action (timeout 00:09:27) [common]
219 14:01:06.907658 Using /lava-952823 at stage 0
220 14:01:06.908077 Fetching tests from https://github.com/kernelci/test-definitions.git
221 14:01:06.908392 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/952823/lava-overlay-w_u6u8i6/lava-952823/0/tests/1_kselftest-dt'
222 14:01:10.417827 Running '/usr/bin/git checkout kernelci.org
223 14:01:10.755471 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/952823/lava-overlay-w_u6u8i6/lava-952823/0/tests/1_kselftest-dt/automated/linux/kselftest/kselftest.yaml
224 14:01:10.756954 uuid=952823_1.6.2.4.5 testdef=None
225 14:01:10.757305 end: 1.6.2.4.5 git-repo-action (duration 00:00:04) [common]
227 14:01:10.758047 start: 1.6.2.4.6 test-overlay (timeout 00:09:23) [common]
228 14:01:10.760895 end: 1.6.2.4.6 test-overlay (duration 00:00:00) [common]
230 14:01:10.761710 start: 1.6.2.4.7 test-install-overlay (timeout 00:09:23) [common]
231 14:01:10.765441 end: 1.6.2.4.7 test-install-overlay (duration 00:00:00) [common]
233 14:01:10.766300 start: 1.6.2.4.8 test-runscript-overlay (timeout 00:09:23) [common]
234 14:01:10.769901 runner path: /var/lib/lava/dispatcher/tmp/952823/lava-overlay-w_u6u8i6/lava-952823/0/tests/1_kselftest-dt test_uuid 952823_1.6.2.4.5
235 14:01:10.770190 BOARD='beaglebone-black'
236 14:01:10.770395 BRANCH='next'
237 14:01:10.770591 SKIPFILE='/dev/null'
238 14:01:10.770787 SKIP_INSTALL='True'
239 14:01:10.770981 TESTPROG_URL='http://storage.kernelci.org/next/master/next-20241107/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz'
240 14:01:10.771177 TST_CASENAME=''
241 14:01:10.771370 TST_CMDFILES='dt'
242 14:01:10.771923 end: 1.6.2.4.8 test-runscript-overlay (duration 00:00:00) [common]
244 14:01:10.772733 Creating lava-test-runner.conf files
245 14:01:10.772939 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/952823/lava-overlay-w_u6u8i6/lava-952823/0 for stage 0
246 14:01:10.773388 - 0_timesync-off
247 14:01:10.773643 - 1_kselftest-dt
248 14:01:10.773977 end: 1.6.2.4 test-definition (duration 00:00:04) [common]
249 14:01:10.774261 start: 1.6.2.5 compress-overlay (timeout 00:09:23) [common]
250 14:01:34.311741 end: 1.6.2.5 compress-overlay (duration 00:00:24) [common]
251 14:01:34.312183 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:09:00) [common]
252 14:01:34.312449 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
253 14:01:34.312717 end: 1.6.2 lava-overlay (duration 00:00:27) [common]
254 14:01:34.312981 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:00) [common]
255 14:01:34.674108 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
256 14:01:34.674588 start: 1.6.4 extract-modules (timeout 00:09:00) [common]
257 14:01:34.674855 extracting modules file /var/lib/lava/dispatcher/tmp/952823/tftp-deploy-qdpf9fzo/modules/modules.tar to /var/lib/lava/dispatcher/tmp/952823/extract-nfsrootfs-u9sj1r2q
258 14:01:35.550040 extracting modules file /var/lib/lava/dispatcher/tmp/952823/tftp-deploy-qdpf9fzo/modules/modules.tar to /var/lib/lava/dispatcher/tmp/952823/extract-overlay-ramdisk-8mrbcetg/ramdisk
259 14:01:36.455676 end: 1.6.4 extract-modules (duration 00:00:02) [common]
260 14:01:36.456164 start: 1.6.5 apply-overlay-tftp (timeout 00:08:58) [common]
261 14:01:36.456450 [common] Applying overlay to NFS
262 14:01:36.456666 [common] Applying overlay /var/lib/lava/dispatcher/tmp/952823/compress-overlay-p146zgrn/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/952823/extract-nfsrootfs-u9sj1r2q
263 14:01:39.195967 end: 1.6.5 apply-overlay-tftp (duration 00:00:03) [common]
264 14:01:39.196474 start: 1.6.6 prepare-kernel (timeout 00:08:55) [common]
265 14:01:39.196747 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:08:55) [common]
266 14:01:39.197023 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
267 14:01:39.197275 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
268 14:01:39.197531 start: 1.6.7 configure-preseed-file (timeout 00:08:55) [common]
269 14:01:39.197780 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
270 14:01:39.198031 start: 1.6.8 compress-ramdisk (timeout 00:08:55) [common]
271 14:01:39.198281 Building ramdisk /var/lib/lava/dispatcher/tmp/952823/extract-overlay-ramdisk-8mrbcetg/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/952823/extract-overlay-ramdisk-8mrbcetg/ramdisk
272 14:01:40.205283 >> 75307 blocks
273 14:01:44.813077 Adding RAMdisk u-boot header.
274 14:01:44.813532 mkimage -A arm -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/952823/extract-overlay-ramdisk-8mrbcetg/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/952823/extract-overlay-ramdisk-8mrbcetg/ramdisk.cpio.gz.uboot
275 14:01:45.016417 output: Image Name:
276 14:01:45.016847 output: Created: Thu Nov 7 14:01:44 2024
277 14:01:45.017061 output: Image Type: ARM Linux RAMDisk Image (uncompressed)
278 14:01:45.017266 output: Data Size: 14830444 Bytes = 14482.86 KiB = 14.14 MiB
279 14:01:45.017467 output: Load Address: 00000000
280 14:01:45.017668 output: Entry Point: 00000000
281 14:01:45.017866 output:
282 14:01:45.018667 rename /var/lib/lava/dispatcher/tmp/952823/extract-overlay-ramdisk-8mrbcetg/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/952823/tftp-deploy-qdpf9fzo/ramdisk/ramdisk.cpio.gz.uboot
283 14:01:45.019113 end: 1.6.8 compress-ramdisk (duration 00:00:06) [common]
284 14:01:45.019414 end: 1.6 prepare-tftp-overlay (duration 00:00:55) [common]
285 14:01:45.019702 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:49) [common]
286 14:01:45.019971 No LXC device requested
287 14:01:45.020536 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
288 14:01:45.021066 start: 1.8 deploy-device-env (timeout 00:08:49) [common]
289 14:01:45.021564 end: 1.8 deploy-device-env (duration 00:00:00) [common]
290 14:01:45.021974 Checking files for TFTP limit of 4294967296 bytes.
291 14:01:45.024652 end: 1 tftp-deploy (duration 00:01:11) [common]
292 14:01:45.025235 start: 2 uboot-action (timeout 00:05:00) [common]
293 14:01:45.025757 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
294 14:01:45.026253 end: 2.1 uboot-from-media (duration 00:00:00) [common]
295 14:01:45.026751 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
296 14:01:45.027498 substitutions:
297 14:01:45.027918 - {BOOTX}: bootz 0x82000000 0x83000000 0x88000000
298 14:01:45.028359 - {DTB_ADDR}: 0x88000000
299 14:01:45.028759 - {DTB}: 952823/tftp-deploy-qdpf9fzo/dtb/am335x-boneblack.dtb
300 14:01:45.029153 - {INITRD}: 952823/tftp-deploy-qdpf9fzo/ramdisk/ramdisk.cpio.gz.uboot
301 14:01:45.029546 - {KERNEL_ADDR}: 0x82000000
302 14:01:45.029935 - {KERNEL}: 952823/tftp-deploy-qdpf9fzo/kernel/zImage
303 14:01:45.030328 - {LAVA_MAC}: None
304 14:01:45.030763 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/952823/extract-nfsrootfs-u9sj1r2q
305 14:01:45.031161 - {NFS_SERVER_IP}: 192.168.6.2
306 14:01:45.031554 - {PRESEED_CONFIG}: None
307 14:01:45.031943 - {PRESEED_LOCAL}: None
308 14:01:45.032368 - {RAMDISK_ADDR}: 0x83000000
309 14:01:45.032759 - {RAMDISK}: 952823/tftp-deploy-qdpf9fzo/ramdisk/ramdisk.cpio.gz.uboot
310 14:01:45.033153 - {ROOT_PART}: None
311 14:01:45.033539 - {ROOT}: None
312 14:01:45.033924 - {SERVER_IP}: 192.168.6.2
313 14:01:45.034308 - {TEE_ADDR}: 0x83000000
314 14:01:45.034690 - {TEE}: None
315 14:01:45.035072 Parsed boot commands:
316 14:01:45.035444 - setenv autoload no
317 14:01:45.035825 - setenv initrd_high 0xffffffff
318 14:01:45.036237 - setenv fdt_high 0xffffffff
319 14:01:45.036619 - dhcp
320 14:01:45.036998 - setenv serverip 192.168.6.2
321 14:01:45.037377 - tftp 0x82000000 952823/tftp-deploy-qdpf9fzo/kernel/zImage
322 14:01:45.037759 - tftp 0x83000000 952823/tftp-deploy-qdpf9fzo/ramdisk/ramdisk.cpio.gz.uboot
323 14:01:45.038140 - setenv initrd_size ${filesize}
324 14:01:45.038517 - tftp 0x88000000 952823/tftp-deploy-qdpf9fzo/dtb/am335x-boneblack.dtb
325 14:01:45.038902 - setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/952823/extract-nfsrootfs-u9sj1r2q,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
326 14:01:45.039294 - bootz 0x82000000 0x83000000 0x88000000
327 14:01:45.039788 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
329 14:01:45.041291 start: 2.3 connect-device (timeout 00:05:00) [common]
330 14:01:45.041711 [common] connect-device Connecting to device using 'telnet conserv1 3003'
331 14:01:45.057049 Setting prompt string to ['lava-test: # ']
332 14:01:45.058555 end: 2.3 connect-device (duration 00:00:00) [common]
333 14:01:45.059160 start: 2.4 uboot-commands (timeout 00:05:00) [common]
334 14:01:45.059871 start: 2.4.1 reset-device (timeout 00:05:00) [common]
335 14:01:45.060478 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
336 14:01:45.061653 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=beaglebone-black-01'
337 14:01:45.099315 >> OK - accepted request
338 14:01:45.101624 Returned 0 in 0 seconds
339 14:01:45.202711 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
341 14:01:45.204408 end: 2.4.1 reset-device (duration 00:00:00) [common]
342 14:01:45.204954 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
343 14:01:45.205444 Setting prompt string to ['Hit any key to stop autoboot']
344 14:01:45.205893 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
345 14:01:45.207449 Trying 192.168.56.21...
346 14:01:45.207916 Connected to conserv1.
347 14:01:45.208348 Escape character is '^]'.
348 14:01:45.208747
349 14:01:45.209156 ser2net port telnet,3003 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.2.3:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
350 14:01:45.209556
351 14:01:53.706010
352 14:01:53.706617 U-Boot SPL 2022.07-rc3-dirty (May 24 2022 - 12:39:48 +0100)
353 14:01:53.710048 Trying to boot from MMC1
354 14:01:54.283552
355 14:01:54.283949
356 14:01:54.284230 U-Boot 2022.07-rc3-dirty (May 24 2022 - 12:39:48 +0100)
357 14:01:54.284467
358 14:01:54.288958 CPU : AM335X-GP rev 2.1
359 14:01:54.289255 Model: TI AM335x BeagleBone Black
360 14:01:54.293109 DRAM: 512 MiB
361 14:01:54.376044 Core: 160 devices, 18 uclasses, devicetree: separate
362 14:01:54.385736 WDT: Started wdt@44e35000 with servicing (60s timeout)
363 14:01:57.754386 7[r[999;999H[6n8NAND:
364 14:01:57.755100 U-Boot SPL 2022.07-rc3-dirty (May 24 2022 - 12:39:48 +0100)
365 14:01:57.758683 Trying to boot from MMC1
366 14:01:58.331287
367 14:01:58.332049
368 14:01:58.332587 U-Boot 2022.07-rc3-dirty (May 24 2022 - 12:39:48 +0100)
369 14:01:58.333076
370 14:01:58.337107 CPU : AM335X-GP rev 2.1
371 14:01:58.337621 Model: TI AM335x BeagleBone Black
372 14:01:58.340008 DRAM: 512 MiB
373 14:01:58.422743 Core: 160 devices, 18 uclasses, devicetree: separate
374 14:01:58.433227 WDT: Started wdt@44e35000 with servicing (60s timeout)
375 14:02:00.455105 7[r[999;999H[6n8NAND:
376 14:02:00.455791 U-Boot SPL 2022.07-rc3-dirty (May 24 2022 - 12:39:48 +0100)
377 14:02:00.459239 Trying to boot from MMC1
378 14:02:01.034239
379 14:02:01.034888
380 14:02:01.035362 U-Boot 2022.07-rc3-dirty (May 24 2022 - 12:39:48 +0100)
381 14:02:01.035825
382 14:02:01.039560 CPU : AM335X-GP rev 2.1
383 14:02:01.040082 Model: TI AM335x BeagleBone Black
384 14:02:01.043701 DRAM: 512 MiB
385 14:02:01.126874 Core: 160 devices, 18 uclasses, devicetree: separate
386 14:02:01.136566 WDT: Started wdt@44e35000 with servicing (60s timeout)
387 14:02:01.641688 7[r[999;999H[6n8NAND: 0 MiB
388 14:02:01.651913 MMC: OMAP SD/MMC: 0, OMAP SD/MMC: 1
389 14:02:01.725063 Loading Environment from FAT... Unable to use mmc 0:1...
390 14:02:01.746142 <ethaddr> not set. Validating first E-fuse MAC
391 14:02:01.775684 Net: eth2: ethernet@4a100000, eth3: usb_ether
393 14:02:01.835392 Hit any key to stop autoboot: 2
394 14:02:01.836573 end: 2.4.2 bootloader-interrupt (duration 00:00:17) [common]
395 14:02:01.837379 start: 2.4.3 bootloader-commands (timeout 00:04:43) [common]
396 14:02:01.838019 Setting prompt string to ['=>']
397 14:02:01.838661 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:43)
398 14:02:01.844994 0
399 14:02:01.846122 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
400 14:02:01.846778 Sending with 10 millisecond of delay
402 14:02:02.982048 => setenv autoload no
403 14:02:02.993048 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:42)
404 14:02:02.999370 setenv autoload no
405 14:02:03.000285 Sending with 10 millisecond of delay
407 14:02:04.798156 => setenv initrd_high 0xffffffff
408 14:02:04.808909 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
409 14:02:04.809724 setenv initrd_high 0xffffffff
410 14:02:04.810429 Sending with 10 millisecond of delay
412 14:02:06.426851 => setenv fdt_high 0xffffffff
413 14:02:06.437664 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:39)
414 14:02:06.438531 setenv fdt_high 0xffffffff
415 14:02:06.439241 Sending with 10 millisecond of delay
417 14:02:06.731147 => dhcp
418 14:02:06.741909 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:38)
419 14:02:06.742710 dhcp
420 14:02:06.744490 link up on port 0, speed 100, full duplex
421 14:02:06.744930 BOOTP broadcast 1
422 14:02:06.768685 DHCP client bound to address 192.168.6.12 (21 ms)
423 14:02:06.769409 Sending with 10 millisecond of delay
425 14:02:08.446794 => setenv serverip 192.168.6.2
426 14:02:08.457598 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:37)
427 14:02:08.458511 setenv serverip 192.168.6.2
428 14:02:08.459212 Sending with 10 millisecond of delay
430 14:02:11.942428 => tftp 0x82000000 952823/tftp-deploy-qdpf9fzo/kernel/zImage
431 14:02:11.953239 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:33)
432 14:02:11.954091 tftp 0x82000000 952823/tftp-deploy-qdpf9fzo/kernel/zImage
433 14:02:11.954561 link up on port 0, speed 100, full duplex
434 14:02:11.958414 Using ethernet@4a100000 device
435 14:02:11.963821 TFTP from server 192.168.6.2; our IP address is 192.168.6.12
436 14:02:11.964365 Filename '952823/tftp-deploy-qdpf9fzo/kernel/zImage'.
437 14:02:11.970990 Load address: 0x82000000
438 14:02:14.301412 Loading: *################################################## 11 MiB
439 14:02:14.302059 4.7 MiB/s
440 14:02:14.302503 done
441 14:02:14.305546 Bytes transferred = 11510272 (afa200 hex)
442 14:02:14.306439 Sending with 10 millisecond of delay
444 14:02:18.754999 => tftp 0x83000000 952823/tftp-deploy-qdpf9fzo/ramdisk/ramdisk.cpio.gz.uboot
445 14:02:18.765748 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:26)
446 14:02:18.766531 tftp 0x83000000 952823/tftp-deploy-qdpf9fzo/ramdisk/ramdisk.cpio.gz.uboot
447 14:02:18.766973 link up on port 0, speed 100, full duplex
448 14:02:18.770283 Using ethernet@4a100000 device
449 14:02:18.775952 TFTP from server 192.168.6.2; our IP address is 192.168.6.12
450 14:02:18.784588 Filename '952823/tftp-deploy-qdpf9fzo/ramdisk/ramdisk.cpio.gz.uboot'.
451 14:02:18.785040 Load address: 0x83000000
452 14:02:21.799335 Loading: *################################################## 14.1 MiB
453 14:02:21.799933 4.7 MiB/s
454 14:02:21.800419 done
455 14:02:21.803545 Bytes transferred = 14830508 (e24bac hex)
456 14:02:21.804383 Sending with 10 millisecond of delay
458 14:02:23.661302 => setenv initrd_size ${filesize}
459 14:02:23.672087 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:21)
460 14:02:23.672878 setenv initrd_size ${filesize}
461 14:02:23.673580 Sending with 10 millisecond of delay
463 14:02:27.818462 => tftp 0x88000000 952823/tftp-deploy-qdpf9fzo/dtb/am335x-boneblack.dtb
464 14:02:27.829216 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:17)
465 14:02:27.829743 tftp 0x88000000 952823/tftp-deploy-qdpf9fzo/dtb/am335x-boneblack.dtb
466 14:02:27.829972 link up on port 0, speed 100, full duplex
467 14:02:27.833711 Using ethernet@4a100000 device
468 14:02:27.839250 TFTP from server 192.168.6.2; our IP address is 192.168.6.12
469 14:02:27.852515 Filename '952823/tftp-deploy-qdpf9fzo/dtb/am335x-boneblack.dtb'.
470 14:02:27.853065 Load address: 0x88000000
471 14:02:27.864088 Loading: *################################################## 68.9 KiB
472 14:02:27.864592 4.2 MiB/s
473 14:02:27.865035 done
474 14:02:27.870541 Bytes transferred = 70544 (11390 hex)
475 14:02:27.871337 Sending with 10 millisecond of delay
477 14:02:41.051523 => setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/952823/extract-nfsrootfs-u9sj1r2q,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
478 14:02:41.062400 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:04)
479 14:02:41.063328 setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/952823/extract-nfsrootfs-u9sj1r2q,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
480 14:02:41.064120 Sending with 10 millisecond of delay
482 14:02:43.404088 => bootz 0x82000000 0x83000000 0x88000000
483 14:02:43.414946 Setting prompt string to ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
484 14:02:43.415631 bootloader-commands: Wait for prompt ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:02)
485 14:02:43.416788 bootz 0x82000000 0x83000000 0x88000000
486 14:02:43.417285 Kernel image @ 0x82000000 [ 0x000000 - 0xafa200 ]
487 14:02:43.417828 ## Loading init Ramdisk from Legacy Image at 83000000 ...
488 14:02:43.422652 Image Name:
489 14:02:43.423142 Created: 2024-11-07 14:01:44 UTC
490 14:02:43.428116 Image Type: ARM Linux RAMDisk Image (uncompressed)
491 14:02:43.433946 Data Size: 14830444 Bytes = 14.1 MiB
492 14:02:43.434427 Load Address: 00000000
493 14:02:43.440117 Entry Point: 00000000
494 14:02:43.608802 Verifying Checksum ... OK
495 14:02:43.609367 ## Flattened Device Tree blob at 88000000
496 14:02:43.615346 Booting using the fdt blob at 0x88000000
497 14:02:43.620237 Using Device Tree in place at 88000000, end 8801438f
498 14:02:43.633037
499 14:02:43.633527 Starting kernel ...
500 14:02:43.633982
501 14:02:43.634928 end: 2.4.3 bootloader-commands (duration 00:00:42) [common]
502 14:02:43.635560 start: 2.4.4 auto-login-action (timeout 00:04:01) [common]
503 14:02:43.636124 Setting prompt string to ['Linux version [0-9]']
504 14:02:43.636635 Setting prompt string to ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
505 14:02:43.637146 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:05:00)
506 14:02:44.481942 [ 0.000000] Booting Linux on physical CPU 0x0
507 14:02:44.487896 start: 2.4.4.1 login-action (timeout 00:04:01) [common]
508 14:02:44.488570 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
509 14:02:44.489094 Setting prompt string to []
510 14:02:44.489642 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
511 14:02:44.490155 Using line separator: #'\n'#
512 14:02:44.490607 No login prompt set.
513 14:02:44.491086 Parsing kernel messages
514 14:02:44.491522 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
515 14:02:44.492414 [login-action] Waiting for messages, (timeout 00:04:01)
516 14:02:44.492921 Waiting using forced prompt support (timeout 00:02:00)
517 14:02:44.507598 [ 0.000000] Linux version 6.12.0-rc6-next-20241107 (KernelCI@build-j366742-arm-gcc-12-multi-v7-defconfig-wzvmg) (arm-linux-gnueabihf-gcc (Debian 12.2.0-14) 12.2.0, GNU ld (GNU Binutils for Debian) 2.40) #1 SMP Thu Nov 7 13:02:26 UTC 2024
518 14:02:44.513238 [ 0.000000] CPU: ARMv7 Processor [413fc082] revision 2 (ARMv7), cr=10c5387d
519 14:02:44.518979 [ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
520 14:02:44.524810 [ 0.000000] OF: fdt: Machine model: TI AM335x BeagleBone Black
521 14:02:44.530416 [ 0.000000] earlycon: omap8250 at MMIO 0x44e09000 (options '')
522 14:02:44.536170 [ 0.000000] printk: legacy bootconsole [omap8250] enabled
523 14:02:44.542054 [ 0.000000] Memory policy: Data cache writeback
524 14:02:44.548628 [ 0.000000] efi: UEFI not found.
525 14:02:44.551403 [ 0.000000] cma: Reserved 64 MiB at 0x9b800000 on node -1
526 14:02:44.558046 [ 0.000000] Zone ranges:
527 14:02:44.563872 [ 0.000000] DMA [mem 0x0000000080000000-0x000000009fdfffff]
528 14:02:44.569604 [ 0.000000] Normal empty
529 14:02:44.570103 [ 0.000000] HighMem empty
530 14:02:44.575252 [ 0.000000] Movable zone start for each node
531 14:02:44.575748 [ 0.000000] Early memory node ranges
532 14:02:44.586841 [ 0.000000] node 0: [mem 0x0000000080000000-0x000000009fdfffff]
533 14:02:44.591360 [ 0.000000] Initmem setup node 0 [mem 0x0000000080000000-0x000000009fdfffff]
534 14:02:44.613551 [ 0.000000] OF: reserved mem: Reserved memory: No reserved-memory node in the DT
535 14:02:44.626072 [ 0.000000] CPU: All CPU(s) started in SVC mode.
536 14:02:44.631551 [ 0.000000] AM335X ES2.1 (sgx neon)
537 14:02:44.644175 [ 0.000000] percpu: Embedded 17 pages/cpu s40204 r8192 d21236 u69632
538 14:02:44.660922 [ 0.000000] Kernel command line: console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/952823/extract-nfsrootfs-u9sj1r2q,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp
539 14:02:44.672555 <6>[ 0.000000] printk: log buffer data + meta data: 131072 + 409600 = 540672 bytes
540 14:02:44.678382 <6>[ 0.000000] Dentry cache hash table entries: 65536 (order: 6, 262144 bytes, linear)
541 14:02:44.689909 <6>[ 0.000000] Inode-cache hash table entries: 32768 (order: 5, 131072 bytes, linear)
542 14:02:44.695592 <6>[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 130560
543 14:02:44.702033 <6>[ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
544 14:02:44.731088 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
545 14:02:44.737010 <6>[ 0.000000] trace event string verifier disabled
546 14:02:44.737495 <6>[ 0.000000] rcu: Hierarchical RCU implementation.
547 14:02:44.742806 <6>[ 0.000000] rcu: RCU event tracing is enabled.
548 14:02:44.754242 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=16 to nr_cpu_ids=1.
549 14:02:44.754764 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
550 14:02:44.765591 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 10 jiffies.
551 14:02:44.771428 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=1
552 14:02:44.782180 <6>[ 0.000000] RCU Tasks Trace: Setting shift to 0 and lim to 1 rcu_task_cb_adjust=1 rcu_task_cpu_ids=1.
553 14:02:44.796257 <6>[ 0.000000] NR_IRQS: 16, nr_irqs: 16, preallocated irqs: 16
554 14:02:44.814805 <6>[ 0.000000] IRQ: Found an INTC at 0x(ptrval) (revision 5.0) with 128 interrupts
555 14:02:44.821621 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
556 14:02:44.914315 <6>[ 0.000000] TI gptimer clocksource: always-on /ocp/interconnect@44c00000/segment@200000/target-module@31000
557 14:02:44.925866 <6>[ 0.000003] sched_clock: 32 bits at 24MHz, resolution 41ns, wraps every 89478484971ns
558 14:02:44.932646 <6>[ 0.008336] clocksource: dmtimer: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 79635851949 ns
559 14:02:44.945664 <6>[ 0.019165] TI gptimer clockevent: 24000000 Hz at /ocp/interconnect@48000000/segment@0/target-module@40000
560 14:02:44.953124 <6>[ 0.034108] Console: colour dummy device 80x30
561 14:02:44.959342 Matched prompt #6: WARNING:
562 14:02:44.959923 Setting prompt string to ['end trace[^\\r]*\\r', '/ #', 'Login timed out', 'Login incorrect']
563 14:02:44.964632 <3>[ 0.039007] WARNING: Your 'console=ttyO0' has been replaced by 'ttyS0'
564 14:02:44.967396 <3>[ 0.046081] This ensures that you still see kernel messages. Please
565 14:02:44.973627 <3>[ 0.052803] update your kernel commandline.
566 14:02:45.014182 <6>[ 0.057416] Calibrating delay loop... 996.14 BogoMIPS (lpj=4980736)
567 14:02:45.019900 <6>[ 0.096173] CPU: Testing write buffer coherency: ok
568 14:02:45.025915 <6>[ 0.101538] CPU0: Spectre v2: using BPIALL workaround
569 14:02:45.026455 <6>[ 0.107002] pid_max: default: 32768 minimum: 301
570 14:02:45.037272 <6>[ 0.112201] Mount-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
571 14:02:45.044295 <6>[ 0.120019] Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
572 14:02:45.051545 <6>[ 0.129383] CPU0: thread -1, cpu 0, socket -1, mpidr 0
573 14:02:45.059942 <6>[ 0.136508] Setting up static identity map for 0x80300000 - 0x803000ac
574 14:02:45.065710 <6>[ 0.146179] rcu: Hierarchical SRCU implementation.
575 14:02:45.073367 <6>[ 0.151466] rcu: Max phase no-delay instances is 1000.
576 14:02:45.081885 <6>[ 0.162604] EFI services will not be available.
577 14:02:45.087686 <6>[ 0.167868] smp: Bringing up secondary CPUs ...
578 14:02:45.093401 <6>[ 0.172911] smp: Brought up 1 node, 1 CPU
579 14:02:45.101621 <6>[ 0.177312] SMP: Total of 1 processors activated (996.14 BogoMIPS).
580 14:02:45.108008 <6>[ 0.184085] CPU: All CPU(s) started in SVC mode.
581 14:02:45.119630 <6>[ 0.189273] Memory: 405936K/522240K available (16384K kernel code, 2540K rwdata, 6828K rodata, 2048K init, 429K bss, 49108K reserved, 65536K cma-reserved, 0K highmem)
582 14:02:45.125386 <6>[ 0.205551] devtmpfs: initialized
583 14:02:45.148110 <6>[ 0.223099] VFP support v0.3: implementor 41 architecture 3 part 30 variant c rev 3
584 14:02:45.159590 <6>[ 0.231685] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
585 14:02:45.165544 <6>[ 0.242145] futex hash table entries: 256 (order: 2, 16384 bytes, linear)
586 14:02:45.176368 <6>[ 0.254444] pinctrl core: initialized pinctrl subsystem
587 14:02:45.185667 <6>[ 0.265158] DMI not present or invalid.
588 14:02:45.194059 <6>[ 0.271012] NET: Registered PF_NETLINK/PF_ROUTE protocol family
589 14:02:45.203582 <6>[ 0.280009] DMA: preallocated 256 KiB pool for atomic coherent allocations
590 14:02:45.218722 <6>[ 0.291558] thermal_sys: Registered thermal governor 'step_wise'
591 14:02:45.219213 <6>[ 0.291724] cpuidle: using governor menu
592 14:02:45.263205 <6>[ 0.326008] /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70: Fixed dependency cycle(s) with /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
593 14:02:45.283271 <6>[ 0.344807] /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
594 14:02:45.283778 <6>[ 0.365458] No ATAGs?
595 14:02:45.290561 <6>[ 0.368090] hw-breakpoint: debug architecture 0x4 unsupported.
596 14:02:45.300959 <6>[ 0.380181] Serial: AMBA PL011 UART driver
597 14:02:45.334084 <6>[ 0.415051] iommu: Default domain type: Translated
598 14:02:45.343217 <6>[ 0.420396] iommu: DMA domain TLB invalidation policy: strict mode
599 14:02:45.370160 <5>[ 0.450508] SCSI subsystem initialized
600 14:02:45.376077 <6>[ 0.455385] usbcore: registered new interface driver usbfs
601 14:02:45.381928 <6>[ 0.461439] usbcore: registered new interface driver hub
602 14:02:45.390672 <6>[ 0.467230] usbcore: registered new device driver usb
603 14:02:45.396435 <6>[ 0.473788] pps_core: LinuxPPS API ver. 1 registered
604 14:02:45.402238 <6>[ 0.479176] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
605 14:02:45.408107 <6>[ 0.488907] PTP clock support registered
606 14:02:45.413045 <6>[ 0.493365] EDAC MC: Ver: 3.0.0
607 14:02:45.462541 <6>[ 0.541004] scmi_core: SCMI protocol bus registered
608 14:02:45.478097 <6>[ 0.558433] vgaarb: loaded
609 14:02:45.484253 <6>[ 0.562274] clocksource: Switched to clocksource dmtimer
610 14:02:45.518117 <6>[ 0.598765] NET: Registered PF_INET protocol family
611 14:02:45.530662 <6>[ 0.604456] IP idents hash table entries: 8192 (order: 4, 65536 bytes, linear)
612 14:02:45.536418 <6>[ 0.613317] tcp_listen_portaddr_hash hash table entries: 512 (order: 0, 4096 bytes, linear)
613 14:02:45.547929 <6>[ 0.622208] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
614 14:02:45.553679 <6>[ 0.630486] TCP established hash table entries: 4096 (order: 2, 16384 bytes, linear)
615 14:02:45.565228 <6>[ 0.638779] TCP bind hash table entries: 4096 (order: 4, 65536 bytes, linear)
616 14:02:45.571108 <6>[ 0.646498] TCP: Hash tables configured (established 4096 bind 4096)
617 14:02:45.576955 <6>[ 0.653428] UDP hash table entries: 256 (order: 1, 8192 bytes, linear)
618 14:02:45.582797 <6>[ 0.660440] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes, linear)
619 14:02:45.590308 <6>[ 0.668057] NET: Registered PF_UNIX/PF_LOCAL protocol family
620 14:02:45.676910 <6>[ 0.752162] RPC: Registered named UNIX socket transport module.
621 14:02:45.677426 <6>[ 0.758595] RPC: Registered udp transport module.
622 14:02:45.682543 <6>[ 0.763719] RPC: Registered tcp transport module.
623 14:02:45.691179 <6>[ 0.768824] RPC: Registered tcp-with-tls transport module.
624 14:02:45.696925 <6>[ 0.774745] RPC: Registered tcp NFSv4.1 backchannel transport module.
625 14:02:45.704210 <6>[ 0.781655] PCI: CLS 0 bytes, default 64
626 14:02:45.706482 <5>[ 0.787471] Initialise system trusted keyrings
627 14:02:45.729727 <6>[ 0.807732] Trying to unpack rootfs image as initramfs...
628 14:02:45.811207 <6>[ 0.885978] workingset: timestamp_bits=30 max_order=17 bucket_order=0
629 14:02:45.816072 <6>[ 0.893535] squashfs: version 4.0 (2009/01/31) Phillip Lougher
630 14:02:45.852322 <5>[ 0.933296] NFS: Registering the id_resolver key type
631 14:02:45.858041 <5>[ 0.938881] Key type id_resolver registered
632 14:02:45.863963 <5>[ 0.943530] Key type id_legacy registered
633 14:02:45.869592 <6>[ 0.947964] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
634 14:02:45.879225 <6>[ 0.955169] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
635 14:02:45.951767 <5>[ 1.032745] Key type asymmetric registered
636 14:02:45.957626 <5>[ 1.037269] Asymmetric key parser 'x509' registered
637 14:02:45.969105 <6>[ 1.042759] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 246)
638 14:02:45.969594 <6>[ 1.050648] io scheduler mq-deadline registered
639 14:02:45.974969 <6>[ 1.055627] io scheduler kyber registered
640 14:02:45.980448 <6>[ 1.060086] io scheduler bfq registered
641 14:02:46.065624 <6>[ 1.142983] ledtrig-cpu: registered to indicate activity on CPUs
642 14:02:46.336269 <6>[ 1.413451] Serial: 8250/16550 driver, 5 ports, IRQ sharing enabled
643 14:02:46.366429 <6>[ 1.447389] msm_serial: driver initialized
644 14:02:46.372591 <6>[ 1.452176] SuperH (H)SCI(F) driver initialized
645 14:02:46.378630 <6>[ 1.457498] STMicroelectronics ASC driver initialized
646 14:02:46.383770 <6>[ 1.463154] STM32 USART driver initialized
647 14:02:46.513364 <6>[ 1.594447] brd: module loaded
648 14:02:46.544789 <6>[ 1.625029] loop: module loaded
649 14:02:46.579615 <6>[ 1.659753] CAN device driver interface
650 14:02:46.586128 <6>[ 1.664974] bgmac_bcma: Broadcom 47xx GBit MAC driver loaded
651 14:02:46.591920 <6>[ 1.671901] e1000e: Intel(R) PRO/1000 Network Driver
652 14:02:46.597821 <6>[ 1.677348] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
653 14:02:46.603465 <6>[ 1.683787] igb: Intel(R) Gigabit Ethernet Network Driver
654 14:02:46.611717 <6>[ 1.689611] igb: Copyright (c) 2007-2014 Intel Corporation.
655 14:02:46.623564 <6>[ 1.698903] pegasus: Pegasus/Pegasus II USB Ethernet driver
656 14:02:46.629298 <6>[ 1.705059] usbcore: registered new interface driver pegasus
657 14:02:46.632071 <6>[ 1.711184] usbcore: registered new interface driver asix
658 14:02:46.637809 <6>[ 1.717091] usbcore: registered new interface driver ax88179_178a
659 14:02:46.643564 <6>[ 1.723685] usbcore: registered new interface driver cdc_ether
660 14:02:46.649334 <6>[ 1.729981] usbcore: registered new interface driver smsc75xx
661 14:02:46.660858 <6>[ 1.736212] usbcore: registered new interface driver smsc95xx
662 14:02:46.666617 <6>[ 1.742442] usbcore: registered new interface driver net1080
663 14:02:46.672471 <6>[ 1.748566] usbcore: registered new interface driver cdc_subset
664 14:02:46.678193 <6>[ 1.754985] usbcore: registered new interface driver zaurus
665 14:02:46.683219 <6>[ 1.761027] usbcore: registered new interface driver cdc_ncm
666 14:02:46.693141 <6>[ 1.770594] usbcore: registered new interface driver usb-storage
667 14:02:46.702671 <6>[ 1.781836] i2c_dev: i2c /dev entries driver
668 14:02:46.728517 <5>[ 1.801514] cpuidle: enable-method property 'ti,am3352' found operations
669 14:02:46.734335 <6>[ 1.811142] sdhci: Secure Digital Host Controller Interface driver
670 14:02:46.742343 <6>[ 1.817909] sdhci: Copyright(c) Pierre Ossman
671 14:02:46.749829 <6>[ 1.824549] Synopsys Designware Multimedia Card Interface Driver
672 14:02:46.754946 <6>[ 1.832730] sdhci-pltfm: SDHCI platform and OF driver helper
673 14:02:46.769474 <6>[ 1.843092] usbcore: registered new interface driver usbhid
674 14:02:46.769960 <6>[ 1.849116] usbhid: USB HID core driver
675 14:02:46.782924 <6>[ 1.861399] NET: Registered PF_INET6 protocol family
676 14:02:47.272292 <6>[ 2.353176] Segment Routing with IPv6
677 14:02:47.277802 <6>[ 2.357328] In-situ OAM (IOAM) with IPv6
678 14:02:47.284613 <6>[ 2.361721] sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver
679 14:02:47.290528 <6>[ 2.369181] NET: Registered PF_PACKET protocol family
680 14:02:47.296284 <6>[ 2.374745] can: controller area network core
681 14:02:47.302112 <6>[ 2.379571] NET: Registered PF_CAN protocol family
682 14:02:47.302775 <6>[ 2.384801] can: raw protocol
683 14:02:47.307859 <6>[ 2.388126] can: broadcast manager protocol
684 14:02:47.314404 <6>[ 2.392735] can: netlink gateway - max_hops=1
685 14:02:47.320500 <5>[ 2.398263] Key type dns_resolver registered
686 14:02:47.326797 <6>[ 2.403339] ThumbEE CPU extension supported.
687 14:02:47.327393 <5>[ 2.408027] Registering SWP/SWPB emulation handler
688 14:02:47.336566 <3>[ 2.413728] omap_voltage_late_init: Voltage driver support not added
689 14:02:47.544490 <5>[ 2.623042] Loading compiled-in X.509 certificates
690 14:02:47.604719 <6>[ 2.670866] /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70: Fixed dependency cycle(s) with /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
691 14:02:47.634211 <6>[ 2.700316] /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70: Fixed dependency cycle(s) with /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
692 14:02:47.782858 <6>[ 2.845053] /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70: Fixed dependency cycle(s) with /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
693 14:02:47.798379 <6>[ 2.864623] /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70: Fixed dependency cycle(s) with /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
694 14:02:47.824883 <6>[ 2.890862] /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800/clkout2-pins
695 14:02:47.834852 <6>[ 2.912489] pinctrl-single 44e10800.pinmux: 142 pins, size 568
696 14:02:47.861505 <3>[ 2.936489] ti-sysc 44e31000.target-module: probe with driver ti-sysc failed with error -16
697 14:02:48.139369 <6>[ 3.205555] /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
698 14:02:48.165318 <3>[ 3.240386] ti-sysc 48040000.target-module: probe with driver ti-sysc failed with error -16
699 14:02:48.393663 <6>[ 3.473134] OMAP GPIO hardware version 0.1
700 14:02:48.414418 <6>[ 3.491868] omap-mailbox 480c8000.mailbox: omap mailbox rev 0x400
701 14:02:48.506716 <4>[ 3.583881] at24 2-0054: supply vcc not found, using dummy regulator
702 14:02:48.541633 <4>[ 3.619697] at24 2-0055: supply vcc not found, using dummy regulator
703 14:02:48.580233 <4>[ 3.657406] at24 2-0056: supply vcc not found, using dummy regulator
704 14:02:48.621031 <4>[ 3.698241] at24 2-0057: supply vcc not found, using dummy regulator
705 14:02:48.657196 <6>[ 3.735808] omap_i2c 4819c000.i2c: bus 2 rev0.11 at 100 kHz
706 14:02:48.733261 <3>[ 3.807756] 48000000.interconnect:segment@200000:target-module@0:mpu@0:fck: device ID is greater than 24
707 14:02:48.755905 <6>[ 3.822124] /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
708 14:02:48.782958 <6>[ 3.845540] /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
709 14:02:48.800393 <6>[ 3.864734] /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70: Fixed dependency cycle(s) with /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
710 14:02:48.815528 <6>[ 3.882694] /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
711 14:02:48.838137 <4>[ 3.913209] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
712 14:02:48.845849 <4>[ 3.921761] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
713 14:02:48.912885 <6>[ 3.992459] Freeing initrd memory: 14484K
714 14:02:48.920108 <6>[ 3.998402] omap_rng 48310000.rng: Random Number Generator ver. 20
715 14:02:48.944385 <5>[ 4.025359] random: crng init done
716 14:02:48.995498 <6>[ 4.072274] davinci_mdio 4a101000.mdio: davinci mdio revision 1.6, bus freq 1000000
717 14:02:49.079854 <6>[ 4.154716] davinci_mdio 4a101000.mdio: phy[0]: device 4a101000.mdio:00, driver SMSC LAN8710/LAN8720
718 14:02:49.085580 <6>[ 4.165015] cpsw-switch 4a100000.switch: initialized cpsw ale version 1.4
719 14:02:49.097557 <6>[ 4.172348] cpsw-switch 4a100000.switch: ALE Table size 1024, Policers 0
720 14:02:49.103202 <6>[ 4.179792] cpsw-switch 4a100000.switch: cpts: overflow check period 500 (jiffies)
721 14:02:49.114678 <6>[ 4.187927] cpsw-switch 4a100000.switch: CPTS: ref_clk_freq:250000000 calc_mult:2147483648 calc_shift:29 error:0 nsec/sec
722 14:02:49.122054 <6>[ 4.199571] cpsw-switch 4a100000.switch: Detected MACID = 78:a5:04:e2:4c:3d
723 14:02:49.135244 <5>[ 4.208615] cpsw-switch 4a100000.switch: initialized (regs 0x4a100000, pool size 256) hw_ver:0019010C 1.12 (0)
724 14:02:49.163063 <3>[ 4.238512] debugfs: Directory '49000000.dma' with parent 'dmaengine' already present!
725 14:02:49.167922 <6>[ 4.247116] edma 49000000.dma: TI EDMA DMA engine driver
726 14:02:49.239611 <3>[ 4.315150] target-module@4b000000:target-module@140000:pmu@0:fck: device ID is greater than 24
727 14:02:49.254188 <6>[ 4.329510] hw perfevents: enabled with armv7_cortex_a8 PMU driver, 5 (8000000f) counters available
728 14:02:49.268020 <3>[ 4.346587] l3-aon-clkctrl:0000:0: failed to disable
729 14:02:49.318067 <6>[ 4.393442] 44e09000.serial: ttyS0 at MMIO 0x44e09000 (irq = 36, base_baud = 3000000) is a 8250
730 14:02:49.323762 <6>[ 4.402917] printk: legacy console [ttyS0] enabled
731 14:02:49.329479 <6>[ 4.402917] printk: legacy console [ttyS0] enabled
732 14:02:49.335102 <6>[ 4.413247] printk: legacy bootconsole [omap8250] disabled
733 14:02:49.340367 <6>[ 4.413247] printk: legacy bootconsole [omap8250] disabled
734 14:02:49.378766 <4>[ 4.453049] tps65217-pmic: Failed to locate of_node [id: -1]
735 14:02:49.381667 <4>[ 4.460451] tps65217-bl: Failed to locate of_node [id: -1]
736 14:02:49.398712 <6>[ 4.480093] tps65217 0-0024: TPS65217 ID 0xe version 1.2
737 14:02:49.423118 <6>[ 4.487036] /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
738 14:02:49.440311 <6>[ 4.504693] /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70: Fixed dependency cycle(s) with /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
739 14:02:49.444290 <6>[ 4.522543] omap_i2c 44e0b000.i2c: bus 0 rev0.11 at 400 kHz
740 14:02:49.466794 <6>[ 4.542605] omap_gpio 44e07000.gpio: Could not set line 6 debounce to 200000 microseconds (-22)
741 14:02:49.472653 <6>[ 4.551660] sdhci-omap 48060000.mmc: Got CD GPIO
742 14:02:49.480709 <4>[ 4.556838] sdhci-omap 48060000.mmc: supply pbias not found, using dummy regulator
743 14:02:49.495541 <4>[ 4.570465] sdhci-omap 48060000.mmc: supply vqmmc not found, using dummy regulator
744 14:02:49.503119 <4>[ 4.579268] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
745 14:02:49.537014 <4>[ 4.614120] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
746 14:02:49.636050 <6>[ 4.712835] at24 0-0050: 32768 byte 24c256 EEPROM, writable, 1 bytes/write
747 14:02:49.668921 <6>[ 4.745793] mmc0: SDHCI controller on 48060000.mmc [48060000.mmc] using External DMA
748 14:02:49.690181 <6>[ 4.765173] mmc1: SDHCI controller on 481d8000.mmc [481d8000.mmc] using External DMA
749 14:02:49.695944 <6>[ 4.774080] cpsw-switch 4a100000.switch: starting ndev. mode: dual_mac
750 14:02:49.740416 <6>[ 4.812349] mmc0: new high speed SDHC card at address 1234
751 14:02:49.740960 <6>[ 4.819767] mmcblk0: mmc0:1234 SA32G 29.1 GiB
752 14:02:49.747125 <6>[ 4.829018] mmcblk0: p1
753 14:02:49.779427 <6>[ 4.853496] SMSC LAN8710/LAN8720 4a101000.mdio:00: attached PHY driver (mii_bus:phy_addr=4a101000.mdio:00, irq=POLL)
754 14:02:49.806642 <6>[ 4.878008] mmc1: new high speed MMC card at address 0001
755 14:02:49.807215 <6>[ 4.885764] mmcblk1: mmc1:0001 MMC04G 3.60 GiB
756 14:02:49.816295 <6>[ 4.895117] mmcblk1boot0: mmc1:0001 MMC04G 2.00 MiB
757 14:02:49.824530 <6>[ 4.903326] mmcblk1boot1: mmc1:0001 MMC04G 2.00 MiB
758 14:02:49.833639 <6>[ 4.911157] mmcblk1rpmb: mmc1:0001 MMC04G 128 KiB, chardev (236:0)
759 14:02:51.867915 <6>[ 6.943322] cpsw-switch 4a100000.switch eth0: Link is Up - 100Mbps/Full - flow control off
760 14:02:51.941247 <5>[ 6.982281] Sending DHCP requests ., OK
761 14:02:51.952509 <6>[ 7.026781] IP-Config: Got DHCP answer from 192.168.6.1, my address is 192.168.6.12
762 14:02:51.953015 <6>[ 7.034938] IP-Config: Complete:
763 14:02:51.963754 <6>[ 7.038476] device=eth0, hwaddr=78:a5:04:e2:4c:3d, ipaddr=192.168.6.12, mask=255.255.255.0, gw=192.168.6.1
764 14:02:51.969502 <6>[ 7.048988] host=192.168.6.12, domain=, nis-domain=(none)
765 14:02:51.981796 <6>[ 7.055198] bootserver=192.168.6.1, rootserver=192.168.6.2, rootpath=
766 14:02:51.982264 <6>[ 7.055233] nameserver0=10.255.253.1
767 14:02:51.988008 <6>[ 7.067777] clk: Disabling unused clocks
768 14:02:51.993884 <6>[ 7.072549] PM: genpd: Disabling unused power domains
769 14:02:52.013515 <6>[ 7.091190] Freeing unused kernel image (initmem) memory: 2048K
770 14:02:52.020735 <6>[ 7.100871] Run /init as init process
771 14:02:52.045873 Loading, please wait...
772 14:02:52.122323 Starting systemd-udevd version 252.22-1~deb12u1
773 14:02:55.190419 <4>[ 10.265373] am335x-phy-driver 47401300.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
774 14:02:55.368846 <4>[ 10.443935] am335x-phy-driver 47401b00.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
775 14:02:55.491206 <6>[ 10.572764] musb-hdrc musb-hdrc.1: MUSB HDRC host driver
776 14:02:55.502024 <6>[ 10.578439] musb-hdrc musb-hdrc.1: new USB bus registered, assigned bus number 1
777 14:02:55.752654 <6>[ 10.832846] hub 1-0:1.0: USB hub found
778 14:02:55.814902 <6>[ 10.894865] hub 1-0:1.0: 1 port detected
779 14:02:55.986926 <6>[ 11.066624] tda998x 0-0070: found TDA19988
780 14:02:58.867526 Begin: Loading essential drivers ... done.
781 14:02:58.873149 Begin: Running /scripts/init-premount ... done.
782 14:02:58.878742 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
783 14:02:58.888120 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
784 14:02:58.895593 Device /sys/class/net/eth0 found
785 14:02:58.896099 done.
786 14:02:58.958189 Begin: Waiting up to 180 secs for any network device to become available ... done.
787 14:02:59.033857 IP-Config: eth0 hardware address 78:a5:04:e2:4c:3d mtu 1500 DHCP
788 14:02:59.138282 IP-Config: eth0 guessed broadcast address 192.168.6.255
789 14:02:59.143761 IP-Config: eth0 complete (dhcp from 192.168.6.1):
790 14:02:59.149403 address: 192.168.6.12 broadcast: 192.168.6.255 netmask: 255.255.255.0
791 14:02:59.158407 gateway: 192.168.6.1 dns0 : 10.255.253.1 dns1 : 0.0.0.0
792 14:02:59.163096 rootserver: 192.168.6.1 rootpath:
793 14:02:59.163589 filename :
794 14:02:59.289675 done.
795 14:02:59.307957 Begin: Running /scripts/nfs-bottom ... done.
796 14:02:59.377924 Begin: Running /scripts/init-bottom ... done.
797 14:03:00.932525 <30>[ 16.010278] systemd[1]: System time before build time, advancing clock.
798 14:03:01.146307 <30>[ 16.199935] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
799 14:03:01.153910 <30>[ 16.233641] systemd[1]: Detected architecture arm.
800 14:03:01.165720
801 14:03:01.166292 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
802 14:03:01.166810
803 14:03:01.193245 <30>[ 16.271884] systemd[1]: Hostname set to <debian-bookworm-armhf>.
804 14:03:03.303089 <30>[ 18.380166] systemd[1]: Queued start job for default target graphical.target.
805 14:03:03.320491 <30>[ 18.395433] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
806 14:03:03.327934 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
807 14:03:03.352265 <30>[ 18.428675] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
808 14:03:03.365334 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
809 14:03:03.390362 <30>[ 18.464791] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
810 14:03:03.397771 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
811 14:03:03.418857 <30>[ 18.496350] systemd[1]: Created slice user.slice - User and Session Slice.
812 14:03:03.430800 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
813 14:03:03.464551 <30>[ 18.533447] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
814 14:03:03.470567 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
815 14:03:03.499510 <30>[ 18.574416] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
816 14:03:03.510588 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
817 14:03:03.548556 <30>[ 18.613266] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
818 14:03:03.554932 <30>[ 18.633703] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
819 14:03:03.562486 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
820 14:03:03.586684 <30>[ 18.662680] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
821 14:03:03.594895 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
822 14:03:03.617479 <30>[ 18.693114] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
823 14:03:03.625960 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
824 14:03:03.647429 <30>[ 18.723263] systemd[1]: Reached target paths.target - Path Units.
825 14:03:03.652592 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
826 14:03:03.677143 <30>[ 18.752960] systemd[1]: Reached target remote-fs.target - Remote File Systems.
827 14:03:03.685007 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
828 14:03:03.706964 <30>[ 18.782807] systemd[1]: Reached target slices.target - Slice Units.
829 14:03:03.712466 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
830 14:03:03.737257 <30>[ 18.813086] systemd[1]: Reached target swap.target - Swaps.
831 14:03:03.741334 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
832 14:03:03.767342 <30>[ 18.842983] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
833 14:03:03.776370 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
834 14:03:03.798517 <30>[ 18.873901] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
835 14:03:03.806800 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
836 14:03:03.885935 <30>[ 18.956575] systemd[1]: systemd-journald-audit.socket - Journal Audit Socket was skipped because of an unmet condition check (ConditionSecurity=audit).
837 14:03:03.898724 <30>[ 18.974201] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
838 14:03:03.907121 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
839 14:03:03.930443 <30>[ 19.005129] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
840 14:03:03.937885 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
841 14:03:03.960086 <30>[ 19.035470] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
842 14:03:03.968262 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
843 14:03:03.992940 <30>[ 19.067288] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
844 14:03:03.998586 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
845 14:03:04.029977 <30>[ 19.104108] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
846 14:03:04.037638 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
847 14:03:04.066302 <30>[ 19.135792] systemd[1]: dev-hugepages.mount - Huge Pages File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/mm/hugepages).
848 14:03:04.086691 <30>[ 19.156073] systemd[1]: dev-mqueue.mount - POSIX Message Queue File System was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/mqueue).
849 14:03:04.127027 <30>[ 19.203412] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
850 14:03:04.142728 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
851 14:03:04.174578 <30>[ 19.250739] systemd[1]: Mounting sys-kernel-tracing.mount - Kernel Trace File System...
852 14:03:04.198173 Mounting [0;1;39msys-kernel-tracin…[0m - Kernel Trace File System...
853 14:03:04.261774 <30>[ 19.336960] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
854 14:03:04.278419 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
855 14:03:04.310262 <30>[ 19.386078] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
856 14:03:04.337335 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
857 14:03:04.387394 <30>[ 19.463579] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
858 14:03:04.406882 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
859 14:03:04.438857 <30>[ 19.515588] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
860 14:03:04.465303 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
861 14:03:04.520098 <30>[ 19.595601] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
862 14:03:04.547334 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
863 14:03:04.598536 <30>[ 19.675008] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
864 14:03:04.624117 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
865 14:03:04.677699 <30>[ 19.754157] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
866 14:03:04.696800 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
867 14:03:04.726615 <28>[ 19.794987] systemd[1]: systemd-journald.service: unit configures an IP firewall, but the local system does not support BPF/cgroup firewalling.
868 14:03:04.735099 <28>[ 19.810699] systemd[1]: (This warning is only shown for the first unit using IP firewalling.)
869 14:03:04.778730 <30>[ 19.855696] systemd[1]: Starting systemd-journald.service - Journal Service...
870 14:03:04.795939 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
871 14:03:04.868027 <30>[ 19.944261] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
872 14:03:04.894638 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
873 14:03:04.939004 <30>[ 20.015510] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
874 14:03:04.988070 Starting [0;1;39msystemd-network-g… units from Kernel command line...
875 14:03:05.051775 <30>[ 20.126695] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
876 14:03:05.096892 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
877 14:03:05.160538 <30>[ 20.236317] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
878 14:03:05.216724 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
879 14:03:05.273200 <30>[ 20.349830] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
880 14:03:05.318401 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
881 14:03:05.347401 <30>[ 20.424001] systemd[1]: Mounted sys-kernel-tracing.mount - Kernel Trace File System.
882 14:03:05.373215 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-tracing…nt[0m - Kernel Trace File System.
883 14:03:05.402240 <30>[ 20.477733] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
884 14:03:05.435311 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
885 14:03:05.609916 <30>[ 20.687000] systemd[1]: modprobe@configfs.service: Deactivated successfully.
886 14:03:05.644616 <30>[ 20.720557] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
887 14:03:05.676910 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
888 14:03:05.698138 <30>[ 20.773953] systemd[1]: Started systemd-journald.service - Journal Service.
889 14:03:05.705038 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
890 14:03:05.737284 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
891 14:03:05.762556 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
892 14:03:05.799533 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
893 14:03:05.827074 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
894 14:03:05.852754 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
895 14:03:05.889429 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
896 14:03:05.910742 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
897 14:03:05.939514 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
898 14:03:05.977016 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
899 14:03:06.030494 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
900 14:03:06.074557 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
901 14:03:06.128982 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
902 14:03:06.210840 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
903 14:03:06.266681 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
904 14:03:06.436348 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
905 14:03:06.451931 <46>[ 21.528790] systemd-journald[164]: Received client request to flush runtime journal.
906 14:03:06.616303 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
907 14:03:06.684283 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
908 14:03:07.492993 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
909 14:03:07.578789 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
910 14:03:08.248635 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
911 14:03:08.399501 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
912 14:03:08.427321 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
913 14:03:08.447256 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
914 14:03:08.518800 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
915 14:03:08.563942 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
916 14:03:09.544494 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
917 14:03:09.617652 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
918 14:03:09.676628 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
919 14:03:09.788872 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
920 14:03:09.870983 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
921 14:03:11.964822 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
922 14:03:12.399069 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
923 14:03:12.691276 <5>[ 27.768482] cfg80211: Loading compiled-in X.509 certificates for regulatory database
924 14:03:13.489182 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
925 14:03:14.188973 <5>[ 29.267993] Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
926 14:03:14.307040 <5>[ 29.384540] Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
927 14:03:14.320091 <4>[ 29.396872] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
928 14:03:14.326109 <6>[ 29.406030] cfg80211: failed to load regulatory.db
929 14:03:14.689615 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
930 14:03:14.826394 <46>[ 29.894318] systemd-journald[164]: Oldest entry in /var/log/journal/658c871cd7314ccea6115dc5728f8992/system.journal is older than the configured file retention duration (1month), suggesting rotation.
931 14:03:14.982910 <46>[ 30.053966] systemd-journald[164]: /var/log/journal/658c871cd7314ccea6115dc5728f8992/system.journal: Journal header limits reached or header out-of-date, rotating.
932 14:03:15.426140 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
933 14:03:23.980654 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
934 14:03:24.012572 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
935 14:03:24.039686 [[0;32m OK [0m] Reached target [0;1;39musb-gadget.…m - Hardware activated USB gadget.
936 14:03:24.068153 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
937 14:03:24.140732 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
938 14:03:24.208380 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
939 14:03:24.264401 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
940 14:03:24.320750 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
941 14:03:24.374448 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
942 14:03:24.403405 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
943 14:03:24.432154 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
944 14:03:24.473590 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
945 14:03:24.500094 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
946 14:03:24.546380 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
947 14:03:24.576438 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
948 14:03:24.599309 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
949 14:03:24.633328 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
950 14:03:24.670324 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
951 14:03:24.703178 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
952 14:03:24.726644 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
953 14:03:24.756763 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
954 14:03:24.776706 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
955 14:03:24.803123 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
956 14:03:24.876973 Starting [0;1;39malsa-restore.serv…- Save/Restore Sound Card State...
957 14:03:24.920574 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
958 14:03:25.009398 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
959 14:03:25.091357 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
960 14:03:25.179086 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
961 14:03:25.236845 [[0;32m OK [0m] Finished [0;1;39malsa-restore.serv…m - Save/Restore Sound Card State.
962 14:03:25.246885 [[0;32m OK [0m] Reached target [0;1;39msound.target[0m - Sound Card.
963 14:03:25.456242 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
964 14:03:25.527880 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
965 14:03:25.597617 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
966 14:03:25.625604 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
967 14:03:25.655572 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
968 14:03:25.822112 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
969 14:03:26.180672 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
970 14:03:26.238606 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
971 14:03:26.273821 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
972 14:03:26.363553 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
973 14:03:26.542790 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
974 14:03:26.676218
975 14:03:26.676633 Debian GNU/Linux 12worm-armhf login: root (automatic login)
976 14:03:26.679685
977 14:03:26.981778 Linux debian-bookworm-armhf 6.12.0-rc6-next-20241107 #1 SMP Thu Nov 7 13:02:26 UTC 2024 armv7l
978 14:03:26.982199
979 14:03:26.987402 The programs included with the Debian GNU/Linux system are free software;
980 14:03:26.996279 the exact distribution terms for each program are described in the
981 14:03:26.996615 individual files in /usr/share/doc/*/copyright.
982 14:03:26.996835
983 14:03:27.007811 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
984 14:03:27.008175 permitted by applicable law.
985 14:03:31.652843 Unable to match end of the kernel message
987 14:03:31.654571 Setting prompt string to ['/ #']
988 14:03:31.655208 end: 2.4.4.1 login-action (duration 00:00:47) [common]
990 14:03:31.657038 end: 2.4.4 auto-login-action (duration 00:00:48) [common]
991 14:03:31.657662 start: 2.4.5 expect-shell-connection (timeout 00:03:13) [common]
992 14:03:31.658140 Setting prompt string to ['/ #']
993 14:03:31.658590 Forcing a shell prompt, looking for ['/ #']
995 14:03:31.709616 / #
996 14:03:31.710218 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
997 14:03:31.710701 Waiting using forced prompt support (timeout 00:02:30)
998 14:03:31.714765
999 14:03:31.723494 end: 2.4.5 expect-shell-connection (duration 00:00:00) [common]
1000 14:03:31.724146 start: 2.4.6 export-device-env (timeout 00:03:13) [common]
1001 14:03:31.724655 Sending with 10 millisecond of delay
1003 14:03:36.720773 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/952823/extract-nfsrootfs-u9sj1r2q'
1004 14:03:36.731952 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/952823/extract-nfsrootfs-u9sj1r2q'
1005 14:03:36.733002 Sending with 10 millisecond of delay
1007 14:03:38.831869 / # export NFS_SERVER_IP='192.168.6.2'
1008 14:03:38.842849 export NFS_SERVER_IP='192.168.6.2'
1009 14:03:38.843806 end: 2.4.6 export-device-env (duration 00:00:07) [common]
1010 14:03:38.844480 end: 2.4 uboot-commands (duration 00:01:54) [common]
1011 14:03:38.845103 end: 2 uboot-action (duration 00:01:54) [common]
1012 14:03:38.845801 start: 3 lava-test-retry (timeout 00:06:55) [common]
1013 14:03:38.846431 start: 3.1 lava-test-shell (timeout 00:06:55) [common]
1014 14:03:38.846900 Using namespace: common
1016 14:03:38.948102 / # #
1017 14:03:38.948976 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
1018 14:03:38.953446 #
1019 14:03:38.958842 Using /lava-952823
1021 14:03:39.060075 / # export SHELL=/bin/bash
1022 14:03:39.064419 export SHELL=/bin/bash
1024 14:03:39.171504 / # . /lava-952823/environment
1025 14:03:39.176718 . /lava-952823/environment
1027 14:03:39.289260 / # /lava-952823/bin/lava-test-runner /lava-952823/0
1028 14:03:39.290046 Test shell timeout: 10s (minimum of the action and connection timeout)
1029 14:03:39.293479 /lava-952823/bin/lava-test-runner /lava-952823/0
1030 14:03:39.680517 + export TESTRUN_ID=0_timesync-off
1031 14:03:39.687543 + TESTRUN_ID=0_timesync-off
1032 14:03:39.688141 + cd /lava-952823/0/tests/0_timesync-off
1033 14:03:39.688569 ++ cat uuid
1034 14:03:39.704642 + UUID=952823_1.6.2.4.1
1035 14:03:39.705127 + set +x
1036 14:03:39.713172 <LAVA_SIGNAL_STARTRUN 0_timesync-off 952823_1.6.2.4.1>
1037 14:03:39.713613 + systemctl stop systemd-timesyncd
1038 14:03:39.714295 Received signal: <STARTRUN> 0_timesync-off 952823_1.6.2.4.1
1039 14:03:39.714721 Starting test lava.0_timesync-off (952823_1.6.2.4.1)
1040 14:03:39.715244 Skipping test definition patterns.
1041 14:03:39.993110 + set +x
1042 14:03:39.993734 <LAVA_SIGNAL_ENDRUN 0_timesync-off 952823_1.6.2.4.1>
1043 14:03:39.994420 Received signal: <ENDRUN> 0_timesync-off 952823_1.6.2.4.1
1044 14:03:39.994924 Ending use of test pattern.
1045 14:03:39.995332 Ending test lava.0_timesync-off (952823_1.6.2.4.1), duration 0.28
1047 14:03:40.204255 + export TESTRUN_ID=1_kselftest-dt
1048 14:03:40.212094 + TESTRUN_ID=1_kselftest-dt
1049 14:03:40.212612 + cd /lava-952823/0/tests/1_kselftest-dt
1050 14:03:40.213044 ++ cat uuid
1051 14:03:40.228060 + UUID=952823_1.6.2.4.5
1052 14:03:40.228606 + set +x
1053 14:03:40.233595 <LAVA_SIGNAL_STARTRUN 1_kselftest-dt 952823_1.6.2.4.5>
1054 14:03:40.234111 + cd ./automated/linux/kselftest/
1055 14:03:40.234806 Received signal: <STARTRUN> 1_kselftest-dt 952823_1.6.2.4.5
1056 14:03:40.235229 Starting test lava.1_kselftest-dt (952823_1.6.2.4.5)
1057 14:03:40.235709 Skipping test definition patterns.
1058 14:03:40.259856 + ./kselftest.sh -c dt -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/next/master/next-20241107/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz -L '' -S /dev/null -b beaglebone-black -g next -e '' -p /opt/kselftests/mainline/ -n 1 -i 1 -E ''
1059 14:03:40.362321 INFO: install_deps skipped
1060 14:03:41.071833 --2024-11-07 14:03:41-- http://storage.kernelci.org/next/master/next-20241107/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz
1061 14:03:41.349496 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
1062 14:03:41.494790 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
1063 14:03:41.639760 HTTP request sent, awaiting response... 200 OK
1064 14:03:41.640345 Length: 4158136 (4.0M) [application/octet-stream]
1065 14:03:41.645224 Saving to: 'kselftest_armhf.tar.gz'
1066 14:03:41.645617
1067 14:03:43.201844
kselftest_armhf.tar 0%[ ] 0 --.-KB/s
kselftest_armhf.tar 1%[ ] 49.92K 175KB/s
kselftest_armhf.tar 4%[ ] 194.76K 337KB/s
kselftest_armhf.tar 19%[==> ] 773.17K 905KB/s
kselftest_armhf.tar 35%[======> ] 1.41M 1.27MB/s
kselftest_armhf.tar 77%[==============> ] 3.05M 2.18MB/s
kselftest_armhf.tar 100%[===================>] 3.96M 2.55MB/s in 1.6s
1068 14:03:43.203400
1069 14:03:43.847959 2024-11-07 14:03:43 (2.55 MB/s) - 'kselftest_armhf.tar.gz' saved [4158136/4158136]
1070 14:03:43.848419
1071 14:03:56.829717 skiplist:
1072 14:03:56.830158 ========================================
1073 14:03:56.834328 ========================================
1074 14:03:56.934253 dt:test_unprobed_devices.sh
1075 14:03:56.965071 ============== Tests to run ===============
1076 14:03:56.975899 dt:test_unprobed_devices.sh
1077 14:03:56.979801 ===========End Tests to run ===============
1078 14:03:56.987885 shardfile-dt pass
1079 14:03:57.224454 <12>[ 72.308141] kselftest: Running tests in dt
1080 14:03:57.253103 TAP version 13
1081 14:03:57.278953 1..1
1082 14:03:57.330500 # timeout set to 45
1083 14:03:57.330882 # selftests: dt: test_unprobed_devices.sh
1084 14:03:58.253912 # TAP version 13
1085 14:04:23.240129 # 1..257
1086 14:04:23.413383 # ok 1 / # SKIP
1087 14:04:23.430707 # ok 2 /clk_mcasp0
1088 14:04:23.503779 # ok 3 /clk_mcasp0_fixed # SKIP
1089 14:04:23.573781 # ok 4 /cpus/cpu@0 # SKIP
1090 14:04:23.650199 # ok 5 /cpus/idle-states/mpu_gate # SKIP
1091 14:04:23.672439 # ok 6 /fixedregulator0
1092 14:04:23.687815 # ok 7 /leds
1093 14:04:23.713988 # ok 8 /ocp
1094 14:04:23.736659 # ok 9 /ocp/interconnect@44c00000
1095 14:04:23.758914 # ok 10 /ocp/interconnect@44c00000/segment@0
1096 14:04:23.779957 # ok 11 /ocp/interconnect@44c00000/segment@100000
1097 14:04:23.808419 # ok 12 /ocp/interconnect@44c00000/segment@100000/target-module@0
1098 14:04:23.877085 # not ok 13 /ocp/interconnect@44c00000/segment@100000/target-module@0/cpu@0
1099 14:04:23.900409 # ok 14 /ocp/interconnect@44c00000/segment@200000
1100 14:04:23.926347 # ok 15 /ocp/interconnect@44c00000/segment@200000/target-module@0
1101 14:04:24.029637 # not ok 16 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0
1102 14:04:24.106763 # ok 17 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0 # SKIP
1103 14:04:24.180561 # ok 18 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@0 # SKIP
1104 14:04:24.252108 # ok 19 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@120 # SKIP
1105 14:04:24.319954 # ok 20 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@14c # SKIP
1106 14:04:24.392541 # ok 21 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@18 # SKIP
1107 14:04:24.467901 # ok 22 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@1c # SKIP
1108 14:04:24.542139 # ok 23 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@24 # SKIP
1109 14:04:24.610994 # ok 24 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@38 # SKIP
1110 14:04:24.687498 # ok 25 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@e8 # SKIP
1111 14:04:24.754580 # ok 26 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400 # SKIP
1112 14:04:24.826938 # ok 27 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@0 # SKIP
1113 14:04:24.898935 # ok 28 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@14 # SKIP
1114 14:04:24.970867 # ok 29 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@b0 # SKIP
1115 14:04:25.049302 # ok 30 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600 # SKIP
1116 14:04:25.116116 # ok 31 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600/clock@0 # SKIP
1117 14:04:25.187060 # ok 32 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800 # SKIP
1118 14:04:25.259134 # ok 33 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800/clock@0 # SKIP
1119 14:04:25.330685 # ok 34 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900 # SKIP
1120 14:04:25.403730 # ok 35 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900/clock@0 # SKIP
1121 14:04:25.474555 # ok 36 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00 # SKIP
1122 14:04:25.547214 # ok 37 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00/clock@0 # SKIP
1123 14:04:25.619620 # ok 38 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-24mhz # SKIP
1124 14:04:25.691237 # ok 39 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-32768 # SKIP
1125 14:04:25.769113 # ok 40 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-rc32k # SKIP
1126 14:04:25.842624 # ok 41 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clkdiv32k # SKIP
1127 14:04:25.912082 # ok 42 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-125mhz-gclk # SKIP
1128 14:04:25.983753 # ok 43 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-cpts-rft@520 # SKIP
1129 14:04:26.055444 # ok 44 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4-div2 # SKIP
1130 14:04:26.128793 # ok 45 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4@480 # SKIP
1131 14:04:26.200317 # ok 46 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m5@484 # SKIP
1132 14:04:26.272573 # ok 47 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m6@4d8 # SKIP
1133 14:04:26.344106 # ok 48 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-x2 # SKIP
1134 14:04:26.416447 # ok 49 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2-div2 # SKIP
1135 14:04:26.488676 # ok 50 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2@4a0 # SKIP
1136 14:04:26.561904 # ok 51 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-disp-m2@4a4 # SKIP
1137 14:04:26.639154 # ok 52 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-mpu-m2@4a8 # SKIP
1138 14:04:26.711384 # ok 53 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4 # SKIP
1139 14:04:26.783772 # ok 54 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4-wkupdm # SKIP
1140 14:04:26.855575 # ok 55 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2@4ac # SKIP
1141 14:04:26.925902 # ok 56 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-gpio0-dbclk-mux@53c # SKIP
1142 14:04:26.999256 # ok 57 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-ieee5000-fck-1@e4 # SKIP
1143 14:04:27.070473 # ok 58 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3-gclk # SKIP
1144 14:04:27.147492 # ok 59 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3s-gclk # SKIP
1145 14:04:27.216243 # ok 60 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4-rtc-gclk # SKIP
1146 14:04:27.289743 # ok 61 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4fw-gclk # SKIP
1147 14:04:27.362104 # ok 62 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4hs-gclk # SKIP
1148 14:04:27.433879 # ok 63 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4ls-gclk # SKIP
1149 14:04:27.510999 # ok 64 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-lcd-gclk@534 # SKIP
1150 14:04:27.582009 # ok 65 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmc # SKIP
1151 14:04:27.651735 # ok 66 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmu-fck-1@914 # SKIP
1152 14:04:27.724557 # ok 67 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-pruss-ocp-gclk@530 # SKIP
1153 14:04:27.796689 # ok 68 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-sysclk-div # SKIP
1154 14:04:27.869135 # ok 69 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-tclkin # SKIP
1155 14:04:27.945452 # ok 70 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer1-fck@528 # SKIP
1156 14:04:28.022109 # ok 71 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer2-fck@508 # SKIP
1157 14:04:28.091840 # ok 72 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer3-fck@50c # SKIP
1158 14:04:28.168657 # ok 73 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer4-fck@510 # SKIP
1159 14:04:28.242712 # ok 74 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer5-fck@518 # SKIP
1160 14:04:28.310117 # ok 75 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer6-fck@51c # SKIP
1161 14:04:28.382560 # ok 76 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer7-fck@504 # SKIP
1162 14:04:28.458839 # ok 77 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-usbotg-fck-8@47c # SKIP
1163 14:04:28.531818 # ok 78 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-19200000 # SKIP
1164 14:04:28.600281 # ok 79 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-24000000 # SKIP
1165 14:04:28.677606 # ok 80 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-25000000 # SKIP
1166 14:04:28.746811 # ok 81 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-26000000 # SKIP
1167 14:04:28.818620 # ok 82 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-wdt1-fck@538 # SKIP
1168 14:04:28.890117 # ok 83 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@488 # SKIP
1169 14:04:28.966263 # ok 84 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@48c # SKIP
1170 14:04:29.034693 # ok 85 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@490 # SKIP
1171 14:04:29.106316 # ok 86 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@494 # SKIP
1172 14:04:29.178115 # ok 87 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@498 # SKIP
1173 14:04:29.251973 # ok 88 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c # SKIP
1174 14:04:29.324843 # ok 89 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fck-div@0 # SKIP
1175 14:04:29.402275 # ok 90 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fclk-clksel@1 # SKIP
1176 14:04:29.467435 # ok 91 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700 # SKIP
1177 14:04:29.542594 # ok 92 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2-div@3 # SKIP
1178 14:04:29.617674 # ok 93 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2@7 # SKIP
1179 14:04:29.686490 # ok 94 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-sysclkout-pre@0 # SKIP
1180 14:04:29.707111 # ok 95 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1000
1181 14:04:29.736485 # ok 96 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1100
1182 14:04:29.759528 # ok 97 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1200
1183 14:04:29.786423 # ok 98 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@c00
1184 14:04:29.809479 # ok 99 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@d00
1185 14:04:29.830623 # ok 100 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@e00
1186 14:04:29.855136 # ok 101 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@f00
1187 14:04:29.877749 # ok 102 /ocp/interconnect@44c00000/segment@200000/target-module@10000
1188 14:04:29.982662 # not ok 103 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0
1189 14:04:30.007731 # ok 104 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/control@620
1190 14:04:30.036905 # ok 105 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/dma-router@f90
1191 14:04:30.060897 # ok 106 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800
1192 14:04:30.170335 # not ok 107 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0
1193 14:04:30.239887 # ok 108 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-adc-tsc-fck # SKIP
1194 14:04:30.311681 # ok 109 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-aes0-fck # SKIP
1195 14:04:30.389091 # ok 110 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan0-fck # SKIP
1196 14:04:30.460982 # ok 111 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan1-fck # SKIP
1197 14:04:30.529321 # ok 112 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp0-fck # SKIP
1198 14:04:30.602970 # ok 113 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp1-fck # SKIP
1199 14:04:30.674393 # ok 114 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-rng-fck # SKIP
1200 14:04:30.747249 # ok 115 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sha0-fck # SKIP
1201 14:04:30.819476 # ok 116 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex0-fck # SKIP
1202 14:04:30.891602 # ok 117 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex1-fck # SKIP
1203 14:04:30.968516 # ok 118 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sys-clkin-22@40 # SKIP
1204 14:04:31.036434 # ok 119 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664 # SKIP
1205 14:04:31.111386 # ok 120 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm0-tbclk@0 # SKIP
1206 14:04:31.184096 # ok 121 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm1-tbclk@1 # SKIP
1207 14:04:31.260292 # ok 122 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm2-tbclk@2 # SKIP
1208 14:04:31.281996 # ok 123 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/phy-gmii-sel
1209 14:04:31.350811 # not ok 124 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/wkup_m3_ipc@1324
1210 14:04:31.421766 # not ok 125 /ocp/interconnect@44c00000/segment@200000/target-module@31000
1211 14:04:31.493203 # ok 126 /ocp/interconnect@44c00000/segment@200000/target-module@31000/timer@0 # SKIP
1212 14:04:31.516253 # ok 127 /ocp/interconnect@44c00000/segment@200000/target-module@35000
1213 14:04:31.588777 # not ok 128 /ocp/interconnect@44c00000/segment@200000/target-module@35000/wdt@0
1214 14:04:31.611247 # ok 129 /ocp/interconnect@44c00000/segment@200000/target-module@3e000
1215 14:04:31.683287 # not ok 130 /ocp/interconnect@44c00000/segment@200000/target-module@3e000/rtc@0
1216 14:04:31.704801 # ok 131 /ocp/interconnect@44c00000/segment@200000/target-module@7000
1217 14:04:31.730066 # ok 132 /ocp/interconnect@44c00000/segment@200000/target-module@7000/gpio@0
1218 14:04:31.752737 # ok 133 /ocp/interconnect@44c00000/segment@200000/target-module@9000
1219 14:04:31.780214 # ok 134 /ocp/interconnect@44c00000/segment@200000/target-module@9000/serial@0
1220 14:04:31.800269 # ok 135 /ocp/interconnect@44c00000/segment@200000/target-module@b000
1221 14:04:31.824592 # ok 136 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0
1222 14:04:31.849337 # ok 137 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/eeprom@50
1223 14:04:31.923952 # ok 138 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/eeprom@50/nvmem-layout # SKIP
1224 14:04:31.946115 # ok 139 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
1225 14:04:31.972509 # ok 140 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24
1226 14:04:32.041405 # not ok 141 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/charger
1227 14:04:32.118342 # not ok 142 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/pwrbutton
1228 14:04:32.139409 # ok 143 /ocp/interconnect@44c00000/segment@200000/target-module@d000
1229 14:04:32.237977 # not ok 144 /ocp/interconnect@47c00000
1230 14:04:32.314959 # not ok 145 /ocp/interconnect@47c00000/segment@0
1231 14:04:32.335235 # ok 146 /ocp/interconnect@48000000
1232 14:04:32.361792 # ok 147 /ocp/interconnect@48000000/segment@0
1233 14:04:32.384222 # ok 148 /ocp/interconnect@48000000/segment@0/target-module@22000
1234 14:04:32.408958 # ok 149 /ocp/interconnect@48000000/segment@0/target-module@24000
1235 14:04:32.430885 # ok 150 /ocp/interconnect@48000000/segment@0/target-module@2a000
1236 14:04:32.452835 # ok 151 /ocp/interconnect@48000000/segment@0/target-module@30000
1237 14:04:32.477155 # ok 152 /ocp/interconnect@48000000/segment@0/target-module@38000
1238 14:04:32.505032 # ok 153 /ocp/interconnect@48000000/segment@0/target-module@38000/mcasp@0
1239 14:04:32.528884 # ok 154 /ocp/interconnect@48000000/segment@0/target-module@3c000
1240 14:04:32.596285 # not ok 155 /ocp/interconnect@48000000/segment@0/target-module@40000
1241 14:04:32.669387 # ok 156 /ocp/interconnect@48000000/segment@0/target-module@40000/timer@0 # SKIP
1242 14:04:32.691840 # ok 157 /ocp/interconnect@48000000/segment@0/target-module@42000
1243 14:04:32.716055 # ok 158 /ocp/interconnect@48000000/segment@0/target-module@42000/timer@0
1244 14:04:32.741487 # ok 159 /ocp/interconnect@48000000/segment@0/target-module@44000
1245 14:04:32.762299 # ok 160 /ocp/interconnect@48000000/segment@0/target-module@44000/timer@0
1246 14:04:32.785898 # ok 161 /ocp/interconnect@48000000/segment@0/target-module@46000
1247 14:04:32.810490 # ok 162 /ocp/interconnect@48000000/segment@0/target-module@46000/timer@0
1248 14:04:32.833133 # ok 163 /ocp/interconnect@48000000/segment@0/target-module@48000
1249 14:04:32.857854 # ok 164 /ocp/interconnect@48000000/segment@0/target-module@48000/timer@0
1250 14:04:32.884640 # ok 165 /ocp/interconnect@48000000/segment@0/target-module@4a000
1251 14:04:32.909636 # ok 166 /ocp/interconnect@48000000/segment@0/target-module@4a000/timer@0
1252 14:04:32.927932 # ok 167 /ocp/interconnect@48000000/segment@0/target-module@4c000
1253 14:04:32.952394 # ok 168 /ocp/interconnect@48000000/segment@0/target-module@4c000/gpio@0
1254 14:04:32.974773 # ok 169 /ocp/interconnect@48000000/segment@0/target-module@60000
1255 14:04:32.998487 # ok 170 /ocp/interconnect@48000000/segment@0/target-module@60000/mmc@0
1256 14:04:33.026176 # ok 171 /ocp/interconnect@48000000/segment@0/target-module@c8000
1257 14:04:33.048705 # ok 172 /ocp/interconnect@48000000/segment@0/target-module@c8000/mailbox@0
1258 14:04:33.076270 # ok 173 /ocp/interconnect@48000000/segment@0/target-module@ca000
1259 14:04:33.094379 # ok 174 /ocp/interconnect@48000000/segment@0/target-module@ca000/spinlock@0
1260 14:04:33.115198 # ok 175 /ocp/interconnect@48000000/segment@100000
1261 14:04:33.144558 # ok 176 /ocp/interconnect@48000000/segment@100000/target-module@9c000
1262 14:04:33.169843 # ok 177 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0
1263 14:04:33.238197 # not ok 178 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/eeprom@54
1264 14:04:33.314618 # ok 179 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/eeprom@54/nvmem-layout # SKIP
1265 14:04:33.383657 # not ok 180 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/eeprom@55
1266 14:04:33.457937 # ok 181 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/eeprom@55/nvmem-layout # SKIP
1267 14:04:33.528646 # not ok 182 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/eeprom@56
1268 14:04:33.609933 # ok 183 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/eeprom@56/nvmem-layout # SKIP
1269 14:04:33.673735 # not ok 184 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/eeprom@57
1270 14:04:33.751586 # ok 185 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/eeprom@57/nvmem-layout # SKIP
1271 14:04:33.768772 # ok 186 /ocp/interconnect@48000000/segment@100000/target-module@a0000
1272 14:04:33.792432 # ok 187 /ocp/interconnect@48000000/segment@100000/target-module@a6000
1273 14:04:33.815666 # ok 188 /ocp/interconnect@48000000/segment@100000/target-module@a8000
1274 14:04:33.839773 # ok 189 /ocp/interconnect@48000000/segment@100000/target-module@aa000
1275 14:04:33.862401 # ok 190 /ocp/interconnect@48000000/segment@100000/target-module@ac000
1276 14:04:33.887573 # ok 191 /ocp/interconnect@48000000/segment@100000/target-module@ac000/gpio@0
1277 14:04:33.915290 # ok 192 /ocp/interconnect@48000000/segment@100000/target-module@ae000
1278 14:04:33.939716 # ok 193 /ocp/interconnect@48000000/segment@100000/target-module@ae000/gpio@0
1279 14:04:33.959048 # ok 194 /ocp/interconnect@48000000/segment@100000/target-module@cc000
1280 14:04:33.986899 # ok 195 /ocp/interconnect@48000000/segment@100000/target-module@d0000
1281 14:04:34.008231 # ok 196 /ocp/interconnect@48000000/segment@100000/target-module@d8000
1282 14:04:34.035336 # ok 197 /ocp/interconnect@48000000/segment@100000/target-module@d8000/mmc@0
1283 14:04:34.057774 # ok 198 /ocp/interconnect@48000000/segment@200000
1284 14:04:34.076798 # ok 199 /ocp/interconnect@48000000/segment@200000/target-module@0
1285 14:04:34.155059 # ok 200 /ocp/interconnect@48000000/segment@200000/target-module@0/mpu@0 # SKIP
1286 14:04:34.175420 # ok 201 /ocp/interconnect@48000000/segment@300000
1287 14:04:34.198869 # ok 202 /ocp/interconnect@48000000/segment@300000/target-module@0
1288 14:04:34.223438 # ok 203 /ocp/interconnect@48000000/segment@300000/target-module@10000
1289 14:04:34.248618 # ok 204 /ocp/interconnect@48000000/segment@300000/target-module@10000/rng@0
1290 14:04:34.268960 # ok 205 /ocp/interconnect@48000000/segment@300000/target-module@2000
1291 14:04:34.290962 # ok 206 /ocp/interconnect@48000000/segment@300000/target-module@4000
1292 14:04:34.318635 # ok 207 /ocp/interconnect@48000000/segment@300000/target-module@e000
1293 14:04:34.390045 # not ok 208 /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
1294 14:04:34.411716 # ok 209 /ocp/interconnect@4a000000
1295 14:04:34.429869 # ok 210 /ocp/interconnect@4a000000/segment@0
1296 14:04:34.458921 # ok 211 /ocp/interconnect@4a000000/segment@0/target-module@100000
1297 14:04:34.481850 # ok 212 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0
1298 14:04:34.506964 # ok 213 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0/mdio@1000
1299 14:04:34.530101 # ok 214 /ocp/interconnect@4a000000/segment@0/target-module@300000
1300 14:04:34.600950 # not ok 215 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0
1301 14:04:34.706917 # ok 216 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/cfg@26000 # SKIP
1302 14:04:34.779727 # not ok 217 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/interrupt-controller@20000
1303 14:04:34.884254 # ok 218 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/mii-rt@32000 # SKIP
1304 14:04:34.954691 # not ok 219 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@34000
1305 14:04:35.036464 # not ok 220 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@38000
1306 14:04:35.125527 # not ok 221 /ocp/interconnect@4b140000
1307 14:04:35.198201 # not ok 222 /ocp/interconnect@4b140000/segment@0
1308 14:04:35.269425 # ok 223 /ocp/interrupt-controller@48200000 # SKIP
1309 14:04:35.294370 # ok 224 /ocp/target-module@40300000
1310 14:04:35.316879 # ok 225 /ocp/target-module@40300000/sram@0
1311 14:04:35.386780 # ok 226 /ocp/target-module@40300000/sram@0/pm-code-sram@0 # SKIP
1312 14:04:35.464104 # ok 227 /ocp/target-module@40300000/sram@0/pm-data-sram@1000 # SKIP
1313 14:04:35.479544 # ok 228 /ocp/target-module@47400000
1314 14:04:35.503645 # ok 229 /ocp/target-module@47400000/dma-controller@2000
1315 14:04:35.526486 # ok 230 /ocp/target-module@47400000/usb-phy@1300
1316 14:04:35.549763 # ok 231 /ocp/target-module@47400000/usb-phy@1b00
1317 14:04:35.575931 # ok 232 /ocp/target-module@47400000/usb@1400
1318 14:04:35.597017 # ok 233 /ocp/target-module@47400000/usb@1800
1319 14:04:35.616300 # ok 234 /ocp/target-module@47810000
1320 14:04:35.642363 # ok 235 /ocp/target-module@49000000
1321 14:04:35.664245 # ok 236 /ocp/target-module@49000000/dma@0
1322 14:04:35.682883 # ok 237 /ocp/target-module@49800000
1323 14:04:35.706743 # ok 238 /ocp/target-module@49800000/dma@0
1324 14:04:35.732894 # ok 239 /ocp/target-module@49900000
1325 14:04:35.755681 # ok 240 /ocp/target-module@49900000/dma@0
1326 14:04:35.772374 # ok 241 /ocp/target-module@49a00000
1327 14:04:35.796934 # ok 242 /ocp/target-module@49a00000/dma@0
1328 14:04:35.823159 # ok 243 /ocp/target-module@4c000000
1329 14:04:35.894939 # not ok 244 /ocp/target-module@4c000000/emif@0
1330 14:04:35.916381 # ok 245 /ocp/target-module@50000000
1331 14:04:35.943399 # ok 246 /ocp/target-module@53100000
1332 14:04:36.013635 # not ok 247 /ocp/target-module@53100000/sham@0
1333 14:04:36.035785 # ok 248 /ocp/target-module@53500000
1334 14:04:36.107417 # not ok 249 /ocp/target-module@53500000/aes@0
1335 14:04:36.126062 # ok 250 /ocp/target-module@56000000
1336 14:04:36.231381 # ok 251 /ocp/target-module@56000000/gpu@0 # SKIP
1337 14:04:36.304428 # ok 252 /opp-table # SKIP
1338 14:04:36.375166 # ok 253 /soc # SKIP
1339 14:04:36.394883 # ok 254 /sound
1340 14:04:36.415670 # ok 255 /target-module@4b000000
1341 14:04:36.444576 # ok 256 /target-module@4b000000/target-module@140000
1342 14:04:36.460857 # ok 257 /target-module@4b000000/target-module@140000/pmu@0
1343 14:04:36.469476 # # Totals: pass:117 fail:27 xfail:0 xpass:0 skip:113 error:0
1344 14:04:36.476560 not ok 1 selftests: dt: test_unprobed_devices.sh # exit=1
1345 14:04:38.713209 dt_test_unprobed_devices_sh_ skip
1346 14:04:38.718896 dt_test_unprobed_devices_sh_clk_mcasp0 pass
1347 14:04:38.724415 dt_test_unprobed_devices_sh_clk_mcasp0_fixed skip
1348 14:04:38.724968 dt_test_unprobed_devices_sh_cpus_cpu_0 skip
1349 14:04:38.733276 dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate skip
1350 14:04:38.733797 dt_test_unprobed_devices_sh_fixedregulator0 pass
1351 14:04:38.738837 dt_test_unprobed_devices_sh_leds pass
1352 14:04:38.744426 dt_test_unprobed_devices_sh_ocp pass
1353 14:04:38.750092 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 pass
1354 14:04:38.755710 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 pass
1355 14:04:38.761365 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 pass
1356 14:04:38.766869 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 pass
1357 14:04:38.777923 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 fail
1358 14:04:38.783522 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 pass
1359 14:04:38.789194 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 pass
1360 14:04:38.800385 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 fail
1361 14:04:38.811626 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 skip
1362 14:04:38.817296 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 skip
1363 14:04:38.828429 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 skip
1364 14:04:38.839641 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c skip
1365 14:04:38.850867 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 skip
1366 14:04:38.862059 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c skip
1367 14:04:38.867662 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 skip
1368 14:04:38.878887 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 skip
1369 14:04:38.890115 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 skip
1370 14:04:38.901257 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 skip
1371 14:04:38.906880 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 skip
1372 14:04:38.918159 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 skip
1373 14:04:38.929221 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 skip
1374 14:04:38.940386 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 skip
1375 14:04:38.951585 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 skip
1376 14:04:38.957236 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 skip
1377 14:04:38.968422 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 skip
1378 14:04:38.979567 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 skip
1379 14:04:38.990798 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 skip
1380 14:04:38.996465 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 skip
1381 14:04:39.007533 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 skip
1382 14:04:39.018746 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz skip
1383 14:04:39.029968 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 skip
1384 14:04:39.041118 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k skip
1385 14:04:39.052320 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k skip
1386 14:04:39.063511 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk skip
1387 14:04:39.074723 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 skip
1388 14:04:39.085847 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 skip
1389 14:04:39.097122 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 skip
1390 14:04:39.108351 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 skip
1391 14:04:39.119473 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 skip
1392 14:04:39.130698 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 skip
1393 14:04:39.141838 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 skip
1394 14:04:39.153099 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 skip
1395 14:04:39.164280 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 skip
1396 14:04:39.175422 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 skip
1397 14:04:39.186630 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 skip
1398 14:04:39.197767 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm skip
1399 14:04:39.208962 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac skip
1400 14:04:39.220222 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c skip
1401 14:04:39.231395 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 skip
1402 14:04:39.242568 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk skip
1403 14:04:39.248240 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk skip
1404 14:04:39.259351 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk skip
1405 14:04:39.270531 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk skip
1406 14:04:39.281727 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk skip
1407 14:04:39.292936 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk skip
1408 14:04:39.304124 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 skip
1409 14:04:39.315340 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc skip
1410 14:04:39.326469 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 skip
1411 14:04:39.337643 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 skip
1412 14:04:39.348842 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div skip
1413 14:04:39.359975 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin skip
1414 14:04:39.365598 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 skip
1415 14:04:39.376885 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 skip
1416 14:04:39.388086 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c skip
1417 14:04:39.399175 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 skip
1418 14:04:39.410451 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 skip
1419 14:04:39.421597 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c skip
1420 14:04:39.432746 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 skip
1421 14:04:39.443944 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c skip
1422 14:04:39.455128 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 skip
1423 14:04:39.466316 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 skip
1424 14:04:39.477529 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 skip
1425 14:04:39.488728 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 skip
1426 14:04:39.499903 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 skip
1427 14:04:39.511146 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 skip
1428 14:04:39.522291 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c skip
1429 14:04:39.527965 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 skip
1430 14:04:39.539092 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 skip
1431 14:04:39.550349 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 skip
1432 14:04:39.561429 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c skip
1433 14:04:39.572726 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 skip
1434 14:04:39.583909 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 skip
1435 14:04:39.595037 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 skip
1436 14:04:39.606192 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 skip
1437 14:04:39.617536 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 skip
1438 14:04:39.628628 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 skip
1439 14:04:39.639800 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 pass
1440 14:04:39.651009 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 pass
1441 14:04:39.656666 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 pass
1442 14:04:39.667768 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 pass
1443 14:04:39.678952 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 pass
1444 14:04:39.684597 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 pass
1445 14:04:39.695771 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 pass
1446 14:04:39.701411 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 pass
1447 14:04:39.712550 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 fail
1448 14:04:39.723792 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 pass
1449 14:04:39.729311 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 pass
1450 14:04:39.740589 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 pass
1451 14:04:39.751716 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 fail
1452 14:04:39.762930 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck skip
1453 14:04:39.774074 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck skip
1454 14:04:39.785279 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck skip
1455 14:04:39.796551 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck skip
1456 14:04:39.813253 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck skip
1457 14:04:39.824528 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck skip
1458 14:04:39.835670 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck skip
1459 14:04:39.846862 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck skip
1460 14:04:39.858055 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck skip
1461 14:04:39.869282 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck skip
1462 14:04:39.880472 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 skip
1463 14:04:39.897253 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 skip
1464 14:04:39.908427 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 skip
1465 14:04:39.919610 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 skip
1466 14:04:39.936406 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 skip
1467 14:04:39.947600 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel pass
1468 14:04:39.953227 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 fail
1469 14:04:39.964374 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 fail
1470 14:04:39.970005 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 skip
1471 14:04:39.981151 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 pass
1472 14:04:39.992332 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 fail
1473 14:04:39.998000 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 pass
1474 14:04:40.009091 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 fail
1475 14:04:40.014713 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 pass
1476 14:04:40.025884 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 pass
1477 14:04:40.031553 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 pass
1478 14:04:40.042706 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 pass
1479 14:04:40.048360 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 pass
1480 14:04:40.059490 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 pass
1481 14:04:40.065141 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_eeprom_50 pass
1482 14:04:40.076265 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_eeprom_50_nvmem-layout skip
1483 14:04:40.087456 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 pass
1484 14:04:40.098616 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 pass
1485 14:04:40.109881 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger fail
1486 14:04:40.115500 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton fail
1487 14:04:40.126609 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 pass
1488 14:04:40.132285 dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 fail
1489 14:04:40.137911 dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 fail
1490 14:04:40.143402 dt_test_unprobed_devices_sh_ocp_interconnect_48000000 pass
1491 14:04:40.149058 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 pass
1492 14:04:40.154677 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 pass
1493 14:04:40.165817 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 pass
1494 14:04:40.171434 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 pass
1495 14:04:40.182563 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 pass
1496 14:04:40.188320 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 pass
1497 14:04:40.199345 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 pass
1498 14:04:40.205035 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 pass
1499 14:04:40.210711 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 fail
1500 14:04:40.221734 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 skip
1501 14:04:40.227422 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 pass
1502 14:04:40.238606 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 pass
1503 14:04:40.244214 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 pass
1504 14:04:40.255307 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 pass
1505 14:04:40.260937 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 pass
1506 14:04:40.272106 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 pass
1507 14:04:40.277749 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 pass
1508 14:04:40.288889 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 pass
1509 14:04:40.294478 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 pass
1510 14:04:40.305707 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 pass
1511 14:04:40.311330 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 pass
1512 14:04:40.316852 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 pass
1513 14:04:40.328062 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 pass
1514 14:04:40.333762 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 pass
1515 14:04:40.344905 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 pass
1516 14:04:40.350522 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 pass
1517 14:04:40.361585 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 pass
1518 14:04:40.367268 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 pass
1519 14:04:40.378445 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 pass
1520 14:04:40.384149 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 pass
1521 14:04:40.395201 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 pass
1522 14:04:40.400909 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_54 fail
1523 14:04:40.412047 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_54_nvmem-layout skip
1524 14:04:40.423171 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_55 fail
1525 14:04:40.434380 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_55_nvmem-layout skip
1526 14:04:40.445631 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_56 fail
1527 14:04:40.456770 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_56_nvmem-layout skip
1528 14:04:40.462326 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_57 fail
1529 14:04:40.473593 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_57_nvmem-layout skip
1530 14:04:40.484724 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 pass
1531 14:04:40.490404 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 pass
1532 14:04:40.501499 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 pass
1533 14:04:40.507188 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 pass
1534 14:04:40.518299 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 pass
1535 14:04:40.523861 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 pass
1536 14:04:40.535186 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 pass
1537 14:04:40.540767 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 pass
1538 14:04:40.551871 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 pass
1539 14:04:40.557519 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 pass
1540 14:04:40.568660 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 pass
1541 14:04:40.574348 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 pass
1542 14:04:40.585380 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 pass
1543 14:04:40.591067 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 pass
1544 14:04:40.602238 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 skip
1545 14:04:40.607791 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 pass
1546 14:04:40.613476 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 pass
1547 14:04:40.624636 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 pass
1548 14:04:40.630189 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 pass
1549 14:04:40.641382 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 pass
1550 14:04:40.647032 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 pass
1551 14:04:40.658221 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 pass
1552 14:04:40.663873 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 fail
1553 14:04:40.669418 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 pass
1554 14:04:40.675072 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 pass
1555 14:04:40.686174 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 pass
1556 14:04:40.691772 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 pass
1557 14:04:40.702955 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 pass
1558 14:04:40.708724 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 pass
1559 14:04:40.719744 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 fail
1560 14:04:40.730932 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 skip
1561 14:04:40.742160 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 fail
1562 14:04:40.747760 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 skip
1563 14:04:40.758982 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 fail
1564 14:04:40.770182 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 fail
1565 14:04:40.775871 dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 fail
1566 14:04:40.781644 dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 fail
1567 14:04:40.786998 dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 skip
1568 14:04:40.792670 dt_test_unprobed_devices_sh_ocp_target-module_40300000 pass
1569 14:04:40.798262 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 pass
1570 14:04:40.803856 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 skip
1571 14:04:40.809388 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 skip
1572 14:04:40.815019 dt_test_unprobed_devices_sh_ocp_target-module_47400000 pass
1573 14:04:40.826301 dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 pass
1574 14:04:40.831853 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 pass
1575 14:04:40.837469 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 pass
1576 14:04:40.843143 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 pass
1577 14:04:40.848692 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 pass
1578 14:04:40.854191 dt_test_unprobed_devices_sh_ocp_target-module_47810000 pass
1579 14:04:40.859765 dt_test_unprobed_devices_sh_ocp_target-module_49000000 pass
1580 14:04:40.865338 dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 pass
1581 14:04:40.871009 dt_test_unprobed_devices_sh_ocp_target-module_49800000 pass
1582 14:04:40.876582 dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 pass
1583 14:04:40.882244 dt_test_unprobed_devices_sh_ocp_target-module_49900000 pass
1584 14:04:40.887815 dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 pass
1585 14:04:40.893405 dt_test_unprobed_devices_sh_ocp_target-module_49a00000 pass
1586 14:04:40.899871 dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 pass
1587 14:04:40.904720 dt_test_unprobed_devices_sh_ocp_target-module_4c000000 pass
1588 14:04:40.910296 dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 fail
1589 14:04:40.915900 dt_test_unprobed_devices_sh_ocp_target-module_50000000 pass
1590 14:04:40.921479 dt_test_unprobed_devices_sh_ocp_target-module_53100000 pass
1591 14:04:40.927091 dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 fail
1592 14:04:40.932641 dt_test_unprobed_devices_sh_ocp_target-module_53500000 pass
1593 14:04:40.938294 dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 fail
1594 14:04:40.943875 dt_test_unprobed_devices_sh_ocp_target-module_56000000 pass
1595 14:04:40.949459 dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 skip
1596 14:04:40.955061 dt_test_unprobed_devices_sh_opp-table skip
1597 14:04:40.955641 dt_test_unprobed_devices_sh_soc skip
1598 14:04:40.960692 dt_test_unprobed_devices_sh_sound pass
1599 14:04:40.966279 dt_test_unprobed_devices_sh_target-module_4b000000 pass
1600 14:04:40.971940 dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 pass
1601 14:04:40.977465 dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 pass
1602 14:04:40.983081 dt_test_unprobed_devices_sh fail
1603 14:04:40.988684 + ../../utils/send-to-lava.sh ./output/result.txt
1604 14:04:40.994257 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-dt RESULT=pass>
1605 14:04:40.995227 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-dt RESULT=pass
1607 14:04:40.998957 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip>
1608 14:04:40.999772 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip
1610 14:04:41.072406 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass>
1611 14:04:41.073309 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass
1613 14:04:41.162875 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip>
1614 14:04:41.163760 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip
1616 14:04:41.247717 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip>
1617 14:04:41.248640 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip
1619 14:04:41.335000 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip>
1620 14:04:41.335871 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip
1622 14:04:41.424270 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass>
1623 14:04:41.425189 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass
1625 14:04:41.507884 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass>
1626 14:04:41.508810 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass
1628 14:04:41.600230 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass>
1629 14:04:41.601113 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass
1631 14:04:41.691524 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass>
1632 14:04:41.692418 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass
1634 14:04:41.784496 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass>
1635 14:04:41.785379 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass
1637 14:04:41.875716 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass>
1638 14:04:41.876626 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass
1640 14:04:41.967273 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass>
1641 14:04:41.968149 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass
1643 14:04:42.052524 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail>
1644 14:04:42.053378 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail
1646 14:04:42.140760 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass>
1647 14:04:42.141631 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass
1649 14:04:42.228948 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass>
1650 14:04:42.229789 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass
1652 14:04:42.319713 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail>
1653 14:04:42.320612 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail
1655 14:04:42.407517 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip>
1656 14:04:42.408464 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip
1658 14:04:42.497398 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip>
1659 14:04:42.498278 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip
1661 14:04:42.588616 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip>
1662 14:04:42.589505 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip
1664 14:04:42.679275 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip>
1665 14:04:42.680133 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip
1667 14:04:42.763111 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip>
1668 14:04:42.763953 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip
1670 14:04:42.857519 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip>
1671 14:04:42.858389 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip
1673 14:04:42.947911 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip>
1674 14:04:42.948824 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip
1676 14:04:43.038396 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip>
1677 14:04:43.039292 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip
1679 14:04:43.122610 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip>
1680 14:04:43.123507 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip
1682 14:04:43.207155 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip>
1683 14:04:43.208111 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip
1685 14:04:43.293943 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip>
1686 14:04:43.294838 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip
1688 14:04:43.379554 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip>
1689 14:04:43.380541 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip
1691 14:04:43.470431 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip>
1692 14:04:43.471325 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip
1694 14:04:43.555306 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip>
1695 14:04:43.556200 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip
1697 14:04:43.647397 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip>
1698 14:04:43.648306 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip
1700 14:04:43.738682 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip>
1701 14:04:43.739557 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip
1703 14:04:43.828283 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip>
1704 14:04:43.829151 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip
1706 14:04:43.912440 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip>
1707 14:04:43.913314 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip
1709 14:04:43.996867 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip>
1710 14:04:43.997716 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip
1712 14:04:44.088672 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip>
1713 14:04:44.089573 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip
1715 14:04:44.179854 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip>
1716 14:04:44.180825 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip
1718 14:04:44.265558 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip>
1719 14:04:44.266449 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip
1721 14:04:44.355773 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip>
1722 14:04:44.356696 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip
1724 14:04:44.447918 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip>
1725 14:04:44.448874 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip
1727 14:04:44.537524 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip>
1728 14:04:44.538436 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip
1730 14:04:44.629225 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip>
1731 14:04:44.630128 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip
1733 14:04:44.714468 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip>
1734 14:04:44.715358 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip
1736 14:04:44.800577 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip>
1737 14:04:44.801448 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip
1739 14:04:44.891531 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip>
1740 14:04:44.892450 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip
1742 14:04:44.976857 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip>
1743 14:04:44.977725 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip
1745 14:04:45.068619 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip>
1746 14:04:45.069500 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip
1748 14:04:45.159427 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip>
1749 14:04:45.160332 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip
1751 14:04:45.250221 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip>
1752 14:04:45.251063 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip
1754 14:04:45.340261 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip>
1755 14:04:45.341171 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip
1757 14:04:45.431621 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip>
1758 14:04:45.432319 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip
1760 14:04:45.519592 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip>
1761 14:04:45.520264 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip
1763 14:04:45.609889 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip>
1764 14:04:45.610522 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip
1766 14:04:45.700137 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip>
1767 14:04:45.700769 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip
1769 14:04:45.785463 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip>
1770 14:04:45.786158 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip
1772 14:04:45.877175 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip>
1773 14:04:45.877843 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip
1775 14:04:45.973444 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip>
1776 14:04:45.974070 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip
1778 14:04:46.067116 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip>
1779 14:04:46.068030 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip
1781 14:04:46.160530 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip>
1782 14:04:46.161413 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip
1784 14:04:46.249502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip>
1785 14:04:46.250378 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip
1787 14:04:46.344376 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip>
1788 14:04:46.345074 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip
1790 14:04:46.442825 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip>
1791 14:04:46.443528 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip
1793 14:04:46.535002 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip>
1794 14:04:46.535687 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip
1796 14:04:46.627255 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip>
1797 14:04:46.628217 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip
1799 14:04:46.717898 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip>
1800 14:04:46.718830 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip
1802 14:04:46.808445 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip>
1803 14:04:46.809365 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip
1805 14:04:46.894802 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip>
1806 14:04:46.895717 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip
1808 14:04:46.979397 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip>
1809 14:04:46.980377 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip
1811 14:04:47.070646 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip>
1812 14:04:47.071549 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip
1814 14:04:47.162140 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip>
1815 14:04:47.163004 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip
1817 14:04:47.245878 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip>
1818 14:04:47.246711 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip
1820 14:04:47.330217 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip>
1821 14:04:47.331063 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip
1823 14:04:47.420247 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip>
1824 14:04:47.421175 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip
1826 14:04:47.505209 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip>
1827 14:04:47.506136 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip
1829 14:04:47.595905 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip>
1830 14:04:47.596811 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip
1832 14:04:47.680785 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip>
1833 14:04:47.681642 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip
1835 14:04:47.770673 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip>
1836 14:04:47.771507 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip
1838 14:04:47.855172 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip>
1839 14:04:47.856040 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip
1841 14:04:47.944625 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip>
1842 14:04:47.945523 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip
1844 14:04:48.030094 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip>
1845 14:04:48.030942 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip
1847 14:04:48.120331 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip>
1848 14:04:48.121248 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip
1850 14:04:48.205980 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip>
1851 14:04:48.206863 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip
1853 14:04:48.297764 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip>
1854 14:04:48.298571 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip
1856 14:04:48.388588 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip>
1857 14:04:48.389463 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip
1859 14:04:48.478885 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip>
1860 14:04:48.479714 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip
1862 14:04:48.565201 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip>
1863 14:04:48.566107 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip
1865 14:04:48.649667 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip>
1866 14:04:48.650456 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip
1868 14:04:48.740658 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip>
1869 14:04:48.741483 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip
1871 14:04:48.828485 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip>
1872 14:04:48.829357 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip
1874 14:04:48.918859 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip>
1875 14:04:48.919700 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip
1877 14:04:49.009430 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip>
1878 14:04:49.010296 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip
1880 14:04:49.101753 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip>
1881 14:04:49.102652 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip
1883 14:04:49.186362 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip>
1884 14:04:49.187453 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip
1886 14:04:49.276787 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip>
1887 14:04:49.277410 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip
1889 14:04:49.363749 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass>
1890 14:04:49.364409 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass
1892 14:04:49.449380 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass>
1893 14:04:49.450035 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass
1895 14:04:49.534135 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass>
1896 14:04:49.534786 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass
1898 14:04:49.624478 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass>
1899 14:04:49.625121 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass
1901 14:04:49.714982 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass>
1902 14:04:49.715644 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass
1904 14:04:49.800191 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass>
1905 14:04:49.800817 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass
1907 14:04:49.885177 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass>
1908 14:04:49.885784 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass
1910 14:04:49.975677 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass>
1911 14:04:49.976336 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass
1913 14:04:50.067322 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail>
1914 14:04:50.067960 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail
1916 14:04:50.158958 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass>
1917 14:04:50.159558 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass
1919 14:04:50.249943 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass>
1920 14:04:50.250548 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass
1922 14:04:50.334883 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass>
1923 14:04:50.335478 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass
1925 14:04:50.425248 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail>
1926 14:04:50.425893 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail
1928 14:04:50.519857 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip>
1929 14:04:50.520540 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip
1931 14:04:50.609918 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip>
1932 14:04:50.610566 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip
1934 14:04:50.701595 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip>
1935 14:04:50.702220 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip
1937 14:04:50.787098 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip>
1938 14:04:50.787707 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip
1940 14:04:50.878706 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip>
1941 14:04:50.879281 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip
1943 14:04:50.970099 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip>
1944 14:04:50.970678 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip
1946 14:04:51.061738 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip>
1947 14:04:51.062658 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip
1949 14:04:51.153424 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip>
1950 14:04:51.154440 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip
1952 14:04:51.247508 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip>
1953 14:04:51.248556 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip
1955 14:04:51.336806 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip>
1956 14:04:51.337683 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip
1958 14:04:51.423165 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip>
1959 14:04:51.424085 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip
1961 14:04:51.513006 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip>
1962 14:04:51.513961 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip
1964 14:04:51.597877 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip
1966 14:04:51.600992 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip>
1967 14:04:51.688046 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip
1969 14:04:51.691096 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip>
1970 14:04:51.778317 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip
1972 14:04:51.781431 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip>
1973 14:04:51.870508 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass>
1974 14:04:51.871468 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass
1976 14:04:51.954570 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail>
1977 14:04:51.955526 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail
1979 14:04:52.043350 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail>
1980 14:04:52.044290 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail
1982 14:04:52.136943 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip>
1983 14:04:52.137919 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip
1985 14:04:52.227842 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass>
1986 14:04:52.228794 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass
1988 14:04:52.313822 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail>
1989 14:04:52.314729 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail
1991 14:04:52.405791 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass>
1992 14:04:52.406698 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass
1994 14:04:52.496746 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail>
1995 14:04:52.497661 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail
1997 14:04:52.582254 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass>
1998 14:04:52.583163 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass
2000 14:04:52.668578 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass>
2001 14:04:52.669477 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass
2003 14:04:52.758992 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass>
2004 14:04:52.760051 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass
2006 14:04:52.851175 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass>
2007 14:04:52.852244 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass
2009 14:04:52.935547 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass>
2010 14:04:52.936502 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass
2012 14:04:53.027108 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass>
2013 14:04:53.028025 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass
2015 14:04:53.118435 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_eeprom_50 RESULT=pass>
2016 14:04:53.119326 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_eeprom_50 RESULT=pass
2018 14:04:53.205300 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_eeprom_50_nvmem-layout RESULT=skip>
2019 14:04:53.206290 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_eeprom_50_nvmem-layout RESULT=skip
2021 14:04:53.294630 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass>
2022 14:04:53.295513 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass
2024 14:04:53.386111 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass>
2025 14:04:53.387089 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass
2027 14:04:53.478145 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail>
2028 14:04:53.478991 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail
2030 14:04:53.568694 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail>
2031 14:04:53.569601 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail
2033 14:04:53.652236 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass>
2034 14:04:53.653050 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass
2036 14:04:53.738830 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail>
2037 14:04:53.739676 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail
2039 14:04:53.824697 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail>
2040 14:04:53.825590 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail
2042 14:04:53.914370 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass>
2043 14:04:53.915212 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass
2045 14:04:54.000115 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass>
2046 14:04:54.000903 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass
2048 14:04:54.093190 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass>
2049 14:04:54.094019 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass
2051 14:04:54.186001 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass>
2052 14:04:54.186776 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass
2054 14:04:54.276468 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass>
2055 14:04:54.277279 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass
2057 14:04:54.361958 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass>
2058 14:04:54.362819 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass
2060 14:04:54.453064 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass>
2061 14:04:54.453940 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass
2063 14:04:54.539375 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass>
2064 14:04:54.540283 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass
2066 14:04:54.628506 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass>
2067 14:04:54.629370 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass
2069 14:04:54.714095 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail>
2070 14:04:54.714923 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail
2072 14:04:54.805148 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip>
2073 14:04:54.805989 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip
2075 14:04:54.897003 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass>
2076 14:04:54.897851 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass
2078 14:04:54.983089 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass>
2079 14:04:54.983901 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass
2081 14:04:55.072826 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass>
2082 14:04:55.073665 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass
2084 14:04:55.163838 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass>
2085 14:04:55.164710 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass
2087 14:04:55.252727 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass>
2088 14:04:55.253540 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass
2090 14:04:55.338773 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass>
2091 14:04:55.339651 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass
2093 14:04:55.425057 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass>
2094 14:04:55.425981 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass
2096 14:04:55.515816 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass>
2097 14:04:55.516734 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass
2099 14:04:55.605217 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass>
2100 14:04:55.606122 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass
2102 14:04:55.690425 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass>
2103 14:04:55.691419 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass
2105 14:04:55.775900 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass>
2106 14:04:55.776809 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass
2108 14:04:55.868571 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass>
2109 14:04:55.869545 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass
2111 14:04:55.958737 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass>
2112 14:04:55.959614 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass
2114 14:04:56.045033 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass>
2115 14:04:56.045945 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass
2117 14:04:56.137648 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass>
2118 14:04:56.138530 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass
2120 14:04:56.223273 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass>
2121 14:04:56.224154 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass
2123 14:04:56.313033 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass>
2124 14:04:56.313917 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass
2126 14:04:56.405153 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass>
2127 14:04:56.406067 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass
2129 14:04:56.493745 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass>
2130 14:04:56.494632 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass
2132 14:04:56.586697 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass>
2133 14:04:56.587594 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass
2135 14:04:56.671922 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass>
2136 14:04:56.672836 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass
2138 14:04:56.758108 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_54 RESULT=fail>
2139 14:04:56.758970 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_54 RESULT=fail
2141 14:04:56.850941 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_54_nvmem-layout RESULT=skip>
2142 14:04:56.851831 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_54_nvmem-layout RESULT=skip
2144 14:04:56.935963 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_55 RESULT=fail>
2145 14:04:56.936852 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_55 RESULT=fail
2147 14:04:57.026888 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_55_nvmem-layout RESULT=skip>
2148 14:04:57.027802 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_55_nvmem-layout RESULT=skip
2150 14:04:57.119178 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_56 RESULT=fail>
2151 14:04:57.120112 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_56 RESULT=fail
2153 14:04:57.205649 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_56_nvmem-layout RESULT=skip>
2154 14:04:57.206632 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_56_nvmem-layout RESULT=skip
2156 14:04:57.295012 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_57 RESULT=fail>
2157 14:04:57.296035 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_57 RESULT=fail
2159 14:04:57.389057 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_57_nvmem-layout RESULT=skip>
2160 14:04:57.390006 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_57_nvmem-layout RESULT=skip
2162 14:04:57.476728 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass>
2163 14:04:57.477643 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass
2165 14:04:57.561695 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass>
2166 14:04:57.562632 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass
2168 14:04:57.645957 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass>
2169 14:04:57.646858 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass
2171 14:04:57.730576 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass>
2172 14:04:57.731458 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass
2174 14:04:57.816229 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass>
2175 14:04:57.817079 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass
2177 14:04:57.909550 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass>
2178 14:04:57.910433 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass
2180 14:04:57.996541 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass>
2181 14:04:57.997452 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass
2183 14:04:58.087074 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass>
2184 14:04:58.088109 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass
2186 14:04:58.177030 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass>
2187 14:04:58.177979 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass
2189 14:04:58.262284 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass>
2190 14:04:58.263266 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass
2192 14:04:58.352800 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass>
2193 14:04:58.353735 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass
2195 14:04:58.438859 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass>
2196 14:04:58.439912 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass
2198 14:04:58.526733 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass>
2199 14:04:58.527664 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass
2201 14:04:58.612089 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass>
2202 14:04:58.612951 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass
2204 14:04:58.702785 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip>
2205 14:04:58.703644 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip
2207 14:04:58.793599 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass>
2208 14:04:58.794469 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass
2210 14:04:58.885767 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass>
2211 14:04:58.886630 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass
2213 14:04:58.977734 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass>
2214 14:04:58.978635 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass
2216 14:04:59.069346 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass>
2217 14:04:59.070196 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass
2219 14:04:59.155368 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass>
2220 14:04:59.156404 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass
2222 14:04:59.245423 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass>
2223 14:04:59.246250 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass
2225 14:04:59.335224 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass>
2226 14:04:59.336091 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass
2228 14:04:59.426012 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail>
2229 14:04:59.427147 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail
2231 14:04:59.517658 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass>
2232 14:04:59.518569 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass
2234 14:04:59.609477 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass>
2235 14:04:59.610382 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass
2237 14:04:59.701479 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass>
2238 14:04:59.702257 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass
2240 14:04:59.787030 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass>
2241 14:04:59.787912 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass
2243 14:04:59.873760 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass>
2244 14:04:59.874542 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass
2246 14:04:59.957450 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass>
2247 14:04:59.958220 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass
2249 14:05:00.048430 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail>
2250 14:05:00.049241 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail
2252 14:05:00.134531 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip>
2253 14:05:00.135340 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip
2255 14:05:00.227918 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail>
2256 14:05:00.228744 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail
2258 14:05:00.317864 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip>
2259 14:05:00.318620 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip
2261 14:05:00.401842 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail>
2262 14:05:00.402707 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail
2264 14:05:00.493052 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail>
2265 14:05:00.493913 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail
2267 14:05:00.575956 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail>
2268 14:05:00.577135 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail
2270 14:05:00.666573 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail>
2271 14:05:00.667394 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail
2273 14:05:00.750637 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip>
2274 14:05:00.751557 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip
2276 14:05:00.842779 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass>
2277 14:05:00.843701 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass
2279 14:05:00.933747 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass>
2280 14:05:00.934654 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass
2282 14:05:01.025322 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip>
2283 14:05:01.026256 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip
2285 14:05:01.107297 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip
2287 14:05:01.110383 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip>
2288 14:05:01.193053 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass>
2289 14:05:01.193970 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass
2291 14:05:01.288589 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass>
2292 14:05:01.289509 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass
2294 14:05:01.374278 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass>
2295 14:05:01.375211 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass
2297 14:05:01.462991 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass>
2298 14:05:01.463855 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass
2300 14:05:01.553753 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass>
2301 14:05:01.554465 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass
2303 14:05:01.644565 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass>
2304 14:05:01.645199 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass
2306 14:05:01.740885 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass>
2307 14:05:01.741507 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass
2309 14:05:01.832348 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass>
2310 14:05:01.832979 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass
2312 14:05:01.924413 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass>
2313 14:05:01.925055 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass
2315 14:05:02.015395 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass>
2316 14:05:02.016407 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass
2318 14:05:02.101009 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass>
2319 14:05:02.102035 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass
2321 14:05:02.191623 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass>
2322 14:05:02.192718 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass
2324 14:05:02.282135 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass>
2325 14:05:02.282729 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass
2327 14:05:02.370981 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass>
2328 14:05:02.371618 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass
2330 14:05:02.456405 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass>
2331 14:05:02.457336 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass
2333 14:05:02.546248 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass>
2334 14:05:02.546898 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass
2336 14:05:02.635242 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail>
2337 14:05:02.636027 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail
2339 14:05:02.829355 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass>
2340 14:05:02.829977 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass
2342 14:05:02.930907 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass>
2343 14:05:02.931737 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass
2345 14:05:03.026670 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail>
2346 14:05:03.027534 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail
2348 14:05:03.116974 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass>
2349 14:05:03.117764 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass
2351 14:05:03.208635 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail>
2352 14:05:03.209470 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail
2354 14:05:03.302045 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass>
2355 14:05:03.302862 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass
2357 14:05:03.393899 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip>
2358 14:05:03.394755 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip
2360 14:05:03.477631 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip>
2361 14:05:03.478474 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip
2363 14:05:03.561115 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip>
2364 14:05:03.561952 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip
2366 14:05:03.649616 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass>
2367 14:05:03.650453 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass
2369 14:05:03.746222 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass>
2370 14:05:03.747019 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass
2372 14:05:03.839644 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass>
2373 14:05:03.840530 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass
2375 14:05:03.933393 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass>
2376 14:05:03.934287 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass
2378 14:05:04.022695 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail>
2379 14:05:04.023309 + set +x
2380 14:05:04.023967 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail
2382 14:05:04.030053 <LAVA_SIGNAL_ENDRUN 1_kselftest-dt 952823_1.6.2.4.5>
2383 14:05:04.030447 <LAVA_TEST_RUNNER EXIT>
2384 14:05:04.030976 Received signal: <ENDRUN> 1_kselftest-dt 952823_1.6.2.4.5
2385 14:05:04.031336 Ending use of test pattern.
2386 14:05:04.031626 Ending test lava.1_kselftest-dt (952823_1.6.2.4.5), duration 83.80
2388 14:05:04.032673 ok: lava_test_shell seems to have completed
2389 14:05:04.048265 dt_test_unprobed_devices_sh: fail
dt_test_unprobed_devices_sh_: skip
dt_test_unprobed_devices_sh_clk_mcasp0: pass
dt_test_unprobed_devices_sh_clk_mcasp0_fixed: skip
dt_test_unprobed_devices_sh_cpus_cpu_0: skip
dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate: skip
dt_test_unprobed_devices_sh_fixedregulator0: pass
dt_test_unprobed_devices_sh_leds: pass
dt_test_unprobed_devices_sh_ocp: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0: fail
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_eeprom_50: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_eeprom_50_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_54: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_54_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_55: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_55_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_56: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_56_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_57: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_57_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000: skip
dt_test_unprobed_devices_sh_ocp_target-module_47400000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800: pass
dt_test_unprobed_devices_sh_ocp_target-module_47810000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_50000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_53500000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_56000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0: skip
dt_test_unprobed_devices_sh_opp-table: skip
dt_test_unprobed_devices_sh_soc: skip
dt_test_unprobed_devices_sh_sound: pass
dt_test_unprobed_devices_sh_target-module_4b000000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0: pass
shardfile-dt: pass
2390 14:05:04.050629 end: 3.1 lava-test-shell (duration 00:01:25) [common]
2391 14:05:04.051345 end: 3 lava-test-retry (duration 00:01:25) [common]
2392 14:05:04.052179 start: 4 finalize (timeout 00:05:30) [common]
2393 14:05:04.052914 start: 4.1 power-off (timeout 00:00:30) [common]
2394 14:05:04.054148 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=beaglebone-black-01'
2395 14:05:04.091287 >> OK - accepted request
2396 14:05:04.093387 Returned 0 in 0 seconds
2397 14:05:04.194754 end: 4.1 power-off (duration 00:00:00) [common]
2399 14:05:04.196871 start: 4.2 read-feedback (timeout 00:05:30) [common]
2400 14:05:04.198232 Listened to connection for namespace 'common' for up to 1s
2401 14:05:04.199274 Listened to connection for namespace 'common' for up to 1s
2402 14:05:05.199030 Finalising connection for namespace 'common'
2403 14:05:05.200059 Disconnecting from shell: Finalise
2404 14:05:05.200710 / #
2405 14:05:05.302020 end: 4.2 read-feedback (duration 00:00:01) [common]
2406 14:05:05.303003 end: 4 finalize (duration 00:00:01) [common]
2407 14:05:05.303829 Cleaning after the job
2408 14:05:05.304659 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/952823/tftp-deploy-qdpf9fzo/ramdisk
2409 14:05:05.316535 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/952823/tftp-deploy-qdpf9fzo/kernel
2410 14:05:05.319826 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/952823/tftp-deploy-qdpf9fzo/dtb
2411 14:05:05.321350 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/952823/tftp-deploy-qdpf9fzo/nfsrootfs
2412 14:05:05.365023 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/952823/tftp-deploy-qdpf9fzo/modules
2413 14:05:05.370399 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/952823
2414 14:05:08.717484 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/952823
2415 14:05:08.718157 Job finished correctly