Boot log: beaglebone-black
- Warnings: 2
- Kernel Warnings: 15
- Errors: 0
- Boot result: PASS
- Kernel Errors: 10
1 11:25:06.559243 lava-dispatcher, installed at version: 2024.01
2 11:25:06.560012 start: 0 validate
3 11:25:06.560487 Start time: 2024-11-08 11:25:06.560458+00:00 (UTC)
4 11:25:06.561031 Using caching service: 'http://192.168.6.3:8001/api/v1/fetch?url=%s'
5 11:25:06.561570 Validating that http://192.168.6.3:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farmhf%2Finitrd.cpio.gz exists
6 11:25:06.595894 Using caching service: 'http://192.168.6.3:8001/api/v1/fetch?url=%s'
7 11:25:06.596430 Validating that http://192.168.6.3:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241108%2Farm%2Fmulti_v7_defconfig%2Fclang-17%2Fkernel%2FzImage exists
8 11:25:06.617445 Using caching service: 'http://192.168.6.3:8001/api/v1/fetch?url=%s'
9 11:25:06.618211 Validating that http://192.168.6.3:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241108%2Farm%2Fmulti_v7_defconfig%2Fclang-17%2Fdtbs%2Fti%2Fomap%2Fam335x-boneblack.dtb exists
10 11:25:06.643243 Using caching service: 'http://192.168.6.3:8001/api/v1/fetch?url=%s'
11 11:25:06.643793 Validating that http://192.168.6.3:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farmhf%2Ffull.rootfs.tar.xz exists
12 11:25:06.671348 Using caching service: 'http://192.168.6.3:8001/api/v1/fetch?url=%s'
13 11:25:06.671791 Validating that http://192.168.6.3:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241108%2Farm%2Fmulti_v7_defconfig%2Fclang-17%2Fmodules.tar.xz exists
14 11:25:06.703740 validate duration: 0.14
16 11:25:06.704662 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 11:25:06.705002 start: 1.1 download-retry (timeout 00:10:00) [common]
18 11:25:06.705307 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 11:25:06.705920 Not decompressing ramdisk as can be used compressed.
20 11:25:06.706371 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/initrd.cpio.gz
21 11:25:06.706659 saving as /var/lib/lava/dispatcher/tmp/958774/tftp-deploy-smwqpcp0/ramdisk/initrd.cpio.gz
22 11:25:06.706933 total size: 4775763 (4 MB)
23 11:25:06.737433 progress 0 % (0 MB)
24 11:25:06.741753 progress 5 % (0 MB)
25 11:25:06.745328 progress 10 % (0 MB)
26 11:25:06.748788 progress 15 % (0 MB)
27 11:25:06.752744 progress 20 % (0 MB)
28 11:25:06.756369 progress 25 % (1 MB)
29 11:25:06.759774 progress 30 % (1 MB)
30 11:25:06.763760 progress 35 % (1 MB)
31 11:25:06.767123 progress 40 % (1 MB)
32 11:25:06.770494 progress 45 % (2 MB)
33 11:25:06.774414 progress 50 % (2 MB)
34 11:25:06.778168 progress 55 % (2 MB)
35 11:25:06.781355 progress 60 % (2 MB)
36 11:25:06.784673 progress 65 % (2 MB)
37 11:25:06.788373 progress 70 % (3 MB)
38 11:25:06.791602 progress 75 % (3 MB)
39 11:25:06.794614 progress 80 % (3 MB)
40 11:25:06.797612 progress 85 % (3 MB)
41 11:25:06.801003 progress 90 % (4 MB)
42 11:25:06.803936 progress 95 % (4 MB)
43 11:25:06.806934 progress 100 % (4 MB)
44 11:25:06.807623 4 MB downloaded in 0.10 s (45.24 MB/s)
45 11:25:06.808181 end: 1.1.1 http-download (duration 00:00:00) [common]
47 11:25:06.809053 end: 1.1 download-retry (duration 00:00:00) [common]
48 11:25:06.809381 start: 1.2 download-retry (timeout 00:10:00) [common]
49 11:25:06.809652 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 11:25:06.810278 downloading http://storage.kernelci.org/next/master/next-20241108/arm/multi_v7_defconfig/clang-17/kernel/zImage
51 11:25:06.810602 saving as /var/lib/lava/dispatcher/tmp/958774/tftp-deploy-smwqpcp0/kernel/zImage
52 11:25:06.810840 total size: 12128768 (11 MB)
53 11:25:06.811057 No compression specified
54 11:25:06.841782 progress 0 % (0 MB)
55 11:25:06.849467 progress 5 % (0 MB)
56 11:25:06.857404 progress 10 % (1 MB)
57 11:25:06.864883 progress 15 % (1 MB)
58 11:25:06.872715 progress 20 % (2 MB)
59 11:25:06.879935 progress 25 % (2 MB)
60 11:25:06.887498 progress 30 % (3 MB)
61 11:25:06.894788 progress 35 % (4 MB)
62 11:25:06.902566 progress 40 % (4 MB)
63 11:25:06.909783 progress 45 % (5 MB)
64 11:25:06.917351 progress 50 % (5 MB)
65 11:25:06.924479 progress 55 % (6 MB)
66 11:25:06.932036 progress 60 % (6 MB)
67 11:25:06.939124 progress 65 % (7 MB)
68 11:25:06.947062 progress 70 % (8 MB)
69 11:25:06.954230 progress 75 % (8 MB)
70 11:25:06.961704 progress 80 % (9 MB)
71 11:25:06.968793 progress 85 % (9 MB)
72 11:25:06.976255 progress 90 % (10 MB)
73 11:25:06.982991 progress 95 % (11 MB)
74 11:25:06.990089 progress 100 % (11 MB)
75 11:25:06.990538 11 MB downloaded in 0.18 s (64.37 MB/s)
76 11:25:06.991004 end: 1.2.1 http-download (duration 00:00:00) [common]
78 11:25:06.991806 end: 1.2 download-retry (duration 00:00:00) [common]
79 11:25:06.992078 start: 1.3 download-retry (timeout 00:10:00) [common]
80 11:25:06.992339 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 11:25:06.992819 downloading http://storage.kernelci.org/next/master/next-20241108/arm/multi_v7_defconfig/clang-17/dtbs/ti/omap/am335x-boneblack.dtb
82 11:25:06.993076 saving as /var/lib/lava/dispatcher/tmp/958774/tftp-deploy-smwqpcp0/dtb/am335x-boneblack.dtb
83 11:25:06.993280 total size: 70544 (0 MB)
84 11:25:06.993485 No compression specified
85 11:25:07.030232 progress 46 % (0 MB)
86 11:25:07.031064 progress 92 % (0 MB)
87 11:25:07.031730 progress 100 % (0 MB)
88 11:25:07.032104 0 MB downloaded in 0.04 s (1.73 MB/s)
89 11:25:07.032551 end: 1.3.1 http-download (duration 00:00:00) [common]
91 11:25:07.033356 end: 1.3 download-retry (duration 00:00:00) [common]
92 11:25:07.033616 start: 1.4 download-retry (timeout 00:10:00) [common]
93 11:25:07.033903 start: 1.4.1 http-download (timeout 00:10:00) [common]
94 11:25:07.034364 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/full.rootfs.tar.xz
95 11:25:07.034599 saving as /var/lib/lava/dispatcher/tmp/958774/tftp-deploy-smwqpcp0/nfsrootfs/full.rootfs.tar
96 11:25:07.034800 total size: 117747780 (112 MB)
97 11:25:07.035008 Using unxz to decompress xz
98 11:25:07.073340 progress 0 % (0 MB)
99 11:25:07.803044 progress 5 % (5 MB)
100 11:25:08.537632 progress 10 % (11 MB)
101 11:25:09.299559 progress 15 % (16 MB)
102 11:25:10.008472 progress 20 % (22 MB)
103 11:25:10.583713 progress 25 % (28 MB)
104 11:25:11.379037 progress 30 % (33 MB)
105 11:25:12.171622 progress 35 % (39 MB)
106 11:25:12.513579 progress 40 % (44 MB)
107 11:25:12.858629 progress 45 % (50 MB)
108 11:25:13.506640 progress 50 % (56 MB)
109 11:25:14.303068 progress 55 % (61 MB)
110 11:25:15.019475 progress 60 % (67 MB)
111 11:25:15.722765 progress 65 % (73 MB)
112 11:25:16.474381 progress 70 % (78 MB)
113 11:25:17.221499 progress 75 % (84 MB)
114 11:25:17.954432 progress 80 % (89 MB)
115 11:25:18.651725 progress 85 % (95 MB)
116 11:25:19.420628 progress 90 % (101 MB)
117 11:25:20.165340 progress 95 % (106 MB)
118 11:25:20.966036 progress 100 % (112 MB)
119 11:25:20.978317 112 MB downloaded in 13.94 s (8.05 MB/s)
120 11:25:20.979223 end: 1.4.1 http-download (duration 00:00:14) [common]
122 11:25:20.980850 end: 1.4 download-retry (duration 00:00:14) [common]
123 11:25:20.981372 start: 1.5 download-retry (timeout 00:09:46) [common]
124 11:25:20.981924 start: 1.5.1 http-download (timeout 00:09:46) [common]
125 11:25:20.982773 downloading http://storage.kernelci.org/next/master/next-20241108/arm/multi_v7_defconfig/clang-17/modules.tar.xz
126 11:25:20.983236 saving as /var/lib/lava/dispatcher/tmp/958774/tftp-deploy-smwqpcp0/modules/modules.tar
127 11:25:20.983650 total size: 6933168 (6 MB)
128 11:25:20.984073 Using unxz to decompress xz
129 11:25:21.023093 progress 0 % (0 MB)
130 11:25:21.059017 progress 5 % (0 MB)
131 11:25:21.107017 progress 10 % (0 MB)
132 11:25:21.150966 progress 15 % (1 MB)
133 11:25:21.199566 progress 20 % (1 MB)
134 11:25:21.246191 progress 25 % (1 MB)
135 11:25:21.294227 progress 30 % (2 MB)
136 11:25:21.341825 progress 35 % (2 MB)
137 11:25:21.385224 progress 40 % (2 MB)
138 11:25:21.433220 progress 45 % (3 MB)
139 11:25:21.479421 progress 50 % (3 MB)
140 11:25:21.527304 progress 55 % (3 MB)
141 11:25:21.573531 progress 60 % (3 MB)
142 11:25:21.619957 progress 65 % (4 MB)
143 11:25:21.670683 progress 70 % (4 MB)
144 11:25:21.714789 progress 75 % (4 MB)
145 11:25:21.762730 progress 80 % (5 MB)
146 11:25:21.806530 progress 85 % (5 MB)
147 11:25:21.854556 progress 90 % (5 MB)
148 11:25:21.902076 progress 95 % (6 MB)
149 11:25:21.945704 progress 100 % (6 MB)
150 11:25:21.958714 6 MB downloaded in 0.98 s (6.78 MB/s)
151 11:25:21.959454 end: 1.5.1 http-download (duration 00:00:01) [common]
153 11:25:21.961074 end: 1.5 download-retry (duration 00:00:01) [common]
154 11:25:21.961607 start: 1.6 prepare-tftp-overlay (timeout 00:09:45) [common]
155 11:25:21.962184 start: 1.6.1 extract-nfsrootfs (timeout 00:09:45) [common]
156 11:25:39.147297 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/958774/extract-nfsrootfs-pf6y72e4
157 11:25:39.148060 end: 1.6.1 extract-nfsrootfs (duration 00:00:17) [common]
158 11:25:39.148460 start: 1.6.2 lava-overlay (timeout 00:09:28) [common]
159 11:25:39.149237 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/958774/lava-overlay-o5mvzvym
160 11:25:39.149774 makedir: /var/lib/lava/dispatcher/tmp/958774/lava-overlay-o5mvzvym/lava-958774/bin
161 11:25:39.150228 makedir: /var/lib/lava/dispatcher/tmp/958774/lava-overlay-o5mvzvym/lava-958774/tests
162 11:25:39.150685 makedir: /var/lib/lava/dispatcher/tmp/958774/lava-overlay-o5mvzvym/lava-958774/results
163 11:25:39.151149 Creating /var/lib/lava/dispatcher/tmp/958774/lava-overlay-o5mvzvym/lava-958774/bin/lava-add-keys
164 11:25:39.151899 Creating /var/lib/lava/dispatcher/tmp/958774/lava-overlay-o5mvzvym/lava-958774/bin/lava-add-sources
165 11:25:39.152621 Creating /var/lib/lava/dispatcher/tmp/958774/lava-overlay-o5mvzvym/lava-958774/bin/lava-background-process-start
166 11:25:39.153326 Creating /var/lib/lava/dispatcher/tmp/958774/lava-overlay-o5mvzvym/lava-958774/bin/lava-background-process-stop
167 11:25:39.154076 Creating /var/lib/lava/dispatcher/tmp/958774/lava-overlay-o5mvzvym/lava-958774/bin/lava-common-functions
168 11:25:39.154770 Creating /var/lib/lava/dispatcher/tmp/958774/lava-overlay-o5mvzvym/lava-958774/bin/lava-echo-ipv4
169 11:25:39.155468 Creating /var/lib/lava/dispatcher/tmp/958774/lava-overlay-o5mvzvym/lava-958774/bin/lava-install-packages
170 11:25:39.156172 Creating /var/lib/lava/dispatcher/tmp/958774/lava-overlay-o5mvzvym/lava-958774/bin/lava-installed-packages
171 11:25:39.156822 Creating /var/lib/lava/dispatcher/tmp/958774/lava-overlay-o5mvzvym/lava-958774/bin/lava-os-build
172 11:25:39.157459 Creating /var/lib/lava/dispatcher/tmp/958774/lava-overlay-o5mvzvym/lava-958774/bin/lava-probe-channel
173 11:25:39.158148 Creating /var/lib/lava/dispatcher/tmp/958774/lava-overlay-o5mvzvym/lava-958774/bin/lava-probe-ip
174 11:25:39.158773 Creating /var/lib/lava/dispatcher/tmp/958774/lava-overlay-o5mvzvym/lava-958774/bin/lava-target-ip
175 11:25:39.159378 Creating /var/lib/lava/dispatcher/tmp/958774/lava-overlay-o5mvzvym/lava-958774/bin/lava-target-mac
176 11:25:39.159982 Creating /var/lib/lava/dispatcher/tmp/958774/lava-overlay-o5mvzvym/lava-958774/bin/lava-target-storage
177 11:25:39.160601 Creating /var/lib/lava/dispatcher/tmp/958774/lava-overlay-o5mvzvym/lava-958774/bin/lava-test-case
178 11:25:39.161234 Creating /var/lib/lava/dispatcher/tmp/958774/lava-overlay-o5mvzvym/lava-958774/bin/lava-test-event
179 11:25:39.161889 Creating /var/lib/lava/dispatcher/tmp/958774/lava-overlay-o5mvzvym/lava-958774/bin/lava-test-feedback
180 11:25:39.162550 Creating /var/lib/lava/dispatcher/tmp/958774/lava-overlay-o5mvzvym/lava-958774/bin/lava-test-raise
181 11:25:39.163217 Creating /var/lib/lava/dispatcher/tmp/958774/lava-overlay-o5mvzvym/lava-958774/bin/lava-test-reference
182 11:25:39.163833 Creating /var/lib/lava/dispatcher/tmp/958774/lava-overlay-o5mvzvym/lava-958774/bin/lava-test-runner
183 11:25:39.164446 Creating /var/lib/lava/dispatcher/tmp/958774/lava-overlay-o5mvzvym/lava-958774/bin/lava-test-set
184 11:25:39.165045 Creating /var/lib/lava/dispatcher/tmp/958774/lava-overlay-o5mvzvym/lava-958774/bin/lava-test-shell
185 11:25:39.165694 Updating /var/lib/lava/dispatcher/tmp/958774/lava-overlay-o5mvzvym/lava-958774/bin/lava-add-keys (debian)
186 11:25:39.166432 Updating /var/lib/lava/dispatcher/tmp/958774/lava-overlay-o5mvzvym/lava-958774/bin/lava-add-sources (debian)
187 11:25:39.167072 Updating /var/lib/lava/dispatcher/tmp/958774/lava-overlay-o5mvzvym/lava-958774/bin/lava-install-packages (debian)
188 11:25:39.167703 Updating /var/lib/lava/dispatcher/tmp/958774/lava-overlay-o5mvzvym/lava-958774/bin/lava-installed-packages (debian)
189 11:25:39.168320 Updating /var/lib/lava/dispatcher/tmp/958774/lava-overlay-o5mvzvym/lava-958774/bin/lava-os-build (debian)
190 11:25:39.168864 Creating /var/lib/lava/dispatcher/tmp/958774/lava-overlay-o5mvzvym/lava-958774/environment
191 11:25:39.169333 LAVA metadata
192 11:25:39.169661 - LAVA_JOB_ID=958774
193 11:25:39.169960 - LAVA_DISPATCHER_IP=192.168.6.3
194 11:25:39.170462 start: 1.6.2.1 ssh-authorize (timeout 00:09:28) [common]
195 11:25:39.171829 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
196 11:25:39.172226 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:28) [common]
197 11:25:39.172491 skipped lava-vland-overlay
198 11:25:39.172794 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
199 11:25:39.173155 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:28) [common]
200 11:25:39.173422 skipped lava-multinode-overlay
201 11:25:39.173722 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
202 11:25:39.174127 start: 1.6.2.4 test-definition (timeout 00:09:28) [common]
203 11:25:39.174451 Loading test definitions
204 11:25:39.174808 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:28) [common]
205 11:25:39.175112 Using /lava-958774 at stage 0
206 11:25:39.176474 uuid=958774_1.6.2.4.1 testdef=None
207 11:25:39.176856 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
208 11:25:39.177190 start: 1.6.2.4.2 test-overlay (timeout 00:09:28) [common]
209 11:25:39.179296 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
211 11:25:39.180303 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:28) [common]
212 11:25:39.182798 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
214 11:25:39.183843 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:28) [common]
215 11:25:39.186150 runner path: /var/lib/lava/dispatcher/tmp/958774/lava-overlay-o5mvzvym/lava-958774/0/tests/0_timesync-off test_uuid 958774_1.6.2.4.1
216 11:25:39.186852 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
218 11:25:39.187879 start: 1.6.2.4.5 git-repo-action (timeout 00:09:28) [common]
219 11:25:39.188161 Using /lava-958774 at stage 0
220 11:25:39.188610 Fetching tests from https://github.com/kernelci/test-definitions.git
221 11:25:39.188980 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/958774/lava-overlay-o5mvzvym/lava-958774/0/tests/1_kselftest-dt'
222 11:25:42.589486 Running '/usr/bin/git checkout kernelci.org
223 11:25:43.047714 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/958774/lava-overlay-o5mvzvym/lava-958774/0/tests/1_kselftest-dt/automated/linux/kselftest/kselftest.yaml
224 11:25:43.049170 uuid=958774_1.6.2.4.5 testdef=None
225 11:25:43.049517 end: 1.6.2.4.5 git-repo-action (duration 00:00:04) [common]
227 11:25:43.050750 start: 1.6.2.4.6 test-overlay (timeout 00:09:24) [common]
228 11:25:43.056107 end: 1.6.2.4.6 test-overlay (duration 00:00:00) [common]
230 11:25:43.057682 start: 1.6.2.4.7 test-install-overlay (timeout 00:09:24) [common]
231 11:25:43.064855 end: 1.6.2.4.7 test-install-overlay (duration 00:00:00) [common]
233 11:25:43.066546 start: 1.6.2.4.8 test-runscript-overlay (timeout 00:09:24) [common]
234 11:25:43.073503 runner path: /var/lib/lava/dispatcher/tmp/958774/lava-overlay-o5mvzvym/lava-958774/0/tests/1_kselftest-dt test_uuid 958774_1.6.2.4.5
235 11:25:43.074093 BOARD='beaglebone-black'
236 11:25:43.074501 BRANCH='next'
237 11:25:43.074889 SKIPFILE='/dev/null'
238 11:25:43.075280 SKIP_INSTALL='True'
239 11:25:43.075663 TESTPROG_URL='http://storage.kernelci.org/next/master/next-20241108/arm/multi_v7_defconfig/clang-17/kselftest.tar.xz'
240 11:25:43.076052 TST_CASENAME=''
241 11:25:43.076437 TST_CMDFILES='dt'
242 11:25:43.077427 end: 1.6.2.4.8 test-runscript-overlay (duration 00:00:00) [common]
244 11:25:43.078974 Creating lava-test-runner.conf files
245 11:25:43.079378 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/958774/lava-overlay-o5mvzvym/lava-958774/0 for stage 0
246 11:25:43.080025 - 0_timesync-off
247 11:25:43.080478 - 1_kselftest-dt
248 11:25:43.081101 end: 1.6.2.4 test-definition (duration 00:00:04) [common]
249 11:25:43.081643 start: 1.6.2.5 compress-overlay (timeout 00:09:24) [common]
250 11:26:07.013589 end: 1.6.2.5 compress-overlay (duration 00:00:24) [common]
251 11:26:07.014054 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:09:00) [common]
252 11:26:07.014320 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
253 11:26:07.014590 end: 1.6.2 lava-overlay (duration 00:00:28) [common]
254 11:26:07.014850 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:00) [common]
255 11:26:07.374625 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
256 11:26:07.375067 start: 1.6.4 extract-modules (timeout 00:08:59) [common]
257 11:26:07.375313 extracting modules file /var/lib/lava/dispatcher/tmp/958774/tftp-deploy-smwqpcp0/modules/modules.tar to /var/lib/lava/dispatcher/tmp/958774/extract-nfsrootfs-pf6y72e4
258 11:26:08.288121 extracting modules file /var/lib/lava/dispatcher/tmp/958774/tftp-deploy-smwqpcp0/modules/modules.tar to /var/lib/lava/dispatcher/tmp/958774/extract-overlay-ramdisk-e4a9hcxv/ramdisk
259 11:26:09.217144 end: 1.6.4 extract-modules (duration 00:00:02) [common]
260 11:26:09.217615 start: 1.6.5 apply-overlay-tftp (timeout 00:08:57) [common]
261 11:26:09.217947 [common] Applying overlay to NFS
262 11:26:09.218169 [common] Applying overlay /var/lib/lava/dispatcher/tmp/958774/compress-overlay-adq0_59s/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/958774/extract-nfsrootfs-pf6y72e4
263 11:26:11.958300 end: 1.6.5 apply-overlay-tftp (duration 00:00:03) [common]
264 11:26:11.958768 start: 1.6.6 prepare-kernel (timeout 00:08:55) [common]
265 11:26:11.959040 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:08:55) [common]
266 11:26:11.959341 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
267 11:26:11.959599 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
268 11:26:11.959856 start: 1.6.7 configure-preseed-file (timeout 00:08:55) [common]
269 11:26:11.960106 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
270 11:26:11.960361 start: 1.6.8 compress-ramdisk (timeout 00:08:55) [common]
271 11:26:11.960583 Building ramdisk /var/lib/lava/dispatcher/tmp/958774/extract-overlay-ramdisk-e4a9hcxv/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/958774/extract-overlay-ramdisk-e4a9hcxv/ramdisk
272 11:26:13.143569 >> 79383 blocks
273 11:26:18.278091 Adding RAMdisk u-boot header.
274 11:26:18.278578 mkimage -A arm -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/958774/extract-overlay-ramdisk-e4a9hcxv/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/958774/extract-overlay-ramdisk-e4a9hcxv/ramdisk.cpio.gz.uboot
275 11:26:18.445986 output: Image Name:
276 11:26:18.446666 output: Created: Fri Nov 8 11:26:18 2024
277 11:26:18.447126 output: Image Type: ARM Linux RAMDisk Image (uncompressed)
278 11:26:18.447572 output: Data Size: 15384641 Bytes = 15024.06 KiB = 14.67 MiB
279 11:26:18.448016 output: Load Address: 00000000
280 11:26:18.448449 output: Entry Point: 00000000
281 11:26:18.448885 output:
282 11:26:18.450138 rename /var/lib/lava/dispatcher/tmp/958774/extract-overlay-ramdisk-e4a9hcxv/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/958774/tftp-deploy-smwqpcp0/ramdisk/ramdisk.cpio.gz.uboot
283 11:26:18.450925 end: 1.6.8 compress-ramdisk (duration 00:00:06) [common]
284 11:26:18.451525 end: 1.6 prepare-tftp-overlay (duration 00:00:56) [common]
285 11:26:18.452102 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:48) [common]
286 11:26:18.452596 No LXC device requested
287 11:26:18.453139 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
288 11:26:18.453701 start: 1.8 deploy-device-env (timeout 00:08:48) [common]
289 11:26:18.454283 end: 1.8 deploy-device-env (duration 00:00:00) [common]
290 11:26:18.454738 Checking files for TFTP limit of 4294967296 bytes.
291 11:26:18.457661 end: 1 tftp-deploy (duration 00:01:12) [common]
292 11:26:18.458327 start: 2 uboot-action (timeout 00:05:00) [common]
293 11:26:18.458899 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
294 11:26:18.459443 end: 2.1 uboot-from-media (duration 00:00:00) [common]
295 11:26:18.459987 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
296 11:26:18.460798 substitutions:
297 11:26:18.461256 - {BOOTX}: bootz 0x82000000 0x83000000 0x88000000
298 11:26:18.461702 - {DTB_ADDR}: 0x88000000
299 11:26:18.462175 - {DTB}: 958774/tftp-deploy-smwqpcp0/dtb/am335x-boneblack.dtb
300 11:26:18.462613 - {INITRD}: 958774/tftp-deploy-smwqpcp0/ramdisk/ramdisk.cpio.gz.uboot
301 11:26:18.463044 - {KERNEL_ADDR}: 0x82000000
302 11:26:18.463471 - {KERNEL}: 958774/tftp-deploy-smwqpcp0/kernel/zImage
303 11:26:18.463898 - {LAVA_MAC}: None
304 11:26:18.464369 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/958774/extract-nfsrootfs-pf6y72e4
305 11:26:18.464804 - {NFS_SERVER_IP}: 192.168.6.3
306 11:26:18.465230 - {PRESEED_CONFIG}: None
307 11:26:18.465653 - {PRESEED_LOCAL}: None
308 11:26:18.466111 - {RAMDISK_ADDR}: 0x83000000
309 11:26:18.466538 - {RAMDISK}: 958774/tftp-deploy-smwqpcp0/ramdisk/ramdisk.cpio.gz.uboot
310 11:26:18.466967 - {ROOT_PART}: None
311 11:26:18.467389 - {ROOT}: None
312 11:26:18.467811 - {SERVER_IP}: 192.168.6.3
313 11:26:18.468227 - {TEE_ADDR}: 0x83000000
314 11:26:18.468645 - {TEE}: None
315 11:26:18.469064 Parsed boot commands:
316 11:26:18.469475 - setenv autoload no
317 11:26:18.469914 - setenv initrd_high 0xffffffff
318 11:26:18.470337 - setenv fdt_high 0xffffffff
319 11:26:18.470753 - dhcp
320 11:26:18.471169 - setenv serverip 192.168.6.3
321 11:26:18.471586 - tftp 0x82000000 958774/tftp-deploy-smwqpcp0/kernel/zImage
322 11:26:18.472003 - tftp 0x83000000 958774/tftp-deploy-smwqpcp0/ramdisk/ramdisk.cpio.gz.uboot
323 11:26:18.472422 - setenv initrd_size ${filesize}
324 11:26:18.472839 - tftp 0x88000000 958774/tftp-deploy-smwqpcp0/dtb/am335x-boneblack.dtb
325 11:26:18.473258 - setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.3:/var/lib/lava/dispatcher/tmp/958774/extract-nfsrootfs-pf6y72e4,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
326 11:26:18.473684 - bootz 0x82000000 0x83000000 0x88000000
327 11:26:18.474253 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
329 11:26:18.475877 start: 2.3 connect-device (timeout 00:05:00) [common]
330 11:26:18.476337 [common] connect-device Connecting to device using 'telnet conserv3 3000'
331 11:26:18.492396 Setting prompt string to ['lava-test: # ']
332 11:26:18.494040 end: 2.3 connect-device (duration 00:00:00) [common]
333 11:26:18.494717 start: 2.4 uboot-commands (timeout 00:05:00) [common]
334 11:26:18.495317 start: 2.4.1 reset-device (timeout 00:05:00) [common]
335 11:26:18.495895 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
336 11:26:18.497399 Calling: 'curl' 'http://conserv3.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=beaglebone-black-03'
337 11:26:18.535623 >> OK - accepted request
338 11:26:18.537722 Returned 0 in 0 seconds
339 11:26:18.639236 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
341 11:26:18.641073 end: 2.4.1 reset-device (duration 00:00:00) [common]
342 11:26:18.641736 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
343 11:26:18.642382 Setting prompt string to ['Hit any key to stop autoboot']
344 11:26:18.642894 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
345 11:26:18.644635 Trying 192.168.56.22...
346 11:26:18.645185 Connected to conserv3.
347 11:26:18.645638 Escape character is '^]'.
348 11:26:18.646152
349 11:26:18.646642 ser2net port telnet,3000 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.2.3:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
350 11:26:18.647112
351 11:26:27.280142
352 11:26:27.287235 U-Boot SPL 2023.01-rc4-00025-gb92e12ac87 (Dec 26 2022 - 18:25:48 +0000)
353 11:26:27.287703 Trying to boot from MMC1
354 11:26:27.873168
355 11:26:27.873772
356 11:26:27.878602 U-Boot 2023.01-rc4-00025-gb92e12ac87 (Dec 26 2022 - 18:25:48 +0000)
357 11:26:27.878897
358 11:26:27.879125 CPU : AM335X-GP rev 2.0
359 11:26:27.882911 Model: TI AM335x BeagleBone Black
360 11:26:27.883194 DRAM: 512 MiB
361 11:26:31.335465
362 11:26:31.342375 U-Boot SPL 2023.01-rc4-00025-gb92e12ac87 (Dec 26 2022 - 18:25:48 +0000)
363 11:26:31.343113 Trying to boot from MMC1
364 11:26:31.929234
365 11:26:31.930146
366 11:26:31.934351 U-Boot 2023.01-rc4-00025-gb92e12ac87 (Dec 26 2022 - 18:25:48 +0000)
367 11:26:31.934991
368 11:26:31.935572 CPU : AM335X-GP rev 2.0
369 11:26:31.939567 Model: TI AM335x BeagleBone Black
370 11:26:31.940185 DRAM: 512 MiB
371 11:26:34.029117
372 11:26:34.036348 U-Boot SPL 2023.01-rc4-00025-gb92e12ac87 (Dec 26 2022 - 18:25:48 +0000)
373 11:26:34.036917 Trying to boot from MMC1
374 11:26:34.622058
375 11:26:34.622675
376 11:26:34.627540 U-Boot 2023.01-rc4-00025-gb92e12ac87 (Dec 26 2022 - 18:25:48 +0000)
377 11:26:34.628108
378 11:26:34.628575 CPU : AM335X-GP rev 2.0
379 11:26:34.631712 Model: TI AM335x BeagleBone Black
380 11:26:34.632277 DRAM: 512 MiB
381 11:26:34.716233 Core: 160 devices, 18 uclasses, devicetree: separate
382 11:26:34.730117 WDT: Started wdt@44e35000 with servicing every 1000ms (60s timeout)
383 11:26:35.131827 NAND: 0 MiB
384 11:26:35.141964 MMC: OMAP SD/MMC: 0, OMAP SD/MMC: 1
385 11:26:35.215541 Loading Environment from FAT... Unable to read "uboot.env" from mmc0:1...
386 11:26:35.237889 <ethaddr> not set. Validating first E-fuse MAC
387 11:26:35.267549 Net: eth2: ethernet@4a100000, eth3: usb_ether
389 11:26:35.326189 Hit any key to stop autoboot: 2
390 11:26:35.327124 end: 2.4.2 bootloader-interrupt (duration 00:00:17) [common]
391 11:26:35.327802 start: 2.4.3 bootloader-commands (timeout 00:04:43) [common]
392 11:26:35.328396 Setting prompt string to ['=>']
393 11:26:35.328949 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:43)
394 11:26:35.335954 0
395 11:26:35.337008 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
396 11:26:35.337589 Sending with 10 millisecond of delay
398 11:26:36.472668 => setenv autoload no
399 11:26:36.483572 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:42)
400 11:26:36.489145 setenv autoload no
401 11:26:36.489959 Sending with 10 millisecond of delay
403 11:26:38.287397 => setenv initrd_high 0xffffffff
404 11:26:38.298242 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
405 11:26:38.299181 setenv initrd_high 0xffffffff
406 11:26:38.299945 Sending with 10 millisecond of delay
408 11:26:39.916997 => setenv fdt_high 0xffffffff
409 11:26:39.927863 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:39)
410 11:26:39.928838 setenv fdt_high 0xffffffff
411 11:26:39.929619 Sending with 10 millisecond of delay
413 11:26:40.221795 => dhcp
414 11:26:40.232666 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:38)
415 11:26:40.233656 dhcp
416 11:26:40.234195 link up on port 0, speed 100, full duplex
417 11:26:40.234689 BOOTP broadcast 1
418 11:26:40.487082 BOOTP broadcast 2
419 11:26:40.989043 BOOTP broadcast 3
420 11:26:41.990856 BOOTP broadcast 4
421 11:26:43.992707 BOOTP broadcast 5
422 11:26:44.075035 DHCP client bound to address 192.168.6.23 (3837 ms)
423 11:26:44.075696 Sending with 10 millisecond of delay
425 11:26:45.752939 => setenv serverip 192.168.6.3
426 11:26:45.763534 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:33)
427 11:26:45.764167 setenv serverip 192.168.6.3
428 11:26:45.764670 Sending with 10 millisecond of delay
430 11:26:49.252879 => tftp 0x82000000 958774/tftp-deploy-smwqpcp0/kernel/zImage
431 11:26:49.263783 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:29)
432 11:26:49.264826 tftp 0x82000000 958774/tftp-deploy-smwqpcp0/kernel/zImage
433 11:26:49.265341 link up on port 0, speed 100, full duplex
434 11:26:49.268537 Using ethernet@4a100000 device
435 11:26:49.274182 TFTP from server 192.168.6.3; our IP address is 192.168.6.23
436 11:26:49.281537 Filename '958774/tftp-deploy-smwqpcp0/kernel/zImage'.
437 11:26:49.282122 Load address: 0x82000000
438 11:26:51.472241 Loading: *################################################## 11.6 MiB
439 11:26:51.472918 5.3 MiB/s
440 11:26:51.473386 done
441 11:26:51.476234 Bytes transferred = 12128768 (b91200 hex)
442 11:26:51.477026 Sending with 10 millisecond of delay
444 11:26:55.926397 => tftp 0x83000000 958774/tftp-deploy-smwqpcp0/ramdisk/ramdisk.cpio.gz.uboot
445 11:26:55.937213 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:23)
446 11:26:55.938171 tftp 0x83000000 958774/tftp-deploy-smwqpcp0/ramdisk/ramdisk.cpio.gz.uboot
447 11:26:55.938608 link up on port 0, speed 100, full duplex
448 11:26:55.942106 Using ethernet@4a100000 device
449 11:26:55.947677 TFTP from server 192.168.6.3; our IP address is 192.168.6.23
450 11:26:55.956459 Filename '958774/tftp-deploy-smwqpcp0/ramdisk/ramdisk.cpio.gz.uboot'.
451 11:26:55.956942 Load address: 0x83000000
452 11:26:58.692542 Loading: *################################################## 14.7 MiB
453 11:26:58.692967 5.4 MiB/s
454 11:26:58.693177 done
455 11:26:58.696745 Bytes transferred = 15384705 (eac081 hex)
456 11:26:58.697286 Sending with 10 millisecond of delay
458 11:27:00.555529 => setenv initrd_size ${filesize}
459 11:27:00.566314 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
460 11:27:00.566877 setenv initrd_size ${filesize}
461 11:27:00.567347 Sending with 10 millisecond of delay
463 11:27:04.714766 => tftp 0x88000000 958774/tftp-deploy-smwqpcp0/dtb/am335x-boneblack.dtb
464 11:27:04.725346 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:14)
465 11:27:04.725933 tftp 0x88000000 958774/tftp-deploy-smwqpcp0/dtb/am335x-boneblack.dtb
466 11:27:04.726191 link up on port 0, speed 100, full duplex
467 11:27:04.730327 Using ethernet@4a100000 device
468 11:27:04.736026 TFTP from server 192.168.6.3; our IP address is 192.168.6.23
469 11:27:04.747170 Filename '958774/tftp-deploy-smwqpcp0/dtb/am335x-boneblack.dtb'.
470 11:27:04.747509 Load address: 0x88000000
471 11:27:04.757264 Loading: *################################################## 68.9 KiB
472 11:27:04.757584 4.8 MiB/s
473 11:27:04.765702 done
474 11:27:04.766020 Bytes transferred = 70544 (11390 hex)
475 11:27:04.766778 Sending with 10 millisecond of delay
477 11:27:17.951807 => setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.3:/var/lib/lava/dispatcher/tmp/958774/extract-nfsrootfs-pf6y72e4,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
478 11:27:17.962609 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:00)
479 11:27:17.963459 setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.3:/var/lib/lava/dispatcher/tmp/958774/extract-nfsrootfs-pf6y72e4,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
480 11:27:17.964162 Sending with 10 millisecond of delay
482 11:27:20.305473 => bootz 0x82000000 0x83000000 0x88000000
483 11:27:20.316274 Setting prompt string to ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
484 11:27:20.316813 bootloader-commands: Wait for prompt ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:03:58)
485 11:27:20.317774 bootz 0x82000000 0x83000000 0x88000000
486 11:27:20.318303 Kernel image @ 0x82000000 [ 0x000000 - 0xb91200 ]
487 11:27:20.318794 ## Loading init Ramdisk from Legacy Image at 83000000 ...
488 11:27:20.323704 Image Name:
489 11:27:20.324182 Created: 2024-11-08 11:26:18 UTC
490 11:27:20.332614 Image Type: ARM Linux RAMDisk Image (uncompressed)
491 11:27:20.333090 Data Size: 15384641 Bytes = 14.7 MiB
492 11:27:20.340991 Load Address: 00000000
493 11:27:20.341437 Entry Point: 00000000
494 11:27:20.515898 Verifying Checksum ... OK
495 11:27:20.516296 ## Flattened Device Tree blob at 88000000
496 11:27:20.522334 Booting using the fdt blob at 0x88000000
497 11:27:20.522609 Working FDT set to 88000000
498 11:27:20.527911 Using Device Tree in place at 88000000, end 8801438f
499 11:27:20.531312 Working FDT set to 88000000
500 11:27:20.545560
501 11:27:20.545852 Starting kernel ...
502 11:27:20.546061
503 11:27:20.546616 end: 2.4.3 bootloader-commands (duration 00:00:45) [common]
504 11:27:20.546924 start: 2.4.4 auto-login-action (timeout 00:03:58) [common]
505 11:27:20.547159 Setting prompt string to ['Linux version [0-9]']
506 11:27:20.547389 Setting prompt string to ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
507 11:27:20.547623 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:05:00)
508 11:27:21.462613 [ 0.000000] Booting Linux on physical CPU 0x0
509 11:27:21.468635 start: 2.4.4.1 login-action (timeout 00:03:57) [common]
510 11:27:21.469197 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
511 11:27:21.469654 Setting prompt string to []
512 11:27:21.470185 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
513 11:27:21.470629 Using line separator: #'\n'#
514 11:27:21.471030 No login prompt set.
515 11:27:21.471448 Parsing kernel messages
516 11:27:21.471833 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
517 11:27:21.472623 [login-action] Waiting for messages, (timeout 00:03:57)
518 11:27:21.473050 Waiting using forced prompt support (timeout 00:01:58)
519 11:27:21.485364 [ 0.000000] Linux version 6.12.0-rc6-next-20241108 (KernelCI@build-j368331-arm-clang-17-multi-v7-defconfig-d8vrp) (Debian clang version 17.0.6 (++20231208085813+6009708b4367-1~exp1~20231208085906.81), Debian LLD 17.0.6) #1 SMP Fri Nov 8 10:29:39 UTC 2024
520 11:27:21.496815 [ 0.000000] CPU: ARMv7 Processor [413fc082] revision 2 (ARMv7), cr=10c5387d
521 11:27:21.502618 [ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
522 11:27:21.508192 [ 0.000000] OF: fdt: Machine model: TI AM335x BeagleBone Black
523 11:27:21.513921 [ 0.000000] earlycon: omap8250 at MMIO 0x44e09000 (options '')
524 11:27:21.519740 [ 0.000000] printk: legacy bootconsole [omap8250] enabled
525 11:27:21.526463 [ 0.000000] Memory policy: Data cache writeback
526 11:27:21.526886 [ 0.000000] efi: UEFI not found.
527 11:27:21.534682 [ 0.000000] cma: Reserved 64 MiB at 0x9b800000 on node -1
528 11:27:21.540345 [ 0.000000] Zone ranges:
529 11:27:21.546074 [ 0.000000] DMA [mem 0x0000000080000000-0x000000009fdfffff]
530 11:27:21.551794 [ 0.000000] Normal empty
531 11:27:21.552204 [ 0.000000] HighMem empty
532 11:27:21.557668 [ 0.000000] Movable zone start for each node
533 11:27:21.558111 [ 0.000000] Early memory node ranges
534 11:27:21.569199 [ 0.000000] node 0: [mem 0x0000000080000000-0x000000009fdfffff]
535 11:27:21.574512 [ 0.000000] Initmem setup node 0 [mem 0x0000000080000000-0x000000009fdfffff]
536 11:27:21.587811 [ 0.000000] OF: reserved mem: Reserved memory: No reserved-memory node in the DT
537 11:27:21.601219 [ 0.000000] CPU: All CPU(s) started in SVC mode.
538 11:27:21.606003 [ 0.000000] AM335X ES2.0 (sgx neon)
539 11:27:21.618740 [ 0.000000] percpu: Embedded 17 pages/cpu s40204 r8192 d21236 u69632
540 11:27:21.639041 [ 0.000000] Kernel command line: console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.3:/var/lib/lava/dispatcher/tmp/958774/extract-nfsrootfs-pf6y72e4,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp
541 11:27:21.644950 <6>[ 0.000000] printk: log buffer data + meta data: 131072 + 409600 = 540672 bytes
542 11:27:21.656477 <6>[ 0.000000] Dentry cache hash table entries: 65536 (order: 6, 262144 bytes, linear)
543 11:27:21.662173 <6>[ 0.000000] Inode-cache hash table entries: 32768 (order: 5, 131072 bytes, linear)
544 11:27:21.668042 <6>[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 130560
545 11:27:21.677243 <6>[ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
546 11:27:21.706413 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
547 11:27:21.712436 <6>[ 0.000000] trace event string verifier disabled
548 11:27:21.712870 <6>[ 0.000000] rcu: Hierarchical RCU implementation.
549 11:27:21.718141 <6>[ 0.000000] rcu: RCU event tracing is enabled.
550 11:27:21.729626 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=16 to nr_cpu_ids=1.
551 11:27:21.730090 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
552 11:27:21.741023 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 10 jiffies.
553 11:27:21.746814 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=1
554 11:27:21.757698 <6>[ 0.000000] RCU Tasks Trace: Setting shift to 0 and lim to 1 rcu_task_cb_adjust=1 rcu_task_cpu_ids=1.
555 11:27:21.772722 <6>[ 0.000000] NR_IRQS: 16, nr_irqs: 16, preallocated irqs: 16
556 11:27:21.791069 <6>[ 0.000000] IRQ: Found an INTC at 0x(ptrval) (revision 5.0) with 128 interrupts
557 11:27:21.797835 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
558 11:27:21.900740 <6>[ 0.000000] TI gptimer clocksource: always-on /ocp/interconnect@44c00000/segment@200000/target-module@31000
559 11:27:21.912166 <6>[ 0.000002] sched_clock: 32 bits at 24MHz, resolution 41ns, wraps every 89478484971ns
560 11:27:21.918962 <6>[ 0.008337] clocksource: dmtimer: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 79635851949 ns
561 11:27:21.932054 <6>[ 0.019225] TI gptimer clockevent: 24000000 Hz at /ocp/interconnect@48000000/segment@0/target-module@40000
562 11:27:21.939845 <6>[ 0.034503] Console: colour dummy device 80x30
563 11:27:21.946000 Matched prompt #6: WARNING:
564 11:27:21.946462 Setting prompt string to ['end trace[^\\r]*\\r', '/ #', 'Login timed out', 'Login incorrect']
565 11:27:21.951377 <3>[ 0.039398] WARNING: Your 'console=ttyO0' has been replaced by 'ttyS0'
566 11:27:21.957092 <3>[ 0.046473] This ensures that you still see kernel messages. Please
567 11:27:21.960344 <3>[ 0.053200] update your kernel commandline.
568 11:27:22.000576 <6>[ 0.057814] Calibrating delay loop... 996.14 BogoMIPS (lpj=4980736)
569 11:27:22.006313 <6>[ 0.096230] CPU: Testing write buffer coherency: ok
570 11:27:22.012255 <6>[ 0.101598] CPU0: Spectre v2: using BPIALL workaround
571 11:27:22.012679 <6>[ 0.107064] pid_max: default: 32768 minimum: 301
572 11:27:22.023742 <6>[ 0.112266] Mount-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
573 11:27:22.030841 <6>[ 0.120086] Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
574 11:27:22.038106 <6>[ 0.129560] CPU0: thread -1, cpu 0, socket -1, mpidr 0
575 11:27:22.046613 <6>[ 0.136627] Setting up static identity map for 0x80300000 - 0x803000ac
576 11:27:22.052310 <6>[ 0.146441] rcu: Hierarchical SRCU implementation.
577 11:27:22.059938 <6>[ 0.151723] rcu: Max phase no-delay instances is 1000.
578 11:27:22.068895 <6>[ 0.163289] EFI services will not be available.
579 11:27:22.074865 <6>[ 0.168570] smp: Bringing up secondary CPUs ...
580 11:27:22.080497 <6>[ 0.173619] smp: Brought up 1 node, 1 CPU
581 11:27:22.086287 <6>[ 0.178019] SMP: Total of 1 processors activated (996.14 BogoMIPS).
582 11:27:22.092208 <6>[ 0.184789] CPU: All CPU(s) started in SVC mode.
583 11:27:22.112593 <6>[ 0.189987] Memory: 404372K/522240K available (17408K kernel code, 2537K rwdata, 6736K rodata, 2048K init, 430K bss, 50672K reserved, 65536K cma-reserved, 0K highmem)
584 11:27:22.113022 <6>[ 0.206290] devtmpfs: initialized
585 11:27:22.135756 <6>[ 0.224186] VFP support v0.3: implementor 41 architecture 3 part 30 variant c rev 3
586 11:27:22.147051 <6>[ 0.232786] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
587 11:27:22.153026 <6>[ 0.243245] futex hash table entries: 256 (order: 2, 16384 bytes, linear)
588 11:27:22.163777 <6>[ 0.255525] pinctrl core: initialized pinctrl subsystem
589 11:27:22.173548 <6>[ 0.266542] DMI not present or invalid.
590 11:27:22.181828 <6>[ 0.272419] NET: Registered PF_NETLINK/PF_ROUTE protocol family
591 11:27:22.191303 <6>[ 0.281422] DMA: preallocated 256 KiB pool for atomic coherent allocations
592 11:27:22.206788 <6>[ 0.293139] thermal_sys: Registered thermal governor 'step_wise'
593 11:27:22.207270 <6>[ 0.293332] cpuidle: using governor menu
594 11:27:22.241979 <6>[ 0.322319] /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70: Fixed dependency cycle(s) with /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
595 11:27:22.261445 <6>[ 0.341146] /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
596 11:27:22.267166 <6>[ 0.361813] No ATAGs?
597 11:27:22.274374 <6>[ 0.364444] hw-breakpoint: debug architecture 0x4 unsupported.
598 11:27:22.283865 <6>[ 0.376674] Serial: AMBA PL011 UART driver
599 11:27:22.320834 <6>[ 0.415437] iommu: Default domain type: Translated
600 11:27:22.329926 <6>[ 0.420784] iommu: DMA domain TLB invalidation policy: strict mode
601 11:27:22.356467 <5>[ 0.450486] SCSI subsystem initialized
602 11:27:22.362314 <6>[ 0.455380] usbcore: registered new interface driver usbfs
603 11:27:22.368144 <6>[ 0.461469] usbcore: registered new interface driver hub
604 11:27:22.375359 <6>[ 0.467257] usbcore: registered new device driver usb
605 11:27:22.380759 <6>[ 0.473829] pps_core: LinuxPPS API ver. 1 registered
606 11:27:22.392340 <6>[ 0.479214] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
607 11:27:22.399513 <6>[ 0.488947] PTP clock support registered
608 11:27:22.399942 <6>[ 0.493412] EDAC MC: Ver: 3.0.0
609 11:27:22.451238 <6>[ 0.543354] scmi_core: SCMI protocol bus registered
610 11:27:22.475514 <6>[ 0.569291] vgaarb: loaded
611 11:27:22.481575 <6>[ 0.573151] clocksource: Switched to clocksource dmtimer
612 11:27:22.508220 <6>[ 0.602529] NET: Registered PF_INET protocol family
613 11:27:22.520953 <6>[ 0.608255] IP idents hash table entries: 8192 (order: 4, 65536 bytes, linear)
614 11:27:22.527847 <6>[ 0.617291] tcp_listen_portaddr_hash hash table entries: 512 (order: 0, 4096 bytes, linear)
615 11:27:22.539348 <6>[ 0.626232] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
616 11:27:22.545076 <6>[ 0.634496] TCP established hash table entries: 4096 (order: 2, 16384 bytes, linear)
617 11:27:22.550937 <6>[ 0.642765] TCP bind hash table entries: 4096 (order: 4, 65536 bytes, linear)
618 11:27:22.556731 <6>[ 0.650482] TCP: Hash tables configured (established 4096 bind 4096)
619 11:27:22.568448 <6>[ 0.657406] UDP hash table entries: 256 (order: 1, 8192 bytes, linear)
620 11:27:22.574261 <6>[ 0.664440] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes, linear)
621 11:27:22.580703 <6>[ 0.672025] NET: Registered PF_UNIX/PF_LOCAL protocol family
622 11:27:22.664629 <6>[ 0.753618] RPC: Registered named UNIX socket transport module.
623 11:27:22.665132 <6>[ 0.760006] RPC: Registered udp transport module.
624 11:27:22.670392 <6>[ 0.765161] RPC: Registered tcp transport module.
625 11:27:22.679037 <6>[ 0.770266] RPC: Registered tcp-with-tls transport module.
626 11:27:22.684919 <6>[ 0.776190] RPC: Registered tcp NFSv4.1 backchannel transport module.
627 11:27:22.692084 <6>[ 0.783120] PCI: CLS 0 bytes, default 64
628 11:27:22.694386 <5>[ 0.788953] Initialise system trusted keyrings
629 11:27:22.716200 <6>[ 0.807778] Trying to unpack rootfs image as initramfs...
630 11:27:22.784924 <6>[ 0.873309] workingset: timestamp_bits=30 max_order=17 bucket_order=0
631 11:27:22.789688 <6>[ 0.880823] squashfs: version 4.0 (2009/01/31) Phillip Lougher
632 11:27:22.829405 <5>[ 0.924049] NFS: Registering the id_resolver key type
633 11:27:22.835256 <5>[ 0.929638] Key type id_resolver registered
634 11:27:22.841053 <5>[ 0.934318] Key type id_legacy registered
635 11:27:22.846852 <6>[ 0.938760] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
636 11:27:22.856461 <6>[ 0.945978] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
637 11:27:22.939096 <5>[ 1.033640] Key type asymmetric registered
638 11:27:22.944956 <5>[ 1.038164] Asymmetric key parser 'x509' registered
639 11:27:22.956733 <6>[ 1.043679] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 246)
640 11:27:22.957137 <6>[ 1.051568] io scheduler mq-deadline registered
641 11:27:22.962368 <6>[ 1.056555] io scheduler kyber registered
642 11:27:22.967896 <6>[ 1.061008] io scheduler bfq registered
643 11:27:23.063071 <6>[ 1.153904] ledtrig-cpu: registered to indicate activity on CPUs
644 11:27:23.369610 <6>[ 1.460040] Serial: 8250/16550 driver, 5 ports, IRQ sharing enabled
645 11:27:23.403575 <6>[ 1.497881] msm_serial: driver initialized
646 11:27:23.409688 <6>[ 1.502675] SuperH (H)SCI(F) driver initialized
647 11:27:23.415517 <6>[ 1.507998] STMicroelectronics ASC driver initialized
648 11:27:23.420976 <6>[ 1.513692] STM32 USART driver initialized
649 11:27:23.571455 <6>[ 1.665166] brd: module loaded
650 11:27:23.590747 <6>[ 1.684377] loop: module loaded
651 11:27:23.637860 <6>[ 1.731178] CAN device driver interface
652 11:27:23.644580 <6>[ 1.736553] bgmac_bcma: Broadcom 47xx GBit MAC driver loaded
653 11:27:23.650294 <6>[ 1.743677] e1000e: Intel(R) PRO/1000 Network Driver
654 11:27:23.656099 <6>[ 1.749067] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
655 11:27:23.661874 <6>[ 1.755529] igb: Intel(R) Gigabit Ethernet Network Driver
656 11:27:23.670133 <6>[ 1.761352] igb: Copyright (c) 2007-2014 Intel Corporation.
657 11:27:23.682027 <6>[ 1.770715] pegasus: Pegasus/Pegasus II USB Ethernet driver
658 11:27:23.687793 <6>[ 1.776891] usbcore: registered new interface driver pegasus
659 11:27:23.693552 <6>[ 1.783020] usbcore: registered new interface driver asix
660 11:27:23.699335 <6>[ 1.788909] usbcore: registered new interface driver ax88179_178a
661 11:27:23.705123 <6>[ 1.795500] usbcore: registered new interface driver cdc_ether
662 11:27:23.710952 <6>[ 1.801799] usbcore: registered new interface driver smsc75xx
663 11:27:23.716661 <6>[ 1.808029] usbcore: registered new interface driver smsc95xx
664 11:27:23.722432 <6>[ 1.814254] usbcore: registered new interface driver net1080
665 11:27:23.728219 <6>[ 1.820380] usbcore: registered new interface driver cdc_subset
666 11:27:23.734134 <6>[ 1.826807] usbcore: registered new interface driver zaurus
667 11:27:23.741679 <6>[ 1.832852] usbcore: registered new interface driver cdc_ncm
668 11:27:23.751527 <6>[ 1.842440] usbcore: registered new interface driver usb-storage
669 11:27:23.761250 <6>[ 1.853786] i2c_dev: i2c /dev entries driver
670 11:27:23.785878 <5>[ 1.872435] cpuidle: enable-method property 'ti,am3352' found operations
671 11:27:23.791670 <6>[ 1.881958] sdhci: Secure Digital Host Controller Interface driver
672 11:27:23.799206 <6>[ 1.888716] sdhci: Copyright(c) Pierre Ossman
673 11:27:23.806314 <6>[ 1.895221] Synopsys Designware Multimedia Card Interface Driver
674 11:27:23.811781 <6>[ 1.903058] sdhci-pltfm: SDHCI platform and OF driver helper
675 11:27:23.825961 <6>[ 1.913012] usbcore: registered new interface driver usbhid
676 11:27:23.826488 <6>[ 1.919126] usbhid: USB HID core driver
677 11:27:23.838900 <6>[ 1.930856] NET: Registered PF_INET6 protocol family
678 11:27:24.310411 <6>[ 2.405018] Segment Routing with IPv6
679 11:27:24.316266 <6>[ 2.409160] In-situ OAM (IOAM) with IPv6
680 11:27:24.323067 <6>[ 2.413673] sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver
681 11:27:24.328884 <6>[ 2.421070] NET: Registered PF_PACKET protocol family
682 11:27:24.334693 <6>[ 2.426642] can: controller area network core
683 11:27:24.340494 <6>[ 2.431479] NET: Registered PF_CAN protocol family
684 11:27:24.341017 <6>[ 2.436711] can: raw protocol
685 11:27:24.346231 <6>[ 2.440038] can: broadcast manager protocol
686 11:27:24.352865 <6>[ 2.444634] can: netlink gateway - max_hops=1
687 11:27:24.358883 <5>[ 2.450138] Key type dns_resolver registered
688 11:27:24.365186 <6>[ 2.455214] ThumbEE CPU extension supported.
689 11:27:24.365717 <5>[ 2.459902] Registering SWP/SWPB emulation handler
690 11:27:24.374926 <3>[ 2.465611] omap_voltage_late_init: Voltage driver support not added
691 11:27:24.598243 <5>[ 2.690375] Loading compiled-in X.509 certificates
692 11:27:24.661998 <6>[ 2.741841] /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70: Fixed dependency cycle(s) with /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
693 11:27:24.691973 <6>[ 2.771703] /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70: Fixed dependency cycle(s) with /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
694 11:27:24.836421 <6>[ 2.912026] /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70: Fixed dependency cycle(s) with /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
695 11:27:24.851997 <6>[ 2.931748] /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70: Fixed dependency cycle(s) with /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
696 11:27:24.879026 <6>[ 2.958510] /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800/clkout2-pins
697 11:27:24.889206 <6>[ 2.980055] pinctrl-single 44e10800.pinmux: 142 pins, size 568
698 11:27:24.916030 <3>[ 3.004542] ti-sysc 44e31000.target-module: probe with driver ti-sysc failed with error -16
699 11:27:25.187288 <6>[ 3.267062] /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
700 11:27:25.213700 <3>[ 3.302278] ti-sysc 48040000.target-module: probe with driver ti-sysc failed with error -16
701 11:27:25.381784 <6>[ 3.474626] OMAP GPIO hardware version 0.1
702 11:27:25.402942 <6>[ 3.493862] omap-mailbox 480c8000.mailbox: omap mailbox rev 0x400
703 11:27:25.464615 <4>[ 3.555327] at24 2-0054: supply vcc not found, using dummy regulator
704 11:27:25.497787 <4>[ 3.588451] at24 2-0055: supply vcc not found, using dummy regulator
705 11:27:25.536908 <4>[ 3.627567] at24 2-0056: supply vcc not found, using dummy regulator
706 11:27:25.576422 <4>[ 3.666860] at24 2-0057: supply vcc not found, using dummy regulator
707 11:27:25.628062 <6>[ 3.721842] Freeing initrd memory: 15028K
708 11:27:25.635741 <6>[ 3.727185] omap_i2c 4819c000.i2c: bus 2 rev0.11 at 100 kHz
709 11:27:25.671686 <3>[ 3.759083] 48000000.interconnect:segment@200000:target-module@0:mpu@0:fck: device ID is greater than 24
710 11:27:25.693999 <6>[ 3.773727] /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
711 11:27:25.721285 <6>[ 3.797234] /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
712 11:27:25.738588 <6>[ 3.816516] /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70: Fixed dependency cycle(s) with /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
713 11:27:25.754706 <6>[ 3.834485] /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
714 11:27:25.776670 <4>[ 3.864916] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
715 11:27:25.784573 <4>[ 3.873835] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
716 11:27:25.793217 <6>[ 3.884053] omap_rng 48310000.rng: Random Number Generator ver. 20
717 11:27:25.817369 <5>[ 3.911044] random: crng init done
718 11:27:25.863879 <6>[ 3.953215] davinci_mdio 4a101000.mdio: davinci mdio revision 1.6, bus freq 1000000
719 11:27:25.947323 <6>[ 4.035598] davinci_mdio 4a101000.mdio: phy[0]: device 4a101000.mdio:00, driver SMSC LAN8710/LAN8720
720 11:27:25.952957 <6>[ 4.045940] cpsw-switch 4a100000.switch: initialized cpsw ale version 1.4
721 11:27:25.964707 <6>[ 4.053277] cpsw-switch 4a100000.switch: ALE Table size 1024, Policers 0
722 11:27:25.970563 <6>[ 4.060740] cpsw-switch 4a100000.switch: cpts: overflow check period 500 (jiffies)
723 11:27:25.982107 <6>[ 4.068890] cpsw-switch 4a100000.switch: CPTS: ref_clk_freq:250000000 calc_mult:2147483648 calc_shift:29 error:0 nsec/sec
724 11:27:25.989564 <6>[ 4.080530] cpsw-switch 4a100000.switch: Detected MACID = 90:59:af:5c:d5:d8
725 11:27:26.002720 <5>[ 4.089660] cpsw-switch 4a100000.switch: initialized (regs 0x4a100000, pool size 256) hw_ver:0019010C 1.12 (0)
726 11:27:26.031396 <3>[ 4.120098] debugfs: Directory '49000000.dma' with parent 'dmaengine' already present!
727 11:27:26.036937 <6>[ 4.128739] edma 49000000.dma: TI EDMA DMA engine driver
728 11:27:26.110044 <3>[ 4.198266] target-module@4b000000:target-module@140000:pmu@0:fck: device ID is greater than 24
729 11:27:26.124860 <6>[ 4.212772] hw perfevents: enabled with armv7_cortex_a8 PMU driver, 5 (8000000f) counters available
730 11:27:26.137893 <3>[ 4.229980] l3-aon-clkctrl:0000:0: failed to disable
731 11:27:26.193167 <6>[ 4.282040] 44e09000.serial: ttyS0 at MMIO 0x44e09000 (irq = 36, base_baud = 3000000) is a 8250
732 11:27:26.198878 <6>[ 4.291565] printk: legacy console [ttyS0] enabled
733 11:27:26.204536 <6>[ 4.291565] printk: legacy console [ttyS0] enabled
734 11:27:26.210344 <6>[ 4.301903] printk: legacy bootconsole [omap8250] disabled
735 11:27:26.216068 <6>[ 4.301903] printk: legacy bootconsole [omap8250] disabled
736 11:27:26.246085 <4>[ 4.333979] tps65217-pmic: Failed to locate of_node [id: -1]
737 11:27:26.249646 <4>[ 4.341381] tps65217-bl: Failed to locate of_node [id: -1]
738 11:27:26.266535 <6>[ 4.361516] tps65217 0-0024: TPS65217 ID 0xe version 1.2
739 11:27:26.286960 <6>[ 4.368527] /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
740 11:27:26.304358 <6>[ 4.386179] /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70: Fixed dependency cycle(s) with /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
741 11:27:26.312447 <6>[ 4.404039] omap_i2c 44e0b000.i2c: bus 0 rev0.11 at 400 kHz
742 11:27:26.335185 <6>[ 4.424437] omap_gpio 44e07000.gpio: Could not set line 6 debounce to 200000 microseconds (-22)
743 11:27:26.341009 <6>[ 4.433602] sdhci-omap 48060000.mmc: Got CD GPIO
744 11:27:26.348115 <4>[ 4.438727] sdhci-omap 48060000.mmc: supply pbias not found, using dummy regulator
745 11:27:26.364001 <4>[ 4.452415] sdhci-omap 48060000.mmc: supply vqmmc not found, using dummy regulator
746 11:27:26.370371 <4>[ 4.461239] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
747 11:27:26.380239 <4>[ 4.469892] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
748 11:27:26.425647 <6>[ 4.514000] at24 0-0050: 32768 byte 24c256 EEPROM, writable, 1 bytes/write
749 11:27:26.432735 <6>[ 4.522204] mmc0: SDHCI controller on 48060000.mmc [48060000.mmc] using External DMA
750 11:27:26.444036 <6>[ 4.533454] mmc1: SDHCI controller on 481d8000.mmc [481d8000.mmc] using External DMA
751 11:27:26.468587 <6>[ 4.560113] cpsw-switch 4a100000.switch: starting ndev. mode: dual_mac
752 11:27:26.494732 <6>[ 4.580290] mmc0: new high speed SDHC card at address 0001
753 11:27:26.495277 <6>[ 4.587592] mmcblk0: mmc0:0001 EB1QT 29.8 GiB
754 11:27:26.501949 <6>[ 4.596624] mmcblk0: p1
755 11:27:26.539833 <6>[ 4.625327] mmc1: new high speed MMC card at address 0001
756 11:27:26.540161 <6>[ 4.632649] mmcblk1: mmc1:0001 MMC02G 1.79 GiB
757 11:27:26.552920 <6>[ 4.641508] SMSC LAN8710/LAN8720 4a101000.mdio:00: attached PHY driver (mii_bus:phy_addr=4a101000.mdio:00, irq=POLL)
758 11:27:26.560869 <6>[ 4.653203] mmcblk1:
759 11:27:26.565713 <6>[ 4.658063] mmcblk1boot0: mmc1:0001 MMC02G 1.00 MiB
760 11:27:26.579012 <6>[ 4.671789] mmcblk1boot1: mmc1:0001 MMC02G 1.00 MiB
761 11:27:26.588104 <6>[ 4.679124] mmcblk1rpmb: mmc1:0001 MMC02G 128 KiB, chardev (236:0)
762 11:27:28.675141 <6>[ 6.764183] cpsw-switch 4a100000.switch eth0: Link is Up - 100Mbps/Full - flow control off
763 11:27:28.788620 <5>[ 6.803158] Sending DHCP requests ., OK
764 11:27:28.800070 <6>[ 6.887695] IP-Config: Got DHCP answer from 192.168.6.1, my address is 192.168.6.23
765 11:27:28.800637 <6>[ 6.895856] IP-Config: Complete:
766 11:27:28.811294 <6>[ 6.899397] device=eth0, hwaddr=90:59:af:5c:d5:d8, ipaddr=192.168.6.23, mask=255.255.255.0, gw=192.168.6.1
767 11:27:28.817084 <6>[ 6.909920] host=192.168.6.23, domain=, nis-domain=(none)
768 11:27:28.829465 <6>[ 6.916132] bootserver=192.168.6.1, rootserver=192.168.6.3, rootpath=
769 11:27:28.830395 <6>[ 6.916170] nameserver0=10.255.253.1
770 11:27:28.835491 <6>[ 6.928746] clk: Disabling unused clocks
771 11:27:28.841286 <6>[ 6.933485] PM: genpd: Disabling unused power domains
772 11:27:28.858986 <6>[ 6.950094] Freeing unused kernel image (initmem) memory: 2048K
773 11:27:28.866359 <6>[ 6.959955] Run /init as init process
774 11:27:28.893909 Loading, please wait...
775 11:27:28.969670 Starting systemd-udevd version 252.22-1~deb12u1
776 11:27:31.998190 <4>[ 10.085800] am335x-phy-driver 47401300.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
777 11:27:32.110810 <4>[ 10.198536] am335x-phy-driver 47401b00.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
778 11:27:32.277491 <6>[ 10.372591] musb-hdrc musb-hdrc.1: MUSB HDRC host driver
779 11:27:32.288331 <6>[ 10.378453] musb-hdrc musb-hdrc.1: new USB bus registered, assigned bus number 1
780 11:27:32.541107 <6>[ 10.634726] hub 1-0:1.0: USB hub found
781 11:27:32.627584 <6>[ 10.721127] hub 1-0:1.0: 1 port detected
782 11:27:32.673995 <6>[ 10.767279] tda998x 0-0070: found TDA19988
783 11:27:35.524001 Begin: Loading essential drivers ... done.
784 11:27:35.529563 Begin: Running /scripts/init-premount ... done.
785 11:27:35.535139 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
786 11:27:35.545334 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
787 11:27:35.553037 Device /sys/class/net/eth0 found
788 11:27:35.553560 done.
789 11:27:35.612873 Begin: Waiting up to 180 secs for any network device to become available ... done.
790 11:27:35.691579 IP-Config: eth0 hardware address 90:59:af:5c:d5:d8 mtu 1500 DHCP
791 11:27:35.813353 IP-Config: eth0 guessed broadcast address 192.168.6.255
792 11:27:35.818860 IP-Config: eth0 complete (dhcp from 192.168.6.1):
793 11:27:35.824397 address: 192.168.6.23 broadcast: 192.168.6.255 netmask: 255.255.255.0
794 11:27:35.835636 gateway: 192.168.6.1 dns0 : 10.255.253.1 dns1 : 0.0.0.0
795 11:27:35.836097 rootserver: 192.168.6.1 rootpath:
796 11:27:35.839127 filename :
797 11:27:35.916933 done.
798 11:27:35.931527 Begin: Running /scripts/nfs-bottom ... done.
799 11:27:36.007428 Begin: Running /scripts/init-bottom ... done.
800 11:27:37.446367 <30>[ 15.537112] systemd[1]: System time before build time, advancing clock.
801 11:27:37.625241 <30>[ 15.689852] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
802 11:27:37.634187 <30>[ 15.726928] systemd[1]: Detected architecture arm.
803 11:27:37.647699
804 11:27:37.648176 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
805 11:27:37.648598
806 11:27:37.671449 <30>[ 15.762957] systemd[1]: Hostname set to <debian-bookworm-armhf>.
807 11:27:39.810999 <30>[ 17.901319] systemd[1]: Queued start job for default target graphical.target.
808 11:27:39.828304 <30>[ 17.916424] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
809 11:27:39.835769 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
810 11:27:39.857890 <30>[ 17.946253] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
811 11:27:39.865237 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
812 11:27:39.888144 <30>[ 17.976639] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
813 11:27:39.895796 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
814 11:27:39.916349 <30>[ 18.005163] systemd[1]: Created slice user.slice - User and Session Slice.
815 11:27:39.922192 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
816 11:27:39.951398 <30>[ 18.034535] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
817 11:27:39.957440 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
818 11:27:39.975363 <30>[ 18.064327] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
819 11:27:39.984384 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
820 11:27:40.013375 <30>[ 18.094332] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
821 11:27:40.025864 <30>[ 18.114883] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
822 11:27:40.030340 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
823 11:27:40.054526 <30>[ 18.143688] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
824 11:27:40.062812 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
825 11:27:40.085257 <30>[ 18.174031] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
826 11:27:40.094286 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
827 11:27:40.114973 <30>[ 18.204132] systemd[1]: Reached target paths.target - Path Units.
828 11:27:40.119199 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
829 11:27:40.144691 <30>[ 18.233840] systemd[1]: Reached target remote-fs.target - Remote File Systems.
830 11:27:40.152072 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
831 11:27:40.174566 <30>[ 18.263699] systemd[1]: Reached target slices.target - Slice Units.
832 11:27:40.180014 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
833 11:27:40.206478 <30>[ 18.294971] systemd[1]: Reached target swap.target - Swaps.
834 11:27:40.210485 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
835 11:27:40.234915 <30>[ 18.323845] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
836 11:27:40.243804 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
837 11:27:40.266007 <30>[ 18.354840] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
838 11:27:40.274371 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
839 11:27:40.356142 <30>[ 18.440103] systemd[1]: systemd-journald-audit.socket - Journal Audit Socket was skipped because of an unmet condition check (ConditionSecurity=audit).
840 11:27:40.369068 <30>[ 18.457842] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
841 11:27:40.377456 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
842 11:27:40.406796 <30>[ 18.494973] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
843 11:27:40.414119 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
844 11:27:40.438401 <30>[ 18.526841] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
845 11:27:40.446402 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
846 11:27:40.476449 <30>[ 18.564438] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
847 11:27:40.482001 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
848 11:27:40.506014 <30>[ 18.594829] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
849 11:27:40.514611 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
850 11:27:40.542125 <30>[ 18.624994] systemd[1]: dev-hugepages.mount - Huge Pages File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/mm/hugepages).
851 11:27:40.557866 <30>[ 18.641606] systemd[1]: dev-mqueue.mount - POSIX Message Queue File System was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/mqueue).
852 11:27:40.608963 <30>[ 18.698812] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
853 11:27:40.634155 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
854 11:27:40.684687 <30>[ 18.774337] systemd[1]: Mounting sys-kernel-tracing.mount - Kernel Trace File System...
855 11:27:40.706978 Mounting [0;1;39msys-kernel-tracin…[0m - Kernel Trace File System...
856 11:27:40.805653 <30>[ 18.894323] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
857 11:27:40.835068 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
858 11:27:40.886065 <30>[ 18.976030] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
859 11:27:40.912566 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
860 11:27:40.965428 <30>[ 19.055103] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
861 11:27:40.993710 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
862 11:27:41.047273 <30>[ 19.137471] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
863 11:27:41.074619 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
864 11:27:41.127037 <30>[ 19.216007] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
865 11:27:41.154660 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
866 11:27:41.205041 <30>[ 19.295092] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
867 11:27:41.224233 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
868 11:27:41.255091 <30>[ 19.345107] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
869 11:27:41.283517 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
870 11:27:41.313992 <28>[ 19.396047] systemd[1]: systemd-journald.service: unit configures an IP firewall, but the local system does not support BPF/cgroup firewalling.
871 11:27:41.322515 <28>[ 19.411683] systemd[1]: (This warning is only shown for the first unit using IP firewalling.)
872 11:27:41.364114 <30>[ 19.454587] systemd[1]: Starting systemd-journald.service - Journal Service...
873 11:27:41.392298 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
874 11:27:41.455602 <30>[ 19.545336] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
875 11:27:41.474091 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
876 11:27:41.506450 <30>[ 19.596375] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
877 11:27:41.558155 Starting [0;1;39msystemd-network-g… units from Kernel command line...
878 11:27:41.640584 <30>[ 19.729070] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
879 11:27:41.688253 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
880 11:27:41.748505 <30>[ 19.838627] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
881 11:27:41.824473 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
882 11:27:41.894768 <30>[ 19.984938] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
883 11:27:41.933779 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
884 11:27:41.954835 <30>[ 20.044844] systemd[1]: Mounted sys-kernel-tracing.mount - Kernel Trace File System.
885 11:27:41.975349 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-tracing…nt[0m - Kernel Trace File System.
886 11:27:42.006542 <30>[ 20.095422] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
887 11:27:42.030659 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
888 11:27:42.165629 <30>[ 20.256163] systemd[1]: modprobe@configfs.service: Deactivated successfully.
889 11:27:42.204406 <30>[ 20.293832] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
890 11:27:42.233663 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
891 11:27:42.255147 <30>[ 20.346006] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
892 11:27:42.284581 <30>[ 20.373799] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
893 11:27:42.293015 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
894 11:27:42.315604 <30>[ 20.404852] systemd[1]: Started systemd-journald.service - Journal Service.
895 11:27:42.322442 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
896 11:27:42.355641 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
897 11:27:42.387157 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
898 11:27:42.416026 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
899 11:27:42.440409 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
900 11:27:42.474816 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
901 11:27:42.498158 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
902 11:27:42.517158 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
903 11:27:42.539336 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
904 11:27:42.604142 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
905 11:27:42.645300 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
906 11:27:42.708803 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
907 11:27:42.780603 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
908 11:27:42.834628 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
909 11:27:42.995683 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
910 11:27:43.098447 <46>[ 21.188329] systemd-journald[164]: Received client request to flush runtime journal.
911 11:27:43.166639 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
912 11:27:43.255980 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
913 11:27:44.051648 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
914 11:27:44.107020 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
915 11:27:44.778425 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
916 11:27:44.957966 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
917 11:27:44.986713 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
918 11:27:45.005453 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
919 11:27:45.075194 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
920 11:27:45.135578 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
921 11:27:46.098337 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
922 11:27:46.166350 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
923 11:27:46.354741 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
924 11:27:46.456750 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
925 11:27:46.500176 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
926 11:27:48.166340 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
927 11:27:48.681899 <5>[ 26.771976] cfg80211: Loading compiled-in X.509 certificates for regulatory database
928 11:27:49.385090 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
929 11:27:50.143486 <5>[ 28.235753] Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
930 11:27:50.227310 <5>[ 28.318046] Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
931 11:27:50.244889 <4>[ 28.334827] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
932 11:27:50.250879 <6>[ 28.343956] cfg80211: failed to load regulatory.db
933 11:27:50.477392 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
934 11:27:51.089851 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
935 11:27:51.209601 <46>[ 29.290764] systemd-journald[164]: Oldest entry in /var/log/journal/658c871cd7314ccea6115dc5728f8992/system.journal is older than the configured file retention duration (1month), suggesting rotation.
936 11:27:51.239243 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
937 11:27:51.359972 <46>[ 29.443279] systemd-journald[164]: /var/log/journal/658c871cd7314ccea6115dc5728f8992/system.journal: Journal header limits reached or header out-of-date, rotating.
938 11:28:00.163290 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
939 11:28:00.185296 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
940 11:28:00.206286 [[0;32m OK [0m] Reached target [0;1;39musb-gadget.…m - Hardware activated USB gadget.
941 11:28:00.226698 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
942 11:28:00.284688 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
943 11:28:00.328247 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
944 11:28:00.396515 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
945 11:28:00.464345 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
946 11:28:00.509673 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
947 11:28:00.542012 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
948 11:28:00.572399 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
949 11:28:00.600181 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
950 11:28:00.641183 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
951 11:28:00.674385 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
952 11:28:00.708276 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
953 11:28:00.742605 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
954 11:28:00.787464 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
955 11:28:00.822399 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
956 11:28:00.846246 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
957 11:28:00.867148 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
958 11:28:00.912782 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
959 11:28:00.932964 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
960 11:28:00.957095 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
961 11:28:01.034849 Starting [0;1;39malsa-restore.serv…- Save/Restore Sound Card State...
962 11:28:01.129202 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
963 11:28:01.233111 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
964 11:28:01.325859 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
965 11:28:01.366552 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
966 11:28:01.422188 [[0;32m OK [0m] Finished [0;1;39malsa-restore.serv…m - Save/Restore Sound Card State.
967 11:28:01.447113 [[0;32m OK [0m] Reached target [0;1;39msound.target[0m - Sound Card.
968 11:28:01.637092 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
969 11:28:01.704883 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
970 11:28:01.766788 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
971 11:28:01.784723 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
972 11:28:01.806132 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
973 11:28:02.033378 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
974 11:28:02.338753 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
975 11:28:02.390920 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
976 11:28:02.420162 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
977 11:28:02.513613 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
978 11:28:02.691165 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
979 11:28:02.823837
980 11:28:02.827424 Debian GNU/Linux 12 worm-armhf login: root (automatic login)
981 11:28:02.827940
982 11:28:03.161664 Linux debian-bookworm-armhf 6.12.0-rc6-next-20241108 #1 SMP Fri Nov 8 10:29:39 UTC 2024 armv7l
983 11:28:03.162408
984 11:28:03.167120 The programs included with the Debian GNU/Linux system are free software;
985 11:28:03.176180 the exact distribution terms for each program are described in the
986 11:28:03.176759 individual files in /usr/share/doc/*/copyright.
987 11:28:03.177239
988 11:28:03.187557 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
989 11:28:03.188105 permitted by applicable law.
990 11:28:07.893246 Unable to match end of the kernel message
992 11:28:07.895000 Setting prompt string to ['/ #']
993 11:28:07.895638 end: 2.4.4.1 login-action (duration 00:00:46) [common]
995 11:28:07.897173 end: 2.4.4 auto-login-action (duration 00:00:47) [common]
996 11:28:07.897792 start: 2.4.5 expect-shell-connection (timeout 00:03:11) [common]
997 11:28:07.898380 Setting prompt string to ['/ #']
998 11:28:07.898869 Forcing a shell prompt, looking for ['/ #']
1000 11:28:07.949894 / #
1001 11:28:07.950663 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
1002 11:28:07.951188 Waiting using forced prompt support (timeout 00:02:30)
1003 11:28:07.956762
1004 11:28:07.962259 end: 2.4.5 expect-shell-connection (duration 00:00:00) [common]
1005 11:28:07.962903 start: 2.4.6 export-device-env (timeout 00:03:10) [common]
1006 11:28:07.963440 Sending with 10 millisecond of delay
1008 11:28:12.951166 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/958774/extract-nfsrootfs-pf6y72e4'
1009 11:28:12.962110 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/958774/extract-nfsrootfs-pf6y72e4'
1010 11:28:12.963285 Sending with 10 millisecond of delay
1012 11:28:15.061388 / # export NFS_SERVER_IP='192.168.6.3'
1013 11:28:15.072599 export NFS_SERVER_IP='192.168.6.3'
1014 11:28:15.073882 end: 2.4.6 export-device-env (duration 00:00:07) [common]
1015 11:28:15.074771 end: 2.4 uboot-commands (duration 00:01:57) [common]
1016 11:28:15.075646 end: 2 uboot-action (duration 00:01:57) [common]
1017 11:28:15.076475 start: 3 lava-test-retry (timeout 00:06:52) [common]
1018 11:28:15.077359 start: 3.1 lava-test-shell (timeout 00:06:52) [common]
1019 11:28:15.078096 Using namespace: common
1021 11:28:15.179775 / # #
1022 11:28:15.180692 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
1023 11:28:15.184402 #
1024 11:28:15.191521 Using /lava-958774
1026 11:28:15.293199 / # export SHELL=/bin/bash
1027 11:28:15.298949 export SHELL=/bin/bash
1029 11:28:15.406340 / # . /lava-958774/environment
1030 11:28:15.412126 . /lava-958774/environment
1032 11:28:15.526490 / # /lava-958774/bin/lava-test-runner /lava-958774/0
1033 11:28:15.527572 Test shell timeout: 10s (minimum of the action and connection timeout)
1034 11:28:15.532333 /lava-958774/bin/lava-test-runner /lava-958774/0
1035 11:28:15.926076 + export TESTRUN_ID=0_timesync-off
1036 11:28:15.933950 + TESTRUN_ID=0_timesync-off
1037 11:28:15.934590 + cd /lava-958774/0/tests/0_timesync-off
1038 11:28:15.935132 ++ cat uuid
1039 11:28:15.958580 + UUID=958774_1.6.2.4.1
1040 11:28:15.959197 + set +x
1041 11:28:15.967148 <LAVA_SIGNAL_STARTRUN 0_timesync-off 958774_1.6.2.4.1>
1042 11:28:15.967764 + systemctl stop systemd-timesyncd
1043 11:28:15.968791 Received signal: <STARTRUN> 0_timesync-off 958774_1.6.2.4.1
1044 11:28:15.969445 Starting test lava.0_timesync-off (958774_1.6.2.4.1)
1045 11:28:15.970139 Skipping test definition patterns.
1046 11:28:16.307011 + set +x
1047 11:28:16.307597 <LAVA_SIGNAL_ENDRUN 0_timesync-off 958774_1.6.2.4.1>
1048 11:28:16.308289 Received signal: <ENDRUN> 0_timesync-off 958774_1.6.2.4.1
1049 11:28:16.308797 Ending use of test pattern.
1050 11:28:16.309212 Ending test lava.0_timesync-off (958774_1.6.2.4.1), duration 0.34
1052 11:28:16.464961 + export TESTRUN_ID=1_kselftest-dt
1053 11:28:16.472918 + TESTRUN_ID=1_kselftest-dt
1054 11:28:16.473406 + cd /lava-958774/0/tests/1_kselftest-dt
1055 11:28:16.473862 ++ cat uuid
1056 11:28:16.490355 + UUID=958774_1.6.2.4.5
1057 11:28:16.490866 + set +x
1058 11:28:16.495963 <LAVA_SIGNAL_STARTRUN 1_kselftest-dt 958774_1.6.2.4.5>
1059 11:28:16.496449 + cd ./automated/linux/kselftest/
1060 11:28:16.497134 Received signal: <STARTRUN> 1_kselftest-dt 958774_1.6.2.4.5
1061 11:28:16.497575 Starting test lava.1_kselftest-dt (958774_1.6.2.4.5)
1062 11:28:16.498108 Skipping test definition patterns.
1063 11:28:16.521844 + ./kselftest.sh -c dt -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/next/master/next-20241108/arm/multi_v7_defconfig/clang-17/kselftest.tar.xz -L '' -S /dev/null -b beaglebone-black -g next -e '' -p /opt/kselftests/mainline/ -n 1 -i 1 -E ''
1064 11:28:16.650422 INFO: install_deps skipped
1065 11:28:17.244250 --2024-11-08 11:28:17-- http://storage.kernelci.org/next/master/next-20241108/arm/multi_v7_defconfig/clang-17/kselftest.tar.xz
1066 11:28:17.497460 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
1067 11:28:17.634527 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
1068 11:28:17.770816 HTTP request sent, awaiting response... 200 OK
1069 11:28:17.771318 Length: 2739884 (2.6M) [application/octet-stream]
1070 11:28:17.776495 Saving to: 'kselftest_armhf.tar.gz'
1071 11:28:17.776945
1072 11:28:19.020318
kselftest_armhf.tar 0%[ ] 0 --.-KB/s
kselftest_armhf.tar 1%[ ] 49.92K 187KB/s
kselftest_armhf.tar 8%[> ] 218.67K 402KB/s
kselftest_armhf.tar 31%[=====> ] 836.45K 891KB/s
kselftest_armhf.tar 88%[================> ] 2.31M 1.91MB/s
kselftest_armhf.tar 100%[===================>] 2.61M 2.10MB/s in 1.2s
1073 11:28:19.020981
1074 11:28:19.497183 2024-11-08 11:28:18 (2.10 MB/s) - 'kselftest_armhf.tar.gz' saved [2739884/2739884]
1075 11:28:19.497908
1076 11:28:32.884380 skiplist:
1077 11:28:32.885068 ========================================
1078 11:28:32.889917 ========================================
1079 11:28:33.007881 dt:test_unprobed_devices.sh
1080 11:28:33.044990 ============== Tests to run ===============
1081 11:28:33.052948 dt:test_unprobed_devices.sh
1082 11:28:33.056853 ===========End Tests to run ===============
1083 11:28:33.067767 shardfile-dt pass
1084 11:28:33.301474 <12>[ 71.396604] kselftest: Running tests in dt
1085 11:28:33.332281 TAP version 13
1086 11:28:33.355551 1..1
1087 11:28:33.410207 # timeout set to 45
1088 11:28:33.410844 # selftests: dt: test_unprobed_devices.sh
1089 11:28:34.308067 # TAP version 13
1090 11:28:59.684420 # 1..257
1091 11:28:59.890308 # ok 1 / # SKIP
1092 11:28:59.912588 # ok 2 /clk_mcasp0
1093 11:28:59.990473 # ok 3 /clk_mcasp0_fixed # SKIP
1094 11:29:00.063450 # ok 4 /cpus/cpu@0 # SKIP
1095 11:29:00.136264 # ok 5 /cpus/idle-states/mpu_gate # SKIP
1096 11:29:00.162028 # ok 6 /fixedregulator0
1097 11:29:00.175072 # ok 7 /leds
1098 11:29:00.202612 # ok 8 /ocp
1099 11:29:00.222693 # ok 9 /ocp/interconnect@44c00000
1100 11:29:00.252710 # ok 10 /ocp/interconnect@44c00000/segment@0
1101 11:29:00.271640 # ok 11 /ocp/interconnect@44c00000/segment@100000
1102 11:29:00.298438 # ok 12 /ocp/interconnect@44c00000/segment@100000/target-module@0
1103 11:29:00.371122 # not ok 13 /ocp/interconnect@44c00000/segment@100000/target-module@0/cpu@0
1104 11:29:00.388626 # ok 14 /ocp/interconnect@44c00000/segment@200000
1105 11:29:00.415115 # ok 15 /ocp/interconnect@44c00000/segment@200000/target-module@0
1106 11:29:00.523015 # not ok 16 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0
1107 11:29:00.596962 # ok 17 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0 # SKIP
1108 11:29:00.676325 # ok 18 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@0 # SKIP
1109 11:29:00.745067 # ok 19 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@120 # SKIP
1110 11:29:00.817926 # ok 20 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@14c # SKIP
1111 11:29:00.896440 # ok 21 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@18 # SKIP
1112 11:29:00.965635 # ok 22 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@1c # SKIP
1113 11:29:01.038861 # ok 23 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@24 # SKIP
1114 11:29:01.113450 # ok 24 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@38 # SKIP
1115 11:29:01.186910 # ok 25 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@e8 # SKIP
1116 11:29:01.259995 # ok 26 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400 # SKIP
1117 11:29:01.334554 # ok 27 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@0 # SKIP
1118 11:29:01.408588 # ok 28 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@14 # SKIP
1119 11:29:01.482539 # ok 29 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@b0 # SKIP
1120 11:29:01.555007 # ok 30 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600 # SKIP
1121 11:29:01.629733 # ok 31 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600/clock@0 # SKIP
1122 11:29:01.706580 # ok 32 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800 # SKIP
1123 11:29:01.779244 # ok 33 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800/clock@0 # SKIP
1124 11:29:01.850697 # ok 34 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900 # SKIP
1125 11:29:01.924570 # ok 35 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900/clock@0 # SKIP
1126 11:29:01.996892 # ok 36 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00 # SKIP
1127 11:29:02.071936 # ok 37 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00/clock@0 # SKIP
1128 11:29:02.144310 # ok 38 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-24mhz # SKIP
1129 11:29:02.218344 # ok 39 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-32768 # SKIP
1130 11:29:02.297415 # ok 40 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-rc32k # SKIP
1131 11:29:02.371150 # ok 41 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clkdiv32k # SKIP
1132 11:29:02.442133 # ok 42 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-125mhz-gclk # SKIP
1133 11:29:02.514918 # ok 43 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-cpts-rft@520 # SKIP
1134 11:29:02.588441 # ok 44 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4-div2 # SKIP
1135 11:29:02.662244 # ok 45 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4@480 # SKIP
1136 11:29:02.733952 # ok 46 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m5@484 # SKIP
1137 11:29:02.811229 # ok 47 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m6@4d8 # SKIP
1138 11:29:02.883116 # ok 48 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-x2 # SKIP
1139 11:29:02.956861 # ok 49 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2-div2 # SKIP
1140 11:29:03.030412 # ok 50 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2@4a0 # SKIP
1141 11:29:03.108784 # ok 51 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-disp-m2@4a4 # SKIP
1142 11:29:03.182130 # ok 52 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-mpu-m2@4a8 # SKIP
1143 11:29:03.250935 # ok 53 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4 # SKIP
1144 11:29:03.329448 # ok 54 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4-wkupdm # SKIP
1145 11:29:03.399079 # ok 55 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2@4ac # SKIP
1146 11:29:03.474403 # ok 56 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-gpio0-dbclk-mux@53c # SKIP
1147 11:29:03.544899 # ok 57 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-ieee5000-fck-1@e4 # SKIP
1148 11:29:03.617715 # ok 58 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3-gclk # SKIP
1149 11:29:03.690982 # ok 59 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3s-gclk # SKIP
1150 11:29:03.769204 # ok 60 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4-rtc-gclk # SKIP
1151 11:29:03.845021 # ok 61 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4fw-gclk # SKIP
1152 11:29:03.916981 # ok 62 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4hs-gclk # SKIP
1153 11:29:03.990983 # ok 63 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4ls-gclk # SKIP
1154 11:29:04.064585 # ok 64 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-lcd-gclk@534 # SKIP
1155 11:29:04.136145 # ok 65 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmc # SKIP
1156 11:29:04.210608 # ok 66 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmu-fck-1@914 # SKIP
1157 11:29:04.284923 # ok 67 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-pruss-ocp-gclk@530 # SKIP
1158 11:29:04.357606 # ok 68 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-sysclk-div # SKIP
1159 11:29:04.430763 # ok 69 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-tclkin # SKIP
1160 11:29:04.505437 # ok 70 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer1-fck@528 # SKIP
1161 11:29:04.578805 # ok 71 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer2-fck@508 # SKIP
1162 11:29:04.656760 # ok 72 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer3-fck@50c # SKIP
1163 11:29:04.726632 # ok 73 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer4-fck@510 # SKIP
1164 11:29:04.799302 # ok 74 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer5-fck@518 # SKIP
1165 11:29:04.872991 # ok 75 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer6-fck@51c # SKIP
1166 11:29:04.947486 # ok 76 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer7-fck@504 # SKIP
1167 11:29:05.021277 # ok 77 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-usbotg-fck-8@47c # SKIP
1168 11:29:05.094266 # ok 78 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-19200000 # SKIP
1169 11:29:05.167291 # ok 79 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-24000000 # SKIP
1170 11:29:05.239997 # ok 80 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-25000000 # SKIP
1171 11:29:05.313144 # ok 81 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-26000000 # SKIP
1172 11:29:05.386155 # ok 82 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-wdt1-fck@538 # SKIP
1173 11:29:05.459011 # ok 83 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@488 # SKIP
1174 11:29:05.532227 # ok 84 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@48c # SKIP
1175 11:29:05.606032 # ok 85 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@490 # SKIP
1176 11:29:05.678642 # ok 86 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@494 # SKIP
1177 11:29:05.756349 # ok 87 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@498 # SKIP
1178 11:29:05.825212 # ok 88 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c # SKIP
1179 11:29:05.902769 # ok 89 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fck-div@0 # SKIP
1180 11:29:05.976229 # ok 90 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fclk-clksel@1 # SKIP
1181 11:29:06.044421 # ok 91 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700 # SKIP
1182 11:29:06.119939 # ok 92 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2-div@3 # SKIP
1183 11:29:06.198588 # ok 93 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2@7 # SKIP
1184 11:29:06.272908 # ok 94 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-sysclkout-pre@0 # SKIP
1185 11:29:06.290606 # ok 95 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1000
1186 11:29:06.315649 # ok 96 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1100
1187 11:29:06.344845 # ok 97 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1200
1188 11:29:06.369134 # ok 98 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@c00
1189 11:29:06.389452 # ok 99 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@d00
1190 11:29:06.417872 # ok 100 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@e00
1191 11:29:06.439727 # ok 101 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@f00
1192 11:29:06.466192 # ok 102 /ocp/interconnect@44c00000/segment@200000/target-module@10000
1193 11:29:06.573742 # not ok 103 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0
1194 11:29:06.598705 # ok 104 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/control@620
1195 11:29:06.620547 # ok 105 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/dma-router@f90
1196 11:29:06.648427 # ok 106 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800
1197 11:29:06.751690 # not ok 107 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0
1198 11:29:06.832771 # ok 108 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-adc-tsc-fck # SKIP
1199 11:29:06.903841 # ok 109 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-aes0-fck # SKIP
1200 11:29:06.976053 # ok 110 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan0-fck # SKIP
1201 11:29:07.052831 # ok 111 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan1-fck # SKIP
1202 11:29:07.126293 # ok 112 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp0-fck # SKIP
1203 11:29:07.199506 # ok 113 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp1-fck # SKIP
1204 11:29:07.277798 # ok 114 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-rng-fck # SKIP
1205 11:29:07.347680 # ok 115 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sha0-fck # SKIP
1206 11:29:07.422284 # ok 116 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex0-fck # SKIP
1207 11:29:07.495916 # ok 117 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex1-fck # SKIP
1208 11:29:07.569488 # ok 118 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sys-clkin-22@40 # SKIP
1209 11:29:07.641607 # ok 119 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664 # SKIP
1210 11:29:07.718007 # ok 120 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm0-tbclk@0 # SKIP
1211 11:29:07.791048 # ok 121 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm1-tbclk@1 # SKIP
1212 11:29:07.865026 # ok 122 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm2-tbclk@2 # SKIP
1213 11:29:07.886697 # ok 123 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/phy-gmii-sel
1214 11:29:07.957969 # not ok 124 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/wkup_m3_ipc@1324
1215 11:29:08.037468 # not ok 125 /ocp/interconnect@44c00000/segment@200000/target-module@31000
1216 11:29:08.105191 # ok 126 /ocp/interconnect@44c00000/segment@200000/target-module@31000/timer@0 # SKIP
1217 11:29:08.128522 # ok 127 /ocp/interconnect@44c00000/segment@200000/target-module@35000
1218 11:29:08.200482 # not ok 128 /ocp/interconnect@44c00000/segment@200000/target-module@35000/wdt@0
1219 11:29:08.223442 # ok 129 /ocp/interconnect@44c00000/segment@200000/target-module@3e000
1220 11:29:08.299502 # not ok 130 /ocp/interconnect@44c00000/segment@200000/target-module@3e000/rtc@0
1221 11:29:08.323504 # ok 131 /ocp/interconnect@44c00000/segment@200000/target-module@7000
1222 11:29:08.349211 # ok 132 /ocp/interconnect@44c00000/segment@200000/target-module@7000/gpio@0
1223 11:29:08.368566 # ok 133 /ocp/interconnect@44c00000/segment@200000/target-module@9000
1224 11:29:08.397564 # ok 134 /ocp/interconnect@44c00000/segment@200000/target-module@9000/serial@0
1225 11:29:08.418465 # ok 135 /ocp/interconnect@44c00000/segment@200000/target-module@b000
1226 11:29:08.441067 # ok 136 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0
1227 11:29:08.466090 # ok 137 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/eeprom@50
1228 11:29:08.546792 # ok 138 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/eeprom@50/nvmem-layout # SKIP
1229 11:29:08.565281 # ok 139 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
1230 11:29:08.589494 # ok 140 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24
1231 11:29:08.667096 # not ok 141 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/charger
1232 11:29:08.739039 # not ok 142 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/pwrbutton
1233 11:29:08.758376 # ok 143 /ocp/interconnect@44c00000/segment@200000/target-module@d000
1234 11:29:08.858679 # not ok 144 /ocp/interconnect@47c00000
1235 11:29:08.931272 # not ok 145 /ocp/interconnect@47c00000/segment@0
1236 11:29:08.955461 # ok 146 /ocp/interconnect@48000000
1237 11:29:08.976863 # ok 147 /ocp/interconnect@48000000/segment@0
1238 11:29:09.006738 # ok 148 /ocp/interconnect@48000000/segment@0/target-module@22000
1239 11:29:09.028166 # ok 149 /ocp/interconnect@48000000/segment@0/target-module@24000
1240 11:29:09.053460 # ok 150 /ocp/interconnect@48000000/segment@0/target-module@2a000
1241 11:29:09.078202 # ok 151 /ocp/interconnect@48000000/segment@0/target-module@30000
1242 11:29:09.098161 # ok 152 /ocp/interconnect@48000000/segment@0/target-module@38000
1243 11:29:09.126220 # ok 153 /ocp/interconnect@48000000/segment@0/target-module@38000/mcasp@0
1244 11:29:09.148154 # ok 154 /ocp/interconnect@48000000/segment@0/target-module@3c000
1245 11:29:09.218043 # not ok 155 /ocp/interconnect@48000000/segment@0/target-module@40000
1246 11:29:09.295963 # ok 156 /ocp/interconnect@48000000/segment@0/target-module@40000/timer@0 # SKIP
1247 11:29:09.318131 # ok 157 /ocp/interconnect@48000000/segment@0/target-module@42000
1248 11:29:09.340771 # ok 158 /ocp/interconnect@48000000/segment@0/target-module@42000/timer@0
1249 11:29:09.362497 # ok 159 /ocp/interconnect@48000000/segment@0/target-module@44000
1250 11:29:09.386868 # ok 160 /ocp/interconnect@48000000/segment@0/target-module@44000/timer@0
1251 11:29:09.410172 # ok 161 /ocp/interconnect@48000000/segment@0/target-module@46000
1252 11:29:09.434240 # ok 162 /ocp/interconnect@48000000/segment@0/target-module@46000/timer@0
1253 11:29:09.458046 # ok 163 /ocp/interconnect@48000000/segment@0/target-module@48000
1254 11:29:09.481903 # ok 164 /ocp/interconnect@48000000/segment@0/target-module@48000/timer@0
1255 11:29:09.503969 # ok 165 /ocp/interconnect@48000000/segment@0/target-module@4a000
1256 11:29:09.529589 # ok 166 /ocp/interconnect@48000000/segment@0/target-module@4a000/timer@0
1257 11:29:09.556976 # ok 167 /ocp/interconnect@48000000/segment@0/target-module@4c000
1258 11:29:09.578690 # ok 168 /ocp/interconnect@48000000/segment@0/target-module@4c000/gpio@0
1259 11:29:09.600382 # ok 169 /ocp/interconnect@48000000/segment@0/target-module@60000
1260 11:29:09.624683 # ok 170 /ocp/interconnect@48000000/segment@0/target-module@60000/mmc@0
1261 11:29:09.653198 # ok 171 /ocp/interconnect@48000000/segment@0/target-module@c8000
1262 11:29:09.673767 # ok 172 /ocp/interconnect@48000000/segment@0/target-module@c8000/mailbox@0
1263 11:29:09.696500 # ok 173 /ocp/interconnect@48000000/segment@0/target-module@ca000
1264 11:29:09.721757 # ok 174 /ocp/interconnect@48000000/segment@0/target-module@ca000/spinlock@0
1265 11:29:09.746682 # ok 175 /ocp/interconnect@48000000/segment@100000
1266 11:29:09.773002 # ok 176 /ocp/interconnect@48000000/segment@100000/target-module@9c000
1267 11:29:09.799018 # ok 177 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0
1268 11:29:09.868115 # not ok 178 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/eeprom@54
1269 11:29:09.942918 # ok 179 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/eeprom@54/nvmem-layout # SKIP
1270 11:29:10.014808 # not ok 180 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/eeprom@55
1271 11:29:10.091821 # ok 181 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/eeprom@55/nvmem-layout # SKIP
1272 11:29:10.161292 # not ok 182 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/eeprom@56
1273 11:29:10.241584 # ok 183 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/eeprom@56/nvmem-layout # SKIP
1274 11:29:10.311016 # not ok 184 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/eeprom@57
1275 11:29:10.385343 # ok 185 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/eeprom@57/nvmem-layout # SKIP
1276 11:29:10.406657 # ok 186 /ocp/interconnect@48000000/segment@100000/target-module@a0000
1277 11:29:10.429857 # ok 187 /ocp/interconnect@48000000/segment@100000/target-module@a6000
1278 11:29:10.454457 # ok 188 /ocp/interconnect@48000000/segment@100000/target-module@a8000
1279 11:29:10.481310 # ok 189 /ocp/interconnect@48000000/segment@100000/target-module@aa000
1280 11:29:10.501661 # ok 190 /ocp/interconnect@48000000/segment@100000/target-module@ac000
1281 11:29:10.527309 # ok 191 /ocp/interconnect@48000000/segment@100000/target-module@ac000/gpio@0
1282 11:29:10.550594 # ok 192 /ocp/interconnect@48000000/segment@100000/target-module@ae000
1283 11:29:10.575410 # ok 193 /ocp/interconnect@48000000/segment@100000/target-module@ae000/gpio@0
1284 11:29:10.604773 # ok 194 /ocp/interconnect@48000000/segment@100000/target-module@cc000
1285 11:29:10.623662 # ok 195 /ocp/interconnect@48000000/segment@100000/target-module@d0000
1286 11:29:10.647220 # ok 196 /ocp/interconnect@48000000/segment@100000/target-module@d8000
1287 11:29:10.672700 # ok 197 /ocp/interconnect@48000000/segment@100000/target-module@d8000/mmc@0
1288 11:29:10.696614 # ok 198 /ocp/interconnect@48000000/segment@200000
1289 11:29:10.724200 # ok 199 /ocp/interconnect@48000000/segment@200000/target-module@0
1290 11:29:10.799393 # ok 200 /ocp/interconnect@48000000/segment@200000/target-module@0/mpu@0 # SKIP
1291 11:29:10.816197 # ok 201 /ocp/interconnect@48000000/segment@300000
1292 11:29:10.841496 # ok 202 /ocp/interconnect@48000000/segment@300000/target-module@0
1293 11:29:10.868408 # ok 203 /ocp/interconnect@48000000/segment@300000/target-module@10000
1294 11:29:10.890926 # ok 204 /ocp/interconnect@48000000/segment@300000/target-module@10000/rng@0
1295 11:29:10.914152 # ok 205 /ocp/interconnect@48000000/segment@300000/target-module@2000
1296 11:29:10.940776 # ok 206 /ocp/interconnect@48000000/segment@300000/target-module@4000
1297 11:29:10.961340 # ok 207 /ocp/interconnect@48000000/segment@300000/target-module@e000
1298 11:29:11.036106 # not ok 208 /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
1299 11:29:11.059165 # ok 209 /ocp/interconnect@4a000000
1300 11:29:11.084435 # ok 210 /ocp/interconnect@4a000000/segment@0
1301 11:29:11.108217 # ok 211 /ocp/interconnect@4a000000/segment@0/target-module@100000
1302 11:29:11.131304 # ok 212 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0
1303 11:29:11.156615 # ok 213 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0/mdio@1000
1304 11:29:11.179119 # ok 214 /ocp/interconnect@4a000000/segment@0/target-module@300000
1305 11:29:11.253198 # not ok 215 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0
1306 11:29:11.361353 # ok 216 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/cfg@26000 # SKIP
1307 11:29:11.435622 # not ok 217 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/interrupt-controller@20000
1308 11:29:11.541675 # ok 218 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/mii-rt@32000 # SKIP
1309 11:29:11.614158 # not ok 219 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@34000
1310 11:29:11.686074 # not ok 220 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@38000
1311 11:29:11.788880 # not ok 221 /ocp/interconnect@4b140000
1312 11:29:11.866714 # not ok 222 /ocp/interconnect@4b140000/segment@0
1313 11:29:11.945366 # ok 223 /ocp/interrupt-controller@48200000 # SKIP
1314 11:29:11.960146 # ok 224 /ocp/target-module@40300000
1315 11:29:11.984338 # ok 225 /ocp/target-module@40300000/sram@0
1316 11:29:12.060077 # ok 226 /ocp/target-module@40300000/sram@0/pm-code-sram@0 # SKIP
1317 11:29:12.146216 # ok 227 /ocp/target-module@40300000/sram@0/pm-data-sram@1000 # SKIP
1318 11:29:12.165431 # ok 228 /ocp/target-module@47400000
1319 11:29:12.193264 # ok 229 /ocp/target-module@47400000/dma-controller@2000
1320 11:29:12.211551 # ok 230 /ocp/target-module@47400000/usb-phy@1300
1321 11:29:12.236700 # ok 231 /ocp/target-module@47400000/usb-phy@1b00
1322 11:29:12.261719 # ok 232 /ocp/target-module@47400000/usb@1400
1323 11:29:12.281304 # ok 233 /ocp/target-module@47400000/usb@1800
1324 11:29:12.305602 # ok 234 /ocp/target-module@47810000
1325 11:29:12.326502 # ok 235 /ocp/target-module@49000000
1326 11:29:12.349341 # ok 236 /ocp/target-module@49000000/dma@0
1327 11:29:12.375618 # ok 237 /ocp/target-module@49800000
1328 11:29:12.395518 # ok 238 /ocp/target-module@49800000/dma@0
1329 11:29:12.422196 # ok 239 /ocp/target-module@49900000
1330 11:29:12.446018 # ok 240 /ocp/target-module@49900000/dma@0
1331 11:29:12.463960 # ok 241 /ocp/target-module@49a00000
1332 11:29:12.492324 # ok 242 /ocp/target-module@49a00000/dma@0
1333 11:29:12.514000 # ok 243 /ocp/target-module@4c000000
1334 11:29:12.582907 # not ok 244 /ocp/target-module@4c000000/emif@0
1335 11:29:12.605755 # ok 245 /ocp/target-module@50000000
1336 11:29:12.627781 # ok 246 /ocp/target-module@53100000
1337 11:29:12.704422 # not ok 247 /ocp/target-module@53100000/sham@0
1338 11:29:12.725495 # ok 248 /ocp/target-module@53500000
1339 11:29:12.796030 # not ok 249 /ocp/target-module@53500000/aes@0
1340 11:29:12.817926 # ok 250 /ocp/target-module@56000000
1341 11:29:12.924703 # ok 251 /ocp/target-module@56000000/gpu@0 # SKIP
1342 11:29:12.993998 # ok 252 /opp-table # SKIP
1343 11:29:13.069712 # ok 253 /soc # SKIP
1344 11:29:13.086509 # ok 254 /sound
1345 11:29:13.110932 # ok 255 /target-module@4b000000
1346 11:29:13.137048 # ok 256 /target-module@4b000000/target-module@140000
1347 11:29:13.157921 # ok 257 /target-module@4b000000/target-module@140000/pmu@0
1348 11:29:13.166481 # # Totals: pass:117 fail:27 xfail:0 xpass:0 skip:113 error:0
1349 11:29:13.174457 not ok 1 selftests: dt: test_unprobed_devices.sh # exit=1
1350 11:29:15.288712 dt_test_unprobed_devices_sh_ skip
1351 11:29:15.294043 dt_test_unprobed_devices_sh_clk_mcasp0 pass
1352 11:29:15.299762 dt_test_unprobed_devices_sh_clk_mcasp0_fixed skip
1353 11:29:15.300276 dt_test_unprobed_devices_sh_cpus_cpu_0 skip
1354 11:29:15.305291 dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate skip
1355 11:29:15.310842 dt_test_unprobed_devices_sh_fixedregulator0 pass
1356 11:29:15.316474 dt_test_unprobed_devices_sh_leds pass
1357 11:29:15.316906 dt_test_unprobed_devices_sh_ocp pass
1358 11:29:15.321983 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 pass
1359 11:29:15.327566 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 pass
1360 11:29:15.333220 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 pass
1361 11:29:15.344433 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 pass
1362 11:29:15.350112 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 fail
1363 11:29:15.355699 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 pass
1364 11:29:15.366912 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 pass
1365 11:29:15.372438 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 fail
1366 11:29:15.383723 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 skip
1367 11:29:15.394888 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 skip
1368 11:29:15.406117 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 skip
1369 11:29:15.411675 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c skip
1370 11:29:15.422893 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 skip
1371 11:29:15.434096 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c skip
1372 11:29:15.445334 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 skip
1373 11:29:15.456500 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 skip
1374 11:29:15.462107 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 skip
1375 11:29:15.473402 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 skip
1376 11:29:15.484607 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 skip
1377 11:29:15.495776 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 skip
1378 11:29:15.507010 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 skip
1379 11:29:15.512673 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 skip
1380 11:29:15.523764 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 skip
1381 11:29:15.534967 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 skip
1382 11:29:15.546155 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 skip
1383 11:29:15.551791 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 skip
1384 11:29:15.562929 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 skip
1385 11:29:15.574117 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 skip
1386 11:29:15.585354 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 skip
1387 11:29:15.596534 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz skip
1388 11:29:15.602201 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 skip
1389 11:29:15.613405 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k skip
1390 11:29:15.624497 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k skip
1391 11:29:15.635687 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk skip
1392 11:29:15.646866 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 skip
1393 11:29:15.658112 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 skip
1394 11:29:15.669241 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 skip
1395 11:29:15.680450 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 skip
1396 11:29:15.691631 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 skip
1397 11:29:15.702822 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 skip
1398 11:29:15.714063 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 skip
1399 11:29:15.725216 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 skip
1400 11:29:15.736432 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 skip
1401 11:29:15.747584 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 skip
1402 11:29:15.758795 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 skip
1403 11:29:15.770035 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm skip
1404 11:29:15.781189 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac skip
1405 11:29:15.792372 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c skip
1406 11:29:15.803553 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 skip
1407 11:29:15.814766 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk skip
1408 11:29:15.825943 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk skip
1409 11:29:15.837139 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk skip
1410 11:29:15.848412 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk skip
1411 11:29:15.859523 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk skip
1412 11:29:15.870718 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk skip
1413 11:29:15.881925 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 skip
1414 11:29:15.887561 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc skip
1415 11:29:15.898674 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 skip
1416 11:29:15.909933 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 skip
1417 11:29:15.921091 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div skip
1418 11:29:15.932270 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin skip
1419 11:29:15.943471 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 skip
1420 11:29:15.954656 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 skip
1421 11:29:15.965879 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c skip
1422 11:29:15.977051 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 skip
1423 11:29:15.988234 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 skip
1424 11:29:15.999466 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c skip
1425 11:29:16.010657 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 skip
1426 11:29:16.021830 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c skip
1427 11:29:16.033034 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 skip
1428 11:29:16.044232 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 skip
1429 11:29:16.055416 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 skip
1430 11:29:16.066596 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 skip
1431 11:29:16.077792 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 skip
1432 11:29:16.083482 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 skip
1433 11:29:16.094562 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c skip
1434 11:29:16.105771 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 skip
1435 11:29:16.116971 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 skip
1436 11:29:16.128157 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 skip
1437 11:29:16.133787 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c skip
1438 11:29:16.150555 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 skip
1439 11:29:16.161736 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 skip
1440 11:29:16.167377 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 skip
1441 11:29:16.184080 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 skip
1442 11:29:16.195319 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 skip
1443 11:29:16.206490 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 skip
1444 11:29:16.212140 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 pass
1445 11:29:16.223299 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 pass
1446 11:29:16.234507 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 pass
1447 11:29:16.240114 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 pass
1448 11:29:16.251276 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 pass
1449 11:29:16.262480 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 pass
1450 11:29:16.268108 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 pass
1451 11:29:16.279234 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 pass
1452 11:29:16.284936 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 fail
1453 11:29:16.296040 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 pass
1454 11:29:16.307244 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 pass
1455 11:29:16.318450 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 pass
1456 11:29:16.329631 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 fail
1457 11:29:16.340817 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck skip
1458 11:29:16.352024 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck skip
1459 11:29:16.363233 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck skip
1460 11:29:16.374496 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck skip
1461 11:29:16.385591 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck skip
1462 11:29:16.396757 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck skip
1463 11:29:16.408008 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck skip
1464 11:29:16.419178 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck skip
1465 11:29:16.436058 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck skip
1466 11:29:16.447162 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck skip
1467 11:29:16.458327 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 skip
1468 11:29:16.469512 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 skip
1469 11:29:16.480709 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 skip
1470 11:29:16.497513 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 skip
1471 11:29:16.508685 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 skip
1472 11:29:16.519878 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel pass
1473 11:29:16.531094 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 fail
1474 11:29:16.536714 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 fail
1475 11:29:16.547845 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 skip
1476 11:29:16.559044 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 pass
1477 11:29:16.564696 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 fail
1478 11:29:16.575844 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 pass
1479 11:29:16.581546 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 fail
1480 11:29:16.592614 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 pass
1481 11:29:16.598262 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 pass
1482 11:29:16.609385 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 pass
1483 11:29:16.615059 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 pass
1484 11:29:16.626187 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 pass
1485 11:29:16.631844 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 pass
1486 11:29:16.643010 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_eeprom_50 pass
1487 11:29:16.654192 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_eeprom_50_nvmem-layout skip
1488 11:29:16.665400 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 pass
1489 11:29:16.671057 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 pass
1490 11:29:16.682158 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger fail
1491 11:29:16.693376 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton fail
1492 11:29:16.699026 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 pass
1493 11:29:16.704609 dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 fail
1494 11:29:16.715783 dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 fail
1495 11:29:16.716337 dt_test_unprobed_devices_sh_ocp_interconnect_48000000 pass
1496 11:29:16.726955 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 pass
1497 11:29:16.732641 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 pass
1498 11:29:16.738191 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 pass
1499 11:29:16.749328 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 pass
1500 11:29:16.754974 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 pass
1501 11:29:16.766134 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 pass
1502 11:29:16.771772 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 pass
1503 11:29:16.782889 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 pass
1504 11:29:16.788580 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 fail
1505 11:29:16.794159 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 skip
1506 11:29:16.805284 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 pass
1507 11:29:16.810958 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 pass
1508 11:29:16.822138 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 pass
1509 11:29:16.827805 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 pass
1510 11:29:16.838919 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 pass
1511 11:29:16.844561 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 pass
1512 11:29:16.855622 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 pass
1513 11:29:16.861255 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 pass
1514 11:29:16.872454 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 pass
1515 11:29:16.878316 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 pass
1516 11:29:16.889284 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 pass
1517 11:29:16.894853 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 pass
1518 11:29:16.900452 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 pass
1519 11:29:16.911678 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 pass
1520 11:29:16.917150 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 pass
1521 11:29:16.928348 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 pass
1522 11:29:16.934052 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 pass
1523 11:29:16.945071 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 pass
1524 11:29:16.950783 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 pass
1525 11:29:16.962035 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 pass
1526 11:29:16.967576 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 pass
1527 11:29:16.978730 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_54 fail
1528 11:29:16.989940 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_54_nvmem-layout skip
1529 11:29:17.001128 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_55 fail
1530 11:29:17.012325 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_55_nvmem-layout skip
1531 11:29:17.017944 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_56 fail
1532 11:29:17.029159 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_56_nvmem-layout skip
1533 11:29:17.040309 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_57 fail
1534 11:29:17.051520 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_57_nvmem-layout skip
1535 11:29:17.057120 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 pass
1536 11:29:17.068197 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 pass
1537 11:29:17.073869 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 pass
1538 11:29:17.084990 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 pass
1539 11:29:17.090650 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 pass
1540 11:29:17.101856 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 pass
1541 11:29:17.107514 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 pass
1542 11:29:17.118680 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 pass
1543 11:29:17.124286 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 pass
1544 11:29:17.135514 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 pass
1545 11:29:17.141056 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 pass
1546 11:29:17.152253 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 pass
1547 11:29:17.157886 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 pass
1548 11:29:17.169029 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 pass
1549 11:29:17.174657 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 skip
1550 11:29:17.180229 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 pass
1551 11:29:17.191372 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 pass
1552 11:29:17.197023 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 pass
1553 11:29:17.208179 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 pass
1554 11:29:17.213783 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 pass
1555 11:29:17.224989 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 pass
1556 11:29:17.230587 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 pass
1557 11:29:17.241745 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 fail
1558 11:29:17.247392 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 pass
1559 11:29:17.252976 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 pass
1560 11:29:17.258575 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 pass
1561 11:29:17.269728 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 pass
1562 11:29:17.275316 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 pass
1563 11:29:17.286584 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 pass
1564 11:29:17.292134 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 fail
1565 11:29:17.303331 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 skip
1566 11:29:17.314734 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 fail
1567 11:29:17.325859 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 skip
1568 11:29:17.337022 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 fail
1569 11:29:17.344061 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 fail
1570 11:29:17.348187 dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 fail
1571 11:29:17.353867 dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 fail
1572 11:29:17.359445 dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 skip
1573 11:29:17.365006 dt_test_unprobed_devices_sh_ocp_target-module_40300000 pass
1574 11:29:17.370628 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 pass
1575 11:29:17.382055 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 skip
1576 11:29:17.387633 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 skip
1577 11:29:17.393228 dt_test_unprobed_devices_sh_ocp_target-module_47400000 pass
1578 11:29:17.398819 dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 pass
1579 11:29:17.404507 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 pass
1580 11:29:17.415689 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 pass
1581 11:29:17.421340 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 pass
1582 11:29:17.426936 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 pass
1583 11:29:17.432555 dt_test_unprobed_devices_sh_ocp_target-module_47810000 pass
1584 11:29:17.438152 dt_test_unprobed_devices_sh_ocp_target-module_49000000 pass
1585 11:29:17.443755 dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 pass
1586 11:29:17.449373 dt_test_unprobed_devices_sh_ocp_target-module_49800000 pass
1587 11:29:17.454961 dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 pass
1588 11:29:17.460570 dt_test_unprobed_devices_sh_ocp_target-module_49900000 pass
1589 11:29:17.466164 dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 pass
1590 11:29:17.471730 dt_test_unprobed_devices_sh_ocp_target-module_49a00000 pass
1591 11:29:17.477363 dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 pass
1592 11:29:17.482987 dt_test_unprobed_devices_sh_ocp_target-module_4c000000 pass
1593 11:29:17.488556 dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 fail
1594 11:29:17.494276 dt_test_unprobed_devices_sh_ocp_target-module_50000000 pass
1595 11:29:17.499868 dt_test_unprobed_devices_sh_ocp_target-module_53100000 pass
1596 11:29:17.505445 dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 fail
1597 11:29:17.511063 dt_test_unprobed_devices_sh_ocp_target-module_53500000 pass
1598 11:29:17.516875 dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 fail
1599 11:29:17.522421 dt_test_unprobed_devices_sh_ocp_target-module_56000000 pass
1600 11:29:17.528060 dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 skip
1601 11:29:17.528596 dt_test_unprobed_devices_sh_opp-table skip
1602 11:29:17.533676 dt_test_unprobed_devices_sh_soc skip
1603 11:29:17.539225 dt_test_unprobed_devices_sh_sound pass
1604 11:29:17.539751 dt_test_unprobed_devices_sh_target-module_4b000000 pass
1605 11:29:17.550390 dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 pass
1606 11:29:17.556032 dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 pass
1607 11:29:17.561729 dt_test_unprobed_devices_sh fail
1608 11:29:17.562300 + ../../utils/send-to-lava.sh ./output/result.txt
1609 11:29:17.569245 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-dt RESULT=pass>
1610 11:29:17.570185 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-dt RESULT=pass
1612 11:29:17.591039 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip>
1613 11:29:17.591860 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip
1615 11:29:17.692840 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass>
1616 11:29:17.693667 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass
1618 11:29:17.795922 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip>
1619 11:29:17.796754 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip
1621 11:29:17.888100 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip>
1622 11:29:17.888930 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip
1624 11:29:17.983691 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip>
1625 11:29:17.984534 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip
1627 11:29:18.083561 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass>
1628 11:29:18.084512 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass
1630 11:29:18.179793 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass>
1631 11:29:18.180634 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass
1633 11:29:18.279214 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass>
1634 11:29:18.280358 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass
1636 11:29:18.383106 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass>
1637 11:29:18.384225 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass
1639 11:29:18.478419 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass>
1640 11:29:18.479528 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass
1642 11:29:18.579896 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass>
1643 11:29:18.581181 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass
1645 11:29:18.685925 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass>
1646 11:29:18.687101 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass
1648 11:29:18.784345 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail>
1649 11:29:18.785507 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail
1651 11:29:18.883961 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass>
1652 11:29:18.885040 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass
1654 11:29:18.985801 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass>
1655 11:29:18.986895 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass
1657 11:29:19.089036 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail>
1658 11:29:19.090342 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail
1660 11:29:19.184072 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip>
1661 11:29:19.185370 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip
1663 11:29:19.286689 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip>
1664 11:29:19.287778 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip
1666 11:29:19.387235 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip>
1667 11:29:19.388426 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip
1669 11:29:19.482256 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip>
1670 11:29:19.483439 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip
1672 11:29:19.583594 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip>
1673 11:29:19.584770 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip
1675 11:29:19.684586 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip>
1676 11:29:19.685755 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip
1678 11:29:19.783900 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip>
1679 11:29:19.784771 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip
1681 11:29:19.885341 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip>
1682 11:29:19.886282 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip
1684 11:29:19.986491 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip>
1685 11:29:19.987369 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip
1687 11:29:20.082660 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip>
1688 11:29:20.083535 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip
1690 11:29:20.184097 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip>
1691 11:29:20.184968 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip
1693 11:29:20.285234 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip>
1694 11:29:20.286095 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip
1696 11:29:20.383520 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip>
1697 11:29:20.384330 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip
1699 11:29:20.478018 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip>
1700 11:29:20.478852 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip
1702 11:29:20.579523 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip>
1703 11:29:20.580346 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip
1705 11:29:20.680231 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip>
1706 11:29:20.681060 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip
1708 11:29:20.781649 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip>
1709 11:29:20.782598 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip
1711 11:29:20.877608 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip>
1712 11:29:20.878506 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip
1714 11:29:20.979254 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip>
1715 11:29:20.980085 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip
1717 11:29:21.079574 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip>
1718 11:29:21.080432 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip
1720 11:29:21.177227 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip>
1721 11:29:21.178140 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip
1723 11:29:21.279403 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip>
1724 11:29:21.280270 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip
1726 11:29:21.380664 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip>
1727 11:29:21.381495 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip
1729 11:29:21.482159 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip>
1730 11:29:21.483050 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip
1732 11:29:21.583529 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip>
1733 11:29:21.584378 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip
1735 11:29:21.685184 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip>
1736 11:29:21.686052 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip
1738 11:29:21.780888 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip>
1739 11:29:21.781732 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip
1741 11:29:21.882066 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip>
1742 11:29:21.883295 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip
1744 11:29:21.982741 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip>
1745 11:29:21.983882 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip
1747 11:29:22.084779 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip>
1748 11:29:22.085963 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip
1750 11:29:22.185104 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip>
1751 11:29:22.186246 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip
1753 11:29:22.286201 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip>
1754 11:29:22.287252 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip
1756 11:29:22.386229 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip>
1757 11:29:22.387400 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip
1759 11:29:22.487709 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip>
1760 11:29:22.488578 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip
1762 11:29:22.588988 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip>
1763 11:29:22.589868 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip
1765 11:29:22.690399 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip>
1766 11:29:22.691212 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip
1768 11:29:22.790902 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip>
1769 11:29:22.791703 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip
1771 11:29:22.893178 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip>
1772 11:29:22.893973 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip
1774 11:29:22.993471 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip>
1775 11:29:22.994320 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip
1777 11:29:23.095220 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip>
1778 11:29:23.095829 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip
1780 11:29:23.196503 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip>
1781 11:29:23.197062 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip
1783 11:29:23.297173 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip>
1784 11:29:23.297732 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip
1786 11:29:23.398126 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip>
1787 11:29:23.399016 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip
1789 11:29:23.495201 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip>
1790 11:29:23.496069 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip
1792 11:29:23.595778 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip>
1793 11:29:23.596549 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip
1795 11:29:23.696945 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip>
1796 11:29:23.697705 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip
1798 11:29:23.797900 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip>
1799 11:29:23.798740 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip
1801 11:29:23.900050 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip>
1802 11:29:23.900791 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip
1804 11:29:24.000584 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip>
1805 11:29:24.001289 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip
1807 11:29:24.102185 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip>
1808 11:29:24.103064 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip
1810 11:29:24.203625 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip>
1811 11:29:24.204494 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip
1813 11:29:24.304398 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip>
1814 11:29:24.305291 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip
1816 11:29:24.404967 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip>
1817 11:29:24.405847 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip
1819 11:29:24.509592 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip>
1820 11:29:24.510349 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip
1822 11:29:24.608424 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip>
1823 11:29:24.609292 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip
1825 11:29:24.709465 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip>
1826 11:29:24.710344 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip
1828 11:29:24.810870 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip>
1829 11:29:24.811705 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip
1831 11:29:24.912067 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip>
1832 11:29:24.912925 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip
1834 11:29:25.013667 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip>
1835 11:29:25.014573 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip
1837 11:29:25.114687 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip>
1838 11:29:25.115539 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip
1840 11:29:25.212506 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip>
1841 11:29:25.213345 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip
1843 11:29:25.313416 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip>
1844 11:29:25.314296 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip
1846 11:29:25.414355 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip>
1847 11:29:25.415213 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip
1849 11:29:25.515574 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip>
1850 11:29:25.516457 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip
1852 11:29:25.616957 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip>
1853 11:29:25.617776 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip
1855 11:29:25.713139 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip>
1856 11:29:25.714029 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip
1858 11:29:25.814079 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip>
1859 11:29:25.814939 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip
1861 11:29:25.915035 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip>
1862 11:29:25.915885 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip
1864 11:29:26.016896 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip>
1865 11:29:26.017767 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip
1867 11:29:26.118447 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip>
1868 11:29:26.119358 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip
1870 11:29:26.220232 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip>
1871 11:29:26.221121 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip
1873 11:29:26.322271 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip>
1874 11:29:26.323148 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip
1876 11:29:26.425916 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip>
1877 11:29:26.426794 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip
1879 11:29:26.528863 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip>
1880 11:29:26.529486 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip
1882 11:29:26.626281 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip>
1883 11:29:26.627220 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip
1885 11:29:26.729754 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip>
1886 11:29:26.730749 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip
1888 11:29:26.830486 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip>
1889 11:29:26.831419 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip
1891 11:29:26.931887 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip>
1892 11:29:26.932794 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip
1894 11:29:27.030932 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass>
1895 11:29:27.031909 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass
1897 11:29:27.132194 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass>
1898 11:29:27.133099 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass
1900 11:29:27.233400 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass>
1901 11:29:27.234277 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass
1903 11:29:27.334359 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass>
1904 11:29:27.335221 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass
1906 11:29:27.435474 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass>
1907 11:29:27.436355 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass
1909 11:29:27.536605 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass>
1910 11:29:27.537210 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass
1912 11:29:27.637704 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass>
1913 11:29:27.638654 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass
1915 11:29:27.737543 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass>
1916 11:29:27.738429 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass
1918 11:29:27.839063 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail>
1919 11:29:27.839918 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail
1921 11:29:27.941487 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass>
1922 11:29:27.942400 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass
1924 11:29:28.043603 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass>
1925 11:29:28.044666 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass
1927 11:29:28.144168 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass>
1928 11:29:28.145046 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass
1930 11:29:28.246393 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail>
1931 11:29:28.247249 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail
1933 11:29:28.348526 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip>
1934 11:29:28.349385 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip
1936 11:29:28.449084 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip>
1937 11:29:28.449709 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip
1939 11:29:28.548656 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip>
1940 11:29:28.549510 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip
1942 11:29:28.643450 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip>
1943 11:29:28.644348 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip
1945 11:29:28.737060 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip>
1946 11:29:28.737951 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip
1948 11:29:28.839093 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip>
1949 11:29:28.839949 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip
1951 11:29:28.940095 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip>
1952 11:29:28.940940 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip
1954 11:29:29.041774 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip>
1955 11:29:29.042697 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip
1957 11:29:29.143824 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip>
1958 11:29:29.144751 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip
1960 11:29:29.244872 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip>
1961 11:29:29.245770 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip
1963 11:29:29.345699 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip>
1964 11:29:29.346596 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip
1966 11:29:29.446234 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip>
1967 11:29:29.447101 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip
1969 11:29:29.548444 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip
1971 11:29:29.551606 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip>
1972 11:29:29.647641 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip
1974 11:29:29.650744 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip>
1975 11:29:29.741348 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip
1977 11:29:29.744518 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip>
1978 11:29:29.842875 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass>
1979 11:29:29.843668 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass
1981 11:29:29.944200 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail>
1982 11:29:29.945005 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail
1984 11:29:30.044059 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail>
1985 11:29:30.044661 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail
1987 11:29:30.146184 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip>
1988 11:29:30.146990 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip
1990 11:29:30.246568 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass>
1991 11:29:30.247390 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass
1993 11:29:30.348567 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail>
1994 11:29:30.349402 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail
1996 11:29:30.440689 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass>
1997 11:29:30.441553 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass
1999 11:29:30.537934 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail>
2000 11:29:30.538750 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail
2002 11:29:30.630654 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass>
2003 11:29:30.631454 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass
2005 11:29:30.732757 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass>
2006 11:29:30.733530 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass
2008 11:29:30.833879 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass>
2009 11:29:30.834728 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass
2011 11:29:30.935470 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass>
2012 11:29:30.936297 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass
2014 11:29:31.035678 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass>
2015 11:29:31.036601 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass
2017 11:29:31.132009 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass>
2018 11:29:31.132944 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass
2020 11:29:31.227410 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_eeprom_50 RESULT=pass>
2021 11:29:31.228319 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_eeprom_50 RESULT=pass
2023 11:29:31.328909 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_eeprom_50_nvmem-layout RESULT=skip>
2024 11:29:31.329798 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_eeprom_50_nvmem-layout RESULT=skip
2026 11:29:31.430589 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass>
2027 11:29:31.431500 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass
2029 11:29:31.537768 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass>
2030 11:29:31.540859 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass
2032 11:29:31.638517 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail>
2033 11:29:31.639406 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail
2035 11:29:31.739667 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail>
2036 11:29:31.740555 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail
2038 11:29:31.838612 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass>
2039 11:29:31.839495 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass
2041 11:29:31.937281 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail>
2042 11:29:31.939823 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail
2044 11:29:32.033139 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail>
2045 11:29:32.034156 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail
2047 11:29:32.133240 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass>
2048 11:29:32.134166 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass
2050 11:29:32.235413 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass>
2051 11:29:32.236262 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass
2053 11:29:32.336204 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass>
2054 11:29:32.337064 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass
2056 11:29:32.436874 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass>
2057 11:29:32.437691 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass
2059 11:29:32.537480 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass>
2060 11:29:32.538324 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass
2062 11:29:32.638922 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass>
2063 11:29:32.639826 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass
2065 11:29:32.730329 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass>
2066 11:29:32.731172 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass
2068 11:29:32.831728 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass>
2069 11:29:32.832607 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass
2071 11:29:32.925127 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass>
2072 11:29:32.926026 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass
2074 11:29:33.018141 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail>
2075 11:29:33.019023 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail
2077 11:29:33.112235 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip>
2078 11:29:33.113092 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip
2080 11:29:33.204978 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass>
2081 11:29:33.205880 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass
2083 11:29:33.299266 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass>
2084 11:29:33.300148 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass
2086 11:29:33.393019 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass>
2087 11:29:33.393912 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass
2089 11:29:33.487776 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass>
2090 11:29:33.488696 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass
2092 11:29:33.575310 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass>
2093 11:29:33.576237 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass
2095 11:29:33.676880 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass>
2096 11:29:33.677795 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass
2098 11:29:33.774391 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass>
2099 11:29:33.775469 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass
2101 11:29:33.876976 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass>
2102 11:29:33.877924 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass
2104 11:29:33.969550 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass>
2105 11:29:33.970514 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass
2107 11:29:34.072547 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass>
2108 11:29:34.073467 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass
2110 11:29:34.165363 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass>
2111 11:29:34.166304 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass
2113 11:29:34.259890 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass>
2114 11:29:34.260779 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass
2116 11:29:34.355229 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass>
2117 11:29:34.356127 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass
2119 11:29:34.455683 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass>
2120 11:29:34.456570 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass
2122 11:29:34.555973 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass>
2123 11:29:34.556842 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass
2125 11:29:34.657878 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass>
2126 11:29:34.658761 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass
2128 11:29:34.758629 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass>
2129 11:29:34.759490 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass
2131 11:29:34.860608 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass>
2132 11:29:34.861505 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass
2134 11:29:34.958692 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass>
2135 11:29:34.959519 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass
2137 11:29:35.061664 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass>
2138 11:29:35.062542 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass
2140 11:29:35.166390 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass>
2141 11:29:35.167320 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass
2143 11:29:35.266886 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_54 RESULT=fail>
2144 11:29:35.268131 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_54 RESULT=fail
2146 11:29:35.360878 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_54_nvmem-layout RESULT=skip>
2147 11:29:35.361533 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_54_nvmem-layout RESULT=skip
2149 11:29:35.461781 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_55 RESULT=fail>
2150 11:29:35.462605 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_55 RESULT=fail
2152 11:29:35.563980 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_55_nvmem-layout RESULT=skip>
2153 11:29:35.565138 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_55_nvmem-layout RESULT=skip
2155 11:29:35.663886 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_56 RESULT=fail>
2156 11:29:35.665245 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_56 RESULT=fail
2158 11:29:35.766519 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_56_nvmem-layout RESULT=skip>
2159 11:29:35.767204 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_56_nvmem-layout RESULT=skip
2161 11:29:35.866245 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_57 RESULT=fail>
2162 11:29:35.866762 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_57 RESULT=fail
2164 11:29:35.967926 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_57_nvmem-layout RESULT=skip>
2165 11:29:35.968604 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_57_nvmem-layout RESULT=skip
2167 11:29:36.066750 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass>
2168 11:29:36.067632 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass
2170 11:29:36.167417 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass>
2171 11:29:36.168298 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass
2173 11:29:36.268752 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass>
2174 11:29:36.269612 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass
2176 11:29:36.370140 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass>
2177 11:29:36.371009 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass
2179 11:29:36.471757 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass>
2180 11:29:36.472643 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass
2182 11:29:36.573337 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass>
2183 11:29:36.574227 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass
2185 11:29:36.676166 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass>
2186 11:29:36.677022 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass
2188 11:29:36.775467 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass>
2189 11:29:36.776357 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass
2191 11:29:36.872039 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass>
2192 11:29:36.873032 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass
2194 11:29:36.967266 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass>
2195 11:29:36.968137 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass
2197 11:29:37.055917 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass>
2198 11:29:37.057981 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass
2200 11:29:37.150344 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass>
2201 11:29:37.151170 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass
2203 11:29:37.242709 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass>
2204 11:29:37.243552 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass
2206 11:29:37.337449 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass>
2207 11:29:37.338331 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass
2209 11:29:37.435194 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip>
2210 11:29:37.436058 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip
2212 11:29:37.524557 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass>
2213 11:29:37.525371 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass
2215 11:29:37.614323 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass>
2216 11:29:37.615209 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass
2218 11:29:37.708797 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass>
2219 11:29:37.709669 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass
2221 11:29:37.805243 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass>
2222 11:29:37.806320 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass
2224 11:29:37.901420 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass>
2225 11:29:37.902319 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass
2227 11:29:37.997385 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass>
2228 11:29:37.998460 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass
2230 11:29:38.092301 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass>
2231 11:29:38.093176 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass
2233 11:29:38.188439 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail>
2234 11:29:38.189637 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail
2236 11:29:38.279274 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass>
2237 11:29:38.280143 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass
2239 11:29:38.374952 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass>
2240 11:29:38.375827 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass
2242 11:29:38.470241 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass>
2243 11:29:38.471115 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass
2245 11:29:38.566405 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass>
2246 11:29:38.567434 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass
2248 11:29:38.667274 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass>
2249 11:29:38.668239 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass
2251 11:29:38.770956 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass>
2252 11:29:38.771878 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass
2254 11:29:38.867999 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail>
2255 11:29:38.868927 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail
2257 11:29:38.966083 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip>
2258 11:29:38.967039 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip
2260 11:29:39.064442 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail>
2261 11:29:39.065430 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail
2263 11:29:39.161736 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip>
2264 11:29:39.162919 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip
2266 11:29:39.263266 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail>
2267 11:29:39.264223 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail
2269 11:29:39.367072 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail>
2270 11:29:39.368052 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail
2272 11:29:39.474783 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail>
2273 11:29:39.475717 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail
2275 11:29:39.573591 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail>
2276 11:29:39.574494 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail
2278 11:29:39.666917 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip>
2279 11:29:39.667752 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip
2281 11:29:39.761719 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass>
2282 11:29:39.762587 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass
2284 11:29:39.857660 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass>
2285 11:29:39.858548 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass
2287 11:29:39.954135 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip>
2288 11:29:39.955002 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip
2290 11:29:40.047487 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip
2292 11:29:40.050472 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip>
2293 11:29:40.145145 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass>
2294 11:29:40.146033 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass
2296 11:29:40.240813 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass>
2297 11:29:40.241624 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass
2299 11:29:40.336269 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass>
2300 11:29:40.337102 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass
2302 11:29:40.432949 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass>
2303 11:29:40.433898 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass
2305 11:29:40.527250 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass>
2306 11:29:40.528084 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass
2308 11:29:40.623259 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass>
2309 11:29:40.624153 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass
2311 11:29:40.719424 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass>
2312 11:29:40.720303 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass
2314 11:29:40.816594 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass>
2315 11:29:40.817201 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass
2317 11:29:40.912196 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass>
2318 11:29:40.912824 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass
2320 11:29:41.008866 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass>
2321 11:29:41.009471 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass
2323 11:29:41.105420 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass>
2324 11:29:41.106066 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass
2326 11:29:41.201916 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass>
2327 11:29:41.202555 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass
2329 11:29:41.301038 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass>
2330 11:29:41.301706 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass
2332 11:29:41.396465 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass>
2333 11:29:41.397256 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass
2335 11:29:41.674411 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass>
2336 11:29:41.675201 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass
2338 11:29:41.779561 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass>
2339 11:29:41.780218 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass
2341 11:29:41.876218 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail>
2342 11:29:41.876863 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail
2344 11:29:41.971590 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass>
2345 11:29:41.972514 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass
2347 11:29:42.065940 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass>
2348 11:29:42.066834 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass
2350 11:29:42.164336 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail>
2351 11:29:42.164940 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail
2353 11:29:42.259909 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass>
2354 11:29:42.260524 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass
2356 11:29:42.357917 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail>
2357 11:29:42.358849 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail
2359 11:29:42.452875 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass>
2360 11:29:42.453497 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass
2362 11:29:42.548657 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip>
2363 11:29:42.549476 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip
2365 11:29:42.642791 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip>
2366 11:29:42.643603 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip
2368 11:29:42.736617 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip>
2369 11:29:42.737424 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip
2371 11:29:42.833037 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass>
2372 11:29:42.833871 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass
2374 11:29:42.929901 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass>
2375 11:29:42.930787 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass
2377 11:29:43.027161 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass>
2378 11:29:43.028079 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass
2380 11:29:43.129154 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass>
2381 11:29:43.130139 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass
2383 11:29:43.222731 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail>
2384 11:29:43.223372 + set +x
2385 11:29:43.224110 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail
2387 11:29:43.231767 <LAVA_SIGNAL_ENDRUN 1_kselftest-dt 958774_1.6.2.4.5>
2388 11:29:43.232306 <LAVA_TEST_RUNNER EXIT>
2389 11:29:43.233023 Received signal: <ENDRUN> 1_kselftest-dt 958774_1.6.2.4.5
2390 11:29:43.233517 Ending use of test pattern.
2391 11:29:43.234032 Ending test lava.1_kselftest-dt (958774_1.6.2.4.5), duration 86.74
2393 11:29:43.235724 ok: lava_test_shell seems to have completed
2394 11:29:43.249776 dt_test_unprobed_devices_sh: fail
dt_test_unprobed_devices_sh_: skip
dt_test_unprobed_devices_sh_clk_mcasp0: pass
dt_test_unprobed_devices_sh_clk_mcasp0_fixed: skip
dt_test_unprobed_devices_sh_cpus_cpu_0: skip
dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate: skip
dt_test_unprobed_devices_sh_fixedregulator0: pass
dt_test_unprobed_devices_sh_leds: pass
dt_test_unprobed_devices_sh_ocp: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0: fail
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_eeprom_50: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_eeprom_50_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_54: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_54_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_55: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_55_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_56: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_56_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_57: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_57_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000: skip
dt_test_unprobed_devices_sh_ocp_target-module_47400000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800: pass
dt_test_unprobed_devices_sh_ocp_target-module_47810000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_50000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_53500000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_56000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0: skip
dt_test_unprobed_devices_sh_opp-table: skip
dt_test_unprobed_devices_sh_soc: skip
dt_test_unprobed_devices_sh_sound: pass
dt_test_unprobed_devices_sh_target-module_4b000000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0: pass
shardfile-dt: pass
2395 11:29:43.251916 end: 3.1 lava-test-shell (duration 00:01:28) [common]
2396 11:29:43.252553 end: 3 lava-test-retry (duration 00:01:28) [common]
2397 11:29:43.253179 start: 4 finalize (timeout 00:05:23) [common]
2398 11:29:43.253798 start: 4.1 power-off (timeout 00:00:30) [common]
2399 11:29:43.254889 Calling: 'curl' 'http://conserv3.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=beaglebone-black-03'
2400 11:29:43.291155 >> OK - accepted request
2401 11:29:43.292906 Returned 0 in 0 seconds
2402 11:29:43.394217 end: 4.1 power-off (duration 00:00:00) [common]
2404 11:29:43.396013 start: 4.2 read-feedback (timeout 00:05:23) [common]
2405 11:29:43.397143 Listened to connection for namespace 'common' for up to 1s
2406 11:29:43.398017 Listened to connection for namespace 'common' for up to 1s
2407 11:29:44.398102 Finalising connection for namespace 'common'
2408 11:29:44.398849 Disconnecting from shell: Finalise
2409 11:29:44.399337 / #
2410 11:29:44.500307 end: 4.2 read-feedback (duration 00:00:01) [common]
2411 11:29:44.500848 end: 4 finalize (duration 00:00:01) [common]
2412 11:29:44.501202 Cleaning after the job
2413 11:29:44.501581 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/958774/tftp-deploy-smwqpcp0/ramdisk
2414 11:29:44.503699 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/958774/tftp-deploy-smwqpcp0/kernel
2415 11:29:44.505058 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/958774/tftp-deploy-smwqpcp0/dtb
2416 11:29:44.506047 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/958774/tftp-deploy-smwqpcp0/nfsrootfs
2417 11:29:44.523448 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/958774/tftp-deploy-smwqpcp0/modules
2418 11:29:44.527710 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/958774
2419 11:29:47.552968 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/958774
2420 11:29:47.553584 Job finished correctly