Boot log: beaglebone-black
- Warnings: 2
- Kernel Warnings: 15
- Errors: 0
- Boot result: PASS
- Kernel Errors: 10
1 11:20:37.078006 lava-dispatcher, installed at version: 2023.08
2 11:20:37.078327 start: 0 validate
3 11:20:37.078508 Start time: 2024-11-08 11:20:37.078496+00:00 (UTC)
4 11:20:37.078735 Validating that http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/initrd.cpio.gz exists
5 11:20:37.844345 Validating that http://storage.kernelci.org/next/master/next-20241108/arm/multi_v7_defconfig/clang-17/kernel/zImage exists
6 11:20:37.958753 Validating that http://storage.kernelci.org/next/master/next-20241108/arm/multi_v7_defconfig/clang-17/dtbs/ti/omap/am335x-boneblack.dtb exists
7 11:20:38.072915 Validating that http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/full.rootfs.tar.xz exists
8 11:20:38.186981 Validating that http://storage.kernelci.org/next/master/next-20241108/arm/multi_v7_defconfig/clang-17/modules.tar.xz exists
9 11:20:38.305718 validate duration: 1.23
11 11:20:38.306498 start: 1 tftp-deploy (timeout 00:10:00) [common]
12 11:20:38.306831 start: 1.1 download-retry (timeout 00:10:00) [common]
13 11:20:38.307141 start: 1.1.1 http-download (timeout 00:10:00) [common]
14 11:20:38.307602 Not decompressing ramdisk as can be used compressed.
15 11:20:38.307901 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/initrd.cpio.gz
16 11:20:38.308143 saving as /var/lib/lava/dispatcher/tmp/1219295/tftp-deploy-xjexk29k/ramdisk/initrd.cpio.gz
17 11:20:38.308385 total size: 4775763 (4 MB)
18 11:20:38.538341 progress 0 % (0 MB)
19 11:20:38.876000 progress 5 % (0 MB)
20 11:20:39.097980 progress 10 % (0 MB)
21 11:20:39.119279 progress 15 % (0 MB)
22 11:20:39.212819 progress 20 % (0 MB)
23 11:20:39.227443 progress 25 % (1 MB)
24 11:20:39.331458 progress 30 % (1 MB)
25 11:20:39.438625 progress 35 % (1 MB)
26 11:20:39.541736 progress 40 % (1 MB)
27 11:20:39.562137 progress 45 % (2 MB)
28 11:20:39.664819 progress 50 % (2 MB)
29 11:20:39.770437 progress 55 % (2 MB)
30 11:20:39.790091 progress 60 % (2 MB)
31 11:20:39.892511 progress 65 % (2 MB)
32 11:20:39.997539 progress 70 % (3 MB)
33 11:20:40.016981 progress 75 % (3 MB)
34 11:20:40.119955 progress 80 % (3 MB)
35 11:20:40.220248 progress 85 % (3 MB)
36 11:20:40.244614 progress 90 % (4 MB)
37 11:20:40.343183 progress 95 % (4 MB)
38 11:20:40.443092 progress 100 % (4 MB)
39 11:20:40.443869 4 MB downloaded in 2.14 s (2.13 MB/s)
40 11:20:40.444348 end: 1.1.1 http-download (duration 00:00:02) [common]
42 11:20:40.445251 end: 1.1 download-retry (duration 00:00:02) [common]
43 11:20:40.445548 start: 1.2 download-retry (timeout 00:09:58) [common]
44 11:20:40.445839 start: 1.2.1 http-download (timeout 00:09:58) [common]
45 11:20:40.446249 downloading http://storage.kernelci.org/next/master/next-20241108/arm/multi_v7_defconfig/clang-17/kernel/zImage
46 11:20:40.446477 saving as /var/lib/lava/dispatcher/tmp/1219295/tftp-deploy-xjexk29k/kernel/zImage
47 11:20:40.446696 total size: 12128768 (11 MB)
48 11:20:40.446917 No compression specified
49 11:20:40.562716 progress 0 % (0 MB)
50 11:20:40.899505 progress 5 % (0 MB)
51 11:20:41.142949 progress 10 % (1 MB)
52 11:20:41.370320 progress 15 % (1 MB)
53 11:20:41.600568 progress 20 % (2 MB)
54 11:20:41.825335 progress 25 % (2 MB)
55 11:20:42.052368 progress 30 % (3 MB)
56 11:20:42.274936 progress 35 % (4 MB)
57 11:20:42.546923 progress 40 % (4 MB)
58 11:20:42.725254 progress 45 % (5 MB)
59 11:20:42.948987 progress 50 % (5 MB)
60 11:20:43.168208 progress 55 % (6 MB)
61 11:20:43.390781 progress 60 % (6 MB)
62 11:20:43.608983 progress 65 % (7 MB)
63 11:20:43.834543 progress 70 % (8 MB)
64 11:20:44.052264 progress 75 % (8 MB)
65 11:20:44.272443 progress 80 % (9 MB)
66 11:20:44.489977 progress 85 % (9 MB)
67 11:20:44.712167 progress 90 % (10 MB)
68 11:20:44.931101 progress 95 % (11 MB)
69 11:20:45.080593 progress 100 % (11 MB)
70 11:20:45.081112 11 MB downloaded in 4.63 s (2.50 MB/s)
71 11:20:45.081567 end: 1.2.1 http-download (duration 00:00:05) [common]
73 11:20:45.082385 end: 1.2 download-retry (duration 00:00:05) [common]
74 11:20:45.082684 start: 1.3 download-retry (timeout 00:09:53) [common]
75 11:20:45.082973 start: 1.3.1 http-download (timeout 00:09:53) [common]
76 11:20:45.083382 downloading http://storage.kernelci.org/next/master/next-20241108/arm/multi_v7_defconfig/clang-17/dtbs/ti/omap/am335x-boneblack.dtb
77 11:20:45.083612 saving as /var/lib/lava/dispatcher/tmp/1219295/tftp-deploy-xjexk29k/dtb/am335x-boneblack.dtb
78 11:20:45.083831 total size: 70544 (0 MB)
79 11:20:45.084050 No compression specified
80 11:20:45.203510 progress 46 % (0 MB)
81 11:20:45.206323 progress 92 % (0 MB)
82 11:20:45.207318 progress 100 % (0 MB)
83 11:20:45.207719 0 MB downloaded in 0.12 s (0.54 MB/s)
84 11:20:45.208147 end: 1.3.1 http-download (duration 00:00:00) [common]
86 11:20:45.208986 end: 1.3 download-retry (duration 00:00:00) [common]
87 11:20:45.209269 start: 1.4 download-retry (timeout 00:09:53) [common]
88 11:20:45.209556 start: 1.4.1 http-download (timeout 00:09:53) [common]
89 11:20:45.209949 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/full.rootfs.tar.xz
90 11:20:45.210175 saving as /var/lib/lava/dispatcher/tmp/1219295/tftp-deploy-xjexk29k/nfsrootfs/full.rootfs.tar
91 11:20:45.210392 total size: 117747780 (112 MB)
92 11:20:45.210619 Using unxz to decompress xz
93 11:20:45.327119 progress 0 % (0 MB)
94 11:20:47.820590 progress 5 % (5 MB)
95 11:20:49.941666 progress 10 % (11 MB)
96 11:20:52.036978 progress 15 % (16 MB)
97 11:20:54.052633 progress 20 % (22 MB)
98 11:20:55.935208 progress 25 % (28 MB)
99 11:20:57.500907 progress 30 % (33 MB)
100 11:20:58.754413 progress 35 % (39 MB)
101 11:21:00.094782 progress 40 % (44 MB)
102 11:21:01.357469 progress 45 % (50 MB)
103 11:21:02.780175 progress 50 % (56 MB)
104 11:21:04.227762 progress 55 % (61 MB)
105 11:21:05.640898 progress 60 % (67 MB)
106 11:21:06.988685 progress 65 % (73 MB)
107 11:21:08.343707 progress 70 % (78 MB)
108 11:21:09.701484 progress 75 % (84 MB)
109 11:21:11.018853 progress 80 % (89 MB)
110 11:21:12.251141 progress 85 % (95 MB)
111 11:21:13.375844 progress 90 % (101 MB)
112 11:21:14.374853 progress 95 % (106 MB)
113 11:21:15.268159 progress 100 % (112 MB)
114 11:21:15.271623 112 MB downloaded in 30.06 s (3.74 MB/s)
115 11:21:15.271947 end: 1.4.1 http-download (duration 00:00:30) [common]
117 11:21:15.272527 end: 1.4 download-retry (duration 00:00:30) [common]
118 11:21:15.272741 start: 1.5 download-retry (timeout 00:09:23) [common]
119 11:21:15.272943 start: 1.5.1 http-download (timeout 00:09:23) [common]
120 11:21:15.273241 downloading http://storage.kernelci.org/next/master/next-20241108/arm/multi_v7_defconfig/clang-17/modules.tar.xz
121 11:21:15.273401 saving as /var/lib/lava/dispatcher/tmp/1219295/tftp-deploy-xjexk29k/modules/modules.tar
122 11:21:15.273551 total size: 6933168 (6 MB)
123 11:21:15.273704 Using unxz to decompress xz
124 11:21:15.389183 progress 0 % (0 MB)
125 11:21:15.627346 progress 5 % (0 MB)
126 11:21:15.743020 progress 10 % (0 MB)
127 11:21:15.951543 progress 15 % (1 MB)
128 11:21:15.981711 progress 20 % (1 MB)
129 11:21:16.007644 progress 25 % (1 MB)
130 11:21:16.088792 progress 30 % (2 MB)
131 11:21:16.199779 progress 35 % (2 MB)
132 11:21:16.303527 progress 40 % (2 MB)
133 11:21:16.412149 progress 45 % (3 MB)
134 11:21:16.509504 progress 50 % (3 MB)
135 11:21:16.616154 progress 55 % (3 MB)
136 11:21:16.653327 progress 60 % (3 MB)
137 11:21:16.759921 progress 65 % (4 MB)
138 11:21:16.866894 progress 70 % (4 MB)
139 11:21:16.969453 progress 75 % (4 MB)
140 11:21:17.069320 progress 80 % (5 MB)
141 11:21:17.106106 progress 85 % (5 MB)
142 11:21:17.211333 progress 90 % (5 MB)
143 11:21:17.317016 progress 95 % (6 MB)
144 11:21:17.415308 progress 100 % (6 MB)
145 11:21:17.417983 6 MB downloaded in 2.14 s (3.08 MB/s)
146 11:21:17.418388 end: 1.5.1 http-download (duration 00:00:02) [common]
148 11:21:17.419117 end: 1.5 download-retry (duration 00:00:02) [common]
149 11:21:17.419371 start: 1.6 prepare-tftp-overlay (timeout 00:09:21) [common]
150 11:21:17.419645 start: 1.6.1 extract-nfsrootfs (timeout 00:09:21) [common]
151 11:21:23.006348 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/1219295/extract-nfsrootfs-k_16rdse
152 11:21:23.006660 end: 1.6.1 extract-nfsrootfs (duration 00:00:06) [common]
153 11:21:23.006811 start: 1.6.2 lava-overlay (timeout 00:09:15) [common]
154 11:21:23.007109 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/1219295/lava-overlay-1swstikt
155 11:21:23.007300 makedir: /var/lib/lava/dispatcher/tmp/1219295/lava-overlay-1swstikt/lava-1219295/bin
156 11:21:23.007446 makedir: /var/lib/lava/dispatcher/tmp/1219295/lava-overlay-1swstikt/lava-1219295/tests
157 11:21:23.007599 makedir: /var/lib/lava/dispatcher/tmp/1219295/lava-overlay-1swstikt/lava-1219295/results
158 11:21:23.007762 Creating /var/lib/lava/dispatcher/tmp/1219295/lava-overlay-1swstikt/lava-1219295/bin/lava-add-keys
159 11:21:23.007987 Creating /var/lib/lava/dispatcher/tmp/1219295/lava-overlay-1swstikt/lava-1219295/bin/lava-add-sources
160 11:21:23.008168 Creating /var/lib/lava/dispatcher/tmp/1219295/lava-overlay-1swstikt/lava-1219295/bin/lava-background-process-start
161 11:21:23.008354 Creating /var/lib/lava/dispatcher/tmp/1219295/lava-overlay-1swstikt/lava-1219295/bin/lava-background-process-stop
162 11:21:23.008558 Creating /var/lib/lava/dispatcher/tmp/1219295/lava-overlay-1swstikt/lava-1219295/bin/lava-common-functions
163 11:21:23.008786 Creating /var/lib/lava/dispatcher/tmp/1219295/lava-overlay-1swstikt/lava-1219295/bin/lava-echo-ipv4
164 11:21:23.008963 Creating /var/lib/lava/dispatcher/tmp/1219295/lava-overlay-1swstikt/lava-1219295/bin/lava-install-packages
165 11:21:23.009139 Creating /var/lib/lava/dispatcher/tmp/1219295/lava-overlay-1swstikt/lava-1219295/bin/lava-installed-packages
166 11:21:23.009313 Creating /var/lib/lava/dispatcher/tmp/1219295/lava-overlay-1swstikt/lava-1219295/bin/lava-os-build
167 11:21:23.009487 Creating /var/lib/lava/dispatcher/tmp/1219295/lava-overlay-1swstikt/lava-1219295/bin/lava-probe-channel
168 11:21:23.009659 Creating /var/lib/lava/dispatcher/tmp/1219295/lava-overlay-1swstikt/lava-1219295/bin/lava-probe-ip
169 11:21:23.009835 Creating /var/lib/lava/dispatcher/tmp/1219295/lava-overlay-1swstikt/lava-1219295/bin/lava-target-ip
170 11:21:23.010007 Creating /var/lib/lava/dispatcher/tmp/1219295/lava-overlay-1swstikt/lava-1219295/bin/lava-target-mac
171 11:21:23.010179 Creating /var/lib/lava/dispatcher/tmp/1219295/lava-overlay-1swstikt/lava-1219295/bin/lava-target-storage
172 11:21:23.010355 Creating /var/lib/lava/dispatcher/tmp/1219295/lava-overlay-1swstikt/lava-1219295/bin/lava-test-case
173 11:21:23.010528 Creating /var/lib/lava/dispatcher/tmp/1219295/lava-overlay-1swstikt/lava-1219295/bin/lava-test-event
174 11:21:23.010699 Creating /var/lib/lava/dispatcher/tmp/1219295/lava-overlay-1swstikt/lava-1219295/bin/lava-test-feedback
175 11:21:23.010869 Creating /var/lib/lava/dispatcher/tmp/1219295/lava-overlay-1swstikt/lava-1219295/bin/lava-test-raise
176 11:21:23.011041 Creating /var/lib/lava/dispatcher/tmp/1219295/lava-overlay-1swstikt/lava-1219295/bin/lava-test-reference
177 11:21:23.011213 Creating /var/lib/lava/dispatcher/tmp/1219295/lava-overlay-1swstikt/lava-1219295/bin/lava-test-runner
178 11:21:23.011387 Creating /var/lib/lava/dispatcher/tmp/1219295/lava-overlay-1swstikt/lava-1219295/bin/lava-test-set
179 11:21:23.011558 Creating /var/lib/lava/dispatcher/tmp/1219295/lava-overlay-1swstikt/lava-1219295/bin/lava-test-shell
180 11:21:23.011733 Updating /var/lib/lava/dispatcher/tmp/1219295/lava-overlay-1swstikt/lava-1219295/bin/lava-add-keys (debian)
181 11:21:23.011958 Updating /var/lib/lava/dispatcher/tmp/1219295/lava-overlay-1swstikt/lava-1219295/bin/lava-add-sources (debian)
182 11:21:23.012154 Updating /var/lib/lava/dispatcher/tmp/1219295/lava-overlay-1swstikt/lava-1219295/bin/lava-install-packages (debian)
183 11:21:23.012349 Updating /var/lib/lava/dispatcher/tmp/1219295/lava-overlay-1swstikt/lava-1219295/bin/lava-installed-packages (debian)
184 11:21:23.012543 Updating /var/lib/lava/dispatcher/tmp/1219295/lava-overlay-1swstikt/lava-1219295/bin/lava-os-build (debian)
185 11:21:23.012720 Creating /var/lib/lava/dispatcher/tmp/1219295/lava-overlay-1swstikt/lava-1219295/environment
186 11:21:23.012855 LAVA metadata
187 11:21:23.012957 - LAVA_JOB_ID=1219295
188 11:21:23.013056 - LAVA_DISPATCHER_IP=192.168.11.5
189 11:21:23.013200 start: 1.6.2.1 ssh-authorize (timeout 00:09:15) [common]
190 11:21:23.013532 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
191 11:21:23.013658 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:15) [common]
192 11:21:23.013753 skipped lava-vland-overlay
193 11:21:23.013868 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
194 11:21:23.013988 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:15) [common]
195 11:21:23.014086 skipped lava-multinode-overlay
196 11:21:23.014201 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
197 11:21:23.014319 start: 1.6.2.4 test-definition (timeout 00:09:15) [common]
198 11:21:23.014422 Loading test definitions
199 11:21:23.014548 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:15) [common]
200 11:21:23.014649 Using /lava-1219295 at stage 0
201 11:21:23.015062 uuid=1219295_1.6.2.4.1 testdef=None
202 11:21:23.015189 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
203 11:21:23.015311 start: 1.6.2.4.2 test-overlay (timeout 00:09:15) [common]
204 11:21:23.015930 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
206 11:21:23.016270 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:15) [common]
207 11:21:23.017078 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
209 11:21:23.017428 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:15) [common]
210 11:21:23.018190 runner path: /var/lib/lava/dispatcher/tmp/1219295/lava-overlay-1swstikt/lava-1219295/0/tests/0_timesync-off test_uuid 1219295_1.6.2.4.1
211 11:21:23.018402 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
213 11:21:23.018767 start: 1.6.2.4.5 git-repo-action (timeout 00:09:15) [common]
214 11:21:23.018871 Using /lava-1219295 at stage 0
215 11:21:23.019012 Fetching tests from https://github.com/kernelci/test-definitions.git
216 11:21:23.019118 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/1219295/lava-overlay-1swstikt/lava-1219295/0/tests/1_kselftest-dt'
217 11:21:28.087087 Running '/usr/bin/git checkout kernelci.org
218 11:21:28.199144 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/1219295/lava-overlay-1swstikt/lava-1219295/0/tests/1_kselftest-dt/automated/linux/kselftest/kselftest.yaml
219 11:21:28.199989 uuid=1219295_1.6.2.4.5 testdef=None
220 11:21:28.200198 end: 1.6.2.4.5 git-repo-action (duration 00:00:05) [common]
222 11:21:28.200665 start: 1.6.2.4.6 test-overlay (timeout 00:09:10) [common]
223 11:21:28.202237 end: 1.6.2.4.6 test-overlay (duration 00:00:00) [common]
225 11:21:28.202728 start: 1.6.2.4.7 test-install-overlay (timeout 00:09:10) [common]
226 11:21:28.204885 end: 1.6.2.4.7 test-install-overlay (duration 00:00:00) [common]
228 11:21:28.205394 start: 1.6.2.4.8 test-runscript-overlay (timeout 00:09:10) [common]
229 11:21:28.207476 runner path: /var/lib/lava/dispatcher/tmp/1219295/lava-overlay-1swstikt/lava-1219295/0/tests/1_kselftest-dt test_uuid 1219295_1.6.2.4.5
230 11:21:28.207642 BOARD='beaglebone-black'
231 11:21:28.207776 BRANCH='next'
232 11:21:28.207905 SKIPFILE='/dev/null'
233 11:21:28.208032 SKIP_INSTALL='True'
234 11:21:28.208157 TESTPROG_URL='http://storage.kernelci.org/next/master/next-20241108/arm/multi_v7_defconfig/clang-17/kselftest.tar.xz'
235 11:21:28.208286 TST_CASENAME=''
236 11:21:28.208412 TST_CMDFILES='dt'
237 11:21:28.208688 end: 1.6.2.4.8 test-runscript-overlay (duration 00:00:00) [common]
239 11:21:28.209039 Creating lava-test-runner.conf files
240 11:21:28.209128 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/1219295/lava-overlay-1swstikt/lava-1219295/0 for stage 0
241 11:21:28.209252 - 0_timesync-off
242 11:21:28.209345 - 1_kselftest-dt
243 11:21:28.209480 end: 1.6.2.4 test-definition (duration 00:00:05) [common]
244 11:21:28.209596 start: 1.6.2.5 compress-overlay (timeout 00:09:10) [common]
245 11:21:36.676515 end: 1.6.2.5 compress-overlay (duration 00:00:08) [common]
246 11:21:36.676750 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:09:02) [common]
247 11:21:36.676905 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
248 11:21:36.677053 end: 1.6.2 lava-overlay (duration 00:00:14) [common]
249 11:21:36.677200 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:02) [common]
250 11:21:36.803295 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
251 11:21:36.803604 start: 1.6.4 extract-modules (timeout 00:09:02) [common]
252 11:21:36.803780 extracting modules file /var/lib/lava/dispatcher/tmp/1219295/tftp-deploy-xjexk29k/modules/modules.tar to /var/lib/lava/dispatcher/tmp/1219295/extract-nfsrootfs-k_16rdse
253 11:21:37.110810 extracting modules file /var/lib/lava/dispatcher/tmp/1219295/tftp-deploy-xjexk29k/modules/modules.tar to /var/lib/lava/dispatcher/tmp/1219295/extract-overlay-ramdisk-9zg5v0y8/ramdisk
254 11:21:37.423781 end: 1.6.4 extract-modules (duration 00:00:01) [common]
255 11:21:37.424001 start: 1.6.5 apply-overlay-tftp (timeout 00:09:01) [common]
256 11:21:37.424135 [common] Applying overlay to NFS
257 11:21:37.424243 [common] Applying overlay /var/lib/lava/dispatcher/tmp/1219295/compress-overlay-azv4rj1x/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/1219295/extract-nfsrootfs-k_16rdse
258 11:21:38.613612 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
259 11:21:38.613828 start: 1.6.6 prepare-kernel (timeout 00:09:00) [common]
260 11:21:38.613956 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:09:00) [common]
261 11:21:38.614087 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
262 11:21:38.614206 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
263 11:21:38.614328 start: 1.6.7 configure-preseed-file (timeout 00:09:00) [common]
264 11:21:38.614444 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
265 11:21:38.614562 start: 1.6.8 compress-ramdisk (timeout 00:09:00) [common]
266 11:21:38.614664 Building ramdisk /var/lib/lava/dispatcher/tmp/1219295/extract-overlay-ramdisk-9zg5v0y8/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/1219295/extract-overlay-ramdisk-9zg5v0y8/ramdisk
267 11:21:38.938511 >> 79383 blocks
268 11:21:41.077509 Adding RAMdisk u-boot header.
269 11:21:41.077794 mkimage -A arm -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/1219295/extract-overlay-ramdisk-9zg5v0y8/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/1219295/extract-overlay-ramdisk-9zg5v0y8/ramdisk.cpio.gz.uboot
270 11:21:41.235435 output: Image Name:
271 11:21:41.235697 output: Created: Fri Nov 8 11:21:41 2024
272 11:21:41.235842 output: Image Type: ARM Linux RAMDisk Image (uncompressed)
273 11:21:41.235980 output: Data Size: 15380840 Bytes = 15020.35 KiB = 14.67 MiB
274 11:21:41.236114 output: Load Address: 00000000
275 11:21:41.236245 output: Entry Point: 00000000
276 11:21:41.236376 output:
277 11:21:41.236601 rename /var/lib/lava/dispatcher/tmp/1219295/extract-overlay-ramdisk-9zg5v0y8/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/1219295/tftp-deploy-xjexk29k/ramdisk/ramdisk.cpio.gz.uboot
278 11:21:41.236874 end: 1.6.8 compress-ramdisk (duration 00:00:03) [common]
279 11:21:41.237102 end: 1.6 prepare-tftp-overlay (duration 00:00:24) [common]
280 11:21:41.237323 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:57) [common]
281 11:21:41.237496 No LXC device requested
282 11:21:41.237705 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
283 11:21:41.237919 start: 1.8 deploy-device-env (timeout 00:08:57) [common]
284 11:21:41.238126 end: 1.8 deploy-device-env (duration 00:00:00) [common]
285 11:21:41.238293 Checking files for TFTP limit of 4294967296 bytes.
286 11:21:41.239316 end: 1 tftp-deploy (duration 00:01:03) [common]
287 11:21:41.239542 start: 2 uboot-action (timeout 00:05:00) [common]
288 11:21:41.239762 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
289 11:21:41.239970 end: 2.1 uboot-from-media (duration 00:00:00) [common]
290 11:21:41.240181 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
291 11:21:41.240492 substitutions:
292 11:21:41.240663 - {BOOTX}: bootz 0x82000000 0x83000000 0x88000000
293 11:21:41.240844 - {DTB_ADDR}: 0x88000000
294 11:21:41.241007 - {DTB}: 1219295/tftp-deploy-xjexk29k/dtb/am335x-boneblack.dtb
295 11:21:41.241171 - {INITRD}: 1219295/tftp-deploy-xjexk29k/ramdisk/ramdisk.cpio.gz.uboot
296 11:21:41.241333 - {KERNEL_ADDR}: 0x82000000
297 11:21:41.241494 - {KERNEL}: 1219295/tftp-deploy-xjexk29k/kernel/zImage
298 11:21:41.241654 - {LAVA_MAC}: None
299 11:21:41.241824 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/1219295/extract-nfsrootfs-k_16rdse
300 11:21:41.241984 - {NFS_SERVER_IP}: 192.168.11.5
301 11:21:41.242141 - {PRESEED_CONFIG}: None
302 11:21:41.242298 - {PRESEED_LOCAL}: None
303 11:21:41.242453 - {RAMDISK_ADDR}: 0x83000000
304 11:21:41.242609 - {RAMDISK}: 1219295/tftp-deploy-xjexk29k/ramdisk/ramdisk.cpio.gz.uboot
305 11:21:41.242764 - {ROOT_PART}: None
306 11:21:41.242919 - {ROOT}: None
307 11:21:41.243074 - {SERVER_IP}: 192.168.11.5
308 11:21:41.243228 - {TEE_ADDR}: 0x83000000
309 11:21:41.243381 - {TEE}: None
310 11:21:41.243534 Parsed boot commands:
311 11:21:41.243684 - setenv autoload no
312 11:21:41.243839 - setenv initrd_high 0xffffffff
313 11:21:41.243993 - setenv fdt_high 0xffffffff
314 11:21:41.244146 - dhcp
315 11:21:41.244298 - setenv serverip 192.168.11.5
316 11:21:41.244451 - tftp 0x82000000 1219295/tftp-deploy-xjexk29k/kernel/zImage
317 11:21:41.244605 - tftp 0x83000000 1219295/tftp-deploy-xjexk29k/ramdisk/ramdisk.cpio.gz.uboot
318 11:21:41.244771 - setenv initrd_size ${filesize}
319 11:21:41.244925 - tftp 0x88000000 1219295/tftp-deploy-xjexk29k/dtb/am335x-boneblack.dtb
320 11:21:41.245079 - setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.11.5:/var/lib/lava/dispatcher/tmp/1219295/extract-nfsrootfs-k_16rdse,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
321 11:21:41.245239 - bootz 0x82000000 0x83000000 0x88000000
322 11:21:41.245437 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
324 11:21:41.246003 start: 2.3 connect-device (timeout 00:05:00) [common]
325 11:21:41.246168 [common] connect-device Connecting to device using 'telnet 127.0.0.1 63003'
326 11:21:41.607657 Setting prompt string to ['lava-test: # ']
327 11:21:41.608115 end: 2.3 connect-device (duration 00:00:00) [common]
328 11:21:41.608265 start: 2.4 uboot-commands (timeout 00:05:00) [common]
329 11:21:41.608445 start: 2.4.1 reset-device (timeout 00:05:00) [common]
330 11:21:41.608599 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
331 11:21:41.608927 Calling: 'curl' 'http://192.168.11.5:18083/1-1.3.4/1/reset'
332 11:21:41.972282 Returned 0 in 0 seconds
333 11:21:42.073356 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
335 11:21:42.074259 end: 2.4.1 reset-device (duration 00:00:00) [common]
336 11:21:42.074572 start: 2.4.2 bootloader-interrupt (timeout 00:04:59) [common]
337 11:21:42.074858 Setting prompt string to ['Press SPACE to abort autoboot in 2 seconds']
338 11:21:42.075113 bootloader-interrupt: Wait for prompt ['Press SPACE to abort autoboot in 2 seconds'] (timeout 00:05:00)
339 11:21:42.075858 Trying 127.0.0.1...
340 11:21:42.076097 Connected to 127.0.0.1.
341 11:21:42.076309 Escape character is '^]'.
342 11:21:46.903630
343 11:21:46.907410 U-Boot SPL 2019.04-00002-gf15b99f0b6 (Oct 01 2019 - 09:28:05 -0500)
344 11:21:46.963933 Trying to boot from MMC2
345 11:21:47.012391 Loading Environment from EXT4... Card did not respond to voltage select!
346 11:21:47.079479
347 11:21:47.079793
348 11:21:47.085076 U-Boot 2019.04-00002-gf15b99f0b6 (Oct 01 2019 - 09:28:05 -0500), Build: jenkins-github_Bootloader-Builder-131
349 11:21:47.085343
350 11:21:47.090067 CPU : AM335X-GP rev 2.1
351 11:21:47.144006 I2C: ready
352 11:21:47.144348 DRAM: 512 MiB
353 11:21:47.198354 No match for driver 'omap_hsmmc'
354 11:21:47.203835 No match for driver 'omap_hsmmc'
355 11:21:47.204145 Some drivers were not found
356 11:21:47.210069 Reset Source: Power-on reset has occurred.
357 11:21:47.210352 RTC 32KCLK Source: External.
358 11:21:47.217691 MMC: OMAP SD/MMC: 0, OMAP SD/MMC: 1
359 11:21:47.230878 Loading Environment from EXT4... Card did not respond to voltage select!
360 11:21:47.295503 Board: BeagleBone Black
361 11:21:47.299447 <ethaddr> not set. Validating first E-fuse MAC
362 11:21:47.355989 BeagleBone Black:
363 11:21:47.356313 BeagleBone: cape eeprom: i2c_probe: 0x54:
364 11:21:47.361584 BeagleBone: cape eeprom: i2c_probe: 0x55:
365 11:21:47.367443 BeagleBone: cape eeprom: i2c_probe: 0x56:
366 11:21:47.367711 BeagleBone: cape eeprom: i2c_probe: 0x57:
367 11:21:47.372577 Net: eth0: MII MODE
368 11:21:47.381767 cpsw, usb_ether
369 11:21:47.382041 Press SPACE to abort autoboot in 2 seconds
370 11:21:47.432857 end: 2.4.2 bootloader-interrupt (duration 00:00:05) [common]
371 11:21:47.433256 start: 2.4.3 bootloader-commands (timeout 00:04:54) [common]
372 11:21:47.433561 Setting prompt string to ['=> ']
373 11:21:47.433825 bootloader-commands: Wait for prompt ['=> '] (timeout 00:04:54)
374 11:21:47.436974 Setting prompt string to ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid']
375 11:21:47.437280 Sending with 10 millisecond of delay
377 11:21:48.571901 => setenv autoload no
378 11:21:48.582392 bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:53)
379 11:21:48.584784 setenv autoload no
380 11:21:48.585257 Sending with 10 millisecond of delay
382 11:21:50.382187 => setenv initrd_high 0xffffffff
383 11:21:50.392705 bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:51)
384 11:21:50.393203 setenv initrd_high 0xffffffff
385 11:21:50.393655 Sending with 10 millisecond of delay
387 11:21:52.009971 => setenv fdt_high 0xffffffff
388 11:21:52.020479 bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:49)
389 11:21:52.020967 setenv fdt_high 0xffffffff
390 11:21:52.021416 Sending with 10 millisecond of delay
392 11:21:52.312879 => dhcp
393 11:21:52.323377 bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:49)
394 11:21:52.323849 dhcp
395 11:21:52.324095 link up on port 0, speed 100, full duplex
396 11:21:52.324342 BOOTP broadcast 1
397 11:21:52.331753 DHCP client bound to address 192.168.11.3 (3 ms)
398 11:21:52.332188 Sending with 10 millisecond of delay
400 11:21:54.068930 => setenv serverip 192.168.11.5
401 11:21:54.079454 bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:47)
402 11:21:54.079930 setenv serverip 192.168.11.5
403 11:21:54.080383 Sending with 10 millisecond of delay
405 11:21:57.623548 => tftp 0x82000000 1219295/tftp-deploy-xjexk29k/kernel/zImage
406 11:21:57.634029 bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:44)
407 11:21:57.634537 tftp 0x82000000 1219295/tftp-deploy-xjexk29k/kernel/zImage
408 11:21:57.634790 link up on port 0, speed 100, full duplex
409 11:21:57.635029 Using cpsw device
410 11:21:57.638297 TFTP from server 192.168.11.5; our IP address is 192.168.11.3
411 11:21:57.643871 Filename '1219295/tftp-deploy-xjexk29k/kernel/zImage'.
412 11:21:57.738875 Load address: 0x82000000
413 11:21:57.825409 Loading: *#################################################################
414 11:21:57.998640 #################################################################
415 11:21:58.172749 #################################################################
416 11:21:58.369235 #################################################################
417 11:21:58.543339 #################################################################
418 11:21:58.712546 #################################################################
419 11:21:58.887469 #################################################################
420 11:21:59.062151 #################################################################
421 11:21:59.237321 #################################################################
422 11:21:59.433777 #################################################################
423 11:21:59.608158 #################################################################
424 11:21:59.775849 #################################################################
425 11:21:59.897528 ###############################################
426 11:21:59.897905 5.1 MiB/s
427 11:21:59.898145 done
428 11:21:59.901070 Bytes transferred = 12128768 (b91200 hex)
429 11:21:59.901548 Sending with 10 millisecond of delay
431 11:22:04.408317 => tftp 0x83000000 1219295/tftp-deploy-xjexk29k/ramdisk/ramdisk.cpio.gz.uboot
432 11:22:04.418856 bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:37)
433 11:22:04.419335 tftp 0x83000000 1219295/tftp-deploy-xjexk29k/ramdisk/ramdisk.cpio.gz.uboot
434 11:22:04.419569 link up on port 0, speed 100, full duplex
435 11:22:04.419786 Using cpsw device
436 11:22:04.423094 TFTP from server 192.168.11.5; our IP address is 192.168.11.3
437 11:22:04.436973 Filename '1219295/tftp-deploy-xjexk29k/ramdisk/ramdisk.cpio.gz.uboot'.
438 11:22:04.437365 Load address: 0x83000000
439 11:22:04.736591 Loading: *#################################################################
440 11:22:04.780901 #################################################################
441 11:22:04.954866 #################################################################
442 11:22:05.176294 #################################################################
443 11:22:05.308840 #################################################################
444 11:22:05.483953 #################################################################
445 11:22:05.671180 #################################################################
446 11:22:05.844798 #################################################################
447 11:22:06.019301 #################################################################
448 11:22:06.193890 #################################################################
449 11:22:06.366893 #################################################################
450 11:22:06.540234 #################################################################
451 11:22:06.712863 #################################################################
452 11:22:06.881163 #################################################################
453 11:22:07.054525 #################################################################
454 11:22:07.250652 #################################################################
455 11:22:07.256864 ########
456 11:22:07.257171 5.2 MiB/s
457 11:22:07.257446 done
458 11:22:07.257708 Bytes transferred = 15380904 (eab1a8 hex)
459 11:22:07.260468 Sending with 10 millisecond of delay
461 11:22:09.117628 => setenv initrd_size ${filesize}
462 11:22:09.128130 bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:32)
463 11:22:09.128643 setenv initrd_size ${filesize}
464 11:22:09.129135 Sending with 10 millisecond of delay
466 11:22:13.335113 => tftp 0x88000000 1219295/tftp-deploy-xjexk29k/dtb/am335x-boneblack.dtb
467 11:22:13.345627 bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:28)
468 11:22:13.346217 tftp 0x88000000 1219295/tftp-deploy-xjexk29k/dtb/am335x-boneblack.dtb
469 11:22:13.346499 link up on port 0, speed 100, full duplex
470 11:22:13.346756 Using cpsw device
471 11:22:13.349825 TFTP from server 192.168.11.5; our IP address is 192.168.11.3
472 11:22:13.375253 Filename '1219295/tftp-deploy-xjexk29k/dtb/am335x-boneblack.dtb'.
473 11:22:13.375520 Load address: 0x88000000
474 11:22:13.375760 Loading: *#####
475 11:22:13.375993 4.5 MiB/s
476 11:22:13.382014 done
477 11:22:13.382239 Bytes transferred = 70544 (11390 hex)
478 11:22:13.382664 Sending with 10 millisecond of delay
480 11:22:26.681331 => setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.11.5:/var/lib/lava/dispatcher/tmp/1219295/extract-nfsrootfs-k_16rdse,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
481 11:22:26.691813 bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:15)
482 11:22:26.692267 setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.11.5:/var/lib/lava/dispatcher/tmp/1219295/extract-nfsrootfs-k_16rdse,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
483 11:22:26.692742 Sending with 10 millisecond of delay
485 11:22:29.031566 => bootz 0x82000000 0x83000000 0x88000000
486 11:22:29.042085 Setting prompt string to ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid']
487 11:22:29.042422 bootloader-commands: Wait for prompt ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:12)
488 11:22:29.042959 bootz 0x82000000 0x83000000 0x88000000
489 11:22:29.043202 ## Loading init Ramdisk from Legacy Image at 83000000 ...
490 11:22:29.043660 Image Name:
491 11:22:29.043881 Created: 2024-11-08 11:21:41 UTC
492 11:22:29.049279 Image Type: ARM Linux RAMDisk Image (uncompressed)
493 11:22:29.054804 Data Size: 15380840 Bytes = 14.7 MiB
494 11:22:29.055083 Load Address: 00000000
495 11:22:29.062015 Entry Point: 00000000
496 11:22:29.204748 Verifying Checksum ... OK
497 11:22:29.205022 ## Flattened Device Tree blob at 88000000
498 11:22:29.211212 Booting using the fdt blob at 0x88000000
499 11:22:29.216133 Using Device Tree in place at 88000000, end 8801438f
500 11:22:29.223775
501 11:22:29.224052 Starting kernel ...
502 11:22:29.224275
503 11:22:29.224820 end: 2.4.3 bootloader-commands (duration 00:00:42) [common]
504 11:22:29.225122 start: 2.4.4 auto-login-action (timeout 00:04:12) [common]
505 11:22:29.225369 Setting prompt string to ['Linux version [0-9]']
506 11:22:29.225611 Setting prompt string to ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid']
507 11:22:29.225860 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:05:00)
508 11:22:30.140734 [ 0.000000] Booting Linux on physical CPU 0x0
509 11:22:30.146769 start: 2.4.4.1 login-action (timeout 00:04:11) [common]
510 11:22:30.147075 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
511 11:22:30.147334 Setting prompt string to []
512 11:22:30.147594 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
513 11:22:30.147843 Using line separator: #'\n'#
514 11:22:30.148061 No login prompt set.
515 11:22:30.148288 Parsing kernel messages
516 11:22:30.148504 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
517 11:22:30.148913 [login-action] Waiting for messages, (timeout 00:04:11)
518 11:22:30.163535 [ 0.000000] Linux version 6.12.0-rc6-next-20241108 (KernelCI@build-j368331-arm-clang-17-multi-v7-defconfig-d8vrp) (Debian clang version 17.0.6 (++20231208085813+6009708b4367-1~exp1~20231208085906.81), Debian LLD 17.0.6) #1 SMP Fri Nov 8 10:29:39 UTC 2024
519 11:22:30.174904 [ 0.000000] CPU: ARMv7 Processor [413fc082] revision 2 (ARMv7), cr=10c5387d
520 11:22:30.180781 [ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
521 11:22:30.186405 [ 0.000000] OF: fdt: Machine model: TI AM335x BeagleBone Black
522 11:22:30.192153 [ 0.000000] earlycon: omap8250 at MMIO 0x44e09000 (options '')
523 11:22:30.197913 [ 0.000000] printk: legacy bootconsole [omap8250] enabled
524 11:22:30.204650 [ 0.000000] Memory policy: Data cache writeback
525 11:22:30.204945 [ 0.000000] efi: UEFI not found.
526 11:22:30.212847 [ 0.000000] cma: Reserved 64 MiB at 0x9b800000 on node -1
527 11:22:30.218544 [ 0.000000] Zone ranges:
528 11:22:30.224277 [ 0.000000] DMA [mem 0x0000000080000000-0x000000009fdfffff]
529 11:22:30.230034 [ 0.000000] Normal empty
530 11:22:30.230308 [ 0.000000] HighMem empty
531 11:22:30.232902 [ 0.000000] Movable zone start for each node
532 11:22:30.238794 [ 0.000000] Early memory node ranges
533 11:22:30.244357 [ 0.000000] node 0: [mem 0x0000000080000000-0x000000009fdfffff]
534 11:22:30.252561 [ 0.000000] Initmem setup node 0 [mem 0x0000000080000000-0x000000009fdfffff]
535 11:22:30.265889 [ 0.000000] OF: reserved mem: Reserved memory: No reserved-memory node in the DT
536 11:22:30.279273 [ 0.000000] CPU: All CPU(s) started in SVC mode.
537 11:22:30.284943 [ 0.000000] AM335X ES2.1 (sgx neon)
538 11:22:30.296873 [ 0.000000] percpu: Embedded 17 pages/cpu s40204 r8192 d21236 u69632
539 11:22:30.314375 [ 0.000000] Kernel command line: console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.11.5:/var/lib/lava/dispatcher/tmp/1219295/extract-nfsrootfs-k_16rdse,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp
540 11:22:30.325988 <6>[ 0.000000] printk: log buffer data + meta data: 131072 + 409600 = 540672 bytes
541 11:22:30.331768 <6>[ 0.000000] Dentry cache hash table entries: 65536 (order: 6, 262144 bytes, linear)
542 11:22:30.343255 <6>[ 0.000000] Inode-cache hash table entries: 32768 (order: 5, 131072 bytes, linear)
543 11:22:30.349003 <6>[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 130560
544 11:22:30.355594 <6>[ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
545 11:22:30.384786 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
546 11:22:30.390837 <6>[ 0.000000] trace event string verifier disabled
547 11:22:30.391169 <6>[ 0.000000] rcu: Hierarchical RCU implementation.
548 11:22:30.396537 <6>[ 0.000000] rcu: RCU event tracing is enabled.
549 11:22:30.408038 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=16 to nr_cpu_ids=1.
550 11:22:30.408317 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
551 11:22:30.419414 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 10 jiffies.
552 11:22:30.425182 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=1
553 11:22:30.435978 <6>[ 0.000000] RCU Tasks Trace: Setting shift to 0 and lim to 1 rcu_task_cb_adjust=1 rcu_task_cpu_ids=1.
554 11:22:30.451102 <6>[ 0.000000] NR_IRQS: 16, nr_irqs: 16, preallocated irqs: 16
555 11:22:30.469415 <6>[ 0.000000] IRQ: Found an INTC at 0x(ptrval) (revision 5.0) with 128 interrupts
556 11:22:30.476228 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
557 11:22:30.578907 <6>[ 0.000000] TI gptimer clocksource: always-on /ocp/interconnect@44c00000/segment@200000/target-module@31000
558 11:22:30.590405 <6>[ 0.000003] sched_clock: 32 bits at 24MHz, resolution 41ns, wraps every 89478484971ns
559 11:22:30.597295 <6>[ 0.008336] clocksource: dmtimer: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 79635851949 ns
560 11:22:30.610298 <6>[ 0.019229] TI gptimer clockevent: 24000000 Hz at /ocp/interconnect@48000000/segment@0/target-module@40000
561 11:22:30.618172 <6>[ 0.034511] Console: colour dummy device 80x30
562 11:22:30.624111 Matched prompt #6: WARNING:
563 11:22:30.624405 Setting prompt string to ['end trace[^\\r]*\\r', '/ #', 'Login timed out', 'Login incorrect']
564 11:22:30.629642 <3>[ 0.039411] WARNING: Your 'console=ttyO0' has been replaced by 'ttyS0'
565 11:22:30.635351 <3>[ 0.046480] This ensures that you still see kernel messages. Please
566 11:22:30.638557 <3>[ 0.053207] update your kernel commandline.
567 11:22:30.678778 <6>[ 0.057819] Calibrating delay loop... 996.14 BogoMIPS (lpj=4980736)
568 11:22:30.684530 <6>[ 0.096236] CPU: Testing write buffer coherency: ok
569 11:22:30.690527 <6>[ 0.101605] CPU0: Spectre v2: using BPIALL workaround
570 11:22:30.690803 <6>[ 0.107073] pid_max: default: 32768 minimum: 301
571 11:22:30.702026 <6>[ 0.112272] Mount-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
572 11:22:30.709048 <6>[ 0.120093] Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
573 11:22:30.716294 <6>[ 0.129552] CPU0: thread -1, cpu 0, socket -1, mpidr 0
574 11:22:30.724904 <6>[ 0.136633] Setting up static identity map for 0x80300000 - 0x803000ac
575 11:22:30.730550 <6>[ 0.146427] rcu: Hierarchical SRCU implementation.
576 11:22:30.738207 <6>[ 0.151709] rcu: Max phase no-delay instances is 1000.
577 11:22:30.747166 <6>[ 0.163250] EFI services will not be available.
578 11:22:30.753029 <6>[ 0.168531] smp: Bringing up secondary CPUs ...
579 11:22:30.758772 <6>[ 0.173582] smp: Brought up 1 node, 1 CPU
580 11:22:30.764525 <6>[ 0.177981] SMP: Total of 1 processors activated (996.14 BogoMIPS).
581 11:22:30.770428 <6>[ 0.184750] CPU: All CPU(s) started in SVC mode.
582 11:22:30.790826 <6>[ 0.189951] Memory: 404376K/522240K available (17408K kernel code, 2537K rwdata, 6736K rodata, 2048K init, 430K bss, 50668K reserved, 65536K cma-reserved, 0K highmem)
583 11:22:30.791117 <6>[ 0.206246] devtmpfs: initialized
584 11:22:30.813900 <6>[ 0.224146] VFP support v0.3: implementor 41 architecture 3 part 30 variant c rev 3
585 11:22:30.825403 <6>[ 0.232730] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
586 11:22:30.831291 <6>[ 0.243188] futex hash table entries: 256 (order: 2, 16384 bytes, linear)
587 11:22:30.841931 <6>[ 0.255486] pinctrl core: initialized pinctrl subsystem
588 11:22:30.851755 <6>[ 0.266482] DMI not present or invalid.
589 11:22:30.860099 <6>[ 0.272356] NET: Registered PF_NETLINK/PF_ROUTE protocol family
590 11:22:30.869644 <6>[ 0.281373] DMA: preallocated 256 KiB pool for atomic coherent allocations
591 11:22:30.884901 <6>[ 0.293065] thermal_sys: Registered thermal governor 'step_wise'
592 11:22:30.885178 <6>[ 0.293254] cpuidle: using governor menu
593 11:22:30.923983 <6>[ 0.322206] /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70: Fixed dependency cycle(s) with /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
594 11:22:30.939509 <6>[ 0.341030] /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
595 11:22:30.945227 <6>[ 0.361707] No ATAGs?
596 11:22:30.951388 <6>[ 0.364338] hw-breakpoint: debug architecture 0x4 unsupported.
597 11:22:30.961791 <6>[ 0.376543] Serial: AMBA PL011 UART driver
598 11:22:30.998913 <6>[ 0.415268] iommu: Default domain type: Translated
599 11:22:31.008092 <6>[ 0.420616] iommu: DMA domain TLB invalidation policy: strict mode
600 11:22:31.035409 <5>[ 0.451043] SCSI subsystem initialized
601 11:22:31.041241 <6>[ 0.455944] usbcore: registered new interface driver usbfs
602 11:22:31.046976 <6>[ 0.462028] usbcore: registered new interface driver hub
603 11:22:31.055907 <6>[ 0.467817] usbcore: registered new device driver usb
604 11:22:31.061648 <6>[ 0.474386] pps_core: LinuxPPS API ver. 1 registered
605 11:22:31.067356 <6>[ 0.479824] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
606 11:22:31.073218 <6>[ 0.489528] PTP clock support registered
607 11:22:31.078267 <6>[ 0.493975] EDAC MC: Ver: 3.0.0
608 11:22:31.129291 <6>[ 0.543216] scmi_core: SCMI protocol bus registered
609 11:22:31.153531 <6>[ 0.569159] vgaarb: loaded
610 11:22:31.159569 <6>[ 0.573016] clocksource: Switched to clocksource dmtimer
611 11:22:31.186404 <6>[ 0.602392] NET: Registered PF_INET protocol family
612 11:22:31.199136 <6>[ 0.608119] IP idents hash table entries: 8192 (order: 4, 65536 bytes, linear)
613 11:22:31.204852 <6>[ 0.617152] tcp_listen_portaddr_hash hash table entries: 512 (order: 0, 4096 bytes, linear)
614 11:22:31.216393 <6>[ 0.626095] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
615 11:22:31.222133 <6>[ 0.634361] TCP established hash table entries: 4096 (order: 2, 16384 bytes, linear)
616 11:22:31.233757 <6>[ 0.642633] TCP bind hash table entries: 4096 (order: 4, 65536 bytes, linear)
617 11:22:31.239597 <6>[ 0.650349] TCP: Hash tables configured (established 4096 bind 4096)
618 11:22:31.245329 <6>[ 0.657278] UDP hash table entries: 256 (order: 1, 8192 bytes, linear)
619 11:22:31.251220 <6>[ 0.664313] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes, linear)
620 11:22:31.258761 <6>[ 0.671904] NET: Registered PF_UNIX/PF_LOCAL protocol family
621 11:22:31.342771 <6>[ 0.753518] RPC: Registered named UNIX socket transport module.
622 11:22:31.343107 <6>[ 0.759905] RPC: Registered udp transport module.
623 11:22:31.348503 <6>[ 0.765063] RPC: Registered tcp transport module.
624 11:22:31.357255 <6>[ 0.770170] RPC: Registered tcp-with-tls transport module.
625 11:22:31.363001 <6>[ 0.776095] RPC: Registered tcp NFSv4.1 backchannel transport module.
626 11:22:31.370379 <6>[ 0.783022] PCI: CLS 0 bytes, default 64
627 11:22:31.372555 <5>[ 0.788875] Initialise system trusted keyrings
628 11:22:31.394408 <6>[ 0.807715] Trying to unpack rootfs image as initramfs...
629 11:22:31.463252 <6>[ 0.873471] workingset: timestamp_bits=30 max_order=17 bucket_order=0
630 11:22:31.468102 <6>[ 0.880972] squashfs: version 4.0 (2009/01/31) Phillip Lougher
631 11:22:31.507768 <5>[ 0.924035] NFS: Registering the id_resolver key type
632 11:22:31.513499 <5>[ 0.929624] Key type id_resolver registered
633 11:22:31.519251 <5>[ 0.934316] Key type id_legacy registered
634 11:22:31.525143 <6>[ 0.938752] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
635 11:22:31.534684 <6>[ 0.945981] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
636 11:22:31.617514 <5>[ 1.033928] Key type asymmetric registered
637 11:22:31.623493 <5>[ 1.038453] Asymmetric key parser 'x509' registered
638 11:22:31.634995 <6>[ 1.044024] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 246)
639 11:22:31.635274 <6>[ 1.051912] io scheduler mq-deadline registered
640 11:22:31.640881 <6>[ 1.056913] io scheduler kyber registered
641 11:22:31.646484 <6>[ 1.061368] io scheduler bfq registered
642 11:22:31.762629 <6>[ 1.175248] ledtrig-cpu: registered to indicate activity on CPUs
643 11:22:32.024213 <6>[ 1.436719] Serial: 8250/16550 driver, 5 ports, IRQ sharing enabled
644 11:22:32.062353 <6>[ 1.478327] msm_serial: driver initialized
645 11:22:32.068306 <6>[ 1.483365] SuperH (H)SCI(F) driver initialized
646 11:22:32.074188 <6>[ 1.488519] STMicroelectronics ASC driver initialized
647 11:22:32.079456 <6>[ 1.494206] STM32 USART driver initialized
648 11:22:32.208028 <6>[ 1.623860] brd: module loaded
649 11:22:32.244456 <6>[ 1.660074] loop: module loaded
650 11:22:32.295762 <6>[ 1.711124] CAN device driver interface
651 11:22:32.302476 <6>[ 1.716489] bgmac_bcma: Broadcom 47xx GBit MAC driver loaded
652 11:22:32.308206 <6>[ 1.723574] e1000e: Intel(R) PRO/1000 Network Driver
653 11:22:32.314095 <6>[ 1.728962] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
654 11:22:32.319832 <6>[ 1.735430] igb: Intel(R) Gigabit Ethernet Network Driver
655 11:22:32.328022 <6>[ 1.741254] igb: Copyright (c) 2007-2014 Intel Corporation.
656 11:22:32.339831 <6>[ 1.750536] pegasus: Pegasus/Pegasus II USB Ethernet driver
657 11:22:32.345726 <6>[ 1.756705] usbcore: registered new interface driver pegasus
658 11:22:32.351472 <6>[ 1.762834] usbcore: registered new interface driver asix
659 11:22:32.357226 <6>[ 1.768718] usbcore: registered new interface driver ax88179_178a
660 11:22:32.362969 <6>[ 1.775310] usbcore: registered new interface driver cdc_ether
661 11:22:32.368863 <6>[ 1.781605] usbcore: registered new interface driver smsc75xx
662 11:22:32.374593 <6>[ 1.787845] usbcore: registered new interface driver smsc95xx
663 11:22:32.380342 <6>[ 1.794077] usbcore: registered new interface driver net1080
664 11:22:32.386091 <6>[ 1.800200] usbcore: registered new interface driver cdc_subset
665 11:22:32.391843 <6>[ 1.806607] usbcore: registered new interface driver zaurus
666 11:22:32.399514 <6>[ 1.812654] usbcore: registered new interface driver cdc_ncm
667 11:22:32.409380 <6>[ 1.822201] usbcore: registered new interface driver usb-storage
668 11:22:32.418879 <6>[ 1.833507] i2c_dev: i2c /dev entries driver
669 11:22:32.443682 <5>[ 1.852059] cpuidle: enable-method property 'ti,am3352' found operations
670 11:22:32.449451 <6>[ 1.861591] sdhci: Secure Digital Host Controller Interface driver
671 11:22:32.456922 <6>[ 1.868347] sdhci: Copyright(c) Pierre Ossman
672 11:22:32.464034 <6>[ 1.874832] Synopsys Designware Multimedia Card Interface Driver
673 11:22:32.469460 <6>[ 1.882667] sdhci-pltfm: SDHCI platform and OF driver helper
674 11:22:32.483722 <6>[ 1.892650] usbcore: registered new interface driver usbhid
675 11:22:32.483968 <6>[ 1.898771] usbhid: USB HID core driver
676 11:22:32.496792 <6>[ 1.910499] NET: Registered PF_INET6 protocol family
677 11:22:32.957361 <6>[ 2.373779] Segment Routing with IPv6
678 11:22:32.963144 <6>[ 2.377923] In-situ OAM (IOAM) with IPv6
679 11:22:32.969921 <6>[ 2.382316] sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver
680 11:22:32.975795 <6>[ 2.389773] NET: Registered PF_PACKET protocol family
681 11:22:32.981668 <6>[ 2.395342] can: controller area network core
682 11:22:32.987417 <6>[ 2.400169] NET: Registered PF_CAN protocol family
683 11:22:32.987697 <6>[ 2.405403] can: raw protocol
684 11:22:32.993165 <6>[ 2.408730] can: broadcast manager protocol
685 11:22:32.999665 <6>[ 2.413328] can: netlink gateway - max_hops=1
686 11:22:33.005787 <5>[ 2.418845] Key type dns_resolver registered
687 11:22:33.012201 <6>[ 2.423931] ThumbEE CPU extension supported.
688 11:22:33.012485 <5>[ 2.428619] Registering SWP/SWPB emulation handler
689 11:22:33.021853 <3>[ 2.434330] omap_voltage_late_init: Voltage driver support not added
690 11:22:33.236481 <5>[ 2.650545] Loading compiled-in X.509 certificates
691 11:22:33.307187 <6>[ 2.708685] /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70: Fixed dependency cycle(s) with /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
692 11:22:33.337052 <6>[ 2.738615] /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70: Fixed dependency cycle(s) with /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
693 11:22:33.494639 <6>[ 2.891973] /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70: Fixed dependency cycle(s) with /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
694 11:22:33.510047 <6>[ 2.911626] /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70: Fixed dependency cycle(s) with /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
695 11:22:33.537057 <6>[ 2.938486] /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800/clkout2-pins
696 11:22:33.547071 <6>[ 2.960082] pinctrl-single 44e10800.pinmux: 142 pins, size 568
697 11:22:33.574188 <3>[ 2.984598] ti-sysc 44e31000.target-module: probe with driver ti-sysc failed with error -16
698 11:22:33.855401 <6>[ 3.256931] /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
699 11:22:33.881772 <3>[ 3.292176] ti-sysc 48040000.target-module: probe with driver ti-sysc failed with error -16
700 11:22:34.059470 <6>[ 3.474308] OMAP GPIO hardware version 0.1
701 11:22:34.080794 <6>[ 3.493514] omap-mailbox 480c8000.mailbox: omap mailbox rev 0x400
702 11:22:34.142769 <4>[ 3.555310] at24 2-0054: supply vcc not found, using dummy regulator
703 11:22:34.176651 <4>[ 3.589170] at24 2-0055: supply vcc not found, using dummy regulator
704 11:22:34.214153 <4>[ 3.626713] at24 2-0056: supply vcc not found, using dummy regulator
705 11:22:34.255686 <4>[ 3.668076] at24 2-0057: supply vcc not found, using dummy regulator
706 11:22:34.305669 <6>[ 3.719588] Freeing initrd memory: 15024K
707 11:22:34.313286 <6>[ 3.726659] omap_i2c 4819c000.i2c: bus 2 rev0.11 at 100 kHz
708 11:22:34.349446 <3>[ 3.758744] 48000000.interconnect:segment@200000:target-module@0:mpu@0:fck: device ID is greater than 24
709 11:22:34.371774 <6>[ 3.773326] /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
710 11:22:34.398914 <6>[ 3.796700] /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
711 11:22:34.416242 <6>[ 3.816010] /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70: Fixed dependency cycle(s) with /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
712 11:22:34.432394 <6>[ 3.833985] /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
713 11:22:34.454368 <4>[ 3.864737] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
714 11:22:34.462490 <4>[ 3.873400] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
715 11:22:34.471063 <6>[ 3.883766] omap_rng 48310000.rng: Random Number Generator ver. 20
716 11:22:34.495382 <5>[ 3.910852] random: crng init done
717 11:22:34.541952 <6>[ 3.953053] davinci_mdio 4a101000.mdio: davinci mdio revision 1.6, bus freq 1000000
718 11:22:34.625265 <6>[ 4.035477] davinci_mdio 4a101000.mdio: phy[0]: device 4a101000.mdio:00, driver SMSC LAN8710/LAN8720
719 11:22:34.631017 <6>[ 4.045800] cpsw-switch 4a100000.switch: initialized cpsw ale version 1.4
720 11:22:34.642779 <6>[ 4.053144] cpsw-switch 4a100000.switch: ALE Table size 1024, Policers 0
721 11:22:34.648644 <6>[ 4.060600] cpsw-switch 4a100000.switch: cpts: overflow check period 500 (jiffies)
722 11:22:34.660136 <6>[ 4.068739] cpsw-switch 4a100000.switch: CPTS: ref_clk_freq:250000000 calc_mult:2147483648 calc_shift:29 error:0 nsec/sec
723 11:22:34.667671 <6>[ 4.080385] cpsw-switch 4a100000.switch: Detected MACID = 64:cf:d9:3f:a0:d5
724 11:22:34.680863 <5>[ 4.089502] cpsw-switch 4a100000.switch: initialized (regs 0x4a100000, pool size 256) hw_ver:0019010C 1.12 (0)
725 11:22:34.709144 <3>[ 4.119881] debugfs: Directory '49000000.dma' with parent 'dmaengine' already present!
726 11:22:34.714976 <6>[ 4.128526] edma 49000000.dma: TI EDMA DMA engine driver
727 11:22:34.787880 <3>[ 4.197988] target-module@4b000000:target-module@140000:pmu@0:fck: device ID is greater than 24
728 11:22:34.802728 <6>[ 4.212487] hw perfevents: enabled with armv7_cortex_a8 PMU driver, 5 (8000000f) counters available
729 11:22:34.815730 <3>[ 4.229700] l3-aon-clkctrl:0000:0: failed to disable
730 11:22:34.871036 <6>[ 4.281783] 44e09000.serial: ttyS0 at MMIO 0x44e09000 (irq = 36, base_baud = 3000000) is a 8250
731 11:22:34.876805 <6>[ 4.291296] printk: legacy console [ttyS0] enabled
732 11:22:34.882411 <6>[ 4.291296] printk: legacy console [ttyS0] enabled
733 11:22:34.888033 <6>[ 4.301628] printk: legacy bootconsole [omap8250] disabled
734 11:22:34.893830 <6>[ 4.301628] printk: legacy bootconsole [omap8250] disabled
735 11:22:34.924029 <4>[ 4.333857] tps65217-pmic: Failed to locate of_node [id: -1]
736 11:22:34.927611 <4>[ 4.341262] tps65217-bl: Failed to locate of_node [id: -1]
737 11:22:34.944568 <6>[ 4.361406] tps65217 0-0024: TPS65217 ID 0xe version 1.2
738 11:22:34.968643 <6>[ 4.368417] /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
739 11:22:34.986016 <6>[ 4.386075] /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70: Fixed dependency cycle(s) with /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
740 11:22:34.990338 <6>[ 4.403921] omap_i2c 44e0b000.i2c: bus 0 rev0.11 at 400 kHz
741 11:22:35.013195 <6>[ 4.424324] omap_gpio 44e07000.gpio: Could not set line 6 debounce to 200000 microseconds (-22)
742 11:22:35.019031 <6>[ 4.433488] sdhci-omap 48060000.mmc: Got CD GPIO
743 11:22:35.027075 <4>[ 4.438610] sdhci-omap 48060000.mmc: supply pbias not found, using dummy regulator
744 11:22:35.041903 <4>[ 4.452310] sdhci-omap 48060000.mmc: supply vqmmc not found, using dummy regulator
745 11:22:35.048315 <4>[ 4.461072] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
746 11:22:35.058262 <4>[ 4.469718] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
747 11:22:35.098947 <6>[ 4.511238] at24 0-0050: 32768 byte 24c256 EEPROM, writable, 1 bytes/write
748 11:22:35.122051 <6>[ 4.532585] mmc1: SDHCI controller on 481d8000.mmc [481d8000.mmc] using External DMA
749 11:22:35.130002 <6>[ 4.541371] mmc0: SDHCI controller on 48060000.mmc [48060000.mmc] using External DMA
750 11:22:35.142797 <6>[ 4.555226] cpsw-switch 4a100000.switch: starting ndev. mode: dual_mac
751 11:22:35.205987 <6>[ 4.612383] mmc1: new high speed MMC card at address 0001
752 11:22:35.206266 <6>[ 4.620575] mmcblk1: mmc1:0001 M62704 3.56 GiB
753 11:22:35.217332 <6>[ 4.632476] mmcblk1: p1
754 11:22:35.230514 <6>[ 4.636940] SMSC LAN8710/LAN8720 4a101000.mdio:00: attached PHY driver (mii_bus:phy_addr=4a101000.mdio:00, irq=POLL)
755 11:22:35.235618 <6>[ 4.649709] mmcblk1boot0: mmc1:0001 M62704 2.00 MiB
756 11:22:35.247626 <6>[ 4.661713] mmcblk1boot1: mmc1:0001 M62704 2.00 MiB
757 11:22:35.261600 <6>[ 4.674430] mmcblk1rpmb: mmc1:0001 M62704 512 KiB, chardev (236:0)
758 11:22:38.393130 <6>[ 7.804051] cpsw-switch 4a100000.switch eth0: Link is Up - 100Mbps/Full - flow control off
759 11:22:38.466551 <5>[ 7.843025] Sending DHCP requests ., OK
760 11:22:38.477855 <6>[ 7.887471] IP-Config: Got DHCP answer from 192.168.11.1, my address is 192.168.11.3
761 11:22:38.478155 <6>[ 7.895720] IP-Config: Complete:
762 11:22:38.489194 <6>[ 7.899259] device=eth0, hwaddr=64:cf:d9:3f:a0:d5, ipaddr=192.168.11.3, mask=255.255.255.0, gw=192.168.11.1
763 11:22:38.494853 <6>[ 7.909857] host=192.168.11.3, domain=usen.ad.jp, nis-domain=(none)
764 11:22:38.507173 <6>[ 7.916940] bootserver=0.0.0.0, rootserver=192.168.11.5, rootpath=
765 11:22:38.507414 <6>[ 7.916977] nameserver0=192.168.11.1
766 11:22:38.513418 <6>[ 7.929339] clk: Disabling unused clocks
767 11:22:38.519846 <6>[ 7.934105] PM: genpd: Disabling unused power domains
768 11:22:38.537981 <6>[ 7.951243] Freeing unused kernel image (initmem) memory: 2048K
769 11:22:38.545509 <6>[ 7.961050] Run /init as init process
770 11:22:38.571020 Loading, please wait...
771 11:22:38.647935 Starting systemd-udevd version 252.22-1~deb12u1
772 11:22:41.696518 <4>[ 11.106076] am335x-phy-driver 47401300.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
773 11:22:41.854172 <4>[ 11.263675] am335x-phy-driver 47401b00.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
774 11:22:41.986580 <6>[ 11.403676] musb-hdrc musb-hdrc.1: MUSB HDRC host driver
775 11:22:41.997395 <6>[ 11.409352] musb-hdrc musb-hdrc.1: new USB bus registered, assigned bus number 1
776 11:22:42.197125 <6>[ 11.612745] hub 1-0:1.0: USB hub found
777 11:22:42.222162 <6>[ 11.637508] hub 1-0:1.0: 1 port detected
778 11:22:42.320831 <6>[ 11.736022] tda998x 0-0070: found TDA19988
779 11:22:45.172226 Begin: Loading essential drivers ... done.
780 11:22:45.182186 Begin: Running /scripts/init-premount ... done.
781 11:22:45.195292 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
782 11:22:45.201746 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
783 11:22:45.211378 Device /sys/class/net/eth0 found
784 11:22:45.211649 done.
785 11:22:45.272313 Begin: Waiting up to 180 secs for any network device to become available ... done.
786 11:22:45.352189 IP-Config: eth0 hardware address 64:cf:d9:3f:a0:d5 mtu 1500 DHCP
787 11:22:45.352524 IP-Config: eth0 guessed broadcast address 192.168.11.255
788 11:22:45.357702 IP-Config: eth0 complete (dhcp from 192.168.11.1):
789 11:22:45.368800 address: 192.168.11.3 broadcast: 192.168.11.255 netmask: 255.255.255.0
790 11:22:45.374468 gateway: 192.168.11.1 dns0 : 192.168.11.1 dns1 : 0.0.0.0
791 11:22:45.380041 domain : usen.ad.jp
792 11:22:45.385026 rootserver: 192.168.11.1 rootpath:
793 11:22:45.385331 filename :
794 11:22:45.449814 done.
795 11:22:45.470856 Begin: Running /scripts/nfs-bottom ... done.
796 11:22:45.536833 Begin: Running /scripts/init-bottom ... done.
797 11:22:46.971512 <30>[ 16.384272] systemd[1]: System time before build time, advancing clock.
798 11:22:47.138118 <30>[ 16.524725] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
799 11:22:47.147358 <30>[ 16.562059] systemd[1]: Detected architecture arm.
800 11:22:47.160559
801 11:22:47.160861 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
802 11:22:47.161093
803 11:22:47.189293 <30>[ 16.602761] systemd[1]: Hostname set to <debian-bookworm-armhf>.
804 11:22:49.339630 <30>[ 18.752003] systemd[1]: Queued start job for default target graphical.target.
805 11:22:49.356804 <30>[ 18.767061] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
806 11:22:49.364298 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
807 11:22:49.385260 <30>[ 18.795926] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
808 11:22:49.393718 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
809 11:22:49.416047 <30>[ 18.826495] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
810 11:22:49.424392 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
811 11:22:49.444377 <30>[ 18.855014] systemd[1]: Created slice user.slice - User and Session Slice.
812 11:22:49.451001 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
813 11:22:49.479476 <30>[ 18.884404] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
814 11:22:49.485405 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
815 11:22:49.503543 <30>[ 18.914213] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
816 11:22:49.512338 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
817 11:22:49.544303 <30>[ 18.944152] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
818 11:22:49.550808 <30>[ 18.964670] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
819 11:22:49.559216 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
820 11:22:49.582557 <30>[ 18.993576] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
821 11:22:49.590738 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
822 11:22:49.613181 <30>[ 19.023897] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
823 11:22:49.621580 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
824 11:22:49.643055 <30>[ 19.053951] systemd[1]: Reached target paths.target - Path Units.
825 11:22:49.648128 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
826 11:22:49.672674 <30>[ 19.083710] systemd[1]: Reached target remote-fs.target - Remote File Systems.
827 11:22:49.680094 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
828 11:22:49.702533 <30>[ 19.113580] systemd[1]: Reached target slices.target - Slice Units.
829 11:22:49.708090 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
830 11:22:49.732817 <30>[ 19.143778] systemd[1]: Reached target swap.target - Swaps.
831 11:22:49.736822 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
832 11:22:49.763854 <30>[ 19.175004] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
833 11:22:49.776202 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
834 11:22:49.803778 <30>[ 19.214587] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
835 11:22:49.812086 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
836 11:22:49.899330 <30>[ 19.305226] systemd[1]: systemd-journald-audit.socket - Journal Audit Socket was skipped because of an unmet condition check (ConditionSecurity=audit).
837 11:22:49.912280 <30>[ 19.322727] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
838 11:22:49.920705 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
839 11:22:49.944671 <30>[ 19.354830] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
840 11:22:49.952075 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
841 11:22:49.976160 <30>[ 19.386714] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
842 11:22:49.984298 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
843 11:22:50.007635 <30>[ 19.418232] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
844 11:22:50.013239 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
845 11:22:50.046779 <30>[ 19.456483] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
846 11:22:50.054170 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
847 11:22:50.079838 <30>[ 19.484660] systemd[1]: dev-hugepages.mount - Huge Pages File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/mm/hugepages).
848 11:22:50.096257 <30>[ 19.501128] systemd[1]: dev-mqueue.mount - POSIX Message Queue File System was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/mqueue).
849 11:22:50.146708 <30>[ 19.558372] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
850 11:22:50.177075 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
851 11:22:50.246467 <30>[ 19.658049] systemd[1]: Mounting sys-kernel-tracing.mount - Kernel Trace File System...
852 11:22:50.265220 Mounting [0;1;39msys-kernel-tracin…[0m - Kernel Trace File System...
853 11:22:50.336199 <30>[ 19.746766] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
854 11:22:50.370803 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
855 11:22:50.423193 <30>[ 19.834502] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
856 11:22:50.446924 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
857 11:22:50.503327 <30>[ 19.914895] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
858 11:22:50.527804 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
859 11:22:50.585304 <30>[ 19.997413] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
860 11:22:50.605215 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
861 11:22:50.665063 <30>[ 20.075947] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
862 11:22:50.693052 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
863 11:22:50.752444 <30>[ 20.164448] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
864 11:22:50.769112 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
865 11:22:50.806681 <30>[ 20.218628] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
866 11:22:50.831718 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
867 11:22:50.861241 <28>[ 20.265496] systemd[1]: systemd-journald.service: unit configures an IP firewall, but the local system does not support BPF/cgroup firewalling.
868 11:22:50.869672 <28>[ 20.280799] systemd[1]: (This warning is only shown for the first unit using IP firewalling.)
869 11:22:50.913119 <30>[ 20.324141] systemd[1]: Starting systemd-journald.service - Journal Service...
870 11:22:50.919418 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
871 11:22:50.967440 <30>[ 20.379091] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
872 11:22:50.983456 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
873 11:22:51.032609 <30>[ 20.444562] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
874 11:22:51.074584 Starting [0;1;39msystemd-network-g… units from Kernel command line...
875 11:22:51.135670 <30>[ 20.546144] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
876 11:22:51.176079 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
877 11:22:51.226432 <30>[ 20.637625] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
878 11:22:51.283582 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
879 11:22:51.402531 <30>[ 20.814629] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
880 11:22:51.442401 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
881 11:22:51.464898 <30>[ 20.876751] systemd[1]: Mounted sys-kernel-tracing.mount - Kernel Trace File System.
882 11:22:51.499299 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-tracing…nt[0m - Kernel Trace File System.
883 11:22:51.526403 <30>[ 20.937235] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
884 11:22:51.560520 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
885 11:22:51.697804 <30>[ 21.110474] systemd[1]: modprobe@configfs.service: Deactivated successfully.
886 11:22:51.733258 <30>[ 21.144785] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
887 11:22:51.762279 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
888 11:22:51.793026 <30>[ 21.205846] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
889 11:22:51.823150 <30>[ 21.234943] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
890 11:22:51.852421 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
891 11:22:51.873006 <30>[ 21.286031] systemd[1]: modprobe@drm.service: Deactivated successfully.
892 11:22:51.912602 <30>[ 21.323783] systemd[1]: Finished modprobe@drm.service - Load Kernel Module drm.
893 11:22:51.920142 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
894 11:22:51.929402 <30>[ 21.342055] systemd[1]: Started systemd-journald.service - Journal Service.
895 11:22:51.952341 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
896 11:22:51.994056 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
897 11:22:52.018180 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
898 11:22:52.053676 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
899 11:22:52.082693 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
900 11:22:52.104979 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
901 11:22:52.132761 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
902 11:22:52.162401 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
903 11:22:52.222170 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
904 11:22:52.292326 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
905 11:22:52.333243 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
906 11:22:52.417113 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
907 11:22:52.496221 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
908 11:22:52.635248 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
909 11:22:52.686727 <46>[ 22.098722] systemd-journald[163]: Received client request to flush runtime journal.
910 11:22:52.776084 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
911 11:22:52.899970 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
912 11:22:53.684552 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
913 11:22:53.749299 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
914 11:22:54.503455 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
915 11:22:54.676443 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
916 11:22:54.712455 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
917 11:22:54.732340 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
918 11:22:54.821348 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
919 11:22:54.874473 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
920 11:22:55.783634 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
921 11:22:55.842651 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
922 11:22:56.307266 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
923 11:22:56.442640 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
924 11:22:56.504195 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
925 11:22:58.453247 [[0m[0;31m* [0m] (1 of 5) Job systemd-timesyncd.service/start running (9s / 1min 37s)
926 11:22:58.525703 M[K[[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
927 11:22:58.901740 [K[[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
928 11:22:59.074405 <5>[ 28.486732] cfg80211: Loading compiled-in X.509 certificates for regulatory database
929 11:22:59.529537 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
930 11:23:00.444475 <5>[ 29.858934] Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
931 11:23:00.539399 <5>[ 29.948958] Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
932 11:23:00.545143 <4>[ 29.959161] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
933 11:23:00.552928 <6>[ 29.968315] cfg80211: failed to load regulatory.db
934 11:23:01.481894 <46>[ 30.884138] systemd-journald[163]: Oldest entry in /var/log/journal/658c871cd7314ccea6115dc5728f8992/system.journal is older than the configured file retention duration (1month), suggesting rotation.
935 11:23:01.548404 <46>[ 30.953690] systemd-journald[163]: /var/log/journal/658c871cd7314ccea6115dc5728f8992/system.journal: Journal header limits reached or header out-of-date, rotating.
936 11:23:01.564655 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
937 11:23:01.595755 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
938 11:23:09.860493 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
939 11:23:09.889072 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
940 11:23:09.913729 [[0;32m OK [0m] Reached target [0;1;39musb-gadget.…m - Hardware activated USB gadget.
941 11:23:09.934350 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
942 11:23:09.992455 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
943 11:23:10.041870 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
944 11:23:10.106846 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
945 11:23:10.154705 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
946 11:23:10.218512 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
947 11:23:10.248315 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
948 11:23:10.289739 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
949 11:23:10.323609 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
950 11:23:10.350853 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
951 11:23:10.393743 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
952 11:23:10.434741 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
953 11:23:10.446541 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
954 11:23:10.489101 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
955 11:23:10.531489 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
956 11:23:10.553595 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
957 11:23:10.572727 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
958 11:23:10.602641 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
959 11:23:10.622454 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
960 11:23:10.651525 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
961 11:23:10.722332 Starting [0;1;39malsa-restore.serv…- Save/Restore Sound Card State...
962 11:23:10.762379 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
963 11:23:10.853786 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
964 11:23:10.942104 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
965 11:23:11.013459 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
966 11:23:11.046816 [[0;32m OK [0m] Finished [0;1;39malsa-restore.serv…m - Save/Restore Sound Card State.
967 11:23:11.058612 [[0;32m OK [0m] Reached target [0;1;39msound.target[0m - Sound Card.
968 11:23:11.301713 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
969 11:23:11.353254 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
970 11:23:11.424557 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
971 11:23:11.451359 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
972 11:23:11.474295 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
973 11:23:11.666421 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
974 11:23:12.015040 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
975 11:23:12.076287 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
976 11:23:12.106388 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
977 11:23:12.193920 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
978 11:23:12.371248 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
979 11:23:12.510024
980 11:23:12.513637 Debian GNU/Linux 12 debworm-armhf login: root (automatic login)
981 11:23:12.513922
982 11:23:12.827434 Linux debian-bookworm-armhf 6.12.0-rc6-next-20241108 #1 SMP Fri Nov 8 10:29:39 UTC 2024 armv7l
983 11:23:12.827723
984 11:23:12.833057 The programs included with the Debian GNU/Linux system are free software;
985 11:23:12.838562 the exact distribution terms for each program are described in the
986 11:23:12.844207 individual files in /usr/share/doc/*/copyright.
987 11:23:12.844490
988 11:23:12.849806 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
989 11:23:12.853401 permitted by applicable law.
990 11:23:17.594029 Unable to match end of the kernel message
992 11:23:17.595103 Setting prompt string to ['/ #']
993 11:23:17.595534 end: 2.4.4.1 login-action (duration 00:00:47) [common]
995 11:23:17.596637 end: 2.4.4 auto-login-action (duration 00:00:48) [common]
996 11:23:17.597100 start: 2.4.5 expect-shell-connection (timeout 00:03:24) [common]
997 11:23:17.597477 Setting prompt string to ['/ #']
998 11:23:17.597755 Forcing a shell prompt, looking for ['/ #']
1000 11:23:17.648328 / #
1001 11:23:17.648721 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
1002 11:23:17.648994 Waiting using forced prompt support (timeout 00:02:30)
1003 11:23:17.653126
1004 11:23:17.659386 end: 2.4.5 expect-shell-connection (duration 00:00:00) [common]
1005 11:23:17.659721 start: 2.4.6 export-device-env (timeout 00:03:24) [common]
1006 11:23:17.659989 Sending with 10 millisecond of delay
1008 11:23:22.708590 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/1219295/extract-nfsrootfs-k_16rdse'
1009 11:23:22.719212 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/1219295/extract-nfsrootfs-k_16rdse'
1010 11:23:22.720033 Sending with 10 millisecond of delay
1012 11:23:24.878360 / # export NFS_SERVER_IP='192.168.11.5'
1013 11:23:24.888962 export NFS_SERVER_IP='192.168.11.5'
1014 11:23:24.889738 end: 2.4.6 export-device-env (duration 00:00:07) [common]
1015 11:23:24.890062 end: 2.4 uboot-commands (duration 00:01:43) [common]
1016 11:23:24.890370 end: 2 uboot-action (duration 00:01:44) [common]
1017 11:23:24.890687 start: 3 lava-test-retry (timeout 00:07:13) [common]
1018 11:23:24.890998 start: 3.1 lava-test-shell (timeout 00:07:13) [common]
1019 11:23:24.891260 Using namespace: common
1021 11:23:24.991993 / # #
1022 11:23:24.992376 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
1023 11:23:24.996834 #
1024 11:23:25.003265 Using /lava-1219295
1026 11:23:25.104012 / # export SHELL=/bin/bash
1027 11:23:25.108770 export SHELL=/bin/bash
1029 11:23:25.216132 / # . /lava-1219295/environment
1030 11:23:25.220882 . /lava-1219295/environment
1032 11:23:25.334259 / # /lava-1219295/bin/lava-test-runner /lava-1219295/0
1033 11:23:25.334640 Test shell timeout: 10s (minimum of the action and connection timeout)
1034 11:23:25.338962 /lava-1219295/bin/lava-test-runner /lava-1219295/0
1035 11:23:25.775750 + export TESTRUN_ID=0_timesync-off
1036 11:23:25.783744 + TESTRUN_ID=0_timesync-off
1037 11:23:25.783996 + cd /lava-1219295/0/tests/0_timesync-off
1038 11:23:25.784223 ++ cat uuid
1039 11:23:25.801076 + UUID=1219295_1.6.2.4.1
1040 11:23:25.801383 + set +x
1041 11:23:25.806689 <LAVA_SIGNAL_STARTRUN 0_timesync-off 1219295_1.6.2.4.1>
1042 11:23:25.807200 Received signal: <STARTRUN> 0_timesync-off 1219295_1.6.2.4.1
1043 11:23:25.807448 Starting test lava.0_timesync-off (1219295_1.6.2.4.1)
1044 11:23:25.807732 Skipping test definition patterns.
1045 11:23:25.809889 + systemctl stop systemd-timesyncd
1046 11:23:26.107705 + set +x
1047 11:23:26.108211 Received signal: <ENDRUN> 0_timesync-off 1219295_1.6.2.4.1
1048 11:23:26.108500 Ending use of test pattern.
1049 11:23:26.108745 Ending test lava.0_timesync-off (1219295_1.6.2.4.1), duration 0.30
1051 11:23:26.110874 <LAVA_SIGNAL_ENDRUN 0_timesync-off 1219295_1.6.2.4.1>
1052 11:23:26.290203 + export TESTRUN_ID=1_kselftest-dt
1053 11:23:26.298243 + TESTRUN_ID=1_kselftest-dt
1054 11:23:26.298483 + cd /lava-1219295/0/tests/1_kselftest-dt
1055 11:23:26.298707 ++ cat uuid
1056 11:23:26.329212 + UUID=1219295_1.6.2.4.5
1057 11:23:26.329514 + set +x
1058 11:23:26.334807 <LAVA_SIGNAL_STARTRUN 1_kselftest-dt 1219295_1.6.2.4.5>
1059 11:23:26.335061 + cd ./automated/linux/kselftest/
1060 11:23:26.335526 Received signal: <STARTRUN> 1_kselftest-dt 1219295_1.6.2.4.5
1061 11:23:26.335790 Starting test lava.1_kselftest-dt (1219295_1.6.2.4.5)
1062 11:23:26.336082 Skipping test definition patterns.
1063 11:23:26.361190 + ./kselftest.sh -c dt -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/next/master/next-20241108/arm/multi_v7_defconfig/clang-17/kselftest.tar.xz -L '' -S /dev/null -b beaglebone-black -g next -e '' -p /opt/kselftests/mainline/ -n 1 -i 1 -E ''
1064 11:23:26.508498 INFO: install_deps skipped
1065 11:23:27.128067 --2024-11-08 11:23:27-- http://storage.kernelci.org/next/master/next-20241108/arm/multi_v7_defconfig/clang-17/kselftest.tar.xz
1066 11:23:27.143310 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
1067 11:23:27.257741 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
1068 11:23:27.369679 HTTP request sent, awaiting response... 200 OK
1069 11:23:27.370013 Length: 2739884 (2.6M) [application/octet-stream]
1070 11:23:27.375158 Saving to: 'kselftest_armhf.tar.gz'
1071 11:23:27.375448
1072 11:23:28.720683 kselftest_armhf.tar 0%[ ] 0 --.-KB/s kselftest_armhf.tar 1%[ ] 49.92K 218KB/s kselftest_armhf.tar 8%[> ] 218.67K 483KB/s kselftest_armhf.tar 16%[==> ] 430.04K 636KB/s kselftest_armhf.tar 49%[========> ] 1.29M 1.45MB/s kselftest_armhf.tar 72%[=============> ] 1.90M 1.71MB/s kselftest_armhf.tar 97%[==================> ] 2.55M 1.91MB/s kselftest_armhf.tar 100%[===================>] 2.61M 1.94MB/s in 1.3s
1073 11:23:28.721067
1074 11:23:29.103158 2024-11-08 11:23:28 (1.94 MB/s) - 'kselftest_armhf.tar.gz' saved [2739884/2739884]
1075 11:23:29.103542
1076 11:23:54.689380 skiplist:
1077 11:23:54.689744 ========================================
1078 11:23:54.695096 ========================================
1079 11:23:54.805388 dt:test_unprobed_devices.sh
1080 11:23:54.839809 ============== Tests to run ===============
1081 11:23:54.847563 dt:test_unprobed_devices.sh
1082 11:23:54.851469 ===========End Tests to run ===============
1083 11:23:54.861605 shardfile-dt pass
1084 11:23:55.099234 <12>[ 84.517471] kselftest: Running tests in dt
1085 11:23:55.128525 TAP version 13
1086 11:23:55.153629 1..1
1087 11:23:55.209794 # timeout set to 45
1088 11:23:55.210072 # selftests: dt: test_unprobed_devices.sh
1089 11:23:56.037833 # TAP version 13
1090 11:24:21.654060 # 1..257
1091 11:24:21.859477 # ok 1 / # SKIP
1092 11:24:21.887261 # ok 2 /clk_mcasp0
1093 11:24:21.955139 # ok 3 /clk_mcasp0_fixed # SKIP
1094 11:24:22.027515 # ok 4 /cpus/cpu@0 # SKIP
1095 11:24:22.103130 # ok 5 /cpus/idle-states/mpu_gate # SKIP
1096 11:24:22.123133 # ok 6 /fixedregulator0
1097 11:24:22.148518 # ok 7 /leds
1098 11:24:22.165139 # ok 8 /ocp
1099 11:24:22.189412 # ok 9 /ocp/interconnect@44c00000
1100 11:24:22.214392 # ok 10 /ocp/interconnect@44c00000/segment@0
1101 11:24:22.241754 # ok 11 /ocp/interconnect@44c00000/segment@100000
1102 11:24:22.265295 # ok 12 /ocp/interconnect@44c00000/segment@100000/target-module@0
1103 11:24:22.335717 # not ok 13 /ocp/interconnect@44c00000/segment@100000/target-module@0/cpu@0
1104 11:24:22.356731 # ok 14 /ocp/interconnect@44c00000/segment@200000
1105 11:24:22.385243 # ok 15 /ocp/interconnect@44c00000/segment@200000/target-module@0
1106 11:24:22.490838 # not ok 16 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0
1107 11:24:22.565881 # ok 17 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0 # SKIP
1108 11:24:22.641213 # ok 18 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@0 # SKIP
1109 11:24:22.715719 # ok 19 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@120 # SKIP
1110 11:24:22.790600 # ok 20 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@14c # SKIP
1111 11:24:22.863700 # ok 21 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@18 # SKIP
1112 11:24:22.940381 # ok 22 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@1c # SKIP
1113 11:24:23.011698 # ok 23 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@24 # SKIP
1114 11:24:23.086693 # ok 24 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@38 # SKIP
1115 11:24:23.161315 # ok 25 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@e8 # SKIP
1116 11:24:23.233937 # ok 26 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400 # SKIP
1117 11:24:23.308868 # ok 27 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@0 # SKIP
1118 11:24:23.382949 # ok 28 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@14 # SKIP
1119 11:24:23.456819 # ok 29 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@b0 # SKIP
1120 11:24:23.531933 # ok 30 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600 # SKIP
1121 11:24:23.606779 # ok 31 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600/clock@0 # SKIP
1122 11:24:23.681063 # ok 32 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800 # SKIP
1123 11:24:23.756425 # ok 33 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800/clock@0 # SKIP
1124 11:24:23.830787 # ok 34 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900 # SKIP
1125 11:24:23.906151 # ok 35 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900/clock@0 # SKIP
1126 11:24:23.984065 # ok 36 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00 # SKIP
1127 11:24:24.054647 # ok 37 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00/clock@0 # SKIP
1128 11:24:24.134194 # ok 38 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-24mhz # SKIP
1129 11:24:24.208350 # ok 39 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-32768 # SKIP
1130 11:24:24.284320 # ok 40 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-rc32k # SKIP
1131 11:24:24.358456 # ok 41 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clkdiv32k # SKIP
1132 11:24:24.435335 # ok 42 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-125mhz-gclk # SKIP
1133 11:24:24.509023 # ok 43 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-cpts-rft@520 # SKIP
1134 11:24:24.581797 # ok 44 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4-div2 # SKIP
1135 11:24:24.655805 # ok 45 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4@480 # SKIP
1136 11:24:24.734983 # ok 46 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m5@484 # SKIP
1137 11:24:24.809016 # ok 47 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m6@4d8 # SKIP
1138 11:24:24.881379 # ok 48 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-x2 # SKIP
1139 11:24:24.956129 # ok 49 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2-div2 # SKIP
1140 11:24:25.030960 # ok 50 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2@4a0 # SKIP
1141 11:24:25.105860 # ok 51 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-disp-m2@4a4 # SKIP
1142 11:24:25.185065 # ok 52 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-mpu-m2@4a8 # SKIP
1143 11:24:25.258846 # ok 53 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4 # SKIP
1144 11:24:25.331940 # ok 54 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4-wkupdm # SKIP
1145 11:24:25.406315 # ok 55 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2@4ac # SKIP
1146 11:24:25.481628 # ok 56 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-gpio0-dbclk-mux@53c # SKIP
1147 11:24:25.556119 # ok 57 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-ieee5000-fck-1@e4 # SKIP
1148 11:24:25.631860 # ok 58 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3-gclk # SKIP
1149 11:24:25.705926 # ok 59 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3s-gclk # SKIP
1150 11:24:25.784483 # ok 60 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4-rtc-gclk # SKIP
1151 11:24:25.860108 # ok 61 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4fw-gclk # SKIP
1152 11:24:25.933135 # ok 62 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4hs-gclk # SKIP
1153 11:24:26.006358 # ok 63 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4ls-gclk # SKIP
1154 11:24:26.080856 # ok 64 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-lcd-gclk@534 # SKIP
1155 11:24:26.153601 # ok 65 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmc # SKIP
1156 11:24:26.229790 # ok 66 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmu-fck-1@914 # SKIP
1157 11:24:26.302725 # ok 67 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-pruss-ocp-gclk@530 # SKIP
1158 11:24:26.376603 # ok 68 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-sysclk-div # SKIP
1159 11:24:26.449310 # ok 69 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-tclkin # SKIP
1160 11:24:26.524821 # ok 70 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer1-fck@528 # SKIP
1161 11:24:26.602835 # ok 71 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer2-fck@508 # SKIP
1162 11:24:26.673802 # ok 72 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer3-fck@50c # SKIP
1163 11:24:26.747996 # ok 73 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer4-fck@510 # SKIP
1164 11:24:26.823355 # ok 74 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer5-fck@518 # SKIP
1165 11:24:26.897146 # ok 75 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer6-fck@51c # SKIP
1166 11:24:26.972329 # ok 76 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer7-fck@504 # SKIP
1167 11:24:27.046120 # ok 77 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-usbotg-fck-8@47c # SKIP
1168 11:24:27.120275 # ok 78 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-19200000 # SKIP
1169 11:24:27.198546 # ok 79 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-24000000 # SKIP
1170 11:24:27.269841 # ok 80 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-25000000 # SKIP
1171 11:24:27.344440 # ok 81 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-26000000 # SKIP
1172 11:24:27.422440 # ok 82 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-wdt1-fck@538 # SKIP
1173 11:24:27.493938 # ok 83 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@488 # SKIP
1174 11:24:27.568895 # ok 84 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@48c # SKIP
1175 11:24:27.643813 # ok 85 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@490 # SKIP
1176 11:24:27.723562 # ok 86 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@494 # SKIP
1177 11:24:27.797714 # ok 87 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@498 # SKIP
1178 11:24:27.869346 # ok 88 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c # SKIP
1179 11:24:27.944323 # ok 89 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fck-div@0 # SKIP
1180 11:24:28.018521 # ok 90 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fclk-clksel@1 # SKIP
1181 11:24:28.091297 # ok 91 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700 # SKIP
1182 11:24:28.167296 # ok 92 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2-div@3 # SKIP
1183 11:24:28.241531 # ok 93 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2@7 # SKIP
1184 11:24:28.316546 # ok 94 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-sysclkout-pre@0 # SKIP
1185 11:24:28.338160 # ok 95 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1000
1186 11:24:28.366282 # ok 96 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1100
1187 11:24:28.391479 # ok 97 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1200
1188 11:24:28.411981 # ok 98 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@c00
1189 11:24:28.440612 # ok 99 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@d00
1190 11:24:28.461141 # ok 100 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@e00
1191 11:24:28.485160 # ok 101 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@f00
1192 11:24:28.508609 # ok 102 /ocp/interconnect@44c00000/segment@200000/target-module@10000
1193 11:24:28.620274 # not ok 103 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0
1194 11:24:28.646844 # ok 104 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/control@620
1195 11:24:28.670599 # ok 105 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/dma-router@f90
1196 11:24:28.694476 # ok 106 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800
1197 11:24:28.805041 # not ok 107 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0
1198 11:24:28.882634 # ok 108 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-adc-tsc-fck # SKIP
1199 11:24:28.957699 # ok 109 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-aes0-fck # SKIP
1200 11:24:29.032366 # ok 110 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan0-fck # SKIP
1201 11:24:29.106200 # ok 111 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan1-fck # SKIP
1202 11:24:29.180839 # ok 112 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp0-fck # SKIP
1203 11:24:29.255978 # ok 113 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp1-fck # SKIP
1204 11:24:29.334851 # ok 114 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-rng-fck # SKIP
1205 11:24:29.405944 # ok 115 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sha0-fck # SKIP
1206 11:24:29.481651 # ok 116 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex0-fck # SKIP
1207 11:24:29.556455 # ok 117 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex1-fck # SKIP
1208 11:24:29.631519 # ok 118 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sys-clkin-22@40 # SKIP
1209 11:24:29.704988 # ok 119 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664 # SKIP
1210 11:24:29.786954 # ok 120 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm0-tbclk@0 # SKIP
1211 11:24:29.860924 # ok 121 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm1-tbclk@1 # SKIP
1212 11:24:29.933920 # ok 122 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm2-tbclk@2 # SKIP
1213 11:24:29.955199 # ok 123 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/phy-gmii-sel
1214 11:24:30.030441 # not ok 124 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/wkup_m3_ipc@1324
1215 11:24:30.100225 # not ok 125 /ocp/interconnect@44c00000/segment@200000/target-module@31000
1216 11:24:30.176555 # ok 126 /ocp/interconnect@44c00000/segment@200000/target-module@31000/timer@0 # SKIP
1217 11:24:30.198251 # ok 127 /ocp/interconnect@44c00000/segment@200000/target-module@35000
1218 11:24:30.271933 # not ok 128 /ocp/interconnect@44c00000/segment@200000/target-module@35000/wdt@0
1219 11:24:30.298517 # ok 129 /ocp/interconnect@44c00000/segment@200000/target-module@3e000
1220 11:24:30.369076 # not ok 130 /ocp/interconnect@44c00000/segment@200000/target-module@3e000/rtc@0
1221 11:24:30.392173 # ok 131 /ocp/interconnect@44c00000/segment@200000/target-module@7000
1222 11:24:30.421900 # ok 132 /ocp/interconnect@44c00000/segment@200000/target-module@7000/gpio@0
1223 11:24:30.445208 # ok 133 /ocp/interconnect@44c00000/segment@200000/target-module@9000
1224 11:24:30.471073 # ok 134 /ocp/interconnect@44c00000/segment@200000/target-module@9000/serial@0
1225 11:24:30.494199 # ok 135 /ocp/interconnect@44c00000/segment@200000/target-module@b000
1226 11:24:30.515669 # ok 136 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0
1227 11:24:30.545035 # ok 137 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/eeprom@50
1228 11:24:30.622429 # ok 138 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/eeprom@50/nvmem-layout # SKIP
1229 11:24:30.645656 # ok 139 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
1230 11:24:30.666296 # ok 140 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24
1231 11:24:30.745178 # not ok 141 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/charger
1232 11:24:30.817652 # not ok 142 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/pwrbutton
1233 11:24:30.838364 # ok 143 /ocp/interconnect@44c00000/segment@200000/target-module@d000
1234 11:24:30.948791 # not ok 144 /ocp/interconnect@47c00000
1235 11:24:31.018445 # not ok 145 /ocp/interconnect@47c00000/segment@0
1236 11:24:31.042279 # ok 146 /ocp/interconnect@48000000
1237 11:24:31.065410 # ok 147 /ocp/interconnect@48000000/segment@0
1238 11:24:31.094845 # ok 148 /ocp/interconnect@48000000/segment@0/target-module@22000
1239 11:24:31.114782 # ok 149 /ocp/interconnect@48000000/segment@0/target-module@24000
1240 11:24:31.142159 # ok 150 /ocp/interconnect@48000000/segment@0/target-module@2a000
1241 11:24:31.164784 # ok 151 /ocp/interconnect@48000000/segment@0/target-module@30000
1242 11:24:31.188076 # ok 152 /ocp/interconnect@48000000/segment@0/target-module@38000
1243 11:24:31.210510 # ok 153 /ocp/interconnect@48000000/segment@0/target-module@38000/mcasp@0
1244 11:24:31.234933 # ok 154 /ocp/interconnect@48000000/segment@0/target-module@3c000
1245 11:24:31.308661 # not ok 155 /ocp/interconnect@48000000/segment@0/target-module@40000
1246 11:24:31.384039 # ok 156 /ocp/interconnect@48000000/segment@0/target-module@40000/timer@0 # SKIP
1247 11:24:31.406769 # ok 157 /ocp/interconnect@48000000/segment@0/target-module@42000
1248 11:24:31.435520 # ok 158 /ocp/interconnect@48000000/segment@0/target-module@42000/timer@0
1249 11:24:31.460441 # ok 159 /ocp/interconnect@48000000/segment@0/target-module@44000
1250 11:24:31.480148 # ok 160 /ocp/interconnect@48000000/segment@0/target-module@44000/timer@0
1251 11:24:31.503192 # ok 161 /ocp/interconnect@48000000/segment@0/target-module@46000
1252 11:24:31.532520 # ok 162 /ocp/interconnect@48000000/segment@0/target-module@46000/timer@0
1253 11:24:31.554874 # ok 163 /ocp/interconnect@48000000/segment@0/target-module@48000
1254 11:24:31.576418 # ok 164 /ocp/interconnect@48000000/segment@0/target-module@48000/timer@0
1255 11:24:31.599709 # ok 165 /ocp/interconnect@48000000/segment@0/target-module@4a000
1256 11:24:31.624232 # ok 166 /ocp/interconnect@48000000/segment@0/target-module@4a000/timer@0
1257 11:24:31.647652 # ok 167 /ocp/interconnect@48000000/segment@0/target-module@4c000
1258 11:24:31.672301 # ok 168 /ocp/interconnect@48000000/segment@0/target-module@4c000/gpio@0
1259 11:24:31.695661 # ok 169 /ocp/interconnect@48000000/segment@0/target-module@60000
1260 11:24:31.724819 # ok 170 /ocp/interconnect@48000000/segment@0/target-module@60000/mmc@0
1261 11:24:31.744775 # ok 171 /ocp/interconnect@48000000/segment@0/target-module@c8000
1262 11:24:31.773384 # ok 172 /ocp/interconnect@48000000/segment@0/target-module@c8000/mailbox@0
1263 11:24:31.794814 # ok 173 /ocp/interconnect@48000000/segment@0/target-module@ca000
1264 11:24:31.821391 # ok 174 /ocp/interconnect@48000000/segment@0/target-module@ca000/spinlock@0
1265 11:24:31.839015 # ok 175 /ocp/interconnect@48000000/segment@100000
1266 11:24:31.865244 # ok 176 /ocp/interconnect@48000000/segment@100000/target-module@9c000
1267 11:24:31.893642 # ok 177 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0
1268 11:24:31.966983 # not ok 178 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/eeprom@54
1269 11:24:32.040907 # ok 179 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/eeprom@54/nvmem-layout # SKIP
1270 11:24:32.113494 # not ok 180 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/eeprom@55
1271 11:24:32.194756 # ok 181 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/eeprom@55/nvmem-layout # SKIP
1272 11:24:32.266878 # not ok 182 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/eeprom@56
1273 11:24:32.339620 # ok 183 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/eeprom@56/nvmem-layout # SKIP
1274 11:24:32.412988 # not ok 184 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/eeprom@57
1275 11:24:32.490151 # ok 185 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/eeprom@57/nvmem-layout # SKIP
1276 11:24:32.511028 # ok 186 /ocp/interconnect@48000000/segment@100000/target-module@a0000
1277 11:24:32.537073 # ok 187 /ocp/interconnect@48000000/segment@100000/target-module@a6000
1278 11:24:32.558679 # ok 188 /ocp/interconnect@48000000/segment@100000/target-module@a8000
1279 11:24:32.583419 # ok 189 /ocp/interconnect@48000000/segment@100000/target-module@aa000
1280 11:24:32.607608 # ok 190 /ocp/interconnect@48000000/segment@100000/target-module@ac000
1281 11:24:32.632120 # ok 191 /ocp/interconnect@48000000/segment@100000/target-module@ac000/gpio@0
1282 11:24:32.660988 # ok 192 /ocp/interconnect@48000000/segment@100000/target-module@ae000
1283 11:24:32.680823 # ok 193 /ocp/interconnect@48000000/segment@100000/target-module@ae000/gpio@0
1284 11:24:32.703720 # ok 194 /ocp/interconnect@48000000/segment@100000/target-module@cc000
1285 11:24:32.728410 # ok 195 /ocp/interconnect@48000000/segment@100000/target-module@d0000
1286 11:24:32.755251 # ok 196 /ocp/interconnect@48000000/segment@100000/target-module@d8000
1287 11:24:32.777522 # ok 197 /ocp/interconnect@48000000/segment@100000/target-module@d8000/mmc@0
1288 11:24:32.799013 # ok 198 /ocp/interconnect@48000000/segment@200000
1289 11:24:32.825044 # ok 199 /ocp/interconnect@48000000/segment@200000/target-module@0
1290 11:24:32.905083 # ok 200 /ocp/interconnect@48000000/segment@200000/target-module@0/mpu@0 # SKIP
1291 11:24:32.923438 # ok 201 /ocp/interconnect@48000000/segment@300000
1292 11:24:32.947090 # ok 202 /ocp/interconnect@48000000/segment@300000/target-module@0
1293 11:24:32.970940 # ok 203 /ocp/interconnect@48000000/segment@300000/target-module@10000
1294 11:24:33.002587 # ok 204 /ocp/interconnect@48000000/segment@300000/target-module@10000/rng@0
1295 11:24:33.019310 # ok 205 /ocp/interconnect@48000000/segment@300000/target-module@2000
1296 11:24:33.043786 # ok 206 /ocp/interconnect@48000000/segment@300000/target-module@4000
1297 11:24:33.072595 # ok 207 /ocp/interconnect@48000000/segment@300000/target-module@e000
1298 11:24:33.146143 # not ok 208 /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
1299 11:24:33.167749 # ok 209 /ocp/interconnect@4a000000
1300 11:24:33.192103 # ok 210 /ocp/interconnect@4a000000/segment@0
1301 11:24:33.213055 # ok 211 /ocp/interconnect@4a000000/segment@0/target-module@100000
1302 11:24:33.242418 # ok 212 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0
1303 11:24:33.266405 # ok 213 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0/mdio@1000
1304 11:24:33.289989 # ok 214 /ocp/interconnect@4a000000/segment@0/target-module@300000
1305 11:24:33.363491 # not ok 215 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0
1306 11:24:33.473578 # ok 216 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/cfg@26000 # SKIP
1307 11:24:33.548051 # not ok 217 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/interrupt-controller@20000
1308 11:24:33.657779 # ok 218 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/mii-rt@32000 # SKIP
1309 11:24:33.728638 # not ok 219 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@34000
1310 11:24:33.806669 # not ok 220 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@38000
1311 11:24:33.905635 # not ok 221 /ocp/interconnect@4b140000
1312 11:24:33.979985 # not ok 222 /ocp/interconnect@4b140000/segment@0
1313 11:24:34.054368 # ok 223 /ocp/interrupt-controller@48200000 # SKIP
1314 11:24:34.080411 # ok 224 /ocp/target-module@40300000
1315 11:24:34.102869 # ok 225 /ocp/target-module@40300000/sram@0
1316 11:24:34.176885 # ok 226 /ocp/target-module@40300000/sram@0/pm-code-sram@0 # SKIP
1317 11:24:34.251371 # ok 227 /ocp/target-module@40300000/sram@0/pm-data-sram@1000 # SKIP
1318 11:24:34.271944 # ok 228 /ocp/target-module@47400000
1319 11:24:34.297337 # ok 229 /ocp/target-module@47400000/dma-controller@2000
1320 11:24:34.323333 # ok 230 /ocp/target-module@47400000/usb-phy@1300
1321 11:24:34.348096 # ok 231 /ocp/target-module@47400000/usb-phy@1b00
1322 11:24:34.371534 # ok 232 /ocp/target-module@47400000/usb@1400
1323 11:24:34.393057 # ok 233 /ocp/target-module@47400000/usb@1800
1324 11:24:34.417597 # ok 234 /ocp/target-module@47810000
1325 11:24:34.441168 # ok 235 /ocp/target-module@49000000
1326 11:24:34.460448 # ok 236 /ocp/target-module@49000000/dma@0
1327 11:24:34.482505 # ok 237 /ocp/target-module@49800000
1328 11:24:34.510898 # ok 238 /ocp/target-module@49800000/dma@0
1329 11:24:34.529091 # ok 239 /ocp/target-module@49900000
1330 11:24:34.553286 # ok 240 /ocp/target-module@49900000/dma@0
1331 11:24:34.580081 # ok 241 /ocp/target-module@49a00000
1332 11:24:34.598700 # ok 242 /ocp/target-module@49a00000/dma@0
1333 11:24:34.626694 # ok 243 /ocp/target-module@4c000000
1334 11:24:34.701514 # not ok 244 /ocp/target-module@4c000000/emif@0
1335 11:24:34.722118 # ok 245 /ocp/target-module@50000000
1336 11:24:34.742691 # ok 246 /ocp/target-module@53100000
1337 11:24:34.817403 # not ok 247 /ocp/target-module@53100000/sham@0
1338 11:24:34.839350 # ok 248 /ocp/target-module@53500000
1339 11:24:34.913406 # not ok 249 /ocp/target-module@53500000/aes@0
1340 11:24:34.940150 # ok 250 /ocp/target-module@56000000
1341 11:24:35.049522 # ok 251 /ocp/target-module@56000000/gpu@0 # SKIP
1342 11:24:35.121317 # ok 252 /opp-table # SKIP
1343 11:24:35.191034 # ok 253 /soc # SKIP
1344 11:24:35.217314 # ok 254 /sound
1345 11:24:35.242012 # ok 255 /target-module@4b000000
1346 11:24:35.262881 # ok 256 /target-module@4b000000/target-module@140000
1347 11:24:35.284998 # ok 257 /target-module@4b000000/target-module@140000/pmu@0
1348 11:24:35.296192 # # Totals: pass:117 fail:27 xfail:0 xpass:0 skip:113 error:0
1349 11:24:35.302796 not ok 1 selftests: dt: test_unprobed_devices.sh # exit=1
1350 11:24:37.451297 dt_test_unprobed_devices_sh_ skip
1351 11:24:37.456702 dt_test_unprobed_devices_sh_clk_mcasp0 pass
1352 11:24:37.462285 dt_test_unprobed_devices_sh_clk_mcasp0_fixed skip
1353 11:24:37.462520 dt_test_unprobed_devices_sh_cpus_cpu_0 skip
1354 11:24:37.468039 dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate skip
1355 11:24:37.473593 dt_test_unprobed_devices_sh_fixedregulator0 pass
1356 11:24:37.479167 dt_test_unprobed_devices_sh_leds pass
1357 11:24:37.479405 dt_test_unprobed_devices_sh_ocp pass
1358 11:24:37.484797 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 pass
1359 11:24:37.490451 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 pass
1360 11:24:37.496044 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 pass
1361 11:24:37.507170 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 pass
1362 11:24:37.512779 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 fail
1363 11:24:37.518395 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 pass
1364 11:24:37.529641 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 pass
1365 11:24:37.535286 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 fail
1366 11:24:37.546458 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 skip
1367 11:24:37.557677 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 skip
1368 11:24:37.569027 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 skip
1369 11:24:37.574525 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c skip
1370 11:24:37.585800 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 skip
1371 11:24:37.597022 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c skip
1372 11:24:37.608147 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 skip
1373 11:24:37.619339 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 skip
1374 11:24:37.624916 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 skip
1375 11:24:37.636185 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 skip
1376 11:24:37.647357 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 skip
1377 11:24:37.658587 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 skip
1378 11:24:37.669707 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 skip
1379 11:24:37.675330 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 skip
1380 11:24:37.686599 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 skip
1381 11:24:37.697835 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 skip
1382 11:24:37.709102 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 skip
1383 11:24:37.714607 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 skip
1384 11:24:37.725855 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 skip
1385 11:24:37.737083 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 skip
1386 11:24:37.748185 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 skip
1387 11:24:37.759432 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz skip
1388 11:24:37.765101 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 skip
1389 11:24:37.776226 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k skip
1390 11:24:37.787476 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k skip
1391 11:24:37.798602 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk skip
1392 11:24:37.809850 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 skip
1393 11:24:37.821108 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 skip
1394 11:24:37.832225 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 skip
1395 11:24:37.843476 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 skip
1396 11:24:37.854614 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 skip
1397 11:24:37.865848 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 skip
1398 11:24:37.877117 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 skip
1399 11:24:37.888224 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 skip
1400 11:24:37.899348 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 skip
1401 11:24:37.910614 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 skip
1402 11:24:37.921723 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 skip
1403 11:24:37.932987 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm skip
1404 11:24:37.944220 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac skip
1405 11:24:37.955346 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c skip
1406 11:24:37.966610 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 skip
1407 11:24:37.977719 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk skip
1408 11:24:37.988973 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk skip
1409 11:24:38.000098 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk skip
1410 11:24:38.011347 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk skip
1411 11:24:38.022468 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk skip
1412 11:24:38.033719 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk skip
1413 11:24:38.044981 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 skip
1414 11:24:38.050467 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc skip
1415 11:24:38.061718 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 skip
1416 11:24:38.072842 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 skip
1417 11:24:38.084093 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div skip
1418 11:24:38.095216 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin skip
1419 11:24:38.106465 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 skip
1420 11:24:38.117734 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 skip
1421 11:24:38.128841 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c skip
1422 11:24:38.140091 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 skip
1423 11:24:38.151216 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 skip
1424 11:24:38.162466 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c skip
1425 11:24:38.173600 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 skip
1426 11:24:38.184850 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c skip
1427 11:24:38.196087 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 skip
1428 11:24:38.207215 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 skip
1429 11:24:38.218367 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 skip
1430 11:24:38.229493 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 skip
1431 11:24:38.240745 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 skip
1432 11:24:38.246371 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 skip
1433 11:24:38.257594 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c skip
1434 11:24:38.268860 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 skip
1435 11:24:38.280099 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 skip
1436 11:24:38.291214 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 skip
1437 11:24:38.296739 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c skip
1438 11:24:38.313590 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 skip
1439 11:24:38.324721 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 skip
1440 11:24:38.330347 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 skip
1441 11:24:38.347210 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 skip
1442 11:24:38.358346 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 skip
1443 11:24:38.369477 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 skip
1444 11:24:38.375082 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 pass
1445 11:24:38.386355 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 pass
1446 11:24:38.397469 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 pass
1447 11:24:38.403081 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 pass
1448 11:24:38.414343 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 pass
1449 11:24:38.425453 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 pass
1450 11:24:38.431078 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 pass
1451 11:24:38.442327 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 pass
1452 11:24:38.447826 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 fail
1453 11:24:38.459075 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 pass
1454 11:24:38.470201 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 pass
1455 11:24:38.481439 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 pass
1456 11:24:38.492638 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 fail
1457 11:24:38.503769 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck skip
1458 11:24:38.515005 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck skip
1459 11:24:38.526157 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck skip
1460 11:24:38.537378 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck skip
1461 11:24:38.548503 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck skip
1462 11:24:38.559749 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck skip
1463 11:24:38.570999 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck skip
1464 11:24:38.582126 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck skip
1465 11:24:38.598998 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck skip
1466 11:24:38.610182 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck skip
1467 11:24:38.621435 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 skip
1468 11:24:38.632632 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 skip
1469 11:24:38.643750 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 skip
1470 11:24:38.660500 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 skip
1471 11:24:38.671747 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 skip
1472 11:24:38.682999 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel pass
1473 11:24:38.694125 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 fail
1474 11:24:38.699753 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 fail
1475 11:24:38.710996 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 skip
1476 11:24:38.722122 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 pass
1477 11:24:38.727751 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 fail
1478 11:24:38.738996 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 pass
1479 11:24:38.744562 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 fail
1480 11:24:38.755749 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 pass
1481 11:24:38.761254 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 pass
1482 11:24:38.772496 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 pass
1483 11:24:38.778127 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 pass
1484 11:24:38.789248 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 pass
1485 11:24:38.795001 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 pass
1486 11:24:38.806122 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_eeprom_50 pass
1487 11:24:38.817244 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_eeprom_50_nvmem-layout skip
1488 11:24:38.828492 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 pass
1489 11:24:38.834126 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 pass
1490 11:24:38.845288 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger fail
1491 11:24:38.856488 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton fail
1492 11:24:38.862125 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 pass
1493 11:24:38.867621 dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 fail
1494 11:24:38.878865 dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 fail
1495 11:24:38.879142 dt_test_unprobed_devices_sh_ocp_interconnect_48000000 pass
1496 11:24:38.890116 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 pass
1497 11:24:38.895622 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 pass
1498 11:24:38.901247 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 pass
1499 11:24:38.912490 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 pass
1500 11:24:38.917997 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 pass
1501 11:24:38.929238 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 pass
1502 11:24:38.934869 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 pass
1503 11:24:38.946031 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 pass
1504 11:24:38.951609 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 fail
1505 11:24:38.957340 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 skip
1506 11:24:38.968381 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 pass
1507 11:24:38.973982 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 pass
1508 11:24:38.985317 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 pass
1509 11:24:38.990831 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 pass
1510 11:24:39.001977 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 pass
1511 11:24:39.007646 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 pass
1512 11:24:39.018740 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 pass
1513 11:24:39.024370 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 pass
1514 11:24:39.035510 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 pass
1515 11:24:39.041099 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 pass
1516 11:24:39.052344 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 pass
1517 11:24:39.057977 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 pass
1518 11:24:39.063497 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 pass
1519 11:24:39.074716 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 pass
1520 11:24:39.080349 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 pass
1521 11:24:39.091482 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 pass
1522 11:24:39.097191 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 pass
1523 11:24:39.108248 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 pass
1524 11:24:39.113976 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 pass
1525 11:24:39.125127 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 pass
1526 11:24:39.130743 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 pass
1527 11:24:39.141966 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_54 fail
1528 11:24:39.153184 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_54_nvmem-layout skip
1529 11:24:39.164220 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_55 fail
1530 11:24:39.175481 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_55_nvmem-layout skip
1531 11:24:39.181112 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_56 fail
1532 11:24:39.192271 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_56_nvmem-layout skip
1533 11:24:39.203495 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_57 fail
1534 11:24:39.214672 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_57_nvmem-layout skip
1535 11:24:39.220219 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 pass
1536 11:24:39.231468 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 pass
1537 11:24:39.236970 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 pass
1538 11:24:39.248213 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 pass
1539 11:24:39.253845 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 pass
1540 11:24:39.265027 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 pass
1541 11:24:39.270652 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 pass
1542 11:24:39.281775 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 pass
1543 11:24:39.287401 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 pass
1544 11:24:39.298651 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 pass
1545 11:24:39.304153 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 pass
1546 11:24:39.315398 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 pass
1547 11:24:39.321037 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 pass
1548 11:24:39.332097 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 pass
1549 11:24:39.337748 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 skip
1550 11:24:39.343393 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 pass
1551 11:24:39.354483 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 pass
1552 11:24:39.360125 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 pass
1553 11:24:39.371353 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 pass
1554 11:24:39.377007 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 pass
1555 11:24:39.388088 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 pass
1556 11:24:39.393719 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 pass
1557 11:24:39.404999 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 fail
1558 11:24:39.410467 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 pass
1559 11:24:39.416092 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 pass
1560 11:24:39.421719 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 pass
1561 11:24:39.432999 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 pass
1562 11:24:39.438500 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 pass
1563 11:24:39.449711 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 pass
1564 11:24:39.455216 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 fail
1565 11:24:39.466462 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 skip
1566 11:24:39.477586 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 fail
1567 11:24:39.488881 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 skip
1568 11:24:39.500109 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 fail
1569 11:24:39.505738 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 fail
1570 11:24:39.511268 dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 fail
1571 11:24:39.517148 dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 fail
1572 11:24:39.522712 dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 skip
1573 11:24:39.528210 dt_test_unprobed_devices_sh_ocp_target-module_40300000 pass
1574 11:24:39.534019 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 pass
1575 11:24:39.545126 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 skip
1576 11:24:39.550753 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 skip
1577 11:24:39.556211 dt_test_unprobed_devices_sh_ocp_target-module_47400000 pass
1578 11:24:39.561963 dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 pass
1579 11:24:39.567477 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 pass
1580 11:24:39.578744 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 pass
1581 11:24:39.584332 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 pass
1582 11:24:39.589978 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 pass
1583 11:24:39.595479 dt_test_unprobed_devices_sh_ocp_target-module_47810000 pass
1584 11:24:39.601136 dt_test_unprobed_devices_sh_ocp_target-module_49000000 pass
1585 11:24:39.606732 dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 pass
1586 11:24:39.612334 dt_test_unprobed_devices_sh_ocp_target-module_49800000 pass
1587 11:24:39.617999 dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 pass
1588 11:24:39.623652 dt_test_unprobed_devices_sh_ocp_target-module_49900000 pass
1589 11:24:39.629113 dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 pass
1590 11:24:39.634738 dt_test_unprobed_devices_sh_ocp_target-module_49a00000 pass
1591 11:24:39.640356 dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 pass
1592 11:24:39.645992 dt_test_unprobed_devices_sh_ocp_target-module_4c000000 pass
1593 11:24:39.651609 dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 fail
1594 11:24:39.657114 dt_test_unprobed_devices_sh_ocp_target-module_50000000 pass
1595 11:24:39.662711 dt_test_unprobed_devices_sh_ocp_target-module_53100000 pass
1596 11:24:39.668334 dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 fail
1597 11:24:39.673998 dt_test_unprobed_devices_sh_ocp_target-module_53500000 pass
1598 11:24:39.679621 dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 fail
1599 11:24:39.685210 dt_test_unprobed_devices_sh_ocp_target-module_56000000 pass
1600 11:24:39.690863 dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 skip
1601 11:24:39.691119 dt_test_unprobed_devices_sh_opp-table skip
1602 11:24:39.696456 dt_test_unprobed_devices_sh_soc skip
1603 11:24:39.702111 dt_test_unprobed_devices_sh_sound pass
1604 11:24:39.702365 dt_test_unprobed_devices_sh_target-module_4b000000 pass
1605 11:24:39.713222 dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 pass
1606 11:24:39.718835 dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 pass
1607 11:24:39.724458 dt_test_unprobed_devices_sh fail
1608 11:24:39.724687 + ../../utils/send-to-lava.sh ./output/result.txt
1609 11:24:39.732121 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-dt RESULT=pass>
1610 11:24:39.732703 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-dt RESULT=pass
1612 11:24:39.742441 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip>
1613 11:24:39.742930 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip
1615 11:24:39.845726 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass>
1616 11:24:39.846283 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass
1618 11:24:39.949228 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip>
1619 11:24:39.949717 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip
1621 11:24:40.049220 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip>
1622 11:24:40.049712 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip
1624 11:24:40.150169 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip>
1625 11:24:40.150651 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip
1627 11:24:40.250144 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass>
1628 11:24:40.250637 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass
1630 11:24:40.348648 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass>
1631 11:24:40.349142 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass
1633 11:24:40.448358 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass>
1634 11:24:40.448825 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass
1636 11:24:40.550134 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass>
1637 11:24:40.550617 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass
1639 11:24:40.651060 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass>
1640 11:24:40.651615 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass
1642 11:24:40.751764 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass>
1643 11:24:40.752296 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass
1645 11:24:40.855165 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass>
1646 11:24:40.855652 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass
1648 11:24:40.955110 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail>
1649 11:24:40.955591 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail
1651 11:24:41.054646 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass>
1652 11:24:41.055133 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass
1654 11:24:41.157642 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass>
1655 11:24:41.158125 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass
1657 11:24:41.263260 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail>
1658 11:24:41.263757 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail
1660 11:24:41.362965 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip>
1661 11:24:41.363449 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip
1663 11:24:41.464780 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip>
1664 11:24:41.465283 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip
1666 11:24:41.565717 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip>
1667 11:24:41.566213 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip
1669 11:24:41.665105 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip>
1670 11:24:41.665659 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip
1672 11:24:41.767213 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip>
1673 11:24:41.767765 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip
1675 11:24:41.867576 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip>
1676 11:24:41.868064 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip
1678 11:24:41.967706 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip>
1679 11:24:41.968197 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip
1681 11:24:42.067572 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip>
1682 11:24:42.068074 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip
1684 11:24:42.168083 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip>
1685 11:24:42.168572 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip
1687 11:24:42.271314 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip>
1688 11:24:42.271817 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip
1690 11:24:42.374184 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip>
1691 11:24:42.374693 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip
1693 11:24:42.475052 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip>
1694 11:24:42.475576 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip
1696 11:24:42.576568 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip>
1697 11:24:42.577100 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip
1699 11:24:42.677055 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip>
1700 11:24:42.677605 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip
1702 11:24:42.778073 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip>
1703 11:24:42.778622 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip
1705 11:24:42.876540 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip>
1706 11:24:42.877057 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip
1708 11:24:42.977694 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip>
1709 11:24:42.978178 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip
1711 11:24:43.076292 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip>
1712 11:24:43.076771 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip
1714 11:24:43.173651 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip>
1715 11:24:43.174148 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip
1717 11:24:43.276182 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip>
1718 11:24:43.276685 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip
1720 11:24:43.378643 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip>
1721 11:24:43.379137 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip
1723 11:24:43.478788 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip>
1724 11:24:43.479253 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip
1726 11:24:43.580274 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip>
1727 11:24:43.580775 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip
1729 11:24:43.684376 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip>
1730 11:24:43.684962 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip
1732 11:24:43.785539 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip>
1733 11:24:43.786090 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip
1735 11:24:43.886252 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip>
1736 11:24:43.886767 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip
1738 11:24:43.985873 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip>
1739 11:24:43.986364 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip
1741 11:24:44.089105 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip>
1742 11:24:44.089605 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip
1744 11:24:44.188860 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip>
1745 11:24:44.189367 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip
1747 11:24:44.288848 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip>
1748 11:24:44.289354 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip
1750 11:24:44.388846 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip>
1751 11:24:44.389348 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip
1753 11:24:44.490248 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip>
1754 11:24:44.490746 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip
1756 11:24:44.594891 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip>
1757 11:24:44.595393 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip
1759 11:24:44.695600 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip>
1760 11:24:44.696174 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip
1762 11:24:44.796456 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip>
1763 11:24:44.797034 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip
1765 11:24:44.900257 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip>
1766 11:24:44.900778 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip
1768 11:24:45.000350 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip>
1769 11:24:45.000850 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip
1771 11:24:45.099976 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip>
1772 11:24:45.100476 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip
1774 11:24:45.203123 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip>
1775 11:24:45.203624 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip
1777 11:24:45.306494 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip>
1778 11:24:45.307003 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip
1780 11:24:45.407108 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip>
1781 11:24:45.407630 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip
1783 11:24:45.506977 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip>
1784 11:24:45.507496 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip
1786 11:24:45.609101 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip>
1787 11:24:45.609604 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip
1789 11:24:45.712289 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip>
1790 11:24:45.712878 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip
1792 11:24:45.814680 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip>
1793 11:24:45.815238 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip
1795 11:24:45.915959 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip>
1796 11:24:45.916456 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip
1798 11:24:46.017211 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip>
1799 11:24:46.017706 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip
1801 11:24:46.119645 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip>
1802 11:24:46.120138 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip
1804 11:24:46.218552 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip>
1805 11:24:46.219037 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip
1807 11:24:46.317856 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip>
1808 11:24:46.318360 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip
1810 11:24:46.419357 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip>
1811 11:24:46.419872 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip
1813 11:24:46.521103 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip>
1814 11:24:46.521616 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip
1816 11:24:46.623842 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip>
1817 11:24:46.624390 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip
1819 11:24:46.724603 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip>
1820 11:24:46.725198 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip
1822 11:24:46.824349 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip>
1823 11:24:46.824908 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip
1825 11:24:46.922492 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip>
1826 11:24:46.923004 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip
1828 11:24:47.025448 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip>
1829 11:24:47.025939 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip
1831 11:24:47.126429 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip>
1832 11:24:47.126953 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip
1834 11:24:47.224522 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip>
1835 11:24:47.225145 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip
1837 11:24:47.325077 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip>
1838 11:24:47.325581 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip
1840 11:24:47.428999 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip>
1841 11:24:47.429507 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip
1843 11:24:47.527196 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip>
1844 11:24:47.527688 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip
1846 11:24:47.628187 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip>
1847 11:24:47.628747 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip
1849 11:24:47.728907 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip>
1850 11:24:47.729489 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip
1852 11:24:47.831781 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip>
1853 11:24:47.832324 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip
1855 11:24:47.934335 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip>
1856 11:24:47.934833 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip
1858 11:24:48.037369 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip>
1859 11:24:48.037871 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip
1861 11:24:48.140075 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip>
1862 11:24:48.140601 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip
1864 11:24:48.244085 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip>
1865 11:24:48.244620 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip
1867 11:24:48.345187 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip>
1868 11:24:48.345702 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip
1870 11:24:48.445261 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip>
1871 11:24:48.445750 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip
1873 11:24:48.547276 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip>
1874 11:24:48.547761 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip
1876 11:24:48.649115 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip>
1877 11:24:48.649719 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip
1879 11:24:48.749697 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip>
1880 11:24:48.750212 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip
1882 11:24:48.848902 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip>
1883 11:24:48.849501 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip
1885 11:24:48.951309 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip>
1886 11:24:48.951820 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip
1888 11:24:49.056239 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip>
1889 11:24:49.056765 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip
1891 11:24:49.159862 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip>
1892 11:24:49.160346 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip
1894 11:24:49.259478 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass>
1895 11:24:49.259963 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass
1897 11:24:49.364285 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass>
1898 11:24:49.364778 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass
1900 11:24:49.463478 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass>
1901 11:24:49.463981 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass
1903 11:24:49.561874 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass>
1904 11:24:49.562365 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass
1906 11:24:49.660111 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass>
1907 11:24:49.660673 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass
1909 11:24:49.759510 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass>
1910 11:24:49.760005 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass
1912 11:24:49.863013 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass>
1913 11:24:49.863565 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass
1915 11:24:49.961318 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass>
1916 11:24:49.961809 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass
1918 11:24:50.061306 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail>
1919 11:24:50.061794 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail
1921 11:24:50.160190 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass>
1922 11:24:50.160679 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass
1924 11:24:50.260476 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass>
1925 11:24:50.260993 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass
1927 11:24:50.362598 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass>
1928 11:24:50.363092 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass
1930 11:24:50.460231 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail>
1931 11:24:50.460731 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail
1933 11:24:50.558297 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip>
1934 11:24:50.558798 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip
1936 11:24:50.655607 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip>
1937 11:24:50.656179 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip
1939 11:24:50.754924 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip>
1940 11:24:50.755416 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip
1942 11:24:50.858025 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip>
1943 11:24:50.858575 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip
1945 11:24:50.957665 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip>
1946 11:24:50.958155 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip
1948 11:24:51.055605 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip>
1949 11:24:51.056086 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip
1951 11:24:51.157223 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip>
1952 11:24:51.157702 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip
1954 11:24:51.258653 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip>
1955 11:24:51.259141 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip
1957 11:24:51.360968 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip>
1958 11:24:51.361446 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip
1960 11:24:51.463642 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip>
1961 11:24:51.464132 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip
1963 11:24:51.567273 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip>
1964 11:24:51.567763 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip
1966 11:24:51.667637 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip>
1967 11:24:51.668193 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip
1969 11:24:51.766915 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip
1971 11:24:51.770006 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip>
1972 11:24:51.868535 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip
1974 11:24:51.871665 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip>
1975 11:24:51.967573 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip
1977 11:24:51.970688 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip>
1978 11:24:52.067276 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass>
1979 11:24:52.067787 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass
1981 11:24:52.170606 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail>
1982 11:24:52.171106 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail
1984 11:24:52.271604 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail>
1985 11:24:52.272140 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail
1987 11:24:52.373567 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip>
1988 11:24:52.374070 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip
1990 11:24:52.473128 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass>
1991 11:24:52.473620 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass
1993 11:24:52.575379 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail>
1994 11:24:52.575880 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail
1996 11:24:52.674863 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass>
1997 11:24:52.675418 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass
1999 11:24:52.775985 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail>
2000 11:24:52.776531 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail
2002 11:24:52.874862 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass>
2003 11:24:52.875409 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass
2005 11:24:52.975326 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass>
2006 11:24:52.975810 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass
2008 11:24:53.075828 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass>
2009 11:24:53.076322 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass
2011 11:24:53.175850 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass>
2012 11:24:53.176341 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass
2014 11:24:53.273218 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass>
2015 11:24:53.273768 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass
2017 11:24:53.372997 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass>
2018 11:24:53.373498 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass
2020 11:24:53.473717 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_eeprom_50 RESULT=pass>
2021 11:24:53.474222 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_eeprom_50 RESULT=pass
2023 11:24:53.575093 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_eeprom_50_nvmem-layout RESULT=skip>
2024 11:24:53.575592 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_eeprom_50_nvmem-layout RESULT=skip
2026 11:24:53.677092 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass>
2027 11:24:53.677650 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass
2029 11:24:53.776498 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass>
2030 11:24:53.777012 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass
2032 11:24:53.876843 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail>
2033 11:24:53.877431 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail
2035 11:24:53.980835 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail>
2036 11:24:53.981360 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail
2038 11:24:54.080732 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass>
2039 11:24:54.081224 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass
2041 11:24:54.179942 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail>
2042 11:24:54.180440 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail
2044 11:24:54.281967 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail>
2045 11:24:54.282463 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail
2047 11:24:54.382812 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass>
2048 11:24:54.383298 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass
2050 11:24:54.486975 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass>
2051 11:24:54.487463 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass
2053 11:24:54.591350 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass>
2054 11:24:54.591839 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass
2056 11:24:54.692326 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass>
2057 11:24:54.692884 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass
2059 11:24:54.795045 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass>
2060 11:24:54.795597 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass
2062 11:24:54.898534 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass>
2063 11:24:54.899107 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass
2065 11:24:54.999931 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass>
2066 11:24:55.000431 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass
2068 11:24:55.099573 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass>
2069 11:24:55.100073 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass
2071 11:24:55.197230 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass>
2072 11:24:55.197720 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass
2074 11:24:55.315598 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail>
2075 11:24:55.316091 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail
2077 11:24:55.422692 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip>
2078 11:24:55.423189 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip
2080 11:24:55.520464 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass>
2081 11:24:55.520968 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass
2083 11:24:55.618944 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass>
2084 11:24:55.619422 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass
2086 11:24:55.717019 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass>
2087 11:24:55.717569 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass
2089 11:24:55.817014 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass>
2090 11:24:55.817557 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass
2092 11:24:55.915191 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass>
2093 11:24:55.915671 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass
2095 11:24:56.013976 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass>
2096 11:24:56.014455 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass
2098 11:24:56.114926 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass>
2099 11:24:56.115416 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass
2101 11:24:56.211718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass>
2102 11:24:56.212197 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass
2104 11:24:56.309747 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass>
2105 11:24:56.310224 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass
2107 11:24:56.411088 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass>
2108 11:24:56.411571 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass
2110 11:24:56.510935 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass>
2111 11:24:56.511442 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass
2113 11:24:56.612133 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass>
2114 11:24:56.612641 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass
2116 11:24:56.712806 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass>
2117 11:24:56.713361 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass
2119 11:24:56.812952 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass>
2120 11:24:56.813489 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass
2122 11:24:56.910618 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass>
2123 11:24:56.911102 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass
2125 11:24:57.012085 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass>
2126 11:24:57.012564 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass
2128 11:24:57.108929 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass>
2129 11:24:57.109411 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass
2131 11:24:57.212551 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass>
2132 11:24:57.213061 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass
2134 11:24:57.310924 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass>
2135 11:24:57.311406 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass
2137 11:24:57.412222 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass>
2138 11:24:57.412726 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass
2140 11:24:57.512796 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass>
2141 11:24:57.513288 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass
2143 11:24:57.613660 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_54 RESULT=fail>
2144 11:24:57.614141 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_54 RESULT=fail
2146 11:24:57.716459 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_54_nvmem-layout RESULT=skip>
2147 11:24:57.717037 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_54_nvmem-layout RESULT=skip
2149 11:24:57.814009 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_55 RESULT=fail>
2150 11:24:57.814542 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_55 RESULT=fail
2152 11:24:57.915067 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_55_nvmem-layout RESULT=skip>
2153 11:24:57.915555 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_55_nvmem-layout RESULT=skip
2155 11:24:58.014108 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_56 RESULT=fail>
2156 11:24:58.014599 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_56 RESULT=fail
2158 11:24:58.115435 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_56_nvmem-layout RESULT=skip>
2159 11:24:58.115940 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_56_nvmem-layout RESULT=skip
2161 11:24:58.217234 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_57 RESULT=fail>
2162 11:24:58.217757 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_57 RESULT=fail
2164 11:24:58.316110 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_57_nvmem-layout RESULT=skip>
2165 11:24:58.316603 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_57_nvmem-layout RESULT=skip
2167 11:24:58.411617 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass>
2168 11:24:58.412099 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass
2170 11:24:58.512110 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass>
2171 11:24:58.512584 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass
2173 11:24:58.611849 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass>
2174 11:24:58.612330 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass
2176 11:24:58.711574 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass>
2177 11:24:58.711954 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass
2179 11:24:58.812002 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass>
2180 11:24:58.812543 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass
2182 11:24:58.915596 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass>
2183 11:24:58.916082 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass
2185 11:24:59.013315 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass>
2186 11:24:59.013804 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass
2188 11:24:59.113129 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass>
2189 11:24:59.113623 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass
2191 11:24:59.214297 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass>
2192 11:24:59.214789 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass
2194 11:24:59.316659 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass>
2195 11:24:59.317166 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass
2197 11:24:59.417370 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass>
2198 11:24:59.417862 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass
2200 11:24:59.523308 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass>
2201 11:24:59.523804 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass
2203 11:24:59.622085 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass>
2204 11:24:59.622577 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass
2206 11:24:59.720769 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass>
2207 11:24:59.721325 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass
2209 11:24:59.818497 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip>
2210 11:24:59.819054 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip
2212 11:24:59.919761 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass>
2213 11:24:59.920269 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass
2215 11:25:00.024258 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass>
2216 11:25:00.024777 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass
2218 11:25:00.126835 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass>
2219 11:25:00.127327 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass
2221 11:25:00.231279 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass>
2222 11:25:00.231759 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass
2224 11:25:00.332275 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass>
2225 11:25:00.332771 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass
2227 11:25:00.431831 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass>
2228 11:25:00.432313 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass
2230 11:25:00.531799 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass>
2231 11:25:00.532276 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass
2233 11:25:00.631793 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail>
2234 11:25:00.632280 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail
2236 11:25:00.728015 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass>
2237 11:25:00.728558 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass
2239 11:25:00.828272 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass>
2240 11:25:00.828779 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass
2242 11:25:00.930861 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass>
2243 11:25:00.931349 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass
2245 11:25:01.033027 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass>
2246 11:25:01.033510 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass
2248 11:25:01.133320 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass>
2249 11:25:01.133859 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass
2251 11:25:01.233066 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass>
2252 11:25:01.233590 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass
2254 11:25:01.333705 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail>
2255 11:25:01.334221 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail
2257 11:25:01.436389 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip>
2258 11:25:01.436880 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip
2260 11:25:01.541338 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail>
2261 11:25:01.541852 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail
2263 11:25:01.642643 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip>
2264 11:25:01.643153 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip
2266 11:25:01.743517 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail>
2267 11:25:01.744099 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail
2269 11:25:01.844414 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail>
2270 11:25:01.845001 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail
2272 11:25:01.939388 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail>
2273 11:25:01.939906 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail
2275 11:25:02.044775 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail>
2276 11:25:02.045263 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail
2278 11:25:02.142753 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip>
2279 11:25:02.143242 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip
2281 11:25:02.243124 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass>
2282 11:25:02.243617 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass
2284 11:25:02.345626 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass>
2285 11:25:02.346141 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass
2287 11:25:02.451252 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip>
2288 11:25:02.451742 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip
2290 11:25:02.549245 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip
2292 11:25:02.552196 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip>
2293 11:25:02.647826 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass>
2294 11:25:02.648303 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass
2296 11:25:02.744221 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass>
2297 11:25:02.744762 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass
2299 11:25:02.840730 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass>
2300 11:25:02.841247 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass
2302 11:25:02.936473 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass>
2303 11:25:02.936959 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass
2305 11:25:03.032410 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass>
2306 11:25:03.032862 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass
2308 11:25:03.130097 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass>
2309 11:25:03.130584 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass
2311 11:25:03.229375 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass>
2312 11:25:03.229868 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass
2314 11:25:03.327227 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass>
2315 11:25:03.327716 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass
2317 11:25:03.423803 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass>
2318 11:25:03.424284 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass
2320 11:25:03.521600 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass>
2321 11:25:03.522087 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass
2323 11:25:03.622178 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass>
2324 11:25:03.622659 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass
2326 11:25:03.723524 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass>
2327 11:25:03.724083 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass
2329 11:25:03.823411 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass>
2330 11:25:03.823952 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass
2332 11:25:03.923413 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass>
2333 11:25:03.923901 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass
2335 11:25:04.021816 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass>
2336 11:25:04.022292 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass
2338 11:25:04.121480 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass>
2339 11:25:04.121963 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass
2341 11:25:04.222179 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail>
2342 11:25:04.222659 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail
2344 11:25:04.320571 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass>
2345 11:25:04.321078 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass
2347 11:25:04.418363 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass>
2348 11:25:04.418850 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass
2350 11:25:04.516554 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail>
2351 11:25:04.517123 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail
2353 11:25:04.613703 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass>
2354 11:25:04.614198 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass
2356 11:25:04.711051 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail>
2357 11:25:04.711607 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail
2359 11:25:04.808970 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass>
2360 11:25:04.809511 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass
2362 11:25:04.906270 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip>
2363 11:25:04.906826 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip
2365 11:25:05.001657 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip>
2366 11:25:05.002148 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip
2368 11:25:05.098537 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip>
2369 11:25:05.099033 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip
2371 11:25:05.197044 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass>
2372 11:25:05.197523 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass
2374 11:25:05.292617 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass>
2375 11:25:05.293129 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass
2377 11:25:05.391378 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass>
2378 11:25:05.391867 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass
2380 11:25:05.487372 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass>
2381 11:25:05.487861 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass
2383 11:25:05.581169 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail>
2384 11:25:05.581446 + set +x
2385 11:25:05.581896 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail
2387 11:25:05.585516 <LAVA_SIGNAL_ENDRUN 1_kselftest-dt 1219295_1.6.2.4.5>
2388 11:25:05.586004 Received signal: <ENDRUN> 1_kselftest-dt 1219295_1.6.2.4.5
2389 11:25:05.586306 Ending use of test pattern.
2390 11:25:05.586532 Ending test lava.1_kselftest-dt (1219295_1.6.2.4.5), duration 99.25
2392 11:25:05.592872 <LAVA_TEST_RUNNER EXIT>
2393 11:25:05.593399 ok: lava_test_shell seems to have completed
2394 11:25:05.599114 dt_test_unprobed_devices_sh: fail
dt_test_unprobed_devices_sh_: skip
dt_test_unprobed_devices_sh_clk_mcasp0: pass
dt_test_unprobed_devices_sh_clk_mcasp0_fixed: skip
dt_test_unprobed_devices_sh_cpus_cpu_0: skip
dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate: skip
dt_test_unprobed_devices_sh_fixedregulator0: pass
dt_test_unprobed_devices_sh_leds: pass
dt_test_unprobed_devices_sh_ocp: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0: fail
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_eeprom_50: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_eeprom_50_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_54: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_54_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_55: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_55_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_56: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_56_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_57: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_57_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000: skip
dt_test_unprobed_devices_sh_ocp_target-module_47400000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800: pass
dt_test_unprobed_devices_sh_ocp_target-module_47810000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_50000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_53500000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_56000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0: skip
dt_test_unprobed_devices_sh_opp-table: skip
dt_test_unprobed_devices_sh_soc: skip
dt_test_unprobed_devices_sh_sound: pass
dt_test_unprobed_devices_sh_target-module_4b000000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0: pass
shardfile-dt: pass
2395 11:25:05.600123 end: 3.1 lava-test-shell (duration 00:01:41) [common]
2396 11:25:05.600413 end: 3 lava-test-retry (duration 00:01:41) [common]
2397 11:25:05.600699 start: 4 finalize (timeout 00:05:33) [common]
2398 11:25:05.601017 start: 4.1 power-off (timeout 00:00:30) [common]
2399 11:25:05.601386 Calling: 'curl' 'http://192.168.11.5:18083/1-1.3.4/1/off'
2400 11:25:05.970173 Returned 0 in 0 seconds
2401 11:25:06.071063 end: 4.1 power-off (duration 00:00:00) [common]
2403 11:25:06.071999 start: 4.2 read-feedback (timeout 00:05:32) [common]
2404 11:25:06.072610 Listened to connection for namespace 'common' for up to 1s
2405 11:25:06.073170 Listened to connection for namespace 'common' for up to 1s
2406 11:25:07.073520 Finalising connection for namespace 'common'
2407 11:25:07.073957 Disconnecting from shell: Finalise
2408 11:25:07.074229 / #
2409 11:25:07.174758 end: 4.2 read-feedback (duration 00:00:01) [common]
2410 11:25:07.175108 end: 4 finalize (duration 00:00:02) [common]
2411 11:25:07.175466 Cleaning after the job
2412 11:25:07.175788 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/1219295/tftp-deploy-xjexk29k/ramdisk
2413 11:25:07.179587 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/1219295/tftp-deploy-xjexk29k/kernel
2414 11:25:07.182635 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/1219295/tftp-deploy-xjexk29k/dtb
2415 11:25:07.183103 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/1219295/tftp-deploy-xjexk29k/nfsrootfs
2416 11:25:07.234782 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/1219295/tftp-deploy-xjexk29k/modules
2417 11:25:07.238414 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/1219295
2418 11:25:07.902621 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/1219295
2419 11:25:07.902897 Job finished correctly