Boot log: beaglebone-black
- Warnings: 2
- Kernel Warnings: 15
- Errors: 0
- Boot result: PASS
- Kernel Errors: 10
1 10:48:20.339733 lava-dispatcher, installed at version: 2024.01
2 10:48:20.340534 start: 0 validate
3 10:48:20.341032 Start time: 2024-11-08 10:48:20.341001+00:00 (UTC)
4 10:48:20.341602 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 10:48:20.342183 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farmhf%2Finitrd.cpio.gz exists
6 10:48:20.389001 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 10:48:20.389554 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241108%2Farm%2Fmulti_v7_defconfig%2Fgcc-12%2Fkernel%2FzImage exists
8 10:48:20.421813 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 10:48:20.422755 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241108%2Farm%2Fmulti_v7_defconfig%2Fgcc-12%2Fdtbs%2Fti%2Fomap%2Fam335x-boneblack.dtb exists
10 10:48:20.453225 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 10:48:20.453722 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farmhf%2Ffull.rootfs.tar.xz exists
12 10:48:20.484289 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 10:48:20.484780 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241108%2Farm%2Fmulti_v7_defconfig%2Fgcc-12%2Fmodules.tar.xz exists
14 10:48:20.527299 validate duration: 0.19
16 10:48:20.528700 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 10:48:20.529068 start: 1.1 download-retry (timeout 00:10:00) [common]
18 10:48:20.529467 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 10:48:20.530463 Not decompressing ramdisk as can be used compressed.
20 10:48:20.531196 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/initrd.cpio.gz
21 10:48:20.531476 saving as /var/lib/lava/dispatcher/tmp/958645/tftp-deploy-ai35iwtf/ramdisk/initrd.cpio.gz
22 10:48:20.531769 total size: 4775763 (4 MB)
23 10:48:20.574343 progress 0 % (0 MB)
24 10:48:20.579268 progress 5 % (0 MB)
25 10:48:20.586584 progress 10 % (0 MB)
26 10:48:20.595103 progress 15 % (0 MB)
27 10:48:20.604482 progress 20 % (0 MB)
28 10:48:20.608576 progress 25 % (1 MB)
29 10:48:20.612774 progress 30 % (1 MB)
30 10:48:20.616721 progress 35 % (1 MB)
31 10:48:20.620250 progress 40 % (1 MB)
32 10:48:20.623666 progress 45 % (2 MB)
33 10:48:20.627070 progress 50 % (2 MB)
34 10:48:20.630972 progress 55 % (2 MB)
35 10:48:20.634513 progress 60 % (2 MB)
36 10:48:20.638254 progress 65 % (2 MB)
37 10:48:20.642363 progress 70 % (3 MB)
38 10:48:20.645803 progress 75 % (3 MB)
39 10:48:20.649231 progress 80 % (3 MB)
40 10:48:20.652605 progress 85 % (3 MB)
41 10:48:20.656375 progress 90 % (4 MB)
42 10:48:20.659699 progress 95 % (4 MB)
43 10:48:20.662830 progress 100 % (4 MB)
44 10:48:20.663510 4 MB downloaded in 0.13 s (34.58 MB/s)
45 10:48:20.664067 end: 1.1.1 http-download (duration 00:00:00) [common]
47 10:48:20.664983 end: 1.1 download-retry (duration 00:00:00) [common]
48 10:48:20.665288 start: 1.2 download-retry (timeout 00:10:00) [common]
49 10:48:20.665565 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 10:48:20.666058 downloading http://storage.kernelci.org/next/master/next-20241108/arm/multi_v7_defconfig/gcc-12/kernel/zImage
51 10:48:20.666312 saving as /var/lib/lava/dispatcher/tmp/958645/tftp-deploy-ai35iwtf/kernel/zImage
52 10:48:20.666525 total size: 11510272 (10 MB)
53 10:48:20.666864 No compression specified
54 10:48:20.699464 progress 0 % (0 MB)
55 10:48:20.708481 progress 5 % (0 MB)
56 10:48:20.717071 progress 10 % (1 MB)
57 10:48:20.725435 progress 15 % (1 MB)
58 10:48:20.734115 progress 20 % (2 MB)
59 10:48:20.742171 progress 25 % (2 MB)
60 10:48:20.750965 progress 30 % (3 MB)
61 10:48:20.759115 progress 35 % (3 MB)
62 10:48:20.768044 progress 40 % (4 MB)
63 10:48:20.776539 progress 45 % (4 MB)
64 10:48:20.784651 progress 50 % (5 MB)
65 10:48:20.793180 progress 55 % (6 MB)
66 10:48:20.801136 progress 60 % (6 MB)
67 10:48:20.809305 progress 65 % (7 MB)
68 10:48:20.817156 progress 70 % (7 MB)
69 10:48:20.824949 progress 75 % (8 MB)
70 10:48:20.832950 progress 80 % (8 MB)
71 10:48:20.840723 progress 85 % (9 MB)
72 10:48:20.848985 progress 90 % (9 MB)
73 10:48:20.856686 progress 95 % (10 MB)
74 10:48:20.864117 progress 100 % (10 MB)
75 10:48:20.864679 10 MB downloaded in 0.20 s (55.40 MB/s)
76 10:48:20.865209 end: 1.2.1 http-download (duration 00:00:00) [common]
78 10:48:20.866098 end: 1.2 download-retry (duration 00:00:00) [common]
79 10:48:20.866414 start: 1.3 download-retry (timeout 00:10:00) [common]
80 10:48:20.866724 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 10:48:20.867434 downloading http://storage.kernelci.org/next/master/next-20241108/arm/multi_v7_defconfig/gcc-12/dtbs/ti/omap/am335x-boneblack.dtb
82 10:48:20.868301 saving as /var/lib/lava/dispatcher/tmp/958645/tftp-deploy-ai35iwtf/dtb/am335x-boneblack.dtb
83 10:48:20.868551 total size: 70544 (0 MB)
84 10:48:20.868931 No compression specified
85 10:48:20.907116 progress 46 % (0 MB)
86 10:48:20.908086 progress 92 % (0 MB)
87 10:48:20.908786 progress 100 % (0 MB)
88 10:48:20.909189 0 MB downloaded in 0.04 s (1.66 MB/s)
89 10:48:20.909733 end: 1.3.1 http-download (duration 00:00:00) [common]
91 10:48:20.910645 end: 1.3 download-retry (duration 00:00:00) [common]
92 10:48:20.910917 start: 1.4 download-retry (timeout 00:10:00) [common]
93 10:48:20.911250 start: 1.4.1 http-download (timeout 00:10:00) [common]
94 10:48:20.911725 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/full.rootfs.tar.xz
95 10:48:20.911962 saving as /var/lib/lava/dispatcher/tmp/958645/tftp-deploy-ai35iwtf/nfsrootfs/full.rootfs.tar
96 10:48:20.912195 total size: 117747780 (112 MB)
97 10:48:20.912407 Using unxz to decompress xz
98 10:48:20.952862 progress 0 % (0 MB)
99 10:48:21.680546 progress 5 % (5 MB)
100 10:48:22.424720 progress 10 % (11 MB)
101 10:48:23.192146 progress 15 % (16 MB)
102 10:48:23.905496 progress 20 % (22 MB)
103 10:48:24.489308 progress 25 % (28 MB)
104 10:48:25.320255 progress 30 % (33 MB)
105 10:48:26.129329 progress 35 % (39 MB)
106 10:48:26.476828 progress 40 % (44 MB)
107 10:48:26.846128 progress 45 % (50 MB)
108 10:48:27.499334 progress 50 % (56 MB)
109 10:48:28.307772 progress 55 % (61 MB)
110 10:48:29.027830 progress 60 % (67 MB)
111 10:48:29.731939 progress 65 % (73 MB)
112 10:48:30.487488 progress 70 % (78 MB)
113 10:48:31.244167 progress 75 % (84 MB)
114 10:48:31.974211 progress 80 % (89 MB)
115 10:48:32.683130 progress 85 % (95 MB)
116 10:48:33.473664 progress 90 % (101 MB)
117 10:48:34.244420 progress 95 % (106 MB)
118 10:48:35.055119 progress 100 % (112 MB)
119 10:48:35.067856 112 MB downloaded in 14.16 s (7.93 MB/s)
120 10:48:35.068780 end: 1.4.1 http-download (duration 00:00:14) [common]
122 10:48:35.070417 end: 1.4 download-retry (duration 00:00:14) [common]
123 10:48:35.070952 start: 1.5 download-retry (timeout 00:09:45) [common]
124 10:48:35.071478 start: 1.5.1 http-download (timeout 00:09:45) [common]
125 10:48:35.072311 downloading http://storage.kernelci.org/next/master/next-20241108/arm/multi_v7_defconfig/gcc-12/modules.tar.xz
126 10:48:35.072790 saving as /var/lib/lava/dispatcher/tmp/958645/tftp-deploy-ai35iwtf/modules/modules.tar
127 10:48:35.073209 total size: 6625392 (6 MB)
128 10:48:35.073634 Using unxz to decompress xz
129 10:48:35.117515 progress 0 % (0 MB)
130 10:48:35.152632 progress 5 % (0 MB)
131 10:48:35.195601 progress 10 % (0 MB)
132 10:48:35.238736 progress 15 % (0 MB)
133 10:48:35.282335 progress 20 % (1 MB)
134 10:48:35.330463 progress 25 % (1 MB)
135 10:48:35.374230 progress 30 % (1 MB)
136 10:48:35.418951 progress 35 % (2 MB)
137 10:48:35.462801 progress 40 % (2 MB)
138 10:48:35.507667 progress 45 % (2 MB)
139 10:48:35.556009 progress 50 % (3 MB)
140 10:48:35.598782 progress 55 % (3 MB)
141 10:48:35.644405 progress 60 % (3 MB)
142 10:48:35.686773 progress 65 % (4 MB)
143 10:48:35.730218 progress 70 % (4 MB)
144 10:48:35.776033 progress 75 % (4 MB)
145 10:48:35.818820 progress 80 % (5 MB)
146 10:48:35.861474 progress 85 % (5 MB)
147 10:48:35.904724 progress 90 % (5 MB)
148 10:48:35.952308 progress 95 % (6 MB)
149 10:48:35.996667 progress 100 % (6 MB)
150 10:48:36.007554 6 MB downloaded in 0.93 s (6.76 MB/s)
151 10:48:36.008596 end: 1.5.1 http-download (duration 00:00:01) [common]
153 10:48:36.009783 end: 1.5 download-retry (duration 00:00:01) [common]
154 10:48:36.010103 start: 1.6 prepare-tftp-overlay (timeout 00:09:45) [common]
155 10:48:36.010393 start: 1.6.1 extract-nfsrootfs (timeout 00:09:45) [common]
156 10:48:52.322218 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/958645/extract-nfsrootfs-6ziqyt20
157 10:48:52.322834 end: 1.6.1 extract-nfsrootfs (duration 00:00:16) [common]
158 10:48:52.323123 start: 1.6.2 lava-overlay (timeout 00:09:28) [common]
159 10:48:52.323726 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/958645/lava-overlay-txwqol1f
160 10:48:52.324186 makedir: /var/lib/lava/dispatcher/tmp/958645/lava-overlay-txwqol1f/lava-958645/bin
161 10:48:52.324525 makedir: /var/lib/lava/dispatcher/tmp/958645/lava-overlay-txwqol1f/lava-958645/tests
162 10:48:52.324846 makedir: /var/lib/lava/dispatcher/tmp/958645/lava-overlay-txwqol1f/lava-958645/results
163 10:48:52.325175 Creating /var/lib/lava/dispatcher/tmp/958645/lava-overlay-txwqol1f/lava-958645/bin/lava-add-keys
164 10:48:52.325703 Creating /var/lib/lava/dispatcher/tmp/958645/lava-overlay-txwqol1f/lava-958645/bin/lava-add-sources
165 10:48:52.326212 Creating /var/lib/lava/dispatcher/tmp/958645/lava-overlay-txwqol1f/lava-958645/bin/lava-background-process-start
166 10:48:52.326719 Creating /var/lib/lava/dispatcher/tmp/958645/lava-overlay-txwqol1f/lava-958645/bin/lava-background-process-stop
167 10:48:52.327262 Creating /var/lib/lava/dispatcher/tmp/958645/lava-overlay-txwqol1f/lava-958645/bin/lava-common-functions
168 10:48:52.327773 Creating /var/lib/lava/dispatcher/tmp/958645/lava-overlay-txwqol1f/lava-958645/bin/lava-echo-ipv4
169 10:48:52.328305 Creating /var/lib/lava/dispatcher/tmp/958645/lava-overlay-txwqol1f/lava-958645/bin/lava-install-packages
170 10:48:52.328808 Creating /var/lib/lava/dispatcher/tmp/958645/lava-overlay-txwqol1f/lava-958645/bin/lava-installed-packages
171 10:48:52.329296 Creating /var/lib/lava/dispatcher/tmp/958645/lava-overlay-txwqol1f/lava-958645/bin/lava-os-build
172 10:48:52.329790 Creating /var/lib/lava/dispatcher/tmp/958645/lava-overlay-txwqol1f/lava-958645/bin/lava-probe-channel
173 10:48:52.330278 Creating /var/lib/lava/dispatcher/tmp/958645/lava-overlay-txwqol1f/lava-958645/bin/lava-probe-ip
174 10:48:52.330841 Creating /var/lib/lava/dispatcher/tmp/958645/lava-overlay-txwqol1f/lava-958645/bin/lava-target-ip
175 10:48:52.331330 Creating /var/lib/lava/dispatcher/tmp/958645/lava-overlay-txwqol1f/lava-958645/bin/lava-target-mac
176 10:48:52.331803 Creating /var/lib/lava/dispatcher/tmp/958645/lava-overlay-txwqol1f/lava-958645/bin/lava-target-storage
177 10:48:52.332334 Creating /var/lib/lava/dispatcher/tmp/958645/lava-overlay-txwqol1f/lava-958645/bin/lava-test-case
178 10:48:52.332827 Creating /var/lib/lava/dispatcher/tmp/958645/lava-overlay-txwqol1f/lava-958645/bin/lava-test-event
179 10:48:52.333302 Creating /var/lib/lava/dispatcher/tmp/958645/lava-overlay-txwqol1f/lava-958645/bin/lava-test-feedback
180 10:48:52.333794 Creating /var/lib/lava/dispatcher/tmp/958645/lava-overlay-txwqol1f/lava-958645/bin/lava-test-raise
181 10:48:52.334275 Creating /var/lib/lava/dispatcher/tmp/958645/lava-overlay-txwqol1f/lava-958645/bin/lava-test-reference
182 10:48:52.334757 Creating /var/lib/lava/dispatcher/tmp/958645/lava-overlay-txwqol1f/lava-958645/bin/lava-test-runner
183 10:48:52.335236 Creating /var/lib/lava/dispatcher/tmp/958645/lava-overlay-txwqol1f/lava-958645/bin/lava-test-set
184 10:48:52.335705 Creating /var/lib/lava/dispatcher/tmp/958645/lava-overlay-txwqol1f/lava-958645/bin/lava-test-shell
185 10:48:52.336254 Updating /var/lib/lava/dispatcher/tmp/958645/lava-overlay-txwqol1f/lava-958645/bin/lava-add-keys (debian)
186 10:48:52.336807 Updating /var/lib/lava/dispatcher/tmp/958645/lava-overlay-txwqol1f/lava-958645/bin/lava-add-sources (debian)
187 10:48:52.337338 Updating /var/lib/lava/dispatcher/tmp/958645/lava-overlay-txwqol1f/lava-958645/bin/lava-install-packages (debian)
188 10:48:52.337843 Updating /var/lib/lava/dispatcher/tmp/958645/lava-overlay-txwqol1f/lava-958645/bin/lava-installed-packages (debian)
189 10:48:52.338350 Updating /var/lib/lava/dispatcher/tmp/958645/lava-overlay-txwqol1f/lava-958645/bin/lava-os-build (debian)
190 10:48:52.338796 Creating /var/lib/lava/dispatcher/tmp/958645/lava-overlay-txwqol1f/lava-958645/environment
191 10:48:52.339167 LAVA metadata
192 10:48:52.339424 - LAVA_JOB_ID=958645
193 10:48:52.339638 - LAVA_DISPATCHER_IP=192.168.6.2
194 10:48:52.340016 start: 1.6.2.1 ssh-authorize (timeout 00:09:28) [common]
195 10:48:52.341017 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
196 10:48:52.341326 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:28) [common]
197 10:48:52.341533 skipped lava-vland-overlay
198 10:48:52.341773 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
199 10:48:52.342026 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:28) [common]
200 10:48:52.342245 skipped lava-multinode-overlay
201 10:48:52.342487 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
202 10:48:52.342737 start: 1.6.2.4 test-definition (timeout 00:09:28) [common]
203 10:48:52.342983 Loading test definitions
204 10:48:52.343257 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:28) [common]
205 10:48:52.343476 Using /lava-958645 at stage 0
206 10:48:52.344582 uuid=958645_1.6.2.4.1 testdef=None
207 10:48:52.344885 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
208 10:48:52.345146 start: 1.6.2.4.2 test-overlay (timeout 00:09:28) [common]
209 10:48:52.346688 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
211 10:48:52.347467 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:28) [common]
212 10:48:52.349480 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
214 10:48:52.350301 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:28) [common]
215 10:48:52.352187 runner path: /var/lib/lava/dispatcher/tmp/958645/lava-overlay-txwqol1f/lava-958645/0/tests/0_timesync-off test_uuid 958645_1.6.2.4.1
216 10:48:52.352756 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
218 10:48:52.353566 start: 1.6.2.4.5 git-repo-action (timeout 00:09:28) [common]
219 10:48:52.353807 Using /lava-958645 at stage 0
220 10:48:52.354162 Fetching tests from https://github.com/kernelci/test-definitions.git
221 10:48:52.354447 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/958645/lava-overlay-txwqol1f/lava-958645/0/tests/1_kselftest-dt'
222 10:48:55.735885 Running '/usr/bin/git checkout kernelci.org
223 10:48:56.295119 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/958645/lava-overlay-txwqol1f/lava-958645/0/tests/1_kselftest-dt/automated/linux/kselftest/kselftest.yaml
224 10:48:56.296609 uuid=958645_1.6.2.4.5 testdef=None
225 10:48:56.296968 end: 1.6.2.4.5 git-repo-action (duration 00:00:04) [common]
227 10:48:56.297721 start: 1.6.2.4.6 test-overlay (timeout 00:09:24) [common]
228 10:48:56.301031 end: 1.6.2.4.6 test-overlay (duration 00:00:00) [common]
230 10:48:56.301894 start: 1.6.2.4.7 test-install-overlay (timeout 00:09:24) [common]
231 10:48:56.308465 end: 1.6.2.4.7 test-install-overlay (duration 00:00:00) [common]
233 10:48:56.310165 start: 1.6.2.4.8 test-runscript-overlay (timeout 00:09:24) [common]
234 10:48:56.317531 runner path: /var/lib/lava/dispatcher/tmp/958645/lava-overlay-txwqol1f/lava-958645/0/tests/1_kselftest-dt test_uuid 958645_1.6.2.4.5
235 10:48:56.318104 BOARD='beaglebone-black'
236 10:48:56.318508 BRANCH='next'
237 10:48:56.318901 SKIPFILE='/dev/null'
238 10:48:56.319291 SKIP_INSTALL='True'
239 10:48:56.319683 TESTPROG_URL='http://storage.kernelci.org/next/master/next-20241108/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz'
240 10:48:56.320120 TST_CASENAME=''
241 10:48:56.320539 TST_CMDFILES='dt'
242 10:48:56.321613 end: 1.6.2.4.8 test-runscript-overlay (duration 00:00:00) [common]
244 10:48:56.323192 Creating lava-test-runner.conf files
245 10:48:56.323595 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/958645/lava-overlay-txwqol1f/lava-958645/0 for stage 0
246 10:48:56.324526 - 0_timesync-off
247 10:48:56.325041 - 1_kselftest-dt
248 10:48:56.325691 end: 1.6.2.4 test-definition (duration 00:00:04) [common]
249 10:48:56.326244 start: 1.6.2.5 compress-overlay (timeout 00:09:24) [common]
250 10:49:19.742543 end: 1.6.2.5 compress-overlay (duration 00:00:23) [common]
251 10:49:19.742985 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:09:01) [common]
252 10:49:19.743250 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
253 10:49:19.743522 end: 1.6.2 lava-overlay (duration 00:00:27) [common]
254 10:49:19.743787 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:01) [common]
255 10:49:20.103494 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
256 10:49:20.103956 start: 1.6.4 extract-modules (timeout 00:09:00) [common]
257 10:49:20.104265 extracting modules file /var/lib/lava/dispatcher/tmp/958645/tftp-deploy-ai35iwtf/modules/modules.tar to /var/lib/lava/dispatcher/tmp/958645/extract-nfsrootfs-6ziqyt20
258 10:49:21.006414 extracting modules file /var/lib/lava/dispatcher/tmp/958645/tftp-deploy-ai35iwtf/modules/modules.tar to /var/lib/lava/dispatcher/tmp/958645/extract-overlay-ramdisk-x6eo8cjw/ramdisk
259 10:49:21.931285 end: 1.6.4 extract-modules (duration 00:00:02) [common]
260 10:49:21.931747 start: 1.6.5 apply-overlay-tftp (timeout 00:08:59) [common]
261 10:49:21.932058 [common] Applying overlay to NFS
262 10:49:21.932294 [common] Applying overlay /var/lib/lava/dispatcher/tmp/958645/compress-overlay-4ik1dszk/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/958645/extract-nfsrootfs-6ziqyt20
263 10:49:24.679607 end: 1.6.5 apply-overlay-tftp (duration 00:00:03) [common]
264 10:49:24.680121 start: 1.6.6 prepare-kernel (timeout 00:08:56) [common]
265 10:49:24.680429 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:08:56) [common]
266 10:49:24.680726 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
267 10:49:24.680995 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
268 10:49:24.681264 start: 1.6.7 configure-preseed-file (timeout 00:08:56) [common]
269 10:49:24.681528 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
270 10:49:24.681795 start: 1.6.8 compress-ramdisk (timeout 00:08:56) [common]
271 10:49:24.682057 Building ramdisk /var/lib/lava/dispatcher/tmp/958645/extract-overlay-ramdisk-x6eo8cjw/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/958645/extract-overlay-ramdisk-x6eo8cjw/ramdisk
272 10:49:25.667458 >> 75308 blocks
273 10:49:30.257423 Adding RAMdisk u-boot header.
274 10:49:30.257900 mkimage -A arm -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/958645/extract-overlay-ramdisk-x6eo8cjw/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/958645/extract-overlay-ramdisk-x6eo8cjw/ramdisk.cpio.gz.uboot
275 10:49:30.444856 output: Image Name:
276 10:49:30.445252 output: Created: Fri Nov 8 10:49:30 2024
277 10:49:30.445463 output: Image Type: ARM Linux RAMDisk Image (uncompressed)
278 10:49:30.445671 output: Data Size: 14830040 Bytes = 14482.46 KiB = 14.14 MiB
279 10:49:30.445874 output: Load Address: 00000000
280 10:49:30.446074 output: Entry Point: 00000000
281 10:49:30.446272 output:
282 10:49:30.446844 rename /var/lib/lava/dispatcher/tmp/958645/extract-overlay-ramdisk-x6eo8cjw/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/958645/tftp-deploy-ai35iwtf/ramdisk/ramdisk.cpio.gz.uboot
283 10:49:30.447260 end: 1.6.8 compress-ramdisk (duration 00:00:06) [common]
284 10:49:30.447545 end: 1.6 prepare-tftp-overlay (duration 00:00:54) [common]
285 10:49:30.447819 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:50) [common]
286 10:49:30.448144 No LXC device requested
287 10:49:30.448658 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
288 10:49:30.449169 start: 1.8 deploy-device-env (timeout 00:08:50) [common]
289 10:49:30.449664 end: 1.8 deploy-device-env (duration 00:00:00) [common]
290 10:49:30.450073 Checking files for TFTP limit of 4294967296 bytes.
291 10:49:30.452729 end: 1 tftp-deploy (duration 00:01:10) [common]
292 10:49:30.453308 start: 2 uboot-action (timeout 00:05:00) [common]
293 10:49:30.453831 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
294 10:49:30.454329 end: 2.1 uboot-from-media (duration 00:00:00) [common]
295 10:49:30.454828 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
296 10:49:30.455574 substitutions:
297 10:49:30.456019 - {BOOTX}: bootz 0x82000000 0x83000000 0x88000000
298 10:49:30.456451 - {DTB_ADDR}: 0x88000000
299 10:49:30.456853 - {DTB}: 958645/tftp-deploy-ai35iwtf/dtb/am335x-boneblack.dtb
300 10:49:30.457252 - {INITRD}: 958645/tftp-deploy-ai35iwtf/ramdisk/ramdisk.cpio.gz.uboot
301 10:49:30.457648 - {KERNEL_ADDR}: 0x82000000
302 10:49:30.458037 - {KERNEL}: 958645/tftp-deploy-ai35iwtf/kernel/zImage
303 10:49:30.458429 - {LAVA_MAC}: None
304 10:49:30.458855 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/958645/extract-nfsrootfs-6ziqyt20
305 10:49:30.459250 - {NFS_SERVER_IP}: 192.168.6.2
306 10:49:30.459637 - {PRESEED_CONFIG}: None
307 10:49:30.460054 - {PRESEED_LOCAL}: None
308 10:49:30.460446 - {RAMDISK_ADDR}: 0x83000000
309 10:49:30.460831 - {RAMDISK}: 958645/tftp-deploy-ai35iwtf/ramdisk/ramdisk.cpio.gz.uboot
310 10:49:30.461222 - {ROOT_PART}: None
311 10:49:30.461607 - {ROOT}: None
312 10:49:30.461991 - {SERVER_IP}: 192.168.6.2
313 10:49:30.462373 - {TEE_ADDR}: 0x83000000
314 10:49:30.462755 - {TEE}: None
315 10:49:30.463136 Parsed boot commands:
316 10:49:30.463513 - setenv autoload no
317 10:49:30.463895 - setenv initrd_high 0xffffffff
318 10:49:30.464323 - setenv fdt_high 0xffffffff
319 10:49:30.464709 - dhcp
320 10:49:30.465090 - setenv serverip 192.168.6.2
321 10:49:30.465472 - tftp 0x82000000 958645/tftp-deploy-ai35iwtf/kernel/zImage
322 10:49:30.465857 - tftp 0x83000000 958645/tftp-deploy-ai35iwtf/ramdisk/ramdisk.cpio.gz.uboot
323 10:49:30.466242 - setenv initrd_size ${filesize}
324 10:49:30.466622 - tftp 0x88000000 958645/tftp-deploy-ai35iwtf/dtb/am335x-boneblack.dtb
325 10:49:30.467004 - setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/958645/extract-nfsrootfs-6ziqyt20,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
326 10:49:30.467399 - bootz 0x82000000 0x83000000 0x88000000
327 10:49:30.467892 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
329 10:49:30.469398 start: 2.3 connect-device (timeout 00:05:00) [common]
330 10:49:30.469816 [common] connect-device Connecting to device using 'telnet conserv1 3003'
331 10:49:30.484501 Setting prompt string to ['lava-test: # ']
332 10:49:30.485982 end: 2.3 connect-device (duration 00:00:00) [common]
333 10:49:30.486572 start: 2.4 uboot-commands (timeout 00:05:00) [common]
334 10:49:30.487114 start: 2.4.1 reset-device (timeout 00:05:00) [common]
335 10:49:30.487634 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
336 10:49:30.488876 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=beaglebone-black-01'
337 10:49:30.526280 >> OK - accepted request
338 10:49:30.528331 Returned 0 in 0 seconds
339 10:49:30.629481 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
341 10:49:30.631117 end: 2.4.1 reset-device (duration 00:00:00) [common]
342 10:49:30.631665 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
343 10:49:30.632236 Setting prompt string to ['Hit any key to stop autoboot']
344 10:49:30.632699 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
345 10:49:30.634247 Trying 192.168.56.21...
346 10:49:30.634726 Connected to conserv1.
347 10:49:30.635141 Escape character is '^]'.
348 10:49:30.635543
349 10:49:30.635955 ser2net port telnet,3003 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.2.3:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
350 10:49:30.636425
351 10:49:38.387867
352 10:49:38.388526 U-Boot SPL 2022.07-rc3-dirty (May 24 2022 - 12:39:48 +0100)
353 10:49:38.392791 Trying to boot from MMC1
354 10:49:38.965132
355 10:49:38.965683
356 10:49:38.966083 U-Boot 2022.07-rc3-dirty (May 24 2022 - 12:39:48 +0100)
357 10:49:38.966480
358 10:49:38.970300 CPU : AM335X-GP rev 2.1
359 10:49:38.970744 Model: TI AM335x BeagleBone Black
360 10:49:38.974455 DRAM: 512 MiB
361 10:49:39.057367 Core: 160 devices, 18 uclasses, devicetree: separate
362 10:49:39.066852 WDT: Started wdt@44e35000 with servicing (60s timeout)
363 10:49:42.435001 7[r[999;999H[6n8NAND:
364 10:49:42.435641 U-Boot SPL 2022.07-rc3-dirty (May 24 2022 - 12:39:48 +0100)
365 10:49:42.440227 Trying to boot from MMC1
366 10:49:43.012735
367 10:49:43.013365
368 10:49:43.013796 U-Boot 2022.07-rc3-dirty (May 24 2022 - 12:39:48 +0100)
369 10:49:43.014215
370 10:49:43.018099 CPU : AM335X-GP rev 2.1
371 10:49:43.018549 Model: TI AM335x BeagleBone Black
372 10:49:43.022374 DRAM: 512 MiB
373 10:49:43.105102 Core: 160 devices, 18 uclasses, devicetree: separate
374 10:49:43.114651 WDT: Started wdt@44e35000 with servicing (60s timeout)
375 10:49:45.136463 7[r[999;999H[6n8NAND:
376 10:49:45.137093 U-Boot SPL 2022.07-rc3-dirty (May 24 2022 - 12:39:48 +0100)
377 10:49:45.141598 Trying to boot from MMC1
378 10:49:45.716848
379 10:49:45.717472
380 10:49:45.717897 U-Boot 2022.07-rc3-dirty (May 24 2022 - 12:39:48 +0100)
381 10:49:45.718307
382 10:49:45.722098 CPU : AM335X-GP rev 2.1
383 10:49:45.722580 Model: TI AM335x BeagleBone Black
384 10:49:45.726279 DRAM: 512 MiB
385 10:49:45.809537 Core: 160 devices, 18 uclasses, devicetree: separate
386 10:49:45.819193 WDT: Started wdt@44e35000 with servicing (60s timeout)
387 10:49:46.324338 7[r[999;999H[6n8NAND: 0 MiB
388 10:49:46.334516 MMC: OMAP SD/MMC: 0, OMAP SD/MMC: 1
389 10:49:46.407368 Loading Environment from FAT... Unable to use mmc 0:1...
390 10:49:46.428700 <ethaddr> not set. Validating first E-fuse MAC
391 10:49:46.459099 Net: eth2: ethernet@4a100000, eth3: usb_ether
393 10:49:46.518122 Hit any key to stop autoboot: 2
394 10:49:46.519126 end: 2.4.2 bootloader-interrupt (duration 00:00:16) [common]
395 10:49:46.519587 start: 2.4.3 bootloader-commands (timeout 00:04:44) [common]
396 10:49:46.519942 Setting prompt string to ['=>']
397 10:49:46.520323 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:44)
398 10:49:46.527550 0
399 10:49:46.528428 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
400 10:49:46.528953 Sending with 10 millisecond of delay
402 10:49:47.664423 => setenv autoload no
403 10:49:47.675125 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:43)
404 10:49:47.678340 setenv autoload no
405 10:49:47.678892 Sending with 10 millisecond of delay
407 10:49:49.476021 => setenv initrd_high 0xffffffff
408 10:49:49.486810 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
409 10:49:49.487651 setenv initrd_high 0xffffffff
410 10:49:49.488396 Sending with 10 millisecond of delay
412 10:49:51.105010 => setenv fdt_high 0xffffffff
413 10:49:51.115807 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:39)
414 10:49:51.116677 setenv fdt_high 0xffffffff
415 10:49:51.117388 Sending with 10 millisecond of delay
417 10:49:51.409157 => dhcp
418 10:49:51.419915 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:39)
419 10:49:51.420817 dhcp
420 10:49:51.422679 link up on port 0, speed 100, full duplex
421 10:49:51.423120 BOOTP broadcast 1
422 10:49:51.446099 DHCP client bound to address 192.168.6.12 (20 ms)
423 10:49:51.446820 Sending with 10 millisecond of delay
425 10:49:53.123036 => setenv serverip 192.168.6.2
426 10:49:53.133832 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:37)
427 10:49:53.134741 setenv serverip 192.168.6.2
428 10:49:53.135443 Sending with 10 millisecond of delay
430 10:49:56.625315 => tftp 0x82000000 958645/tftp-deploy-ai35iwtf/kernel/zImage
431 10:49:56.635927 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:34)
432 10:49:56.636493 tftp 0x82000000 958645/tftp-deploy-ai35iwtf/kernel/zImage
433 10:49:56.636745 link up on port 0, speed 100, full duplex
434 10:49:56.640561 Using ethernet@4a100000 device
435 10:49:56.646226 TFTP from server 192.168.6.2; our IP address is 192.168.6.12
436 10:49:56.653523 Filename '958645/tftp-deploy-ai35iwtf/kernel/zImage'.
437 10:49:56.653931 Load address: 0x82000000
438 10:49:58.811333 Loading: *################################################## 11 MiB
439 10:49:58.814364 5.1 MiB/s
440 10:49:58.814890 done
441 10:49:58.815626 Bytes transferred = 11510272 (afa200 hex)
442 10:49:58.816387 Sending with 10 millisecond of delay
444 10:50:03.262406 => tftp 0x83000000 958645/tftp-deploy-ai35iwtf/ramdisk/ramdisk.cpio.gz.uboot
445 10:50:03.273186 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:27)
446 10:50:03.273993 tftp 0x83000000 958645/tftp-deploy-ai35iwtf/ramdisk/ramdisk.cpio.gz.uboot
447 10:50:03.274439 link up on port 0, speed 100, full duplex
448 10:50:03.277596 Using ethernet@4a100000 device
449 10:50:03.283164 TFTP from server 192.168.6.2; our IP address is 192.168.6.12
450 10:50:03.291875 Filename '958645/tftp-deploy-ai35iwtf/ramdisk/ramdisk.cpio.gz.uboot'.
451 10:50:03.292395 Load address: 0x83000000
452 10:50:06.257141 Loading: *################################################## 14.1 MiB
453 10:50:06.257751 4.8 MiB/s
454 10:50:06.258184 done
455 10:50:06.261444 Bytes transferred = 14830104 (e24a18 hex)
456 10:50:06.262661 Sending with 10 millisecond of delay
458 10:50:08.120034 => setenv initrd_size ${filesize}
459 10:50:08.130813 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:22)
460 10:50:08.131604 setenv initrd_size ${filesize}
461 10:50:08.132336 Sending with 10 millisecond of delay
463 10:50:12.278812 => tftp 0x88000000 958645/tftp-deploy-ai35iwtf/dtb/am335x-boneblack.dtb
464 10:50:12.289577 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
465 10:50:12.290436 tftp 0x88000000 958645/tftp-deploy-ai35iwtf/dtb/am335x-boneblack.dtb
466 10:50:12.290879 link up on port 0, speed 100, full duplex
467 10:50:12.295110 Using ethernet@4a100000 device
468 10:50:12.300403 TFTP from server 192.168.6.2; our IP address is 192.168.6.12
469 10:50:12.310891 Filename '958645/tftp-deploy-ai35iwtf/dtb/am335x-boneblack.dtb'.
470 10:50:12.311354 Load address: 0x88000000
471 10:50:12.321788 Loading: *################################################## 68.9 KiB
472 10:50:12.322301 4.5 MiB/s
473 10:50:12.330478 done
474 10:50:12.330927 Bytes transferred = 70544 (11390 hex)
475 10:50:12.331588 Sending with 10 millisecond of delay
477 10:50:25.513478 => setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/958645/extract-nfsrootfs-6ziqyt20,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
478 10:50:25.526483 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:05)
479 10:50:25.527080 setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/958645/extract-nfsrootfs-6ziqyt20,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
480 10:50:25.527581 Sending with 10 millisecond of delay
482 10:50:27.866536 => bootz 0x82000000 0x83000000 0x88000000
483 10:50:27.877349 Setting prompt string to ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
484 10:50:27.877942 bootloader-commands: Wait for prompt ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:03)
485 10:50:27.878965 bootz 0x82000000 0x83000000 0x88000000
486 10:50:27.879419 Kernel image @ 0x82000000 [ 0x000000 - 0xafa200 ]
487 10:50:27.879919 ## Loading init Ramdisk from Legacy Image at 83000000 ...
488 10:50:27.884947 Image Name:
489 10:50:27.885398 Created: 2024-11-08 10:49:30 UTC
490 10:50:27.893714 Image Type: ARM Linux RAMDisk Image (uncompressed)
491 10:50:27.894199 Data Size: 14830040 Bytes = 14.1 MiB
492 10:50:27.902134 Load Address: 00000000
493 10:50:27.902608 Entry Point: 00000000
494 10:50:28.071111 Verifying Checksum ... OK
495 10:50:28.071713 ## Flattened Device Tree blob at 88000000
496 10:50:28.077492 Booting using the fdt blob at 0x88000000
497 10:50:28.082491 Using Device Tree in place at 88000000, end 8801438f
498 10:50:28.096181
499 10:50:28.096666 Starting kernel ...
500 10:50:28.097082
501 10:50:28.097948 end: 2.4.3 bootloader-commands (duration 00:00:42) [common]
502 10:50:28.098543 start: 2.4.4 auto-login-action (timeout 00:04:02) [common]
503 10:50:28.099010 Setting prompt string to ['Linux version [0-9]']
504 10:50:28.099459 Setting prompt string to ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
505 10:50:28.099917 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:05:00)
506 10:50:28.945744 [ 0.000000] Booting Linux on physical CPU 0x0
507 10:50:28.951734 start: 2.4.4.1 login-action (timeout 00:04:02) [common]
508 10:50:28.952363 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
509 10:50:28.952841 Setting prompt string to []
510 10:50:28.953326 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
511 10:50:28.953788 Using line separator: #'\n'#
512 10:50:28.954193 No login prompt set.
513 10:50:28.954622 Parsing kernel messages
514 10:50:28.955016 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
515 10:50:28.955781 [login-action] Waiting for messages, (timeout 00:04:01)
516 10:50:28.956266 Waiting using forced prompt support (timeout 00:02:01)
517 10:50:28.965979 [ 0.000000] Linux version 6.12.0-rc6-next-20241108 (KernelCI@build-j368316-arm-gcc-12-multi-v7-defconfig-brkqm) (arm-linux-gnueabihf-gcc (Debian 12.2.0-14) 12.2.0, GNU ld (GNU Binutils for Debian) 2.40) #1 SMP Fri Nov 8 10:24:22 UTC 2024
518 10:50:28.977418 [ 0.000000] CPU: ARMv7 Processor [413fc082] revision 2 (ARMv7), cr=10c5387d
519 10:50:28.983211 [ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
520 10:50:28.988780 [ 0.000000] OF: fdt: Machine model: TI AM335x BeagleBone Black
521 10:50:28.994510 [ 0.000000] earlycon: omap8250 at MMIO 0x44e09000 (options '')
522 10:50:29.000267 [ 0.000000] printk: legacy bootconsole [omap8250] enabled
523 10:50:29.006083 [ 0.000000] Memory policy: Data cache writeback
524 10:50:29.012698 [ 0.000000] efi: UEFI not found.
525 10:50:29.021656 [ 0.000000] cma: Reserved 64 MiB at 0x9b800000 on node -1
526 10:50:29.022118 [ 0.000000] Zone ranges:
527 10:50:29.027252 [ 0.000000] DMA [mem 0x0000000080000000-0x000000009fdfffff]
528 10:50:29.033003 [ 0.000000] Normal empty
529 10:50:29.033471 [ 0.000000] HighMem empty
530 10:50:29.038797 [ 0.000000] Movable zone start for each node
531 10:50:29.044285 [ 0.000000] Early memory node ranges
532 10:50:29.050003 [ 0.000000] node 0: [mem 0x0000000080000000-0x000000009fdfffff]
533 10:50:29.055629 [ 0.000000] Initmem setup node 0 [mem 0x0000000080000000-0x000000009fdfffff]
534 10:50:29.077182 [ 0.000000] OF: reserved mem: Reserved memory: No reserved-memory node in the DT
535 10:50:29.089616 [ 0.000000] CPU: All CPU(s) started in SVC mode.
536 10:50:29.095241 [ 0.000000] AM335X ES2.1 (sgx neon)
537 10:50:29.106948 [ 0.000000] percpu: Embedded 17 pages/cpu s40204 r8192 d21236 u69632
538 10:50:29.124452 [ 0.000000] Kernel command line: console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/958645/extract-nfsrootfs-6ziqyt20,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp
539 10:50:29.136176 <6>[ 0.000000] printk: log buffer data + meta data: 131072 + 409600 = 540672 bytes
540 10:50:29.141923 <6>[ 0.000000] Dentry cache hash table entries: 65536 (order: 6, 262144 bytes, linear)
541 10:50:29.153367 <6>[ 0.000000] Inode-cache hash table entries: 32768 (order: 5, 131072 bytes, linear)
542 10:50:29.160131 <6>[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 130560
543 10:50:29.165524 <6>[ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
544 10:50:29.194589 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
545 10:50:29.200575 <6>[ 0.000000] trace event string verifier disabled
546 10:50:29.201054 <6>[ 0.000000] rcu: Hierarchical RCU implementation.
547 10:50:29.206283 <6>[ 0.000000] rcu: RCU event tracing is enabled.
548 10:50:29.217718 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=16 to nr_cpu_ids=1.
549 10:50:29.218185 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
550 10:50:29.229202 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 10 jiffies.
551 10:50:29.234912 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=1
552 10:50:29.245745 <6>[ 0.000000] RCU Tasks Trace: Setting shift to 0 and lim to 1 rcu_task_cb_adjust=1 rcu_task_cpu_ids=1.
553 10:50:29.260780 <6>[ 0.000000] NR_IRQS: 16, nr_irqs: 16, preallocated irqs: 16
554 10:50:29.278306 <6>[ 0.000000] IRQ: Found an INTC at 0x(ptrval) (revision 5.0) with 128 interrupts
555 10:50:29.285069 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
556 10:50:29.377449 <6>[ 0.000000] TI gptimer clocksource: always-on /ocp/interconnect@44c00000/segment@200000/target-module@31000
557 10:50:29.388837 <6>[ 0.000003] sched_clock: 32 bits at 24MHz, resolution 41ns, wraps every 89478484971ns
558 10:50:29.395642 <6>[ 0.008334] clocksource: dmtimer: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 79635851949 ns
559 10:50:29.408744 <6>[ 0.019161] TI gptimer clockevent: 24000000 Hz at /ocp/interconnect@48000000/segment@0/target-module@40000
560 10:50:29.416287 <6>[ 0.034061] Console: colour dummy device 80x30
561 10:50:29.422300 Matched prompt #6: WARNING:
562 10:50:29.422846 Setting prompt string to ['end trace[^\\r]*\\r', '/ #', 'Login timed out', 'Login incorrect']
563 10:50:29.427673 <3>[ 0.038959] WARNING: Your 'console=ttyO0' has been replaced by 'ttyS0'
564 10:50:29.430490 <3>[ 0.046029] This ensures that you still see kernel messages. Please
565 10:50:29.436667 <3>[ 0.052755] update your kernel commandline.
566 10:50:29.477193 <6>[ 0.057368] Calibrating delay loop... 996.14 BogoMIPS (lpj=4980736)
567 10:50:29.482957 <6>[ 0.096170] CPU: Testing write buffer coherency: ok
568 10:50:29.488862 <6>[ 0.101540] CPU0: Spectre v2: using BPIALL workaround
569 10:50:29.489311 <6>[ 0.107005] pid_max: default: 32768 minimum: 301
570 10:50:29.500457 <6>[ 0.112207] Mount-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
571 10:50:29.507331 <6>[ 0.120034] Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
572 10:50:29.514607 <6>[ 0.129476] CPU0: thread -1, cpu 0, socket -1, mpidr 0
573 10:50:29.523074 <6>[ 0.136563] Setting up static identity map for 0x80300000 - 0x803000ac
574 10:50:29.528896 <6>[ 0.146288] rcu: Hierarchical SRCU implementation.
575 10:50:29.536549 <6>[ 0.151571] rcu: Max phase no-delay instances is 1000.
576 10:50:29.545065 <6>[ 0.162720] EFI services will not be available.
577 10:50:29.550940 <6>[ 0.168008] smp: Bringing up secondary CPUs ...
578 10:50:29.556632 <6>[ 0.173054] smp: Brought up 1 node, 1 CPU
579 10:50:29.562450 <6>[ 0.177452] SMP: Total of 1 processors activated (996.14 BogoMIPS).
580 10:50:29.568376 <6>[ 0.184220] CPU: All CPU(s) started in SVC mode.
581 10:50:29.588758 <6>[ 0.189412] Memory: 405936K/522240K available (16384K kernel code, 2540K rwdata, 6828K rodata, 2048K init, 429K bss, 49108K reserved, 65536K cma-reserved, 0K highmem)
582 10:50:29.589347 <6>[ 0.205726] devtmpfs: initialized
583 10:50:29.611126 <6>[ 0.222971] VFP support v0.3: implementor 41 architecture 3 part 30 variant c rev 3
584 10:50:29.622691 <6>[ 0.231556] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
585 10:50:29.628593 <6>[ 0.242011] futex hash table entries: 256 (order: 2, 16384 bytes, linear)
586 10:50:29.639403 <6>[ 0.254317] pinctrl core: initialized pinctrl subsystem
587 10:50:29.648717 <6>[ 0.265096] DMI not present or invalid.
588 10:50:29.657121 <6>[ 0.270933] NET: Registered PF_NETLINK/PF_ROUTE protocol family
589 10:50:29.666631 <6>[ 0.279931] DMA: preallocated 256 KiB pool for atomic coherent allocations
590 10:50:29.681689 <6>[ 0.291470] thermal_sys: Registered thermal governor 'step_wise'
591 10:50:29.682087 <6>[ 0.291636] cpuidle: using governor menu
592 10:50:29.725879 <6>[ 0.325616] /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70: Fixed dependency cycle(s) with /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
593 10:50:29.741515 <6>[ 0.344424] /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
594 10:50:29.747173 <6>[ 0.365114] No ATAGs?
595 10:50:29.753410 <6>[ 0.367747] hw-breakpoint: debug architecture 0x4 unsupported.
596 10:50:29.763718 <6>[ 0.379811] Serial: AMBA PL011 UART driver
597 10:50:29.797661 <6>[ 0.415323] iommu: Default domain type: Translated
598 10:50:29.806603 <6>[ 0.420671] iommu: DMA domain TLB invalidation policy: strict mode
599 10:50:29.833257 <5>[ 0.450431] SCSI subsystem initialized
600 10:50:29.839084 <6>[ 0.455321] usbcore: registered new interface driver usbfs
601 10:50:29.844871 <6>[ 0.461384] usbcore: registered new interface driver hub
602 10:50:29.851686 <6>[ 0.467167] usbcore: registered new device driver usb
603 10:50:29.857427 <6>[ 0.473714] pps_core: LinuxPPS API ver. 1 registered
604 10:50:29.868912 <6>[ 0.479104] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
605 10:50:29.876163 <6>[ 0.488835] PTP clock support registered
606 10:50:29.876500 <6>[ 0.493301] EDAC MC: Ver: 3.0.0
607 10:50:29.924721 <6>[ 0.539956] scmi_core: SCMI protocol bus registered
608 10:50:29.939812 <6>[ 0.557393] vgaarb: loaded
609 10:50:29.952481 <6>[ 0.570457] clocksource: Switched to clocksource dmtimer
610 10:50:29.980401 <6>[ 0.597770] NET: Registered PF_INET protocol family
611 10:50:29.992777 <6>[ 0.603476] IP idents hash table entries: 8192 (order: 4, 65536 bytes, linear)
612 10:50:29.998638 <6>[ 0.612334] tcp_listen_portaddr_hash hash table entries: 512 (order: 0, 4096 bytes, linear)
613 10:50:30.010043 <6>[ 0.621269] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
614 10:50:30.015866 <6>[ 0.629511] TCP established hash table entries: 4096 (order: 2, 16384 bytes, linear)
615 10:50:30.027440 <6>[ 0.637804] TCP bind hash table entries: 4096 (order: 4, 65536 bytes, linear)
616 10:50:30.033242 <6>[ 0.645521] TCP: Hash tables configured (established 4096 bind 4096)
617 10:50:30.038996 <6>[ 0.652444] UDP hash table entries: 256 (order: 1, 8192 bytes, linear)
618 10:50:30.044966 <6>[ 0.659457] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes, linear)
619 10:50:30.052464 <6>[ 0.667068] NET: Registered PF_UNIX/PF_LOCAL protocol family
620 10:50:30.138770 <6>[ 0.751088] RPC: Registered named UNIX socket transport module.
621 10:50:30.139432 <6>[ 0.757475] RPC: Registered udp transport module.
622 10:50:30.144601 <6>[ 0.762623] RPC: Registered tcp transport module.
623 10:50:30.153174 <6>[ 0.767728] RPC: Registered tcp-with-tls transport module.
624 10:50:30.158921 <6>[ 0.773653] RPC: Registered tcp NFSv4.1 backchannel transport module.
625 10:50:30.166169 <6>[ 0.780574] PCI: CLS 0 bytes, default 64
626 10:50:30.168459 <5>[ 0.786351] Initialise system trusted keyrings
627 10:50:30.191681 <6>[ 0.806572] Trying to unpack rootfs image as initramfs...
628 10:50:30.272492 <6>[ 0.884144] workingset: timestamp_bits=30 max_order=17 bucket_order=0
629 10:50:30.277246 <6>[ 0.891704] squashfs: version 4.0 (2009/01/31) Phillip Lougher
630 10:50:30.313215 <5>[ 0.931113] NFS: Registering the id_resolver key type
631 10:50:30.318967 <5>[ 0.936694] Key type id_resolver registered
632 10:50:30.324728 <5>[ 0.941347] Key type id_legacy registered
633 10:50:30.333196 <6>[ 0.945786] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
634 10:50:30.340236 <6>[ 0.952993] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
635 10:50:30.393119 <5>[ 1.011010] Key type asymmetric registered
636 10:50:30.399014 <5>[ 1.015533] Asymmetric key parser 'x509' registered
637 10:50:30.407396 <6>[ 1.021013] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 246)
638 10:50:30.413190 <6>[ 1.028900] io scheduler mq-deadline registered
639 10:50:30.421909 <6>[ 1.033862] io scheduler kyber registered
640 10:50:30.422556 <6>[ 1.038317] io scheduler bfq registered
641 10:50:30.541892 <6>[ 1.156160] ledtrig-cpu: registered to indicate activity on CPUs
642 10:50:30.816913 <6>[ 1.430983] Serial: 8250/16550 driver, 5 ports, IRQ sharing enabled
643 10:50:30.857711 <6>[ 1.475470] msm_serial: driver initialized
644 10:50:30.863798 <6>[ 1.480268] SuperH (H)SCI(F) driver initialized
645 10:50:30.869730 <6>[ 1.485610] STMicroelectronics ASC driver initialized
646 10:50:30.874942 <6>[ 1.491285] STM32 USART driver initialized
647 10:50:30.987858 <6>[ 1.605014] brd: module loaded
648 10:50:31.020067 <6>[ 1.637210] loop: module loaded
649 10:50:31.061483 <6>[ 1.678392] CAN device driver interface
650 10:50:31.068180 <6>[ 1.683744] bgmac_bcma: Broadcom 47xx GBit MAC driver loaded
651 10:50:31.074006 <6>[ 1.690854] e1000e: Intel(R) PRO/1000 Network Driver
652 10:50:31.080429 <6>[ 1.696242] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
653 10:50:31.086144 <6>[ 1.702694] igb: Intel(R) Gigabit Ethernet Network Driver
654 10:50:31.093737 <6>[ 1.708517] igb: Copyright (c) 2007-2014 Intel Corporation.
655 10:50:31.105706 <6>[ 1.717839] pegasus: Pegasus/Pegasus II USB Ethernet driver
656 10:50:31.111397 <6>[ 1.724001] usbcore: registered new interface driver pegasus
657 10:50:31.117225 <6>[ 1.730127] usbcore: registered new interface driver asix
658 10:50:31.122971 <6>[ 1.736027] usbcore: registered new interface driver ax88179_178a
659 10:50:31.128748 <6>[ 1.742620] usbcore: registered new interface driver cdc_ether
660 10:50:31.134541 <6>[ 1.748918] usbcore: registered new interface driver smsc75xx
661 10:50:31.140304 <6>[ 1.755149] usbcore: registered new interface driver smsc95xx
662 10:50:31.146097 <6>[ 1.761377] usbcore: registered new interface driver net1080
663 10:50:31.151867 <6>[ 1.767502] usbcore: registered new interface driver cdc_subset
664 10:50:31.157736 <6>[ 1.773913] usbcore: registered new interface driver zaurus
665 10:50:31.165291 <6>[ 1.779958] usbcore: registered new interface driver cdc_ncm
666 10:50:31.175212 <6>[ 1.789533] usbcore: registered new interface driver usb-storage
667 10:50:31.184791 <6>[ 1.800867] i2c_dev: i2c /dev entries driver
668 10:50:31.209738 <5>[ 1.819724] cpuidle: enable-method property 'ti,am3352' found operations
669 10:50:31.215603 <6>[ 1.829274] sdhci: Secure Digital Host Controller Interface driver
670 10:50:31.223101 <6>[ 1.836029] sdhci: Copyright(c) Pierre Ossman
671 10:50:31.230455 <6>[ 1.842578] Synopsys Designware Multimedia Card Interface Driver
672 10:50:31.235883 <6>[ 1.850593] sdhci-pltfm: SDHCI platform and OF driver helper
673 10:50:31.250117 <6>[ 1.860610] usbcore: registered new interface driver usbhid
674 10:50:31.250818 <6>[ 1.866632] usbhid: USB HID core driver
675 10:50:31.263142 <6>[ 1.878434] NET: Registered PF_INET6 protocol family
676 10:50:31.724224 <6>[ 2.342066] Segment Routing with IPv6
677 10:50:31.730002 <6>[ 2.346215] In-situ OAM (IOAM) with IPv6
678 10:50:31.736808 <6>[ 2.350768] sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver
679 10:50:31.742560 <6>[ 2.358077] NET: Registered PF_PACKET protocol family
680 10:50:31.748331 <6>[ 2.363644] can: controller area network core
681 10:50:31.754129 <6>[ 2.368474] NET: Registered PF_CAN protocol family
682 10:50:31.754857 <6>[ 2.373722] can: raw protocol
683 10:50:31.759872 <6>[ 2.377050] can: broadcast manager protocol
684 10:50:31.766371 <6>[ 2.381651] can: netlink gateway - max_hops=1
685 10:50:31.772565 <5>[ 2.387153] Key type dns_resolver registered
686 10:50:31.778775 <6>[ 2.392224] ThumbEE CPU extension supported.
687 10:50:31.779494 <5>[ 2.396914] Registering SWP/SWPB emulation handler
688 10:50:31.788550 <3>[ 2.402619] omap_voltage_late_init: Voltage driver support not added
689 10:50:31.985546 <5>[ 2.601035] Loading compiled-in X.509 certificates
690 10:50:32.054885 <6>[ 2.657915] /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70: Fixed dependency cycle(s) with /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
691 10:50:32.084265 <6>[ 2.687355] /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70: Fixed dependency cycle(s) with /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
692 10:50:32.239475 <6>[ 2.843236] /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70: Fixed dependency cycle(s) with /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
693 10:50:32.256619 <6>[ 2.862791] /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70: Fixed dependency cycle(s) with /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
694 10:50:32.286117 <6>[ 2.889013] /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800/clkout2-pins
695 10:50:32.296071 <6>[ 2.910619] pinctrl-single 44e10800.pinmux: 142 pins, size 568
696 10:50:32.322550 <3>[ 2.934544] ti-sysc 44e31000.target-module: probe with driver ti-sysc failed with error -16
697 10:50:32.600432 <6>[ 3.203605] /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
698 10:50:32.626245 <3>[ 3.238253] ti-sysc 48040000.target-module: probe with driver ti-sysc failed with error -16
699 10:50:32.865220 <6>[ 3.481506] OMAP GPIO hardware version 0.1
700 10:50:32.885843 <6>[ 3.500180] omap-mailbox 480c8000.mailbox: omap mailbox rev 0x400
701 10:50:32.968461 <4>[ 3.582544] at24 2-0054: supply vcc not found, using dummy regulator
702 10:50:33.001823 <4>[ 3.615911] at24 2-0055: supply vcc not found, using dummy regulator
703 10:50:33.039787 <4>[ 3.653847] at24 2-0056: supply vcc not found, using dummy regulator
704 10:50:33.080189 <4>[ 3.694291] at24 2-0057: supply vcc not found, using dummy regulator
705 10:50:33.122374 <6>[ 3.737300] omap_i2c 4819c000.i2c: bus 2 rev0.11 at 100 kHz
706 10:50:33.196482 <3>[ 3.807336] 48000000.interconnect:segment@200000:target-module@0:mpu@0:fck: device ID is greater than 24
707 10:50:33.218589 <6>[ 3.821745] /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
708 10:50:33.245459 <6>[ 3.844992] /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
709 10:50:33.262881 <6>[ 3.864176] /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70: Fixed dependency cycle(s) with /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
710 10:50:33.279045 <6>[ 3.882132] /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
711 10:50:33.299899 <4>[ 3.912688] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
712 10:50:33.318659 <4>[ 3.931456] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
713 10:50:33.370129 <6>[ 3.986651] Freeing initrd memory: 14484K
714 10:50:33.378446 <6>[ 3.992634] omap_rng 48310000.rng: Random Number Generator ver. 20
715 10:50:33.402393 <5>[ 4.019391] random: crng init done
716 10:50:33.447712 <6>[ 4.060469] davinci_mdio 4a101000.mdio: davinci mdio revision 1.6, bus freq 1000000
717 10:50:33.531137 <6>[ 4.142899] davinci_mdio 4a101000.mdio: phy[0]: device 4a101000.mdio:00, driver SMSC LAN8710/LAN8720
718 10:50:33.536925 <6>[ 4.153201] cpsw-switch 4a100000.switch: initialized cpsw ale version 1.4
719 10:50:33.548643 <6>[ 4.160531] cpsw-switch 4a100000.switch: ALE Table size 1024, Policers 0
720 10:50:33.554460 <6>[ 4.167982] cpsw-switch 4a100000.switch: cpts: overflow check period 500 (jiffies)
721 10:50:33.565986 <6>[ 4.176120] cpsw-switch 4a100000.switch: CPTS: ref_clk_freq:250000000 calc_mult:2147483648 calc_shift:29 error:0 nsec/sec
722 10:50:33.573395 <6>[ 4.187767] cpsw-switch 4a100000.switch: Detected MACID = 78:a5:04:e2:4c:3d
723 10:50:33.586545 <5>[ 4.196806] cpsw-switch 4a100000.switch: initialized (regs 0x4a100000, pool size 256) hw_ver:0019010C 1.12 (0)
724 10:50:33.614429 <3>[ 4.226709] debugfs: Directory '49000000.dma' with parent 'dmaengine' already present!
725 10:50:33.620201 <6>[ 4.235315] edma 49000000.dma: TI EDMA DMA engine driver
726 10:50:33.691375 <3>[ 4.303059] target-module@4b000000:target-module@140000:pmu@0:fck: device ID is greater than 24
727 10:50:33.706171 <6>[ 4.317412] hw perfevents: enabled with armv7_cortex_a8 PMU driver, 5 (8000000f) counters available
728 10:50:33.719031 <3>[ 4.334502] l3-aon-clkctrl:0000:0: failed to disable
729 10:50:33.769298 <6>[ 4.381614] 44e09000.serial: ttyS0 at MMIO 0x44e09000 (irq = 36, base_baud = 3000000) is a 8250
730 10:50:33.775069 <6>[ 4.391088] printk: legacy console [ttyS0] enabled
731 10:50:33.780686 <6>[ 4.391088] printk: legacy console [ttyS0] enabled
732 10:50:33.786307 <6>[ 4.401422] printk: legacy bootconsole [omap8250] disabled
733 10:50:33.792192 <6>[ 4.401422] printk: legacy bootconsole [omap8250] disabled
734 10:50:33.829957 <4>[ 4.441224] tps65217-pmic: Failed to locate of_node [id: -1]
735 10:50:33.833504 <4>[ 4.448638] tps65217-bl: Failed to locate of_node [id: -1]
736 10:50:33.850000 <6>[ 4.468271] tps65217 0-0024: TPS65217 ID 0xe version 1.2
737 10:50:33.873998 <6>[ 4.475204] /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
738 10:50:33.891269 <6>[ 4.492860] /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70: Fixed dependency cycle(s) with /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
739 10:50:33.895617 <6>[ 4.510708] omap_i2c 44e0b000.i2c: bus 0 rev0.11 at 400 kHz
740 10:50:33.918196 <6>[ 4.530787] omap_gpio 44e07000.gpio: Could not set line 6 debounce to 200000 microseconds (-22)
741 10:50:33.924100 <6>[ 4.539843] sdhci-omap 48060000.mmc: Got CD GPIO
742 10:50:33.932120 <4>[ 4.545019] sdhci-omap 48060000.mmc: supply pbias not found, using dummy regulator
743 10:50:33.946823 <4>[ 4.558599] sdhci-omap 48060000.mmc: supply vqmmc not found, using dummy regulator
744 10:50:33.954485 <4>[ 4.567381] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
745 10:50:33.989379 <4>[ 4.602295] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
746 10:50:34.061967 <6>[ 4.675432] at24 0-0050: 32768 byte 24c256 EEPROM, writable, 1 bytes/write
747 10:50:34.108928 <6>[ 4.721135] mmc1: SDHCI controller on 481d8000.mmc [481d8000.mmc] using External DMA
748 10:50:34.115385 <6>[ 4.729634] mmc0: SDHCI controller on 48060000.mmc [48060000.mmc] using External DMA
749 10:50:34.124587 <6>[ 4.738427] cpsw-switch 4a100000.switch: starting ndev. mode: dual_mac
750 10:50:34.177900 <6>[ 4.792844] mmc0: new high speed SDHC card at address 1234
751 10:50:34.186147 <6>[ 4.802194] mmcblk0: mmc0:1234 SA32G 29.1 GiB
752 10:50:34.195656 <6>[ 4.813546] mmcblk0: p1
753 10:50:34.212486 <6>[ 4.822323] SMSC LAN8710/LAN8720 4a101000.mdio:00: attached PHY driver (mii_bus:phy_addr=4a101000.mdio:00, irq=POLL)
754 10:50:34.241016 <6>[ 4.849272] mmc1: new high speed MMC card at address 0001
755 10:50:34.241402 <6>[ 4.856268] mmcblk1: mmc1:0001 MMC04G 3.60 GiB
756 10:50:34.246384 <6>[ 4.864023] mmcblk1boot0: mmc1:0001 MMC04G 2.00 MiB
757 10:50:34.254691 <6>[ 4.871141] mmcblk1boot1: mmc1:0001 MMC04G 2.00 MiB
758 10:50:34.263741 <6>[ 4.878049] mmcblk1rpmb: mmc1:0001 MMC04G 128 KiB, chardev (236:0)
759 10:50:36.319235 <6>[ 6.931516] cpsw-switch 4a100000.switch eth0: Link is Up - 100Mbps/Full - flow control off
760 10:50:36.382856 <5>[ 6.960475] Sending DHCP requests ., OK
761 10:50:36.394186 <6>[ 7.005162] IP-Config: Got DHCP answer from 192.168.6.1, my address is 192.168.6.12
762 10:50:36.395037 <6>[ 7.013355] IP-Config: Complete:
763 10:50:36.405488 <6>[ 7.016896] device=eth0, hwaddr=78:a5:04:e2:4c:3d, ipaddr=192.168.6.12, mask=255.255.255.0, gw=192.168.6.1
764 10:50:36.411172 <6>[ 7.027440] host=192.168.6.12, domain=, nis-domain=(none)
765 10:50:36.423494 <6>[ 7.033660] bootserver=192.168.6.1, rootserver=192.168.6.2, rootpath=
766 10:50:36.424302 <6>[ 7.033694] nameserver0=10.255.253.1
767 10:50:36.429574 <6>[ 7.046240] clk: Disabling unused clocks
768 10:50:36.435402 <6>[ 7.050975] PM: genpd: Disabling unused power domains
769 10:50:36.454599 <6>[ 7.069197] Freeing unused kernel image (initmem) memory: 2048K
770 10:50:36.461915 <6>[ 7.078889] Run /init as init process
771 10:50:36.485692 Loading, please wait...
772 10:50:36.561821 Starting systemd-udevd version 252.22-1~deb12u1
773 10:50:39.652666 <4>[ 10.263710] am335x-phy-driver 47401300.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
774 10:50:39.796773 <4>[ 10.407819] am335x-phy-driver 47401b00.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
775 10:50:39.941420 <6>[ 10.559889] musb-hdrc musb-hdrc.1: MUSB HDRC host driver
776 10:50:39.952402 <6>[ 10.565765] musb-hdrc musb-hdrc.1: new USB bus registered, assigned bus number 1
777 10:50:40.176320 <6>[ 10.793295] hub 1-0:1.0: USB hub found
778 10:50:40.204730 <6>[ 10.821515] hub 1-0:1.0: 1 port detected
779 10:50:40.310236 <6>[ 10.926870] tda998x 0-0070: found TDA19988
780 10:50:43.649216 Begin: Loading essential drivers ... done.
781 10:50:43.652376 Begin: Running /scripts/init-premount ... done.
782 10:50:43.657993 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
783 10:50:43.672066 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
784 10:50:43.672429 Device /sys/class/net/eth0 found
785 10:50:43.672636 done.
786 10:50:43.747042 Begin: Waiting up to 180 secs for any network device to become available ... done.
787 10:50:43.845503 IP-Config: eth0 hardware address 78:a5:04:e2:4c:3d mtu 1500 DHCP
788 10:50:43.863596 IP-Config: eth0 guessed broadcast address 192.168.6.255
789 10:50:43.869175 IP-Config: eth0 complete (dhcp from 192.168.6.1):
790 10:50:43.874756 address: 192.168.6.12 broadcast: 192.168.6.255 netmask: 255.255.255.0
791 10:50:43.885837 gateway: 192.168.6.1 dns0 : 10.255.253.1 dns1 : 0.0.0.0
792 10:50:43.886396 rootserver: 192.168.6.1 rootpath:
793 10:50:43.889343 filename :
794 10:50:44.027373 done.
795 10:50:44.049877 Begin: Running /scripts/nfs-bottom ... done.
796 10:50:44.114634 Begin: Running /scripts/init-bottom ... done.
797 10:50:45.603547 <30>[ 16.217779] systemd[1]: System time before build time, advancing clock.
798 10:50:45.808635 <30>[ 16.396730] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
799 10:50:45.818344 <30>[ 16.434388] systemd[1]: Detected architecture arm.
800 10:50:45.830687
801 10:50:45.831190 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
802 10:50:45.831597
803 10:50:45.855406 <30>[ 16.470247] systemd[1]: Hostname set to <debian-bookworm-armhf>.
804 10:50:48.095904 <30>[ 18.709589] systemd[1]: Queued start job for default target graphical.target.
805 10:50:48.112845 <30>[ 18.724631] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
806 10:50:48.120545 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
807 10:50:48.141034 <30>[ 18.753281] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
808 10:50:48.149470 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
809 10:50:48.171944 <30>[ 18.783910] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
810 10:50:48.180267 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
811 10:50:48.200224 <30>[ 18.812457] systemd[1]: Created slice user.slice - User and Session Slice.
812 10:50:48.206876 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
813 10:50:48.235405 <30>[ 18.841842] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
814 10:50:48.241330 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
815 10:50:48.259283 <30>[ 18.871582] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
816 10:50:48.268292 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
817 10:50:48.300341 <30>[ 18.901613] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
818 10:50:48.306701 <30>[ 18.922132] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
819 10:50:48.315318 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
820 10:50:48.338345 <30>[ 18.950923] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
821 10:50:48.346710 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
822 10:50:48.371034 <30>[ 18.981344] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
823 10:50:48.377674 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
824 10:50:48.399933 <30>[ 19.011498] systemd[1]: Reached target paths.target - Path Units.
825 10:50:48.407865 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
826 10:50:48.428868 <30>[ 19.041136] systemd[1]: Reached target remote-fs.target - Remote File Systems.
827 10:50:48.436347 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
828 10:50:48.458611 <30>[ 19.070968] systemd[1]: Reached target slices.target - Slice Units.
829 10:50:48.463961 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
830 10:50:48.488869 <30>[ 19.101204] systemd[1]: Reached target swap.target - Swaps.
831 10:50:48.492858 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
832 10:50:48.520183 <30>[ 19.132403] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
833 10:50:48.532271 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
834 10:50:48.559803 <30>[ 19.172143] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
835 10:50:48.572714 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
836 10:50:48.647687 <30>[ 19.255187] systemd[1]: systemd-journald-audit.socket - Journal Audit Socket was skipped because of an unmet condition check (ConditionSecurity=audit).
837 10:50:48.660666 <30>[ 19.272892] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
838 10:50:48.669099 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
839 10:50:48.691939 <30>[ 19.303272] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
840 10:50:48.699244 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
841 10:50:48.721742 <30>[ 19.333664] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
842 10:50:48.730199 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
843 10:50:48.756359 <30>[ 19.367532] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
844 10:50:48.761832 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
845 10:50:48.790824 <30>[ 19.402454] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
846 10:50:48.798142 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
847 10:50:48.825899 <30>[ 19.432237] systemd[1]: dev-hugepages.mount - Huge Pages File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/mm/hugepages).
848 10:50:48.842457 <30>[ 19.448887] systemd[1]: dev-mqueue.mount - POSIX Message Queue File System was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/mqueue).
849 10:50:48.893381 <30>[ 19.506501] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
850 10:50:48.919262 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
851 10:50:48.971143 <30>[ 19.584273] systemd[1]: Mounting sys-kernel-tracing.mount - Kernel Trace File System...
852 10:50:48.996151 Mounting [0;1;39msys-kernel-tracin…[0m - Kernel Trace File System...
853 10:50:49.072326 <30>[ 19.684442] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
854 10:50:49.089671 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
855 10:50:49.149177 <30>[ 19.761968] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
856 10:50:49.172865 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
857 10:50:49.199786 <30>[ 19.812907] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
858 10:50:49.220426 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
859 10:50:49.278095 <30>[ 19.891772] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
860 10:50:49.289832 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
861 10:50:49.341530 <30>[ 19.954007] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
862 10:50:49.358028 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
863 10:50:49.398275 <30>[ 20.011819] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
864 10:50:49.415574 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
865 10:50:49.452848 <30>[ 20.066377] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
866 10:50:49.476706 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
867 10:50:49.506311 <28>[ 20.112747] systemd[1]: systemd-journald.service: unit configures an IP firewall, but the local system does not support BPF/cgroup firewalling.
868 10:50:49.514768 <28>[ 20.127486] systemd[1]: (This warning is only shown for the first unit using IP firewalling.)
869 10:50:49.557987 <30>[ 20.171933] systemd[1]: Starting systemd-journald.service - Journal Service...
870 10:50:49.569726 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
871 10:50:49.638556 <30>[ 20.251786] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
872 10:50:49.658578 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
873 10:50:49.695598 <30>[ 20.309066] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
874 10:50:49.765521 Starting [0;1;39msystemd-network-g… units from Kernel command line...
875 10:50:49.809833 <30>[ 20.421931] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
876 10:50:49.867291 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
877 10:50:49.943361 <30>[ 20.556141] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
878 10:50:49.997834 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
879 10:50:50.058495 <30>[ 20.672086] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
880 10:50:50.088858 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
881 10:50:50.109047 <30>[ 20.722544] systemd[1]: Mounted sys-kernel-tracing.mount - Kernel Trace File System.
882 10:50:50.148263 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-tracing…nt[0m - Kernel Trace File System.
883 10:50:50.171631 <30>[ 20.784158] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
884 10:50:50.210065 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
885 10:50:50.328549 <30>[ 20.942722] systemd[1]: modprobe@configfs.service: Deactivated successfully.
886 10:50:50.359078 <30>[ 20.972096] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
887 10:50:50.387311 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
888 10:50:50.399123 <30>[ 21.013518] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
889 10:50:50.438235 <30>[ 21.051011] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
890 10:50:50.446734 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
891 10:50:50.465418 <30>[ 21.079705] systemd[1]: Started systemd-journald.service - Journal Service.
892 10:50:50.497333 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
893 10:50:50.539829 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
894 10:50:50.564159 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
895 10:50:50.599415 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
896 10:50:50.623919 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
897 10:50:50.659729 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
898 10:50:50.681533 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
899 10:50:50.709865 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
900 10:50:50.732857 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
901 10:50:50.799030 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
902 10:50:50.833444 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
903 10:50:50.920016 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
904 10:50:51.011085 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
905 10:50:51.093921 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
906 10:50:51.214479 <46>[ 21.827980] systemd-journald[164]: Received client request to flush runtime journal.
907 10:50:51.231941 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
908 10:50:51.351801 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
909 10:50:52.182391 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
910 10:50:52.570262 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
911 10:50:52.628292 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
912 10:50:53.001257 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
913 10:50:53.210364 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
914 10:50:53.239010 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
915 10:50:53.257935 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
916 10:50:53.340903 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
917 10:50:53.380989 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
918 10:50:54.338501 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
919 10:50:54.400258 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
920 10:50:54.441119 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
921 10:50:54.540168 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
922 10:50:54.584138 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
923 10:50:55.509292 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
924 10:50:56.810407 <5>[ 27.424238] cfg80211: Loading compiled-in X.509 certificates for regulatory database
925 10:50:57.668673 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
926 10:50:58.202280 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
927 10:50:58.448363 <5>[ 29.064326] Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
928 10:50:58.533677 <5>[ 29.144772] Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
929 10:50:58.539380 <4>[ 29.155077] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
930 10:50:58.547318 <6>[ 29.164209] cfg80211: failed to load regulatory.db
931 10:50:58.689459 <46>[ 29.294372] systemd-journald[164]: Oldest entry in /var/log/journal/658c871cd7314ccea6115dc5728f8992/system.journal is older than the configured file retention duration (1month), suggesting rotation.
932 10:50:58.715298 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
933 10:50:58.844400 <46>[ 29.451454] systemd-journald[164]: /var/log/journal/658c871cd7314ccea6115dc5728f8992/system.journal: Journal header limits reached or header out-of-date, rotating.
934 10:51:00.222599 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
935 10:51:08.786996 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
936 10:51:08.813748 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
937 10:51:08.841292 [[0;32m OK [0m] Reached target [0;1;39musb-gadget.…m - Hardware activated USB gadget.
938 10:51:08.859660 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
939 10:51:08.933187 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
940 10:51:08.979951 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
941 10:51:09.049831 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
942 10:51:09.099553 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
943 10:51:09.153220 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
944 10:51:09.188808 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
945 10:51:09.213337 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
946 10:51:09.242510 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
947 10:51:09.284361 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
948 10:51:09.314646 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
949 10:51:09.351569 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
950 10:51:09.381039 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
951 10:51:09.412379 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
952 10:51:09.442662 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
953 10:51:09.474239 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
954 10:51:09.497475 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
955 10:51:09.528475 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
956 10:51:09.547363 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
957 10:51:09.569642 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
958 10:51:09.648257 Starting [0;1;39malsa-restore.serv…- Save/Restore Sound Card State...
959 10:51:09.691474 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
960 10:51:09.778599 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
961 10:51:09.873476 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
962 10:51:09.926587 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
963 10:51:09.970369 [[0;32m OK [0m] Finished [0;1;39malsa-restore.serv…m - Save/Restore Sound Card State.
964 10:51:09.998959 [[0;32m OK [0m] Reached target [0;1;39msound.target[0m - Sound Card.
965 10:51:10.177822 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
966 10:51:10.228045 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
967 10:51:10.286702 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
968 10:51:10.306813 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
969 10:51:10.380836 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
970 10:51:10.605310 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
971 10:51:10.915920 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
972 10:51:10.965009 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
973 10:51:10.992638 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
974 10:51:11.069638 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
975 10:51:11.254144 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
976 10:51:11.386600
977 10:51:11.390447 Debian GNU/Linux 12 debianworm-armhf login: root (automatic login)
978 10:51:11.390947
979 10:51:11.687540 Linux debian-bookworm-armhf 6.12.0-rc6-next-20241108 #1 SMP Fri Nov 8 10:24:22 UTC 2024 armv7l
980 10:51:11.687940
981 10:51:11.693073 The programs included with the Debian GNU/Linux system are free software;
982 10:51:11.702108 the exact distribution terms for each program are described in the
983 10:51:11.702453 individual files in /usr/share/doc/*/copyright.
984 10:51:11.702674
985 10:51:11.712858 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
986 10:51:11.713191 permitted by applicable law.
987 10:51:16.377297 Unable to match end of the kernel message
989 10:51:16.378243 Setting prompt string to ['/ #']
990 10:51:16.378570 end: 2.4.4.1 login-action (duration 00:00:47) [common]
992 10:51:16.379323 end: 2.4.4 auto-login-action (duration 00:00:48) [common]
993 10:51:16.379622 start: 2.4.5 expect-shell-connection (timeout 00:03:14) [common]
994 10:51:16.379858 Setting prompt string to ['/ #']
995 10:51:16.382322 Forcing a shell prompt, looking for ['/ #']
997 10:51:16.432984 / #
998 10:51:16.434057 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
999 10:51:16.434439 Waiting using forced prompt support (timeout 00:02:30)
1000 10:51:16.438698
1001 10:51:16.444721 end: 2.4.5 expect-shell-connection (duration 00:00:00) [common]
1002 10:51:16.445167 start: 2.4.6 export-device-env (timeout 00:03:14) [common]
1003 10:51:16.445443 Sending with 10 millisecond of delay
1005 10:51:21.439194 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/958645/extract-nfsrootfs-6ziqyt20'
1006 10:51:21.450792 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/958645/extract-nfsrootfs-6ziqyt20'
1007 10:51:21.451691 Sending with 10 millisecond of delay
1009 10:51:23.551795 / # export NFS_SERVER_IP='192.168.6.2'
1010 10:51:23.562787 export NFS_SERVER_IP='192.168.6.2'
1011 10:51:23.563829 end: 2.4.6 export-device-env (duration 00:00:07) [common]
1012 10:51:23.564508 end: 2.4 uboot-commands (duration 00:01:53) [common]
1013 10:51:23.565114 end: 2 uboot-action (duration 00:01:53) [common]
1014 10:51:23.565703 start: 3 lava-test-retry (timeout 00:06:57) [common]
1015 10:51:23.566290 start: 3.1 lava-test-shell (timeout 00:06:57) [common]
1016 10:51:23.566763 Using namespace: common
1018 10:51:23.667938 / # #
1019 10:51:23.668702 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
1020 10:51:23.672677 #
1021 10:51:23.679382 Using /lava-958645
1023 10:51:23.780641 / # export SHELL=/bin/bash
1024 10:51:23.785834 export SHELL=/bin/bash
1026 10:51:23.892388 / # . /lava-958645/environment
1027 10:51:23.897702 . /lava-958645/environment
1029 10:51:24.011754 / # /lava-958645/bin/lava-test-runner /lava-958645/0
1030 10:51:24.012516 Test shell timeout: 10s (minimum of the action and connection timeout)
1031 10:51:24.016073 /lava-958645/bin/lava-test-runner /lava-958645/0
1032 10:51:24.501275 + export TESTRUN_ID=0_timesync-off
1033 10:51:24.508569 + TESTRUN_ID=0_timesync-off
1034 10:51:24.509105 + cd /lava-958645/0/tests/0_timesync-off
1035 10:51:24.509539 ++ cat uuid
1036 10:51:24.525257 + UUID=958645_1.6.2.4.1
1037 10:51:24.525832 + set +x
1038 10:51:24.532864 <LAVA_SIGNAL_STARTRUN 0_timesync-off 958645_1.6.2.4.1>
1039 10:51:24.533400 + systemctl stop systemd-timesyncd
1040 10:51:24.534117 Received signal: <STARTRUN> 0_timesync-off 958645_1.6.2.4.1
1041 10:51:24.534576 Starting test lava.0_timesync-off (958645_1.6.2.4.1)
1042 10:51:24.535099 Skipping test definition patterns.
1043 10:51:24.832729 + set +x
1044 10:51:24.833361 <LAVA_SIGNAL_ENDRUN 0_timesync-off 958645_1.6.2.4.1>
1045 10:51:24.834294 Received signal: <ENDRUN> 0_timesync-off 958645_1.6.2.4.1
1046 10:51:24.835087 Ending use of test pattern.
1047 10:51:24.835719 Ending test lava.0_timesync-off (958645_1.6.2.4.1), duration 0.30
1049 10:51:25.024870 + export TESTRUN_ID=1_kselftest-dt
1050 10:51:25.031889 + TESTRUN_ID=1_kselftest-dt
1051 10:51:25.032665 + cd /lava-958645/0/tests/1_kselftest-dt
1052 10:51:25.033321 ++ cat uuid
1053 10:51:25.049466 + UUID=958645_1.6.2.4.5
1054 10:51:25.050156 + set +x
1055 10:51:25.055046 <LAVA_SIGNAL_STARTRUN 1_kselftest-dt 958645_1.6.2.4.5>
1056 10:51:25.055678 + cd ./automated/linux/kselftest/
1057 10:51:25.056552 Received signal: <STARTRUN> 1_kselftest-dt 958645_1.6.2.4.5
1058 10:51:25.057119 Starting test lava.1_kselftest-dt (958645_1.6.2.4.5)
1059 10:51:25.057773 Skipping test definition patterns.
1060 10:51:25.080067 + ./kselftest.sh -c dt -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/next/master/next-20241108/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz -L '' -S /dev/null -b beaglebone-black -g next -e '' -p /opt/kselftests/mainline/ -n 1 -i 1 -E ''
1061 10:51:25.195441 INFO: install_deps skipped
1062 10:51:25.836088 --2024-11-08 10:51:25-- http://storage.kernelci.org/next/master/next-20241108/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz
1063 10:51:25.876059 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
1064 10:51:26.013017 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
1065 10:51:26.149489 HTTP request sent, awaiting response... 200 OK
1066 10:51:26.150233 Length: 4158336 (4.0M) [application/octet-stream]
1067 10:51:26.154980 Saving to: 'kselftest_armhf.tar.gz'
1068 10:51:26.155615
1069 10:51:27.528305
kselftest_armhf.tar 0%[ ] 0 --.-KB/s
kselftest_armhf.tar 1%[ ] 49.92K 187KB/s
kselftest_armhf.tar 4%[ ] 194.76K 360KB/s
kselftest_armhf.tar 18%[==> ] 749.26K 934KB/s
kselftest_armhf.tar 40%[=======> ] 1.61M 1.52MB/s
kselftest_armhf.tar 60%[===========> ] 2.41M 1.88MB/s
kselftest_armhf.tar 100%[===================>] 3.96M 2.89MB/s in 1.4s
1070 10:51:27.528737
1071 10:51:28.291457 2024-11-08 10:51:27 (2.89 MB/s) - 'kselftest_armhf.tar.gz' saved [4158336/4158336]
1072 10:51:28.292196
1073 10:51:41.093994 skiplist:
1074 10:51:41.094679 ========================================
1075 10:51:41.099736 ========================================
1076 10:51:41.199496 dt:test_unprobed_devices.sh
1077 10:51:41.229995 ============== Tests to run ===============
1078 10:51:41.237834 dt:test_unprobed_devices.sh
1079 10:51:41.241807 ===========End Tests to run ===============
1080 10:51:41.252114 shardfile-dt pass
1081 10:51:41.484285 <12>[ 72.103858] kselftest: Running tests in dt
1082 10:51:41.513177 TAP version 13
1083 10:51:41.536379 1..1
1084 10:51:41.590326 # timeout set to 45
1085 10:51:41.590857 # selftests: dt: test_unprobed_devices.sh
1086 10:51:42.368614 # TAP version 13
1087 10:52:07.510528 # 1..257
1088 10:52:07.686881 # ok 1 / # SKIP
1089 10:52:07.711368 # ok 2 /clk_mcasp0
1090 10:52:07.787753 # ok 3 /clk_mcasp0_fixed # SKIP
1091 10:52:07.863035 # ok 4 /cpus/cpu@0 # SKIP
1092 10:52:07.931780 # ok 5 /cpus/idle-states/mpu_gate # SKIP
1093 10:52:07.956319 # ok 6 /fixedregulator0
1094 10:52:07.976251 # ok 7 /leds
1095 10:52:07.995013 # ok 8 /ocp
1096 10:52:08.023864 # ok 9 /ocp/interconnect@44c00000
1097 10:52:08.048548 # ok 10 /ocp/interconnect@44c00000/segment@0
1098 10:52:08.069681 # ok 11 /ocp/interconnect@44c00000/segment@100000
1099 10:52:08.092659 # ok 12 /ocp/interconnect@44c00000/segment@100000/target-module@0
1100 10:52:08.167913 # not ok 13 /ocp/interconnect@44c00000/segment@100000/target-module@0/cpu@0
1101 10:52:08.188414 # ok 14 /ocp/interconnect@44c00000/segment@200000
1102 10:52:08.211195 # ok 15 /ocp/interconnect@44c00000/segment@200000/target-module@0
1103 10:52:08.315118 # not ok 16 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0
1104 10:52:08.388588 # ok 17 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0 # SKIP
1105 10:52:08.461385 # ok 18 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@0 # SKIP
1106 10:52:08.537496 # ok 19 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@120 # SKIP
1107 10:52:08.606109 # ok 20 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@14c # SKIP
1108 10:52:08.677886 # ok 21 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@18 # SKIP
1109 10:52:08.750712 # ok 22 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@1c # SKIP
1110 10:52:08.821768 # ok 23 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@24 # SKIP
1111 10:52:08.899499 # ok 24 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@38 # SKIP
1112 10:52:08.972374 # ok 25 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@e8 # SKIP
1113 10:52:09.041826 # ok 26 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400 # SKIP
1114 10:52:09.113381 # ok 27 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@0 # SKIP
1115 10:52:09.185584 # ok 28 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@14 # SKIP
1116 10:52:09.262350 # ok 29 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@b0 # SKIP
1117 10:52:09.329838 # ok 30 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600 # SKIP
1118 10:52:09.407709 # ok 31 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600/clock@0 # SKIP
1119 10:52:09.473390 # ok 32 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800 # SKIP
1120 10:52:09.547639 # ok 33 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800/clock@0 # SKIP
1121 10:52:09.619536 # ok 34 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900 # SKIP
1122 10:52:09.693498 # ok 35 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900/clock@0 # SKIP
1123 10:52:09.764045 # ok 36 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00 # SKIP
1124 10:52:09.837771 # ok 37 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00/clock@0 # SKIP
1125 10:52:09.910864 # ok 38 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-24mhz # SKIP
1126 10:52:09.983417 # ok 39 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-32768 # SKIP
1127 10:52:10.055859 # ok 40 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-rc32k # SKIP
1128 10:52:10.128989 # ok 41 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clkdiv32k # SKIP
1129 10:52:10.202031 # ok 42 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-125mhz-gclk # SKIP
1130 10:52:10.281035 # ok 43 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-cpts-rft@520 # SKIP
1131 10:52:10.348970 # ok 44 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4-div2 # SKIP
1132 10:52:10.421404 # ok 45 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4@480 # SKIP
1133 10:52:10.494356 # ok 46 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m5@484 # SKIP
1134 10:52:10.567951 # ok 47 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m6@4d8 # SKIP
1135 10:52:10.640940 # ok 48 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-x2 # SKIP
1136 10:52:10.714252 # ok 49 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2-div2 # SKIP
1137 10:52:10.785885 # ok 50 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2@4a0 # SKIP
1138 10:52:10.858789 # ok 51 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-disp-m2@4a4 # SKIP
1139 10:52:10.931149 # ok 52 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-mpu-m2@4a8 # SKIP
1140 10:52:11.003951 # ok 53 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4 # SKIP
1141 10:52:11.076633 # ok 54 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4-wkupdm # SKIP
1142 10:52:11.149930 # ok 55 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2@4ac # SKIP
1143 10:52:11.223275 # ok 56 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-gpio0-dbclk-mux@53c # SKIP
1144 10:52:11.301105 # ok 57 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-ieee5000-fck-1@e4 # SKIP
1145 10:52:11.372853 # ok 58 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3-gclk # SKIP
1146 10:52:11.443709 # ok 59 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3s-gclk # SKIP
1147 10:52:11.515339 # ok 60 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4-rtc-gclk # SKIP
1148 10:52:11.588230 # ok 61 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4fw-gclk # SKIP
1149 10:52:11.661019 # ok 62 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4hs-gclk # SKIP
1150 10:52:11.735215 # ok 63 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4ls-gclk # SKIP
1151 10:52:11.807178 # ok 64 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-lcd-gclk@534 # SKIP
1152 10:52:11.879500 # ok 65 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmc # SKIP
1153 10:52:11.957684 # ok 66 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmu-fck-1@914 # SKIP
1154 10:52:12.031060 # ok 67 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-pruss-ocp-gclk@530 # SKIP
1155 10:52:12.113044 # ok 68 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-sysclk-div # SKIP
1156 10:52:12.179666 # ok 69 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-tclkin # SKIP
1157 10:52:12.252832 # ok 70 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer1-fck@528 # SKIP
1158 10:52:12.325584 # ok 71 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer2-fck@508 # SKIP
1159 10:52:12.398656 # ok 72 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer3-fck@50c # SKIP
1160 10:52:12.471483 # ok 73 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer4-fck@510 # SKIP
1161 10:52:12.544245 # ok 74 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer5-fck@518 # SKIP
1162 10:52:12.615733 # ok 75 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer6-fck@51c # SKIP
1163 10:52:12.688513 # ok 76 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer7-fck@504 # SKIP
1164 10:52:12.761066 # ok 77 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-usbotg-fck-8@47c # SKIP
1165 10:52:12.833042 # ok 78 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-19200000 # SKIP
1166 10:52:12.910020 # ok 79 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-24000000 # SKIP
1167 10:52:12.983975 # ok 80 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-25000000 # SKIP
1168 10:52:13.053304 # ok 81 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-26000000 # SKIP
1169 10:52:13.125332 # ok 82 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-wdt1-fck@538 # SKIP
1170 10:52:13.197778 # ok 83 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@488 # SKIP
1171 10:52:13.269990 # ok 84 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@48c # SKIP
1172 10:52:13.343189 # ok 85 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@490 # SKIP
1173 10:52:13.414912 # ok 86 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@494 # SKIP
1174 10:52:13.487152 # ok 87 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@498 # SKIP
1175 10:52:13.560082 # ok 88 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c # SKIP
1176 10:52:13.634718 # ok 89 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fck-div@0 # SKIP
1177 10:52:13.712012 # ok 90 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fclk-clksel@1 # SKIP
1178 10:52:13.781904 # ok 91 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700 # SKIP
1179 10:52:13.855033 # ok 92 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2-div@3 # SKIP
1180 10:52:13.924701 # ok 93 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2@7 # SKIP
1181 10:52:13.997540 # ok 94 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-sysclkout-pre@0 # SKIP
1182 10:52:14.018974 # ok 95 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1000
1183 10:52:14.042823 # ok 96 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1100
1184 10:52:14.067269 # ok 97 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1200
1185 10:52:14.091083 # ok 98 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@c00
1186 10:52:14.114367 # ok 99 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@d00
1187 10:52:14.138797 # ok 100 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@e00
1188 10:52:14.163819 # ok 101 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@f00
1189 10:52:14.186543 # ok 102 /ocp/interconnect@44c00000/segment@200000/target-module@10000
1190 10:52:14.292628 # not ok 103 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0
1191 10:52:14.317602 # ok 104 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/control@620
1192 10:52:14.342028 # ok 105 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/dma-router@f90
1193 10:52:14.366121 # ok 106 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800
1194 10:52:14.472349 # not ok 107 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0
1195 10:52:14.550892 # ok 108 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-adc-tsc-fck # SKIP
1196 10:52:14.624746 # ok 109 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-aes0-fck # SKIP
1197 10:52:14.691667 # ok 110 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan0-fck # SKIP
1198 10:52:14.765027 # ok 111 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan1-fck # SKIP
1199 10:52:14.837956 # ok 112 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp0-fck # SKIP
1200 10:52:14.911486 # ok 113 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp1-fck # SKIP
1201 10:52:14.984258 # ok 114 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-rng-fck # SKIP
1202 10:52:15.061697 # ok 115 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sha0-fck # SKIP
1203 10:52:15.134214 # ok 116 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex0-fck # SKIP
1204 10:52:15.203066 # ok 117 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex1-fck # SKIP
1205 10:52:15.281281 # ok 118 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sys-clkin-22@40 # SKIP
1206 10:52:15.348803 # ok 119 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664 # SKIP
1207 10:52:15.423839 # ok 120 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm0-tbclk@0 # SKIP
1208 10:52:15.497821 # ok 121 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm1-tbclk@1 # SKIP
1209 10:52:15.571367 # ok 122 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm2-tbclk@2 # SKIP
1210 10:52:15.592737 # ok 123 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/phy-gmii-sel
1211 10:52:15.666854 # not ok 124 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/wkup_m3_ipc@1324
1212 10:52:15.737362 # not ok 125 /ocp/interconnect@44c00000/segment@200000/target-module@31000
1213 10:52:15.810525 # ok 126 /ocp/interconnect@44c00000/segment@200000/target-module@31000/timer@0 # SKIP
1214 10:52:15.832958 # ok 127 /ocp/interconnect@44c00000/segment@200000/target-module@35000
1215 10:52:15.905339 # not ok 128 /ocp/interconnect@44c00000/segment@200000/target-module@35000/wdt@0
1216 10:52:15.927964 # ok 129 /ocp/interconnect@44c00000/segment@200000/target-module@3e000
1217 10:52:15.999880 # not ok 130 /ocp/interconnect@44c00000/segment@200000/target-module@3e000/rtc@0
1218 10:52:16.022733 # ok 131 /ocp/interconnect@44c00000/segment@200000/target-module@7000
1219 10:52:16.047034 # ok 132 /ocp/interconnect@44c00000/segment@200000/target-module@7000/gpio@0
1220 10:52:16.069025 # ok 133 /ocp/interconnect@44c00000/segment@200000/target-module@9000
1221 10:52:16.095448 # ok 134 /ocp/interconnect@44c00000/segment@200000/target-module@9000/serial@0
1222 10:52:16.117033 # ok 135 /ocp/interconnect@44c00000/segment@200000/target-module@b000
1223 10:52:16.147278 # ok 136 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0
1224 10:52:16.172072 # ok 137 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/eeprom@50
1225 10:52:16.249019 # ok 138 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/eeprom@50/nvmem-layout # SKIP
1226 10:52:16.268317 # ok 139 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
1227 10:52:16.292538 # ok 140 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24
1228 10:52:16.362971 # not ok 141 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/charger
1229 10:52:16.440696 # not ok 142 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/pwrbutton
1230 10:52:16.460662 # ok 143 /ocp/interconnect@44c00000/segment@200000/target-module@d000
1231 10:52:16.558921 # not ok 144 /ocp/interconnect@47c00000
1232 10:52:16.634995 # not ok 145 /ocp/interconnect@47c00000/segment@0
1233 10:52:16.655208 # ok 146 /ocp/interconnect@48000000
1234 10:52:16.675416 # ok 147 /ocp/interconnect@48000000/segment@0
1235 10:52:16.705240 # ok 148 /ocp/interconnect@48000000/segment@0/target-module@22000
1236 10:52:16.724259 # ok 149 /ocp/interconnect@48000000/segment@0/target-module@24000
1237 10:52:16.746329 # ok 150 /ocp/interconnect@48000000/segment@0/target-module@2a000
1238 10:52:16.771277 # ok 151 /ocp/interconnect@48000000/segment@0/target-module@30000
1239 10:52:16.798474 # ok 152 /ocp/interconnect@48000000/segment@0/target-module@38000
1240 10:52:16.820985 # ok 153 /ocp/interconnect@48000000/segment@0/target-module@38000/mcasp@0
1241 10:52:16.841939 # ok 154 /ocp/interconnect@48000000/segment@0/target-module@3c000
1242 10:52:16.918136 # not ok 155 /ocp/interconnect@48000000/segment@0/target-module@40000
1243 10:52:16.991586 # ok 156 /ocp/interconnect@48000000/segment@0/target-module@40000/timer@0 # SKIP
1244 10:52:17.012423 # ok 157 /ocp/interconnect@48000000/segment@0/target-module@42000
1245 10:52:17.039590 # ok 158 /ocp/interconnect@48000000/segment@0/target-module@42000/timer@0
1246 10:52:17.060582 # ok 159 /ocp/interconnect@48000000/segment@0/target-module@44000
1247 10:52:17.083505 # ok 160 /ocp/interconnect@48000000/segment@0/target-module@44000/timer@0
1248 10:52:17.105197 # ok 161 /ocp/interconnect@48000000/segment@0/target-module@46000
1249 10:52:17.131288 # ok 162 /ocp/interconnect@48000000/segment@0/target-module@46000/timer@0
1250 10:52:17.169033 # ok 163 /ocp/interconnect@48000000/segment@0/target-module@48000
1251 10:52:17.179515 # ok 164 /ocp/interconnect@48000000/segment@0/target-module@48000/timer@0
1252 10:52:17.202761 # ok 165 /ocp/interconnect@48000000/segment@0/target-module@4a000
1253 10:52:17.230990 # ok 166 /ocp/interconnect@48000000/segment@0/target-module@4a000/timer@0
1254 10:52:17.259022 # ok 167 /ocp/interconnect@48000000/segment@0/target-module@4c000
1255 10:52:17.280885 # ok 168 /ocp/interconnect@48000000/segment@0/target-module@4c000/gpio@0
1256 10:52:17.307696 # ok 169 /ocp/interconnect@48000000/segment@0/target-module@60000
1257 10:52:17.325496 # ok 170 /ocp/interconnect@48000000/segment@0/target-module@60000/mmc@0
1258 10:52:17.348314 # ok 171 /ocp/interconnect@48000000/segment@0/target-module@c8000
1259 10:52:17.373348 # ok 172 /ocp/interconnect@48000000/segment@0/target-module@c8000/mailbox@0
1260 10:52:17.395500 # ok 173 /ocp/interconnect@48000000/segment@0/target-module@ca000
1261 10:52:17.420141 # ok 174 /ocp/interconnect@48000000/segment@0/target-module@ca000/spinlock@0
1262 10:52:17.440554 # ok 175 /ocp/interconnect@48000000/segment@100000
1263 10:52:17.470715 # ok 176 /ocp/interconnect@48000000/segment@100000/target-module@9c000
1264 10:52:17.490342 # ok 177 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0
1265 10:52:17.564552 # not ok 178 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/eeprom@54
1266 10:52:17.638134 # ok 179 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/eeprom@54/nvmem-layout # SKIP
1267 10:52:17.708653 # not ok 180 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/eeprom@55
1268 10:52:17.782442 # ok 181 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/eeprom@55/nvmem-layout # SKIP
1269 10:52:17.857094 # not ok 182 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/eeprom@56
1270 10:52:17.927597 # ok 183 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/eeprom@56/nvmem-layout # SKIP
1271 10:52:17.998500 # not ok 184 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/eeprom@57
1272 10:52:18.072312 # ok 185 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/eeprom@57/nvmem-layout # SKIP
1273 10:52:18.092073 # ok 186 /ocp/interconnect@48000000/segment@100000/target-module@a0000
1274 10:52:18.115561 # ok 187 /ocp/interconnect@48000000/segment@100000/target-module@a6000
1275 10:52:18.139150 # ok 188 /ocp/interconnect@48000000/segment@100000/target-module@a8000
1276 10:52:18.163668 # ok 189 /ocp/interconnect@48000000/segment@100000/target-module@aa000
1277 10:52:18.186029 # ok 190 /ocp/interconnect@48000000/segment@100000/target-module@ac000
1278 10:52:18.217484 # ok 191 /ocp/interconnect@48000000/segment@100000/target-module@ac000/gpio@0
1279 10:52:18.235023 # ok 192 /ocp/interconnect@48000000/segment@100000/target-module@ae000
1280 10:52:18.261329 # ok 193 /ocp/interconnect@48000000/segment@100000/target-module@ae000/gpio@0
1281 10:52:18.282343 # ok 194 /ocp/interconnect@48000000/segment@100000/target-module@cc000
1282 10:52:18.306384 # ok 195 /ocp/interconnect@48000000/segment@100000/target-module@d0000
1283 10:52:18.328856 # ok 196 /ocp/interconnect@48000000/segment@100000/target-module@d8000
1284 10:52:18.354565 # ok 197 /ocp/interconnect@48000000/segment@100000/target-module@d8000/mmc@0
1285 10:52:18.374973 # ok 198 /ocp/interconnect@48000000/segment@200000
1286 10:52:18.402279 # ok 199 /ocp/interconnect@48000000/segment@200000/target-module@0
1287 10:52:18.477796 # ok 200 /ocp/interconnect@48000000/segment@200000/target-module@0/mpu@0 # SKIP
1288 10:52:18.497887 # ok 201 /ocp/interconnect@48000000/segment@300000
1289 10:52:18.520315 # ok 202 /ocp/interconnect@48000000/segment@300000/target-module@0
1290 10:52:18.542330 # ok 203 /ocp/interconnect@48000000/segment@300000/target-module@10000
1291 10:52:18.571129 # ok 204 /ocp/interconnect@48000000/segment@300000/target-module@10000/rng@0
1292 10:52:18.598256 # ok 205 /ocp/interconnect@48000000/segment@300000/target-module@2000
1293 10:52:18.613588 # ok 206 /ocp/interconnect@48000000/segment@300000/target-module@4000
1294 10:52:18.638415 # ok 207 /ocp/interconnect@48000000/segment@300000/target-module@e000
1295 10:52:18.714539 # not ok 208 /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
1296 10:52:18.729022 # ok 209 /ocp/interconnect@4a000000
1297 10:52:18.753288 # ok 210 /ocp/interconnect@4a000000/segment@0
1298 10:52:18.778104 # ok 211 /ocp/interconnect@4a000000/segment@0/target-module@100000
1299 10:52:18.803301 # ok 212 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0
1300 10:52:18.828030 # ok 213 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0/mdio@1000
1301 10:52:18.849752 # ok 214 /ocp/interconnect@4a000000/segment@0/target-module@300000
1302 10:52:18.925773 # not ok 215 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0
1303 10:52:19.031709 # ok 216 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/cfg@26000 # SKIP
1304 10:52:19.101706 # not ok 217 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/interrupt-controller@20000
1305 10:52:19.206674 # ok 218 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/mii-rt@32000 # SKIP
1306 10:52:19.277147 # not ok 219 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@34000
1307 10:52:19.348392 # not ok 220 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@38000
1308 10:52:19.448693 # not ok 221 /ocp/interconnect@4b140000
1309 10:52:19.520975 # not ok 222 /ocp/interconnect@4b140000/segment@0
1310 10:52:19.592090 # ok 223 /ocp/interrupt-controller@48200000 # SKIP
1311 10:52:19.617319 # ok 224 /ocp/target-module@40300000
1312 10:52:19.638289 # ok 225 /ocp/target-module@40300000/sram@0
1313 10:52:19.713208 # ok 226 /ocp/target-module@40300000/sram@0/pm-code-sram@0 # SKIP
1314 10:52:19.782043 # ok 227 /ocp/target-module@40300000/sram@0/pm-data-sram@1000 # SKIP
1315 10:52:19.802234 # ok 228 /ocp/target-module@47400000
1316 10:52:19.827163 # ok 229 /ocp/target-module@47400000/dma-controller@2000
1317 10:52:19.849472 # ok 230 /ocp/target-module@47400000/usb-phy@1300
1318 10:52:19.876568 # ok 231 /ocp/target-module@47400000/usb-phy@1b00
1319 10:52:19.898371 # ok 232 /ocp/target-module@47400000/usb@1400
1320 10:52:19.917577 # ok 233 /ocp/target-module@47400000/usb@1800
1321 10:52:19.943939 # ok 234 /ocp/target-module@47810000
1322 10:52:19.966506 # ok 235 /ocp/target-module@49000000
1323 10:52:19.985153 # ok 236 /ocp/target-module@49000000/dma@0
1324 10:52:20.007711 # ok 237 /ocp/target-module@49800000
1325 10:52:20.030420 # ok 238 /ocp/target-module@49800000/dma@0
1326 10:52:20.056070 # ok 239 /ocp/target-module@49900000
1327 10:52:20.078326 # ok 240 /ocp/target-module@49900000/dma@0
1328 10:52:20.101527 # ok 241 /ocp/target-module@49a00000
1329 10:52:20.124568 # ok 242 /ocp/target-module@49a00000/dma@0
1330 10:52:20.147858 # ok 243 /ocp/target-module@4c000000
1331 10:52:20.218304 # not ok 244 /ocp/target-module@4c000000/emif@0
1332 10:52:20.243562 # ok 245 /ocp/target-module@50000000
1333 10:52:20.265539 # ok 246 /ocp/target-module@53100000
1334 10:52:20.333230 # not ok 247 /ocp/target-module@53100000/sham@0
1335 10:52:20.358034 # ok 248 /ocp/target-module@53500000
1336 10:52:20.434922 # not ok 249 /ocp/target-module@53500000/aes@0
1337 10:52:20.451579 # ok 250 /ocp/target-module@56000000
1338 10:52:20.559274 # ok 251 /ocp/target-module@56000000/gpu@0 # SKIP
1339 10:52:20.627013 # ok 252 /opp-table # SKIP
1340 10:52:20.700193 # ok 253 /soc # SKIP
1341 10:52:20.721849 # ok 254 /sound
1342 10:52:20.740228 # ok 255 /target-module@4b000000
1343 10:52:20.764812 # ok 256 /target-module@4b000000/target-module@140000
1344 10:52:20.786699 # ok 257 /target-module@4b000000/target-module@140000/pmu@0
1345 10:52:20.794949 # # Totals: pass:117 fail:27 xfail:0 xpass:0 skip:113 error:0
1346 10:52:20.803617 not ok 1 selftests: dt: test_unprobed_devices.sh # exit=1
1347 10:52:23.090090 dt_test_unprobed_devices_sh_ skip
1348 10:52:23.095921 dt_test_unprobed_devices_sh_clk_mcasp0 pass
1349 10:52:23.101481 dt_test_unprobed_devices_sh_clk_mcasp0_fixed skip
1350 10:52:23.102016 dt_test_unprobed_devices_sh_cpus_cpu_0 skip
1351 10:52:23.110351 dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate skip
1352 10:52:23.110892 dt_test_unprobed_devices_sh_fixedregulator0 pass
1353 10:52:23.115810 dt_test_unprobed_devices_sh_leds pass
1354 10:52:23.121407 dt_test_unprobed_devices_sh_ocp pass
1355 10:52:23.125199 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 pass
1356 10:52:23.130737 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 pass
1357 10:52:23.136461 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 pass
1358 10:52:23.145704 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 pass
1359 10:52:23.151252 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 fail
1360 10:52:23.162524 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 pass
1361 10:52:23.166035 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 pass
1362 10:52:23.176967 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 fail
1363 10:52:23.186403 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 skip
1364 10:52:23.198060 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 skip
1365 10:52:23.203358 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 skip
1366 10:52:23.217612 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c skip
1367 10:52:23.226489 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 skip
1368 10:52:23.237739 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c skip
1369 10:52:23.248941 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 skip
1370 10:52:23.254650 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 skip
1371 10:52:23.265795 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 skip
1372 10:52:23.276954 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 skip
1373 10:52:23.288149 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 skip
1374 10:52:23.293673 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 skip
1375 10:52:23.305061 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 skip
1376 10:52:23.316243 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 skip
1377 10:52:23.327336 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 skip
1378 10:52:23.332980 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 skip
1379 10:52:23.344205 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 skip
1380 10:52:23.355230 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 skip
1381 10:52:23.366405 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 skip
1382 10:52:23.372057 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 skip
1383 10:52:23.383170 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 skip
1384 10:52:23.394377 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz skip
1385 10:52:23.405611 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 skip
1386 10:52:23.416861 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k skip
1387 10:52:23.428023 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k skip
1388 10:52:23.439247 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk skip
1389 10:52:23.450338 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 skip
1390 10:52:23.461544 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 skip
1391 10:52:23.472830 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 skip
1392 10:52:23.483938 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 skip
1393 10:52:23.495278 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 skip
1394 10:52:23.506369 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 skip
1395 10:52:23.517522 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 skip
1396 10:52:23.528715 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 skip
1397 10:52:23.539925 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 skip
1398 10:52:23.551078 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 skip
1399 10:52:23.562255 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 skip
1400 10:52:23.573503 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm skip
1401 10:52:23.584572 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac skip
1402 10:52:23.595776 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c skip
1403 10:52:23.607029 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 skip
1404 10:52:23.618235 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk skip
1405 10:52:23.629429 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk skip
1406 10:52:23.640634 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk skip
1407 10:52:23.646251 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk skip
1408 10:52:23.657397 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk skip
1409 10:52:23.668577 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk skip
1410 10:52:23.679801 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 skip
1411 10:52:23.691034 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc skip
1412 10:52:23.702135 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 skip
1413 10:52:23.713413 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 skip
1414 10:52:23.724564 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div skip
1415 10:52:23.735747 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin skip
1416 10:52:23.746957 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 skip
1417 10:52:23.758116 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 skip
1418 10:52:23.769347 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c skip
1419 10:52:23.780543 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 skip
1420 10:52:23.791649 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 skip
1421 10:52:23.802914 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c skip
1422 10:52:23.814074 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 skip
1423 10:52:23.825272 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c skip
1424 10:52:23.830865 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 skip
1425 10:52:23.842057 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 skip
1426 10:52:23.853326 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 skip
1427 10:52:23.864456 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 skip
1428 10:52:23.875697 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 skip
1429 10:52:23.886929 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 skip
1430 10:52:23.898080 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c skip
1431 10:52:23.909389 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 skip
1432 10:52:23.914828 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 skip
1433 10:52:23.926122 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 skip
1434 10:52:23.937151 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c skip
1435 10:52:23.948366 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 skip
1436 10:52:23.959595 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 skip
1437 10:52:23.970764 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 skip
1438 10:52:23.981915 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 skip
1439 10:52:23.993122 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 skip
1440 10:52:24.004363 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 skip
1441 10:52:24.015518 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 pass
1442 10:52:24.026734 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 pass
1443 10:52:24.032350 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 pass
1444 10:52:24.043462 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 pass
1445 10:52:24.054668 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 pass
1446 10:52:24.060292 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 pass
1447 10:52:24.071501 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 pass
1448 10:52:24.082683 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 pass
1449 10:52:24.088301 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 fail
1450 10:52:24.099476 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 pass
1451 10:52:24.110725 dt_test_unprobed_devices_sh_ocp_interconnect_44c00040_segment_200000_target-module_10000_scm_0_dma-router_f90 pass
1452 10:52:24.116325 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 pass
1453 10:52:24.127476 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 fail
1454 10:52:24.138746 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck skip
1455 10:52:24.149815 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck skip
1456 10:52:24.166571 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck skip
1457 10:52:24.177779 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck skip
1458 10:52:24.189150 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck skip
1459 10:52:24.200232 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck skip
1460 10:52:24.211350 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck skip
1461 10:52:24.222592 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck skip
1462 10:52:24.233722 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck skip
1463 10:52:24.250529 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck skip
1464 10:52:24.261710 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 skip
1465 10:52:24.272888 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 skip
1466 10:52:24.284238 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 skip
1467 10:52:24.295321 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 skip
1468 10:52:24.312074 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 skip
1469 10:52:24.323308 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel pass
1470 10:52:24.334447 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 fail
1471 10:52:24.340060 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 fail
1472 10:52:24.351204 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 skip
1473 10:52:24.356812 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 pass
1474 10:52:24.368087 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 fail
1475 10:52:24.374588 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 pass
1476 10:52:24.384826 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 fail
1477 10:52:24.390411 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 pass
1478 10:52:24.401630 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 pass
1479 10:52:24.407244 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 pass
1480 10:52:24.418478 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 pass
1481 10:52:24.424060 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 pass
1482 10:52:24.435221 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 pass
1483 10:52:24.446397 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_eeprom_50 pass
1484 10:52:24.457677 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_eeprom_50_nvmem-layout skip
1485 10:52:24.463395 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 pass
1486 10:52:24.474769 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 pass
1487 10:52:24.486012 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger fail
1488 10:52:24.496869 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton fail
1489 10:52:24.502443 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 pass
1490 10:52:24.508100 dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 fail
1491 10:52:24.513632 dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 fail
1492 10:52:24.519251 dt_test_unprobed_devices_sh_ocp_interconnect_48000000 pass
1493 10:52:24.524799 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 pass
1494 10:52:24.536055 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 pass
1495 10:52:24.541739 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 pass
1496 10:52:24.547197 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 pass
1497 10:52:24.558365 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 pass
1498 10:52:24.565021 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 pass
1499 10:52:24.575157 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 pass
1500 10:52:24.580765 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 pass
1501 10:52:24.591821 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 fail
1502 10:52:24.597477 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 skip
1503 10:52:24.608682 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 pass
1504 10:52:24.614369 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 pass
1505 10:52:24.620018 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 pass
1506 10:52:24.631231 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 pass
1507 10:52:24.636761 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 pass
1508 10:52:24.647922 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 pass
1509 10:52:24.653541 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 pass
1510 10:52:24.664685 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 pass
1511 10:52:24.670275 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 pass
1512 10:52:24.681495 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 pass
1513 10:52:24.687110 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 pass
1514 10:52:24.698365 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 pass
1515 10:52:24.703894 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 pass
1516 10:52:24.715077 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 pass
1517 10:52:24.720688 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 pass
1518 10:52:24.731810 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 pass
1519 10:52:24.737434 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 pass
1520 10:52:24.748621 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 pass
1521 10:52:24.754237 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 pass
1522 10:52:24.759844 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 pass
1523 10:52:24.771031 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 pass
1524 10:52:24.782236 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_54 fail
1525 10:52:24.787850 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_54_nvmem-layout skip
1526 10:52:24.799005 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_55 fail
1527 10:52:24.810194 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_55_nvmem-layout skip
1528 10:52:24.821471 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_56 fail
1529 10:52:24.832523 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_56_nvmem-layout skip
1530 10:52:24.843758 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_57 fail
1531 10:52:24.849310 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_57_nvmem-layout skip
1532 10:52:24.860561 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 pass
1533 10:52:24.866166 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 pass
1534 10:52:24.877336 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 pass
1535 10:52:24.882963 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 pass
1536 10:52:24.894138 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 pass
1537 10:52:24.905286 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 pass
1538 10:52:24.910852 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 pass
1539 10:52:24.922129 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 pass
1540 10:52:24.927663 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 pass
1541 10:52:24.938924 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 pass
1542 10:52:24.944456 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 pass
1543 10:52:24.955713 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 pass
1544 10:52:24.961284 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 pass
1545 10:52:24.966869 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 pass
1546 10:52:24.978084 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 skip
1547 10:52:24.983648 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 pass
1548 10:52:24.989261 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 pass
1549 10:52:25.000490 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 pass
1550 10:52:25.006012 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 pass
1551 10:52:25.017229 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 pass
1552 10:52:25.022784 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 pass
1553 10:52:25.034009 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 pass
1554 10:52:25.039622 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 fail
1555 10:52:25.045160 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 pass
1556 10:52:25.050927 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 pass
1557 10:52:25.061998 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 pass
1558 10:52:25.067560 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 pass
1559 10:52:25.078839 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 pass
1560 10:52:25.090001 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 pass
1561 10:52:25.095555 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 fail
1562 10:52:25.106774 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 skip
1563 10:52:25.117933 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 fail
1564 10:52:25.123454 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 skip
1565 10:52:25.134709 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 fail
1566 10:52:25.145977 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 fail
1567 10:52:25.151534 dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 fail
1568 10:52:25.157112 dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 fail
1569 10:52:25.162830 dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 skip
1570 10:52:25.169023 dt_test_unprobed_devices_sh_ocp_target-module_40300000 pass
1571 10:52:25.173995 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 pass
1572 10:52:25.179574 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 skip
1573 10:52:25.190842 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 skip
1574 10:52:25.196429 dt_test_unprobed_devices_sh_ocp_target-module_47400000 pass
1575 10:52:25.202009 dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 pass
1576 10:52:25.207617 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 pass
1577 10:52:25.213188 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 pass
1578 10:52:25.218804 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 pass
1579 10:52:25.224315 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 pass
1580 10:52:25.230049 dt_test_unprobed_devices_sh_ocp_target-module_47810000 pass
1581 10:52:25.235568 dt_test_unprobed_devices_sh_ocp_target-module_49000000 pass
1582 10:52:25.241189 dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 pass
1583 10:52:25.246726 dt_test_unprobed_devices_sh_ocp_target-module_49800000 pass
1584 10:52:25.252459 dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 pass
1585 10:52:25.257995 dt_test_unprobed_devices_sh_ocp_target-module_49900000 pass
1586 10:52:25.263824 dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 pass
1587 10:52:25.269317 dt_test_unprobed_devices_sh_ocp_target-module_49a00000 pass
1588 10:52:25.274907 dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 pass
1589 10:52:25.280543 dt_test_unprobed_devices_sh_ocp_target-module_4c000000 pass
1590 10:52:25.294792 dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 fail
1591 10:52:25.295746 dt_test_unprobed_devices_sh_ocp_target-module_50000000 pass
1592 10:52:25.296668 dt_test_unprobed_devices_sh_ocp_target-module_53100000 pass
1593 10:52:25.302048 dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 fail
1594 10:52:25.308073 dt_test_unprobed_devices_sh_ocp_target-module_53500000 pass
1595 10:52:25.313329 dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 fail
1596 10:52:25.320546 dt_test_unprobed_devices_sh_ocp_target-module_56000000 pass
1597 10:52:25.326265 dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 skip
1598 10:52:25.331792 dt_test_unprobed_devices_sh_opp-table skip
1599 10:52:25.332347 dt_test_unprobed_devices_sh_soc skip
1600 10:52:25.337351 dt_test_unprobed_devices_sh_sound pass
1601 10:52:25.342971 dt_test_unprobed_devices_sh_target-module_4b000000 pass
1602 10:52:25.348586 dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 pass
1603 10:52:25.354207 dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 pass
1604 10:52:25.359841 dt_test_unprobed_devices_sh fail
1605 10:52:25.365391 + ../../utils/send-to-lava.sh ./output/result.txt
1606 10:52:25.370979 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-dt RESULT=pass>
1607 10:52:25.371895 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-dt RESULT=pass
1609 10:52:25.376942 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip>
1610 10:52:25.377826 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip
1612 10:52:25.466477 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass>
1613 10:52:25.467377 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass
1615 10:52:25.551812 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip>
1616 10:52:25.552877 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip
1618 10:52:25.641323 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip>
1619 10:52:25.642211 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip
1621 10:52:25.735881 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip>
1622 10:52:25.736872 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip
1624 10:52:25.830051 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass>
1625 10:52:25.830680 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass
1627 10:52:25.917155 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass>
1628 10:52:25.917787 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass
1630 10:52:26.007465 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass>
1631 10:52:26.008057 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass
1633 10:52:26.094616 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass>
1634 10:52:26.095520 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass
1636 10:52:26.186129 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass>
1637 10:52:26.187028 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass
1639 10:52:26.278167 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass>
1640 10:52:26.279055 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass
1642 10:52:26.365871 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass>
1643 10:52:26.366752 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass
1645 10:52:26.461045 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail>
1646 10:52:26.461966 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail
1648 10:52:26.544046 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass>
1649 10:52:26.545034 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass
1651 10:52:26.633859 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass>
1652 10:52:26.635294 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass
1654 10:52:26.839205 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail>
1655 10:52:26.839874 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail
1657 10:52:26.944596 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip>
1658 10:52:26.945474 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip
1660 10:52:27.035416 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip>
1661 10:52:27.036302 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip
1663 10:52:27.122503 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip>
1664 10:52:27.123342 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip
1666 10:52:27.213986 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip>
1667 10:52:27.214837 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip
1669 10:52:27.300999 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip>
1670 10:52:27.301860 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip
1672 10:52:27.392148 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip>
1673 10:52:27.393021 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip
1675 10:52:27.483273 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip>
1676 10:52:27.484159 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip
1678 10:52:27.570468 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip>
1679 10:52:27.571403 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip
1681 10:52:27.659059 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip>
1682 10:52:27.659950 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip
1684 10:52:27.742762 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip>
1685 10:52:27.744140 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip
1687 10:52:27.827830 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip>
1688 10:52:27.828895 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip
1690 10:52:27.918575 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip>
1691 10:52:27.919747 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip
1693 10:52:28.009375 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip>
1694 10:52:28.010572 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip
1696 10:52:28.098063 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip>
1697 10:52:28.098989 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip
1699 10:52:28.184063 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip>
1700 10:52:28.185137 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip
1702 10:52:28.267932 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip>
1703 10:52:28.269431 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip
1705 10:52:28.354004 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip>
1706 10:52:28.354876 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip
1708 10:52:28.440230 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip>
1709 10:52:28.440996 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip
1711 10:52:28.533929 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip>
1712 10:52:28.534879 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip
1714 10:52:28.622656 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip>
1715 10:52:28.623638 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip
1717 10:52:28.714597 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip>
1718 10:52:28.715559 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip
1720 10:52:28.805162 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip>
1721 10:52:28.806090 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip
1723 10:52:28.889601 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip>
1724 10:52:28.890481 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip
1726 10:52:28.975257 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip>
1727 10:52:28.976121 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip
1729 10:52:29.061503 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip>
1730 10:52:29.062413 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip
1732 10:52:29.153292 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip>
1733 10:52:29.154172 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip
1735 10:52:29.240367 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip>
1736 10:52:29.241202 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip
1738 10:52:29.330200 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip>
1739 10:52:29.331149 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip
1741 10:52:29.422223 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip>
1742 10:52:29.423147 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip
1744 10:52:29.511825 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip>
1745 10:52:29.512796 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip
1747 10:52:29.596511 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip>
1748 10:52:29.597300 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip
1750 10:52:29.682271 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip>
1751 10:52:29.683179 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip
1753 10:52:29.773584 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip>
1754 10:52:29.774502 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip
1756 10:52:29.860648 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip>
1757 10:52:29.861555 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip
1759 10:52:29.950606 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip>
1760 10:52:29.951865 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip
1762 10:52:30.037635 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip>
1763 10:52:30.038624 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip
1765 10:52:30.123442 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip>
1766 10:52:30.124386 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip
1768 10:52:30.215325 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip>
1769 10:52:30.216196 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip
1771 10:52:30.300522 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip>
1772 10:52:30.301377 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip
1774 10:52:30.393914 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip>
1775 10:52:30.394751 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip
1777 10:52:30.479379 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip>
1778 10:52:30.480298 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip
1780 10:52:30.569399 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip>
1781 10:52:30.570267 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip
1783 10:52:30.659355 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip>
1784 10:52:30.660272 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip
1786 10:52:30.744042 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip>
1787 10:52:30.744882 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip
1789 10:52:30.829557 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip>
1790 10:52:30.830398 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip
1792 10:52:30.913811 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip>
1793 10:52:30.914665 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip
1795 10:52:30.999371 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip>
1796 10:52:31.000196 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip
1798 10:52:31.091665 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip>
1799 10:52:31.092568 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip
1801 10:52:31.177089 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip>
1802 10:52:31.177990 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip
1804 10:52:31.264977 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip>
1805 10:52:31.265894 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip
1807 10:52:31.361737 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip>
1808 10:52:31.362645 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip
1810 10:52:31.451378 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip>
1811 10:52:31.452345 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip
1813 10:52:31.541899 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip>
1814 10:52:31.542814 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip
1816 10:52:31.625647 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip>
1817 10:52:31.626550 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip
1819 10:52:31.712943 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip>
1820 10:52:31.713856 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip
1822 10:52:31.805376 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip>
1823 10:52:31.806292 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip
1825 10:52:31.888864 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip>
1826 10:52:31.889769 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip
1828 10:52:31.975567 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip>
1829 10:52:31.976530 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip
1831 10:52:32.064893 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip>
1832 10:52:32.065785 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip
1834 10:52:32.157143 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip>
1835 10:52:32.158049 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip
1837 10:52:32.243229 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip>
1838 10:52:32.244149 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip
1840 10:52:32.332172 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip>
1841 10:52:32.333101 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip
1843 10:52:32.423913 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip>
1844 10:52:32.424863 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip
1846 10:52:32.509176 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip>
1847 10:52:32.510145 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip
1849 10:52:32.601290 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip>
1850 10:52:32.602396 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip
1852 10:52:32.686824 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip>
1853 10:52:32.687831 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip
1855 10:52:32.771790 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip>
1856 10:52:32.772805 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip
1858 10:52:32.856667 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip>
1859 10:52:32.857526 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip
1861 10:52:32.951337 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip>
1862 10:52:32.952394 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip
1864 10:52:33.042607 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip>
1865 10:52:33.043486 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip
1867 10:52:33.129426 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip>
1868 10:52:33.130293 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip
1870 10:52:33.221422 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip>
1871 10:52:33.222295 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip
1873 10:52:33.314620 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip>
1874 10:52:33.315484 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip
1876 10:52:33.400610 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip>
1877 10:52:33.401536 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip
1879 10:52:33.492569 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip>
1880 10:52:33.493418 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip
1882 10:52:33.585439 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip>
1883 10:52:33.586235 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip
1885 10:52:33.670745 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip>
1886 10:52:33.671444 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip
1888 10:52:33.758181 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip>
1889 10:52:33.758866 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip
1891 10:52:33.844461 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass>
1892 10:52:33.845088 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass
1894 10:52:33.930949 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass>
1895 10:52:33.931553 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass
1897 10:52:34.022354 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass>
1898 10:52:34.023003 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass
1900 10:52:34.106350 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass>
1901 10:52:34.107105 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass
1903 10:52:34.197916 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass>
1904 10:52:34.198812 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass
1906 10:52:34.282215 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass>
1907 10:52:34.283078 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass
1909 10:52:34.368149 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass>
1910 10:52:34.369073 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass
1912 10:52:34.458680 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass>
1913 10:52:34.459667 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass
1915 10:52:34.545206 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail>
1916 10:52:34.546106 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail
1918 10:52:34.639383 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass>
1919 10:52:34.640436 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass
1921 10:52:34.729049 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass>
1922 10:52:34.729650 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass
1924 10:52:34.814214 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass>
1925 10:52:34.814822 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass
1927 10:52:34.905224 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail>
1928 10:52:34.905871 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail
1930 10:52:34.994825 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip>
1931 10:52:34.995453 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip
1933 10:52:35.087129 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip>
1934 10:52:35.088045 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip
1936 10:52:35.180790 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip>
1937 10:52:35.181682 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip
1939 10:52:35.272095 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip>
1940 10:52:35.272755 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip
1942 10:52:35.358516 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip>
1943 10:52:35.359216 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip
1945 10:52:35.451626 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip>
1946 10:52:35.452575 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip
1948 10:52:35.541566 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip>
1949 10:52:35.542440 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip
1951 10:52:35.626237 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip>
1952 10:52:35.627049 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip
1954 10:52:35.711549 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip>
1955 10:52:35.712431 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip
1957 10:52:35.797352 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip>
1958 10:52:35.798215 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip
1960 10:52:35.891361 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip>
1961 10:52:35.892189 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip
1963 10:52:35.983439 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip>
1964 10:52:35.984085 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip
1966 10:52:36.072552 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip
1968 10:52:36.075574 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip>
1969 10:52:36.159962 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip
1971 10:52:36.163086 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip>
1972 10:52:36.248519 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip
1974 10:52:36.251617 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip>
1975 10:52:36.335208 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass>
1976 10:52:36.336031 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass
1978 10:52:36.420989 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail>
1979 10:52:36.421877 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail
1981 10:52:36.511479 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail>
1982 10:52:36.512393 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail
1984 10:52:36.597619 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip>
1985 10:52:36.598474 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip
1987 10:52:36.688585 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass>
1988 10:52:36.689397 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass
1990 10:52:36.780022 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail>
1991 10:52:36.780849 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail
1993 10:52:36.867927 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass>
1994 10:52:36.868779 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass
1996 10:52:36.957722 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail>
1997 10:52:36.958544 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail
1999 10:52:37.043521 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass>
2000 10:52:37.044402 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass
2002 10:52:37.137531 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass>
2003 10:52:37.138352 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass
2005 10:52:37.228168 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass>
2006 10:52:37.228986 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass
2008 10:52:37.320262 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass>
2009 10:52:37.321083 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass
2011 10:52:37.411735 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass>
2012 10:52:37.412604 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass
2014 10:52:37.498832 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass>
2015 10:52:37.499667 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass
2017 10:52:37.586137 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_eeprom_50 RESULT=pass>
2018 10:52:37.586989 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_eeprom_50 RESULT=pass
2020 10:52:37.678852 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_eeprom_50_nvmem-layout RESULT=skip>
2021 10:52:37.679652 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_eeprom_50_nvmem-layout RESULT=skip
2023 10:52:37.769961 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass>
2024 10:52:37.770794 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass
2026 10:52:37.860405 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass>
2027 10:52:37.861217 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass
2029 10:52:37.950507 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail>
2030 10:52:37.951396 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail
2032 10:52:38.036026 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail>
2033 10:52:38.036948 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail
2035 10:52:38.126779 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass>
2036 10:52:38.127656 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass
2038 10:52:38.210196 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail>
2039 10:52:38.211170 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail
2041 10:52:38.300211 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail>
2042 10:52:38.301072 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail
2044 10:52:38.390155 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass>
2045 10:52:38.390995 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass
2047 10:52:38.476551 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass>
2048 10:52:38.477449 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass
2050 10:52:38.569970 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass>
2051 10:52:38.570812 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass
2053 10:52:38.656945 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass>
2054 10:52:38.657729 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass
2056 10:52:38.746864 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass>
2057 10:52:38.747650 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass
2059 10:52:38.838540 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass>
2060 10:52:38.839355 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass
2062 10:52:38.923493 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass>
2063 10:52:38.924299 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass
2065 10:52:39.014794 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass>
2066 10:52:39.015587 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass
2068 10:52:39.106124 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass>
2069 10:52:39.106915 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass
2071 10:52:39.196987 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail>
2072 10:52:39.197769 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail
2074 10:52:39.288553 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip>
2075 10:52:39.289343 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip
2077 10:52:39.377753 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass>
2078 10:52:39.378541 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass
2080 10:52:39.466941 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass>
2081 10:52:39.467743 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass
2083 10:52:39.557542 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass>
2084 10:52:39.558362 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass
2086 10:52:39.649318 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass>
2087 10:52:39.650111 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass
2089 10:52:39.733688 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass>
2090 10:52:39.734495 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass
2092 10:52:39.824751 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass>
2093 10:52:39.825511 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass
2095 10:52:39.909776 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass>
2096 10:52:39.910511 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass
2098 10:52:39.996869 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass>
2099 10:52:39.997627 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass
2101 10:52:40.087602 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass>
2102 10:52:40.088397 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass
2104 10:52:40.173742 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass>
2105 10:52:40.174499 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass
2107 10:52:40.264981 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass>
2108 10:52:40.265728 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass
2110 10:52:40.358542 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass>
2111 10:52:40.359286 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass
2113 10:52:40.447214 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass>
2114 10:52:40.448031 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass
2116 10:52:40.533280 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass>
2117 10:52:40.534099 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass
2119 10:52:40.618729 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass>
2120 10:52:40.619548 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass
2122 10:52:40.710414 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass>
2123 10:52:40.711189 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass
2125 10:52:40.796221 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass>
2126 10:52:40.797024 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass
2128 10:52:40.887116 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass>
2129 10:52:40.887848 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass
2131 10:52:40.969938 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass>
2132 10:52:40.970682 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass
2134 10:52:41.064561 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass>
2135 10:52:41.065390 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass
2137 10:52:41.156274 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass>
2138 10:52:41.157011 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass
2140 10:52:41.249558 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_54 RESULT=fail>
2141 10:52:41.250390 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_54 RESULT=fail
2143 10:52:41.339594 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_54_nvmem-layout RESULT=skip>
2144 10:52:41.340426 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_54_nvmem-layout RESULT=skip
2146 10:52:41.430850 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_55 RESULT=fail>
2147 10:52:41.431689 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_55 RESULT=fail
2149 10:52:41.524310 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_55_nvmem-layout RESULT=skip>
2150 10:52:41.525136 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_55_nvmem-layout RESULT=skip
2152 10:52:41.608912 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_56 RESULT=fail>
2153 10:52:41.609742 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_56 RESULT=fail
2155 10:52:41.700566 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_56_nvmem-layout RESULT=skip>
2156 10:52:41.701349 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_56_nvmem-layout RESULT=skip
2158 10:52:41.791355 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_57 RESULT=fail>
2159 10:52:41.792168 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_57 RESULT=fail
2161 10:52:41.886412 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_57_nvmem-layout RESULT=skip>
2162 10:52:41.887423 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_57_nvmem-layout RESULT=skip
2164 10:52:41.985263 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass>
2165 10:52:41.986223 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass
2167 10:52:42.091227 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass>
2168 10:52:42.092109 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass
2170 10:52:42.182893 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass>
2171 10:52:42.183662 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass
2173 10:52:42.272476 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass>
2174 10:52:42.273252 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass
2176 10:52:42.357405 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass>
2177 10:52:42.358187 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass
2179 10:52:42.446495 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass>
2180 10:52:42.447294 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass
2182 10:52:42.532515 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass>
2183 10:52:42.533333 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass
2185 10:52:42.622850 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass>
2186 10:52:42.623649 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass
2188 10:52:42.706438 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass>
2189 10:52:42.707292 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass
2191 10:52:42.792175 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass>
2192 10:52:42.792953 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass
2194 10:52:42.877779 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass>
2195 10:52:42.878561 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass
2197 10:52:42.968909 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass>
2198 10:52:42.969710 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass
2200 10:52:43.051969 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass>
2201 10:52:43.052833 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass
2203 10:52:43.143774 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass>
2204 10:52:43.144615 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass
2206 10:52:43.230837 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip>
2207 10:52:43.231612 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip
2209 10:52:43.321949 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass>
2210 10:52:43.322743 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass
2212 10:52:43.415283 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass>
2213 10:52:43.416141 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass
2215 10:52:43.507141 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass>
2216 10:52:43.507970 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass
2218 10:52:43.598230 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass>
2219 10:52:43.599107 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass
2221 10:52:43.683151 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass>
2222 10:52:43.684182 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass
2224 10:52:43.768630 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass>
2225 10:52:43.769486 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass
2227 10:52:43.859012 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass>
2228 10:52:43.859819 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass
2230 10:52:43.944748 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail>
2231 10:52:43.945645 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail
2233 10:52:44.031529 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass>
2234 10:52:44.032413 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass
2236 10:52:44.122673 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass>
2237 10:52:44.123717 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass
2239 10:52:44.209417 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass>
2240 10:52:44.210181 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass
2242 10:52:44.301618 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass>
2243 10:52:44.302398 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass
2245 10:52:44.387101 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass>
2246 10:52:44.387921 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass
2248 10:52:44.477388 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass>
2249 10:52:44.478273 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass
2251 10:52:44.563517 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail>
2252 10:52:44.564431 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail
2254 10:52:44.655358 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip>
2255 10:52:44.656169 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip
2257 10:52:44.743761 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail>
2258 10:52:44.744599 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail
2260 10:52:44.833643 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip>
2261 10:52:44.834556 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip
2263 10:52:44.924337 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail>
2264 10:52:44.925132 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail
2266 10:52:45.010071 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail>
2267 10:52:45.010864 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail
2269 10:52:45.090853 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail>
2270 10:52:45.091668 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail
2272 10:52:45.177139 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail>
2273 10:52:45.177890 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail
2275 10:52:45.267047 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip>
2276 10:52:45.267802 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip
2278 10:52:45.350935 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass>
2279 10:52:45.351716 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass
2281 10:52:45.443462 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass>
2282 10:52:45.444279 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass
2284 10:52:45.536676 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip>
2285 10:52:45.537492 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip
2287 10:52:45.624437 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip
2289 10:52:45.627548 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip>
2290 10:52:45.710539 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass>
2291 10:52:45.711319 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass
2293 10:52:45.803047 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass>
2294 10:52:45.803831 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass
2296 10:52:45.893450 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass>
2297 10:52:45.894220 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass
2299 10:52:45.978734 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass>
2300 10:52:45.979514 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass
2302 10:52:46.068804 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass>
2303 10:52:46.069590 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass
2305 10:52:46.154878 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass>
2306 10:52:46.155637 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass
2308 10:52:46.238648 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass>
2309 10:52:46.239410 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass
2311 10:52:46.324205 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass>
2312 10:52:46.324954 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass
2314 10:52:46.411167 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass>
2315 10:52:46.411974 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass
2317 10:52:46.495940 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass>
2318 10:52:46.496779 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass
2320 10:52:46.587540 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass>
2321 10:52:46.588381 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass
2323 10:52:46.671454 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass>
2324 10:52:46.672300 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass
2326 10:52:46.762916 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass>
2327 10:52:46.763764 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass
2329 10:52:46.852468 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass>
2330 10:52:46.853277 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass
2332 10:52:46.945051 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass>
2333 10:52:46.945863 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass
2335 10:52:47.033514 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass>
2336 10:52:47.034326 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass
2338 10:52:47.125460 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail>
2339 10:52:47.126311 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail
2341 10:52:47.214884 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass>
2342 10:52:47.215732 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass
2344 10:52:47.300045 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass>
2345 10:52:47.300865 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass
2347 10:52:47.390467 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail>
2348 10:52:47.391449 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail
2350 10:52:47.476783 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass>
2351 10:52:47.477621 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass
2353 10:52:47.567857 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail>
2354 10:52:47.568799 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail
2356 10:52:47.654837 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass>
2357 10:52:47.655707 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass
2359 10:52:47.744592 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip>
2360 10:52:47.745424 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip
2362 10:52:47.834417 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip>
2363 10:52:47.835255 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip
2365 10:52:47.924600 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip>
2366 10:52:47.925402 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip
2368 10:52:48.008860 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass>
2369 10:52:48.009676 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass
2371 10:52:48.100297 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass>
2372 10:52:48.101123 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass
2374 10:52:48.188214 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass>
2375 10:52:48.189016 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass
2377 10:52:48.280669 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass>
2378 10:52:48.281521 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass
2380 10:52:48.370408 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail>
2381 10:52:48.370973 + set +x
2382 10:52:48.371628 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail
2384 10:52:48.374721 <LAVA_SIGNAL_ENDRUN 1_kselftest-dt 958645_1.6.2.4.5>
2385 10:52:48.375434 Received signal: <ENDRUN> 1_kselftest-dt 958645_1.6.2.4.5
2386 10:52:48.375874 Ending use of test pattern.
2387 10:52:48.376326 Ending test lava.1_kselftest-dt (958645_1.6.2.4.5), duration 83.32
2389 10:52:48.380120 <LAVA_TEST_RUNNER EXIT>
2390 10:52:48.380821 ok: lava_test_shell seems to have completed
2391 10:52:48.393619 dt_test_unprobed_devices_sh: fail
dt_test_unprobed_devices_sh_: skip
dt_test_unprobed_devices_sh_clk_mcasp0: pass
dt_test_unprobed_devices_sh_clk_mcasp0_fixed: skip
dt_test_unprobed_devices_sh_cpus_cpu_0: skip
dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate: skip
dt_test_unprobed_devices_sh_fixedregulator0: pass
dt_test_unprobed_devices_sh_leds: pass
dt_test_unprobed_devices_sh_ocp: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0: fail
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_eeprom_50: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_eeprom_50_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_54: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_54_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_55: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_55_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_56: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_56_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_57: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_57_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000: skip
dt_test_unprobed_devices_sh_ocp_target-module_47400000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800: pass
dt_test_unprobed_devices_sh_ocp_target-module_47810000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_50000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_53500000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_56000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0: skip
dt_test_unprobed_devices_sh_opp-table: skip
dt_test_unprobed_devices_sh_soc: skip
dt_test_unprobed_devices_sh_sound: pass
dt_test_unprobed_devices_sh_target-module_4b000000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0: pass
shardfile-dt: pass
2392 10:52:48.395509 end: 3.1 lava-test-shell (duration 00:01:25) [common]
2393 10:52:48.396076 end: 3 lava-test-retry (duration 00:01:25) [common]
2394 10:52:48.396633 start: 4 finalize (timeout 00:05:32) [common]
2395 10:52:48.397164 start: 4.1 power-off (timeout 00:00:30) [common]
2396 10:52:48.398126 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=beaglebone-black-01'
2397 10:52:48.433459 >> OK - accepted request
2398 10:52:48.435546 Returned 0 in 0 seconds
2399 10:52:48.536756 end: 4.1 power-off (duration 00:00:00) [common]
2401 10:52:48.538460 start: 4.2 read-feedback (timeout 00:05:32) [common]
2402 10:52:48.539538 Listened to connection for namespace 'common' for up to 1s
2403 10:52:48.540470 Listened to connection for namespace 'common' for up to 1s
2404 10:52:49.539539 Finalising connection for namespace 'common'
2405 10:52:49.540332 Disconnecting from shell: Finalise
2406 10:52:49.540872 / #
2407 10:52:49.641940 end: 4.2 read-feedback (duration 00:00:01) [common]
2408 10:52:49.642731 end: 4 finalize (duration 00:00:01) [common]
2409 10:52:49.643405 Cleaning after the job
2410 10:52:49.644039 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/958645/tftp-deploy-ai35iwtf/ramdisk
2411 10:52:49.653614 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/958645/tftp-deploy-ai35iwtf/kernel
2412 10:52:49.658451 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/958645/tftp-deploy-ai35iwtf/dtb
2413 10:52:49.659840 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/958645/tftp-deploy-ai35iwtf/nfsrootfs
2414 10:52:49.715121 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/958645/tftp-deploy-ai35iwtf/modules
2415 10:52:49.719242 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/958645
2416 10:52:52.631900 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/958645
2417 10:52:52.632574 Job finished correctly