Boot log: beaglebone-black

    1 10:50:40.677659  lava-dispatcher, installed at version: 2023.08
    2 10:50:40.678070  start: 0 validate
    3 10:50:40.678306  Start time: 2024-11-08 10:50:40.678290+00:00 (UTC)
    4 10:50:40.678577  Validating that http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/initrd.cpio.gz exists
    5 10:50:41.011641  Validating that http://storage.kernelci.org/next/master/next-20241108/arm/multi_v7_defconfig/gcc-12/kernel/zImage exists
    6 10:50:41.167808  Validating that http://storage.kernelci.org/next/master/next-20241108/arm/multi_v7_defconfig/gcc-12/dtbs/ti/omap/am335x-boneblack.dtb exists
    7 10:50:41.323557  Validating that http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/full.rootfs.tar.xz exists
    8 10:50:41.480327  Validating that http://storage.kernelci.org/next/master/next-20241108/arm/multi_v7_defconfig/gcc-12/modules.tar.xz exists
    9 10:50:41.644477  validate duration: 0.97
   11 10:50:41.645600  start: 1 tftp-deploy (timeout 00:10:00) [common]
   12 10:50:41.646076  start: 1.1 download-retry (timeout 00:10:00) [common]
   13 10:50:41.646513  start: 1.1.1 http-download (timeout 00:10:00) [common]
   14 10:50:41.647218  Not decompressing ramdisk as can be used compressed.
   15 10:50:41.647645  downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/initrd.cpio.gz
   16 10:50:41.647981  saving as /var/lib/lava/dispatcher/tmp/1219249/tftp-deploy-l4hclial/ramdisk/initrd.cpio.gz
   17 10:50:41.648319  total size: 4775763 (4 MB)
   18 10:50:41.960530  progress   0 % (0 MB)
   19 10:50:42.424647  progress   5 % (0 MB)
   20 10:50:42.625358  progress  10 % (0 MB)
   21 10:50:42.751958  progress  15 % (0 MB)
   22 10:50:42.767199  progress  20 % (0 MB)
   23 10:50:42.888638  progress  25 % (1 MB)
   24 10:50:42.915441  progress  30 % (1 MB)
   25 10:50:43.062977  progress  35 % (1 MB)
   26 10:50:43.203509  progress  40 % (1 MB)
   27 10:50:43.242110  progress  45 % (2 MB)
   28 10:50:43.371693  progress  50 % (2 MB)
   29 10:50:43.515715  progress  55 % (2 MB)
   30 10:50:43.653895  progress  60 % (2 MB)
   31 10:50:43.680688  progress  65 % (2 MB)
   32 10:50:43.825240  progress  70 % (3 MB)
   33 10:50:43.856968  progress  75 % (3 MB)
   34 10:50:43.986983  progress  80 % (3 MB)
   35 10:50:44.127735  progress  85 % (3 MB)
   36 10:50:44.151299  progress  90 % (4 MB)
   37 10:50:44.292373  progress  95 % (4 MB)
   38 10:50:44.421812  progress 100 % (4 MB)
   39 10:50:44.422866  4 MB downloaded in 2.77 s (1.64 MB/s)
   40 10:50:44.423525  end: 1.1.1 http-download (duration 00:00:03) [common]
   42 10:50:44.424677  end: 1.1 download-retry (duration 00:00:03) [common]
   43 10:50:44.425119  start: 1.2 download-retry (timeout 00:09:57) [common]
   44 10:50:44.425519  start: 1.2.1 http-download (timeout 00:09:57) [common]
   45 10:50:44.426108  downloading http://storage.kernelci.org/next/master/next-20241108/arm/multi_v7_defconfig/gcc-12/kernel/zImage
   46 10:50:44.426427  saving as /var/lib/lava/dispatcher/tmp/1219249/tftp-deploy-l4hclial/kernel/zImage
   47 10:50:44.426730  total size: 11510272 (10 MB)
   48 10:50:44.427028  No compression specified
   49 10:50:44.585860  progress   0 % (0 MB)
   50 10:50:44.895532  progress   5 % (0 MB)
   51 10:50:45.067815  progress  10 % (1 MB)
   52 10:50:45.374593  progress  15 % (1 MB)
   53 10:50:45.685243  progress  20 % (2 MB)
   54 10:50:45.988714  progress  25 % (2 MB)
   55 10:50:46.293836  progress  30 % (3 MB)
   56 10:50:46.506774  progress  35 % (3 MB)
   57 10:50:46.774627  progress  40 % (4 MB)
   58 10:50:47.077448  progress  45 % (4 MB)
   59 10:50:47.372696  progress  50 % (5 MB)
   60 10:50:47.659985  progress  55 % (6 MB)
   61 10:50:47.855981  progress  60 % (6 MB)
   62 10:50:48.153524  progress  65 % (7 MB)
   63 10:50:48.437791  progress  70 % (7 MB)
   64 10:50:48.632556  progress  75 % (8 MB)
   65 10:50:48.929646  progress  80 % (8 MB)
   66 10:50:49.220204  progress  85 % (9 MB)
   67 10:50:49.407885  progress  90 % (9 MB)
   68 10:50:49.702201  progress  95 % (10 MB)
   69 10:50:49.992107  progress 100 % (10 MB)
   70 10:50:49.993133  10 MB downloaded in 5.57 s (1.97 MB/s)
   71 10:50:49.994946  end: 1.2.1 http-download (duration 00:00:06) [common]
   73 10:50:49.996360  end: 1.2 download-retry (duration 00:00:06) [common]
   74 10:50:49.996854  start: 1.3 download-retry (timeout 00:09:52) [common]
   75 10:50:49.997390  start: 1.3.1 http-download (timeout 00:09:52) [common]
   76 10:50:49.998301  downloading http://storage.kernelci.org/next/master/next-20241108/arm/multi_v7_defconfig/gcc-12/dtbs/ti/omap/am335x-boneblack.dtb
   77 10:50:49.998657  saving as /var/lib/lava/dispatcher/tmp/1219249/tftp-deploy-l4hclial/dtb/am335x-boneblack.dtb
   78 10:50:49.998958  total size: 70544 (0 MB)
   79 10:50:49.999260  No compression specified
   80 10:50:50.162190  progress  46 % (0 MB)
   81 10:50:50.165030  progress  92 % (0 MB)
   82 10:50:50.166296  progress 100 % (0 MB)
   83 10:50:50.166840  0 MB downloaded in 0.17 s (0.40 MB/s)
   84 10:50:50.167481  end: 1.3.1 http-download (duration 00:00:00) [common]
   86 10:50:50.168594  end: 1.3 download-retry (duration 00:00:00) [common]
   87 10:50:50.169023  start: 1.4 download-retry (timeout 00:09:51) [common]
   88 10:50:50.169464  start: 1.4.1 http-download (timeout 00:09:51) [common]
   89 10:50:50.170043  downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/full.rootfs.tar.xz
   90 10:50:50.170358  saving as /var/lib/lava/dispatcher/tmp/1219249/tftp-deploy-l4hclial/nfsrootfs/full.rootfs.tar
   91 10:50:50.170651  total size: 117747780 (112 MB)
   92 10:50:50.171013  Using unxz to decompress xz
   93 10:50:50.330603  progress   0 % (0 MB)
   94 10:50:53.409084  progress   5 % (5 MB)
   95 10:50:56.052178  progress  10 % (11 MB)
   96 10:50:58.769347  progress  15 % (16 MB)
   97 10:51:01.166417  progress  20 % (22 MB)
   98 10:51:03.122298  progress  25 % (28 MB)
   99 10:51:04.642379  progress  30 % (33 MB)
  100 10:51:05.840510  progress  35 % (39 MB)
  101 10:51:06.813445  progress  40 % (44 MB)
  102 10:51:07.633425  progress  45 % (50 MB)
  103 10:51:08.349645  progress  50 % (56 MB)
  104 10:51:09.112520  progress  55 % (61 MB)
  105 10:51:09.941755  progress  60 % (67 MB)
  106 10:51:10.701383  progress  65 % (73 MB)
  107 10:51:11.594658  progress  70 % (78 MB)
  108 10:51:12.568936  progress  75 % (84 MB)
  109 10:51:13.482984  progress  80 % (89 MB)
  110 10:51:14.371387  progress  85 % (95 MB)
  111 10:51:15.247013  progress  90 % (101 MB)
  112 10:51:16.107826  progress  95 % (106 MB)
  113 10:51:16.964384  progress 100 % (112 MB)
  114 10:51:16.968899  112 MB downloaded in 26.80 s (4.19 MB/s)
  115 10:51:16.969434  end: 1.4.1 http-download (duration 00:00:27) [common]
  117 10:51:16.970572  end: 1.4 download-retry (duration 00:00:27) [common]
  118 10:51:16.970977  start: 1.5 download-retry (timeout 00:09:25) [common]
  119 10:51:16.971414  start: 1.5.1 http-download (timeout 00:09:25) [common]
  120 10:51:16.972066  downloading http://storage.kernelci.org/next/master/next-20241108/arm/multi_v7_defconfig/gcc-12/modules.tar.xz
  121 10:51:16.972386  saving as /var/lib/lava/dispatcher/tmp/1219249/tftp-deploy-l4hclial/modules/modules.tar
  122 10:51:16.972721  total size: 6625392 (6 MB)
  123 10:51:16.972938  Using unxz to decompress xz
  124 10:51:17.132908  progress   0 % (0 MB)
  125 10:51:17.331208  progress   5 % (0 MB)
  126 10:51:17.391549  progress  10 % (0 MB)
  127 10:51:17.424592  progress  15 % (0 MB)
  128 10:51:17.453161  progress  20 % (1 MB)
  129 10:51:17.666527  progress  25 % (1 MB)
  130 10:51:17.695308  progress  30 % (1 MB)
  131 10:51:17.723452  progress  35 % (2 MB)
  132 10:51:17.751546  progress  40 % (2 MB)
  133 10:51:17.779560  progress  45 % (2 MB)
  134 10:51:18.012863  progress  50 % (3 MB)
  135 10:51:18.048921  progress  55 % (3 MB)
  136 10:51:18.086326  progress  60 % (3 MB)
  137 10:51:18.115067  progress  65 % (4 MB)
  138 10:51:18.145456  progress  70 % (4 MB)
  139 10:51:18.250001  progress  75 % (4 MB)
  140 10:51:18.333885  progress  80 % (5 MB)
  141 10:51:18.475270  progress  85 % (5 MB)
  142 10:51:18.610378  progress  90 % (5 MB)
  143 10:51:18.760339  progress  95 % (6 MB)
  144 10:51:18.894080  progress 100 % (6 MB)
  145 10:51:18.896979  6 MB downloaded in 1.92 s (3.28 MB/s)
  146 10:51:18.897658  end: 1.5.1 http-download (duration 00:00:02) [common]
  148 10:51:18.898781  end: 1.5 download-retry (duration 00:00:02) [common]
  149 10:51:18.899320  start: 1.6 prepare-tftp-overlay (timeout 00:09:23) [common]
  150 10:51:18.899852  start: 1.6.1 extract-nfsrootfs (timeout 00:09:23) [common]
  151 10:51:28.260011  Extracted nfsroot to /var/lib/lava/dispatcher/tmp/1219249/extract-nfsrootfs-pybfeead
  152 10:51:28.260349  end: 1.6.1 extract-nfsrootfs (duration 00:00:09) [common]
  153 10:51:28.260530  start: 1.6.2 lava-overlay (timeout 00:09:13) [common]
  154 10:51:28.260915  [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/1219249/lava-overlay-d1z7tohy
  155 10:51:28.261190  makedir: /var/lib/lava/dispatcher/tmp/1219249/lava-overlay-d1z7tohy/lava-1219249/bin
  156 10:51:28.261392  makedir: /var/lib/lava/dispatcher/tmp/1219249/lava-overlay-d1z7tohy/lava-1219249/tests
  157 10:51:28.261590  makedir: /var/lib/lava/dispatcher/tmp/1219249/lava-overlay-d1z7tohy/lava-1219249/results
  158 10:51:28.261778  Creating /var/lib/lava/dispatcher/tmp/1219249/lava-overlay-d1z7tohy/lava-1219249/bin/lava-add-keys
  159 10:51:28.262060  Creating /var/lib/lava/dispatcher/tmp/1219249/lava-overlay-d1z7tohy/lava-1219249/bin/lava-add-sources
  160 10:51:28.262322  Creating /var/lib/lava/dispatcher/tmp/1219249/lava-overlay-d1z7tohy/lava-1219249/bin/lava-background-process-start
  161 10:51:28.262585  Creating /var/lib/lava/dispatcher/tmp/1219249/lava-overlay-d1z7tohy/lava-1219249/bin/lava-background-process-stop
  162 10:51:28.262864  Creating /var/lib/lava/dispatcher/tmp/1219249/lava-overlay-d1z7tohy/lava-1219249/bin/lava-common-functions
  163 10:51:28.263120  Creating /var/lib/lava/dispatcher/tmp/1219249/lava-overlay-d1z7tohy/lava-1219249/bin/lava-echo-ipv4
  164 10:51:28.263384  Creating /var/lib/lava/dispatcher/tmp/1219249/lava-overlay-d1z7tohy/lava-1219249/bin/lava-install-packages
  165 10:51:28.263634  Creating /var/lib/lava/dispatcher/tmp/1219249/lava-overlay-d1z7tohy/lava-1219249/bin/lava-installed-packages
  166 10:51:28.263884  Creating /var/lib/lava/dispatcher/tmp/1219249/lava-overlay-d1z7tohy/lava-1219249/bin/lava-os-build
  167 10:51:28.264134  Creating /var/lib/lava/dispatcher/tmp/1219249/lava-overlay-d1z7tohy/lava-1219249/bin/lava-probe-channel
  168 10:51:28.264387  Creating /var/lib/lava/dispatcher/tmp/1219249/lava-overlay-d1z7tohy/lava-1219249/bin/lava-probe-ip
  169 10:51:28.264638  Creating /var/lib/lava/dispatcher/tmp/1219249/lava-overlay-d1z7tohy/lava-1219249/bin/lava-target-ip
  170 10:51:28.264897  Creating /var/lib/lava/dispatcher/tmp/1219249/lava-overlay-d1z7tohy/lava-1219249/bin/lava-target-mac
  171 10:51:28.265149  Creating /var/lib/lava/dispatcher/tmp/1219249/lava-overlay-d1z7tohy/lava-1219249/bin/lava-target-storage
  172 10:51:28.265404  Creating /var/lib/lava/dispatcher/tmp/1219249/lava-overlay-d1z7tohy/lava-1219249/bin/lava-test-case
  173 10:51:28.265655  Creating /var/lib/lava/dispatcher/tmp/1219249/lava-overlay-d1z7tohy/lava-1219249/bin/lava-test-event
  174 10:51:28.265899  Creating /var/lib/lava/dispatcher/tmp/1219249/lava-overlay-d1z7tohy/lava-1219249/bin/lava-test-feedback
  175 10:51:28.266144  Creating /var/lib/lava/dispatcher/tmp/1219249/lava-overlay-d1z7tohy/lava-1219249/bin/lava-test-raise
  176 10:51:28.266392  Creating /var/lib/lava/dispatcher/tmp/1219249/lava-overlay-d1z7tohy/lava-1219249/bin/lava-test-reference
  177 10:51:28.266640  Creating /var/lib/lava/dispatcher/tmp/1219249/lava-overlay-d1z7tohy/lava-1219249/bin/lava-test-runner
  178 10:51:28.266890  Creating /var/lib/lava/dispatcher/tmp/1219249/lava-overlay-d1z7tohy/lava-1219249/bin/lava-test-set
  179 10:51:28.267135  Creating /var/lib/lava/dispatcher/tmp/1219249/lava-overlay-d1z7tohy/lava-1219249/bin/lava-test-shell
  180 10:51:28.267394  Updating /var/lib/lava/dispatcher/tmp/1219249/lava-overlay-d1z7tohy/lava-1219249/bin/lava-add-keys (debian)
  181 10:51:28.267707  Updating /var/lib/lava/dispatcher/tmp/1219249/lava-overlay-d1z7tohy/lava-1219249/bin/lava-add-sources (debian)
  182 10:51:28.267995  Updating /var/lib/lava/dispatcher/tmp/1219249/lava-overlay-d1z7tohy/lava-1219249/bin/lava-install-packages (debian)
  183 10:51:28.268283  Updating /var/lib/lava/dispatcher/tmp/1219249/lava-overlay-d1z7tohy/lava-1219249/bin/lava-installed-packages (debian)
  184 10:51:28.268569  Updating /var/lib/lava/dispatcher/tmp/1219249/lava-overlay-d1z7tohy/lava-1219249/bin/lava-os-build (debian)
  185 10:51:28.268896  Creating /var/lib/lava/dispatcher/tmp/1219249/lava-overlay-d1z7tohy/lava-1219249/environment
  186 10:51:28.269083  LAVA metadata
  187 10:51:28.269217  - LAVA_JOB_ID=1219249
  188 10:51:28.269345  - LAVA_DISPATCHER_IP=172.16.3.3
  189 10:51:28.269540  start: 1.6.2.1 ssh-authorize (timeout 00:09:13) [common]
  190 10:51:28.270042  end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
  191 10:51:28.270212  start: 1.6.2.2 lava-vland-overlay (timeout 00:09:13) [common]
  192 10:51:28.270337  skipped lava-vland-overlay
  193 10:51:28.270485  end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
  194 10:51:28.270642  start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:13) [common]
  195 10:51:28.270773  skipped lava-multinode-overlay
  196 10:51:28.270922  end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
  197 10:51:28.271078  start: 1.6.2.4 test-definition (timeout 00:09:13) [common]
  198 10:51:28.271216  Loading test definitions
  199 10:51:28.271381  start: 1.6.2.4.1 inline-repo-action (timeout 00:09:13) [common]
  200 10:51:28.271514  Using /lava-1219249 at stage 0
  201 10:51:28.272101  uuid=1219249_1.6.2.4.1 testdef=None
  202 10:51:28.272267  end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
  203 10:51:28.272426  start: 1.6.2.4.2 test-overlay (timeout 00:09:13) [common]
  204 10:51:28.273310  end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
  206 10:51:28.273738  start: 1.6.2.4.3 test-install-overlay (timeout 00:09:13) [common]
  207 10:51:28.274950  end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
  209 10:51:28.275390  start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:13) [common]
  210 10:51:28.291355  runner path: /var/lib/lava/dispatcher/tmp/1219249/lava-overlay-d1z7tohy/lava-1219249/0/tests/0_timesync-off test_uuid 1219249_1.6.2.4.1
  211 10:51:28.307122  end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
  213 10:51:28.307590  start: 1.6.2.4.5 git-repo-action (timeout 00:09:13) [common]
  214 10:51:28.307729  Using /lava-1219249 at stage 0
  215 10:51:28.307921  Fetching tests from https://github.com/kernelci/test-definitions.git
  216 10:51:28.308061  Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/1219249/lava-overlay-d1z7tohy/lava-1219249/0/tests/1_kselftest-dt'
  217 10:51:34.086711  Running '/usr/bin/git checkout kernelci.org
  218 10:51:34.299198  Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/1219249/lava-overlay-d1z7tohy/lava-1219249/0/tests/1_kselftest-dt/automated/linux/kselftest/kselftest.yaml
  219 10:51:34.300356  uuid=1219249_1.6.2.4.5 testdef=None
  220 10:51:34.300657  end: 1.6.2.4.5 git-repo-action (duration 00:00:06) [common]
  222 10:51:34.301273  start: 1.6.2.4.6 test-overlay (timeout 00:09:07) [common]
  223 10:51:34.303550  end: 1.6.2.4.6 test-overlay (duration 00:00:00) [common]
  225 10:51:34.304249  start: 1.6.2.4.7 test-install-overlay (timeout 00:09:07) [common]
  226 10:51:34.307179  end: 1.6.2.4.7 test-install-overlay (duration 00:00:00) [common]
  228 10:51:34.307901  start: 1.6.2.4.8 test-runscript-overlay (timeout 00:09:07) [common]
  229 10:51:34.339929  runner path: /var/lib/lava/dispatcher/tmp/1219249/lava-overlay-d1z7tohy/lava-1219249/0/tests/1_kselftest-dt test_uuid 1219249_1.6.2.4.5
  230 10:51:34.340185  BOARD='beaglebone-black'
  231 10:51:34.340389  BRANCH='next'
  232 10:51:34.340581  SKIPFILE='/dev/null'
  233 10:51:34.340769  SKIP_INSTALL='True'
  234 10:51:34.340942  TESTPROG_URL='http://storage.kernelci.org/next/master/next-20241108/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz'
  235 10:51:34.341082  TST_CASENAME=''
  236 10:51:34.341227  TST_CMDFILES='dt'
  237 10:51:34.341588  end: 1.6.2.4.8 test-runscript-overlay (duration 00:00:00) [common]
  239 10:51:34.342097  Creating lava-test-runner.conf files
  240 10:51:34.342248  Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/1219249/lava-overlay-d1z7tohy/lava-1219249/0 for stage 0
  241 10:51:34.342473  - 0_timesync-off
  242 10:51:34.342634  - 1_kselftest-dt
  243 10:51:34.342870  end: 1.6.2.4 test-definition (duration 00:00:06) [common]
  244 10:51:34.343099  start: 1.6.2.5 compress-overlay (timeout 00:09:07) [common]
  245 10:51:45.596680  end: 1.6.2.5 compress-overlay (duration 00:00:11) [common]
  246 10:51:45.596950  start: 1.6.2.6 persistent-nfs-overlay (timeout 00:08:56) [common]
  247 10:51:45.597121  end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
  248 10:51:45.597295  end: 1.6.2 lava-overlay (duration 00:00:17) [common]
  249 10:51:45.597462  start: 1.6.3 extract-overlay-ramdisk (timeout 00:08:56) [common]
  250 10:51:45.754259  end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
  251 10:51:45.754525  start: 1.6.4 extract-modules (timeout 00:08:56) [common]
  252 10:51:45.754674  extracting modules file /var/lib/lava/dispatcher/tmp/1219249/tftp-deploy-l4hclial/modules/modules.tar to /var/lib/lava/dispatcher/tmp/1219249/extract-nfsrootfs-pybfeead
  253 10:51:46.251412  extracting modules file /var/lib/lava/dispatcher/tmp/1219249/tftp-deploy-l4hclial/modules/modules.tar to /var/lib/lava/dispatcher/tmp/1219249/extract-overlay-ramdisk-smspym64/ramdisk
  254 10:51:46.771964  end: 1.6.4 extract-modules (duration 00:00:01) [common]
  255 10:51:46.772252  start: 1.6.5 apply-overlay-tftp (timeout 00:08:55) [common]
  256 10:51:46.772407  [common] Applying overlay to NFS
  257 10:51:46.772534  [common] Applying overlay /var/lib/lava/dispatcher/tmp/1219249/compress-overlay-fvbvvix7/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/1219249/extract-nfsrootfs-pybfeead
  258 10:51:48.393190  end: 1.6.5 apply-overlay-tftp (duration 00:00:02) [common]
  259 10:51:48.393466  start: 1.6.6 prepare-kernel (timeout 00:08:53) [common]
  260 10:51:48.393637  start: 1.6.6.1 uboot-prepare-kernel (timeout 00:08:53) [common]
  261 10:51:48.393814  end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
  262 10:51:48.393971  end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
  263 10:51:48.394133  start: 1.6.7 configure-preseed-file (timeout 00:08:53) [common]
  264 10:51:48.394292  end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
  265 10:51:48.394450  start: 1.6.8 compress-ramdisk (timeout 00:08:53) [common]
  266 10:51:48.394586  Building ramdisk /var/lib/lava/dispatcher/tmp/1219249/extract-overlay-ramdisk-smspym64/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/1219249/extract-overlay-ramdisk-smspym64/ramdisk
  267 10:51:48.706694  >> 75308 blocks

  268 10:51:51.190238  Adding RAMdisk u-boot header.
  269 10:51:51.190771  mkimage -A arm -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/1219249/extract-overlay-ramdisk-smspym64/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/1219249/extract-overlay-ramdisk-smspym64/ramdisk.cpio.gz.uboot
  270 10:51:51.457423  output: Image Name:   
  271 10:51:51.457811  output: Created:      Fri Nov  8 10:51:51 2024
  272 10:51:51.458134  output: Image Type:   ARM Linux RAMDisk Image (uncompressed)
  273 10:51:51.458439  output: Data Size:    14833976 Bytes = 14486.30 KiB = 14.15 MiB
  274 10:51:51.458736  output: Load Address: 00000000
  275 10:51:51.459022  output: Entry Point:  00000000
  276 10:51:51.459308  output: 
  277 10:51:51.459804  rename /var/lib/lava/dispatcher/tmp/1219249/extract-overlay-ramdisk-smspym64/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/1219249/tftp-deploy-l4hclial/ramdisk/ramdisk.cpio.gz.uboot
  278 10:51:51.460302  end: 1.6.8 compress-ramdisk (duration 00:00:03) [common]
  279 10:51:51.460716  end: 1.6 prepare-tftp-overlay (duration 00:00:33) [common]
  280 10:51:51.460975  start: 1.7 lxc-create-udev-rule-action (timeout 00:08:50) [common]
  281 10:51:51.461202  No LXC device requested
  282 10:51:51.461577  end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
  283 10:51:51.461967  start: 1.8 deploy-device-env (timeout 00:08:50) [common]
  284 10:51:51.462346  end: 1.8 deploy-device-env (duration 00:00:00) [common]
  285 10:51:51.462652  Checking files for TFTP limit of 4294967296 bytes.
  286 10:51:51.464565  end: 1 tftp-deploy (duration 00:01:10) [common]
  287 10:51:51.464924  start: 2 uboot-action (timeout 00:05:00) [common]
  288 10:51:51.465196  start: 2.1 uboot-from-media (timeout 00:05:00) [common]
  289 10:51:51.465579  end: 2.1 uboot-from-media (duration 00:00:00) [common]
  290 10:51:51.465965  start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
  291 10:51:51.466528  substitutions:
  292 10:51:51.466837  - {BOOTX}: bootz 0x82000000 0x83000000 0x88000000
  293 10:51:51.467140  - {DTB_ADDR}: 0x88000000
  294 10:51:51.467429  - {DTB}: 1219249/tftp-deploy-l4hclial/dtb/am335x-boneblack.dtb
  295 10:51:51.467718  - {INITRD}: 1219249/tftp-deploy-l4hclial/ramdisk/ramdisk.cpio.gz.uboot
  296 10:51:51.468007  - {KERNEL_ADDR}: 0x82000000
  297 10:51:51.468295  - {KERNEL}: 1219249/tftp-deploy-l4hclial/kernel/zImage
  298 10:51:51.468580  - {LAVA_MAC}: None
  299 10:51:51.468872  - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/1219249/extract-nfsrootfs-pybfeead
  300 10:51:51.468992  - {NFS_SERVER_IP}: 172.16.3.3
  301 10:51:51.469218  - {PRESEED_CONFIG}: None
  302 10:51:51.469497  - {PRESEED_LOCAL}: None
  303 10:51:51.469776  - {RAMDISK_ADDR}: 0x83000000
  304 10:51:51.470055  - {RAMDISK}: 1219249/tftp-deploy-l4hclial/ramdisk/ramdisk.cpio.gz.uboot
  305 10:51:51.470335  - {ROOT_PART}: None
  306 10:51:51.470610  - {ROOT}: None
  307 10:51:51.470885  - {SERVER_IP}: 172.16.3.3
  308 10:51:51.471158  - {TEE_ADDR}: 0x83000000
  309 10:51:51.471434  - {TEE}: None
  310 10:51:51.471710  Parsed boot commands:
  311 10:51:51.471979  - setenv autoload no
  312 10:51:51.472253  - setenv initrd_high 0xffffffff
  313 10:51:51.472527  - setenv fdt_high 0xffffffff
  314 10:51:51.472833  - dhcp
  315 10:51:51.472949  - setenv serverip 172.16.3.3
  316 10:51:51.473125  - tftp 0x82000000 1219249/tftp-deploy-l4hclial/kernel/zImage
  317 10:51:51.473400  - tftp 0x83000000 1219249/tftp-deploy-l4hclial/ramdisk/ramdisk.cpio.gz.uboot
  318 10:51:51.473675  - setenv initrd_size ${filesize}
  319 10:51:51.473948  - tftp 0x88000000 1219249/tftp-deploy-l4hclial/dtb/am335x-boneblack.dtb
  320 10:51:51.474223  - setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=172.16.3.3:/var/lib/lava/dispatcher/tmp/1219249/extract-nfsrootfs-pybfeead,tcp,hard,v3 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
  321 10:51:51.474512  - bootz 0x82000000 0x83000000 0x88000000
  322 10:51:51.474873  end: 2.2 bootloader-overlay (duration 00:00:00) [common]
  324 10:51:51.475889  start: 2.3 connect-device (timeout 00:05:00) [common]
  325 10:51:51.476188  [common] connect-device Connecting to device using 'telnet ts5 2002'
  326 10:51:51.483455  Setting prompt string to ['lava-test: # ']
  327 10:51:51.483913  end: 2.3 connect-device (duration 00:00:00) [common]
  328 10:51:51.484110  start: 2.4 uboot-commands (timeout 00:05:00) [common]
  329 10:51:51.484291  start: 2.4.1 reset-device (timeout 00:05:00) [common]
  330 10:51:51.484469  start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
  331 10:51:51.484758  Calling: 'drpm' 'lf-bbb-02' 'powercycle'
  332 10:51:51.922730  >> OFF

  333 10:52:07.258879  >> ON

  334 10:52:07.259851  Returned 0 in 15 seconds
  335 10:52:07.360836  end: 2.4.1.1 pdu-reboot (duration 00:00:16) [common]
  337 10:52:07.362019  end: 2.4.1 reset-device (duration 00:00:16) [common]
  338 10:52:07.362448  start: 2.4.2 bootloader-interrupt (timeout 00:04:44) [common]
  339 10:52:07.362841  Setting prompt string to ['Hit any key to stop autoboot']
  340 10:52:07.363182  bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
  341 10:52:07.364128  Trying 192.168.1.205...
  342 10:52:07.364437  Connected to ts5.
  343 10:52:07.364725  Escape character is '^]'.
  344 10:52:07.365039  
  345 10:52:07.365334  ser2net port telnet,2002 device serialdev,/dev/ttyUSB-lf-bbb-02,115200n81,local [] (Debian GNU/Linux)
  346 10:52:07.365624  
  347 10:52:07.844329  
  348 10:52:07.852194  U-Boot SPL 2021.10-nethacked-for-LAVA_hws@denx.de-dirty (Oct 19 2021 - 19:02:35 +0200)
  349 10:52:07.852626  Trying to boot from MMC2
  350 10:52:08.365211  
  351 10:52:08.365761  
  352 10:52:08.371280  U-Boot 2021.10-nethacked-for-LAVA_hws@denx.de-dirty (Oct 19 2021 - 19:02:35 +0200)
  353 10:52:08.371677  
  354 10:52:08.372005  CPU  : AM335X-GP rev 2.1
  355 10:52:08.376823  Model: TI AM335x BeagleBone Black
  356 10:52:08.377208  DRAM:  512 MiB
  357 10:52:08.459234  WDT:   Started with servicing (60s timeout)
  358 10:52:08.865101  NAND:  0 MiB
  359 10:52:08.874759  MMC:   OMAP SD/MMC: 0, OMAP SD/MMC: 1
  360 10:52:08.908574  Loading Environment from FAT... <ethaddr> not set. Validating first E-fuse MAC
  361 10:52:08.937805  Net:   eth2: ethernet@4a100000, eth3: usb_ether
  362 10:52:08.996588  end: 2.4.2 bootloader-interrupt (duration 00:00:02) [common]
  363 10:52:08.997172  start: 2.4.3 bootloader-commands (timeout 00:04:42) [common]
  364 10:52:08.997549  Setting prompt string to ['=> ']
  365 10:52:08.997916  bootloader-commands: Wait for prompt ['=> '] (timeout 00:04:42)
  366 10:52:09.006390  Hit any key to stop autoboot:  2   0 
  367 10:52:09.007155  Setting prompt string to ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid']
  368 10:52:09.007548  Sending with 10 millisecond of delay
  370 10:52:10.143411  => setenv autoload no
  371 10:52:10.153999  bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:41)
  372 10:52:10.157125  setenv autoload no
  373 10:52:10.157731  Sending with 10 millisecond of delay
  375 10:52:11.956739  => setenv initrd_high 0xffffffff
  376 10:52:11.967316  bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:39)
  377 10:52:11.967953  setenv initrd_high 0xffffffff
  378 10:52:11.968519  Sending with 10 millisecond of delay
  380 10:52:13.586875  => setenv fdt_high 0xffffffff
  381 10:52:13.597459  bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:38)
  382 10:52:13.598090  setenv fdt_high 0xffffffff
  383 10:52:13.598664  Sending with 10 millisecond of delay
  385 10:52:13.890535  => dhcp
  386 10:52:13.901089  bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:38)
  387 10:52:13.902933  dhcp
  388 10:52:13.903318  link up on port 0, speed 100, full duplex
  389 10:52:13.903661  BOOTP broadcast 1
  390 10:52:13.957584  DHCP client bound to address 172.16.3.190 (50 ms)
  391 10:52:13.958206  Sending with 10 millisecond of delay
  393 10:52:15.576372  => setenv serverip 172.16.3.3
  394 10:52:15.586994  bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:36)
  395 10:52:15.587631  setenv serverip 172.16.3.3
  396 10:52:15.588206  Sending with 10 millisecond of delay
  398 10:52:19.134949  => tftp 0x82000000 1219249/tftp-deploy-l4hclial/kernel/zImage
  399 10:52:19.145661  bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:32)
  400 10:52:19.146352  tftp 0x82000000 1219249/tftp-deploy-l4hclial/kernel/zImage
  401 10:52:19.147207  link up on port 0, speed 100, full duplex
  402 10:52:19.152031  Using ethernet@4a100000 device
  403 10:52:19.158162  TFTP from server 172.16.3.3; our IP address is 172.16.3.190
  404 10:52:19.158577  Filename '1219249/tftp-deploy-l4hclial/kernel/zImage'.
  405 10:52:19.164074  Load address: 0x82000000
  406 10:52:21.923896  Loading: *##################################################  11 MiB
  407 10:52:21.924353  	 4 MiB/s
  408 10:52:21.924659  done
  409 10:52:21.927228  Bytes transferred = 11510272 (afa200 hex)
  410 10:52:21.927868  Sending with 10 millisecond of delay
  412 10:52:26.440042  => tftp 0x83000000 1219249/tftp-deploy-l4hclial/ramdisk/ramdisk.cpio.gz.uboot
  413 10:52:26.450779  bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:25)
  414 10:52:26.451704  tftp 0x83000000 1219249/tftp-deploy-l4hclial/ramdisk/ramdisk.cpio.gz.uboot
  415 10:52:26.452037  link up on port 0, speed 100, full duplex
  416 10:52:26.456816  Using ethernet@4a100000 device
  417 10:52:26.461782  TFTP from server 172.16.3.3; our IP address is 172.16.3.190
  418 10:52:26.470689  Filename '1219249/tftp-deploy-l4hclial/ramdisk/ramdisk.cpio.gz.uboot'.
  419 10:52:26.470992  Load address: 0x83000000
  420 10:52:30.227535  Loading: *##################################################  14.1 MiB
  421 10:52:30.228022  	 3.8 MiB/s
  422 10:52:30.228337  done
  423 10:52:30.231995  Bytes transferred = 14834040 (e25978 hex)
  424 10:52:30.232647  Sending with 10 millisecond of delay
  426 10:52:32.092121  => setenv initrd_size ${filesize}
  427 10:52:32.102734  bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:19)
  428 10:52:32.103368  setenv initrd_size ${filesize}
  429 10:52:32.103935  Sending with 10 millisecond of delay
  431 10:52:36.315422  => tftp 0x88000000 1219249/tftp-deploy-l4hclial/dtb/am335x-boneblack.dtb
  432 10:52:36.326063  bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:15)
  433 10:52:36.327088  tftp 0x88000000 1219249/tftp-deploy-l4hclial/dtb/am335x-boneblack.dtb
  434 10:52:36.327424  link up on port 0, speed 100, full duplex
  435 10:52:36.332043  Using ethernet@4a100000 device
  436 10:52:36.338159  TFTP from server 172.16.3.3; our IP address is 172.16.3.190
  437 10:52:36.352548  Filename '1219249/tftp-deploy-l4hclial/dtb/am335x-boneblack.dtb'.
  438 10:52:36.352989  Load address: 0x88000000
  439 10:52:36.369688  Loading: *##################################################  68.9 KiB
  440 10:52:36.370076  	 3.2 MiB/s
  441 10:52:36.370388  done
  442 10:52:36.374053  Bytes transferred = 70544 (11390 hex)
  443 10:52:36.374697  Sending with 10 millisecond of delay
  445 10:52:49.750327  => setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=172.16.3.3:/var/lib/lava/dispatcher/tmp/1219249/extract-nfsrootfs-pybfeead,tcp,hard,v3 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
  446 10:52:49.761032  bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:02)
  447 10:52:49.761688  setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=172.16.3.3:/var/lib/lava/dispatcher/tmp/1219249/extract-nfsrootfs-pybfeead,tcp,hard,v3 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
  448 10:52:49.762280  Sending with 10 millisecond of delay
  450 10:52:52.105405  => bootz 0x82000000 0x83000000 0x88000000
  451 10:52:52.116082  Setting prompt string to ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid']
  452 10:52:52.116539  bootloader-commands: Wait for prompt ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:03:59)
  453 10:52:52.117322  bootz 0x82000000 0x83000000 0x88000000
  454 10:52:52.117656  Kernel image @ 0x82000000 [ 0x000000 - 0xafa200 ]
  455 10:52:52.119533  ## Loading init Ramdisk from Legacy Image at 83000000 ...
  456 10:52:52.125547     Image Name:   
  457 10:52:52.125930     Created:      2024-11-08  10:51:51 UTC
  458 10:52:52.134291     Image Type:   ARM Linux RAMDisk Image (uncompressed)
  459 10:52:52.134677     Data Size:    14833976 Bytes = 14.1 MiB
  460 10:52:52.142239     Load Address: 00000000
  461 10:52:52.142621     Entry Point:  00000000
  462 10:52:52.311303     Verifying Checksum ... OK
  463 10:52:52.311689  ## Flattened Device Tree blob at 88000000
  464 10:52:52.318532     Booting using the fdt blob at 0x88000000
  465 10:52:52.322895     Using Device Tree in place at 88000000, end 8801438f
  466 10:52:52.336028  
  467 10:52:52.336414  Starting kernel ...
  468 10:52:52.336725  
  469 10:52:52.337468  end: 2.4.3 bootloader-commands (duration 00:00:43) [common]
  470 10:52:52.337905  start: 2.4.4 auto-login-action (timeout 00:03:59) [common]
  471 10:52:52.338257  Setting prompt string to ['Linux version [0-9]']
  472 10:52:52.338609  Setting prompt string to ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid']
  473 10:52:52.338966  auto-login-action: Wait for prompt ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:05:00)
  474 10:52:53.182609  [    0.000000] Booting Linux on physical CPU 0x0
  475 10:52:53.187882  start: 2.4.4.1 login-action (timeout 00:03:58) [common]
  476 10:52:53.188307  The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
  477 10:52:53.188656  Setting prompt string to []
  478 10:52:53.189040  Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
  479 10:52:53.189385  Using line separator: #'\n'#
  480 10:52:53.189683  No login prompt set.
  481 10:52:53.189993  Parsing kernel messages
  482 10:52:53.190275  ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
  483 10:52:53.190799  [login-action] Waiting for messages, (timeout 00:03:58)
  484 10:52:53.207166  [    0.000000] Linux version 6.12.0-rc6-next-20241108 (KernelCI@build-j368316-arm-gcc-12-multi-v7-defconfig-brkqm) (arm-linux-gnueabihf-gcc (Debian 12.2.0-14) 12.2.0, GNU ld (GNU Binutils for Debian) 2.40) #1 SMP Fri Nov  8 10:24:22 UTC 2024
  485 10:52:53.213198  [    0.000000] CPU: ARMv7 Processor [413fc082] revision 2 (ARMv7), cr=10c5387d
  486 10:52:53.221749  [    0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
  487 10:52:53.227867  [    0.000000] OF: fdt: Machine model: TI AM335x BeagleBone Black
  488 10:52:53.234039  [    0.000000] earlycon: omap8250 at MMIO 0x44e09000 (options '')
  489 10:52:53.237437  [    0.000000] printk: legacy bootconsole [omap8250] enabled
  490 10:52:53.243773  [    0.000000] Memory policy: Data cache writeback
  491 10:52:53.244153  [    0.000000] efi: UEFI not found.
  492 10:52:53.251769  [    0.000000] cma: Reserved 64 MiB at 0x9b800000 on node -1
  493 10:52:53.258184  [    0.000000] Zone ranges:
  494 10:52:53.264345  [    0.000000]   DMA      [mem 0x0000000080000000-0x000000009fdfffff]
  495 10:52:53.270430  [    0.000000]   Normal   empty
  496 10:52:53.270811  [    0.000000]   HighMem  empty
  497 10:52:53.272732  [    0.000000] Movable zone start for each node
  498 10:52:53.277784  [    0.000000] Early memory node ranges
  499 10:52:53.283901  [    0.000000]   node   0: [mem 0x0000000080000000-0x000000009fdfffff]
  500 10:52:53.291832  [    0.000000] Initmem setup node 0 [mem 0x0000000080000000-0x000000009fdfffff]
  501 10:52:53.314319  [    0.000000] OF: reserved mem: Reserved memory: No reserved-memory node in the DT
  502 10:52:53.326110  [    0.000000] CPU: All CPU(s) started in SVC mode.
  503 10:52:53.331638  [    0.000000] AM335X ES2.1 (sgx neon)
  504 10:52:53.342904  [    0.000000] percpu: Embedded 17 pages/cpu s40204 r8192 d21236 u69632
  505 10:52:53.361152  [    0.000000] Kernel command line: console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=172.16.3.3:/var/lib/lava/dispatcher/tmp/1219249/extract-nfsrootfs-pybfeead,tcp,hard,v3 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp
  506 10:52:53.369842  <6>[    0.000000] printk: log buffer data + meta data: 131072 + 409600 = 540672 bytes
  507 10:52:53.382159  <6>[    0.000000] Dentry cache hash table entries: 65536 (order: 6, 262144 bytes, linear)
  508 10:52:53.385635  <6>[    0.000000] Inode-cache hash table entries: 32768 (order: 5, 131072 bytes, linear)
  509 10:52:53.396768  <6>[    0.000000] Built 1 zonelists, mobility grouping on.  Total pages: 130560
  510 10:52:53.402350  <6>[    0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
  511 10:52:53.430535  <6>[    0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
  512 10:52:53.436538  <6>[    0.000000] trace event string verifier disabled
  513 10:52:53.436948  <6>[    0.000000] rcu: Hierarchical RCU implementation.
  514 10:52:53.445126  <6>[    0.000000] rcu: 	RCU event tracing is enabled.
  515 10:52:53.451248  <6>[    0.000000] rcu: 	RCU restricting CPUs from NR_CPUS=16 to nr_cpu_ids=1.
  516 10:52:53.457307  <6>[    0.000000] 	Tracing variant of Tasks RCU enabled.
  517 10:52:53.465892  <6>[    0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 10 jiffies.
  518 10:52:53.472038  <6>[    0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=1
  519 10:52:53.481416  <6>[    0.000000] RCU Tasks Trace: Setting shift to 0 and lim to 1 rcu_task_cb_adjust=1 rcu_task_cpu_ids=1.
  520 10:52:53.497515  <6>[    0.000000] NR_IRQS: 16, nr_irqs: 16, preallocated irqs: 16
  521 10:52:53.515039  <6>[    0.000000] IRQ: Found an INTC at 0x(ptrval) (revision 5.0) with 128 interrupts
  522 10:52:53.521731  <6>[    0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
  523 10:52:53.615777  <6>[    0.000000] TI gptimer clocksource: always-on /ocp/interconnect@44c00000/segment@200000/target-module@31000
  524 10:52:53.625421  <6>[    0.000003] sched_clock: 32 bits at 24MHz, resolution 41ns, wraps every 89478484971ns
  525 10:52:53.636342  <6>[    0.008334] clocksource: dmtimer: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 79635851949 ns
  526 10:52:53.645648  <6>[    0.019163] TI gptimer clockevent: 24000000 Hz at /ocp/interconnect@48000000/segment@0/target-module@40000
  527 10:52:53.653228  <6>[    0.034053] Console: colour dummy device 80x30
  528 10:52:53.658469  Matched prompt #6: WARNING:
  529 10:52:53.658879  Setting prompt string to ['end trace[^\\r]*\\r', '/ #', 'Login timed out', 'Login incorrect']
  530 10:52:53.664210  <3>[    0.038952] WARNING: Your 'console=ttyO0' has been replaced by 'ttyS0'
  531 10:52:53.670413  <3>[    0.046024] This ensures that you still see kernel messages. Please
  532 10:52:53.673629  <3>[    0.052751] update your kernel commandline.
  533 10:52:53.714418  <6>[    0.057363] Calibrating delay loop... 996.14 BogoMIPS (lpj=4980736)
  534 10:52:53.720425  <6>[    0.096171] CPU: Testing write buffer coherency: ok
  535 10:52:53.722739  <6>[    0.101538] CPU0: Spectre v2: using BPIALL workaround
  536 10:52:53.727765  <6>[    0.107005] pid_max: default: 32768 minimum: 301
  537 10:52:53.733868  <6>[    0.112204] Mount-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
  538 10:52:53.743541  <6>[    0.120026] Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
  539 10:52:53.751017  <6>[    0.129411] CPU0: thread -1, cpu 0, socket -1, mpidr 0
  540 10:52:53.764144  <6>[    0.136542] Setting up static identity map for 0x80300000 - 0x803000ac
  541 10:52:53.769162  <6>[    0.146212] rcu: Hierarchical SRCU implementation.
  542 10:52:53.773505  <6>[    0.151494] rcu: 	Max phase no-delay instances is 1000.
  543 10:52:53.782164  <6>[    0.162639] EFI services will not be available.
  544 10:52:53.788151  <6>[    0.167917] smp: Bringing up secondary CPUs ...
  545 10:52:53.793041  <6>[    0.172962] smp: Brought up 1 node, 1 CPU
  546 10:52:53.800403  <6>[    0.177363] SMP: Total of 1 processors activated (996.14 BogoMIPS).
  547 10:52:53.806489  <6>[    0.184135] CPU: All CPU(s) started in SVC mode.
  548 10:52:53.822522  <6>[    0.189319] Memory: 405932K/522240K available (16384K kernel code, 2540K rwdata, 6828K rodata, 2048K init, 429K bss, 49112K reserved, 65536K cma-reserved, 0K highmem)
  549 10:52:53.825761  <6>[    0.205609] devtmpfs: initialized
  550 10:52:53.847769  <6>[    0.222834] VFP support v0.3: implementor 41 architecture 3 part 30 variant c rev 3
  551 10:52:53.856194  <6>[    0.231410] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
  552 10:52:53.865539  <6>[    0.241869] futex hash table entries: 256 (order: 2, 16384 bytes, linear)
  553 10:52:53.876015  <6>[    0.254215] pinctrl core: initialized pinctrl subsystem
  554 10:52:53.884660  <6>[    0.264970] DMI not present or invalid.
  555 10:52:53.894286  <6>[    0.270813] NET: Registered PF_NETLINK/PF_ROUTE protocol family
  556 10:52:53.903485  <6>[    0.279793] DMA: preallocated 256 KiB pool for atomic coherent allocations
  557 10:52:53.918002  <6>[    0.291320] thermal_sys: Registered thermal governor 'step_wise'
  558 10:52:53.918388  <6>[    0.291488] cpuidle: using governor menu
  559 10:52:53.959094  <6>[    0.325457] /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70: Fixed dependency cycle(s) with /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
  560 10:52:53.978782  <6>[    0.344266] /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
  561 10:52:53.983655  <6>[    0.364948] No ATAGs?
  562 10:52:53.990516  <6>[    0.367582] hw-breakpoint: debug architecture 0x4 unsupported.
  563 10:52:53.999776  <6>[    0.379628] Serial: AMBA PL011 UART driver
  564 10:52:54.033520  <6>[    0.415165] iommu: Default domain type: Translated
  565 10:52:54.042877  <6>[    0.420515] iommu: DMA domain TLB invalidation policy: strict mode
  566 10:52:54.070529  <5>[    0.450984] SCSI subsystem initialized
  567 10:52:54.075634  <6>[    0.455867] usbcore: registered new interface driver usbfs
  568 10:52:54.081775  <6>[    0.461926] usbcore: registered new interface driver hub
  569 10:52:54.090415  <6>[    0.467710] usbcore: registered new device driver usb
  570 10:52:54.095416  <6>[    0.474242] pps_core: LinuxPPS API ver. 1 registered
  571 10:52:54.105230  <6>[    0.479668] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
  572 10:52:54.113212  <6>[    0.489353] PTP clock support registered
  573 10:52:54.113593  <6>[    0.493817] EDAC MC: Ver: 3.0.0
  574 10:52:54.161793  <6>[    0.539719] scmi_core: SCMI protocol bus registered
  575 10:52:54.176238  <6>[    0.557155] vgaarb: loaded
  576 10:52:54.188888  <6>[    0.570218] clocksource: Switched to clocksource dmtimer
  577 10:52:54.225783  <6>[    0.606720] NET: Registered PF_INET protocol family
  578 10:52:54.238293  <6>[    0.612421] IP idents hash table entries: 8192 (order: 4, 65536 bytes, linear)
  579 10:52:54.245896  <6>[    0.621294] tcp_listen_portaddr_hash hash table entries: 512 (order: 0, 4096 bytes, linear)
  580 10:52:54.252014  <6>[    0.630231] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
  581 10:52:54.262016  <6>[    0.638472] TCP established hash table entries: 4096 (order: 2, 16384 bytes, linear)
  582 10:52:54.273058  <6>[    0.646759] TCP bind hash table entries: 4096 (order: 4, 65536 bytes, linear)
  583 10:52:54.279138  <6>[    0.654473] TCP: Hash tables configured (established 4096 bind 4096)
  584 10:52:54.282900  <6>[    0.661397] UDP hash table entries: 256 (order: 1, 8192 bytes, linear)
  585 10:52:54.293903  <6>[    0.668405] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes, linear)
  586 10:52:54.298186  <6>[    0.676010] NET: Registered PF_UNIX/PF_LOCAL protocol family
  587 10:52:54.390024  <6>[    0.765255] RPC: Registered named UNIX socket transport module.
  588 10:52:54.390412  <6>[    0.771688] RPC: Registered udp transport module.
  589 10:52:54.394897  <6>[    0.776795] RPC: Registered tcp transport module.
  590 10:52:54.403396  <6>[    0.781916] RPC: Registered tcp-with-tls transport module.
  591 10:52:54.409514  <6>[    0.787824] RPC: Registered tcp NFSv4.1 backchannel transport module.
  592 10:52:54.415648  <6>[    0.794753] PCI: CLS 0 bytes, default 64
  593 10:52:54.419283  <5>[    0.800626] Initialise system trusted keyrings
  594 10:52:54.441388  <6>[    0.819176] Trying to unpack rootfs image as initramfs...
  595 10:52:54.525529  <6>[    0.900438] workingset: timestamp_bits=30 max_order=17 bucket_order=0
  596 10:52:54.529871  <6>[    0.907963] squashfs: version 4.0 (2009/01/31) Phillip Lougher
  597 10:52:54.550034  <5>[    0.930944] NFS: Registering the id_resolver key type
  598 10:52:54.556393  <5>[    0.936556] Key type id_resolver registered
  599 10:52:54.561279  <5>[    0.941251] Key type id_legacy registered
  600 10:52:54.569890  <6>[    0.945694] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
  601 10:52:54.576777  <6>[    0.952923] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
  602 10:52:54.647629  <5>[    1.027829] Key type asymmetric registered
  603 10:52:54.652508  <5>[    1.032409] Asymmetric key parser 'x509' registered
  604 10:52:54.661036  <6>[    1.037832] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 246)
  605 10:52:54.666135  <6>[    1.045752] io scheduler mq-deadline registered
  606 10:52:54.672273  <6>[    1.050702] io scheduler kyber registered
  607 10:52:54.675522  <6>[    1.055152] io scheduler bfq registered
  608 10:52:54.784144  <6>[    1.161329] ledtrig-cpu: registered to indicate activity on CPUs
  609 10:52:55.071307  <6>[    1.448248] Serial: 8250/16550 driver, 5 ports, IRQ sharing enabled
  610 10:52:55.124071  <6>[    1.505262] msm_serial: driver initialized
  611 10:52:55.130230  <6>[    1.510049] SuperH (H)SCI(F) driver initialized
  612 10:52:55.136517  <6>[    1.515414] STMicroelectronics ASC driver initialized
  613 10:52:55.138807  <6>[    1.521104] STM32 USART driver initialized
  614 10:52:55.242821  <6>[    1.623404] brd: module loaded
  615 10:52:55.277324  <6>[    1.657915] loop: module loaded
  616 10:52:55.320704  <6>[    1.701302] CAN device driver interface
  617 10:52:55.326842  <6>[    1.706356] bgmac_bcma: Broadcom 47xx GBit MAC driver loaded
  618 10:52:55.332950  <6>[    1.713433] e1000e: Intel(R) PRO/1000 Network Driver
  619 10:52:55.339326  <6>[    1.718818] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
  620 10:52:55.345310  <6>[    1.725302] igb: Intel(R) Gigabit Ethernet Network Driver
  621 10:52:55.353826  <6>[    1.731149] igb: Copyright (c) 2007-2014 Intel Corporation.
  622 10:52:55.359817  <6>[    1.740539] pegasus: Pegasus/Pegasus II USB Ethernet driver
  623 10:52:55.371133  <6>[    1.746619] usbcore: registered new interface driver pegasus
  624 10:52:55.377232  <6>[    1.752806] usbcore: registered new interface driver asix
  625 10:52:55.383521  <6>[    1.758662] usbcore: registered new interface driver ax88179_178a
  626 10:52:55.389637  <6>[    1.765251] usbcore: registered new interface driver cdc_ether
  627 10:52:55.394520  <6>[    1.771566] usbcore: registered new interface driver smsc75xx
  628 10:52:55.400638  <6>[    1.777774] usbcore: registered new interface driver smsc95xx
  629 10:52:55.405624  <6>[    1.784005] usbcore: registered new interface driver net1080
  630 10:52:55.411775  <6>[    1.790130] usbcore: registered new interface driver cdc_subset
  631 10:52:55.416631  <6>[    1.796541] usbcore: registered new interface driver zaurus
  632 10:52:55.424744  <6>[    1.802608] usbcore: registered new interface driver cdc_ncm
  633 10:52:55.434261  <6>[    1.812191] usbcore: registered new interface driver usb-storage
  634 10:52:55.444760  <6>[    1.823271] i2c_dev: i2c /dev entries driver
  635 10:52:55.468004  <5>[    1.841338] cpuidle: enable-method property 'ti,am3352' found operations
  636 10:52:55.474224  <6>[    1.850851] sdhci: Secure Digital Host Controller Interface driver
  637 10:52:55.481725  <6>[    1.857509] sdhci: Copyright(c) Pierre Ossman
  638 10:52:55.487723  <6>[    1.863929] Synopsys Designware Multimedia Card Interface Driver
  639 10:52:55.495013  <6>[    1.871819] sdhci-pltfm: SDHCI platform and OF driver helper
  640 10:52:55.508002  <6>[    1.881537] usbcore: registered new interface driver usbhid
  641 10:52:55.508386  <6>[    1.887567] usbhid: USB HID core driver
  642 10:52:55.520603  <6>[    1.899016] NET: Registered PF_INET6 protocol family
  643 10:52:55.970067  <6>[    2.351093] Segment Routing with IPv6
  644 10:52:55.976182  <6>[    2.355246] In-situ OAM (IOAM) with IPv6
  645 10:52:55.982318  <6>[    2.359635] sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver
  646 10:52:55.989826  <6>[    2.367024] NET: Registered PF_PACKET protocol family
  647 10:52:55.990209  <6>[    2.372585] can: controller area network core
  648 10:52:55.995923  <6>[    2.377416] NET: Registered PF_CAN protocol family
  649 10:52:56.002069  <6>[    2.382668] can: raw protocol
  650 10:52:56.005682  <6>[    2.385994] can: broadcast manager protocol
  651 10:52:56.011800  <6>[    2.390592] can: netlink gateway - max_hops=1
  652 10:52:56.018069  <5>[    2.396100] Key type dns_resolver registered
  653 10:52:56.024250  <6>[    2.401171] ThumbEE CPU extension supported.
  654 10:52:56.024632  <5>[    2.405858] Registering SWP/SWPB emulation handler
  655 10:52:56.033560  <3>[    2.411557] omap_voltage_late_init: Voltage driver support not added
  656 10:52:56.211806  <5>[    2.590479] Loading compiled-in X.509 certificates
  657 10:52:56.299849  <6>[    2.666908] /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70: Fixed dependency cycle(s) with /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
  658 10:52:56.329131  <6>[    2.696253] /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70: Fixed dependency cycle(s) with /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
  659 10:52:56.462994  <6>[    2.829475] /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70: Fixed dependency cycle(s) with /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
  660 10:52:56.483237  <6>[    2.849092] /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70: Fixed dependency cycle(s) with /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
  661 10:52:56.514634  <6>[    2.875427] /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800/clkout2-pins
  662 10:52:56.518995  <6>[    2.896939] pinctrl-single 44e10800.pinmux: 142 pins, size 568
  663 10:52:56.545997  <3>[    2.920924] ti-sysc 44e31000.target-module: probe with driver ti-sysc failed with error -16
  664 10:52:56.818923  <6>[    3.186457] /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
  665 10:52:56.846811  <3>[    3.221327] ti-sysc 48040000.target-module: probe with driver ti-sysc failed with error -16
  666 10:52:57.082027  <6>[    3.461339] OMAP GPIO hardware version 0.1
  667 10:52:57.102047  <6>[    3.479979] omap-mailbox 480c8000.mailbox: omap mailbox rev 0x400
  668 10:52:57.185668  <4>[    3.562355] at24 2-0054: supply vcc not found, using dummy regulator
  669 10:52:57.217552  <4>[    3.595241] at24 2-0055: supply vcc not found, using dummy regulator
  670 10:52:57.256675  <4>[    3.634883] at24 2-0056: supply vcc not found, using dummy regulator
  671 10:52:57.298811  <4>[    3.676874] at24 2-0057: supply vcc not found, using dummy regulator
  672 10:52:57.338926  <6>[    3.717307] omap_i2c 4819c000.i2c: bus 2 rev0.11 at 100 kHz
  673 10:52:57.399638  <3>[    3.772786] 48000000.interconnect:segment@200000:target-module@0:mpu@0:fck: device ID is greater than 24
  674 10:52:57.420563  <6>[    3.787077] /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
  675 10:52:57.443817  <6>[    3.810326] /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
  676 10:52:57.461183  <6>[    3.829454] /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70: Fixed dependency cycle(s) with /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
  677 10:52:57.481574  <6>[    3.847435] /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
  678 10:52:57.501820  <4>[    3.877779] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
  679 10:52:57.514937  <4>[    3.891043] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
  680 10:52:57.603691  <6>[    3.984324] Freeing initrd memory: 14488K
  681 10:52:57.611685  <6>[    3.990099] omap_rng 48310000.rng: Random Number Generator ver. 20
  682 10:52:57.635665  <5>[    4.016786] random: crng init done
  683 10:52:57.683535  <6>[    4.060237] davinci_mdio 4a101000.mdio: davinci mdio revision 1.6, bus freq 1000000
  684 10:52:57.766710  <6>[    4.142650] davinci_mdio 4a101000.mdio: phy[0]: device 4a101000.mdio:00, driver SMSC LAN8710/LAN8720
  685 10:52:57.772846  <6>[    4.152957] cpsw-switch 4a100000.switch: initialized cpsw ale version 1.4
  686 10:52:57.780201  <6>[    4.160288] cpsw-switch 4a100000.switch: ALE Table size 1024, Policers 0
  687 10:52:57.792326  <6>[    4.167735] cpsw-switch 4a100000.switch: cpts: overflow check period 500 (jiffies)
  688 10:52:57.800963  <6>[    4.175871] cpsw-switch 4a100000.switch: CPTS: ref_clk_freq:250000000 calc_mult:2147483648 calc_shift:29 error:0 nsec/sec
  689 10:52:57.813575  <6>[    4.187513] cpsw-switch 4a100000.switch: Detected MACID = 04:79:b7:e7:06:e0
  690 10:52:57.822819  <5>[    4.196558] cpsw-switch 4a100000.switch: initialized (regs 0x4a100000, pool size 256) hw_ver:0019010C 1.12 (0)
  691 10:52:57.851325  <3>[    4.226362] debugfs: Directory '49000000.dma' with parent 'dmaengine' already present!
  692 10:52:57.855704  <6>[    4.234962] edma 49000000.dma: TI EDMA DMA engine driver
  693 10:52:57.926691  <3>[    4.302454] target-module@4b000000:target-module@140000:pmu@0:fck: device ID is greater than 24
  694 10:52:57.941933  <6>[    4.316783] hw perfevents: enabled with armv7_cortex_a8 PMU driver, 5 (8000000f) counters available
  695 10:52:57.955534  <3>[    4.333873] l3-aon-clkctrl:0000:0: failed to disable
  696 10:52:58.005954  <6>[    4.381367] 44e09000.serial: ttyS0 at MMIO 0x44e09000 (irq = 36, base_baud = 3000000) is a 8250
  697 10:52:58.010814  <6>[    4.390842] printk: legacy console [ttyS0] enabled
  698 10:52:58.019437  <6>[    4.390842] printk: legacy console [ttyS0] enabled
  699 10:52:58.025569  <6>[    4.401173] printk: legacy bootconsole [omap8250] disabled
  700 10:52:58.028835  <6>[    4.401173] printk: legacy bootconsole [omap8250] disabled
  701 10:52:58.065563  <4>[    4.440990] tps65217-pmic: Failed to locate of_node [id: -1]
  702 10:52:58.069936  <4>[    4.448378] tps65217-bl: Failed to locate of_node [id: -1]
  703 10:52:58.085576  <6>[    4.467913] tps65217 0-0024: TPS65217 ID 0xe version 1.2
  704 10:52:58.106691  <6>[    4.474843] /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
  705 10:52:58.127566  <6>[    4.492507] /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70: Fixed dependency cycle(s) with /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
  706 10:52:58.131930  <6>[    4.510359] omap_i2c 44e0b000.i2c: bus 0 rev0.11 at 400 kHz
  707 10:52:58.153695  <6>[    4.530338] omap_gpio 44e07000.gpio: Could not set line 6 debounce to 200000 microseconds (-22)
  708 10:52:58.159697  <6>[    4.539398] sdhci-omap 48060000.mmc: Got CD GPIO
  709 10:52:58.167942  <4>[    4.544573] sdhci-omap 48060000.mmc: supply pbias not found, using dummy regulator
  710 10:52:58.182576  <4>[    4.558179] sdhci-omap 48060000.mmc: supply vqmmc not found, using dummy regulator
  711 10:52:58.190821  <4>[    4.566975] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
  712 10:52:58.224689  <4>[    4.601654] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
  713 10:52:58.322941  <6>[    4.700321] at24 0-0050: 32768 byte 24c256 EEPROM, writable, 1 bytes/write
  714 10:52:58.360178  <6>[    4.735876] mmc0: SDHCI controller on 48060000.mmc [48060000.mmc] using External DMA
  715 10:52:58.393826  <6>[    4.769695] mmc1: SDHCI controller on 481d8000.mmc [481d8000.mmc] using External DMA
  716 10:52:58.400697  <6>[    4.778476] cpsw-switch 4a100000.switch: starting ndev. mode: dual_mac
  717 10:52:58.469019  <6>[    4.840517] mmc1: new high speed MMC card at address 0001
  718 10:52:58.469401  <6>[    4.848690] mmcblk1: mmc1:0001 M62704 3.56 GiB
  719 10:52:58.479651  <6>[    4.859580]  mmcblk1: p1
  720 10:52:58.486564  <6>[    4.864888] mmcblk1boot0: mmc1:0001 M62704 2.00 MiB
  721 10:52:58.495821  <6>[    4.875366] mmcblk1boot1: mmc1:0001 M62704 2.00 MiB
  722 10:52:58.510444  <6>[    4.885925] SMSC LAN8710/LAN8720 4a101000.mdio:00: attached PHY driver (mii_bus:phy_addr=4a101000.mdio:00, irq=POLL)
  723 10:52:58.518796  <6>[    4.897328] mmcblk1rpmb: mmc1:0001 M62704 512 KiB, chardev (236:0)
  724 10:53:00.645769  <6>[    7.021275] cpsw-switch 4a100000.switch eth0: Link is Up - 100Mbps/Full - flow control off
  725 10:53:00.729153  <5>[    7.050242] Sending DHCP requests ., OK
  726 10:53:00.740155  <6>[    7.114745] IP-Config: Got DHCP answer from 172.16.3.3, my address is 172.16.3.190
  727 10:53:00.740534  <6>[    7.122786] IP-Config: Complete:
  728 10:53:00.754786  <6>[    7.126322]      device=eth0, hwaddr=04:79:b7:e7:06:e0, ipaddr=172.16.3.190, mask=255.255.255.0, gw=172.16.3.3
  729 10:53:00.759671  <6>[    7.136773]      host=172.16.3.190, domain=denx.de, nis-domain=(none)
  730 10:53:00.764818  <6>[    7.143616]      bootserver=172.16.3.33, rootserver=172.16.3.3, rootpath=
  731 10:53:00.769649  <6>[    7.143651]      nameserver0=172.16.3.3
  732 10:53:00.777070  <6>[    7.154962]      ntpserver0=172.16.3.3
  733 10:53:00.785276  <6>[    7.160508] clk: Disabling unused clocks
  734 10:53:00.785658  <6>[    7.165116] PM: genpd: Disabling unused power domains
  735 10:53:00.813656  <6>[    7.183325] Freeing unused kernel image (initmem) memory: 2048K
  736 10:53:00.814041  <6>[    7.193629] Run /init as init process
  737 10:53:00.836531  Loading, please wait...
  738 10:53:00.911184  Starting systemd-udevd version 252.22-1~deb12u1
  739 10:53:03.978897  <4>[   10.353181] am335x-phy-driver 47401300.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
  740 10:53:04.135642  <4>[   10.510580] am335x-phy-driver 47401b00.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
  741 10:53:04.329914  <6>[   10.711761] musb-hdrc musb-hdrc.1: MUSB HDRC host driver
  742 10:53:04.340644  <6>[   10.717436] musb-hdrc musb-hdrc.1: new USB bus registered, assigned bus number 1
  743 10:53:04.579618  <6>[   10.960817] hub 1-0:1.0: USB hub found
  744 10:53:04.649118  <6>[   11.029227] hub 1-0:1.0: 1 port detected
  745 10:53:04.802879  <6>[   11.183454] tda998x 0-0070: found TDA19988
  746 10:53:07.419469  Begin: Loading essential drivers ... done.
  747 10:53:07.424370  Begin: Running /scripts/init-premount ... done.
  748 10:53:07.430371  Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
  749 10:53:07.443589  Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
  750 10:53:07.443968  Device /sys/class/net/eth0 found
  751 10:53:07.444280  done.
  752 10:53:07.533734  Begin: Waiting up to 180 secs for any network device to become available ... done.
  753 10:53:07.622470  IP-Config: eth0 hardware address 04:79:b7:e7:06:e0 mtu 1500 DHCP
  754 10:53:07.674222  IP-Config: eth0 complete (dhcp from 172.16.3.3):
  755 10:53:07.684244   address: 172.16.3.190     broadcast: 172.16.3.255     netmask: 255.255.255.0   
  756 10:53:07.689102   gateway: 172.16.3.3       dns0     : 172.16.3.3       dns1   : 0.0.0.0         
  757 10:53:07.694118   domain : denx.de                                                         
  758 10:53:07.700232   rootserver: 172.16.3.33 rootpath: 
  759 10:53:07.704659   filename  : this-host-is-not-configured.kpxe
  760 10:53:07.746151  done.
  761 10:53:07.754555  Begin: Running /scripts/nfs-bottom ... done.
  762 10:53:07.823668  Begin: Running /scripts/init-bottom ... done.
  763 10:53:09.046161  <30>[   15.424216] systemd[1]: System time before build time, advancing clock.
  764 10:53:09.246296  <30>[   15.597958] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
  765 10:53:09.254390  <30>[   15.634702] systemd[1]: Detected architecture arm.
  766 10:53:09.267908  
  767 10:53:09.268294  Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
  768 10:53:09.268603  
  769 10:53:09.293418  <30>[   15.670919] systemd[1]: Hostname set to <debian-bookworm-armhf>.
  770 10:53:11.668567  <30>[   18.045477] systemd[1]: Queued start job for default target graphical.target.
  771 10:53:11.685434  <30>[   18.060599] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
  772 10:53:11.692327  [[0;32m  OK  [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
  773 10:53:11.717696  <30>[   18.093738] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
  774 10:53:11.725936  [[0;32m  OK  [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
  775 10:53:11.747811  <30>[   18.123638] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
  776 10:53:11.756320  [[0;32m  OK  [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
  777 10:53:11.777126  <30>[   18.152459] systemd[1]: Created slice user.slice - User and Session Slice.
  778 10:53:11.783917  [[0;32m  OK  [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
  779 10:53:11.812740  <30>[   18.181560] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
  780 10:53:11.819604  [[0;32m  OK  [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
  781 10:53:11.846891  <30>[   18.221364] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
  782 10:53:11.856617  [[0;32m  OK  [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
  783 10:53:11.883986  <30>[   18.251324] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
  784 10:53:11.897509  <30>[   18.273401] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
  785 10:53:11.903000           Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
  786 10:53:11.925061  <30>[   18.300703] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
  787 10:53:11.932990  [[0;32m  OK  [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
  788 10:53:11.955112  <30>[   18.331086] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
  789 10:53:11.963480  [[0;32m  OK  [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
  790 10:53:11.985328  <30>[   18.361113] systemd[1]: Reached target paths.target - Path Units.
  791 10:53:11.989707  [[0;32m  OK  [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
  792 10:53:12.015088  <30>[   18.390904] systemd[1]: Reached target remote-fs.target - Remote File Systems.
  793 10:53:12.021835  [[0;32m  OK  [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
  794 10:53:12.045137  <30>[   18.420840] systemd[1]: Reached target slices.target - Slice Units.
  795 10:53:12.050615  [[0;32m  OK  [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
  796 10:53:12.074892  <30>[   18.451006] systemd[1]: Reached target swap.target - Swaps.
  797 10:53:12.079121  [[0;32m  OK  [0m] Reached target [0;1;39mswap.target[0m - Swaps.
  798 10:53:12.104522  <30>[   18.480946] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
  799 10:53:12.112985  [[0;32m  OK  [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
  800 10:53:12.135742  <30>[   18.511868] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
  801 10:53:12.144119  [[0;32m  OK  [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
  802 10:53:12.229666  <30>[   18.601070] systemd[1]: systemd-journald-audit.socket - Journal Audit Socket was skipped because of an unmet condition check (ConditionSecurity=audit).
  803 10:53:12.243257  <30>[   18.618722] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
  804 10:53:12.250616  [[0;32m  OK  [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
  805 10:53:12.277135  <30>[   18.654714] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
  806 10:53:12.289928  [[0;32m  OK  [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
  807 10:53:12.318508  <30>[   18.693149] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
  808 10:53:12.325716  [[0;32m  OK  [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
  809 10:53:12.351150  <30>[   18.725409] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
  810 10:53:12.357491  [[0;32m  OK  [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
  811 10:53:12.389030  <30>[   18.763557] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
  812 10:53:12.395924  [[0;32m  OK  [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
  813 10:53:12.422270  <30>[   18.791831] systemd[1]: dev-hugepages.mount - Huge Pages File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/mm/hugepages).
  814 10:53:12.435605  <30>[   18.808302] systemd[1]: dev-mqueue.mount - POSIX Message Queue File System was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/mqueue).
  815 10:53:12.485008  <30>[   18.860759] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
  816 10:53:12.491865           Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
  817 10:53:12.531028  <30>[   18.907937] systemd[1]: Mounting sys-kernel-tracing.mount - Kernel Trace File System...
  818 10:53:12.549125           Mounting [0;1;39msys-kernel-tracin…[0m - Kernel Trace File System...
  819 10:53:12.620313  <30>[   18.995518] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
  820 10:53:12.632187           Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
  821 10:53:12.706996  <30>[   19.081332] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
  822 10:53:12.712992           Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
  823 10:53:12.768121  <30>[   19.144629] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
  824 10:53:12.785325           Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
  825 10:53:12.816319  <30>[   19.194210] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
  826 10:53:12.839747           Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
  827 10:53:12.898099  <30>[   19.274129] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
  828 10:53:12.911871           Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
  829 10:53:12.942854  <30>[   19.319596] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
  830 10:53:12.965194           Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
  831 10:53:13.004628  <30>[   19.381479] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
  832 10:53:13.020558           Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
  833 10:53:13.040490  <28>[   19.412662] systemd[1]: systemd-journald.service: unit configures an IP firewall, but the local system does not support BPF/cgroup firewalling.
  834 10:53:13.056836  <28>[   19.432360] systemd[1]: (This warning is only shown for the first unit using IP firewalling.)
  835 10:53:13.106354  <30>[   19.481453] systemd[1]: Starting systemd-journald.service - Journal Service...
  836 10:53:13.111943           Starting [0;1;39msystemd-journald.service[0m - Journal Service...
  837 10:53:13.185061  <30>[   19.561748] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
  838 10:53:13.204300           Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
  839 10:53:13.236780  <30>[   19.613559] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
  840 10:53:13.288567           Starting [0;1;39msystemd-network-g… units from Kernel command line...
  841 10:53:13.339661  <30>[   19.715607] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
  842 10:53:13.394619           Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
  843 10:53:13.450153  <30>[   19.826058] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
  844 10:53:13.504278           Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
  845 10:53:13.533175  <30>[   19.909994] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
  846 10:53:13.623027  [[0;32m  OK  [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
  847 10:53:13.645453  <30>[   20.022597] systemd[1]: Mounted sys-kernel-tracing.mount - Kernel Trace File System.
  848 10:53:13.684953  [[0;32m  OK  [0m] Mounted [0;1;39msys-kernel-tracing…nt[0m - Kernel Trace File System.
  849 10:53:13.706481  <30>[   20.082706] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
  850 10:53:13.733154  [[0;32m  OK  [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
  851 10:53:13.895928  <30>[   20.273055] systemd[1]: modprobe@configfs.service: Deactivated successfully.
  852 10:53:13.925918  <30>[   20.301995] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
  853 10:53:13.954725  [[0;32m  OK  [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
  854 10:53:13.984532  <30>[   20.363020] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
  855 10:53:14.015275  <30>[   20.392086] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
  856 10:53:14.043938  [[0;32m  OK  [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
  857 10:53:14.065326  <30>[   20.442193] systemd[1]: Started systemd-journald.service - Journal Service.
  858 10:53:14.093063  [[0;32m  OK  [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
  859 10:53:14.126140  [[0;32m  OK  [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
  860 10:53:14.157212  [[0;32m  OK  [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
  861 10:53:14.180628  [[0;32m  OK  [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
  862 10:53:14.214715  [[0;32m  OK  [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
  863 10:53:14.246747  [[0;32m  OK  [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
  864 10:53:14.267108  [[0;32m  OK  [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
  865 10:53:14.287359  [[0;32m  OK  [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
  866 10:53:14.318280  [[0;32m  OK  [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
  867 10:53:14.383907           Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
  868 10:53:14.454691           Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
  869 10:53:14.498224           Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
  870 10:53:14.566916           Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
  871 10:53:14.662381           Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
  872 10:53:14.809318  [[0;32m  OK  [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
  873 10:53:14.846544  <46>[   21.223073] systemd-journald[163]: Received client request to flush runtime journal.
  874 10:53:15.008471  [[0;32m  OK  [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
  875 10:53:15.066833  [[0;32m  OK  [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
  876 10:53:15.116469           Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
  877 10:53:15.201178  [[0;32m  OK  [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
  878 10:53:16.174102  [[0;32m  OK  [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
  879 10:53:16.195641  [[0;32m  OK  [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
  880 10:53:16.213971  [[0;32m  OK  [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
  881 10:53:16.507558           Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
  882 10:53:17.052215  [[0;32m  OK  [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
  883 10:53:17.116738           Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
  884 10:53:17.624774  [[0;32m  OK  [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
  885 10:53:17.705203           Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
  886 10:53:19.742192  [[0m[0;31m*     [0m] (1 of 4) Job systemd-networkd.service/start running (8s / 1min 35s)
  887 10:53:20.164902  M[K[[0;32m  OK  [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
  888 10:53:20.345558  [K<5>[   26.723286] cfg80211: Loading compiled-in X.509 certificates for regulatory database
  889 10:53:20.472675  [[0;32m  OK  [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
  890 10:53:21.055363  [[0;32m  OK  [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
  891 10:53:21.719348  <5>[   28.098668] Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
  892 10:53:21.771974  <5>[   28.145830] Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
  893 10:53:21.785037  <4>[   28.156334] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
  894 10:53:21.785423  <6>[   28.165470] cfg80211: failed to load regulatory.db
  895 10:53:22.879555  [[0;32m  OK  [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
  896 10:53:30.462269  [[0;32m  OK  [0m] Reached target [0;1;39mnetwork.target[0m - Network.
  897 10:53:30.485724  [[0;32m  OK  [0m] Reached target [0;1;39musb-gadget.…m - Hardware activated USB gadget.
  898 10:53:30.506046  [[0;32m  OK  [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
  899 10:53:30.564208           Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
  900 10:53:30.607739           Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
  901 10:53:30.654414           Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
  902 10:53:30.701141           Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
  903 10:53:30.965119           Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
  904 10:53:31.008427           Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
  905 10:53:31.049832  [[0;32m  OK  [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
  906 10:53:31.087152  [[0;32m  OK  [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
  907 10:53:31.125356  [[0;32m  OK  [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
  908 10:53:31.169956  [[0;32m  OK  [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
  909 10:53:31.353823  [[0;32m  OK  [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
  910 10:53:31.859694  [[0;32m  OK  [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
  911 10:53:31.885174  [[0;32m  OK  [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
  912 10:53:31.913820  [[0;32m  OK  [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
  913 10:53:31.934139  [[0;32m  OK  [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
  914 10:53:32.143364  [[0;32m  OK  [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
  915 10:53:32.230309  [[0;32m  OK  [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
  916 10:53:32.256004  [[0;32m  OK  [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
  917 10:53:32.346094  [[0;32m  OK  [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
  918 10:53:32.469906  [[0;32m  OK  [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
  919 10:53:32.494302  [[0;32m  OK  [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
  920 10:53:32.524318  [[0;32m  OK  [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
  921 10:53:32.544411  [[0;32m  OK  [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
  922 10:53:32.569913  [[0;32m  OK  [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
  923 10:53:32.645069           Starting [0;1;39malsa-restore.serv…- Save/Restore Sound Card State...
  924 10:53:32.695140           Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
  925 10:53:32.970152           Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
  926 10:53:33.133894           Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
  927 10:53:33.170023           Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
  928 10:53:33.192424  [[0;32m  OK  [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
  929 10:53:33.288927  [[0;32m  OK  [0m] Finished [0;1;39malsa-restore.serv…m - Save/Restore Sound Card State.
  930 10:53:33.312222  [[0;32m  OK  [0m] Reached target [0;1;39msound.target[0m - Sound Card.
  931 10:53:33.523356           Starting [0;1;39msystemd-hostnamed.service[0m - Hostname Service...
  932 10:53:33.543682  [[0;32m  OK  [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
  933 10:53:33.604094  [[0;32m  OK  [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
  934 10:53:33.666773  [[0;32m  OK  [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
  935 10:53:33.701764  [[0;32m  OK  [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
  936 10:53:33.820142  [[0;32m  OK  [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
  937 10:53:34.367158  [[0;32m  OK  [0m] Started [0;1;39msystemd-hostnamed.service[0m - Hostname Service.
  938 10:53:34.467796  [[0;32m  OK  [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
  939 10:53:34.533353  [[0;32m  OK  [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
  940 10:53:34.558111  [[0;32m  OK  [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
  941 10:53:34.666021           Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
  942 10:53:34.927000  [[0;32m  OK  [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
  943 10:53:35.165565  
  944 10:53:35.171045  Debian GNU/Linux 12 debian-bookworm-armworm-armhf login: root (automatic login)
  945 10:53:35.171430  
  946 10:53:35.516103  Linux debian-bookworm-armhf 6.12.0-rc6-next-20241108 #1 SMP Fri Nov  8 10:24:22 UTC 2024 armv7l
  947 10:53:35.516495  
  948 10:53:35.522119  The programs included with the Debian GNU/Linux system are free software;
  949 10:53:35.530662  the exact distribution terms for each program are described in the
  950 10:53:35.536840  individual files in /usr/share/doc/*/copyright.
  951 10:53:35.537218  
  952 10:53:35.543562  Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
  953 10:53:35.543939  permitted by applicable law.
  954 10:53:40.342887  Unable to match end of the kernel message
  956 10:53:40.343904  Setting prompt string to ['/ #']
  957 10:53:40.344332  end: 2.4.4.1 login-action (duration 00:00:47) [common]
  959 10:53:40.345328  end: 2.4.4 auto-login-action (duration 00:00:48) [common]
  960 10:53:40.345751  start: 2.4.5 expect-shell-connection (timeout 00:03:11) [common]
  961 10:53:40.346104  Setting prompt string to ['/ #']
  962 10:53:40.346405  Forcing a shell prompt, looking for ['/ #']
  964 10:53:40.397173  / # 
  965 10:53:40.397687  expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
  966 10:53:40.398057  Waiting using forced prompt support (timeout 00:02:30)
  967 10:53:40.404589  
  968 10:53:40.410409  end: 2.4.5 expect-shell-connection (duration 00:00:00) [common]
  969 10:53:40.410903  start: 2.4.6 export-device-env (timeout 00:03:11) [common]
  970 10:53:40.411278  Sending with 10 millisecond of delay
  972 10:53:45.468422  / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/1219249/extract-nfsrootfs-pybfeead'
  973 10:53:45.479192  export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/1219249/extract-nfsrootfs-pybfeead'
  974 10:53:45.481752  Sending with 10 millisecond of delay
  976 10:53:47.523088  / # export NFS_SERVER_IP='172.16.3.3'
  977 10:53:47.533796  export NFS_SERVER_IP='172.16.3.3'
  978 10:53:47.534504  end: 2.4.6 export-device-env (duration 00:00:07) [common]
  979 10:53:47.534956  end: 2.4 uboot-commands (duration 00:01:56) [common]
  980 10:53:47.535409  end: 2 uboot-action (duration 00:01:56) [common]
  981 10:53:47.535840  start: 3 lava-test-retry (timeout 00:06:54) [common]
  982 10:53:47.536280  start: 3.1 lava-test-shell (timeout 00:06:54) [common]
  983 10:53:47.536623  Using namespace: common
  985 10:53:47.637671  / # #
  986 10:53:47.638178  lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
  987 10:53:47.644838  #
  988 10:53:47.650700  Using /lava-1219249
  990 10:53:47.751772  / # export SHELL=/bin/bash
  991 10:53:47.758932  export SHELL=/bin/bash
  993 10:53:47.868649  / # . /lava-1219249/environment
  994 10:53:47.876070  . /lava-1219249/environment
  996 10:53:47.990219  / # /lava-1219249/bin/lava-test-runner /lava-1219249/0
  997 10:53:47.990738  Test shell timeout: 10s (minimum of the action and connection timeout)
  998 10:53:47.997746  /lava-1219249/bin/lava-test-runner /lava-1219249/0
  999 10:53:48.586740  + export TESTRUN_ID=0_timesync-off
 1000 10:53:48.594943  + TESTRUN_ID=0_timesync-off
 1001 10:53:48.595327  + cd /lava-1219249/0/tests/0_timesync-off
 1002 10:53:48.595642  ++ cat uuid
 1003 10:53:48.618103  + UUID=1219249_1.6.2.4.1
 1004 10:53:48.618492  + set +x
 1005 10:53:48.624306  <LAVA_SIGNAL_STARTRUN 0_timesync-off 1219249_1.6.2.4.1>
 1006 10:53:48.624945  Received signal: <STARTRUN> 0_timesync-off 1219249_1.6.2.4.1
 1007 10:53:48.625292  Starting test lava.0_timesync-off (1219249_1.6.2.4.1)
 1008 10:53:48.625672  Skipping test definition patterns.
 1009 10:53:48.627583  + systemctl stop systemd-timesyncd
 1010 10:53:48.975706  + set +x
 1011 10:53:48.976331  Received signal: <ENDRUN> 0_timesync-off 1219249_1.6.2.4.1
 1012 10:53:48.976714  Ending use of test pattern.
 1013 10:53:48.977053  Ending test lava.0_timesync-off (1219249_1.6.2.4.1), duration 0.35
 1015 10:53:48.978913  <LAVA_SIGNAL_ENDRUN 0_timesync-off 1219249_1.6.2.4.1>
 1016 10:53:49.309179  + export TESTRUN_ID=1_kselftest-dt
 1017 10:53:49.317309  + TESTRUN_ID=1_kselftest-dt
 1018 10:53:49.317696  + cd /lava-1219249/0/tests/1_kselftest-dt
 1019 10:53:49.318012  ++ cat uuid
 1020 10:53:49.334513  + UUID=1219249_1.6.2.4.5
 1021 10:53:49.334900  + set +x
 1022 10:53:49.340679  <LAVA_SIGNAL_STARTRUN 1_kselftest-dt 1219249_1.6.2.4.5>
 1023 10:53:49.341094  + cd ./automated/linux/kselftest/
 1024 10:53:49.341646  Received signal: <STARTRUN> 1_kselftest-dt 1219249_1.6.2.4.5
 1025 10:53:49.341965  Starting test lava.1_kselftest-dt (1219249_1.6.2.4.5)
 1026 10:53:49.342327  Skipping test definition patterns.
 1027 10:53:49.366342  + ./kselftest.sh -c dt -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/next/master/next-20241108/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz -L '' -S /dev/null -b beaglebone-black -g next -e '' -p /opt/kselftests/mainline/ -n 1 -i 1 -E ''
 1028 10:53:49.517965  INFO: install_deps skipped
 1029 10:53:50.079096  --2024-01-26 21:49:17--  http://storage.kernelci.org/next/master/next-20241108/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz
 1030 10:53:50.135595  Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
 1031 10:53:50.295221  Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
 1032 10:53:50.449280  HTTP request sent, awaiting response... 200 OK
 1033 10:53:50.449663  Length: 4158336 (4.0M) [application/octet-stream]
 1034 10:53:50.454211  Saving to: 'kselftest_armhf.tar.gz'
 1035 10:53:50.454589  
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 1180 10:54:14.797075  tar: ./net/packetdrill/tcp_zerocopy_epoll_oneshot.pkt: time stamp 2024-11-05 07:29:13 is 24485971.250949534 s in the future
 1181 10:54:14.923399  tar: ./net/packetdrill/tcp_md5_md5-only-on-client-ack.pkt: time stamp 2024-11-05 07:29:13 is 24485971.124580743 s in the future
 1182 10:54:15.379493  tar: ./net/packetdrill/tcp_slow_start_slow-start-app-limited-9-packets-out.pkt: time stamp 2024-11-05 07:29:13 is 24485970.669567576 s in the future
 1183 10:54:15.506013  tar: ./net/packetdrill/tcp_slow_start_slow-start-fq-ack-per-2pkt.pkt: time stamp 2024-11-05 07:29:13 is 24485970.542143701 s in the future
 1184 10:54:15.630130  tar: ./net/packetdrill/tcp_zerocopy_maxfrags.pkt: time stamp 2024-11-05 07:29:13 is 24485970.415919201 s in the future
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 1187 10:54:16.003437  tar: ./net/packetdrill/tcp_zerocopy_fastopen-server.pkt: time stamp 2024-11-05 07:29:13 is 24485970.043930201 s in the future
 1188 10:54:16.134077  tar: ./net/packetdrill/tcp_slow_start_slow-start-after-win-update.pkt: time stamp 2024-11-05 07:29:13 is 24485969.914347159 s in the future
 1189 10:54:16.258465  tar: ./net/packetdrill/tcp_slow_start_slow-start-ack-per-2pkt.pkt: time stamp 2024-11-05 07:29:13 is 24485969.790176534 s in the future
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 1226 10:54:22.137821  tar: ./net/forwarding/ip6gre_inner_v6_multipath.sh: time stamp 2024-11-05 07:29:13 is 24485963.908505825 s in the future
 1227 10:54:22.266826  tar: ./net/forwarding/sch_ets.sh: time stamp 2024-11-05 07:29:13 is 24485963.7774907 s in the future
 1228 10:54:22.381467  tar: ./net/forwarding/ip6gre_hier_key.sh: time stamp 2024-11-05 07:29:13 is 24485963.664080283 s in the future
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 1230 10:54:22.673228  tar: ./net/forwarding/ip6gre_flat.sh: time stamp 2024-11-05 07:29:13 is 24485963.371794075 s in the future
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 1233 10:54:23.085290  tar: ./net/forwarding/lib.sh: time stamp 2024-11-05 07:29:13 is 24485962.959661825 s in the future
 1234 10:54:23.217919  tar: ./net/forwarding/skbedit_priority.sh: time stamp 2024-11-05 07:29:13 is 24485962.828790325 s in the future
 1235 10:54:23.347276  tar: ./net/forwarding/ip6gre_flat_keys.sh: time stamp 2024-11-05 07:29:13 is 24485962.698856992 s in the future
 1236 10:54:23.474648  tar: ./net/forwarding/min_max_mtu.sh: time stamp 2024-11-05 07:29:13 is 24485962.571113742 s in the future
 1237 10:54:23.617927  tar: ./net/forwarding/bridge_mdb.sh: time stamp 2024-11-05 07:29:13 is 24485962.428283742 s in the future
 1238 10:54:23.764414  tar: ./net/forwarding/vxlan_bridge_1q_port_8472_ipv6.sh: time stamp 2024-11-05 07:29:13 is 24485962.282896242 s in the future
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 1240 10:54:24.042895  tar: ./net/forwarding/mirror_gre_flower.sh: time stamp 2024-11-05 07:29:13 is 24485962.003669033 s in the future
 1241 10:54:24.187911  tar: ./net/forwarding/vxlan_symmetric.sh: time stamp 2024-11-05 07:29:13 is 24485961.857619033 s in the future
 1242 10:54:24.317005  tar: ./net/forwarding/ip6gre_hier_keys.sh: time stamp 2024-11-05 07:29:13 is 24485961.728444658 s in the future
 1243 10:54:24.454959  tar: ./net/forwarding/fib_offload_lib.sh: time stamp 2024-11-05 07:29:13 is 24485961.591498158 s in the future
 1244 10:54:24.589390  tar: ./net/forwarding/sch_tbf_ets.sh: time stamp 2024-11-05 07:29:13 is 24485961.455840575 s in the future
 1245 10:54:24.729641  tar: ./net/forwarding/vxlan_bridge_1d_ipv6.sh: time stamp 2024-11-05 07:29:13 is 24485961.316393741 s in the future
 1246 10:54:24.851681  tar: ./net/forwarding/sch_tbf_etsprio.sh: time stamp 2024-11-05 07:29:13 is 24485961.194390866 s in the future
 1247 10:54:24.972883  tar: ./net/forwarding/mirror_gre_bridge_1d_vlan.sh: time stamp 2024-11-05 07:29:13 is 24485961.074092283 s in the future
 1248 10:54:25.110406  tar: ./net/forwarding/ipip_hier_gre_keys.sh: time stamp 2024-11-05 07:29:13 is 24485960.93505445 s in the future
 1249 10:54:25.249462  tar: ./net/forwarding/mirror_gre_lag_lacp.sh: time stamp 2024-11-05 07:29:13 is 24485960.796634408 s in the future
 1250 10:54:25.368163  tar: ./net/forwarding/lib_sh_test.sh: time stamp 2024-11-05 07:29:13 is 24485960.67654745 s in the future
 1251 10:54:25.514662  tar: ./net/forwarding/vxlan_bridge_1d.sh: time stamp 2024-11-05 07:29:13 is 24485960.53128995 s in the future
 1252 10:54:25.652256  tar: ./net/forwarding/router_vid_1.sh: time stamp 2024-11-05 07:29:13 is 24485960.39266495 s in the future
 1253 10:54:25.785935  tar: ./net/forwarding/ipip_flat_gre_keys.sh: time stamp 2024-11-05 07:29:13 is 24485960.2606887 s in the future
 1254 10:54:25.915478  tar: ./net/forwarding/ip6gre_inner_v4_multipath.sh: time stamp 2024-11-05 07:29:13 is 24485960.130885741 s in the future
 1255 10:54:26.044704  tar: ./net/forwarding/mirror_gre_topo_lib.sh: time stamp 2024-11-05 07:29:13 is 24485960.001394866 s in the future
 1256 10:54:26.180248  tar: ./net/forwarding/tc_police.sh: time stamp 2024-11-05 07:29:13 is 24485959.864678283 s in the future
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 1259 10:54:26.615861  tar: ./net/forwarding/sch_tbf_prio.sh: time stamp 2024-11-05 07:29:13 is 24485959.430237116 s in the future
 1260 10:54:26.746262  tar: ./net/forwarding/router_bridge_vlan.sh: time stamp 2024-11-05 07:29:13 is 24485959.299803158 s in the future
 1261 10:54:26.870132  tar: ./net/forwarding/tc_flower_cfm.sh: time stamp 2024-11-05 07:29:13 is 24485959.174747408 s in the future
 1262 10:54:27.006832  tar: ./net/forwarding/ipip_lib.sh: time stamp 2024-11-05 07:29:13 is 24485959.038598575 s in the future
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 1265 10:54:27.413276  tar: ./net/forwarding/router_mpath_nh.sh: time stamp 2024-11-05 07:29:13 is 24485958.632344991 s in the future
 1266 10:54:27.537451  tar: ./net/forwarding/mirror_gre_bound.sh: time stamp 2024-11-05 07:29:13 is 24485958.508252408 s in the future
 1267 10:54:27.674293  tar: ./net/forwarding/router_bridge.sh: time stamp 2024-11-05 07:29:13 is 24485958.370784408 s in the future
 1268 10:54:27.842613  tar: ./net/forwarding/tc_shblocks.sh: time stamp 2024-11-05 07:29:13 is 24485958.202300033 s in the future
 1269 10:54:27.983857  tar: ./net/forwarding/ipip_hier_gre_key.sh: time stamp 2024-11-05 07:29:13 is 24485958.062545449 s in the future
 1270 10:54:28.122765  tar: ./net/forwarding/ipip_hier_gre.sh: time stamp 2024-11-05 07:29:13 is 24485957.923180533 s in the future
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 1272 10:54:28.442501  tar: ./net/forwarding/ipip_flat_gre_key.sh: time stamp 2024-11-05 07:29:13 is 24485957.603375033 s in the future
 1273 10:54:28.580208  tar: ./net/forwarding/pedit_dsfield.sh: time stamp 2024-11-05 07:29:13 is 24485957.464368158 s in the future
 1274 10:54:28.719449  tar: ./net/forwarding/router_mpath_seed.sh: time stamp 2024-11-05 07:29:13 is 24485957.326282449 s in the future
 1275 10:54:28.887845  tar: ./net/forwarding/q_in_vni.sh: time stamp 2024-11-05 07:29:13 is 24485957.157201033 s in the future
 1276 10:54:29.050886  tar: ./net/forwarding/mirror_topo_lib.sh: time stamp 2024-11-05 07:29:13 is 24485956.994149324 s in the future
 1277 10:54:29.202635  tar: ./net/forwarding/vxlan_bridge_1d_port_8472.sh: time stamp 2024-11-05 07:29:13 is 24485956.844131366 s in the future
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 1279 10:54:29.495283  tar: ./net/forwarding/tc_flower_l2_miss.sh: time stamp 2024-11-05 07:29:13 is 24485956.550438408 s in the future
 1280 10:54:29.643867  tar: ./net/forwarding/tc_tunnel_key.sh: time stamp 2024-11-05 07:29:13 is 24485956.401833908 s in the future
 1281 10:54:29.772036  tar: ./net/forwarding/bridge_sticky_fdb.sh: time stamp 2024-11-05 07:29:13 is 24485956.272807533 s in the future
 1282 10:54:29.908833  tar: ./net/forwarding/bridge_fdb_learning_limit.sh: time stamp 2024-11-05 07:29:13 is 24485956.137951324 s in the future
 1283 10:54:30.079550  tar: ./net/forwarding/ip6_forward_instats_vrf.sh: time stamp 2024-11-05 07:29:13 is 24485955.966423616 s in the future
 1284 10:54:30.231061  tar: ./net/forwarding/router_multicast.sh: time stamp 2024-11-05 07:29:13 is 24485955.814682949 s in the future
 1285 10:54:30.362431  tar: ./net/forwarding/ip6gre_hier.sh: time stamp 2024-11-05 07:29:13 is 24485955.682714741 s in the future
 1286 10:54:30.510793  tar: ./net/forwarding/local_termination.sh: time stamp 2024-11-05 07:29:13 is 24485955.534694949 s in the future
 1287 10:54:30.663707  tar: ./net/forwarding/tc_flower_router.sh: time stamp 2024-11-05 07:29:13 is 24485955.382386366 s in the future
 1288 10:54:30.799647  tar: ./net/forwarding/router_bridge_vlan_upper.sh: time stamp 2024-11-05 07:29:13 is 24485955.246822449 s in the future
 1289 10:54:30.939767  tar: ./net/forwarding/mirror_gre_bridge_1q.sh: time stamp 2024-11-05 07:29:13 is 24485955.105853907 s in the future
 1290 10:54:31.075612  tar: ./net/forwarding/router_broadcast.sh: time stamp 2024-11-05 07:29:13 is 24485954.970011907 s in the future
 1291 10:54:31.199826  tar: ./net/forwarding/mirror_gre_vlan.sh: time stamp 2024-11-05 07:29:13 is 24485954.846390324 s in the future
 1292 10:54:31.349473  tar: ./net/forwarding/vxlan_bridge_1q_ipv6.sh: time stamp 2024-11-05 07:29:13 is 24485954.696129574 s in the future
 1293 10:54:31.497603  tar: ./net/forwarding/router_nh.sh: time stamp 2024-11-05 07:29:13 is 24485954.547048366 s in the future
 1294 10:54:31.647044  tar: ./net/forwarding/tc_chains.sh: time stamp 2024-11-05 07:29:13 is 24485954.398050157 s in the future
 1295 10:54:31.780912  tar: ./net/forwarding/router_bridge_pvid_vlan_upper.sh: time stamp 2024-11-05 07:29:13 is 24485954.266517907 s in the future
 1296 10:54:31.928047  tar: ./net/forwarding/bridge_igmp.sh: time stamp 2024-11-05 07:29:13 is 24485954.116690199 s in the future
 1297 10:54:32.067860  tar: ./net/forwarding/ip6gre_lib.sh: time stamp 2024-11-05 07:29:13 is 24485953.977260366 s in the future
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 1299 10:54:32.353898  tar: ./net/forwarding/devlink_lib.sh: time stamp 2024-11-05 07:29:13 is 24485953.690894532 s in the future
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 2059 10:56:22.772168  tar: ./memfd/memfd_test: time stamp 2024-11-08 10:35:55 is 24756245.265863727 s in the future
 2060 10:56:22.900009  tar: ./memfd/config: time stamp 2024-11-05 07:29:13 is 24485843.137448394 s in the future
 2061 10:56:23.031032  tar: ./memfd/run_fuse_test.sh: time stamp 2024-11-05 07:29:13 is 24485843.007168019 s in the future
 2062 10:56:23.172095  tar: ./memfd/fuse_test: time stamp 2024-11-08 10:35:55 is 24756244.865314227 s in the future
 2063 10:56:23.299950  tar: ./memfd/fuse_mnt: time stamp 2024-11-08 10:35:55 is 24756244.737023602 s in the future
 2064 10:56:23.435537  tar: ./memfd/run_hugetlbfs_test.sh: time stamp 2024-11-05 07:29:13 is 24485842.603311019 s in the future
 2065 10:56:23.490604  tar: ./memfd: time stamp 2024-11-08 10:37:13 is 24756322.545366227 s in the future
 2066 10:56:23.655688  tar: ./gpio/gpio-chip-info: time stamp 2024-11-08 10:35:36 is 24756225.381644936 s in the future
 2067 10:56:23.806968  tar: ./gpio/gpio-mockup-sysfs.sh: time stamp 2024-11-05 07:29:13 is 24485842.231619352 s in the future
 2068 10:56:23.927533  tar: ./gpio/config: time stamp 2024-11-05 07:29:13 is 24485842.110140686 s in the future
 2069 10:56:24.164245  tar: ./gpio/gpio-line-name: time stamp 2024-11-08 10:35:36 is 24756224.873700519 s in the future
 2070 10:56:24.306155  tar: ./gpio/gpio-sim.sh: time stamp 2024-11-05 07:29:13 is 24485841.731282102 s in the future
 2071 10:56:24.432190  tar: ./gpio/gpio-mockup.sh: time stamp 2024-11-05 07:29:13 is 24485841.606100519 s in the future
 2072 10:56:24.581660  tar: ./gpio/gpio-mockup-cdev: time stamp 2024-11-08 10:35:36 is 24756224.456061894 s in the future
 2073 10:56:24.634581  tar: ./gpio: time stamp 2024-11-08 10:37:11 is 24756319.402666769 s in the future
 2074 10:56:24.780601  tar: ./kselftest-list.txt: time stamp 2024-11-08 10:37:22 is 24756330.256220685 s in the future
 2075 10:56:25.458494  tar: ./openat2/rename_attack_test: time stamp 2024-11-08 10:36:35 is 24756282.580941102 s in the future
 2076 10:56:25.839791  tar: ./openat2/openat2_test: time stamp 2024-11-08 10:36:32 is 24756279.197398935 s in the future
 2077 10:56:26.202249  tar: ./openat2/resolve_test: time stamp 2024-11-08 10:36:35 is 24756281.835739935 s in the future
 2078 10:56:26.263648  tar: ./openat2: time stamp 2024-11-08 10:37:17 is 24756323.773018227 s in the future
 2079 10:56:26.431668  tar: ./pstore/pstore_tests: time stamp 2024-11-05 07:29:13 is 24485839.605675019 s in the future
 2080 10:56:26.557601  tar: ./pstore/config: time stamp 2024-11-05 07:29:13 is 24485839.480394727 s in the future
 2081 10:56:26.668667  tar: ./pstore/pstore_crash_test: time stamp 2024-11-05 07:29:13 is 24485839.368580519 s in the future
 2082 10:56:26.808427  tar: ./pstore/pstore_post_reboot_tests: time stamp 2024-11-05 07:29:13 is 24485839.230181894 s in the future
 2083 10:56:26.939541  tar: ./pstore/common_tests: time stamp 2024-11-05 07:29:13 is 24485839.09702106 s in the future
 2084 10:56:27.009499  tar: ./pstore: time stamp 2024-11-08 10:37:17 is 24756323.02666281 s in the future
 2085 10:56:27.167409  tar: ./signal/mangle_uc_sigmask: time stamp 2024-11-08 10:36:44 is 24756289.871261935 s in the future
 2086 10:56:27.331371  tar: ./signal/sas: time stamp 2024-11-08 10:36:44 is 24756289.705629644 s in the future
 2087 10:56:27.398131  tar: ./signal: time stamp 2024-11-08 10:37:18 is 24756323.638540227 s in the future
 2088 10:56:27.559089  tar: ./vDSO/vdso_test_gettimeofday: time stamp 2024-11-08 10:36:50 is 24756295.479389977 s in the future
 2089 10:56:27.682929  tar: ./vDSO/vdso_test_getcpu: time stamp 2024-11-08 10:36:50 is 24756295.354063685 s in the future
 2090 10:56:27.812071  tar: ./vDSO/vdso_test_clock_getres: time stamp 2024-11-08 10:36:51 is 24756296.225874727 s in the future
 2091 10:56:27.950772  tar: ./vDSO/vdso_test_correctness: time stamp 2024-11-08 10:36:51 is 24756296.087366018 s in the future
 2092 10:56:28.077635  tar: ./vDSO/vdso_test_abi: time stamp 2024-11-08 10:36:51 is 24756295.959013685 s in the future
 2093 10:56:28.213181  tar: ./vDSO/vdso_test_getrandom: time stamp 2024-11-08 10:36:51 is 24756295.825769977 s in the future
 2094 10:56:28.350617  tar: ./vDSO/vdso_test_chacha: time stamp 2024-11-08 10:36:51 is 24756295.686776768 s in the future
 2095 10:56:28.401817  tar: ./vDSO: time stamp 2024-11-08 10:37:20 is 24756324.633656352 s in the future
 2096 10:56:28.576060  tar: ./mqueue/mq_open_tests: time stamp 2024-11-08 10:35:58 is 24756242.461705685 s in the future
 2097 10:56:28.726379  tar: ./mqueue/mq_perf_tests: time stamp 2024-11-08 10:35:58 is 24756242.311764602 s in the future
 2098 10:56:28.795372  tar: ./mqueue: time stamp 2024-11-08 10:37:13 is 24756317.24154381 s in the future
 2099 10:56:28.986865  tar: ./sync/sync_test: time stamp 2024-11-08 10:36:45 is 24756289.049801685 s in the future
 2100 10:56:29.116968  tar: ./sync/config: time stamp 2024-11-05 07:29:13 is 24485836.920040393 s in the future
 2101 10:56:29.258769  tar: ./sync: time stamp 2024-11-08 10:37:18 is 24756321.777881185 s in the future
 2102 10:56:29.419368  tar: ./ipc/msgque: time stamp 2024-11-08 10:35:40 is 24756223.616412935 s in the future
 2103 10:56:29.550582  tar: ./ipc/config: time stamp 2024-11-05 07:29:13 is 24485836.48600881 s in the future
 2104 10:56:29.633118  tar: ./ipc: time stamp 2024-11-08 10:37:11 is 24756314.403223685 s in the future
 2105 10:56:30.033465  tar: ./tdx/tdx_guest_test: time stamp 2024-11-08 10:36:45 is 24756288.002803602 s in the future
 2106 10:56:30.159269  tar: ./tdx/config: time stamp 2024-11-05 07:29:13 is 24485835.877457185 s in the future
 2107 10:56:30.211334  tar: ./tdx: time stamp 2024-11-08 10:37:19 is 24756321.82409706 s in the future
 2108 10:56:30.350947  tar: ./tpm2/test_async.sh: time stamp 2024-11-05 07:29:13 is 24485835.686091102 s in the future
 2109 10:56:30.491574  tar: ./tpm2/tpm2.py: time stamp 2024-11-05 07:29:13 is 24485835.544462351 s in the future
 2110 10:56:30.635493  tar: ./tpm2/tpm2_tests.py: time stamp 2024-11-05 07:29:13 is 24485835.402471893 s in the future
 2111 10:56:30.767710  tar: ./tpm2/test_smoke.sh: time stamp 2024-11-05 07:29:13 is 24485835.268691685 s in the future
 2112 10:56:30.892467  tar: ./tpm2/settings: time stamp 2024-11-05 07:29:13 is 24485835.143749601 s in the future
 2113 10:56:31.018581  tar: ./tpm2/test_space.sh: time stamp 2024-11-05 07:29:13 is 24485835.018907601 s in the future
 2114 10:56:31.084382  tar: ./tpm2: time stamp 2024-11-08 10:37:19 is 24756320.952134726 s in the future
 2115 10:56:31.235499  tar: ./ptrace/vmaccess: time stamp 2024-11-08 10:36:32 is 24756273.801411685 s in the future
 2116 10:56:31.363466  tar: ./ptrace/get_set_sud: time stamp 2024-11-08 10:36:32 is 24756273.672989685 s in the future
 2117 10:56:31.510680  tar: ./ptrace/peeksiginfo: time stamp 2024-11-08 10:36:32 is 24756273.526436643 s in the future
 2118 10:56:31.669438  tar: ./ptrace/get_syscall_info: time stamp 2024-11-08 10:36:31 is 24756272.368365768 s in the future
 2119 10:56:31.725665  tar: ./ptrace: time stamp 2024-11-08 10:37:17 is 24756318.309811851 s in the future
 2120 10:56:31.879231  tar: ./syscall_user_dispatch/sud_benchmark: time stamp 2024-11-08 10:36:45 is 24756286.159228851 s in the future
 2121 10:56:32.026603  tar: ./syscall_user_dispatch/config: time stamp 2024-11-05 07:29:13 is 24485834.01235681 s in the future
 2122 10:56:32.187422  tar: ./syscall_user_dispatch/sud_test: time stamp 2024-11-08 10:36:45 is 24756285.85105331 s in the future
 2123 10:56:32.260577  tar: ./syscall_user_dispatch: time stamp 2024-11-08 10:37:18 is 24756318.776220976 s in the future
 2124 10:56:32.478399  tar: ./resctrl/resctrl_tests: time stamp 2024-11-08 10:36:38 is 24756278.559105018 s in the future
 2125 10:56:32.592897  tar: ./resctrl/config: time stamp 2024-11-05 07:29:13 is 24485833.442559268 s in the future
 2126 10:56:32.718311  tar: ./resctrl/settings: time stamp 2024-11-05 07:29:13 is 24485833.317760476 s in the future
 2127 10:56:32.784457  tar: ./resctrl: time stamp 2024-11-08 10:37:17 is 24756317.250681685 s in the future
 2128 10:56:32.926119  tar: ./proc/setns-sysvipc: time stamp 2024-11-08 10:36:31 is 24756271.11151531 s in the future
 2129 10:56:33.064632  tar: ./proc/read: time stamp 2024-11-08 10:36:31 is 24756270.971581685 s in the future
 2130 10:56:33.202665  tar: ./proc/proc-subset-pid: time stamp 2024-11-08 10:36:30 is 24756269.833349851 s in the future
 2131 10:56:33.345915  tar: ./proc/proc-loadavg-001: time stamp 2024-11-08 10:36:30 is 24756269.691379684 s in the future
 2132 10:56:33.479876  tar: ./proc/proc-self-map-files-002: time stamp 2024-11-08 10:36:30 is 24756269.557851226 s in the future
 2133 10:56:33.618638  tar: ./proc/proc-empty-vm: time stamp 2024-11-08 10:36:30 is 24756269.419245101 s in the future
 2134 10:56:33.750825  tar: ./proc/proc-tid0: time stamp 2024-11-08 10:36:30 is 24756269.285853976 s in the future
 2135 10:56:33.895574  tar: ./proc/proc-pid-vm: time stamp 2024-11-08 10:36:30 is 24756269.140942559 s in the future
 2136 10:56:34.030055  tar: ./proc/proc-self-isnt-kthread: time stamp 2024-11-08 10:36:30 is 24756269.007424268 s in the future
 2137 10:56:34.160064  tar: ./proc/proc-2-is-kthread: time stamp 2024-11-08 10:36:30 is 24756268.877135851 s in the future
 2138 10:56:34.342944  tar: ./proc/proc-uptime-001: time stamp 2024-11-08 10:36:30 is 24756268.693826309 s in the future
 2139 10:56:34.479575  tar: ./proc/proc-uptime-002: time stamp 2024-11-08 10:36:31 is 24756269.557148643 s in the future
 2140 10:56:34.620584  tar: ./proc/proc-self-syscall: time stamp 2024-11-08 10:36:30 is 24756268.415332434 s in the future
 2141 10:56:34.730613  tar: ./proc/proc-multiple-procfs: time stamp 2024-11-08 10:36:31 is 24756269.306888726 s in the future
 2142 10:56:34.859625  tar: ./proc/config: time stamp 2024-11-05 07:29:13 is 24485831.176597351 s in the future
 2143 10:56:34.996202  tar: ./proc/thread-self: time stamp 2024-11-08 10:36:31 is 24756269.040024893 s in the future
 2144 10:56:35.121980  tar: ./proc/setns-dcache: time stamp 2024-11-08 10:36:31 is 24756268.915009851 s in the future
 2145 10:56:35.247968  tar: ./proc/proc-self-map-files-001: time stamp 2024-11-08 10:36:30 is 24756267.789791101 s in the future
 2146 10:56:35.377573  tar: ./proc/proc-self-wchan: time stamp 2024-11-08 10:36:30 is 24756267.659327559 s in the future
 2147 10:56:35.523332  tar: ./proc/proc-fsconfig-hidepid: time stamp 2024-11-08 10:36:31 is 24756268.514547393 s in the future
 2148 10:56:35.648373  tar: ./proc/fd-002-posix-eq: time stamp 2024-11-08 10:36:29 is 24756266.389477476 s in the future
 2149 10:56:35.794442  tar: ./proc/fd-001-lookup: time stamp 2024-11-08 10:36:29 is 24756266.241938976 s in the future
 2150 10:56:36.057813  tar: ./proc/fd-003-kthread: time stamp 2024-11-08 10:36:29 is 24756265.977550392 s in the future
 2151 10:56:36.189566  tar: ./proc/self: time stamp 2024-11-08 10:36:31 is 24756267.847260142 s in the future
 2152 10:56:36.243633  tar: ./proc: time stamp 2024-11-08 10:37:16 is 24756312.792012142 s in the future
 2153 10:56:36.447944  tar: ./core/close_range_test: time stamp 2024-11-08 10:34:23 is 24756139.589423434 s in the future
 2154 10:56:36.622432  tar: ./core/unshare_test: time stamp 2024-11-08 10:34:23 is 24756139.414097017 s in the future
 2155 10:56:36.679493  tar: ./core: time stamp 2024-11-08 10:37:07 is 24756303.355607892 s in the future
 2156 10:56:36.806411  tar: ./run_kselftest.sh: time stamp 2024-11-08 10:37:06 is 24756302.230258226 s in the future
 2157 10:56:37.080205  tar: ./futex/functional/futex_wait: time stamp 2024-11-08 10:35:35 is 24756210.957952642 s in the future
 2158 10:56:37.198919  tar: ./futex/functional/run.sh: time stamp 2024-11-05 07:29:13 is 24485828.838385517 s in the future
 2159 10:56:37.346306  tar: ./futex/functional/futex_wait_private_mapped_file: time stamp 2024-11-08 10:35:35 is 24756210.692917226 s in the future
 2160 10:56:37.512897  tar: ./futex/functional/futex_wait_wouldblock: time stamp 2024-11-08 10:35:34 is 24756209.526205059 s in the future
 2161 10:56:37.714294  tar: ./futex/functional/futex_wait_timeout: time stamp 2024-11-08 10:35:34 is 24756209.324053267 s in the future
 2162 10:56:37.927105  tar: ./futex/functional/futex_wait_uninitialized_heap: time stamp 2024-11-08 10:35:35 is 24756210.112620642 s in the future
 2163 10:56:38.051192  tar: ./futex/functional/futex_requeue: time stamp 2024-11-08 10:35:35 is 24756209.987231434 s in the future
 2164 10:56:38.273661  tar: ./futex/functional/futex_requeue_pi_signal_restart: time stamp 2024-11-08 10:35:34 is 24756208.765354267 s in the future
 2165 10:56:38.483288  tar: ./futex/functional/futex_waitv: time stamp 2024-11-08 10:35:35 is 24756209.554311517 s in the future
 2166 10:56:38.639499  tar: ./futex/functional/futex_requeue_pi_mismatched_ops: time stamp 2024-11-08 10:35:35 is 24756209.400272517 s in the future
 2167 10:56:38.783517  tar: ./futex/functional/futex_requeue_pi: time stamp 2024-11-08 10:35:34 is 24756208.2537456 s in the future
 2168 10:56:38.850349  tar: ./futex/functional: time stamp 2024-11-08 10:37:11 is 24756305.186929517 s in the future
 2169 10:56:39.125094  tar: ./futex/run.sh: time stamp 2024-11-08 10:37:11 is 24756304.911467517 s in the future
 2170 10:56:39.190939  tar: ./futex: time stamp 2024-11-08 10:37:11 is 24756304.844645934 s in the future
 2171 10:56:39.243916  tar: .: time stamp 2024-11-08 10:37:22 is 24756315.791284892 s in the future
 2172 10:56:39.540393  skiplist:
 2173 10:56:39.540772  ========================================
 2174 10:56:39.547103  ========================================
 2175 10:56:39.852681  dt:test_unprobed_devices.sh
 2176 10:56:39.946627  ============== Tests to run ===============
 2177 10:56:39.959077  dt:test_unprobed_devices.sh
 2178 10:56:39.962299  ===========End Tests to run ===============
 2179 10:56:39.993385  shardfile-dt pass
 2180 10:56:40.319303  <12>[  226.710877] kselftest: Running tests in dt
 2181 10:56:40.351408  TAP version 13
 2182 10:56:40.373996  1..1
 2183 10:56:40.428893  # timeout set to 45
 2184 10:56:40.429275  # selftests: dt: test_unprobed_devices.sh
 2185 10:56:41.231436  # TAP version 13
 2186 10:57:06.683332  # 1..257
 2187 10:57:06.851416  # ok 1 / # SKIP
 2188 10:57:06.874092  # ok 2 /clk_mcasp0
 2189 10:57:06.946239  # ok 3 /clk_mcasp0_fixed # SKIP
 2190 10:57:07.021827  # ok 4 /cpus/cpu@0 # SKIP
 2191 10:57:07.096684  # ok 5 /cpus/idle-states/mpu_gate # SKIP
 2192 10:57:07.123112  # ok 6 /fixedregulator0
 2193 10:57:07.142500  # ok 7 /leds
 2194 10:57:07.159865  # ok 8 /ocp
 2195 10:57:07.184757  # ok 9 /ocp/interconnect@44c00000
 2196 10:57:07.212990  # ok 10 /ocp/interconnect@44c00000/segment@0
 2197 10:57:07.235096  # ok 11 /ocp/interconnect@44c00000/segment@100000
 2198 10:57:07.256468  # ok 12 /ocp/interconnect@44c00000/segment@100000/target-module@0
 2199 10:57:07.333761  # not ok 13 /ocp/interconnect@44c00000/segment@100000/target-module@0/cpu@0
 2200 10:57:07.350769  # ok 14 /ocp/interconnect@44c00000/segment@200000
 2201 10:57:07.375345  # ok 15 /ocp/interconnect@44c00000/segment@200000/target-module@0
 2202 10:57:07.485362  # not ok 16 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0
 2203 10:57:07.560871  # ok 17 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0 # SKIP
 2204 10:57:07.634260  # ok 18 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@0 # SKIP
 2205 10:57:07.708767  # ok 19 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@120 # SKIP
 2206 10:57:07.784065  # ok 20 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@14c # SKIP
 2207 10:57:07.857692  # ok 21 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@18 # SKIP
 2208 10:57:07.937082  # ok 22 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@1c # SKIP
 2209 10:57:08.009269  # ok 23 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@24 # SKIP
 2210 10:57:08.081782  # ok 24 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@38 # SKIP
 2211 10:57:08.157358  # ok 25 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@e8 # SKIP
 2212 10:57:08.230590  # ok 26 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400 # SKIP
 2213 10:57:08.303897  # ok 27 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@0 # SKIP
 2214 10:57:08.377380  # ok 28 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@14 # SKIP
 2215 10:57:08.454320  # ok 29 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@b0 # SKIP
 2216 10:57:08.524177  # ok 30 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600 # SKIP
 2217 10:57:08.599785  # ok 31 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600/clock@0 # SKIP
 2218 10:57:08.673221  # ok 32 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800 # SKIP
 2219 10:57:08.748700  # ok 33 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800/clock@0 # SKIP
 2220 10:57:08.822842  # ok 34 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900 # SKIP
 2221 10:57:08.897374  # ok 35 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900/clock@0 # SKIP
 2222 10:57:08.972003  # ok 36 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00 # SKIP
 2223 10:57:09.045599  # ok 37 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00/clock@0 # SKIP
 2224 10:57:09.120451  # ok 38 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-24mhz # SKIP
 2225 10:57:09.195256  # ok 39 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-32768 # SKIP
 2226 10:57:09.268833  # ok 40 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-rc32k # SKIP
 2227 10:57:09.343602  # ok 41 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clkdiv32k # SKIP
 2228 10:57:09.418519  # ok 42 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-125mhz-gclk # SKIP
 2229 10:57:09.498572  # ok 43 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-cpts-rft@520 # SKIP
 2230 10:57:09.567868  # ok 44 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4-div2 # SKIP
 2231 10:57:09.646454  # ok 45 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4@480 # SKIP
 2232 10:57:09.717808  # ok 46 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m5@484 # SKIP
 2233 10:57:09.795099  # ok 47 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m6@4d8 # SKIP
 2234 10:57:09.865351  # ok 48 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-x2 # SKIP
 2235 10:57:09.940151  # ok 49 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2-div2 # SKIP
 2236 10:57:10.015905  # ok 50 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2@4a0 # SKIP
 2237 10:57:10.090686  # ok 51 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-disp-m2@4a4 # SKIP
 2238 10:57:10.165046  # ok 52 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-mpu-m2@4a8 # SKIP
 2239 10:57:10.239926  # ok 53 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4 # SKIP
 2240 10:57:10.315541  # ok 54 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4-wkupdm # SKIP
 2241 10:57:10.389103  # ok 55 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2@4ac # SKIP
 2242 10:57:10.468269  # ok 56 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-gpio0-dbclk-mux@53c # SKIP
 2243 10:57:10.543224  # ok 57 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-ieee5000-fck-1@e4 # SKIP
 2244 10:57:10.614381  # ok 58 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3-gclk # SKIP
 2245 10:57:10.688044  # ok 59 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3s-gclk # SKIP
 2246 10:57:10.766241  # ok 60 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4-rtc-gclk # SKIP
 2247 10:57:10.837810  # ok 61 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4fw-gclk # SKIP
 2248 10:57:10.916044  # ok 62 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4hs-gclk # SKIP
 2249 10:57:10.986109  # ok 63 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4ls-gclk # SKIP
 2250 10:57:11.060958  # ok 64 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-lcd-gclk@534 # SKIP
 2251 10:57:11.136755  # ok 65 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmc # SKIP
 2252 10:57:11.211605  # ok 66 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmu-fck-1@914 # SKIP
 2253 10:57:11.286305  # ok 67 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-pruss-ocp-gclk@530 # SKIP
 2254 10:57:11.356776  # ok 68 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-sysclk-div # SKIP
 2255 10:57:11.430488  # ok 69 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-tclkin # SKIP
 2256 10:57:11.505200  # ok 70 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer1-fck@528 # SKIP
 2257 10:57:11.580238  # ok 71 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer2-fck@508 # SKIP
 2258 10:57:11.659089  # ok 72 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer3-fck@50c # SKIP
 2259 10:57:11.731788  # ok 73 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer4-fck@510 # SKIP
 2260 10:57:11.807492  # ok 74 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer5-fck@518 # SKIP
 2261 10:57:11.923263  # ok 75 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer6-fck@51c # SKIP
 2262 10:57:11.958753  # ok 76 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer7-fck@504 # SKIP
 2263 10:57:12.031472  # ok 77 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-usbotg-fck-8@47c # SKIP
 2264 10:57:12.102911  # ok 78 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-19200000 # SKIP
 2265 10:57:12.176513  # ok 79 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-24000000 # SKIP
 2266 10:57:12.251436  # ok 80 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-25000000 # SKIP
 2267 10:57:12.326235  # ok 81 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-26000000 # SKIP
 2268 10:57:12.400000  # ok 82 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-wdt1-fck@538 # SKIP
 2269 10:57:12.478790  # ok 83 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@488 # SKIP
 2270 10:57:12.547986  # ok 84 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@48c # SKIP
 2271 10:57:12.621676  # ok 85 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@490 # SKIP
 2272 10:57:12.697351  # ok 86 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@494 # SKIP
 2273 10:57:12.778016  # ok 87 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@498 # SKIP
 2274 10:57:12.845278  # ok 88 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c # SKIP
 2275 10:57:12.921228  # ok 89 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fck-div@0 # SKIP
 2276 10:57:12.997267  # ok 90 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fclk-clksel@1 # SKIP
 2277 10:57:13.068743  # ok 91 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700 # SKIP
 2278 10:57:13.145689  # ok 92 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2-div@3 # SKIP
 2279 10:57:13.218480  # ok 93 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2@7 # SKIP
 2280 10:57:13.294718  # ok 94 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-sysclkout-pre@0 # SKIP
 2281 10:57:13.318628  # ok 95 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1000
 2282 10:57:13.346112  # ok 96 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1100
 2283 10:57:13.370112  # ok 97 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1200
 2284 10:57:13.391513  # ok 98 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@c00
 2285 10:57:13.416337  # ok 99 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@d00
 2286 10:57:13.441205  # ok 100 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@e00
 2287 10:57:13.465017  # ok 101 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@f00
 2288 10:57:13.487492  # ok 102 /ocp/interconnect@44c00000/segment@200000/target-module@10000
 2289 10:57:13.596607  # not ok 103 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0
 2290 10:57:13.627074  # ok 104 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/control@620
 2291 10:57:13.650940  # ok 105 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/dma-router@f90
 2292 10:57:13.671414  # ok 106 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800
 2293 10:57:13.785462  # not ok 107 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0
 2294 10:57:13.858276  # ok 108 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-adc-tsc-fck # SKIP
 2295 10:57:13.935515  # ok 109 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-aes0-fck # SKIP
 2296 10:57:14.008277  # ok 110 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan0-fck # SKIP
 2297 10:57:14.088807  # ok 111 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan1-fck # SKIP
 2298 10:57:14.162983  # ok 112 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp0-fck # SKIP
 2299 10:57:14.235965  # ok 113 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp1-fck # SKIP
 2300 10:57:14.308861  # ok 114 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-rng-fck # SKIP
 2301 10:57:14.388238  # ok 115 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sha0-fck # SKIP
 2302 10:57:14.463357  # ok 116 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex0-fck # SKIP
 2303 10:57:14.535155  # ok 117 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex1-fck # SKIP
 2304 10:57:14.609228  # ok 118 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sys-clkin-22@40 # SKIP
 2305 10:57:14.682045  # ok 119 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664 # SKIP
 2306 10:57:14.759286  # ok 120 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm0-tbclk@0 # SKIP
 2307 10:57:14.833433  # ok 121 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm1-tbclk@1 # SKIP
 2308 10:57:14.907659  # ok 122 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm2-tbclk@2 # SKIP
 2309 10:57:14.934715  # ok 123 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/phy-gmii-sel
 2310 10:57:15.005217  # not ok 124 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/wkup_m3_ipc@1324
 2311 10:57:15.075318  # not ok 125 /ocp/interconnect@44c00000/segment@200000/target-module@31000
 2312 10:57:15.149898  # ok 126 /ocp/interconnect@44c00000/segment@200000/target-module@31000/timer@0 # SKIP
 2313 10:57:15.173452  # ok 127 /ocp/interconnect@44c00000/segment@200000/target-module@35000
 2314 10:57:15.249605  # not ok 128 /ocp/interconnect@44c00000/segment@200000/target-module@35000/wdt@0
 2315 10:57:15.274330  # ok 129 /ocp/interconnect@44c00000/segment@200000/target-module@3e000
 2316 10:57:15.348665  # not ok 130 /ocp/interconnect@44c00000/segment@200000/target-module@3e000/rtc@0
 2317 10:57:15.369270  # ok 131 /ocp/interconnect@44c00000/segment@200000/target-module@7000
 2318 10:57:15.391753  # ok 132 /ocp/interconnect@44c00000/segment@200000/target-module@7000/gpio@0
 2319 10:57:15.418554  # ok 133 /ocp/interconnect@44c00000/segment@200000/target-module@9000
 2320 10:57:15.440234  # ok 134 /ocp/interconnect@44c00000/segment@200000/target-module@9000/serial@0
 2321 10:57:15.467233  # ok 135 /ocp/interconnect@44c00000/segment@200000/target-module@b000
 2322 10:57:15.488820  # ok 136 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0
 2323 10:57:15.513657  # ok 137 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/eeprom@50
 2324 10:57:15.590494  # ok 138 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/eeprom@50/nvmem-layout # SKIP
 2325 10:57:15.613249  # ok 139 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
 2326 10:57:15.640202  # ok 140 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24
 2327 10:57:15.711401  # not ok 141 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/charger
 2328 10:57:15.785792  # not ok 142 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/pwrbutton
 2329 10:57:15.807353  # ok 143 /ocp/interconnect@44c00000/segment@200000/target-module@d000
 2330 10:57:15.911630  # not ok 144 /ocp/interconnect@47c00000
 2331 10:57:15.984502  # not ok 145 /ocp/interconnect@47c00000/segment@0
 2332 10:57:16.010789  # ok 146 /ocp/interconnect@48000000
 2333 10:57:16.034329  # ok 147 /ocp/interconnect@48000000/segment@0
 2334 10:57:16.055271  # ok 148 /ocp/interconnect@48000000/segment@0/target-module@22000
 2335 10:57:16.084825  # ok 149 /ocp/interconnect@48000000/segment@0/target-module@24000
 2336 10:57:16.107656  # ok 150 /ocp/interconnect@48000000/segment@0/target-module@2a000
 2337 10:57:16.126398  # ok 151 /ocp/interconnect@48000000/segment@0/target-module@30000
 2338 10:57:16.154856  # ok 152 /ocp/interconnect@48000000/segment@0/target-module@38000
 2339 10:57:16.178369  # ok 153 /ocp/interconnect@48000000/segment@0/target-module@38000/mcasp@0
 2340 10:57:16.205282  # ok 154 /ocp/interconnect@48000000/segment@0/target-module@3c000
 2341 10:57:16.277313  # not ok 155 /ocp/interconnect@48000000/segment@0/target-module@40000
 2342 10:57:16.351756  # ok 156 /ocp/interconnect@48000000/segment@0/target-module@40000/timer@0 # SKIP
 2343 10:57:16.376477  # ok 157 /ocp/interconnect@48000000/segment@0/target-module@42000
 2344 10:57:16.398952  # ok 158 /ocp/interconnect@48000000/segment@0/target-module@42000/timer@0
 2345 10:57:16.424320  # ok 159 /ocp/interconnect@48000000/segment@0/target-module@44000
 2346 10:57:16.448924  # ok 160 /ocp/interconnect@48000000/segment@0/target-module@44000/timer@0
 2347 10:57:16.471248  # ok 161 /ocp/interconnect@48000000/segment@0/target-module@46000
 2348 10:57:16.492080  # ok 162 /ocp/interconnect@48000000/segment@0/target-module@46000/timer@0
 2349 10:57:16.517730  # ok 163 /ocp/interconnect@48000000/segment@0/target-module@48000
 2350 10:57:16.541352  # ok 164 /ocp/interconnect@48000000/segment@0/target-module@48000/timer@0
 2351 10:57:16.563634  # ok 165 /ocp/interconnect@48000000/segment@0/target-module@4a000
 2352 10:57:16.592912  # ok 166 /ocp/interconnect@48000000/segment@0/target-module@4a000/timer@0
 2353 10:57:16.612851  # ok 167 /ocp/interconnect@48000000/segment@0/target-module@4c000
 2354 10:57:16.636271  # ok 168 /ocp/interconnect@48000000/segment@0/target-module@4c000/gpio@0
 2355 10:57:16.659632  # ok 169 /ocp/interconnect@48000000/segment@0/target-module@60000
 2356 10:57:16.685176  # ok 170 /ocp/interconnect@48000000/segment@0/target-module@60000/mmc@0
 2357 10:57:16.707777  # ok 171 /ocp/interconnect@48000000/segment@0/target-module@c8000
 2358 10:57:16.736742  # ok 172 /ocp/interconnect@48000000/segment@0/target-module@c8000/mailbox@0
 2359 10:57:16.758488  # ok 173 /ocp/interconnect@48000000/segment@0/target-module@ca000
 2360 10:57:16.780975  # ok 174 /ocp/interconnect@48000000/segment@0/target-module@ca000/spinlock@0
 2361 10:57:16.805366  # ok 175 /ocp/interconnect@48000000/segment@100000
 2362 10:57:16.829229  # ok 176 /ocp/interconnect@48000000/segment@100000/target-module@9c000
 2363 10:57:16.857193  # ok 177 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0
 2364 10:57:16.930652  # not ok 178 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/eeprom@54
 2365 10:57:17.009590  # ok 179 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/eeprom@54/nvmem-layout # SKIP
 2366 10:57:17.080040  # not ok 180 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/eeprom@55
 2367 10:57:17.151460  # ok 181 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/eeprom@55/nvmem-layout # SKIP
 2368 10:57:17.229167  # not ok 182 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/eeprom@56
 2369 10:57:17.308205  # ok 183 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/eeprom@56/nvmem-layout # SKIP
 2370 10:57:17.380970  # not ok 184 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/eeprom@57
 2371 10:57:17.454149  # ok 185 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/eeprom@57/nvmem-layout # SKIP
 2372 10:57:17.474742  # ok 186 /ocp/interconnect@48000000/segment@100000/target-module@a0000
 2373 10:57:17.501841  # ok 187 /ocp/interconnect@48000000/segment@100000/target-module@a6000
 2374 10:57:17.523365  # ok 188 /ocp/interconnect@48000000/segment@100000/target-module@a8000
 2375 10:57:17.548186  # ok 189 /ocp/interconnect@48000000/segment@100000/target-module@aa000
 2376 10:57:17.574342  # ok 190 /ocp/interconnect@48000000/segment@100000/target-module@ac000
 2377 10:57:17.599211  # ok 191 /ocp/interconnect@48000000/segment@100000/target-module@ac000/gpio@0
 2378 10:57:17.622115  # ok 192 /ocp/interconnect@48000000/segment@100000/target-module@ae000
 2379 10:57:17.644669  # ok 193 /ocp/interconnect@48000000/segment@100000/target-module@ae000/gpio@0
 2380 10:57:17.667293  # ok 194 /ocp/interconnect@48000000/segment@100000/target-module@cc000
 2381 10:57:17.695380  # ok 195 /ocp/interconnect@48000000/segment@100000/target-module@d0000
 2382 10:57:17.718927  # ok 196 /ocp/interconnect@48000000/segment@100000/target-module@d8000
 2383 10:57:17.740427  # ok 197 /ocp/interconnect@48000000/segment@100000/target-module@d8000/mmc@0
 2384 10:57:17.761690  # ok 198 /ocp/interconnect@48000000/segment@200000
 2385 10:57:17.787308  # ok 199 /ocp/interconnect@48000000/segment@200000/target-module@0
 2386 10:57:17.861383  # ok 200 /ocp/interconnect@48000000/segment@200000/target-module@0/mpu@0 # SKIP
 2387 10:57:17.881759  # ok 201 /ocp/interconnect@48000000/segment@300000
 2388 10:57:17.907279  # ok 202 /ocp/interconnect@48000000/segment@300000/target-module@0
 2389 10:57:17.930574  # ok 203 /ocp/interconnect@48000000/segment@300000/target-module@10000
 2390 10:57:17.958348  # ok 204 /ocp/interconnect@48000000/segment@300000/target-module@10000/rng@0
 2391 10:57:17.986496  # ok 205 /ocp/interconnect@48000000/segment@300000/target-module@2000
 2392 10:57:18.008066  # ok 206 /ocp/interconnect@48000000/segment@300000/target-module@4000
 2393 10:57:18.036040  # ok 207 /ocp/interconnect@48000000/segment@300000/target-module@e000
 2394 10:57:18.103724  # not ok 208 /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
 2395 10:57:18.123827  # ok 209 /ocp/interconnect@4a000000
 2396 10:57:18.151442  # ok 210 /ocp/interconnect@4a000000/segment@0
 2397 10:57:18.178299  # ok 211 /ocp/interconnect@4a000000/segment@0/target-module@100000
 2398 10:57:18.198686  # ok 212 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0
 2399 10:57:18.227710  # ok 213 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0/mdio@1000
 2400 10:57:18.247145  # ok 214 /ocp/interconnect@4a000000/segment@0/target-module@300000
 2401 10:57:18.319373  # not ok 215 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0
 2402 10:57:18.431821  # ok 216 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/cfg@26000 # SKIP
 2403 10:57:18.510764  # not ok 217 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/interrupt-controller@20000
 2404 10:57:18.614752  # ok 218 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/mii-rt@32000 # SKIP
 2405 10:57:18.687199  # not ok 219 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@34000
 2406 10:57:18.763931  # not ok 220 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@38000
 2407 10:57:18.865206  # not ok 221 /ocp/interconnect@4b140000
 2408 10:57:18.943404  # not ok 222 /ocp/interconnect@4b140000/segment@0
 2409 10:57:19.016335  # ok 223 /ocp/interrupt-controller@48200000 # SKIP
 2410 10:57:19.034280  # ok 224 /ocp/target-module@40300000
 2411 10:57:19.062971  # ok 225 /ocp/target-module@40300000/sram@0
 2412 10:57:19.138266  # ok 226 /ocp/target-module@40300000/sram@0/pm-code-sram@0 # SKIP
 2413 10:57:19.209313  # ok 227 /ocp/target-module@40300000/sram@0/pm-data-sram@1000 # SKIP
 2414 10:57:19.229274  # ok 228 /ocp/target-module@47400000
 2415 10:57:19.258034  # ok 229 /ocp/target-module@47400000/dma-controller@2000
 2416 10:57:19.281657  # ok 230 /ocp/target-module@47400000/usb-phy@1300
 2417 10:57:19.302771  # ok 231 /ocp/target-module@47400000/usb-phy@1b00
 2418 10:57:19.381074  # ok 232 /ocp/target-module@47400000/usb@1400
 2419 10:57:19.381452  # ok 233 /ocp/target-module@47400000/usb@1800
 2420 10:57:19.387883  # ok 234 /ocp/target-module@47810000
 2421 10:57:19.395922  # ok 235 /ocp/target-module@49000000
 2422 10:57:19.419121  # ok 236 /ocp/target-module@49000000/dma@0
 2423 10:57:19.442421  # ok 237 /ocp/target-module@49800000
 2424 10:57:19.465553  # ok 238 /ocp/target-module@49800000/dma@0
 2425 10:57:19.485508  # ok 239 /ocp/target-module@49900000
 2426 10:57:19.507221  # ok 240 /ocp/target-module@49900000/dma@0
 2427 10:57:19.533581  # ok 241 /ocp/target-module@49a00000
 2428 10:57:19.555914  # ok 242 /ocp/target-module@49a00000/dma@0
 2429 10:57:19.573710  # ok 243 /ocp/target-module@4c000000
 2430 10:57:19.645415  # not ok 244 /ocp/target-module@4c000000/emif@0
 2431 10:57:19.671481  # ok 245 /ocp/target-module@50000000
 2432 10:57:19.689100  # ok 246 /ocp/target-module@53100000
 2433 10:57:19.765210  # not ok 247 /ocp/target-module@53100000/sham@0
 2434 10:57:19.785411  # ok 248 /ocp/target-module@53500000
 2435 10:57:19.854011  # not ok 249 /ocp/target-module@53500000/aes@0
 2436 10:57:19.874906  # ok 250 /ocp/target-module@56000000
 2437 10:57:19.979376  # ok 251 /ocp/target-module@56000000/gpu@0 # SKIP
 2438 10:57:20.047598  # ok 252 /opp-table # SKIP
 2439 10:57:20.121284  # ok 253 /soc # SKIP
 2440 10:57:20.142022  # ok 254 /sound
 2441 10:57:20.160711  # ok 255 /target-module@4b000000
 2442 10:57:20.187035  # ok 256 /target-module@4b000000/target-module@140000
 2443 10:57:20.207199  # ok 257 /target-module@4b000000/target-module@140000/pmu@0
 2444 10:57:20.215461  # # Totals: pass:117 fail:27 xfail:0 xpass:0 skip:113 error:0
 2445 10:57:20.221699  not ok 1 selftests: dt: test_unprobed_devices.sh # exit=1
 2446 10:57:22.728859  dt_test_unprobed_devices_sh_ skip
 2447 10:57:22.734997  dt_test_unprobed_devices_sh_clk_mcasp0 pass
 2448 10:57:22.739884  dt_test_unprobed_devices_sh_clk_mcasp0_fixed skip
 2449 10:57:22.740274  dt_test_unprobed_devices_sh_cpus_cpu_0 skip
 2450 10:57:22.746013  dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate skip
 2451 10:57:22.752083  dt_test_unprobed_devices_sh_fixedregulator0 pass
 2452 10:57:22.756990  dt_test_unprobed_devices_sh_leds pass
 2453 10:57:22.757370  dt_test_unprobed_devices_sh_ocp pass
 2454 10:57:22.761830  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 pass
 2455 10:57:22.766952  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 pass
 2456 10:57:22.776894  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 pass
 2457 10:57:22.782784  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 pass
 2458 10:57:22.793958  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 fail
 2459 10:57:22.798967  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 pass
 2460 10:57:22.808712  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 pass
 2461 10:57:22.814894  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 fail
 2462 10:57:22.824521  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 skip
 2463 10:57:22.835747  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 skip
 2464 10:57:22.845668  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 skip
 2465 10:57:22.856945  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c skip
 2466 10:57:22.866602  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 skip
 2467 10:57:22.877760  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c skip
 2468 10:57:22.882857  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 skip
 2469 10:57:22.892600  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 skip
 2470 10:57:22.903921  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 skip
 2471 10:57:22.913900  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 skip
 2472 10:57:22.925029  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 skip
 2473 10:57:22.934897  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 skip
 2474 10:57:22.944919  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 skip
 2475 10:57:22.954986  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 skip
 2476 10:57:22.966119  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 skip
 2477 10:57:22.972154  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 skip
 2478 10:57:22.983186  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 skip
 2479 10:57:22.992905  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 skip
 2480 10:57:23.004103  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 skip
 2481 10:57:23.013955  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 skip
 2482 10:57:23.024102  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 skip
 2483 10:57:23.035177  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz skip
 2484 10:57:23.046425  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 skip
 2485 10:57:23.056182  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k skip
 2486 10:57:23.067601  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k skip
 2487 10:57:23.077194  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk skip
 2488 10:57:23.088334  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 skip
 2489 10:57:23.097955  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 skip
 2490 10:57:23.109106  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 skip
 2491 10:57:23.124063  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 skip
 2492 10:57:23.135225  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 skip
 2493 10:57:23.145033  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 skip
 2494 10:57:23.154764  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 skip
 2495 10:57:23.164515  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 skip
 2496 10:57:23.175464  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 skip
 2497 10:57:23.186665  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 skip
 2498 10:57:23.201285  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 skip
 2499 10:57:23.212351  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm skip
 2500 10:57:23.222221  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac skip
 2501 10:57:23.233102  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c skip
 2502 10:57:23.248966  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 skip
 2503 10:57:23.253852  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk skip
 2504 10:57:23.263780  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk skip
 2505 10:57:23.274705  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk skip
 2506 10:57:23.290653  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk skip
 2507 10:57:23.295590  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk skip
 2508 10:57:23.311605  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk skip
 2509 10:57:23.321199  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 skip
 2510 10:57:23.332294  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc skip
 2511 10:57:23.342055  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 skip
 2512 10:57:23.353114  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 skip
 2513 10:57:23.362754  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div skip
 2514 10:57:23.373966  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin skip
 2515 10:57:23.383655  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 skip
 2516 10:57:23.394796  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 skip
 2517 10:57:23.404412  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c skip
 2518 10:57:23.415606  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 skip
 2519 10:57:23.430268  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 skip
 2520 10:57:23.441235  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c skip
 2521 10:57:23.451026  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 skip
 2522 10:57:23.462021  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c skip
 2523 10:57:23.471941  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 skip
 2524 10:57:23.483010  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 skip
 2525 10:57:23.492769  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 skip
 2526 10:57:23.503640  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 skip
 2527 10:57:23.513635  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 skip
 2528 10:57:23.524651  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 skip
 2529 10:57:23.534440  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c skip
 2530 10:57:23.545425  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 skip
 2531 10:57:23.555221  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 skip
 2532 10:57:23.566212  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 skip
 2533 10:57:23.576067  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c skip
 2534 10:57:23.585866  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 skip
 2535 10:57:23.602994  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 skip
 2536 10:57:23.607976  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 skip
 2537 10:57:23.623701  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 skip
 2538 10:57:23.633383  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 skip
 2539 10:57:23.644545  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 skip
 2540 10:57:23.654223  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 pass
 2541 10:57:23.665164  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 pass
 2542 10:57:23.670022  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 pass
 2543 10:57:23.685934  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 pass
 2544 10:57:23.690829  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 pass
 2545 10:57:23.700824  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 pass
 2546 10:57:23.711797  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 pass
 2547 10:57:23.721573  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 pass
 2548 10:57:23.727672  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 fail
 2549 10:57:23.737266  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 pass
 2550 10:57:23.748475  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 pass
 2551 10:57:23.758185  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 pass
 2552 10:57:23.769230  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 fail
 2553 10:57:23.778958  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck skip
 2554 10:57:23.790058  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck skip
 2555 10:57:23.804895  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck skip
 2556 10:57:23.815943  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck skip
 2557 10:57:23.825645  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck skip
 2558 10:57:23.836663  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck skip
 2559 10:57:23.852450  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck skip
 2560 10:57:23.862209  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck skip
 2561 10:57:23.873293  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck skip
 2562 10:57:23.888063  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck skip
 2563 10:57:23.899014  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 skip
 2564 10:57:23.908640  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 skip
 2565 10:57:23.924666  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 skip
 2566 10:57:23.935719  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 skip
 2567 10:57:23.950602  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 skip
 2568 10:57:23.961434  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel pass
 2569 10:57:23.971260  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 fail
 2570 10:57:23.977306  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 fail
 2571 10:57:23.987080  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 skip
 2572 10:57:23.998346  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 pass
 2573 10:57:24.003061  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 fail
 2574 10:57:24.012897  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 pass
 2575 10:57:24.023886  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 fail
 2576 10:57:24.028580  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 pass
 2577 10:57:24.039709  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 pass
 2578 10:57:24.049514  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 pass
 2579 10:57:24.054508  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 pass
 2580 10:57:24.065510  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 pass
 2581 10:57:24.075339  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 pass
 2582 10:57:24.081359  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_eeprom_50 pass
 2583 10:57:24.095985  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_eeprom_50_nvmem-layout skip
 2584 10:57:24.102181  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 pass
 2585 10:57:24.111815  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 pass
 2586 10:57:24.122969  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger fail
 2587 10:57:24.132592  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton fail
 2588 10:57:24.143818  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 pass
 2589 10:57:24.148631  dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 fail
 2590 10:57:24.153571  dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 fail
 2591 10:57:24.158602  dt_test_unprobed_devices_sh_ocp_interconnect_48000000 pass
 2592 10:57:24.164814  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 pass
 2593 10:57:24.169557  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 pass
 2594 10:57:24.179393  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 pass
 2595 10:57:24.190390  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 pass
 2596 10:57:24.195098  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 pass
 2597 10:57:24.206287  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 pass
 2598 10:57:24.211138  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 pass
 2599 10:57:24.220971  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 pass
 2600 10:57:24.227082  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 fail
 2601 10:57:24.236620  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 skip
 2602 10:57:24.247826  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 pass
 2603 10:57:24.252710  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 pass
 2604 10:57:24.262662  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 pass
 2605 10:57:24.268707  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 pass
 2606 10:57:24.278541  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 pass
 2607 10:57:24.283583  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 pass
 2608 10:57:24.294651  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 pass
 2609 10:57:24.304444  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 pass
 2610 10:57:24.310583  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 pass
 2611 10:57:24.320298  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 pass
 2612 10:57:24.325152  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 pass
 2613 10:57:24.336385  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 pass
 2614 10:57:24.341191  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 pass
 2615 10:57:24.352218  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 pass
 2616 10:57:24.357284  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 pass
 2617 10:57:24.367011  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 pass
 2618 10:57:24.377998  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 pass
 2619 10:57:24.387971  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 pass
 2620 10:57:24.393986  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 pass
 2621 10:57:24.398934  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 pass
 2622 10:57:24.408648  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 pass
 2623 10:57:24.419649  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_54 fail
 2624 10:57:24.429466  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_54_nvmem-layout skip
 2625 10:57:24.440513  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_55 fail
 2626 10:57:24.450297  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_55_nvmem-layout skip
 2627 10:57:24.461455  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_56 fail
 2628 10:57:24.471337  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_56_nvmem-layout skip
 2629 10:57:24.477459  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_57 fail
 2630 10:57:24.492195  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_57_nvmem-layout skip
 2631 10:57:24.498254  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 pass
 2632 10:57:24.507903  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 pass
 2633 10:57:24.519083  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 pass
 2634 10:57:24.524007  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 pass
 2635 10:57:24.533628  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 pass
 2636 10:57:24.539915  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 pass
 2637 10:57:24.549577  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 pass
 2638 10:57:24.560768  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 pass
 2639 10:57:24.565633  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 pass
 2640 10:57:24.575457  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 pass
 2641 10:57:24.581562  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 pass
 2642 10:57:24.591177  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 pass
 2643 10:57:24.596193  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 pass
 2644 10:57:24.607222  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 pass
 2645 10:57:24.617010  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 skip
 2646 10:57:24.623093  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 pass
 2647 10:57:24.627950  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 pass
 2648 10:57:24.637759  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 pass
 2649 10:57:24.648710  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 pass
 2650 10:57:24.653623  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 pass
 2651 10:57:24.664626  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 pass
 2652 10:57:24.669696  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 pass
 2653 10:57:24.679588  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 fail
 2654 10:57:24.685775  dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 pass
 2655 10:57:24.690628  dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 pass
 2656 10:57:24.700428  dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 pass
 2657 10:57:24.706544  dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 pass
 2658 10:57:24.716250  dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 pass
 2659 10:57:24.727565  dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 pass
 2660 10:57:24.732407  dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 fail
 2661 10:57:24.742192  dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 skip
 2662 10:57:24.753191  dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 fail
 2663 10:57:24.763078  dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 skip
 2664 10:57:24.773983  dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 fail
 2665 10:57:24.783656  dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 fail
 2666 10:57:24.790000  dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 fail
 2667 10:57:24.794862  dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 fail
 2668 10:57:24.799670  dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 skip
 2669 10:57:24.804747  dt_test_unprobed_devices_sh_ocp_target-module_40300000 pass
 2670 10:57:24.810823  dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 pass
 2671 10:57:24.820648  dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 skip
 2672 10:57:24.825619  dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 skip
 2673 10:57:24.831698  dt_test_unprobed_devices_sh_ocp_target-module_47400000 pass
 2674 10:57:24.841486  dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 pass
 2675 10:57:24.846447  dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 pass
 2676 10:57:24.852583  dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 pass
 2677 10:57:24.857498  dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 pass
 2678 10:57:24.867339  dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 pass
 2679 10:57:24.873347  dt_test_unprobed_devices_sh_ocp_target-module_47810000 pass
 2680 10:57:24.873727  dt_test_unprobed_devices_sh_ocp_target-module_49000000 pass
 2681 10:57:24.883103  dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 pass
 2682 10:57:24.888123  dt_test_unprobed_devices_sh_ocp_target-module_49800000 pass
 2683 10:57:24.894209  dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 pass
 2684 10:57:24.899109  dt_test_unprobed_devices_sh_ocp_target-module_49900000 pass
 2685 10:57:24.903910  dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 pass
 2686 10:57:24.909110  dt_test_unprobed_devices_sh_ocp_target-module_49a00000 pass
 2687 10:57:24.914978  dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 pass
 2688 10:57:24.918828  dt_test_unprobed_devices_sh_ocp_target-module_4c000000 pass
 2689 10:57:24.929819  dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 fail
 2690 10:57:24.930200  dt_test_unprobed_devices_sh_ocp_target-module_50000000 pass
 2691 10:57:24.935895  dt_test_unprobed_devices_sh_ocp_target-module_53100000 pass
 2692 10:57:24.940916  dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 fail
 2693 10:57:24.950657  dt_test_unprobed_devices_sh_ocp_target-module_53500000 pass
 2694 10:57:24.956738  dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 fail
 2695 10:57:24.961590  dt_test_unprobed_devices_sh_ocp_target-module_56000000 pass
 2696 10:57:24.966419  dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 skip
 2697 10:57:24.971434  dt_test_unprobed_devices_sh_opp-table skip
 2698 10:57:24.971818  dt_test_unprobed_devices_sh_soc skip
 2699 10:57:24.977474  dt_test_unprobed_devices_sh_sound pass
 2700 10:57:24.982443  dt_test_unprobed_devices_sh_target-module_4b000000 pass
 2701 10:57:24.987196  dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 pass
 2702 10:57:24.998320  dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 pass
 2703 10:57:24.998714  dt_test_unprobed_devices_sh fail
 2704 10:57:25.003833  + ../../utils/send-to-lava.sh ./output/result.txt
 2705 10:57:25.179868  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-dt RESULT=pass>
 2706 10:57:25.181157  Received signal: <TESTCASE> TEST_CASE_ID=shardfile-dt RESULT=pass
 2708 10:57:25.377284  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip>
 2709 10:57:25.377909  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip
 2711 10:57:25.592847  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass>
 2712 10:57:25.593463  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass
 2714 10:57:25.777762  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip>
 2715 10:57:25.778389  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip
 2717 10:57:25.978408  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip>
 2718 10:57:25.979029  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip
 2720 10:57:26.182514  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip>
 2721 10:57:26.183138  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip
 2723 10:57:26.401175  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass>
 2724 10:57:26.401794  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass
 2726 10:57:26.612295  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass>
 2727 10:57:26.612920  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass
 2729 10:57:26.810806  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass>
 2730 10:57:26.811452  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass
 2732 10:57:27.006676  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass>
 2733 10:57:27.007326  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass
 2735 10:57:27.206529  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass>
 2736 10:57:27.207151  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass
 2738 10:57:27.400344  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass>
 2739 10:57:27.400984  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass
 2741 10:57:27.587149  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass>
 2742 10:57:27.587767  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass
 2744 10:57:27.801123  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail>
 2745 10:57:27.801756  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail
 2747 10:57:28.007199  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass>
 2748 10:57:28.007849  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass
 2750 10:57:28.400515  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass>
 2751 10:57:28.401302  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass
 2753 10:57:28.593424  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail>
 2754 10:57:28.594048  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail
 2756 10:57:28.785437  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip>
 2757 10:57:28.786055  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip
 2759 10:57:29.003892  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip>
 2760 10:57:29.004514  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip
 2762 10:57:29.187713  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip>
 2763 10:57:29.188337  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip
 2765 10:57:29.392454  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip>
 2766 10:57:29.393129  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip
 2768 10:57:29.587826  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip>
 2769 10:57:29.588449  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip
 2771 10:57:29.771667  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip>
 2772 10:57:29.772287  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip
 2774 10:57:29.971174  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip>
 2775 10:57:29.971816  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip
 2777 10:57:30.161028  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip>
 2778 10:57:30.161652  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip
 2780 10:57:30.360412  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip>
 2781 10:57:30.361066  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip
 2783 10:57:30.553243  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip>
 2784 10:57:30.553866  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip
 2786 10:57:30.754148  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip>
 2787 10:57:30.754777  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip
 2789 10:57:30.939018  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip>
 2790 10:57:30.939656  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip
 2792 10:57:31.129993  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip>
 2793 10:57:31.130634  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip
 2795 10:57:31.314549  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip>
 2796 10:57:31.315171  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip
 2798 10:57:31.514128  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip>
 2799 10:57:31.514761  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip
 2801 10:57:31.704080  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip>
 2802 10:57:31.704715  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip
 2804 10:57:31.879098  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip>
 2805 10:57:31.879719  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip
 2807 10:57:32.059443  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip>
 2808 10:57:32.060082  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip
 2810 10:57:32.246115  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip>
 2811 10:57:32.246741  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip
 2813 10:57:32.487608  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip>
 2814 10:57:32.488234  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip
 2816 10:57:32.688946  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip>
 2817 10:57:32.689568  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip
 2819 10:57:32.888424  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip>
 2820 10:57:32.889067  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip
 2822 10:57:33.080594  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip>
 2823 10:57:33.081275  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip
 2825 10:57:33.273927  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip>
 2826 10:57:33.274553  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip
 2828 10:57:33.456826  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip>
 2829 10:57:33.457449  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip
 2831 10:57:33.658639  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip>
 2832 10:57:33.659258  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip
 2834 10:57:33.841369  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip>
 2835 10:57:33.841991  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip
 2837 10:57:34.022903  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip>
 2838 10:57:34.023528  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip
 2840 10:57:34.198178  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip>
 2841 10:57:34.198829  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip
 2843 10:57:34.392603  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip>
 2844 10:57:34.393282  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip
 2846 10:57:34.572070  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip>
 2847 10:57:34.572713  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip
 2849 10:57:34.758111  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip>
 2850 10:57:34.758756  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip
 2852 10:57:34.950133  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip>
 2853 10:57:34.950754  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip
 2855 10:57:35.149890  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip>
 2856 10:57:35.150543  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip
 2858 10:57:35.340115  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip>
 2859 10:57:35.340754  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip
 2861 10:57:35.539687  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip>
 2862 10:57:35.540310  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip
 2864 10:57:35.747803  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip>
 2865 10:57:35.748428  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip
 2867 10:57:35.941114  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip>
 2868 10:57:35.941735  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip
 2870 10:57:36.132407  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip>
 2871 10:57:36.133070  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip
 2873 10:57:36.315425  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip>
 2874 10:57:36.316046  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip
 2876 10:57:36.507801  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip>
 2877 10:57:36.508454  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip
 2879 10:57:36.709653  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip>
 2880 10:57:36.710291  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip
 2882 10:57:36.909293  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip>
 2883 10:57:36.909944  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip
 2885 10:57:37.100257  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip>
 2886 10:57:37.100879  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip
 2888 10:57:37.290217  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip>
 2889 10:57:37.290839  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip
 2891 10:57:37.481467  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip>
 2892 10:57:37.482088  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip
 2894 10:57:37.698930  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip>
 2895 10:57:37.699556  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip
 2897 10:57:37.906957  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip>
 2898 10:57:37.907606  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip
 2900 10:57:38.098992  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip>
 2901 10:57:38.099627  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip
 2903 10:57:38.291232  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip>
 2904 10:57:38.291866  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip
 2906 10:57:38.500454  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip>
 2907 10:57:38.501125  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip
 2909 10:57:38.690833  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip>
 2910 10:57:38.691456  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip
 2912 10:57:38.889278  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip>
 2913 10:57:38.889928  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip
 2915 10:57:39.091370  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip>
 2916 10:57:39.092007  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip
 2918 10:57:39.318153  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip>
 2919 10:57:39.318791  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip
 2921 10:57:39.542128  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip>
 2922 10:57:39.542767  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip
 2924 10:57:39.719714  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip>
 2925 10:57:39.720338  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip
 2927 10:57:39.910922  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip>
 2928 10:57:39.911547  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip
 2930 10:57:40.106374  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip>
 2931 10:57:40.106999  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip
 2933 10:57:40.340963  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip>
 2934 10:57:40.341593  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip
 2936 10:57:40.534331  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip>
 2937 10:57:40.534959  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip
 2939 10:57:40.717037  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip>
 2940 10:57:40.717661  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip
 2942 10:57:40.925126  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip>
 2943 10:57:40.925766  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip
 2945 10:57:41.111144  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip>
 2946 10:57:41.111795  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip
 2948 10:57:41.289690  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip>
 2949 10:57:41.290313  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip
 2951 10:57:41.492831  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip>
 2952 10:57:41.493455  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip
 2954 10:57:41.734543  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip>
 2955 10:57:41.735172  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip
 2957 10:57:41.934821  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip>
 2958 10:57:41.935444  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip
 2960 10:57:42.126907  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip>
 2961 10:57:42.127530  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip
 2963 10:57:42.309723  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip>
 2964 10:57:42.310347  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip
 2966 10:57:42.492398  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip>
 2967 10:57:42.493045  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip
 2969 10:57:42.659203  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip>
 2970 10:57:42.659853  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip
 2972 10:57:42.835751  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip>
 2973 10:57:42.836377  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip
 2975 10:57:43.029044  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip>
 2976 10:57:43.029692  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip
 2978 10:57:43.217952  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip>
 2979 10:57:43.218580  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip
 2981 10:57:43.896913  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip>
 2982 10:57:43.897674  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip
 2984 10:57:44.093629  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip>
 2985 10:57:44.094279  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip
 2987 10:57:44.288121  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip>
 2988 10:57:44.288751  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip
 2990 10:57:44.468393  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass>
 2991 10:57:44.469042  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass
 2993 10:57:44.667815  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass>
 2994 10:57:44.668439  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass
 2996 10:57:44.850269  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass>
 2997 10:57:44.850901  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass
 2999 10:57:45.017935  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass>
 3000 10:57:45.018584  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass
 3002 10:57:45.210935  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass>
 3003 10:57:45.211593  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass
 3005 10:57:45.426249  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass>
 3006 10:57:45.426871  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass
 3008 10:57:45.602343  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass>
 3009 10:57:45.602968  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass
 3011 10:57:45.811176  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass>
 3012 10:57:45.811798  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass
 3014 10:57:46.010440  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail>
 3015 10:57:46.011064  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail
 3017 10:57:46.187738  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass>
 3018 10:57:46.188360  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass
 3020 10:57:46.371305  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass>
 3021 10:57:46.371928  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass
 3023 10:57:46.587680  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass>
 3024 10:57:46.588305  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass
 3026 10:57:46.760845  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail>
 3027 10:57:46.761472  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail
 3029 10:57:46.961578  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip>
 3030 10:57:46.962204  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip
 3032 10:57:47.145387  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip>
 3033 10:57:47.146014  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip
 3035 10:57:47.354727  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip>
 3036 10:57:47.355365  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip
 3038 10:57:47.573402  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip>
 3039 10:57:47.574026  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip
 3041 10:57:47.754227  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip>
 3042 10:57:47.754851  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip
 3044 10:57:47.938030  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip>
 3045 10:57:47.938666  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip
 3047 10:57:48.119925  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip>
 3048 10:57:48.120566  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip
 3050 10:57:48.299484  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip>
 3051 10:57:48.300108  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip
 3053 10:57:48.488710  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip>
 3054 10:57:48.489378  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip
 3056 10:57:48.696855  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip>
 3057 10:57:48.697490  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip
 3059 10:57:49.072744  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip>
 3060 10:57:49.073542  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip
 3062 10:57:49.272395  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip>
 3063 10:57:49.273050  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip
 3065 10:57:49.456891  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip
 3067 10:57:49.459817  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip>
 3068 10:57:49.661023  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip
 3070 10:57:49.664012  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip>
 3071 10:57:49.829436  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip
 3073 10:57:49.832517  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip>
 3074 10:57:50.021692  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass>
 3075 10:57:50.022320  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass
 3077 10:57:50.213758  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail>
 3078 10:57:50.214404  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail
 3080 10:57:50.413120  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail>
 3081 10:57:50.413747  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail
 3083 10:57:50.620911  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip>
 3084 10:57:50.621530  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip
 3086 10:57:50.804375  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass>
 3087 10:57:50.805010  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass
 3089 10:57:50.987006  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail>
 3090 10:57:50.987627  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail
 3092 10:57:51.178691  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass>
 3093 10:57:51.179307  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass
 3095 10:57:51.369567  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail>
 3096 10:57:51.370191  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail
 3098 10:57:51.547863  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass>
 3099 10:57:51.548486  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass
 3101 10:57:51.739900  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass>
 3102 10:57:51.740520  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass
 3104 10:57:51.919202  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass>
 3105 10:57:51.919823  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass
 3107 10:57:52.079223  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass>
 3108 10:57:52.079842  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass
 3110 10:57:52.261709  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass>
 3111 10:57:52.262330  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass
 3113 10:57:52.438910  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass>
 3114 10:57:52.439537  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass
 3116 10:57:52.629924  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_eeprom_50 RESULT=pass>
 3117 10:57:52.630553  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_eeprom_50 RESULT=pass
 3119 10:57:52.822140  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_eeprom_50_nvmem-layout RESULT=skip>
 3120 10:57:52.822766  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_eeprom_50_nvmem-layout RESULT=skip
 3122 10:57:53.046818  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass>
 3123 10:57:53.047464  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass
 3125 10:57:53.238689  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass>
 3126 10:57:53.239310  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass
 3128 10:57:53.464478  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail>
 3129 10:57:53.465129  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail
 3131 10:57:53.698796  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail>
 3132 10:57:53.699433  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail
 3134 10:57:53.879975  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass>
 3135 10:57:53.880599  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass
 3137 10:57:54.069367  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail>
 3138 10:57:54.070012  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail
 3140 10:57:54.276720  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail>
 3141 10:57:54.277362  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail
 3143 10:57:54.462123  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass>
 3144 10:57:54.462748  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass
 3146 10:57:54.653698  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass>
 3147 10:57:54.654318  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass
 3149 10:57:54.840464  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass>
 3150 10:57:54.841111  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass
 3152 10:57:55.029966  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass>
 3153 10:57:55.030586  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass
 3155 10:57:55.222728  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass>
 3156 10:57:55.223391  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass
 3158 10:57:55.404127  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass>
 3159 10:57:55.404751  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass
 3161 10:57:55.621277  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass>
 3162 10:57:55.621897  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass
 3164 10:57:55.805918  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass>
 3165 10:57:55.806541  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass
 3167 10:57:55.986167  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass>
 3168 10:57:55.986786  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass
 3170 10:57:56.163921  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail>
 3171 10:57:56.164548  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail
 3173 10:57:56.348440  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip>
 3174 10:57:56.349087  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip
 3176 10:57:56.539160  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass>
 3177 10:57:56.539796  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass
 3179 10:57:56.732144  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass>
 3180 10:57:56.732768  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass
 3182 10:57:56.924068  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass>
 3183 10:57:56.924690  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass
 3185 10:57:57.107397  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass>
 3186 10:57:57.108024  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass
 3188 10:57:57.289935  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass>
 3189 10:57:57.290575  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass
 3191 10:57:57.476511  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass>
 3192 10:57:57.477159  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass
 3194 10:57:57.650478  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass>
 3195 10:57:57.651102  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass
 3197 10:57:57.838925  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass>
 3198 10:57:57.839546  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass
 3200 10:57:58.038325  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass>
 3201 10:57:58.038946  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass
 3203 10:57:58.218501  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass>
 3204 10:57:58.219121  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass
 3206 10:57:58.397799  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass>
 3207 10:57:58.398417  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass
 3209 10:57:58.586366  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass>
 3210 10:57:58.586989  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass
 3212 10:57:58.774896  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass>
 3213 10:57:58.775517  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass
 3215 10:57:58.985805  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass>
 3216 10:57:58.986430  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass
 3218 10:57:59.190261  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass>
 3219 10:57:59.190907  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass
 3221 10:57:59.381120  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass>
 3222 10:57:59.381738  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass
 3224 10:57:59.572930  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass>
 3225 10:57:59.573555  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass
 3227 10:57:59.759777  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass>
 3228 10:57:59.760400  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass
 3230 10:57:59.941888  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass>
 3231 10:57:59.942509  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass
 3233 10:58:00.140021  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass>
 3234 10:58:00.140644  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass
 3236 10:58:00.318290  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass>
 3237 10:58:00.318910  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass
 3239 10:58:00.509491  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_54 RESULT=fail>
 3240 10:58:00.510128  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_54 RESULT=fail
 3242 10:58:00.702797  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_54_nvmem-layout RESULT=skip>
 3243 10:58:00.703420  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_54_nvmem-layout RESULT=skip
 3245 10:58:00.918979  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_55 RESULT=fail>
 3246 10:58:00.919602  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_55 RESULT=fail
 3248 10:58:01.132257  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_55_nvmem-layout RESULT=skip>
 3249 10:58:01.132881  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_55_nvmem-layout RESULT=skip
 3251 10:58:01.337911  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_56 RESULT=fail>
 3252 10:58:01.338541  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_56 RESULT=fail
 3254 10:58:01.525787  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_56_nvmem-layout RESULT=skip>
 3255 10:58:01.526412  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_56_nvmem-layout RESULT=skip
 3257 10:58:01.728534  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_57 RESULT=fail>
 3258 10:58:01.729205  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_57 RESULT=fail
 3260 10:58:01.929145  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_57_nvmem-layout RESULT=skip>
 3261 10:58:01.929769  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_57_nvmem-layout RESULT=skip
 3263 10:58:02.144347  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass>
 3264 10:58:02.144969  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass
 3266 10:58:02.364664  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass>
 3267 10:58:02.365322  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass
 3269 10:58:02.599794  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass>
 3270 10:58:02.600423  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass
 3272 10:58:02.794873  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass>
 3273 10:58:02.795433  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass
 3275 10:58:02.995071  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass>
 3276 10:58:02.995691  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass
 3278 10:58:03.187976  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass>
 3279 10:58:03.188516  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass
 3281 10:58:03.410438  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass>
 3282 10:58:03.411064  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass
 3284 10:58:03.587714  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass>
 3285 10:58:03.588349  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass
 3287 10:58:03.791191  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass>
 3288 10:58:03.791808  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass
 3290 10:58:04.009602  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass>
 3291 10:58:04.010242  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass
 3293 10:58:04.204734  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass>
 3294 10:58:04.205404  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass
 3296 10:58:04.395710  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass>
 3297 10:58:04.396333  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass
 3299 10:58:04.598783  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass>
 3300 10:58:04.599415  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass
 3302 10:58:04.769657  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass>
 3303 10:58:04.770282  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass
 3305 10:58:04.938038  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip>
 3306 10:58:04.938657  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip
 3308 10:58:05.128597  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass>
 3309 10:58:05.129259  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass
 3311 10:58:05.308933  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass>
 3312 10:58:05.309566  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass
 3314 10:58:05.496539  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass>
 3315 10:58:05.497193  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass
 3317 10:58:05.687117  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass>
 3318 10:58:05.687737  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass
 3320 10:58:05.864246  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass>
 3321 10:58:05.864883  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass
 3323 10:58:06.044518  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass>
 3324 10:58:06.045174  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass
 3326 10:58:06.229009  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass>
 3327 10:58:06.229630  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass
 3329 10:58:06.451471  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail>
 3330 10:58:06.452095  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail
 3332 10:58:06.652499  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass>
 3333 10:58:06.653153  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass
 3335 10:58:06.882921  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass>
 3336 10:58:06.883544  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass
 3338 10:58:07.075784  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass>
 3339 10:58:07.076401  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass
 3341 10:58:07.278269  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass>
 3342 10:58:07.278887  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass
 3344 10:58:07.477680  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass>
 3345 10:58:07.478303  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass
 3347 10:58:07.655895  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass>
 3348 10:58:07.656516  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass
 3350 10:58:07.854310  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail>
 3351 10:58:07.854932  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail
 3353 10:58:08.036967  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip>
 3354 10:58:08.037600  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip
 3356 10:58:08.238709  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail>
 3357 10:58:08.239337  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail
 3359 10:58:08.421063  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip>
 3360 10:58:08.421684  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip
 3362 10:58:08.605748  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail>
 3363 10:58:08.606367  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail
 3365 10:58:08.796900  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail>
 3366 10:58:08.797519  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail
 3368 10:58:08.987322  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail>
 3369 10:58:08.987949  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail
 3371 10:58:09.177601  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail>
 3372 10:58:09.178223  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail
 3374 10:58:09.751110  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip>
 3375 10:58:09.751865  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip
 3377 10:58:09.951252  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass>
 3378 10:58:09.951874  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass
 3380 10:58:10.143644  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass>
 3381 10:58:10.144284  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass
 3383 10:58:10.337323  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip>
 3384 10:58:10.337949  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip
 3386 10:58:10.517663  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip
 3388 10:58:10.521781  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip>
 3389 10:58:10.696376  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass>
 3390 10:58:10.697001  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass
 3392 10:58:10.889198  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass>
 3393 10:58:10.889822  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass
 3395 10:58:11.078840  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass>
 3396 10:58:11.079485  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass
 3398 10:58:11.276891  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass>
 3399 10:58:11.277518  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass
 3401 10:58:11.459943  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass>
 3402 10:58:11.460563  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass
 3404 10:58:11.676751  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass>
 3405 10:58:11.677410  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass
 3407 10:58:11.879855  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass>
 3408 10:58:11.880478  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass
 3410 10:58:12.054455  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass>
 3411 10:58:12.055075  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass
 3413 10:58:12.245865  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass>
 3414 10:58:12.246484  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass
 3416 10:58:12.429858  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass>
 3417 10:58:12.430472  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass
 3419 10:58:12.631868  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass>
 3420 10:58:12.632489  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass
 3422 10:58:12.829543  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass>
 3423 10:58:12.830161  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass
 3425 10:58:13.022162  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass>
 3426 10:58:13.022780  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass
 3428 10:58:13.196888  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass>
 3429 10:58:13.197507  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass
 3431 10:58:13.381054  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass>
 3432 10:58:13.381668  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass
 3434 10:58:13.551373  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass>
 3435 10:58:13.551991  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass
 3437 10:58:13.732494  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail>
 3438 10:58:13.733141  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail
 3440 10:58:13.945053  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass>
 3441 10:58:13.945687  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass
 3443 10:58:14.129251  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass>
 3444 10:58:14.129866  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass
 3446 10:58:14.298388  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail>
 3447 10:58:14.299004  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail
 3449 10:58:14.478241  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass>
 3450 10:58:14.478885  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass
 3452 10:58:15.331574  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail>
 3453 10:58:15.332346  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail
 3455 10:58:16.658620  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass>
 3456 10:58:16.659382  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass
 3458 10:58:16.841641  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip>
 3459 10:58:16.842265  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip
 3461 10:58:17.062484  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip>
 3462 10:58:17.063110  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip
 3464 10:58:17.258825  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip>
 3465 10:58:17.259448  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip
 3467 10:58:17.449148  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass>
 3468 10:58:17.449782  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass
 3470 10:58:17.661765  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass>
 3471 10:58:17.662391  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass
 3473 10:58:17.849320  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass>
 3474 10:58:17.849941  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass
 3476 10:58:18.057985  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass>
 3477 10:58:18.058423  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass
 3479 10:58:18.239418  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail>
 3480 10:58:18.239818  + set +x
 3481 10:58:18.240365  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail
 3483 10:58:18.242652  <LAVA_SIGNAL_ENDRUN 1_kselftest-dt 1219249_1.6.2.4.5>
 3484 10:58:18.243267  Received signal: <ENDRUN> 1_kselftest-dt 1219249_1.6.2.4.5
 3485 10:58:18.243622  Ending use of test pattern.
 3486 10:58:18.243927  Ending test lava.1_kselftest-dt (1219249_1.6.2.4.5), duration 268.90
 3488 10:58:18.306524  <LAVA_TEST_RUNNER EXIT>
 3489 10:58:18.307144  ok: lava_test_shell seems to have completed
 3490 10:58:18.314878  dt_test_unprobed_devices_sh: fail
dt_test_unprobed_devices_sh_: skip
dt_test_unprobed_devices_sh_clk_mcasp0: pass
dt_test_unprobed_devices_sh_clk_mcasp0_fixed: skip
dt_test_unprobed_devices_sh_cpus_cpu_0: skip
dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate: skip
dt_test_unprobed_devices_sh_fixedregulator0: pass
dt_test_unprobed_devices_sh_leds: pass
dt_test_unprobed_devices_sh_ocp: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0: fail
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_eeprom_50: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_eeprom_50_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_54: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_54_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_55: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_55_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_56: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_56_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_57: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_57_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000: skip
dt_test_unprobed_devices_sh_ocp_target-module_47400000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800: pass
dt_test_unprobed_devices_sh_ocp_target-module_47810000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_50000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_53500000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_56000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0: skip
dt_test_unprobed_devices_sh_opp-table: skip
dt_test_unprobed_devices_sh_soc: skip
dt_test_unprobed_devices_sh_sound: pass
dt_test_unprobed_devices_sh_target-module_4b000000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0: pass
shardfile-dt: pass

 3491 10:58:18.316321  end: 3.1 lava-test-shell (duration 00:04:31) [common]
 3492 10:58:18.316749  end: 3 lava-test-retry (duration 00:04:31) [common]
 3493 10:58:18.317198  start: 4 finalize (timeout 00:02:23) [common]
 3494 10:58:18.317624  start: 4.1 power-off (timeout 00:00:30) [common]
 3495 10:58:18.318117  Calling: 'drpm' 'lf-bbb-02' 'off'
 3496 10:58:18.609042  >> OFF

 3497 10:58:18.610216  Returned 0 in 0 seconds
 3498 10:58:18.711156  end: 4.1 power-off (duration 00:00:00) [common]
 3500 10:58:18.712300  start: 4.2 read-feedback (timeout 00:02:23) [common]
 3501 10:58:18.713123  Listened to connection for namespace 'common' for up to 1s
 3502 10:58:18.713806  Listened to connection for namespace 'common' for up to 1s
 3503 10:58:19.713427  Finalising connection for namespace 'common'
 3504 10:58:19.713913  Disconnecting from shell: Finalise
 3505 10:58:19.714285  / # 
 3506 10:58:19.815007  end: 4.2 read-feedback (duration 00:00:01) [common]
 3507 10:58:19.815520  end: 4 finalize (duration 00:00:01) [common]
 3508 10:58:19.816005  Cleaning after the job
 3509 10:58:19.816462  Cleaning up download directory: /var/lib/lava/dispatcher/tmp/1219249/tftp-deploy-l4hclial/ramdisk
 3510 10:58:19.822678  Cleaning up download directory: /var/lib/lava/dispatcher/tmp/1219249/tftp-deploy-l4hclial/kernel
 3511 10:58:19.827534  Cleaning up download directory: /var/lib/lava/dispatcher/tmp/1219249/tftp-deploy-l4hclial/dtb
 3512 10:58:19.828264  Cleaning up download directory: /var/lib/lava/dispatcher/tmp/1219249/tftp-deploy-l4hclial/nfsrootfs
 3513 10:58:19.939259  Cleaning up download directory: /var/lib/lava/dispatcher/tmp/1219249/tftp-deploy-l4hclial/modules
 3514 10:58:19.944715  Override tmp directory removed at /var/lib/lava/dispatcher/tmp/1219249
 3515 10:58:21.106060  Root tmp directory removed at /var/lib/lava/dispatcher/tmp/1219249
 3516 10:58:21.106389  Job finished correctly