Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 10:23:39.359585 lava-dispatcher, installed at version: 2024.01
2 10:23:39.360382 start: 0 validate
3 10:23:39.360863 Start time: 2024-11-08 10:23:39.360832+00:00 (UTC)
4 10:23:39.361387 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 10:23:39.361929 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230703.0%2Farm64%2Frootfs.cpio.gz exists
6 10:23:39.403430 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 10:23:39.404017 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241108%2Farm64%2Fdefconfig%2BCONFIG_RANDOMIZE_BASE%3Dy%2Fgcc-12%2Fkernel%2FImage exists
8 10:23:40.450174 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 10:23:40.450854 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241108%2Farm64%2Fdefconfig%2BCONFIG_RANDOMIZE_BASE%3Dy%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 10:23:45.527837 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 10:23:45.528501 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241108%2Farm64%2Fdefconfig%2BCONFIG_RANDOMIZE_BASE%3Dy%2Fgcc-12%2Fmodules.tar.xz exists
12 10:23:46.587890 validate duration: 7.23
14 10:23:46.589369 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 10:23:46.589991 start: 1.1 download-retry (timeout 00:10:00) [common]
16 10:23:46.590559 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 10:23:46.591521 Not decompressing ramdisk as can be used compressed.
18 10:23:46.592280 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230703.0/arm64/rootfs.cpio.gz
19 10:23:46.592745 saving as /var/lib/lava/dispatcher/tmp/958496/tftp-deploy-fr5ymm_5/ramdisk/rootfs.cpio.gz
20 10:23:46.593228 total size: 8181887 (7 MB)
21 10:23:46.637781 progress 0 % (0 MB)
22 10:23:46.648342 progress 5 % (0 MB)
23 10:23:46.658336 progress 10 % (0 MB)
24 10:23:46.669601 progress 15 % (1 MB)
25 10:23:46.678337 progress 20 % (1 MB)
26 10:23:46.684591 progress 25 % (1 MB)
27 10:23:46.690184 progress 30 % (2 MB)
28 10:23:46.696210 progress 35 % (2 MB)
29 10:23:46.701893 progress 40 % (3 MB)
30 10:23:46.707588 progress 45 % (3 MB)
31 10:23:46.712719 progress 50 % (3 MB)
32 10:23:46.718205 progress 55 % (4 MB)
33 10:23:46.723261 progress 60 % (4 MB)
34 10:23:46.728924 progress 65 % (5 MB)
35 10:23:46.733998 progress 70 % (5 MB)
36 10:23:46.739409 progress 75 % (5 MB)
37 10:23:46.744466 progress 80 % (6 MB)
38 10:23:46.749884 progress 85 % (6 MB)
39 10:23:46.754929 progress 90 % (7 MB)
40 10:23:46.760101 progress 95 % (7 MB)
41 10:23:46.764725 progress 100 % (7 MB)
42 10:23:46.765359 7 MB downloaded in 0.17 s (45.33 MB/s)
43 10:23:46.765915 end: 1.1.1 http-download (duration 00:00:00) [common]
45 10:23:46.766804 end: 1.1 download-retry (duration 00:00:00) [common]
46 10:23:46.767096 start: 1.2 download-retry (timeout 00:10:00) [common]
47 10:23:46.767365 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 10:23:46.767853 downloading http://storage.kernelci.org/next/master/next-20241108/arm64/defconfig+CONFIG_RANDOMIZE_BASE=y/gcc-12/kernel/Image
49 10:23:46.768126 saving as /var/lib/lava/dispatcher/tmp/958496/tftp-deploy-fr5ymm_5/kernel/Image
50 10:23:46.768338 total size: 46121472 (43 MB)
51 10:23:46.768553 No compression specified
52 10:23:46.803926 progress 0 % (0 MB)
53 10:23:46.834990 progress 5 % (2 MB)
54 10:23:46.864325 progress 10 % (4 MB)
55 10:23:46.892460 progress 15 % (6 MB)
56 10:23:46.920393 progress 20 % (8 MB)
57 10:23:46.947938 progress 25 % (11 MB)
58 10:23:46.975885 progress 30 % (13 MB)
59 10:23:47.003410 progress 35 % (15 MB)
60 10:23:47.031600 progress 40 % (17 MB)
61 10:23:47.059124 progress 45 % (19 MB)
62 10:23:47.086680 progress 50 % (22 MB)
63 10:23:47.114647 progress 55 % (24 MB)
64 10:23:47.142443 progress 60 % (26 MB)
65 10:23:47.169987 progress 65 % (28 MB)
66 10:23:47.197985 progress 70 % (30 MB)
67 10:23:47.228487 progress 75 % (33 MB)
68 10:23:47.256803 progress 80 % (35 MB)
69 10:23:47.284555 progress 85 % (37 MB)
70 10:23:47.312494 progress 90 % (39 MB)
71 10:23:47.340596 progress 95 % (41 MB)
72 10:23:47.367616 progress 100 % (43 MB)
73 10:23:47.368303 43 MB downloaded in 0.60 s (73.31 MB/s)
74 10:23:47.368801 end: 1.2.1 http-download (duration 00:00:01) [common]
76 10:23:47.369629 end: 1.2 download-retry (duration 00:00:01) [common]
77 10:23:47.369905 start: 1.3 download-retry (timeout 00:09:59) [common]
78 10:23:47.370191 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 10:23:47.370718 downloading http://storage.kernelci.org/next/master/next-20241108/arm64/defconfig+CONFIG_RANDOMIZE_BASE=y/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
80 10:23:47.371033 saving as /var/lib/lava/dispatcher/tmp/958496/tftp-deploy-fr5ymm_5/dtb/meson-g12b-a311d-libretech-cc.dtb
81 10:23:47.371271 total size: 54703 (0 MB)
82 10:23:47.371505 No compression specified
83 10:23:47.416732 progress 59 % (0 MB)
84 10:23:47.417647 progress 100 % (0 MB)
85 10:23:47.418218 0 MB downloaded in 0.05 s (1.11 MB/s)
86 10:23:47.418688 end: 1.3.1 http-download (duration 00:00:00) [common]
88 10:23:47.419498 end: 1.3 download-retry (duration 00:00:00) [common]
89 10:23:47.419759 start: 1.4 download-retry (timeout 00:09:59) [common]
90 10:23:47.420052 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 10:23:47.420542 downloading http://storage.kernelci.org/next/master/next-20241108/arm64/defconfig+CONFIG_RANDOMIZE_BASE=y/gcc-12/modules.tar.xz
92 10:23:47.420793 saving as /var/lib/lava/dispatcher/tmp/958496/tftp-deploy-fr5ymm_5/modules/modules.tar
93 10:23:47.420999 total size: 11680908 (11 MB)
94 10:23:47.421210 Using unxz to decompress xz
95 10:23:47.457950 progress 0 % (0 MB)
96 10:23:47.524231 progress 5 % (0 MB)
97 10:23:47.598623 progress 10 % (1 MB)
98 10:23:47.693937 progress 15 % (1 MB)
99 10:23:47.789682 progress 20 % (2 MB)
100 10:23:47.868231 progress 25 % (2 MB)
101 10:23:47.940044 progress 30 % (3 MB)
102 10:23:48.019362 progress 35 % (3 MB)
103 10:23:48.098349 progress 40 % (4 MB)
104 10:23:48.175727 progress 45 % (5 MB)
105 10:23:48.259463 progress 50 % (5 MB)
106 10:23:48.340653 progress 55 % (6 MB)
107 10:23:48.422565 progress 60 % (6 MB)
108 10:23:48.504316 progress 65 % (7 MB)
109 10:23:48.585871 progress 70 % (7 MB)
110 10:23:48.667581 progress 75 % (8 MB)
111 10:23:48.750417 progress 80 % (8 MB)
112 10:23:48.829852 progress 85 % (9 MB)
113 10:23:48.907854 progress 90 % (10 MB)
114 10:23:48.985000 progress 95 % (10 MB)
115 10:23:49.061300 progress 100 % (11 MB)
116 10:23:49.073564 11 MB downloaded in 1.65 s (6.74 MB/s)
117 10:23:49.074140 end: 1.4.1 http-download (duration 00:00:02) [common]
119 10:23:49.074970 end: 1.4 download-retry (duration 00:00:02) [common]
120 10:23:49.075240 start: 1.5 prepare-tftp-overlay (timeout 00:09:58) [common]
121 10:23:49.075507 start: 1.5.1 extract-nfsrootfs (timeout 00:09:58) [common]
122 10:23:49.075758 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 10:23:49.076220 start: 1.5.2 lava-overlay (timeout 00:09:58) [common]
124 10:23:49.077371 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/958496/lava-overlay-1k8i99jk
125 10:23:49.078205 makedir: /var/lib/lava/dispatcher/tmp/958496/lava-overlay-1k8i99jk/lava-958496/bin
126 10:23:49.078846 makedir: /var/lib/lava/dispatcher/tmp/958496/lava-overlay-1k8i99jk/lava-958496/tests
127 10:23:49.079462 makedir: /var/lib/lava/dispatcher/tmp/958496/lava-overlay-1k8i99jk/lava-958496/results
128 10:23:49.080128 Creating /var/lib/lava/dispatcher/tmp/958496/lava-overlay-1k8i99jk/lava-958496/bin/lava-add-keys
129 10:23:49.081108 Creating /var/lib/lava/dispatcher/tmp/958496/lava-overlay-1k8i99jk/lava-958496/bin/lava-add-sources
130 10:23:49.082023 Creating /var/lib/lava/dispatcher/tmp/958496/lava-overlay-1k8i99jk/lava-958496/bin/lava-background-process-start
131 10:23:49.082948 Creating /var/lib/lava/dispatcher/tmp/958496/lava-overlay-1k8i99jk/lava-958496/bin/lava-background-process-stop
132 10:23:49.083926 Creating /var/lib/lava/dispatcher/tmp/958496/lava-overlay-1k8i99jk/lava-958496/bin/lava-common-functions
133 10:23:49.084882 Creating /var/lib/lava/dispatcher/tmp/958496/lava-overlay-1k8i99jk/lava-958496/bin/lava-echo-ipv4
134 10:23:49.085785 Creating /var/lib/lava/dispatcher/tmp/958496/lava-overlay-1k8i99jk/lava-958496/bin/lava-install-packages
135 10:23:49.086703 Creating /var/lib/lava/dispatcher/tmp/958496/lava-overlay-1k8i99jk/lava-958496/bin/lava-installed-packages
136 10:23:49.087677 Creating /var/lib/lava/dispatcher/tmp/958496/lava-overlay-1k8i99jk/lava-958496/bin/lava-os-build
137 10:23:49.088646 Creating /var/lib/lava/dispatcher/tmp/958496/lava-overlay-1k8i99jk/lava-958496/bin/lava-probe-channel
138 10:23:49.089549 Creating /var/lib/lava/dispatcher/tmp/958496/lava-overlay-1k8i99jk/lava-958496/bin/lava-probe-ip
139 10:23:49.090437 Creating /var/lib/lava/dispatcher/tmp/958496/lava-overlay-1k8i99jk/lava-958496/bin/lava-target-ip
140 10:23:49.091318 Creating /var/lib/lava/dispatcher/tmp/958496/lava-overlay-1k8i99jk/lava-958496/bin/lava-target-mac
141 10:23:49.092234 Creating /var/lib/lava/dispatcher/tmp/958496/lava-overlay-1k8i99jk/lava-958496/bin/lava-target-storage
142 10:23:49.093147 Creating /var/lib/lava/dispatcher/tmp/958496/lava-overlay-1k8i99jk/lava-958496/bin/lava-test-case
143 10:23:49.094029 Creating /var/lib/lava/dispatcher/tmp/958496/lava-overlay-1k8i99jk/lava-958496/bin/lava-test-event
144 10:23:49.094911 Creating /var/lib/lava/dispatcher/tmp/958496/lava-overlay-1k8i99jk/lava-958496/bin/lava-test-feedback
145 10:23:49.095807 Creating /var/lib/lava/dispatcher/tmp/958496/lava-overlay-1k8i99jk/lava-958496/bin/lava-test-raise
146 10:23:49.096748 Creating /var/lib/lava/dispatcher/tmp/958496/lava-overlay-1k8i99jk/lava-958496/bin/lava-test-reference
147 10:23:49.097644 Creating /var/lib/lava/dispatcher/tmp/958496/lava-overlay-1k8i99jk/lava-958496/bin/lava-test-runner
148 10:23:49.098527 Creating /var/lib/lava/dispatcher/tmp/958496/lava-overlay-1k8i99jk/lava-958496/bin/lava-test-set
149 10:23:49.099404 Creating /var/lib/lava/dispatcher/tmp/958496/lava-overlay-1k8i99jk/lava-958496/bin/lava-test-shell
150 10:23:49.100358 Updating /var/lib/lava/dispatcher/tmp/958496/lava-overlay-1k8i99jk/lava-958496/bin/lava-install-packages (oe)
151 10:23:49.101400 Updating /var/lib/lava/dispatcher/tmp/958496/lava-overlay-1k8i99jk/lava-958496/bin/lava-installed-packages (oe)
152 10:23:49.102230 Creating /var/lib/lava/dispatcher/tmp/958496/lava-overlay-1k8i99jk/lava-958496/environment
153 10:23:49.102946 LAVA metadata
154 10:23:49.103437 - LAVA_JOB_ID=958496
155 10:23:49.103869 - LAVA_DISPATCHER_IP=192.168.6.2
156 10:23:49.104564 start: 1.5.2.1 ssh-authorize (timeout 00:09:57) [common]
157 10:23:49.106354 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 10:23:49.106950 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:57) [common]
159 10:23:49.107362 skipped lava-vland-overlay
160 10:23:49.107853 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 10:23:49.108410 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:57) [common]
162 10:23:49.108843 skipped lava-multinode-overlay
163 10:23:49.109332 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 10:23:49.109830 start: 1.5.2.4 test-definition (timeout 00:09:57) [common]
165 10:23:49.110300 Loading test definitions
166 10:23:49.110844 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:57) [common]
167 10:23:49.111285 Using /lava-958496 at stage 0
168 10:23:49.112917 uuid=958496_1.5.2.4.1 testdef=None
169 10:23:49.113266 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 10:23:49.113542 start: 1.5.2.4.2 test-overlay (timeout 00:09:57) [common]
171 10:23:49.115339 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 10:23:49.116194 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:57) [common]
174 10:23:49.118462 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 10:23:49.119322 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:57) [common]
177 10:23:49.121545 runner path: /var/lib/lava/dispatcher/tmp/958496/lava-overlay-1k8i99jk/lava-958496/0/tests/0_dmesg test_uuid 958496_1.5.2.4.1
178 10:23:49.122116 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 10:23:49.122911 Creating lava-test-runner.conf files
181 10:23:49.123118 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/958496/lava-overlay-1k8i99jk/lava-958496/0 for stage 0
182 10:23:49.123451 - 0_dmesg
183 10:23:49.123815 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 10:23:49.124131 start: 1.5.2.5 compress-overlay (timeout 00:09:57) [common]
185 10:23:49.147878 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 10:23:49.148304 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:57) [common]
187 10:23:49.148580 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 10:23:49.148851 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 10:23:49.149116 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:57) [common]
190 10:23:50.060213 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
191 10:23:50.060705 start: 1.5.4 extract-modules (timeout 00:09:57) [common]
192 10:23:50.060992 extracting modules file /var/lib/lava/dispatcher/tmp/958496/tftp-deploy-fr5ymm_5/modules/modules.tar to /var/lib/lava/dispatcher/tmp/958496/extract-overlay-ramdisk-v2ygf669/ramdisk
193 10:23:51.402171 end: 1.5.4 extract-modules (duration 00:00:01) [common]
194 10:23:51.402659 start: 1.5.5 apply-overlay-tftp (timeout 00:09:55) [common]
195 10:23:51.402938 [common] Applying overlay /var/lib/lava/dispatcher/tmp/958496/compress-overlay-hm0oia7f/overlay-1.5.2.5.tar.gz to ramdisk
196 10:23:51.403153 [common] Applying overlay /var/lib/lava/dispatcher/tmp/958496/compress-overlay-hm0oia7f/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/958496/extract-overlay-ramdisk-v2ygf669/ramdisk
197 10:23:51.432928 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 10:23:51.433344 start: 1.5.6 prepare-kernel (timeout 00:09:55) [common]
199 10:23:51.433616 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:55) [common]
200 10:23:51.433846 Converting downloaded kernel to a uImage
201 10:23:51.434149 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/958496/tftp-deploy-fr5ymm_5/kernel/Image /var/lib/lava/dispatcher/tmp/958496/tftp-deploy-fr5ymm_5/kernel/uImage
202 10:23:51.897019 output: Image Name:
203 10:23:51.897439 output: Created: Fri Nov 8 10:23:51 2024
204 10:23:51.897650 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 10:23:51.897858 output: Data Size: 46121472 Bytes = 45040.50 KiB = 43.98 MiB
206 10:23:51.898063 output: Load Address: 01080000
207 10:23:51.898264 output: Entry Point: 01080000
208 10:23:51.898464 output:
209 10:23:51.898798 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
210 10:23:51.899064 end: 1.5.6 prepare-kernel (duration 00:00:00) [common]
211 10:23:51.899333 start: 1.5.7 configure-preseed-file (timeout 00:09:55) [common]
212 10:23:51.899586 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 10:23:51.899843 start: 1.5.8 compress-ramdisk (timeout 00:09:55) [common]
214 10:23:51.900142 Building ramdisk /var/lib/lava/dispatcher/tmp/958496/extract-overlay-ramdisk-v2ygf669/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/958496/extract-overlay-ramdisk-v2ygf669/ramdisk
215 10:23:54.225794 >> 182876 blocks
216 10:24:02.793791 Adding RAMdisk u-boot header.
217 10:24:02.794490 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/958496/extract-overlay-ramdisk-v2ygf669/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/958496/extract-overlay-ramdisk-v2ygf669/ramdisk.cpio.gz.uboot
218 10:24:03.078596 output: Image Name:
219 10:24:03.079006 output: Created: Fri Nov 8 10:24:02 2024
220 10:24:03.079216 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 10:24:03.079423 output: Data Size: 26183169 Bytes = 25569.50 KiB = 24.97 MiB
222 10:24:03.079624 output: Load Address: 00000000
223 10:24:03.079824 output: Entry Point: 00000000
224 10:24:03.080092 output:
225 10:24:03.080959 rename /var/lib/lava/dispatcher/tmp/958496/extract-overlay-ramdisk-v2ygf669/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/958496/tftp-deploy-fr5ymm_5/ramdisk/ramdisk.cpio.gz.uboot
226 10:24:03.081708 end: 1.5.8 compress-ramdisk (duration 00:00:11) [common]
227 10:24:03.082296 end: 1.5 prepare-tftp-overlay (duration 00:00:14) [common]
228 10:24:03.082867 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:44) [common]
229 10:24:03.083365 No LXC device requested
230 10:24:03.083913 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 10:24:03.084514 start: 1.7 deploy-device-env (timeout 00:09:44) [common]
232 10:24:03.085058 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 10:24:03.085510 Checking files for TFTP limit of 4294967296 bytes.
234 10:24:03.088436 end: 1 tftp-deploy (duration 00:00:16) [common]
235 10:24:03.089070 start: 2 uboot-action (timeout 00:05:00) [common]
236 10:24:03.089647 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 10:24:03.090197 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 10:24:03.090751 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 10:24:03.091331 Using kernel file from prepare-kernel: 958496/tftp-deploy-fr5ymm_5/kernel/uImage
240 10:24:03.092047 substitutions:
241 10:24:03.092515 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 10:24:03.092965 - {DTB_ADDR}: 0x01070000
243 10:24:03.093404 - {DTB}: 958496/tftp-deploy-fr5ymm_5/dtb/meson-g12b-a311d-libretech-cc.dtb
244 10:24:03.093846 - {INITRD}: 958496/tftp-deploy-fr5ymm_5/ramdisk/ramdisk.cpio.gz.uboot
245 10:24:03.094286 - {KERNEL_ADDR}: 0x01080000
246 10:24:03.094719 - {KERNEL}: 958496/tftp-deploy-fr5ymm_5/kernel/uImage
247 10:24:03.095152 - {LAVA_MAC}: None
248 10:24:03.095624 - {PRESEED_CONFIG}: None
249 10:24:03.096089 - {PRESEED_LOCAL}: None
250 10:24:03.096523 - {RAMDISK_ADDR}: 0x08000000
251 10:24:03.096959 - {RAMDISK}: 958496/tftp-deploy-fr5ymm_5/ramdisk/ramdisk.cpio.gz.uboot
252 10:24:03.097400 - {ROOT_PART}: None
253 10:24:03.097833 - {ROOT}: None
254 10:24:03.098268 - {SERVER_IP}: 192.168.6.2
255 10:24:03.098704 - {TEE_ADDR}: 0x83000000
256 10:24:03.099134 - {TEE}: None
257 10:24:03.099564 Parsed boot commands:
258 10:24:03.100003 - setenv autoload no
259 10:24:03.100441 - setenv initrd_high 0xffffffff
260 10:24:03.100872 - setenv fdt_high 0xffffffff
261 10:24:03.101300 - dhcp
262 10:24:03.101729 - setenv serverip 192.168.6.2
263 10:24:03.102159 - tftpboot 0x01080000 958496/tftp-deploy-fr5ymm_5/kernel/uImage
264 10:24:03.102588 - tftpboot 0x08000000 958496/tftp-deploy-fr5ymm_5/ramdisk/ramdisk.cpio.gz.uboot
265 10:24:03.103016 - tftpboot 0x01070000 958496/tftp-deploy-fr5ymm_5/dtb/meson-g12b-a311d-libretech-cc.dtb
266 10:24:03.103447 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 10:24:03.103884 - bootm 0x01080000 0x08000000 0x01070000
268 10:24:03.104461 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 10:24:03.106100 start: 2.3 connect-device (timeout 00:05:00) [common]
271 10:24:03.106581 [common] connect-device Connecting to device using 'telnet conserv1 3007'
272 10:24:03.122221 Setting prompt string to ['lava-test: # ']
273 10:24:03.123840 end: 2.3 connect-device (duration 00:00:00) [common]
274 10:24:03.124544 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 10:24:03.125139 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 10:24:03.125707 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 10:24:03.126970 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
278 10:24:03.164581 >> OK - accepted request
279 10:24:03.166779 Returned 0 in 0 seconds
280 10:24:03.267945 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
282 10:24:03.269751 end: 2.4.1 reset-device (duration 00:00:00) [common]
283 10:24:03.270373 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
284 10:24:03.270933 Setting prompt string to ['Hit any key to stop autoboot']
285 10:24:03.271419 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 10:24:03.273196 Trying 192.168.56.21...
287 10:24:03.273724 Connected to conserv1.
288 10:24:03.274171 Escape character is '^]'.
289 10:24:03.274621
290 10:24:03.275088 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
291 10:24:03.275568
292 10:24:14.795436 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
293 10:24:14.796222 bl2_stage_init 0x01
294 10:24:14.796716 bl2_stage_init 0x81
295 10:24:14.801009 hw id: 0x0000 - pwm id 0x01
296 10:24:14.801570 bl2_stage_init 0xc1
297 10:24:14.802033 bl2_stage_init 0x02
298 10:24:14.802495
299 10:24:14.806479 L0:00000000
300 10:24:14.806998 L1:20000703
301 10:24:14.807453 L2:00008067
302 10:24:14.807888 L3:14000000
303 10:24:14.809426 B2:00402000
304 10:24:14.809903 B1:e0f83180
305 10:24:14.810355
306 10:24:14.810795 TE: 58124
307 10:24:14.811231
308 10:24:14.820547 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
309 10:24:14.821053
310 10:24:14.821490 Board ID = 1
311 10:24:14.821922 Set A53 clk to 24M
312 10:24:14.822351 Set A73 clk to 24M
313 10:24:14.826079 Set clk81 to 24M
314 10:24:14.826557 A53 clk: 1200 MHz
315 10:24:14.826986 A73 clk: 1200 MHz
316 10:24:14.829650 CLK81: 166.6M
317 10:24:14.830128 smccc: 00012a92
318 10:24:14.835175 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
319 10:24:14.840800 board id: 1
320 10:24:14.845924 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
321 10:24:14.856637 fw parse done
322 10:24:14.862562 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
323 10:24:14.905200 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
324 10:24:14.916251 PIEI prepare done
325 10:24:14.916741 fastboot data load
326 10:24:14.917182 fastboot data verify
327 10:24:14.921669 verify result: 266
328 10:24:14.927401 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
329 10:24:14.927967 LPDDR4 probe
330 10:24:14.928460 ddr clk to 1584MHz
331 10:24:14.935267 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
332 10:24:14.972622
333 10:24:14.973126 dmc_version 0001
334 10:24:14.979261 Check phy result
335 10:24:14.985191 INFO : End of CA training
336 10:24:14.985679 INFO : End of initialization
337 10:24:14.990677 INFO : Training has run successfully!
338 10:24:14.991154 Check phy result
339 10:24:14.996334 INFO : End of initialization
340 10:24:14.996813 INFO : End of read enable training
341 10:24:14.999585 INFO : End of fine write leveling
342 10:24:15.005188 INFO : End of Write leveling coarse delay
343 10:24:15.010771 INFO : Training has run successfully!
344 10:24:15.011268 Check phy result
345 10:24:15.011710 INFO : End of initialization
346 10:24:15.016340 INFO : End of read dq deskew training
347 10:24:15.021936 INFO : End of MPR read delay center optimization
348 10:24:15.022431 INFO : End of write delay center optimization
349 10:24:15.027578 INFO : End of read delay center optimization
350 10:24:15.033196 INFO : End of max read latency training
351 10:24:15.033682 INFO : Training has run successfully!
352 10:24:15.038788 1D training succeed
353 10:24:15.044729 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
354 10:24:15.092362 Check phy result
355 10:24:15.092876 INFO : End of initialization
356 10:24:15.114076 INFO : End of 2D read delay Voltage center optimization
357 10:24:15.134369 INFO : End of 2D read delay Voltage center optimization
358 10:24:15.186421 INFO : End of 2D write delay Voltage center optimization
359 10:24:15.235735 INFO : End of 2D write delay Voltage center optimization
360 10:24:15.241258 INFO : Training has run successfully!
361 10:24:15.241725
362 10:24:15.242168 channel==0
363 10:24:15.246881 RxClkDly_Margin_A0==88 ps 9
364 10:24:15.247340 TxDqDly_Margin_A0==98 ps 10
365 10:24:15.252549 RxClkDly_Margin_A1==88 ps 9
366 10:24:15.253007 TxDqDly_Margin_A1==98 ps 10
367 10:24:15.253452 TrainedVREFDQ_A0==74
368 10:24:15.258192 TrainedVREFDQ_A1==74
369 10:24:15.258651 VrefDac_Margin_A0==25
370 10:24:15.259088 DeviceVref_Margin_A0==40
371 10:24:15.263657 VrefDac_Margin_A1==25
372 10:24:15.264140 DeviceVref_Margin_A1==40
373 10:24:15.264582
374 10:24:15.265018
375 10:24:15.269352 channel==1
376 10:24:15.269850 RxClkDly_Margin_A0==98 ps 10
377 10:24:15.270289 TxDqDly_Margin_A0==98 ps 10
378 10:24:15.274938 RxClkDly_Margin_A1==98 ps 10
379 10:24:15.275401 TxDqDly_Margin_A1==98 ps 10
380 10:24:15.280500 TrainedVREFDQ_A0==77
381 10:24:15.280962 TrainedVREFDQ_A1==78
382 10:24:15.281398 VrefDac_Margin_A0==22
383 10:24:15.286180 DeviceVref_Margin_A0==37
384 10:24:15.286639 VrefDac_Margin_A1==22
385 10:24:15.291704 DeviceVref_Margin_A1==36
386 10:24:15.292198
387 10:24:15.292640 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
388 10:24:15.297337
389 10:24:15.325294 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000018 00000015 00000017 00000018 00000018 00000019 00000018 0000001a 0000001a 00000018 00000017 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
390 10:24:15.325826 2D training succeed
391 10:24:15.330913 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
392 10:24:15.336373 auto size-- 65535DDR cs0 size: 2048MB
393 10:24:15.336833 DDR cs1 size: 2048MB
394 10:24:15.341990 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
395 10:24:15.342454 cs0 DataBus test pass
396 10:24:15.347606 cs1 DataBus test pass
397 10:24:15.348098 cs0 AddrBus test pass
398 10:24:15.348536 cs1 AddrBus test pass
399 10:24:15.348964
400 10:24:15.353163 100bdlr_step_size ps== 420
401 10:24:15.353635 result report
402 10:24:15.358752 boot times 0Enable ddr reg access
403 10:24:15.364296 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
404 10:24:15.377754 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
405 10:24:15.950879 0.0;M3 CHK:0;cm4_sp_mode 0
406 10:24:15.951546 MVN_1=0x00000000
407 10:24:15.956236 MVN_2=0x00000000
408 10:24:15.962012 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
409 10:24:15.962484 OPS=0x10
410 10:24:15.962933 ring efuse init
411 10:24:15.963373 chipver efuse init
412 10:24:15.967604 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
413 10:24:15.973183 [0.018960 Inits done]
414 10:24:15.973648 secure task start!
415 10:24:15.974092 high task start!
416 10:24:15.977771 low task start!
417 10:24:15.978247 run into bl31
418 10:24:15.984455 NOTICE: BL31: v1.3(release):4fc40b1
419 10:24:15.992275 NOTICE: BL31: Built : 15:58:17, May 22 2019
420 10:24:15.992749 NOTICE: BL31: G12A normal boot!
421 10:24:16.017731 NOTICE: BL31: BL33 decompress pass
422 10:24:16.023351 ERROR: Error initializing runtime service opteed_fast
423 10:24:17.256384
424 10:24:17.257020
425 10:24:17.264698 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
426 10:24:17.265233
427 10:24:17.265709 Model: Libre Computer AML-A311D-CC Alta
428 10:24:17.473221 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
429 10:24:17.496491 DRAM: 2 GiB (effective 3.8 GiB)
430 10:24:17.639633 Core: 408 devices, 31 uclasses, devicetree: separate
431 10:24:17.645464 WDT: Not starting watchdog@f0d0
432 10:24:17.677707 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
433 10:24:17.690121 Loading Environment from FAT... Card did not respond to voltage select! : -110
434 10:24:17.695082 ** Bad device specification mmc 0 **
435 10:24:17.705427 Card did not respond to voltage select! : -110
436 10:24:17.713057 ** Bad device specification mmc 0 **
437 10:24:17.713531 Couldn't find partition mmc 0
438 10:24:17.721448 Card did not respond to voltage select! : -110
439 10:24:17.726914 ** Bad device specification mmc 0 **
440 10:24:17.727401 Couldn't find partition mmc 0
441 10:24:17.732010 Error: could not access storage.
442 10:24:18.995798 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
443 10:24:18.996513 bl2_stage_init 0x01
444 10:24:18.996988 bl2_stage_init 0x81
445 10:24:19.001363 hw id: 0x0000 - pwm id 0x01
446 10:24:19.001874 bl2_stage_init 0xc1
447 10:24:19.002332 bl2_stage_init 0x02
448 10:24:19.002779
449 10:24:19.006955 L0:00000000
450 10:24:19.007419 L1:20000703
451 10:24:19.007867 L2:00008067
452 10:24:19.008372 L3:14000000
453 10:24:19.012672 B2:00402000
454 10:24:19.013151 B1:e0f83180
455 10:24:19.013597
456 10:24:19.014041 TE: 58124
457 10:24:19.014483
458 10:24:19.018161 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
459 10:24:19.018673
460 10:24:19.019131 Board ID = 1
461 10:24:19.023754 Set A53 clk to 24M
462 10:24:19.024284 Set A73 clk to 24M
463 10:24:19.024740 Set clk81 to 24M
464 10:24:19.029332 A53 clk: 1200 MHz
465 10:24:19.029810 A73 clk: 1200 MHz
466 10:24:19.030254 CLK81: 166.6M
467 10:24:19.030692 smccc: 00012a92
468 10:24:19.034938 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
469 10:24:19.040638 board id: 1
470 10:24:19.046435 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
471 10:24:19.057056 fw parse done
472 10:24:19.063039 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
473 10:24:19.105725 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
474 10:24:19.116660 PIEI prepare done
475 10:24:19.117133 fastboot data load
476 10:24:19.117584 fastboot data verify
477 10:24:19.122156 verify result: 266
478 10:24:19.127776 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
479 10:24:19.128298 LPDDR4 probe
480 10:24:19.128748 ddr clk to 1584MHz
481 10:24:19.135742 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
482 10:24:19.172988
483 10:24:19.173464 dmc_version 0001
484 10:24:19.179742 Check phy result
485 10:24:19.185667 INFO : End of CA training
486 10:24:19.186130 INFO : End of initialization
487 10:24:19.191134 INFO : Training has run successfully!
488 10:24:19.191615 Check phy result
489 10:24:19.196741 INFO : End of initialization
490 10:24:19.197209 INFO : End of read enable training
491 10:24:19.202345 INFO : End of fine write leveling
492 10:24:19.207941 INFO : End of Write leveling coarse delay
493 10:24:19.208435 INFO : Training has run successfully!
494 10:24:19.208881 Check phy result
495 10:24:19.213531 INFO : End of initialization
496 10:24:19.213996 INFO : End of read dq deskew training
497 10:24:19.219139 INFO : End of MPR read delay center optimization
498 10:24:19.224740 INFO : End of write delay center optimization
499 10:24:19.230342 INFO : End of read delay center optimization
500 10:24:19.230807 INFO : End of max read latency training
501 10:24:19.235939 INFO : Training has run successfully!
502 10:24:19.236454 1D training succeed
503 10:24:19.245150 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
504 10:24:19.292765 Check phy result
505 10:24:19.293230 INFO : End of initialization
506 10:24:19.315301 INFO : End of 2D read delay Voltage center optimization
507 10:24:19.335541 INFO : End of 2D read delay Voltage center optimization
508 10:24:19.387663 INFO : End of 2D write delay Voltage center optimization
509 10:24:19.437150 INFO : End of 2D write delay Voltage center optimization
510 10:24:19.442575 INFO : Training has run successfully!
511 10:24:19.443059
512 10:24:19.443515 channel==0
513 10:24:19.448209 RxClkDly_Margin_A0==88 ps 9
514 10:24:19.448687 TxDqDly_Margin_A0==98 ps 10
515 10:24:19.453757 RxClkDly_Margin_A1==88 ps 9
516 10:24:19.454228 TxDqDly_Margin_A1==98 ps 10
517 10:24:19.454678 TrainedVREFDQ_A0==74
518 10:24:19.459320 TrainedVREFDQ_A1==74
519 10:24:19.459802 VrefDac_Margin_A0==25
520 10:24:19.460304 DeviceVref_Margin_A0==40
521 10:24:19.464925 VrefDac_Margin_A1==25
522 10:24:19.465392 DeviceVref_Margin_A1==40
523 10:24:19.465837
524 10:24:19.466276
525 10:24:19.470597 channel==1
526 10:24:19.471065 RxClkDly_Margin_A0==98 ps 10
527 10:24:19.471512 TxDqDly_Margin_A0==98 ps 10
528 10:24:19.476137 RxClkDly_Margin_A1==98 ps 10
529 10:24:19.476604 TxDqDly_Margin_A1==88 ps 9
530 10:24:19.481734 TrainedVREFDQ_A0==76
531 10:24:19.482206 TrainedVREFDQ_A1==77
532 10:24:19.482658 VrefDac_Margin_A0==22
533 10:24:19.487334 DeviceVref_Margin_A0==38
534 10:24:19.487799 VrefDac_Margin_A1==22
535 10:24:19.492925 DeviceVref_Margin_A1==37
536 10:24:19.493394
537 10:24:19.493838 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
538 10:24:19.498618
539 10:24:19.526595 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000019 00000017 00000018 00000016 00000018 00000015 00000018 00000019 00000018 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 0000001a 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
540 10:24:19.527132 2D training succeed
541 10:24:19.532156 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
542 10:24:19.537760 auto size-- 65535DDR cs0 size: 2048MB
543 10:24:19.538249 DDR cs1 size: 2048MB
544 10:24:19.543327 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
545 10:24:19.543816 cs0 DataBus test pass
546 10:24:19.548932 cs1 DataBus test pass
547 10:24:19.549412 cs0 AddrBus test pass
548 10:24:19.549859 cs1 AddrBus test pass
549 10:24:19.550303
550 10:24:19.554579 100bdlr_step_size ps== 420
551 10:24:19.555066 result report
552 10:24:19.560150 boot times 0Enable ddr reg access
553 10:24:19.565581 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
554 10:24:19.579072 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
555 10:24:20.152911 0.0;M3 CHK:0;cm4_sp_mode 0
556 10:24:20.153520 MVN_1=0x00000000
557 10:24:20.158332 MVN_2=0x00000000
558 10:24:20.164162 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
559 10:24:20.164678 OPS=0x10
560 10:24:20.165147 ring efuse init
561 10:24:20.165612 chipver efuse init
562 10:24:20.169722 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
563 10:24:20.175201 [0.018961 Inits done]
564 10:24:20.175682 secure task start!
565 10:24:20.176160 high task start!
566 10:24:20.179857 low task start!
567 10:24:20.180362 run into bl31
568 10:24:20.186427 NOTICE: BL31: v1.3(release):4fc40b1
569 10:24:20.194265 NOTICE: BL31: Built : 15:58:17, May 22 2019
570 10:24:20.194746 NOTICE: BL31: G12A normal boot!
571 10:24:20.219850 NOTICE: BL31: BL33 decompress pass
572 10:24:20.225412 ERROR: Error initializing runtime service opteed_fast
573 10:24:21.458593
574 10:24:21.459230
575 10:24:21.466882 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
576 10:24:21.467377
577 10:24:21.467834 Model: Libre Computer AML-A311D-CC Alta
578 10:24:21.675455 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
579 10:24:21.699061 DRAM: 2 GiB (effective 3.8 GiB)
580 10:24:21.841795 Core: 408 devices, 31 uclasses, devicetree: separate
581 10:24:21.847626 WDT: Not starting watchdog@f0d0
582 10:24:21.879764 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
583 10:24:21.892216 Loading Environment from FAT... Card did not respond to voltage select! : -110
584 10:24:21.897311 ** Bad device specification mmc 0 **
585 10:24:21.907564 Card did not respond to voltage select! : -110
586 10:24:21.915316 ** Bad device specification mmc 0 **
587 10:24:21.915800 Couldn't find partition mmc 0
588 10:24:21.923551 Card did not respond to voltage select! : -110
589 10:24:21.929185 ** Bad device specification mmc 0 **
590 10:24:21.929663 Couldn't find partition mmc 0
591 10:24:21.934133 Error: could not access storage.
592 10:24:22.276594 Net: eth0: ethernet@ff3f0000
593 10:24:22.277143 starting USB...
594 10:24:22.528527 Bus usb@ff500000: Register 3000140 NbrPorts 3
595 10:24:22.529073 Starting the controller
596 10:24:22.535503 USB XHCI 1.10
597 10:24:24.246032 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
598 10:24:24.246679 bl2_stage_init 0x01
599 10:24:24.247157 bl2_stage_init 0x81
600 10:24:24.251559 hw id: 0x0000 - pwm id 0x01
601 10:24:24.252076 bl2_stage_init 0xc1
602 10:24:24.252538 bl2_stage_init 0x02
603 10:24:24.252982
604 10:24:24.257182 L0:00000000
605 10:24:24.257663 L1:20000703
606 10:24:24.258115 L2:00008067
607 10:24:24.258560 L3:14000000
608 10:24:24.262663 B2:00402000
609 10:24:24.263137 B1:e0f83180
610 10:24:24.263585
611 10:24:24.264076 TE: 58124
612 10:24:24.264535
613 10:24:24.268312 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
614 10:24:24.268798
615 10:24:24.269250 Board ID = 1
616 10:24:24.273957 Set A53 clk to 24M
617 10:24:24.274431 Set A73 clk to 24M
618 10:24:24.274879 Set clk81 to 24M
619 10:24:24.279561 A53 clk: 1200 MHz
620 10:24:24.280063 A73 clk: 1200 MHz
621 10:24:24.280513 CLK81: 166.6M
622 10:24:24.280951 smccc: 00012a92
623 10:24:24.285102 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
624 10:24:24.290770 board id: 1
625 10:24:24.296751 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
626 10:24:24.307253 fw parse done
627 10:24:24.313186 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
628 10:24:24.355830 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
629 10:24:24.366698 PIEI prepare done
630 10:24:24.367166 fastboot data load
631 10:24:24.367617 fastboot data verify
632 10:24:24.372415 verify result: 266
633 10:24:24.377916 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
634 10:24:24.378394 LPDDR4 probe
635 10:24:24.378840 ddr clk to 1584MHz
636 10:24:24.385905 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
637 10:24:24.423344
638 10:24:24.423846 dmc_version 0001
639 10:24:24.429897 Check phy result
640 10:24:24.435734 INFO : End of CA training
641 10:24:24.436242 INFO : End of initialization
642 10:24:24.441331 INFO : Training has run successfully!
643 10:24:24.441806 Check phy result
644 10:24:24.446953 INFO : End of initialization
645 10:24:24.447426 INFO : End of read enable training
646 10:24:24.452558 INFO : End of fine write leveling
647 10:24:24.460029 INFO : End of Write leveling coarse delay
648 10:24:24.460505 INFO : Training has run successfully!
649 10:24:24.463249 Check phy result
650 10:24:24.463714 INFO : End of initialization
651 10:24:24.468828 INFO : End of read dq deskew training
652 10:24:24.469297 INFO : End of MPR read delay center optimization
653 10:24:24.474502 INFO : End of write delay center optimization
654 10:24:24.480066 INFO : End of read delay center optimization
655 10:24:24.480542 INFO : End of max read latency training
656 10:24:24.485594 INFO : Training has run successfully!
657 10:24:24.486063 1D training succeed
658 10:24:24.495355 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
659 10:24:24.542962 Check phy result
660 10:24:24.543478 INFO : End of initialization
661 10:24:24.565605 INFO : End of 2D read delay Voltage center optimization
662 10:24:24.585808 INFO : End of 2D read delay Voltage center optimization
663 10:24:24.637935 INFO : End of 2D write delay Voltage center optimization
664 10:24:24.687190 INFO : End of 2D write delay Voltage center optimization
665 10:24:24.692767 INFO : Training has run successfully!
666 10:24:24.693244
667 10:24:24.693701 channel==0
668 10:24:24.698534 RxClkDly_Margin_A0==88 ps 9
669 10:24:24.699004 TxDqDly_Margin_A0==98 ps 10
670 10:24:24.704062 RxClkDly_Margin_A1==88 ps 9
671 10:24:24.704533 TxDqDly_Margin_A1==98 ps 10
672 10:24:24.704990 TrainedVREFDQ_A0==74
673 10:24:24.709664 TrainedVREFDQ_A1==74
674 10:24:24.710149 VrefDac_Margin_A0==25
675 10:24:24.710597 DeviceVref_Margin_A0==40
676 10:24:24.715258 VrefDac_Margin_A1==25
677 10:24:24.715730 DeviceVref_Margin_A1==40
678 10:24:24.716210
679 10:24:24.716656
680 10:24:24.720767 channel==1
681 10:24:24.721238 RxClkDly_Margin_A0==98 ps 10
682 10:24:24.721686 TxDqDly_Margin_A0==88 ps 9
683 10:24:24.726532 RxClkDly_Margin_A1==88 ps 9
684 10:24:24.727005 TxDqDly_Margin_A1==88 ps 9
685 10:24:24.732077 TrainedVREFDQ_A0==76
686 10:24:24.732553 TrainedVREFDQ_A1==77
687 10:24:24.733005 VrefDac_Margin_A0==22
688 10:24:24.737625 DeviceVref_Margin_A0==38
689 10:24:24.738097 VrefDac_Margin_A1==24
690 10:24:24.743161 DeviceVref_Margin_A1==37
691 10:24:24.743626
692 10:24:24.744104 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
693 10:24:24.744553
694 10:24:24.776761 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000017 00000018 00000015 00000018 00000019 00000017 00000019 00000018 0000001a 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
695 10:24:24.777270 2D training succeed
696 10:24:24.782491 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
697 10:24:24.787944 auto size-- 65535DDR cs0 size: 2048MB
698 10:24:24.788455 DDR cs1 size: 2048MB
699 10:24:24.793544 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
700 10:24:24.794015 cs0 DataBus test pass
701 10:24:24.799165 cs1 DataBus test pass
702 10:24:24.799633 cs0 AddrBus test pass
703 10:24:24.800115 cs1 AddrBus test pass
704 10:24:24.800558
705 10:24:24.804759 100bdlr_step_size ps== 420
706 10:24:24.805234 result report
707 10:24:24.810466 boot times 0Enable ddr reg access
708 10:24:24.815639 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
709 10:24:24.829117 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
710 10:24:25.402783 0.0;M3 CHK:0;cm4_sp_mode 0
711 10:24:25.403382 MVN_1=0x00000000
712 10:24:25.408292 MVN_2=0x00000000
713 10:24:25.414190 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
714 10:24:25.414762 OPS=0x10
715 10:24:25.415207 ring efuse init
716 10:24:25.415638 chipver efuse init
717 10:24:25.422296 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
718 10:24:25.422793 [0.018961 Inits done]
719 10:24:25.429898 secure task start!
720 10:24:25.430363 high task start!
721 10:24:25.430792 low task start!
722 10:24:25.431217 run into bl31
723 10:24:25.436564 NOTICE: BL31: v1.3(release):4fc40b1
724 10:24:25.443419 NOTICE: BL31: Built : 15:58:17, May 22 2019
725 10:24:25.443896 NOTICE: BL31: G12A normal boot!
726 10:24:25.469714 NOTICE: BL31: BL33 decompress pass
727 10:24:25.474416 ERROR: Error initializing runtime service opteed_fast
728 10:24:26.708152
729 10:24:26.708781
730 10:24:26.716470 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
731 10:24:26.716958
732 10:24:26.717412 Model: Libre Computer AML-A311D-CC Alta
733 10:24:26.925019 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
734 10:24:26.948284 DRAM: 2 GiB (effective 3.8 GiB)
735 10:24:27.091349 Core: 408 devices, 31 uclasses, devicetree: separate
736 10:24:27.097149 WDT: Not starting watchdog@f0d0
737 10:24:27.129441 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
738 10:24:27.141850 Loading Environment from FAT... Card did not respond to voltage select! : -110
739 10:24:27.146833 ** Bad device specification mmc 0 **
740 10:24:27.157107 Card did not respond to voltage select! : -110
741 10:24:27.164781 ** Bad device specification mmc 0 **
742 10:24:27.165266 Couldn't find partition mmc 0
743 10:24:27.173095 Card did not respond to voltage select! : -110
744 10:24:27.178701 ** Bad device specification mmc 0 **
745 10:24:27.179188 Couldn't find partition mmc 0
746 10:24:27.183766 Error: could not access storage.
747 10:24:27.527291 Net: eth0: ethernet@ff3f0000
748 10:24:27.527869 starting USB...
749 10:24:27.779288 Bus usb@ff500000: Register 3000140 NbrPorts 3
750 10:24:27.780119 Starting the controller
751 10:24:27.786215 USB XHCI 1.10
752 10:24:29.947527 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
753 10:24:29.948328 bl2_stage_init 0x01
754 10:24:29.948891 bl2_stage_init 0x81
755 10:24:29.953164 hw id: 0x0000 - pwm id 0x01
756 10:24:29.953811 bl2_stage_init 0xc1
757 10:24:29.954365 bl2_stage_init 0x02
758 10:24:29.954909
759 10:24:29.958748 L0:00000000
760 10:24:29.959368 L1:20000703
761 10:24:29.959897 L2:00008067
762 10:24:29.960475 L3:14000000
763 10:24:29.964343 B2:00402000
764 10:24:29.964958 B1:e0f83180
765 10:24:29.965485
766 10:24:29.966017 TE: 58159
767 10:24:29.966539
768 10:24:29.969924 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
769 10:24:29.970545
770 10:24:29.971086 Board ID = 1
771 10:24:29.975539 Set A53 clk to 24M
772 10:24:29.976194 Set A73 clk to 24M
773 10:24:29.976746 Set clk81 to 24M
774 10:24:29.981139 A53 clk: 1200 MHz
775 10:24:29.981754 A73 clk: 1200 MHz
776 10:24:29.982280 CLK81: 166.6M
777 10:24:29.982808 smccc: 00012ab5
778 10:24:29.986720 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
779 10:24:29.992348 board id: 1
780 10:24:29.998228 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
781 10:24:30.008893 fw parse done
782 10:24:30.014842 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
783 10:24:30.057436 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
784 10:24:30.068436 PIEI prepare done
785 10:24:30.069071 fastboot data load
786 10:24:30.069631 fastboot data verify
787 10:24:30.073996 verify result: 266
788 10:24:30.079571 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
789 10:24:30.080229 LPDDR4 probe
790 10:24:30.080772 ddr clk to 1584MHz
791 10:24:30.087561 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
792 10:24:30.124826
793 10:24:30.125445 dmc_version 0001
794 10:24:30.131500 Check phy result
795 10:24:30.137365 INFO : End of CA training
796 10:24:30.137969 INFO : End of initialization
797 10:24:30.142957 INFO : Training has run successfully!
798 10:24:30.143564 Check phy result
799 10:24:30.148569 INFO : End of initialization
800 10:24:30.149169 INFO : End of read enable training
801 10:24:30.154187 INFO : End of fine write leveling
802 10:24:30.159740 INFO : End of Write leveling coarse delay
803 10:24:30.160391 INFO : Training has run successfully!
804 10:24:30.160924 Check phy result
805 10:24:30.165365 INFO : End of initialization
806 10:24:30.165978 INFO : End of read dq deskew training
807 10:24:30.170962 INFO : End of MPR read delay center optimization
808 10:24:30.176565 INFO : End of write delay center optimization
809 10:24:30.182182 INFO : End of read delay center optimization
810 10:24:30.182790 INFO : End of max read latency training
811 10:24:30.187768 INFO : Training has run successfully!
812 10:24:30.188417 1D training succeed
813 10:24:30.196906 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
814 10:24:30.244513 Check phy result
815 10:24:30.245120 INFO : End of initialization
816 10:24:30.266063 INFO : End of 2D read delay Voltage center optimization
817 10:24:30.286272 INFO : End of 2D read delay Voltage center optimization
818 10:24:30.338124 INFO : End of 2D write delay Voltage center optimization
819 10:24:30.388438 INFO : End of 2D write delay Voltage center optimization
820 10:24:30.393831 INFO : Training has run successfully!
821 10:24:30.394449
822 10:24:30.394978 channel==0
823 10:24:30.399440 RxClkDly_Margin_A0==88 ps 9
824 10:24:30.400088 TxDqDly_Margin_A0==98 ps 10
825 10:24:30.405058 RxClkDly_Margin_A1==88 ps 9
826 10:24:30.405677 TxDqDly_Margin_A1==98 ps 10
827 10:24:30.406249 TrainedVREFDQ_A0==74
828 10:24:30.410703 TrainedVREFDQ_A1==74
829 10:24:30.411352 VrefDac_Margin_A0==25
830 10:24:30.411901 DeviceVref_Margin_A0==40
831 10:24:30.416338 VrefDac_Margin_A1==25
832 10:24:30.416910 DeviceVref_Margin_A1==40
833 10:24:30.417351
834 10:24:30.417756
835 10:24:30.421816 channel==1
836 10:24:30.422307 RxClkDly_Margin_A0==98 ps 10
837 10:24:30.422712 TxDqDly_Margin_A0==98 ps 10
838 10:24:30.427367 RxClkDly_Margin_A1==98 ps 10
839 10:24:30.427832 TxDqDly_Margin_A1==88 ps 9
840 10:24:30.432923 TrainedVREFDQ_A0==77
841 10:24:30.433388 TrainedVREFDQ_A1==77
842 10:24:30.433788 VrefDac_Margin_A0==23
843 10:24:30.438513 DeviceVref_Margin_A0==37
844 10:24:30.438971 VrefDac_Margin_A1==22
845 10:24:30.444193 DeviceVref_Margin_A1==37
846 10:24:30.444676
847 10:24:30.445073 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
848 10:24:30.449779
849 10:24:30.477696 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000019 00000017 00000019 00000018 0000001a 0000001a 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
850 10:24:30.478189 2D training succeed
851 10:24:30.483360 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
852 10:24:30.489079 auto size-- 65535DDR cs0 size: 2048MB
853 10:24:30.489543 DDR cs1 size: 2048MB
854 10:24:30.494691 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
855 10:24:30.495152 cs0 DataBus test pass
856 10:24:30.500325 cs1 DataBus test pass
857 10:24:30.500796 cs0 AddrBus test pass
858 10:24:30.501192 cs1 AddrBus test pass
859 10:24:30.501582
860 10:24:30.505805 100bdlr_step_size ps== 420
861 10:24:30.506290 result report
862 10:24:30.511413 boot times 0Enable ddr reg access
863 10:24:30.517008 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
864 10:24:30.530472 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
865 10:24:31.102767 0.0;M3 CHK:0;cm4_sp_mode 0
866 10:24:31.103397 MVN_1=0x00000000
867 10:24:31.108048 MVN_2=0x00000000
868 10:24:31.113709 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
869 10:24:31.114189 OPS=0x10
870 10:24:31.114611 ring efuse init
871 10:24:31.115019 chipver efuse init
872 10:24:31.119224 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
873 10:24:31.124977 [0.018960 Inits done]
874 10:24:31.125448 secure task start!
875 10:24:31.125865 high task start!
876 10:24:31.129606 low task start!
877 10:24:31.130074 run into bl31
878 10:24:31.136142 NOTICE: BL31: v1.3(release):4fc40b1
879 10:24:31.144078 NOTICE: BL31: Built : 15:58:17, May 22 2019
880 10:24:31.144550 NOTICE: BL31: G12A normal boot!
881 10:24:31.169246 NOTICE: BL31: BL33 decompress pass
882 10:24:31.175003 ERROR: Error initializing runtime service opteed_fast
883 10:24:32.407697
884 10:24:32.408363
885 10:24:32.416222 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
886 10:24:32.416797
887 10:24:32.417229 Model: Libre Computer AML-A311D-CC Alta
888 10:24:32.624530 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
889 10:24:32.647809 DRAM: 2 GiB (effective 3.8 GiB)
890 10:24:32.790761 Core: 408 devices, 31 uclasses, devicetree: separate
891 10:24:32.796661 WDT: Not starting watchdog@f0d0
892 10:24:32.828884 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
893 10:24:32.841477 Loading Environment from FAT... Card did not respond to voltage select! : -110
894 10:24:32.846322 ** Bad device specification mmc 0 **
895 10:24:32.856650 Card did not respond to voltage select! : -110
896 10:24:32.864304 ** Bad device specification mmc 0 **
897 10:24:32.864758 Couldn't find partition mmc 0
898 10:24:32.872634 Card did not respond to voltage select! : -110
899 10:24:32.878163 ** Bad device specification mmc 0 **
900 10:24:32.878618 Couldn't find partition mmc 0
901 10:24:32.883223 Error: could not access storage.
902 10:24:33.226719 Net: eth0: ethernet@ff3f0000
903 10:24:33.227219 starting USB...
904 10:24:33.478550 Bus usb@ff500000: Register 3000140 NbrPorts 3
905 10:24:33.479064 Starting the controller
906 10:24:33.485551 USB XHCI 1.10
907 10:24:35.039620 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
908 10:24:35.047867 scanning usb for storage devices... 0 Storage Device(s) found
910 10:24:35.099384 Hit any key to stop autoboot: 1
911 10:24:35.100202 end: 2.4.2 bootloader-interrupt (duration 00:00:32) [common]
912 10:24:35.100844 start: 2.4.3 bootloader-commands (timeout 00:04:28) [common]
913 10:24:35.101340 Setting prompt string to ['=>']
914 10:24:35.101831 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:28)
915 10:24:35.115291 0
916 10:24:35.116195 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
917 10:24:35.116721 Sending with 10 millisecond of delay
919 10:24:36.251184 => setenv autoload no
920 10:24:36.261921 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:27)
921 10:24:36.266831 setenv autoload no
922 10:24:36.267560 Sending with 10 millisecond of delay
924 10:24:38.064480 => setenv initrd_high 0xffffffff
925 10:24:38.075270 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:25)
926 10:24:38.076118 setenv initrd_high 0xffffffff
927 10:24:38.076825 Sending with 10 millisecond of delay
929 10:24:39.692935 => setenv fdt_high 0xffffffff
930 10:24:39.703736 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:23)
931 10:24:39.704593 setenv fdt_high 0xffffffff
932 10:24:39.705321 Sending with 10 millisecond of delay
934 10:24:39.997071 => dhcp
935 10:24:40.007790 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:23)
936 10:24:40.008617 dhcp
937 10:24:40.009052 Speed: 1000, full duplex
938 10:24:40.009465 BOOTP broadcast 1
939 10:24:40.017886 DHCP client bound to address 192.168.6.27 (10 ms)
940 10:24:40.018594 Sending with 10 millisecond of delay
942 10:24:41.695085 => setenv serverip 192.168.6.2
943 10:24:41.705891 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:21)
944 10:24:41.706800 setenv serverip 192.168.6.2
945 10:24:41.707493 Sending with 10 millisecond of delay
947 10:24:45.430691 => tftpboot 0x01080000 958496/tftp-deploy-fr5ymm_5/kernel/uImage
948 10:24:45.441466 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
949 10:24:45.442264 tftpboot 0x01080000 958496/tftp-deploy-fr5ymm_5/kernel/uImage
950 10:24:45.442724 Speed: 1000, full duplex
951 10:24:45.443137 Using ethernet@ff3f0000 device
952 10:24:45.443929 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
953 10:24:45.449476 Filename '958496/tftp-deploy-fr5ymm_5/kernel/uImage'.
954 10:24:45.453345 Load address: 0x1080000
955 10:24:48.291422 Loading: *################################################## 44 MiB
956 10:24:48.292089 15.5 MiB/s
957 10:24:48.292529 done
958 10:24:48.295780 Bytes transferred = 46121536 (2bfc240 hex)
959 10:24:48.296611 Sending with 10 millisecond of delay
961 10:24:52.982206 => tftpboot 0x08000000 958496/tftp-deploy-fr5ymm_5/ramdisk/ramdisk.cpio.gz.uboot
962 10:24:52.992947 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:10)
963 10:24:52.993723 tftpboot 0x08000000 958496/tftp-deploy-fr5ymm_5/ramdisk/ramdisk.cpio.gz.uboot
964 10:24:52.994172 Speed: 1000, full duplex
965 10:24:52.994591 Using ethernet@ff3f0000 device
966 10:24:52.995484 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
967 10:24:53.007380 Filename '958496/tftp-deploy-fr5ymm_5/ramdisk/ramdisk.cpio.gz.uboot'.
968 10:24:53.007884 Load address: 0x8000000
969 10:24:59.953645 Loading: *#####################T ############################ UDP wrong checksum 00000005 000022cd
970 10:25:02.701979 UDP wrong checksum 000000ff 00001b6c
971 10:25:02.754366 UDP wrong checksum 000000ff 0000b45e
972 10:25:04.955781 T UDP wrong checksum 00000005 000022cd
973 10:25:14.957159 T UDP wrong checksum 00000005 000022cd
974 10:25:34.962398 T T T T T UDP wrong checksum 00000005 000022cd
975 10:25:49.966819 T T
976 10:25:49.967453 Retry count exceeded; starting again
978 10:25:49.968893 end: 2.4.3 bootloader-commands (duration 00:01:15) [common]
981 10:25:49.970759 end: 2.4 uboot-commands (duration 00:01:47) [common]
983 10:25:49.972271 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
985 10:25:49.973298 end: 2 uboot-action (duration 00:01:47) [common]
987 10:25:49.974791 Cleaning after the job
988 10:25:49.975326 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/958496/tftp-deploy-fr5ymm_5/ramdisk
989 10:25:49.976621 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/958496/tftp-deploy-fr5ymm_5/kernel
990 10:25:50.023034 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/958496/tftp-deploy-fr5ymm_5/dtb
991 10:25:50.023868 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/958496/tftp-deploy-fr5ymm_5/modules
992 10:25:50.046115 start: 4.1 power-off (timeout 00:00:30) [common]
993 10:25:50.046831 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
994 10:25:50.081643 >> OK - accepted request
995 10:25:50.083754 Returned 0 in 0 seconds
996 10:25:50.184705 end: 4.1 power-off (duration 00:00:00) [common]
998 10:25:50.185706 start: 4.2 read-feedback (timeout 00:10:00) [common]
999 10:25:50.186345 Listened to connection for namespace 'common' for up to 1s
1000 10:25:51.187274 Finalising connection for namespace 'common'
1001 10:25:51.187771 Disconnecting from shell: Finalise
1002 10:25:51.188115 =>
1003 10:25:51.288802 end: 4.2 read-feedback (duration 00:00:01) [common]
1004 10:25:51.289256 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/958496
1005 10:25:51.550885 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/958496
1006 10:25:51.551507 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.