Boot log: beaglebone-black
- Warnings: 2
- Kernel Warnings: 15
- Errors: 0
- Boot result: PASS
- Kernel Errors: 10
1 10:48:47.950526 lava-dispatcher, installed at version: 2024.01
2 10:48:47.951370 start: 0 validate
3 10:48:47.951885 Start time: 2024-11-11 10:48:47.951854+00:00 (UTC)
4 10:48:47.952455 Using caching service: 'http://192.168.6.3:8001/api/v1/fetch?url=%s'
5 10:48:47.953048 Validating that http://192.168.6.3:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farmhf%2Finitrd.cpio.gz exists
6 10:48:47.981546 Using caching service: 'http://192.168.6.3:8001/api/v1/fetch?url=%s'
7 10:48:47.982144 Validating that http://192.168.6.3:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241111%2Farm%2Fmulti_v7_defconfig%2Fgcc-12%2Fkernel%2FzImage exists
8 10:48:48.007810 Using caching service: 'http://192.168.6.3:8001/api/v1/fetch?url=%s'
9 10:48:48.008458 Validating that http://192.168.6.3:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241111%2Farm%2Fmulti_v7_defconfig%2Fgcc-12%2Fdtbs%2Fti%2Fomap%2Fam335x-boneblack.dtb exists
10 10:48:48.032822 Using caching service: 'http://192.168.6.3:8001/api/v1/fetch?url=%s'
11 10:48:48.033349 Validating that http://192.168.6.3:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farmhf%2Ffull.rootfs.tar.xz exists
12 10:48:48.056343 Using caching service: 'http://192.168.6.3:8001/api/v1/fetch?url=%s'
13 10:48:48.057037 Validating that http://192.168.6.3:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241111%2Farm%2Fmulti_v7_defconfig%2Fgcc-12%2Fmodules.tar.xz exists
14 10:48:48.094666 validate duration: 0.14
16 10:48:48.095786 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 10:48:48.096233 start: 1.1 download-retry (timeout 00:10:00) [common]
18 10:48:48.096655 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 10:48:48.097437 Not decompressing ramdisk as can be used compressed.
20 10:48:48.097918 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/initrd.cpio.gz
21 10:48:48.098321 saving as /var/lib/lava/dispatcher/tmp/974617/tftp-deploy-a39ntaez/ramdisk/initrd.cpio.gz
22 10:48:48.098700 total size: 4775763 (4 MB)
23 10:48:48.126793 progress 0 % (0 MB)
24 10:48:48.130777 progress 5 % (0 MB)
25 10:48:48.134568 progress 10 % (0 MB)
26 10:48:48.138248 progress 15 % (0 MB)
27 10:48:48.142689 progress 20 % (0 MB)
28 10:48:48.146328 progress 25 % (1 MB)
29 10:48:48.150254 progress 30 % (1 MB)
30 10:48:48.154777 progress 35 % (1 MB)
31 10:48:48.158488 progress 40 % (1 MB)
32 10:48:48.162542 progress 45 % (2 MB)
33 10:48:48.166158 progress 50 % (2 MB)
34 10:48:48.170397 progress 55 % (2 MB)
35 10:48:48.174194 progress 60 % (2 MB)
36 10:48:48.177788 progress 65 % (2 MB)
37 10:48:48.181938 progress 70 % (3 MB)
38 10:48:48.185505 progress 75 % (3 MB)
39 10:48:48.189026 progress 80 % (3 MB)
40 10:48:48.192617 progress 85 % (3 MB)
41 10:48:48.196620 progress 90 % (4 MB)
42 10:48:48.200008 progress 95 % (4 MB)
43 10:48:48.203110 progress 100 % (4 MB)
44 10:48:48.203760 4 MB downloaded in 0.11 s (43.36 MB/s)
45 10:48:48.204342 end: 1.1.1 http-download (duration 00:00:00) [common]
47 10:48:48.205297 end: 1.1 download-retry (duration 00:00:00) [common]
48 10:48:48.205643 start: 1.2 download-retry (timeout 00:10:00) [common]
49 10:48:48.205989 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 10:48:48.206452 downloading http://storage.kernelci.org/next/master/next-20241111/arm/multi_v7_defconfig/gcc-12/kernel/zImage
51 10:48:48.206718 saving as /var/lib/lava/dispatcher/tmp/974617/tftp-deploy-a39ntaez/kernel/zImage
52 10:48:48.206958 total size: 11510272 (10 MB)
53 10:48:48.207196 No compression specified
54 10:48:48.235348 progress 0 % (0 MB)
55 10:48:48.242756 progress 5 % (0 MB)
56 10:48:48.250483 progress 10 % (1 MB)
57 10:48:48.257717 progress 15 % (1 MB)
58 10:48:48.265616 progress 20 % (2 MB)
59 10:48:48.272971 progress 25 % (2 MB)
60 10:48:48.280694 progress 30 % (3 MB)
61 10:48:48.290135 progress 35 % (3 MB)
62 10:48:48.298149 progress 40 % (4 MB)
63 10:48:48.305937 progress 45 % (4 MB)
64 10:48:48.313285 progress 50 % (5 MB)
65 10:48:48.321285 progress 55 % (6 MB)
66 10:48:48.328632 progress 60 % (6 MB)
67 10:48:48.336338 progress 65 % (7 MB)
68 10:48:48.344336 progress 70 % (7 MB)
69 10:48:48.352405 progress 75 % (8 MB)
70 10:48:48.360470 progress 80 % (8 MB)
71 10:48:48.367887 progress 85 % (9 MB)
72 10:48:48.375732 progress 90 % (9 MB)
73 10:48:48.383115 progress 95 % (10 MB)
74 10:48:48.390560 progress 100 % (10 MB)
75 10:48:48.391104 10 MB downloaded in 0.18 s (59.61 MB/s)
76 10:48:48.391602 end: 1.2.1 http-download (duration 00:00:00) [common]
78 10:48:48.392443 end: 1.2 download-retry (duration 00:00:00) [common]
79 10:48:48.392740 start: 1.3 download-retry (timeout 00:10:00) [common]
80 10:48:48.393019 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 10:48:48.393518 downloading http://storage.kernelci.org/next/master/next-20241111/arm/multi_v7_defconfig/gcc-12/dtbs/ti/omap/am335x-boneblack.dtb
82 10:48:48.393786 saving as /var/lib/lava/dispatcher/tmp/974617/tftp-deploy-a39ntaez/dtb/am335x-boneblack.dtb
83 10:48:48.394026 total size: 70544 (0 MB)
84 10:48:48.394248 No compression specified
85 10:48:48.425378 progress 46 % (0 MB)
86 10:48:48.426471 progress 92 % (0 MB)
87 10:48:48.427302 progress 100 % (0 MB)
88 10:48:48.427781 0 MB downloaded in 0.03 s (1.99 MB/s)
89 10:48:48.428360 end: 1.3.1 http-download (duration 00:00:00) [common]
91 10:48:48.429403 end: 1.3 download-retry (duration 00:00:00) [common]
92 10:48:48.429747 start: 1.4 download-retry (timeout 00:10:00) [common]
93 10:48:48.430130 start: 1.4.1 http-download (timeout 00:10:00) [common]
94 10:48:48.430716 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/full.rootfs.tar.xz
95 10:48:48.431054 saving as /var/lib/lava/dispatcher/tmp/974617/tftp-deploy-a39ntaez/nfsrootfs/full.rootfs.tar
96 10:48:48.431319 total size: 117747780 (112 MB)
97 10:48:48.431586 Using unxz to decompress xz
98 10:48:48.460901 progress 0 % (0 MB)
99 10:48:49.199297 progress 5 % (5 MB)
100 10:48:49.947969 progress 10 % (11 MB)
101 10:48:50.727917 progress 15 % (16 MB)
102 10:48:51.497365 progress 20 % (22 MB)
103 10:48:52.070619 progress 25 % (28 MB)
104 10:48:52.864597 progress 30 % (33 MB)
105 10:48:53.660227 progress 35 % (39 MB)
106 10:48:54.008380 progress 40 % (44 MB)
107 10:48:54.408397 progress 45 % (50 MB)
108 10:48:55.231741 progress 50 % (56 MB)
109 10:48:56.216057 progress 55 % (61 MB)
110 10:48:57.099513 progress 60 % (67 MB)
111 10:48:57.966896 progress 65 % (73 MB)
112 10:48:58.741498 progress 70 % (78 MB)
113 10:48:59.497248 progress 75 % (84 MB)
114 10:49:00.228883 progress 80 % (89 MB)
115 10:49:00.949280 progress 85 % (95 MB)
116 10:49:01.742710 progress 90 % (101 MB)
117 10:49:02.523694 progress 95 % (106 MB)
118 10:49:03.338997 progress 100 % (112 MB)
119 10:49:03.351649 112 MB downloaded in 14.92 s (7.53 MB/s)
120 10:49:03.352928 end: 1.4.1 http-download (duration 00:00:15) [common]
122 10:49:03.355565 end: 1.4 download-retry (duration 00:00:15) [common]
123 10:49:03.356128 start: 1.5 download-retry (timeout 00:09:45) [common]
124 10:49:03.356690 start: 1.5.1 http-download (timeout 00:09:45) [common]
125 10:49:03.358249 downloading http://storage.kernelci.org/next/master/next-20241111/arm/multi_v7_defconfig/gcc-12/modules.tar.xz
126 10:49:03.359261 saving as /var/lib/lava/dispatcher/tmp/974617/tftp-deploy-a39ntaez/modules/modules.tar
127 10:49:03.359686 total size: 6626848 (6 MB)
128 10:49:03.360389 Using unxz to decompress xz
129 10:49:03.401363 progress 0 % (0 MB)
130 10:49:03.438358 progress 5 % (0 MB)
131 10:49:03.483228 progress 10 % (0 MB)
132 10:49:03.527466 progress 15 % (0 MB)
133 10:49:03.572043 progress 20 % (1 MB)
134 10:49:03.620530 progress 25 % (1 MB)
135 10:49:03.664340 progress 30 % (1 MB)
136 10:49:03.707122 progress 35 % (2 MB)
137 10:49:03.751940 progress 40 % (2 MB)
138 10:49:03.802301 progress 45 % (2 MB)
139 10:49:03.847566 progress 50 % (3 MB)
140 10:49:03.889764 progress 55 % (3 MB)
141 10:49:03.935634 progress 60 % (3 MB)
142 10:49:03.978161 progress 65 % (4 MB)
143 10:49:04.021750 progress 70 % (4 MB)
144 10:49:04.069409 progress 75 % (4 MB)
145 10:49:04.113170 progress 80 % (5 MB)
146 10:49:04.155887 progress 85 % (5 MB)
147 10:49:04.203871 progress 90 % (5 MB)
148 10:49:04.250090 progress 95 % (6 MB)
149 10:49:04.294311 progress 100 % (6 MB)
150 10:49:04.305372 6 MB downloaded in 0.95 s (6.68 MB/s)
151 10:49:04.306202 end: 1.5.1 http-download (duration 00:00:01) [common]
153 10:49:04.308012 end: 1.5 download-retry (duration 00:00:01) [common]
154 10:49:04.308589 start: 1.6 prepare-tftp-overlay (timeout 00:09:44) [common]
155 10:49:04.309154 start: 1.6.1 extract-nfsrootfs (timeout 00:09:44) [common]
156 10:49:21.295431 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/974617/extract-nfsrootfs-esptk5zt
157 10:49:21.296024 end: 1.6.1 extract-nfsrootfs (duration 00:00:17) [common]
158 10:49:21.296345 start: 1.6.2 lava-overlay (timeout 00:09:27) [common]
159 10:49:21.296968 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/974617/lava-overlay-g20c2579
160 10:49:21.297406 makedir: /var/lib/lava/dispatcher/tmp/974617/lava-overlay-g20c2579/lava-974617/bin
161 10:49:21.297754 makedir: /var/lib/lava/dispatcher/tmp/974617/lava-overlay-g20c2579/lava-974617/tests
162 10:49:21.298143 makedir: /var/lib/lava/dispatcher/tmp/974617/lava-overlay-g20c2579/lava-974617/results
163 10:49:21.298481 Creating /var/lib/lava/dispatcher/tmp/974617/lava-overlay-g20c2579/lava-974617/bin/lava-add-keys
164 10:49:21.299048 Creating /var/lib/lava/dispatcher/tmp/974617/lava-overlay-g20c2579/lava-974617/bin/lava-add-sources
165 10:49:21.299604 Creating /var/lib/lava/dispatcher/tmp/974617/lava-overlay-g20c2579/lava-974617/bin/lava-background-process-start
166 10:49:21.300183 Creating /var/lib/lava/dispatcher/tmp/974617/lava-overlay-g20c2579/lava-974617/bin/lava-background-process-stop
167 10:49:21.300735 Creating /var/lib/lava/dispatcher/tmp/974617/lava-overlay-g20c2579/lava-974617/bin/lava-common-functions
168 10:49:21.301283 Creating /var/lib/lava/dispatcher/tmp/974617/lava-overlay-g20c2579/lava-974617/bin/lava-echo-ipv4
169 10:49:21.301952 Creating /var/lib/lava/dispatcher/tmp/974617/lava-overlay-g20c2579/lava-974617/bin/lava-install-packages
170 10:49:21.302470 Creating /var/lib/lava/dispatcher/tmp/974617/lava-overlay-g20c2579/lava-974617/bin/lava-installed-packages
171 10:49:21.302992 Creating /var/lib/lava/dispatcher/tmp/974617/lava-overlay-g20c2579/lava-974617/bin/lava-os-build
172 10:49:21.303539 Creating /var/lib/lava/dispatcher/tmp/974617/lava-overlay-g20c2579/lava-974617/bin/lava-probe-channel
173 10:49:21.304059 Creating /var/lib/lava/dispatcher/tmp/974617/lava-overlay-g20c2579/lava-974617/bin/lava-probe-ip
174 10:49:21.304574 Creating /var/lib/lava/dispatcher/tmp/974617/lava-overlay-g20c2579/lava-974617/bin/lava-target-ip
175 10:49:21.305064 Creating /var/lib/lava/dispatcher/tmp/974617/lava-overlay-g20c2579/lava-974617/bin/lava-target-mac
176 10:49:21.305549 Creating /var/lib/lava/dispatcher/tmp/974617/lava-overlay-g20c2579/lava-974617/bin/lava-target-storage
177 10:49:21.306114 Creating /var/lib/lava/dispatcher/tmp/974617/lava-overlay-g20c2579/lava-974617/bin/lava-test-case
178 10:49:21.306676 Creating /var/lib/lava/dispatcher/tmp/974617/lava-overlay-g20c2579/lava-974617/bin/lava-test-event
179 10:49:21.307222 Creating /var/lib/lava/dispatcher/tmp/974617/lava-overlay-g20c2579/lava-974617/bin/lava-test-feedback
180 10:49:21.307757 Creating /var/lib/lava/dispatcher/tmp/974617/lava-overlay-g20c2579/lava-974617/bin/lava-test-raise
181 10:49:21.308305 Creating /var/lib/lava/dispatcher/tmp/974617/lava-overlay-g20c2579/lava-974617/bin/lava-test-reference
182 10:49:21.308815 Creating /var/lib/lava/dispatcher/tmp/974617/lava-overlay-g20c2579/lava-974617/bin/lava-test-runner
183 10:49:21.309312 Creating /var/lib/lava/dispatcher/tmp/974617/lava-overlay-g20c2579/lava-974617/bin/lava-test-set
184 10:49:21.309789 Creating /var/lib/lava/dispatcher/tmp/974617/lava-overlay-g20c2579/lava-974617/bin/lava-test-shell
185 10:49:21.310315 Updating /var/lib/lava/dispatcher/tmp/974617/lava-overlay-g20c2579/lava-974617/bin/lava-add-keys (debian)
186 10:49:21.310869 Updating /var/lib/lava/dispatcher/tmp/974617/lava-overlay-g20c2579/lava-974617/bin/lava-add-sources (debian)
187 10:49:21.311403 Updating /var/lib/lava/dispatcher/tmp/974617/lava-overlay-g20c2579/lava-974617/bin/lava-install-packages (debian)
188 10:49:21.311937 Updating /var/lib/lava/dispatcher/tmp/974617/lava-overlay-g20c2579/lava-974617/bin/lava-installed-packages (debian)
189 10:49:21.312468 Updating /var/lib/lava/dispatcher/tmp/974617/lava-overlay-g20c2579/lava-974617/bin/lava-os-build (debian)
190 10:49:21.312923 Creating /var/lib/lava/dispatcher/tmp/974617/lava-overlay-g20c2579/lava-974617/environment
191 10:49:21.313301 LAVA metadata
192 10:49:21.313559 - LAVA_JOB_ID=974617
193 10:49:21.313773 - LAVA_DISPATCHER_IP=192.168.6.3
194 10:49:21.314169 start: 1.6.2.1 ssh-authorize (timeout 00:09:27) [common]
195 10:49:21.315196 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
196 10:49:21.315552 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:27) [common]
197 10:49:21.315763 skipped lava-vland-overlay
198 10:49:21.316007 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
199 10:49:21.316278 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:27) [common]
200 10:49:21.316522 skipped lava-multinode-overlay
201 10:49:21.316770 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
202 10:49:21.317025 start: 1.6.2.4 test-definition (timeout 00:09:27) [common]
203 10:49:21.317283 Loading test definitions
204 10:49:21.317561 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:27) [common]
205 10:49:21.317803 Using /lava-974617 at stage 0
206 10:49:21.319024 uuid=974617_1.6.2.4.1 testdef=None
207 10:49:21.319341 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
208 10:49:21.319604 start: 1.6.2.4.2 test-overlay (timeout 00:09:27) [common]
209 10:49:21.321244 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
211 10:49:21.322070 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:27) [common]
212 10:49:21.324109 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
214 10:49:21.325009 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:27) [common]
215 10:49:21.327108 runner path: /var/lib/lava/dispatcher/tmp/974617/lava-overlay-g20c2579/lava-974617/0/tests/0_timesync-off test_uuid 974617_1.6.2.4.1
216 10:49:21.327757 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
218 10:49:21.328634 start: 1.6.2.4.5 git-repo-action (timeout 00:09:27) [common]
219 10:49:21.328873 Using /lava-974617 at stage 0
220 10:49:21.329276 Fetching tests from https://github.com/kernelci/test-definitions.git
221 10:49:21.329588 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/974617/lava-overlay-g20c2579/lava-974617/0/tests/1_kselftest-dt'
222 10:49:24.783879 Running '/usr/bin/git checkout kernelci.org
223 10:49:25.242342 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/974617/lava-overlay-g20c2579/lava-974617/0/tests/1_kselftest-dt/automated/linux/kselftest/kselftest.yaml
224 10:49:25.243828 uuid=974617_1.6.2.4.5 testdef=None
225 10:49:25.244212 end: 1.6.2.4.5 git-repo-action (duration 00:00:04) [common]
227 10:49:25.244971 start: 1.6.2.4.6 test-overlay (timeout 00:09:23) [common]
228 10:49:25.250134 end: 1.6.2.4.6 test-overlay (duration 00:00:00) [common]
230 10:49:25.251918 start: 1.6.2.4.7 test-install-overlay (timeout 00:09:23) [common]
231 10:49:25.259969 end: 1.6.2.4.7 test-install-overlay (duration 00:00:00) [common]
233 10:49:25.261878 start: 1.6.2.4.8 test-runscript-overlay (timeout 00:09:23) [common]
234 10:49:25.269775 runner path: /var/lib/lava/dispatcher/tmp/974617/lava-overlay-g20c2579/lava-974617/0/tests/1_kselftest-dt test_uuid 974617_1.6.2.4.5
235 10:49:25.270440 BOARD='beaglebone-black'
236 10:49:25.270903 BRANCH='next'
237 10:49:25.271341 SKIPFILE='/dev/null'
238 10:49:25.271777 SKIP_INSTALL='True'
239 10:49:25.272211 TESTPROG_URL='http://storage.kernelci.org/next/master/next-20241111/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz'
240 10:49:25.272651 TST_CASENAME=''
241 10:49:25.273084 TST_CMDFILES='dt'
242 10:49:25.274260 end: 1.6.2.4.8 test-runscript-overlay (duration 00:00:00) [common]
244 10:49:25.275992 Creating lava-test-runner.conf files
245 10:49:25.276440 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/974617/lava-overlay-g20c2579/lava-974617/0 for stage 0
246 10:49:25.277162 - 0_timesync-off
247 10:49:25.277672 - 1_kselftest-dt
248 10:49:25.278415 end: 1.6.2.4 test-definition (duration 00:00:04) [common]
249 10:49:25.279017 start: 1.6.2.5 compress-overlay (timeout 00:09:23) [common]
250 10:49:49.083285 end: 1.6.2.5 compress-overlay (duration 00:00:24) [common]
251 10:49:49.083706 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:08:59) [common]
252 10:49:49.083978 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
253 10:49:49.084249 end: 1.6.2 lava-overlay (duration 00:00:28) [common]
254 10:49:49.084512 start: 1.6.3 extract-overlay-ramdisk (timeout 00:08:59) [common]
255 10:49:49.446643 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
256 10:49:49.447119 start: 1.6.4 extract-modules (timeout 00:08:59) [common]
257 10:49:49.447401 extracting modules file /var/lib/lava/dispatcher/tmp/974617/tftp-deploy-a39ntaez/modules/modules.tar to /var/lib/lava/dispatcher/tmp/974617/extract-nfsrootfs-esptk5zt
258 10:49:50.337658 extracting modules file /var/lib/lava/dispatcher/tmp/974617/tftp-deploy-a39ntaez/modules/modules.tar to /var/lib/lava/dispatcher/tmp/974617/extract-overlay-ramdisk-rc3bke_o/ramdisk
259 10:49:51.254199 end: 1.6.4 extract-modules (duration 00:00:02) [common]
260 10:49:51.254660 start: 1.6.5 apply-overlay-tftp (timeout 00:08:57) [common]
261 10:49:51.254937 [common] Applying overlay to NFS
262 10:49:51.255153 [common] Applying overlay /var/lib/lava/dispatcher/tmp/974617/compress-overlay-2oejagb6/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/974617/extract-nfsrootfs-esptk5zt
263 10:49:54.062028 end: 1.6.5 apply-overlay-tftp (duration 00:00:03) [common]
264 10:49:54.062550 start: 1.6.6 prepare-kernel (timeout 00:08:54) [common]
265 10:49:54.062837 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:08:54) [common]
266 10:49:54.063183 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
267 10:49:54.063448 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
268 10:49:54.063781 start: 1.6.7 configure-preseed-file (timeout 00:08:54) [common]
269 10:49:54.064094 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
270 10:49:54.064364 start: 1.6.8 compress-ramdisk (timeout 00:08:54) [common]
271 10:49:54.064592 Building ramdisk /var/lib/lava/dispatcher/tmp/974617/extract-overlay-ramdisk-rc3bke_o/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/974617/extract-overlay-ramdisk-rc3bke_o/ramdisk
272 10:49:55.084602 >> 75320 blocks
273 10:49:59.673246 Adding RAMdisk u-boot header.
274 10:49:59.673856 mkimage -A arm -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/974617/extract-overlay-ramdisk-rc3bke_o/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/974617/extract-overlay-ramdisk-rc3bke_o/ramdisk.cpio.gz.uboot
275 10:49:59.858975 output: Image Name:
276 10:49:59.859433 output: Created: Mon Nov 11 10:49:59 2024
277 10:49:59.859925 output: Image Type: ARM Linux RAMDisk Image (uncompressed)
278 10:49:59.860386 output: Data Size: 14831631 Bytes = 14484.01 KiB = 14.14 MiB
279 10:49:59.860835 output: Load Address: 00000000
280 10:49:59.861275 output: Entry Point: 00000000
281 10:49:59.861751 output:
282 10:49:59.863009 rename /var/lib/lava/dispatcher/tmp/974617/extract-overlay-ramdisk-rc3bke_o/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/974617/tftp-deploy-a39ntaez/ramdisk/ramdisk.cpio.gz.uboot
283 10:49:59.863764 end: 1.6.8 compress-ramdisk (duration 00:00:06) [common]
284 10:49:59.864187 end: 1.6 prepare-tftp-overlay (duration 00:00:56) [common]
285 10:49:59.864522 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:48) [common]
286 10:49:59.864808 No LXC device requested
287 10:49:59.865127 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
288 10:49:59.865430 start: 1.8 deploy-device-env (timeout 00:08:48) [common]
289 10:49:59.865705 end: 1.8 deploy-device-env (duration 00:00:00) [common]
290 10:49:59.865965 Checking files for TFTP limit of 4294967296 bytes.
291 10:49:59.867592 end: 1 tftp-deploy (duration 00:01:12) [common]
292 10:49:59.868097 start: 2 uboot-action (timeout 00:05:00) [common]
293 10:49:59.868760 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
294 10:49:59.869472 end: 2.1 uboot-from-media (duration 00:00:00) [common]
295 10:49:59.870163 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
296 10:49:59.871099 substitutions:
297 10:49:59.871631 - {BOOTX}: bootz 0x82000000 0x83000000 0x88000000
298 10:49:59.872106 - {DTB_ADDR}: 0x88000000
299 10:49:59.872571 - {DTB}: 974617/tftp-deploy-a39ntaez/dtb/am335x-boneblack.dtb
300 10:49:59.872856 - {INITRD}: 974617/tftp-deploy-a39ntaez/ramdisk/ramdisk.cpio.gz.uboot
301 10:49:59.873076 - {KERNEL_ADDR}: 0x82000000
302 10:49:59.873285 - {KERNEL}: 974617/tftp-deploy-a39ntaez/kernel/zImage
303 10:49:59.873491 - {LAVA_MAC}: None
304 10:49:59.873751 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/974617/extract-nfsrootfs-esptk5zt
305 10:49:59.874042 - {NFS_SERVER_IP}: 192.168.6.3
306 10:49:59.874266 - {PRESEED_CONFIG}: None
307 10:49:59.874479 - {PRESEED_LOCAL}: None
308 10:49:59.874692 - {RAMDISK_ADDR}: 0x83000000
309 10:49:59.874908 - {RAMDISK}: 974617/tftp-deploy-a39ntaez/ramdisk/ramdisk.cpio.gz.uboot
310 10:49:59.875124 - {ROOT_PART}: None
311 10:49:59.875330 - {ROOT}: None
312 10:49:59.875757 - {SERVER_IP}: 192.168.6.3
313 10:49:59.876375 - {TEE_ADDR}: 0x83000000
314 10:49:59.876868 - {TEE}: None
315 10:49:59.877336 Parsed boot commands:
316 10:49:59.877795 - setenv autoload no
317 10:49:59.878306 - setenv initrd_high 0xffffffff
318 10:49:59.878822 - setenv fdt_high 0xffffffff
319 10:49:59.879307 - dhcp
320 10:49:59.879752 - setenv serverip 192.168.6.3
321 10:49:59.880231 - tftp 0x82000000 974617/tftp-deploy-a39ntaez/kernel/zImage
322 10:49:59.880695 - tftp 0x83000000 974617/tftp-deploy-a39ntaez/ramdisk/ramdisk.cpio.gz.uboot
323 10:49:59.881169 - setenv initrd_size ${filesize}
324 10:49:59.881586 - tftp 0x88000000 974617/tftp-deploy-a39ntaez/dtb/am335x-boneblack.dtb
325 10:49:59.882030 - setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.3:/var/lib/lava/dispatcher/tmp/974617/extract-nfsrootfs-esptk5zt,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
326 10:49:59.882496 - bootz 0x82000000 0x83000000 0x88000000
327 10:49:59.883129 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
329 10:49:59.884739 start: 2.3 connect-device (timeout 00:05:00) [common]
330 10:49:59.885264 [common] connect-device Connecting to device using 'telnet conserv3 3000'
331 10:49:59.901029 Setting prompt string to ['lava-test: # ']
332 10:49:59.902645 end: 2.3 connect-device (duration 00:00:00) [common]
333 10:49:59.903324 start: 2.4 uboot-commands (timeout 00:05:00) [common]
334 10:49:59.903892 start: 2.4.1 reset-device (timeout 00:05:00) [common]
335 10:49:59.904448 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
336 10:49:59.905678 Calling: 'curl' 'http://conserv3.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=beaglebone-black-03'
337 10:49:59.940935 >> OK - accepted request
338 10:49:59.943027 Returned 0 in 0 seconds
339 10:50:00.044261 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
341 10:50:00.046449 end: 2.4.1 reset-device (duration 00:00:00) [common]
342 10:50:00.047498 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
343 10:50:00.048259 Setting prompt string to ['Hit any key to stop autoboot']
344 10:50:00.048934 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
345 10:50:00.050949 Trying 192.168.56.22...
346 10:50:00.051647 Connected to conserv3.
347 10:50:00.052377 Escape character is '^]'.
348 10:50:00.052962
349 10:50:00.053515 ser2net port telnet,3000 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.2.3:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
350 10:50:00.054141
351 10:50:07.721785
352 10:50:07.727375 U-Boot SPL 2023.01-rc4-00025-gb92e12ac87 (Dec 26 2022 - 18:25:48 +0000)
353 10:50:07.727682 Trying to boot from MMC1
354 10:50:08.314884
355 10:50:08.315315
356 10:50:08.320276 U-Boot 2023.01-rc4-00025-gb92e12ac87 (Dec 26 2022 - 18:25:48 +0000)
357 10:50:08.320566
358 10:50:08.320788 CPU : AM335X-GP rev 2.0
359 10:50:08.325374 Model: TI AM335x BeagleBone Black
360 10:50:08.325636 DRAM: 512 MiB
361 10:50:11.771493
362 10:50:11.778445 U-Boot SPL 2023.01-rc4-00025-gb92e12ac87 (Dec 26 2022 - 18:25:48 +0000)
363 10:50:11.778742 Trying to boot from MMC1
364 10:50:12.364609
365 10:50:12.365305
366 10:50:12.370076 U-Boot 2023.01-rc4-00025-gb92e12ac87 (Dec 26 2022 - 18:25:48 +0000)
367 10:50:12.370621
368 10:50:12.371071 CPU : AM335X-GP rev 2.0
369 10:50:12.375263 Model: TI AM335x BeagleBone Black
370 10:50:12.375737 DRAM: 512 MiB
371 10:50:14.473715
372 10:50:14.481067 U-Boot SPL 2023.01-rc4-00025-gb92e12ac87 (Dec 26 2022 - 18:25:48 +0000)
373 10:50:14.482162 Trying to boot from MMC1
374 10:50:15.066812
375 10:50:15.067444
376 10:50:15.072177 U-Boot 2023.01-rc4-00025-gb92e12ac87 (Dec 26 2022 - 18:25:48 +0000)
377 10:50:15.072652
378 10:50:15.073083 CPU : AM335X-GP rev 2.0
379 10:50:15.077313 Model: TI AM335x BeagleBone Black
380 10:50:15.077778 DRAM: 512 MiB
381 10:50:15.161005 Core: 160 devices, 18 uclasses, devicetree: separate
382 10:50:15.175848 WDT: Started wdt@44e35000 with servicing every 1000ms (60s timeout)
383 10:50:15.576566 NAND: 0 MiB
384 10:50:15.586667 MMC: OMAP SD/MMC: 0, OMAP SD/MMC: 1
385 10:50:15.661226 Loading Environment from FAT... Unable to read "uboot.env" from mmc0:1...
386 10:50:15.682586 <ethaddr> not set. Validating first E-fuse MAC
387 10:50:15.712069 Net: eth2: ethernet@4a100000, eth3: usb_ether
389 10:50:15.770657 Hit any key to stop autoboot: 2
390 10:50:15.771527 end: 2.4.2 bootloader-interrupt (duration 00:00:16) [common]
391 10:50:15.771926 start: 2.4.3 bootloader-commands (timeout 00:04:44) [common]
392 10:50:15.772241 Setting prompt string to ['=>']
393 10:50:15.772630 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:44)
394 10:50:15.780663 0
395 10:50:15.781369 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
396 10:50:15.781707 Sending with 10 millisecond of delay
398 10:50:16.916811 => setenv autoload no
399 10:50:16.927675 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:43)
400 10:50:16.932883 setenv autoload no
401 10:50:16.933760 Sending with 10 millisecond of delay
403 10:50:18.732146 => setenv initrd_high 0xffffffff
404 10:50:18.742958 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
405 10:50:18.743834 setenv initrd_high 0xffffffff
406 10:50:18.744549 Sending with 10 millisecond of delay
408 10:50:20.361748 => setenv fdt_high 0xffffffff
409 10:50:20.372745 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:39)
410 10:50:20.373685 setenv fdt_high 0xffffffff
411 10:50:20.374499 Sending with 10 millisecond of delay
413 10:50:20.666406 => dhcp
414 10:50:20.677184 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:39)
415 10:50:20.678120 dhcp
416 10:50:20.678604 link up on port 0, speed 100, full duplex
417 10:50:20.679054 BOOTP broadcast 1
418 10:50:20.931246 BOOTP broadcast 2
419 10:50:21.433033 BOOTP broadcast 3
420 10:50:22.435768 BOOTP broadcast 4
421 10:50:24.439167 BOOTP broadcast 5
422 10:50:24.524402 DHCP client bound to address 192.168.6.23 (3842 ms)
423 10:50:24.525245 Sending with 10 millisecond of delay
425 10:50:26.210798 => setenv serverip 192.168.6.3
426 10:50:26.221652 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:34)
427 10:50:26.222636 setenv serverip 192.168.6.3
428 10:50:26.223409 Sending with 10 millisecond of delay
430 10:50:29.707759 => tftp 0x82000000 974617/tftp-deploy-a39ntaez/kernel/zImage
431 10:50:29.718598 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:30)
432 10:50:29.719493 tftp 0x82000000 974617/tftp-deploy-a39ntaez/kernel/zImage
433 10:50:29.719922 link up on port 0, speed 100, full duplex
434 10:50:29.723712 Using ethernet@4a100000 device
435 10:50:29.729206 TFTP from server 192.168.6.3; our IP address is 192.168.6.23
436 10:50:29.729669 Filename '974617/tftp-deploy-a39ntaez/kernel/zImage'.
437 10:50:29.735416 Load address: 0x82000000
438 10:50:31.709660 Loading: *################################################## 11 MiB
439 10:50:31.710090 5.6 MiB/s
440 10:50:31.710316 done
441 10:50:31.713643 Bytes transferred = 11510272 (afa200 hex)
442 10:50:31.714187 Sending with 10 millisecond of delay
444 10:50:36.161051 => tftp 0x83000000 974617/tftp-deploy-a39ntaez/ramdisk/ramdisk.cpio.gz.uboot
445 10:50:36.172015 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:24)
446 10:50:36.172852 tftp 0x83000000 974617/tftp-deploy-a39ntaez/ramdisk/ramdisk.cpio.gz.uboot
447 10:50:36.173288 link up on port 0, speed 100, full duplex
448 10:50:36.176947 Using ethernet@4a100000 device
449 10:50:36.182340 TFTP from server 192.168.6.3; our IP address is 192.168.6.23
450 10:50:36.191104 Filename '974617/tftp-deploy-a39ntaez/ramdisk/ramdisk.cpio.gz.uboot'.
451 10:50:36.191572 Load address: 0x83000000
452 10:50:39.042593 Loading: *################################################## 14.1 MiB
453 10:50:39.043234 5 MiB/s
454 10:50:39.043703 done
455 10:50:39.046063 Bytes transferred = 14831695 (e2504f hex)
456 10:50:39.046873 Sending with 10 millisecond of delay
458 10:50:40.905462 => setenv initrd_size ${filesize}
459 10:50:40.916354 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:19)
460 10:50:40.916862 setenv initrd_size ${filesize}
461 10:50:40.917332 Sending with 10 millisecond of delay
463 10:50:45.064052 => tftp 0x88000000 974617/tftp-deploy-a39ntaez/dtb/am335x-boneblack.dtb
464 10:50:45.074860 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:15)
465 10:50:45.075733 tftp 0x88000000 974617/tftp-deploy-a39ntaez/dtb/am335x-boneblack.dtb
466 10:50:45.076162 link up on port 0, speed 100, full duplex
467 10:50:45.079611 Using ethernet@4a100000 device
468 10:50:45.085511 TFTP from server 192.168.6.3; our IP address is 192.168.6.23
469 10:50:45.092626 Filename '974617/tftp-deploy-a39ntaez/dtb/am335x-boneblack.dtb'.
470 10:50:45.093059 Load address: 0x88000000
471 10:50:45.105665 Loading: *################################################## 68.9 KiB
472 10:50:45.114435 4.5 MiB/s
473 10:50:45.114983 done
474 10:50:45.115385 Bytes transferred = 70544 (11390 hex)
475 10:50:45.116094 Sending with 10 millisecond of delay
477 10:50:58.301927 => setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.3:/var/lib/lava/dispatcher/tmp/974617/extract-nfsrootfs-esptk5zt,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
478 10:50:58.312781 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:02)
479 10:50:58.313782 setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.3:/var/lib/lava/dispatcher/tmp/974617/extract-nfsrootfs-esptk5zt,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
480 10:50:58.314547 Sending with 10 millisecond of delay
482 10:51:00.653012 => bootz 0x82000000 0x83000000 0x88000000
483 10:51:00.663810 Setting prompt string to ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
484 10:51:00.664335 bootloader-commands: Wait for prompt ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:03:59)
485 10:51:00.665317 bootz 0x82000000 0x83000000 0x88000000
486 10:51:00.665755 Kernel image @ 0x82000000 [ 0x000000 - 0xafa200 ]
487 10:51:00.666299 ## Loading init Ramdisk from Legacy Image at 83000000 ...
488 10:51:00.671190 Image Name:
489 10:51:00.671623 Created: 2024-11-11 10:49:59 UTC
490 10:51:00.680078 Image Type: ARM Linux RAMDisk Image (uncompressed)
491 10:51:00.680515 Data Size: 14831631 Bytes = 14.1 MiB
492 10:51:00.688491 Load Address: 00000000
493 10:51:00.688923 Entry Point: 00000000
494 10:51:00.857302 Verifying Checksum ... OK
495 10:51:00.857774 ## Flattened Device Tree blob at 88000000
496 10:51:00.863824 Booting using the fdt blob at 0x88000000
497 10:51:00.864260 Working FDT set to 88000000
498 10:51:00.869385 Using Device Tree in place at 88000000, end 8801438f
499 10:51:00.873895 Working FDT set to 88000000
500 10:51:00.886947
501 10:51:00.887379 Starting kernel ...
502 10:51:00.887783
503 10:51:00.888639 end: 2.4.3 bootloader-commands (duration 00:00:45) [common]
504 10:51:00.889206 start: 2.4.4 auto-login-action (timeout 00:03:59) [common]
505 10:51:00.889657 Setting prompt string to ['Linux version [0-9]']
506 10:51:00.890149 Setting prompt string to ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
507 10:51:00.890611 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:05:00)
508 10:51:01.730842 [ 0.000000] Booting Linux on physical CPU 0x0
509 10:51:01.736834 start: 2.4.4.1 login-action (timeout 00:03:58) [common]
510 10:51:01.737415 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
511 10:51:01.737944 Setting prompt string to []
512 10:51:01.738458 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
513 10:51:01.738924 Using line separator: #'\n'#
514 10:51:01.739339 No login prompt set.
515 10:51:01.739774 Parsing kernel messages
516 10:51:01.740180 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
517 10:51:01.740975 [login-action] Waiting for messages, (timeout 00:03:58)
518 10:51:01.741430 Waiting using forced prompt support (timeout 00:01:59)
519 10:51:01.753512 [ 0.000000] Linux version 6.12.0-rc7-next-20241111 (KernelCI@build-j372631-arm-gcc-12-multi-v7-defconfig-kxcrn) (arm-linux-gnueabihf-gcc (Debian 12.2.0-14) 12.2.0, GNU ld (GNU Binutils for Debian) 2.40) #1 SMP Mon Nov 11 10:30:07 UTC 2024
520 10:51:01.759163 [ 0.000000] CPU: ARMv7 Processor [413fc082] revision 2 (ARMv7), cr=10c5387d
521 10:51:01.770615 [ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
522 10:51:01.776363 [ 0.000000] OF: fdt: Machine model: TI AM335x BeagleBone Black
523 10:51:01.782062 [ 0.000000] earlycon: omap8250 at MMIO 0x44e09000 (options '')
524 10:51:01.787874 [ 0.000000] printk: legacy bootconsole [omap8250] enabled
525 10:51:01.794515 [ 0.000000] Memory policy: Data cache writeback
526 10:51:01.794977 [ 0.000000] efi: UEFI not found.
527 10:51:01.801230 [ 0.000000] cma: Reserved 64 MiB at 0x9b800000 on node -1
528 10:51:01.806914 [ 0.000000] Zone ranges:
529 10:51:01.812648 [ 0.000000] DMA [mem 0x0000000080000000-0x000000009fdfffff]
530 10:51:01.818378 [ 0.000000] Normal empty
531 10:51:01.818806 [ 0.000000] HighMem empty
532 10:51:01.824108 [ 0.000000] Movable zone start for each node
533 10:51:01.824536 [ 0.000000] Early memory node ranges
534 10:51:01.835633 [ 0.000000] node 0: [mem 0x0000000080000000-0x000000009fdfffff]
535 10:51:01.840923 [ 0.000000] Initmem setup node 0 [mem 0x0000000080000000-0x000000009fdfffff]
536 10:51:01.862436 [ 0.000000] OF: reserved mem: Reserved memory: No reserved-memory node in the DT
537 10:51:01.875016 [ 0.000000] CPU: All CPU(s) started in SVC mode.
538 10:51:01.880671 [ 0.000000] AM335X ES2.0 (sgx neon)
539 10:51:01.892342 [ 0.000000] percpu: Embedded 17 pages/cpu s40204 r8192 d21236 u69632
540 10:51:01.912602 [ 0.000000] Kernel command line: console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.3:/var/lib/lava/dispatcher/tmp/974617/extract-nfsrootfs-esptk5zt,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp
541 10:51:01.918667 <6>[ 0.000000] printk: log buffer data + meta data: 131072 + 409600 = 540672 bytes
542 10:51:01.926847 <6>[ 0.000000] Dentry cache hash table entries: 65536 (order: 6, 262144 bytes, linear)
543 10:51:01.938235 <6>[ 0.000000] Inode-cache hash table entries: 32768 (order: 5, 131072 bytes, linear)
544 10:51:01.943954 <6>[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 130560
545 10:51:01.950931 <6>[ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
546 10:51:01.979951 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
547 10:51:01.986080 <6>[ 0.000000] trace event string verifier disabled
548 10:51:01.986511 <6>[ 0.000000] rcu: Hierarchical RCU implementation.
549 10:51:01.991663 <6>[ 0.000000] rcu: RCU event tracing is enabled.
550 10:51:02.003150 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=16 to nr_cpu_ids=1.
551 10:51:02.003593 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
552 10:51:02.014629 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 10 jiffies.
553 10:51:02.020415 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=1
554 10:51:02.031158 <6>[ 0.000000] RCU Tasks Trace: Setting shift to 0 and lim to 1 rcu_task_cb_adjust=1 rcu_task_cpu_ids=1.
555 10:51:02.045278 <6>[ 0.000000] NR_IRQS: 16, nr_irqs: 16, preallocated irqs: 16
556 10:51:02.063730 <6>[ 0.000000] IRQ: Found an INTC at 0x(ptrval) (revision 5.0) with 128 interrupts
557 10:51:02.069543 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
558 10:51:02.163007 <6>[ 0.000000] TI gptimer clocksource: always-on /ocp/interconnect@44c00000/segment@200000/target-module@31000
559 10:51:02.171680 <6>[ 0.000003] sched_clock: 32 bits at 24MHz, resolution 41ns, wraps every 89478484971ns
560 10:51:02.184146 <6>[ 0.008340] clocksource: dmtimer: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 79635851949 ns
561 10:51:02.191817 <6>[ 0.019168] TI gptimer clockevent: 24000000 Hz at /ocp/interconnect@48000000/segment@0/target-module@40000
562 10:51:02.201832 <6>[ 0.034098] Console: colour dummy device 80x30
563 10:51:02.208123 Matched prompt #6: WARNING:
564 10:51:02.208862 Setting prompt string to ['end trace[^\\r]*\\r', '/ #', 'Login timed out', 'Login incorrect']
565 10:51:02.213433 <3>[ 0.038998] WARNING: Your 'console=ttyO0' has been replaced by 'ttyS0'
566 10:51:02.219262 <3>[ 0.046067] This ensures that you still see kernel messages. Please
567 10:51:02.221456 <3>[ 0.052790] update your kernel commandline.
568 10:51:02.262888 <6>[ 0.057402] Calibrating delay loop... 996.14 BogoMIPS (lpj=4980736)
569 10:51:02.268615 <6>[ 0.096178] CPU: Testing write buffer coherency: ok
570 10:51:02.271470 <6>[ 0.101549] CPU0: Spectre v2: using BPIALL workaround
571 10:51:02.277278 <6>[ 0.107019] pid_max: default: 32768 minimum: 301
572 10:51:02.283070 <6>[ 0.112214] Mount-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
573 10:51:02.291638 <6>[ 0.120035] Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
574 10:51:02.298808 <6>[ 0.129407] CPU0: thread -1, cpu 0, socket -1, mpidr 0
575 10:51:02.307463 <6>[ 0.136518] Setting up static identity map for 0x80300000 - 0x803000ac
576 10:51:02.314073 <6>[ 0.146197] rcu: Hierarchical SRCU implementation.
577 10:51:02.321190 <6>[ 0.151480] rcu: Max phase no-delay instances is 1000.
578 10:51:02.330573 <6>[ 0.162610] EFI services will not be available.
579 10:51:02.336425 <6>[ 0.167893] smp: Bringing up secondary CPUs ...
580 10:51:02.342121 <6>[ 0.172938] smp: Brought up 1 node, 1 CPU
581 10:51:02.348158 <6>[ 0.177339] SMP: Total of 1 processors activated (996.14 BogoMIPS).
582 10:51:02.353789 <6>[ 0.184110] CPU: All CPU(s) started in SVC mode.
583 10:51:02.373255 <6>[ 0.189297] Memory: 405932K/522240K available (16384K kernel code, 2541K rwdata, 6828K rodata, 2048K init, 429K bss, 49112K reserved, 65536K cma-reserved, 0K highmem)
584 10:51:02.373880 <6>[ 0.205576] devtmpfs: initialized
585 10:51:02.396902 <6>[ 0.223170] VFP support v0.3: implementor 41 architecture 3 part 30 variant c rev 3
586 10:51:02.405373 <6>[ 0.231757] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
587 10:51:02.413629 <6>[ 0.242218] futex hash table entries: 256 (order: 2, 16384 bytes, linear)
588 10:51:02.424341 <6>[ 0.254488] pinctrl core: initialized pinctrl subsystem
589 10:51:02.434434 <6>[ 0.265217] DMI not present or invalid.
590 10:51:02.442891 <6>[ 0.271078] NET: Registered PF_NETLINK/PF_ROUTE protocol family
591 10:51:02.452297 <6>[ 0.280064] DMA: preallocated 256 KiB pool for atomic coherent allocations
592 10:51:02.466510 <6>[ 0.291603] thermal_sys: Registered thermal governor 'step_wise'
593 10:51:02.467091 <6>[ 0.291766] cpuidle: using governor menu
594 10:51:02.511856 <6>[ 0.325806] /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70: Fixed dependency cycle(s) with /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
595 10:51:02.526420 <6>[ 0.344626] /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
596 10:51:02.532889 <6>[ 0.365301] No ATAGs?
597 10:51:02.538286 <6>[ 0.367931] hw-breakpoint: debug architecture 0x4 unsupported.
598 10:51:02.548605 <6>[ 0.380020] Serial: AMBA PL011 UART driver
599 10:51:02.582896 <6>[ 0.415016] iommu: Default domain type: Translated
600 10:51:02.591072 <6>[ 0.420358] iommu: DMA domain TLB invalidation policy: strict mode
601 10:51:02.619164 <5>[ 0.450675] SCSI subsystem initialized
602 10:51:02.625024 <6>[ 0.455551] usbcore: registered new interface driver usbfs
603 10:51:02.630677 <6>[ 0.461609] usbcore: registered new interface driver hub
604 10:51:02.637579 <6>[ 0.467393] usbcore: registered new device driver usb
605 10:51:02.643280 <6>[ 0.473932] pps_core: LinuxPPS API ver. 1 registered
606 10:51:02.654868 <6>[ 0.479320] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
607 10:51:02.662010 <6>[ 0.489054] PTP clock support registered
608 10:51:02.662562 <6>[ 0.493512] EDAC MC: Ver: 3.0.0
609 10:51:02.709443 <6>[ 0.540150] scmi_core: SCMI protocol bus registered
610 10:51:02.726026 <6>[ 0.557574] vgaarb: loaded
611 10:51:02.732183 <6>[ 0.561430] clocksource: Switched to clocksource dmtimer
612 10:51:02.775308 <6>[ 0.607257] NET: Registered PF_INET protocol family
613 10:51:02.787897 <6>[ 0.612934] IP idents hash table entries: 8192 (order: 4, 65536 bytes, linear)
614 10:51:02.793628 <6>[ 0.621812] tcp_listen_portaddr_hash hash table entries: 512 (order: 0, 4096 bytes, linear)
615 10:51:02.805151 <6>[ 0.630702] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
616 10:51:02.810874 <6>[ 0.638989] TCP established hash table entries: 4096 (order: 2, 16384 bytes, linear)
617 10:51:02.822368 <6>[ 0.647279] TCP bind hash table entries: 4096 (order: 4, 65536 bytes, linear)
618 10:51:02.828294 <6>[ 0.654996] TCP: Hash tables configured (established 4096 bind 4096)
619 10:51:02.834138 <6>[ 0.661920] UDP hash table entries: 256 (order: 1, 8192 bytes, linear)
620 10:51:02.839924 <6>[ 0.668929] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes, linear)
621 10:51:02.847466 <6>[ 0.676537] NET: Registered PF_UNIX/PF_LOCAL protocol family
622 10:51:02.939176 <6>[ 0.765759] RPC: Registered named UNIX socket transport module.
623 10:51:02.939722 <6>[ 0.772195] RPC: Registered udp transport module.
624 10:51:02.944907 <6>[ 0.777303] RPC: Registered tcp transport module.
625 10:51:02.950556 <6>[ 0.782425] RPC: Registered tcp-with-tls transport module.
626 10:51:02.963571 <6>[ 0.788333] RPC: Registered tcp NFSv4.1 backchannel transport module.
627 10:51:02.964018 <6>[ 0.795258] PCI: CLS 0 bytes, default 64
628 10:51:02.970741 <5>[ 0.801022] Initialise system trusted keyrings
629 10:51:02.990454 <6>[ 0.819639] Trying to unpack rootfs image as initramfs...
630 10:51:03.075757 <6>[ 0.901848] workingset: timestamp_bits=30 max_order=17 bucket_order=0
631 10:51:03.080597 <6>[ 0.909361] squashfs: version 4.0 (2009/01/31) Phillip Lougher
632 10:51:03.099782 <5>[ 0.932071] NFS: Registering the id_resolver key type
633 10:51:03.105580 <5>[ 0.937658] Key type id_resolver registered
634 10:51:03.111381 <5>[ 0.942336] Key type id_legacy registered
635 10:51:03.117272 <6>[ 0.946774] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
636 10:51:03.126761 <6>[ 0.953974] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
637 10:51:03.196023 <5>[ 1.028215] Key type asymmetric registered
638 10:51:03.201762 <5>[ 1.032794] Asymmetric key parser 'x509' registered
639 10:51:03.210157 <6>[ 1.038222] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 246)
640 10:51:03.215980 <6>[ 1.046141] io scheduler mq-deadline registered
641 10:51:03.224698 <6>[ 1.051069] io scheduler kyber registered
642 10:51:03.225265 <6>[ 1.055540] io scheduler bfq registered
643 10:51:03.332352 <6>[ 1.161762] ledtrig-cpu: registered to indicate activity on CPUs
644 10:51:03.616222 <6>[ 1.444677] Serial: 8250/16550 driver, 5 ports, IRQ sharing enabled
645 10:51:03.652203 <6>[ 1.484299] msm_serial: driver initialized
646 10:51:03.658263 <6>[ 1.489091] SuperH (H)SCI(F) driver initialized
647 10:51:03.664203 <6>[ 1.494424] STMicroelectronics ASC driver initialized
648 10:51:03.669284 <6>[ 1.500030] STM32 USART driver initialized
649 10:51:03.796632 <6>[ 1.628327] brd: module loaded
650 10:51:03.831633 <6>[ 1.663293] loop: module loaded
651 10:51:03.870690 <6>[ 1.702282] CAN device driver interface
652 10:51:03.877321 <6>[ 1.707299] bgmac_bcma: Broadcom 47xx GBit MAC driver loaded
653 10:51:03.882988 <6>[ 1.714348] e1000e: Intel(R) PRO/1000 Network Driver
654 10:51:03.890003 <6>[ 1.719736] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
655 10:51:03.895741 <6>[ 1.726224] igb: Intel(R) Gigabit Ethernet Network Driver
656 10:51:03.902902 <6>[ 1.732074] igb: Copyright (c) 2007-2014 Intel Corporation.
657 10:51:03.914573 <6>[ 1.741278] pegasus: Pegasus/Pegasus II USB Ethernet driver
658 10:51:03.920376 <6>[ 1.747432] usbcore: registered new interface driver pegasus
659 10:51:03.926210 <6>[ 1.753589] usbcore: registered new interface driver asix
660 10:51:03.931958 <6>[ 1.759441] usbcore: registered new interface driver ax88179_178a
661 10:51:03.937729 <6>[ 1.766044] usbcore: registered new interface driver cdc_ether
662 10:51:03.943489 <6>[ 1.772366] usbcore: registered new interface driver smsc75xx
663 10:51:03.949285 <6>[ 1.778577] usbcore: registered new interface driver smsc95xx
664 10:51:03.955108 <6>[ 1.784808] usbcore: registered new interface driver net1080
665 10:51:03.960904 <6>[ 1.790937] usbcore: registered new interface driver cdc_subset
666 10:51:03.966673 <6>[ 1.797347] usbcore: registered new interface driver zaurus
667 10:51:03.973769 <6>[ 1.803410] usbcore: registered new interface driver cdc_ncm
668 10:51:03.984273 <6>[ 1.812988] usbcore: registered new interface driver usb-storage
669 10:51:03.993534 <6>[ 1.824011] i2c_dev: i2c /dev entries driver
670 10:51:04.017646 <5>[ 1.842163] cpuidle: enable-method property 'ti,am3352' found operations
671 10:51:04.023359 <6>[ 1.851577] sdhci: Secure Digital Host Controller Interface driver
672 10:51:04.030700 <6>[ 1.858231] sdhci: Copyright(c) Pierre Ossman
673 10:51:04.038033 <6>[ 1.864597] Synopsys Designware Multimedia Card Interface Driver
674 10:51:04.043475 <6>[ 1.872530] sdhci-pltfm: SDHCI platform and OF driver helper
675 10:51:04.057440 <6>[ 1.882310] usbcore: registered new interface driver usbhid
676 10:51:04.058229 <6>[ 1.888339] usbhid: USB HID core driver
677 10:51:04.069101 <6>[ 1.899783] NET: Registered PF_INET6 protocol family
678 10:51:04.520684 <6>[ 2.352937] Segment Routing with IPv6
679 10:51:04.526611 <6>[ 2.357085] In-situ OAM (IOAM) with IPv6
680 10:51:04.533249 <6>[ 2.361599] sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver
681 10:51:04.539025 <6>[ 2.368858] NET: Registered PF_PACKET protocol family
682 10:51:04.544824 <6>[ 2.374428] can: controller area network core
683 10:51:04.550573 <6>[ 2.379258] NET: Registered PF_CAN protocol family
684 10:51:04.551158 <6>[ 2.384495] can: raw protocol
685 10:51:04.556395 <6>[ 2.387821] can: broadcast manager protocol
686 10:51:04.562862 <6>[ 2.392434] can: netlink gateway - max_hops=1
687 10:51:04.568998 <5>[ 2.397935] Key type dns_resolver registered
688 10:51:04.575382 <6>[ 2.403007] ThumbEE CPU extension supported.
689 10:51:04.575972 <5>[ 2.407693] Registering SWP/SWPB emulation handler
690 10:51:04.585051 <3>[ 2.413392] omap_voltage_late_init: Voltage driver support not added
691 10:51:04.801540 <5>[ 2.632202] Loading compiled-in X.509 certificates
692 10:51:04.876106 <6>[ 2.693365] /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70: Fixed dependency cycle(s) with /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
693 10:51:04.905639 <6>[ 2.722763] /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70: Fixed dependency cycle(s) with /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
694 10:51:05.067071 <6>[ 2.884763] /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70: Fixed dependency cycle(s) with /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
695 10:51:05.087166 <6>[ 2.904325] /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70: Fixed dependency cycle(s) with /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
696 10:51:05.113715 <6>[ 2.930661] /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800/clkout2-pins
697 10:51:05.123649 <6>[ 2.952265] pinctrl-single 44e10800.pinmux: 142 pins, size 568
698 10:51:05.150047 <3>[ 2.976173] ti-sysc 44e31000.target-module: probe with driver ti-sysc failed with error -16
699 10:51:05.417446 <6>[ 3.234832] /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
700 10:51:05.443271 <3>[ 3.269595] ti-sysc 48040000.target-module: probe with driver ti-sysc failed with error -16
701 10:51:05.682083 <6>[ 3.512752] OMAP GPIO hardware version 0.1
702 10:51:05.702905 <6>[ 3.531601] omap-mailbox 480c8000.mailbox: omap mailbox rev 0x400
703 10:51:05.784539 <4>[ 3.612965] at24 2-0054: supply vcc not found, using dummy regulator
704 10:51:05.821114 <4>[ 3.649589] at24 2-0055: supply vcc not found, using dummy regulator
705 10:51:05.858536 <4>[ 3.686952] at24 2-0056: supply vcc not found, using dummy regulator
706 10:51:05.897344 <4>[ 3.726589] at24 2-0057: supply vcc not found, using dummy regulator
707 10:51:05.935828 <6>[ 3.765106] omap_i2c 4819c000.i2c: bus 2 rev0.11 at 100 kHz
708 10:51:05.991767 <3>[ 3.817860] 48000000.interconnect:segment@200000:target-module@0:mpu@0:fck: device ID is greater than 24
709 10:51:06.014914 <6>[ 3.832314] /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
710 10:51:06.041900 <6>[ 3.855590] /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
711 10:51:06.059188 <6>[ 3.874788] /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70: Fixed dependency cycle(s) with /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
712 10:51:06.074613 <6>[ 3.892742] /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
713 10:51:06.096007 <4>[ 3.923145] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
714 10:51:06.122417 <6>[ 3.954446] Freeing initrd memory: 14488K
715 10:51:06.132083 <4>[ 3.959258] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
716 10:51:06.165739 <6>[ 3.995107] omap_rng 48310000.rng: Random Number Generator ver. 20
717 10:51:06.190364 <5>[ 4.021730] random: crng init done
718 10:51:06.234440 <6>[ 4.061430] davinci_mdio 4a101000.mdio: davinci mdio revision 1.6, bus freq 1000000
719 10:51:06.317707 <6>[ 4.143863] davinci_mdio 4a101000.mdio: phy[0]: device 4a101000.mdio:00, driver SMSC LAN8710/LAN8720
720 10:51:06.323713 <6>[ 4.154171] cpsw-switch 4a100000.switch: initialized cpsw ale version 1.4
721 10:51:06.335269 <6>[ 4.161510] cpsw-switch 4a100000.switch: ALE Table size 1024, Policers 0
722 10:51:06.341147 <6>[ 4.168974] cpsw-switch 4a100000.switch: cpts: overflow check period 500 (jiffies)
723 10:51:06.352636 <6>[ 4.177107] cpsw-switch 4a100000.switch: CPTS: ref_clk_freq:250000000 calc_mult:2147483648 calc_shift:29 error:0 nsec/sec
724 10:51:06.360075 <6>[ 4.188758] cpsw-switch 4a100000.switch: Detected MACID = 90:59:af:5c:d5:d8
725 10:51:06.372173 <5>[ 4.197804] cpsw-switch 4a100000.switch: initialized (regs 0x4a100000, pool size 256) hw_ver:0019010C 1.12 (0)
726 10:51:06.401103 <3>[ 4.227712] debugfs: Directory '49000000.dma' with parent 'dmaengine' already present!
727 10:51:06.406880 <6>[ 4.236304] edma 49000000.dma: TI EDMA DMA engine driver
728 10:51:06.478234 <3>[ 4.304078] target-module@4b000000:target-module@140000:pmu@0:fck: device ID is greater than 24
729 10:51:06.492759 <6>[ 4.318396] hw perfevents: enabled with armv7_cortex_a8 PMU driver, 5 (8000000f) counters available
730 10:51:06.505778 <3>[ 4.335484] l3-aon-clkctrl:0000:0: failed to disable
731 10:51:06.555987 <6>[ 4.382589] 44e09000.serial: ttyS0 at MMIO 0x44e09000 (irq = 36, base_baud = 3000000) is a 8250
732 10:51:06.561703 <6>[ 4.392060] printk: legacy console [ttyS0] enabled
733 10:51:06.564366 <6>[ 4.392060] printk: legacy console [ttyS0] enabled
734 10:51:06.569973 <6>[ 4.402404] printk: legacy bootconsole [omap8250] disabled
735 10:51:06.577956 <6>[ 4.402404] printk: legacy bootconsole [omap8250] disabled
736 10:51:06.616720 <4>[ 4.442203] tps65217-pmic: Failed to locate of_node [id: -1]
737 10:51:06.619345 <4>[ 4.449592] tps65217-bl: Failed to locate of_node [id: -1]
738 10:51:06.636543 <6>[ 4.469151] tps65217 0-0024: TPS65217 ID 0xe version 1.2
739 10:51:06.660693 <6>[ 4.476107] /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
740 10:51:06.677802 <6>[ 4.493742] /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70: Fixed dependency cycle(s) with /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
741 10:51:06.682348 <6>[ 4.511603] omap_i2c 44e0b000.i2c: bus 0 rev0.11 at 400 kHz
742 10:51:06.704685 <6>[ 4.531694] omap_gpio 44e07000.gpio: Could not set line 6 debounce to 200000 microseconds (-22)
743 10:51:06.710567 <6>[ 4.540751] sdhci-omap 48060000.mmc: Got CD GPIO
744 10:51:06.718644 <4>[ 4.545918] sdhci-omap 48060000.mmc: supply pbias not found, using dummy regulator
745 10:51:06.733406 <4>[ 4.559502] sdhci-omap 48060000.mmc: supply vqmmc not found, using dummy regulator
746 10:51:06.741007 <4>[ 4.568312] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
747 10:51:06.775796 <4>[ 4.603198] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
748 10:51:06.823501 <6>[ 4.651621] at24 0-0050: 32768 byte 24c256 EEPROM, writable, 1 bytes/write
749 10:51:06.857302 <6>[ 4.684423] mmc1: SDHCI controller on 481d8000.mmc [481d8000.mmc] using External DMA
750 10:51:06.880085 <6>[ 4.706391] mmc0: SDHCI controller on 48060000.mmc [48060000.mmc] using External DMA
751 10:51:06.886875 <6>[ 4.715276] cpsw-switch 4a100000.switch: starting ndev. mode: dual_mac
752 10:51:06.937715 <6>[ 4.760866] mmc0: new high speed SDHC card at address 0001
753 10:51:06.938326 <6>[ 4.768335] mmcblk0: mmc0:0001 EB1QT 29.8 GiB
754 10:51:06.945735 <6>[ 4.776778] mmcblk0: p1
755 10:51:06.953273 <6>[ 4.781246] mmc1: new high speed MMC card at address 0001
756 10:51:06.958337 <6>[ 4.788814] mmcblk1: mmc1:0001 MMC02G 1.79 GiB
757 10:51:06.971381 <6>[ 4.797968] SMSC LAN8710/LAN8720 4a101000.mdio:00: attached PHY driver (mii_bus:phy_addr=4a101000.mdio:00, irq=POLL)
758 10:51:06.977983 <6>[ 4.809299] mmcblk1:
759 10:51:06.980607 <6>[ 4.812718] mmcblk1boot0: mmc1:0001 MMC02G 1.00 MiB
760 10:51:06.989597 <6>[ 4.819689] mmcblk1boot1: mmc1:0001 MMC02G 1.00 MiB
761 10:51:07.003513 <6>[ 4.832271] mmcblk1rpmb: mmc1:0001 MMC02G 128 KiB, chardev (236:0)
762 10:51:09.114789 <6>[ 6.942474] cpsw-switch 4a100000.switch eth0: Link is Up - 100Mbps/Full - flow control off
763 10:51:09.248941 <5>[ 6.981547] Sending DHCP requests ., OK
764 10:51:09.260340 <6>[ 7.085858] IP-Config: Got DHCP answer from 192.168.6.1, my address is 192.168.6.23
765 10:51:09.260892 <6>[ 7.094001] IP-Config: Complete:
766 10:51:09.271627 <6>[ 7.097539] device=eth0, hwaddr=90:59:af:5c:d5:d8, ipaddr=192.168.6.23, mask=255.255.255.0, gw=192.168.6.1
767 10:51:09.277341 <6>[ 7.108052] host=192.168.6.23, domain=, nis-domain=(none)
768 10:51:09.289564 <6>[ 7.114271] bootserver=192.168.6.1, rootserver=192.168.6.3, rootpath=
769 10:51:09.290139 <6>[ 7.114307] nameserver0=10.255.253.1
770 10:51:09.295988 <6>[ 7.126813] clk: Disabling unused clocks
771 10:51:09.301606 <6>[ 7.131592] PM: genpd: Disabling unused power domains
772 10:51:09.320921 <6>[ 7.150026] Freeing unused kernel image (initmem) memory: 2048K
773 10:51:09.329034 <6>[ 7.160366] Run /init as init process
774 10:51:09.353092 Loading, please wait...
775 10:51:09.428522 Starting systemd-udevd version 252.22-1~deb12u1
776 10:51:12.726918 <4>[ 10.552889] am335x-phy-driver 47401300.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
777 10:51:12.857656 <4>[ 10.683099] am335x-phy-driver 47401b00.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
778 10:51:13.053774 <6>[ 10.886502] musb-hdrc musb-hdrc.1: MUSB HDRC host driver
779 10:51:13.064521 <6>[ 10.892322] musb-hdrc musb-hdrc.1: new USB bus registered, assigned bus number 1
780 10:51:13.072366 <6>[ 10.903465] tda998x 0-0070: found TDA19988
781 10:51:13.299906 <6>[ 11.131233] hub 1-0:1.0: USB hub found
782 10:51:13.310414 <6>[ 11.141640] hub 1-0:1.0: 1 port detected
783 10:51:16.018128 Begin: Loading essential drivers ... done.
784 10:51:16.023398 Begin: Running /scripts/init-premount ... done.
785 10:51:16.028976 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
786 10:51:16.042903 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
787 10:51:16.043407 Device /sys/class/net/eth0 found
788 10:51:16.043805 done.
789 10:51:16.120047 Begin: Waiting up to 180 secs for any network device to become available ... done.
790 10:51:16.191771 IP-Config: eth0 hardware address 90:59:af:5c:d5:d8 mtu 1500 DHCP
791 10:51:16.292858 IP-Config: eth0 guessed broadcast address 192.168.6.255
792 10:51:16.298242 IP-Config: eth0 complete (dhcp from 192.168.6.1):
793 10:51:16.303860 address: 192.168.6.23 broadcast: 192.168.6.255 netmask: 255.255.255.0
794 10:51:16.315039 gateway: 192.168.6.1 dns0 : 10.255.253.1 dns1 : 0.0.0.0
795 10:51:16.315498 rootserver: 192.168.6.1 rootpath:
796 10:51:16.318479 filename :
797 10:51:16.398120 done.
798 10:51:16.421238 Begin: Running /scripts/nfs-bottom ... done.
799 10:51:16.483906 Begin: Running /scripts/init-bottom ... done.
800 10:51:17.931381 <30>[ 15.759797] systemd[1]: System time before build time, advancing clock.
801 10:51:18.186766 <30>[ 15.989248] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
802 10:51:18.194715 <30>[ 16.025973] systemd[1]: Detected architecture arm.
803 10:51:18.207682
804 10:51:18.207985 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
805 10:51:18.208193
806 10:51:18.231921 <30>[ 16.061034] systemd[1]: Hostname set to <debian-bookworm-armhf>.
807 10:51:20.397709 <30>[ 18.225751] systemd[1]: Queued start job for default target graphical.target.
808 10:51:20.414429 <30>[ 18.240318] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
809 10:51:20.422043 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
810 10:51:20.451834 <30>[ 18.277376] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
811 10:51:20.459276 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
812 10:51:20.489063 <30>[ 18.314225] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
813 10:51:20.496449 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
814 10:51:20.529649 <30>[ 18.355252] systemd[1]: Created slice user.slice - User and Session Slice.
815 10:51:20.536259 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
816 10:51:20.561884 <30>[ 18.382646] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
817 10:51:20.567855 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
818 10:51:20.585927 <30>[ 18.412536] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
819 10:51:20.594913 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
820 10:51:20.624565 <30>[ 18.442509] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
821 10:51:20.636489 <30>[ 18.463328] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
822 10:51:20.642114 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
823 10:51:20.665022 <30>[ 18.491915] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
824 10:51:20.673206 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
825 10:51:20.695888 <30>[ 18.522285] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
826 10:51:20.704101 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
827 10:51:20.725601 <30>[ 18.552435] systemd[1]: Reached target paths.target - Path Units.
828 10:51:20.730696 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
829 10:51:20.755496 <30>[ 18.582204] systemd[1]: Reached target remote-fs.target - Remote File Systems.
830 10:51:20.762745 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
831 10:51:20.785165 <30>[ 18.611976] systemd[1]: Reached target slices.target - Slice Units.
832 10:51:20.790628 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
833 10:51:20.815500 <30>[ 18.642228] systemd[1]: Reached target swap.target - Swaps.
834 10:51:20.819443 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
835 10:51:20.845685 <30>[ 18.672345] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
836 10:51:20.854596 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
837 10:51:20.876575 <30>[ 18.703130] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
838 10:51:20.884832 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
839 10:51:20.964157 <30>[ 18.785930] systemd[1]: systemd-journald-audit.socket - Journal Audit Socket was skipped because of an unmet condition check (ConditionSecurity=audit).
840 10:51:20.976891 <30>[ 18.803547] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
841 10:51:20.985334 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
842 10:51:21.008372 <30>[ 18.834186] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
843 10:51:21.015799 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
844 10:51:21.038089 <30>[ 18.864605] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
845 10:51:21.046241 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
846 10:51:21.071087 <30>[ 18.896518] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
847 10:51:21.076666 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
848 10:51:21.107761 <30>[ 18.933182] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
849 10:51:21.115349 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
850 10:51:21.142591 <30>[ 18.963253] systemd[1]: dev-hugepages.mount - Huge Pages File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/mm/hugepages).
851 10:51:21.161228 <30>[ 18.981858] systemd[1]: dev-mqueue.mount - POSIX Message Queue File System was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/mqueue).
852 10:51:21.209236 <30>[ 19.036779] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
853 10:51:21.235738 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
854 10:51:21.287162 <30>[ 19.114538] systemd[1]: Mounting sys-kernel-tracing.mount - Kernel Trace File System...
855 10:51:21.306932 Mounting [0;1;39msys-kernel-tracin…[0m - Kernel Trace File System...
856 10:51:21.369964 <30>[ 19.196276] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
857 10:51:21.394176 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
858 10:51:21.446415 <30>[ 19.273412] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
859 10:51:21.464520 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
860 10:51:21.525678 <30>[ 19.353021] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
861 10:51:21.543100 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
862 10:51:21.605006 <30>[ 19.432816] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
863 10:51:21.615841 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
864 10:51:21.658302 <30>[ 19.484940] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
865 10:51:21.685060 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
866 10:51:21.735751 <30>[ 19.563365] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
867 10:51:21.754870 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
868 10:51:21.785608 <30>[ 19.613307] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
869 10:51:21.815081 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
870 10:51:21.842030 <28>[ 19.663752] systemd[1]: systemd-journald.service: unit configures an IP firewall, but the local system does not support BPF/cgroup firewalling.
871 10:51:21.850514 <28>[ 19.677373] systemd[1]: (This warning is only shown for the first unit using IP firewalling.)
872 10:51:21.894752 <30>[ 19.722849] systemd[1]: Starting systemd-journald.service - Journal Service...
873 10:51:21.906026 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
874 10:51:21.987685 <30>[ 19.813041] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
875 10:51:21.995286 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
876 10:51:22.033198 <30>[ 19.860856] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
877 10:51:22.079163 Starting [0;1;39msystemd-network-g… units from Kernel command line...
878 10:51:22.176690 <30>[ 20.002799] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
879 10:51:22.215646 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
880 10:51:22.277073 <30>[ 20.104006] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
881 10:51:22.326688 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
882 10:51:22.415574 <30>[ 20.242365] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
883 10:51:22.423592 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
884 10:51:22.466386 <30>[ 20.293940] systemd[1]: Mounted sys-kernel-tracing.mount - Kernel Trace File System.
885 10:51:22.489885 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-tracing…nt[0m - Kernel Trace File System.
886 10:51:22.538689 <30>[ 20.365280] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
887 10:51:22.566648 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
888 10:51:22.695718 <30>[ 20.524045] systemd[1]: modprobe@configfs.service: Deactivated successfully.
889 10:51:22.726107 <30>[ 20.553368] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
890 10:51:22.754855 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
891 10:51:22.776513 <30>[ 20.603312] systemd[1]: Started systemd-journald.service - Journal Service.
892 10:51:22.783338 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
893 10:51:22.811838 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
894 10:51:22.840035 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
895 10:51:22.876536 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
896 10:51:22.908559 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
897 10:51:22.945012 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
898 10:51:22.975227 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
899 10:51:22.998501 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
900 10:51:23.027582 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
901 10:51:23.055092 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
902 10:51:23.118265 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
903 10:51:23.174058 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
904 10:51:23.227021 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
905 10:51:23.321246 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
906 10:51:23.414132 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
907 10:51:23.517495 <46>[ 21.345225] systemd-journald[164]: Received client request to flush runtime journal.
908 10:51:23.565491 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
909 10:51:23.648377 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
910 10:51:24.505969 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
911 10:51:24.833355 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
912 10:51:24.897397 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
913 10:51:25.278463 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
914 10:51:25.448673 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
915 10:51:25.485120 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
916 10:51:25.504903 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
917 10:51:25.585339 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
918 10:51:25.648389 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
919 10:51:26.591991 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
920 10:51:26.666164 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
921 10:51:26.780331 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
922 10:51:26.873998 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
923 10:51:26.944812 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
924 10:51:28.845602 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
925 10:51:29.710081 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m <5>[ 27.534216] cfg80211: Loading compiled-in X.509 certificates for regulatory database
926 10:51:29.710567 - Coldplug All udev Devices.
927 10:51:30.505785 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
928 10:51:31.256871 <5>[ 29.082724] Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
929 10:51:31.264225 <5>[ 29.090831] Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
930 10:51:31.270041 <4>[ 29.100076] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
931 10:51:31.278146 <6>[ 29.109172] cfg80211: failed to load regulatory.db
932 10:51:31.590208 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
933 10:51:31.700418 <46>[ 29.519281] systemd-journald[164]: Oldest entry in /var/log/journal/658c871cd7314ccea6115dc5728f8992/system.journal is older than the configured file retention duration (1month), suggesting rotation.
934 10:51:31.868556 <46>[ 29.689441] systemd-journald[164]: /var/log/journal/658c871cd7314ccea6115dc5728f8992/system.journal: Journal header limits reached or header out-of-date, rotating.
935 10:51:32.393855 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
936 10:51:41.018690 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
937 10:51:41.051147 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
938 10:51:41.077043 [[0;32m OK [0m] Reached target [0;1;39musb-gadget.…m - Hardware activated USB gadget.
939 10:51:41.097341 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
940 10:51:41.154990 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
941 10:51:41.196923 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
942 10:51:41.234554 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
943 10:51:41.298756 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
944 10:51:41.373969 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
945 10:51:41.401885 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
946 10:51:41.442726 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
947 10:51:41.469139 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
948 10:51:41.511759 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
949 10:51:41.547737 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
950 10:51:41.581784 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
951 10:51:41.607875 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
952 10:51:41.637432 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
953 10:51:41.667043 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
954 10:51:41.686307 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
955 10:51:41.705469 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
956 10:51:41.732981 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
957 10:51:41.755184 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
958 10:51:41.777770 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
959 10:51:41.855956 Starting [0;1;39malsa-restore.serv…- Save/Restore Sound Card State...
960 10:51:41.915724 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
961 10:51:42.010698 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
962 10:51:42.078099 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
963 10:51:42.147963 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
964 10:51:42.194774 [[0;32m OK [0m] Finished [0;1;39malsa-restore.serv…m - Save/Restore Sound Card State.
965 10:51:42.209554 [[0;32m OK [0m] Reached target [0;1;39msound.target[0m - Sound Card.
966 10:51:42.406569 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
967 10:51:42.470352 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
968 10:51:42.538316 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
969 10:51:42.564127 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
970 10:51:42.722092 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
971 10:51:42.824077 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
972 10:51:43.185468 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
973 10:51:43.234255 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
974 10:51:43.260952 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
975 10:51:43.339973 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
976 10:51:43.534542 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
977 10:51:43.667353
978 10:51:43.672718 Debian GNU/Linux 12 debian-bookworm-armhfkworm-armhf login: root (automatic login)
979 10:51:43.673023
980 10:51:44.017684 Linux debian-bookworm-armhf 6.12.0-rc7-next-20241111 #1 SMP Mon Nov 11 10:30:07 UTC 2024 armv7l
981 10:51:44.018368
982 10:51:44.023060 The programs included with the Debian GNU/Linux system are free software;
983 10:51:44.028632 the exact distribution terms for each program are described in the
984 10:51:44.034426 individual files in /usr/share/doc/*/copyright.
985 10:51:44.034776
986 10:51:44.039716 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
987 10:51:44.043304 permitted by applicable law.
988 10:51:48.703284 Unable to match end of the kernel message
990 10:51:48.704186 Setting prompt string to ['/ #']
991 10:51:48.704493 end: 2.4.4.1 login-action (duration 00:00:47) [common]
993 10:51:48.705196 end: 2.4.4 auto-login-action (duration 00:00:48) [common]
994 10:51:48.705481 start: 2.4.5 expect-shell-connection (timeout 00:03:11) [common]
995 10:51:48.705718 Setting prompt string to ['/ #']
996 10:51:48.705979 Forcing a shell prompt, looking for ['/ #']
998 10:51:48.756585 / #
999 10:51:48.757356 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
1000 10:51:48.757949 Waiting using forced prompt support (timeout 00:02:30)
1001 10:51:48.761148
1002 10:51:48.771568 end: 2.4.5 expect-shell-connection (duration 00:00:00) [common]
1003 10:51:48.772239 start: 2.4.6 export-device-env (timeout 00:03:11) [common]
1004 10:51:48.772784 Sending with 10 millisecond of delay
1006 10:51:53.765336 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/974617/extract-nfsrootfs-esptk5zt'
1007 10:51:53.776477 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/974617/extract-nfsrootfs-esptk5zt'
1008 10:51:53.777329 Sending with 10 millisecond of delay
1010 10:51:55.877667 / # export NFS_SERVER_IP='192.168.6.3'
1011 10:51:55.888796 export NFS_SERVER_IP='192.168.6.3'
1012 10:51:55.890478 end: 2.4.6 export-device-env (duration 00:00:07) [common]
1013 10:51:55.891160 end: 2.4 uboot-commands (duration 00:01:56) [common]
1014 10:51:55.891770 end: 2 uboot-action (duration 00:01:56) [common]
1015 10:51:55.892380 start: 3 lava-test-retry (timeout 00:06:52) [common]
1016 10:51:55.892994 start: 3.1 lava-test-shell (timeout 00:06:52) [common]
1017 10:51:55.893745 Using namespace: common
1019 10:51:55.995069 / # #
1020 10:51:55.995873 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
1021 10:51:56.000784 #
1022 10:51:56.007135 Using /lava-974617
1024 10:51:56.108379 / # export SHELL=/bin/bash
1025 10:51:56.113626 export SHELL=/bin/bash
1027 10:51:56.220977 / # . /lava-974617/environment
1028 10:51:56.226293 . /lava-974617/environment
1030 10:51:56.339825 / # /lava-974617/bin/lava-test-runner /lava-974617/0
1031 10:51:56.340573 Test shell timeout: 10s (minimum of the action and connection timeout)
1032 10:51:56.345273 /lava-974617/bin/lava-test-runner /lava-974617/0
1033 10:51:56.722873 + export TESTRUN_ID=0_timesync-off
1034 10:51:56.730839 + TESTRUN_ID=0_timesync-off
1035 10:51:56.731200 + cd /lava-974617/0/tests/0_timesync-off
1036 10:51:56.731443 ++ cat uuid
1037 10:51:56.746762 + UUID=974617_1.6.2.4.1
1038 10:51:56.747412 + set +x
1039 10:51:56.754551 <LAVA_SIGNAL_STARTRUN 0_timesync-off 974617_1.6.2.4.1>
1040 10:51:56.755119 + systemctl stop systemd-timesyncd
1041 10:51:56.755875 Received signal: <STARTRUN> 0_timesync-off 974617_1.6.2.4.1
1042 10:51:56.756362 Starting test lava.0_timesync-off (974617_1.6.2.4.1)
1043 10:51:56.756935 Skipping test definition patterns.
1044 10:51:57.064927 + set +x
1045 10:51:57.065610 <LAVA_SIGNAL_ENDRUN 0_timesync-off 974617_1.6.2.4.1>
1046 10:51:57.066423 Received signal: <ENDRUN> 0_timesync-off 974617_1.6.2.4.1
1047 10:51:57.066965 Ending use of test pattern.
1048 10:51:57.067432 Ending test lava.0_timesync-off (974617_1.6.2.4.1), duration 0.31
1050 10:51:57.261901 + export TESTRUN_ID=1_kselftest-dt
1051 10:51:57.269959 + TESTRUN_ID=1_kselftest-dt
1052 10:51:57.270584 + cd /lava-974617/0/tests/1_kselftest-dt
1053 10:51:57.271080 ++ cat uuid
1054 10:51:57.285457 + UUID=974617_1.6.2.4.5
1055 10:51:57.286110 + set +x
1056 10:51:57.291068 <LAVA_SIGNAL_STARTRUN 1_kselftest-dt 974617_1.6.2.4.5>
1057 10:51:57.291643 + cd ./automated/linux/kselftest/
1058 10:51:57.292383 Received signal: <STARTRUN> 1_kselftest-dt 974617_1.6.2.4.5
1059 10:51:57.292861 Starting test lava.1_kselftest-dt (974617_1.6.2.4.5)
1060 10:51:57.293392 Skipping test definition patterns.
1061 10:51:57.317266 + ./kselftest.sh -c dt -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/next/master/next-20241111/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz -L '' -S /dev/null -b beaglebone-black -g next -e '' -p /opt/kselftests/mainline/ -n 1 -i 1 -E ''
1062 10:51:57.450267 INFO: install_deps skipped
1063 10:51:58.045565 --2024-11-11 10:51:58-- http://storage.kernelci.org/next/master/next-20241111/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz
1064 10:51:58.079947 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
1065 10:51:58.225894 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
1066 10:51:58.370073 HTTP request sent, awaiting response... 200 OK
1067 10:51:58.370756 Length: 4159272 (4.0M) [application/octet-stream]
1068 10:51:58.375361 Saving to: 'kselftest_armhf.tar.gz'
1069 10:51:58.375881
1070 10:52:00.324466
kselftest_armhf.tar 0%[ ] 0 --.-KB/s
kselftest_armhf.tar 1%[ ] 49.92K 175KB/s
kselftest_armhf.tar 5%[> ] 218.67K 377KB/s
kselftest_armhf.tar 20%[===> ] 837.85K 838KB/s
kselftest_armhf.tar 37%[======> ] 1.47M 1.22MB/s
kselftest_armhf.tar 54%[=========> ] 2.14M 1.50MB/s
kselftest_armhf.tar 64%[===========> ] 2.56M 1.57MB/s
kselftest_armhf.tar 89%[================> ] 3.56M 1.92MB/s
kselftest_armhf.tar 100%[===================>] 3.97M 2.04MB/s in 1.9s
1071 10:52:00.325189
1072 10:52:00.852228 2024-11-11 10:52:00 (2.04 MB/s) - 'kselftest_armhf.tar.gz' saved [4159272/4159272]
1073 10:52:00.852903
1074 10:52:16.081029 skiplist:
1075 10:52:16.081434 ========================================
1076 10:52:16.086978 ========================================
1077 10:52:16.197266 dt:test_unprobed_devices.sh
1078 10:52:16.235869 ============== Tests to run ===============
1079 10:52:16.248354 dt:test_unprobed_devices.sh
1080 10:52:16.252315 ===========End Tests to run ===============
1081 10:52:16.263406 shardfile-dt pass
1082 10:52:16.499842 <12>[ 74.333114] kselftest: Running tests in dt
1083 10:52:16.527747 TAP version 13
1084 10:52:16.549978 1..1
1085 10:52:16.605343 # timeout set to 45
1086 10:52:16.606093 # selftests: dt: test_unprobed_devices.sh
1087 10:52:17.491200 # TAP version 13
1088 10:52:42.392950 # 1..257
1089 10:52:42.561246 # ok 1 / # SKIP
1090 10:52:42.582655 # ok 2 /clk_mcasp0
1091 10:52:42.652190 # ok 3 /clk_mcasp0_fixed # SKIP
1092 10:52:42.724262 # ok 4 /cpus/cpu@0 # SKIP
1093 10:52:42.796730 # ok 5 /cpus/idle-states/mpu_gate # SKIP
1094 10:52:42.820732 # ok 6 /fixedregulator0
1095 10:52:42.841049 # ok 7 /leds
1096 10:52:42.862349 # ok 8 /ocp
1097 10:52:42.881512 # ok 9 /ocp/interconnect@44c00000
1098 10:52:42.907057 # ok 10 /ocp/interconnect@44c00000/segment@0
1099 10:52:42.929536 # ok 11 /ocp/interconnect@44c00000/segment@100000
1100 10:52:42.958148 # ok 12 /ocp/interconnect@44c00000/segment@100000/target-module@0
1101 10:52:43.027964 # not ok 13 /ocp/interconnect@44c00000/segment@100000/target-module@0/cpu@0
1102 10:52:43.069563 # ok 14 /ocp/interconnect@44c00000/segment@200000
1103 10:52:43.103153 # ok 15 /ocp/interconnect@44c00000/segment@200000/target-module@0
1104 10:52:43.210186 # not ok 16 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0
1105 10:52:43.279858 # ok 17 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0 # SKIP
1106 10:52:43.353751 # ok 18 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@0 # SKIP
1107 10:52:43.425382 # ok 19 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@120 # SKIP
1108 10:52:43.497375 # ok 20 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@14c # SKIP
1109 10:52:43.572795 # ok 21 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@18 # SKIP
1110 10:52:43.645000 # ok 22 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@1c # SKIP
1111 10:52:43.717539 # ok 23 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@24 # SKIP
1112 10:52:43.789142 # ok 24 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@38 # SKIP
1113 10:52:43.860304 # ok 25 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@e8 # SKIP
1114 10:52:43.934151 # ok 26 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400 # SKIP
1115 10:52:44.002854 # ok 27 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@0 # SKIP
1116 10:52:44.074702 # ok 28 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@14 # SKIP
1117 10:52:44.144919 # ok 29 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@b0 # SKIP
1118 10:52:44.214326 # ok 30 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600 # SKIP
1119 10:52:44.288036 # ok 31 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600/clock@0 # SKIP
1120 10:52:44.359201 # ok 32 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800 # SKIP
1121 10:52:44.431236 # ok 33 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800/clock@0 # SKIP
1122 10:52:44.503902 # ok 34 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900 # SKIP
1123 10:52:44.571871 # ok 35 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900/clock@0 # SKIP
1124 10:52:44.642633 # ok 36 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00 # SKIP
1125 10:52:44.714619 # ok 37 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00/clock@0 # SKIP
1126 10:52:44.786440 # ok 38 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-24mhz # SKIP
1127 10:52:44.857644 # ok 39 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-32768 # SKIP
1128 10:52:44.928576 # ok 40 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-rc32k # SKIP
1129 10:52:45.000912 # ok 41 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clkdiv32k # SKIP
1130 10:52:45.074466 # ok 42 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-125mhz-gclk # SKIP
1131 10:52:45.143664 # ok 43 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-cpts-rft@520 # SKIP
1132 10:52:45.220325 # ok 44 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4-div2 # SKIP
1133 10:52:45.292345 # ok 45 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4@480 # SKIP
1134 10:52:45.362712 # ok 46 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m5@484 # SKIP
1135 10:52:45.430147 # ok 47 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m6@4d8 # SKIP
1136 10:52:45.501875 # ok 48 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-x2 # SKIP
1137 10:52:45.580362 # ok 49 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2-div2 # SKIP
1138 10:52:45.646006 # ok 50 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2@4a0 # SKIP
1139 10:52:45.721570 # ok 51 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-disp-m2@4a4 # SKIP
1140 10:52:45.788163 # ok 52 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-mpu-m2@4a8 # SKIP
1141 10:52:45.859468 # ok 53 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4 # SKIP
1142 10:52:45.931649 # ok 54 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4-wkupdm # SKIP
1143 10:52:46.003943 # ok 55 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2@4ac # SKIP
1144 10:52:46.073047 # ok 56 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-gpio0-dbclk-mux@53c # SKIP
1145 10:52:46.149493 # ok 57 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-ieee5000-fck-1@e4 # SKIP
1146 10:52:46.220065 # ok 58 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3-gclk # SKIP
1147 10:52:46.291494 # ok 59 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3s-gclk # SKIP
1148 10:52:46.362280 # ok 60 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4-rtc-gclk # SKIP
1149 10:52:46.428106 # ok 61 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4fw-gclk # SKIP
1150 10:52:46.499941 # ok 62 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4hs-gclk # SKIP
1151 10:52:46.571048 # ok 63 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4ls-gclk # SKIP
1152 10:52:46.647935 # ok 64 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-lcd-gclk@534 # SKIP
1153 10:52:46.718187 # ok 65 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmc # SKIP
1154 10:52:46.790108 # ok 66 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmu-fck-1@914 # SKIP
1155 10:52:46.862137 # ok 67 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-pruss-ocp-gclk@530 # SKIP
1156 10:52:46.931600 # ok 68 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-sysclk-div # SKIP
1157 10:52:46.999854 # ok 69 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-tclkin # SKIP
1158 10:52:47.076041 # ok 70 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer1-fck@528 # SKIP
1159 10:52:47.148581 # ok 71 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer2-fck@508 # SKIP
1160 10:52:47.218663 # ok 72 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer3-fck@50c # SKIP
1161 10:52:47.291097 # ok 73 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer4-fck@510 # SKIP
1162 10:52:47.363658 # ok 74 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer5-fck@518 # SKIP
1163 10:52:47.435459 # ok 75 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer6-fck@51c # SKIP
1164 10:52:47.506859 # ok 76 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer7-fck@504 # SKIP
1165 10:52:47.578274 # ok 77 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-usbotg-fck-8@47c # SKIP
1166 10:52:47.649642 # ok 78 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-19200000 # SKIP
1167 10:52:47.721694 # ok 79 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-24000000 # SKIP
1168 10:52:47.793657 # ok 80 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-25000000 # SKIP
1169 10:52:47.865110 # ok 81 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-26000000 # SKIP
1170 10:52:47.940959 # ok 82 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-wdt1-fck@538 # SKIP
1171 10:52:48.008641 # ok 83 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@488 # SKIP
1172 10:52:48.081046 # ok 84 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@48c # SKIP
1173 10:52:48.153567 # ok 85 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@490 # SKIP
1174 10:52:48.229164 # ok 86 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@494 # SKIP
1175 10:52:48.300960 # ok 87 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@498 # SKIP
1176 10:52:48.371448 # ok 88 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c # SKIP
1177 10:52:48.442903 # ok 89 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fck-div@0 # SKIP
1178 10:52:48.518552 # ok 90 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fclk-clksel@1 # SKIP
1179 10:52:48.582958 # ok 91 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700 # SKIP
1180 10:52:48.657274 # ok 92 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2-div@3 # SKIP
1181 10:52:48.729685 # ok 93 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2@7 # SKIP
1182 10:52:48.806921 # ok 94 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-sysclkout-pre@0 # SKIP
1183 10:52:48.824754 # ok 95 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1000
1184 10:52:48.848412 # ok 96 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1100
1185 10:52:48.872528 # ok 97 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1200
1186 10:52:48.895755 # ok 98 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@c00
1187 10:52:48.919280 # ok 99 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@d00
1188 10:52:48.944539 # ok 100 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@e00
1189 10:52:48.968165 # ok 101 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@f00
1190 10:52:48.994330 # ok 102 /ocp/interconnect@44c00000/segment@200000/target-module@10000
1191 10:52:49.108838 # not ok 103 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0
1192 10:52:49.134754 # ok 104 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/control@620
1193 10:52:49.156042 # ok 105 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/dma-router@f90
1194 10:52:49.179455 # ok 106 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800
1195 10:52:49.289979 # not ok 107 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0
1196 10:52:49.370428 # ok 108 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-adc-tsc-fck # SKIP
1197 10:52:49.441698 # ok 109 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-aes0-fck # SKIP
1198 10:52:49.510051 # ok 110 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan0-fck # SKIP
1199 10:52:49.582076 # ok 111 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan1-fck # SKIP
1200 10:52:49.658972 # ok 112 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp0-fck # SKIP
1201 10:52:49.726825 # ok 113 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp1-fck # SKIP
1202 10:52:49.801135 # ok 114 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-rng-fck # SKIP
1203 10:52:49.878331 # ok 115 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sha0-fck # SKIP
1204 10:52:49.956815 # ok 116 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex0-fck # SKIP
1205 10:52:50.027475 # ok 117 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex1-fck # SKIP
1206 10:52:50.099457 # ok 118 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sys-clkin-22@40 # SKIP
1207 10:52:50.170785 # ok 119 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664 # SKIP
1208 10:52:50.252363 # ok 120 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm0-tbclk@0 # SKIP
1209 10:52:50.320117 # ok 121 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm1-tbclk@1 # SKIP
1210 10:52:50.400379 # ok 122 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm2-tbclk@2 # SKIP
1211 10:52:50.418614 # ok 123 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/phy-gmii-sel
1212 10:52:50.489453 # not ok 124 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/wkup_m3_ipc@1324
1213 10:52:50.560104 # not ok 125 /ocp/interconnect@44c00000/segment@200000/target-module@31000
1214 10:52:50.638109 # ok 126 /ocp/interconnect@44c00000/segment@200000/target-module@31000/timer@0 # SKIP
1215 10:52:50.658795 # ok 127 /ocp/interconnect@44c00000/segment@200000/target-module@35000
1216 10:52:50.728616 # not ok 128 /ocp/interconnect@44c00000/segment@200000/target-module@35000/wdt@0
1217 10:52:50.751708 # ok 129 /ocp/interconnect@44c00000/segment@200000/target-module@3e000
1218 10:52:50.826440 # not ok 130 /ocp/interconnect@44c00000/segment@200000/target-module@3e000/rtc@0
1219 10:52:50.847728 # ok 131 /ocp/interconnect@44c00000/segment@200000/target-module@7000
1220 10:52:50.869245 # ok 132 /ocp/interconnect@44c00000/segment@200000/target-module@7000/gpio@0
1221 10:52:50.892252 # ok 133 /ocp/interconnect@44c00000/segment@200000/target-module@9000
1222 10:52:50.917560 # ok 134 /ocp/interconnect@44c00000/segment@200000/target-module@9000/serial@0
1223 10:52:50.940621 # ok 135 /ocp/interconnect@44c00000/segment@200000/target-module@b000
1224 10:52:50.969347 # ok 136 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0
1225 10:52:50.988635 # ok 137 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/eeprom@50
1226 10:52:51.064798 # ok 138 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/eeprom@50/nvmem-layout # SKIP
1227 10:52:51.086464 # ok 139 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
1228 10:52:51.110826 # ok 140 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24
1229 10:52:51.183445 # not ok 141 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/charger
1230 10:52:51.253748 # not ok 142 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/pwrbutton
1231 10:52:51.274831 # ok 143 /ocp/interconnect@44c00000/segment@200000/target-module@d000
1232 10:52:51.380633 # not ok 144 /ocp/interconnect@47c00000
1233 10:52:51.447842 # not ok 145 /ocp/interconnect@47c00000/segment@0
1234 10:52:51.473072 # ok 146 /ocp/interconnect@48000000
1235 10:52:51.496855 # ok 147 /ocp/interconnect@48000000/segment@0
1236 10:52:51.517430 # ok 148 /ocp/interconnect@48000000/segment@0/target-module@22000
1237 10:52:51.540324 # ok 149 /ocp/interconnect@48000000/segment@0/target-module@24000
1238 10:52:51.564432 # ok 150 /ocp/interconnect@48000000/segment@0/target-module@2a000
1239 10:52:51.588412 # ok 151 /ocp/interconnect@48000000/segment@0/target-module@30000
1240 10:52:51.615757 # ok 152 /ocp/interconnect@48000000/segment@0/target-module@38000
1241 10:52:51.639066 # ok 153 /ocp/interconnect@48000000/segment@0/target-module@38000/mcasp@0
1242 10:52:51.666167 # ok 154 /ocp/interconnect@48000000/segment@0/target-module@3c000
1243 10:52:51.736758 # not ok 155 /ocp/interconnect@48000000/segment@0/target-module@40000
1244 10:52:51.810037 # ok 156 /ocp/interconnect@48000000/segment@0/target-module@40000/timer@0 # SKIP
1245 10:52:51.827252 # ok 157 /ocp/interconnect@48000000/segment@0/target-module@42000
1246 10:52:51.851788 # ok 158 /ocp/interconnect@48000000/segment@0/target-module@42000/timer@0
1247 10:52:51.874040 # ok 159 /ocp/interconnect@48000000/segment@0/target-module@44000
1248 10:52:51.898237 # ok 160 /ocp/interconnect@48000000/segment@0/target-module@44000/timer@0
1249 10:52:51.921375 # ok 161 /ocp/interconnect@48000000/segment@0/target-module@46000
1250 10:52:51.945159 # ok 162 /ocp/interconnect@48000000/segment@0/target-module@46000/timer@0
1251 10:52:51.968564 # ok 163 /ocp/interconnect@48000000/segment@0/target-module@48000
1252 10:52:51.992598 # ok 164 /ocp/interconnect@48000000/segment@0/target-module@48000/timer@0
1253 10:52:52.018834 # ok 165 /ocp/interconnect@48000000/segment@0/target-module@4a000
1254 10:52:52.041374 # ok 166 /ocp/interconnect@48000000/segment@0/target-module@4a000/timer@0
1255 10:52:52.064007 # ok 167 /ocp/interconnect@48000000/segment@0/target-module@4c000
1256 10:52:52.087879 # ok 168 /ocp/interconnect@48000000/segment@0/target-module@4c000/gpio@0
1257 10:52:52.110855 # ok 169 /ocp/interconnect@48000000/segment@0/target-module@60000
1258 10:52:52.134571 # ok 170 /ocp/interconnect@48000000/segment@0/target-module@60000/mmc@0
1259 10:52:52.157223 # ok 171 /ocp/interconnect@48000000/segment@0/target-module@c8000
1260 10:52:52.182313 # ok 172 /ocp/interconnect@48000000/segment@0/target-module@c8000/mailbox@0
1261 10:52:52.204541 # ok 173 /ocp/interconnect@48000000/segment@0/target-module@ca000
1262 10:52:52.231581 # ok 174 /ocp/interconnect@48000000/segment@0/target-module@ca000/spinlock@0
1263 10:52:52.249621 # ok 175 /ocp/interconnect@48000000/segment@100000
1264 10:52:52.275381 # ok 176 /ocp/interconnect@48000000/segment@100000/target-module@9c000
1265 10:52:52.300315 # ok 177 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0
1266 10:52:52.373329 # not ok 178 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/eeprom@54
1267 10:52:52.446724 # ok 179 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/eeprom@54/nvmem-layout # SKIP
1268 10:52:52.516763 # not ok 180 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/eeprom@55
1269 10:52:52.590455 # ok 181 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/eeprom@55/nvmem-layout # SKIP
1270 10:52:52.666159 # not ok 182 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/eeprom@56
1271 10:52:52.735674 # ok 183 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/eeprom@56/nvmem-layout # SKIP
1272 10:52:52.806424 # not ok 184 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/eeprom@57
1273 10:52:52.879805 # ok 185 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/eeprom@57/nvmem-layout # SKIP
1274 10:52:52.904932 # ok 186 /ocp/interconnect@48000000/segment@100000/target-module@a0000
1275 10:52:52.928330 # ok 187 /ocp/interconnect@48000000/segment@100000/target-module@a6000
1276 10:52:52.948028 # ok 188 /ocp/interconnect@48000000/segment@100000/target-module@a8000
1277 10:52:52.970994 # ok 189 /ocp/interconnect@48000000/segment@100000/target-module@aa000
1278 10:52:52.994103 # ok 190 /ocp/interconnect@48000000/segment@100000/target-module@ac000
1279 10:52:53.018424 # ok 191 /ocp/interconnect@48000000/segment@100000/target-module@ac000/gpio@0
1280 10:52:53.041718 # ok 192 /ocp/interconnect@48000000/segment@100000/target-module@ae000
1281 10:52:53.069498 # ok 193 /ocp/interconnect@48000000/segment@100000/target-module@ae000/gpio@0
1282 10:52:53.090247 # ok 194 /ocp/interconnect@48000000/segment@100000/target-module@cc000
1283 10:52:53.116937 # ok 195 /ocp/interconnect@48000000/segment@100000/target-module@d0000
1284 10:52:53.138952 # ok 196 /ocp/interconnect@48000000/segment@100000/target-module@d8000
1285 10:52:53.164978 # ok 197 /ocp/interconnect@48000000/segment@100000/target-module@d8000/mmc@0
1286 10:52:53.186967 # ok 198 /ocp/interconnect@48000000/segment@200000
1287 10:52:53.206814 # ok 199 /ocp/interconnect@48000000/segment@200000/target-module@0
1288 10:52:53.284746 # ok 200 /ocp/interconnect@48000000/segment@200000/target-module@0/mpu@0 # SKIP
1289 10:52:53.305553 # ok 201 /ocp/interconnect@48000000/segment@300000
1290 10:52:53.327668 # ok 202 /ocp/interconnect@48000000/segment@300000/target-module@0
1291 10:52:53.354712 # ok 203 /ocp/interconnect@48000000/segment@300000/target-module@10000
1292 10:52:53.374410 # ok 204 /ocp/interconnect@48000000/segment@300000/target-module@10000/rng@0
1293 10:52:53.397788 # ok 205 /ocp/interconnect@48000000/segment@300000/target-module@2000
1294 10:52:53.425952 # ok 206 /ocp/interconnect@48000000/segment@300000/target-module@4000
1295 10:52:53.450085 # ok 207 /ocp/interconnect@48000000/segment@300000/target-module@e000
1296 10:52:53.519199 # not ok 208 /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
1297 10:52:53.537740 # ok 209 /ocp/interconnect@4a000000
1298 10:52:53.560528 # ok 210 /ocp/interconnect@4a000000/segment@0
1299 10:52:53.586519 # ok 211 /ocp/interconnect@4a000000/segment@0/target-module@100000
1300 10:52:53.615607 # ok 212 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0
1301 10:52:53.639465 # ok 213 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0/mdio@1000
1302 10:52:53.661560 # ok 214 /ocp/interconnect@4a000000/segment@0/target-module@300000
1303 10:52:53.729918 # not ok 215 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0
1304 10:52:53.840711 # ok 216 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/cfg@26000 # SKIP
1305 10:52:53.911784 # not ok 217 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/interrupt-controller@20000
1306 10:52:54.014166 # ok 218 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/mii-rt@32000 # SKIP
1307 10:52:54.084595 # not ok 219 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@34000
1308 10:52:54.156254 # not ok 220 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@38000
1309 10:52:54.255682 # not ok 221 /ocp/interconnect@4b140000
1310 10:52:54.329730 # not ok 222 /ocp/interconnect@4b140000/segment@0
1311 10:52:54.403365 # ok 223 /ocp/interrupt-controller@48200000 # SKIP
1312 10:52:54.425108 # ok 224 /ocp/target-module@40300000
1313 10:52:54.445425 # ok 225 /ocp/target-module@40300000/sram@0
1314 10:52:54.517710 # ok 226 /ocp/target-module@40300000/sram@0/pm-code-sram@0 # SKIP
1315 10:52:54.589569 # ok 227 /ocp/target-module@40300000/sram@0/pm-data-sram@1000 # SKIP
1316 10:52:54.612459 # ok 228 /ocp/target-module@47400000
1317 10:52:54.637602 # ok 229 /ocp/target-module@47400000/dma-controller@2000
1318 10:52:54.656186 # ok 230 /ocp/target-module@47400000/usb-phy@1300
1319 10:52:54.678315 # ok 231 /ocp/target-module@47400000/usb-phy@1b00
1320 10:52:54.705492 # ok 232 /ocp/target-module@47400000/usb@1400
1321 10:52:54.726763 # ok 233 /ocp/target-module@47400000/usb@1800
1322 10:52:54.745575 # ok 234 /ocp/target-module@47810000
1323 10:52:54.768148 # ok 235 /ocp/target-module@49000000
1324 10:52:54.795018 # ok 236 /ocp/target-module@49000000/dma@0
1325 10:52:54.815973 # ok 237 /ocp/target-module@49800000
1326 10:52:54.840781 # ok 238 /ocp/target-module@49800000/dma@0
1327 10:52:54.861754 # ok 239 /ocp/target-module@49900000
1328 10:52:54.881377 # ok 240 /ocp/target-module@49900000/dma@0
1329 10:52:54.905211 # ok 241 /ocp/target-module@49a00000
1330 10:52:54.927227 # ok 242 /ocp/target-module@49a00000/dma@0
1331 10:52:54.953208 # ok 243 /ocp/target-module@4c000000
1332 10:52:55.025111 # not ok 244 /ocp/target-module@4c000000/emif@0
1333 10:52:55.041189 # ok 245 /ocp/target-module@50000000
1334 10:52:55.065055 # ok 246 /ocp/target-module@53100000
1335 10:52:55.135289 # not ok 247 /ocp/target-module@53100000/sham@0
1336 10:52:55.157773 # ok 248 /ocp/target-module@53500000
1337 10:52:55.232911 # not ok 249 /ocp/target-module@53500000/aes@0
1338 10:52:55.254449 # ok 250 /ocp/target-module@56000000
1339 10:52:55.357182 # ok 251 /ocp/target-module@56000000/gpu@0 # SKIP
1340 10:52:55.424076 # ok 252 /opp-table # SKIP
1341 10:52:55.496732 # ok 253 /soc # SKIP
1342 10:52:55.513637 # ok 254 /sound
1343 10:52:55.542857 # ok 255 /target-module@4b000000
1344 10:52:55.563063 # ok 256 /target-module@4b000000/target-module@140000
1345 10:52:55.583994 # ok 257 /target-module@4b000000/target-module@140000/pmu@0
1346 10:52:55.592613 # # Totals: pass:117 fail:27 xfail:0 xpass:0 skip:113 error:0
1347 10:52:55.600272 not ok 1 selftests: dt: test_unprobed_devices.sh # exit=1
1348 10:52:57.741286 dt_test_unprobed_devices_sh_ skip
1349 10:52:57.746680 dt_test_unprobed_devices_sh_clk_mcasp0 pass
1350 10:52:57.752306 dt_test_unprobed_devices_sh_clk_mcasp0_fixed skip
1351 10:52:57.752820 dt_test_unprobed_devices_sh_cpus_cpu_0 skip
1352 10:52:57.757993 dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate skip
1353 10:52:57.763527 dt_test_unprobed_devices_sh_fixedregulator0 pass
1354 10:52:57.769060 dt_test_unprobed_devices_sh_leds pass
1355 10:52:57.769489 dt_test_unprobed_devices_sh_ocp pass
1356 10:52:57.774745 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 pass
1357 10:52:57.780336 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 pass
1358 10:52:57.785986 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 pass
1359 10:52:57.797148 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 pass
1360 10:52:57.802805 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 fail
1361 10:52:57.808360 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 pass
1362 10:52:57.819588 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 pass
1363 10:52:57.825158 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 fail
1364 10:52:57.836343 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 skip
1365 10:52:57.847662 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 skip
1366 10:52:57.858872 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 skip
1367 10:52:57.864458 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c skip
1368 10:52:57.875677 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 skip
1369 10:52:57.886887 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c skip
1370 10:52:57.898130 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 skip
1371 10:52:57.909298 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 skip
1372 10:52:57.915083 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 skip
1373 10:52:57.928016 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 skip
1374 10:52:57.937509 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 skip
1375 10:52:57.948705 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 skip
1376 10:52:57.959889 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 skip
1377 10:52:57.965456 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 skip
1378 10:52:57.976652 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 skip
1379 10:52:57.987838 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 skip
1380 10:52:57.999073 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 skip
1381 10:52:58.004719 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 skip
1382 10:52:58.015852 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 skip
1383 10:52:58.027091 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 skip
1384 10:52:58.038218 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 skip
1385 10:52:58.049574 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz skip
1386 10:52:58.055151 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 skip
1387 10:52:58.066205 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k skip
1388 10:52:58.077381 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k skip
1389 10:52:58.088599 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk skip
1390 10:52:58.099792 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 skip
1391 10:52:58.111018 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 skip
1392 10:52:58.122174 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 skip
1393 10:52:58.133359 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 skip
1394 10:52:58.144571 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 skip
1395 10:52:58.155734 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 skip
1396 10:52:58.166931 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 skip
1397 10:52:58.178137 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 skip
1398 10:52:58.195161 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 skip
1399 10:52:58.201505 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 skip
1400 10:52:58.212679 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 skip
1401 10:52:58.223903 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm skip
1402 10:52:58.235054 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac skip
1403 10:52:58.246228 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c skip
1404 10:52:58.257401 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 skip
1405 10:52:58.268575 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk skip
1406 10:52:58.279806 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk skip
1407 10:52:58.291067 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk skip
1408 10:52:58.302189 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk skip
1409 10:52:58.313357 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk skip
1410 10:52:58.318994 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk skip
1411 10:52:58.330259 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 skip
1412 10:52:58.341407 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc skip
1413 10:52:58.352607 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 skip
1414 10:52:58.363758 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 skip
1415 10:52:58.375017 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div skip
1416 10:52:58.386161 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin skip
1417 10:52:58.397368 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 skip
1418 10:52:58.408647 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 skip
1419 10:52:58.419787 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c skip
1420 10:52:58.430906 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 skip
1421 10:52:58.442287 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 skip
1422 10:52:58.453388 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c skip
1423 10:52:58.464603 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 skip
1424 10:52:58.475767 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c skip
1425 10:52:58.486967 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 skip
1426 10:52:58.498212 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 skip
1427 10:52:58.509363 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 skip
1428 10:52:58.520592 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 skip
1429 10:52:58.526308 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 skip
1430 10:52:58.537352 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 skip
1431 10:52:58.548664 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c skip
1432 10:52:58.559742 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 skip
1433 10:52:58.570902 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 skip
1434 10:52:58.576612 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 skip
1435 10:52:58.587685 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c skip
1436 10:52:58.598903 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 skip
1437 10:52:58.615673 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 skip
1438 10:52:58.621336 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 skip
1439 10:52:58.632564 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 skip
1440 10:52:58.643769 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 skip
1441 10:52:58.660565 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 skip
1442 10:52:58.666221 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 pass
1443 10:52:58.677329 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 pass
1444 10:52:58.688554 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 pass
1445 10:52:58.694172 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 pass
1446 10:52:58.705312 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 pass
1447 10:52:58.716469 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 pass
1448 10:52:58.722058 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 pass
1449 10:52:58.733290 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 pass
1450 10:52:58.738700 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 fail
1451 10:52:58.749926 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 pass
1452 10:52:58.761196 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 pass
1453 10:52:58.772312 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 pass
1454 10:52:58.777942 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 fail
1455 10:52:58.794693 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck skip
1456 10:52:58.805889 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck skip
1457 10:52:58.817051 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck skip
1458 10:52:58.828257 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck skip
1459 10:52:58.839536 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck skip
1460 10:52:58.850708 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck skip
1461 10:52:58.861902 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck skip
1462 10:52:58.873099 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck skip
1463 10:52:58.884301 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck skip
1464 10:52:58.901079 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck skip
1465 10:52:58.912271 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 skip
1466 10:52:58.923463 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 skip
1467 10:52:58.934650 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 skip
1468 10:52:58.951439 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 skip
1469 10:52:58.962614 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 skip
1470 10:52:58.973769 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel pass
1471 10:52:58.985009 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 fail
1472 10:52:58.990640 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 fail
1473 10:52:59.001884 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 skip
1474 10:52:59.007447 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 pass
1475 10:52:59.018565 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 fail
1476 10:52:59.024234 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 pass
1477 10:52:59.035370 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 fail
1478 10:52:59.040996 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 pass
1479 10:52:59.052179 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 pass
1480 10:52:59.063348 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 pass
1481 10:52:59.068972 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 pass
1482 10:52:59.080179 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 pass
1483 10:52:59.085856 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 pass
1484 10:52:59.096995 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_eeprom_50 pass
1485 10:52:59.108185 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_eeprom_50_nvmem-layout skip
1486 10:52:59.119356 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 pass
1487 10:52:59.124999 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 pass
1488 10:52:59.136143 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger fail
1489 10:52:59.147343 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton fail
1490 10:52:59.153027 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 pass
1491 10:52:59.158601 dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 fail
1492 10:52:59.164220 dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 fail
1493 10:52:59.169721 dt_test_unprobed_devices_sh_ocp_interconnect_48000000 pass
1494 10:52:59.175572 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 pass
1495 10:52:59.186835 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 pass
1496 10:52:59.192199 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 pass
1497 10:52:59.203282 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 pass
1498 10:52:59.208929 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 pass
1499 10:52:59.214536 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 pass
1500 10:52:59.225743 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 pass
1501 10:52:59.231287 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 pass
1502 10:52:59.242345 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 fail
1503 10:52:59.247928 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 skip
1504 10:52:59.259093 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 pass
1505 10:52:59.264726 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 pass
1506 10:52:59.275966 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 pass
1507 10:52:59.281522 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 pass
1508 10:52:59.292705 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 pass
1509 10:52:59.298300 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 pass
1510 10:52:59.309578 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 pass
1511 10:52:59.315146 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 pass
1512 10:52:59.320669 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 pass
1513 10:52:59.331843 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 pass
1514 10:52:59.337487 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 pass
1515 10:52:59.348768 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 pass
1516 10:52:59.354267 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 pass
1517 10:52:59.365485 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 pass
1518 10:52:59.371091 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 pass
1519 10:52:59.382170 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 pass
1520 10:52:59.387959 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 pass
1521 10:52:59.399035 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 pass
1522 10:52:59.404744 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 pass
1523 10:52:59.410354 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 pass
1524 10:52:59.421479 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 pass
1525 10:52:59.432716 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_54 fail
1526 10:52:59.443830 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_54_nvmem-layout skip
1527 10:52:59.449497 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_55 fail
1528 10:52:59.460732 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_55_nvmem-layout skip
1529 10:52:59.471843 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_56 fail
1530 10:52:59.483038 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_56_nvmem-layout skip
1531 10:52:59.494290 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_57 fail
1532 10:52:59.505503 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_57_nvmem-layout skip
1533 10:52:59.511079 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 pass
1534 10:52:59.522235 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 pass
1535 10:52:59.527822 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 pass
1536 10:52:59.538950 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 pass
1537 10:52:59.544688 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 pass
1538 10:52:59.555872 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 pass
1539 10:52:59.561418 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 pass
1540 10:52:59.572689 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 pass
1541 10:52:59.578175 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 pass
1542 10:52:59.589328 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 pass
1543 10:52:59.594999 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 pass
1544 10:52:59.606147 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 pass
1545 10:52:59.611778 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 pass
1546 10:52:59.617371 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 pass
1547 10:52:59.628511 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 skip
1548 10:52:59.634178 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 pass
1549 10:52:59.645369 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 pass
1550 10:52:59.650944 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 pass
1551 10:52:59.662145 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 pass
1552 10:52:59.667736 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 pass
1553 10:52:59.678853 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 pass
1554 10:52:59.684570 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 pass
1555 10:52:59.695754 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 fail
1556 10:52:59.696315 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 pass
1557 10:52:59.706866 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 pass
1558 10:52:59.712501 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 pass
1559 10:52:59.723664 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 pass
1560 10:52:59.729314 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 pass
1561 10:52:59.740415 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 pass
1562 10:52:59.746093 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 fail
1563 10:52:59.757221 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 skip
1564 10:52:59.768483 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 fail
1565 10:52:59.779657 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 skip
1566 10:52:59.785267 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 fail
1567 10:52:59.796498 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 fail
1568 10:52:59.802143 dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 fail
1569 10:52:59.807699 dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 fail
1570 10:52:59.813282 dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 skip
1571 10:52:59.818894 dt_test_unprobed_devices_sh_ocp_target-module_40300000 pass
1572 10:52:59.824502 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 pass
1573 10:52:59.830222 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 skip
1574 10:52:59.841347 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 skip
1575 10:52:59.846964 dt_test_unprobed_devices_sh_ocp_target-module_47400000 pass
1576 10:52:59.852504 dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 pass
1577 10:52:59.858120 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 pass
1578 10:52:59.863682 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 pass
1579 10:52:59.869319 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 pass
1580 10:52:59.880487 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 pass
1581 10:52:59.886086 dt_test_unprobed_devices_sh_ocp_target-module_47810000 pass
1582 10:52:59.886443 dt_test_unprobed_devices_sh_ocp_target-module_49000000 pass
1583 10:52:59.897295 dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 pass
1584 10:52:59.897663 dt_test_unprobed_devices_sh_ocp_target-module_49800000 pass
1585 10:52:59.908495 dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 pass
1586 10:52:59.908879 dt_test_unprobed_devices_sh_ocp_target-module_49900000 pass
1587 10:52:59.919729 dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 pass
1588 10:52:59.920274 dt_test_unprobed_devices_sh_ocp_target-module_49a00000 pass
1589 10:52:59.930864 dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 pass
1590 10:52:59.931391 dt_test_unprobed_devices_sh_ocp_target-module_4c000000 pass
1591 10:52:59.942101 dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 fail
1592 10:52:59.942497 dt_test_unprobed_devices_sh_ocp_target-module_50000000 pass
1593 10:52:59.947711 dt_test_unprobed_devices_sh_ocp_target-module_53100000 pass
1594 10:52:59.953351 dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 fail
1595 10:52:59.958902 dt_test_unprobed_devices_sh_ocp_target-module_53500000 pass
1596 10:52:59.964531 dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 fail
1597 10:52:59.970095 dt_test_unprobed_devices_sh_ocp_target-module_56000000 pass
1598 10:52:59.975696 dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 skip
1599 10:52:59.981307 dt_test_unprobed_devices_sh_opp-table skip
1600 10:52:59.986930 dt_test_unprobed_devices_sh_soc skip
1601 10:52:59.987480 dt_test_unprobed_devices_sh_sound pass
1602 10:52:59.992512 dt_test_unprobed_devices_sh_target-module_4b000000 pass
1603 10:53:00.003780 dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 pass
1604 10:53:00.009303 dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 pass
1605 10:53:00.009672 dt_test_unprobed_devices_sh fail
1606 10:53:00.014970 + ../../utils/send-to-lava.sh ./output/result.txt
1607 10:53:00.021534 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-dt RESULT=pass>
1608 10:53:00.022383 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-dt RESULT=pass
1610 10:53:00.031473 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip>
1611 10:53:00.032086 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip
1613 10:53:00.123526 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass>
1614 10:53:00.124174 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass
1616 10:53:00.215327 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip>
1617 10:53:00.215973 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip
1619 10:53:00.306727 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip>
1620 10:53:00.307313 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip
1622 10:53:00.400562 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip>
1623 10:53:00.401479 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip
1625 10:53:00.493616 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass>
1626 10:53:00.494464 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass
1628 10:53:00.583642 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass>
1629 10:53:00.584503 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass
1631 10:53:00.675460 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass>
1632 10:53:00.676331 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass
1634 10:53:00.769282 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass>
1635 10:53:00.770028 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass
1637 10:53:00.869008 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass>
1638 10:53:00.869861 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass
1640 10:53:00.965383 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass>
1641 10:53:00.966165 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass
1643 10:53:01.056417 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass>
1644 10:53:01.057275 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass
1646 10:53:01.148251 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail>
1647 10:53:01.149027 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail
1649 10:53:01.235439 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass>
1650 10:53:01.236233 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass
1652 10:53:01.335519 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass>
1653 10:53:01.336265 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass
1655 10:53:01.428602 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail>
1656 10:53:01.429308 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail
1658 10:53:01.518090 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip>
1659 10:53:01.520933 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip
1661 10:53:01.608820 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip>
1662 10:53:01.609641 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip
1664 10:53:01.702880 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip>
1665 10:53:01.703679 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip
1667 10:53:01.795397 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip>
1668 10:53:01.796164 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip
1670 10:53:01.886963 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip>
1671 10:53:01.887724 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip
1673 10:53:01.979158 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip>
1674 10:53:01.979920 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip
1676 10:53:02.070203 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip>
1677 10:53:02.071051 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip
1679 10:53:02.162389 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip>
1680 10:53:02.163173 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip
1682 10:53:02.264070 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip>
1683 10:53:02.264872 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip
1685 10:53:02.364784 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip>
1686 10:53:02.365573 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip
1688 10:53:02.458874 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip>
1689 10:53:02.459677 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip
1691 10:53:02.547868 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip>
1692 10:53:02.548663 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip
1694 10:53:02.639096 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip>
1695 10:53:02.639883 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip
1697 10:53:02.729065 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip>
1698 10:53:02.729865 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip
1700 10:53:02.819710 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip>
1701 10:53:02.820493 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip
1703 10:53:02.911488 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip>
1704 10:53:02.912334 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip
1706 10:53:03.004568 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip>
1707 10:53:03.005374 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip
1709 10:53:03.096885 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip>
1710 10:53:03.097774 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip
1712 10:53:03.189186 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip>
1713 10:53:03.189991 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip
1715 10:53:03.279784 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip>
1716 10:53:03.280558 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip
1718 10:53:03.374088 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip>
1719 10:53:03.374906 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip
1721 10:53:03.469462 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip>
1722 10:53:03.470408 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip
1724 10:53:03.559604 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip>
1725 10:53:03.560451 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip
1727 10:53:03.650671 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip>
1728 10:53:03.651462 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip
1730 10:53:03.739645 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip>
1731 10:53:03.740419 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip
1733 10:53:03.831594 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip>
1734 10:53:03.832345 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip
1736 10:53:03.922543 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip>
1737 10:53:03.923266 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip
1739 10:53:04.013487 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip>
1740 10:53:04.014243 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip
1742 10:53:04.105341 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip>
1743 10:53:04.106147 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip
1745 10:53:04.197790 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip>
1746 10:53:04.198571 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip
1748 10:53:04.291172 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip>
1749 10:53:04.291937 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip
1751 10:53:04.382896 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip>
1752 10:53:04.383695 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip
1754 10:53:04.474770 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip>
1755 10:53:04.475606 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip
1757 10:53:04.566069 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip>
1758 10:53:04.566920 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip
1760 10:53:04.656725 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip>
1761 10:53:04.657514 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip
1763 10:53:04.750201 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip>
1764 10:53:04.751108 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip
1766 10:53:04.841723 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip>
1767 10:53:04.842665 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip
1769 10:53:04.943727 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip>
1770 10:53:04.944602 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip
1772 10:53:05.036222 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip>
1773 10:53:05.037139 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip
1775 10:53:05.129443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip>
1776 10:53:05.130407 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip
1778 10:53:05.223520 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip>
1779 10:53:05.224423 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip
1781 10:53:05.313388 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip>
1782 10:53:05.314295 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip
1784 10:53:05.405502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip>
1785 10:53:05.406395 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip
1787 10:53:05.496449 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip>
1788 10:53:05.497409 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip
1790 10:53:05.586411 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip>
1791 10:53:05.587306 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip
1793 10:53:05.677378 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip>
1794 10:53:05.678252 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip
1796 10:53:05.768945 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip>
1797 10:53:05.769776 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip
1799 10:53:05.860368 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip>
1800 10:53:05.861197 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip
1802 10:53:05.950949 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip>
1803 10:53:05.951775 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip
1805 10:53:06.044198 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip>
1806 10:53:06.045076 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip
1808 10:53:06.137625 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip>
1809 10:53:06.139878 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip
1811 10:53:06.229898 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip>
1812 10:53:06.230761 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip
1814 10:53:06.319324 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip>
1815 10:53:06.320189 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip
1817 10:53:06.408178 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip>
1818 10:53:06.409091 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip
1820 10:53:06.500585 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip>
1821 10:53:06.501511 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip
1823 10:53:06.590230 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip>
1824 10:53:06.591135 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip
1826 10:53:06.682687 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip>
1827 10:53:06.683535 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip
1829 10:53:06.775590 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip>
1830 10:53:06.776422 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip
1832 10:53:06.868252 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip>
1833 10:53:06.869198 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip
1835 10:53:06.962043 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip>
1836 10:53:06.962909 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip
1838 10:53:07.053023 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip>
1839 10:53:07.053908 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip
1841 10:53:07.145061 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip>
1842 10:53:07.145913 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip
1844 10:53:07.237826 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip>
1845 10:53:07.238662 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip
1847 10:53:07.330912 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip>
1848 10:53:07.331846 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip
1850 10:53:07.431399 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip>
1851 10:53:07.432326 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip
1853 10:53:07.533640 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip>
1854 10:53:07.534611 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip
1856 10:53:07.634643 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip>
1857 10:53:07.635375 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip
1859 10:53:07.726036 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip>
1860 10:53:07.726639 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip
1862 10:53:07.820011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip>
1863 10:53:07.820840 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip
1865 10:53:07.921526 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip>
1866 10:53:07.922166 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip
1868 10:53:08.022932 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip>
1869 10:53:08.023807 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip
1871 10:53:08.114893 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip>
1872 10:53:08.115752 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip
1874 10:53:08.210111 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip>
1875 10:53:08.210966 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip
1877 10:53:08.300424 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip>
1878 10:53:08.301295 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip
1880 10:53:08.390363 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip>
1881 10:53:08.391194 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip
1883 10:53:08.484294 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip>
1884 10:53:08.485184 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip
1886 10:53:08.576349 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip>
1887 10:53:08.577275 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip
1889 10:53:08.669668 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip>
1890 10:53:08.670762 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip
1892 10:53:08.759801 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass>
1893 10:53:08.760673 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass
1895 10:53:08.853022 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass>
1896 10:53:08.854150 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass
1898 10:53:08.948631 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass>
1899 10:53:08.949735 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass
1901 10:53:09.048272 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass>
1902 10:53:09.049367 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass
1904 10:53:09.139189 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass>
1905 10:53:09.140354 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass
1907 10:53:09.231432 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass>
1908 10:53:09.232510 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass
1910 10:53:09.324160 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass>
1911 10:53:09.325034 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass
1913 10:53:09.414817 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass>
1914 10:53:09.415775 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass
1916 10:53:09.671271 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail>
1917 10:53:09.671877 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail
1919 10:53:09.776307 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass>
1920 10:53:09.777191 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass
1922 10:53:09.868950 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass>
1923 10:53:09.869883 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass
1925 10:53:09.960066 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass>
1926 10:53:09.960888 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass
1928 10:53:10.052036 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail>
1929 10:53:10.052951 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail
1931 10:53:10.148382 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip>
1932 10:53:10.149275 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip
1934 10:53:10.240576 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip>
1935 10:53:10.241428 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip
1937 10:53:10.331864 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip>
1938 10:53:10.332739 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip
1940 10:53:10.424794 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip>
1941 10:53:10.425724 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip
1943 10:53:10.518499 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip>
1944 10:53:10.519411 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip
1946 10:53:10.613378 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip>
1947 10:53:10.614351 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip
1949 10:53:10.706738 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip>
1950 10:53:10.707623 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip
1952 10:53:10.799073 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip>
1953 10:53:10.799969 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip
1955 10:53:10.890733 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip>
1956 10:53:10.891665 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip
1958 10:53:10.984041 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip>
1959 10:53:10.984968 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip
1961 10:53:11.085327 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip>
1962 10:53:11.086310 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip
1964 10:53:11.185308 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip>
1965 10:53:11.186267 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip
1967 10:53:11.278636 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip
1969 10:53:11.281599 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip>
1970 10:53:11.371454 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip
1972 10:53:11.374416 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip>
1973 10:53:11.464969 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip
1975 10:53:11.468114 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip>
1976 10:53:11.557556 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass>
1977 10:53:11.558535 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass
1979 10:53:11.651549 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail>
1980 10:53:11.652409 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail
1982 10:53:11.742409 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail>
1983 10:53:11.743310 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail
1985 10:53:11.837350 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip>
1986 10:53:11.838252 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip
1988 10:53:11.928265 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass>
1989 10:53:11.929139 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass
1991 10:53:12.022800 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail>
1992 10:53:12.023733 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail
1994 10:53:12.116082 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass>
1995 10:53:12.116971 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass
1997 10:53:12.207461 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail>
1998 10:53:12.208404 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail
2000 10:53:12.299293 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass>
2001 10:53:12.300201 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass
2003 10:53:12.391640 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass>
2004 10:53:12.392544 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass
2006 10:53:12.484195 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass>
2007 10:53:12.485109 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass
2009 10:53:12.578786 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass>
2010 10:53:12.579649 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass
2012 10:53:12.671562 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass>
2013 10:53:12.672432 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass
2015 10:53:12.774173 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass>
2016 10:53:12.774974 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass
2018 10:53:12.866894 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_eeprom_50 RESULT=pass>
2019 10:53:12.867670 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_eeprom_50 RESULT=pass
2021 10:53:12.961313 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_eeprom_50_nvmem-layout RESULT=skip>
2022 10:53:12.962146 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_eeprom_50_nvmem-layout RESULT=skip
2024 10:53:13.061489 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass>
2025 10:53:13.062342 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass
2027 10:53:13.162870 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass>
2028 10:53:13.163722 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass
2030 10:53:13.264876 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail>
2031 10:53:13.265739 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail
2033 10:53:13.358807 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail>
2034 10:53:13.359740 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail
2036 10:53:13.448985 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass>
2037 10:53:13.449920 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass
2039 10:53:13.537209 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail>
2040 10:53:13.538120 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail
2042 10:53:13.630748 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail>
2043 10:53:13.631666 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail
2045 10:53:13.723924 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass>
2046 10:53:13.724842 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass
2048 10:53:13.816042 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass>
2049 10:53:13.816941 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass
2051 10:53:13.910309 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass>
2052 10:53:13.911266 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass
2054 10:53:14.011475 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass>
2055 10:53:14.012442 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass
2057 10:53:14.116370 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass>
2058 10:53:14.117274 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass
2060 10:53:14.216606 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass>
2061 10:53:14.217512 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass
2063 10:53:14.310632 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass>
2064 10:53:14.311624 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass
2066 10:53:14.405188 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass>
2067 10:53:14.406121 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass
2069 10:53:14.497636 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass>
2070 10:53:14.498627 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass
2072 10:53:14.588036 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail>
2073 10:53:14.588948 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail
2075 10:53:14.680480 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip>
2076 10:53:14.681293 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip
2078 10:53:14.789799 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass>
2079 10:53:14.791045 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass
2081 10:53:14.883375 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass>
2082 10:53:14.884061 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass
2084 10:53:14.982783 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass>
2085 10:53:14.983671 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass
2087 10:53:15.083563 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass>
2088 10:53:15.084554 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass
2090 10:53:15.176663 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass>
2091 10:53:15.177625 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass
2093 10:53:15.269873 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass>
2094 10:53:15.270847 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass
2096 10:53:15.362588 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass>
2097 10:53:15.363584 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass
2099 10:53:15.456405 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass>
2100 10:53:15.457356 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass
2102 10:53:15.547425 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass>
2103 10:53:15.548305 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass
2105 10:53:15.638332 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass>
2106 10:53:15.639211 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass
2108 10:53:15.724346 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass>
2109 10:53:15.725224 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass
2111 10:53:15.818284 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass>
2112 10:53:15.819165 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass
2114 10:53:15.909405 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass>
2115 10:53:15.910338 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass
2117 10:53:16.002333 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass>
2118 10:53:16.003225 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass
2120 10:53:16.103455 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass>
2121 10:53:16.104414 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass
2123 10:53:16.197760 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass>
2124 10:53:16.198713 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass
2126 10:53:16.287497 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass>
2127 10:53:16.288452 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass
2129 10:53:16.380366 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass>
2130 10:53:16.381302 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass
2132 10:53:16.474959 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass>
2133 10:53:16.475683 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass
2135 10:53:16.570104 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass>
2136 10:53:16.571037 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass
2138 10:53:16.672042 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass>
2139 10:53:16.672939 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass
2141 10:53:16.773804 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_54 RESULT=fail>
2142 10:53:16.774759 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_54 RESULT=fail
2144 10:53:16.875269 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_54_nvmem-layout RESULT=skip>
2145 10:53:16.875955 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_54_nvmem-layout RESULT=skip
2147 10:53:16.977316 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_55 RESULT=fail>
2148 10:53:16.978463 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_55 RESULT=fail
2150 10:53:17.079328 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_55_nvmem-layout RESULT=skip>
2151 10:53:17.080312 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_55_nvmem-layout RESULT=skip
2153 10:53:17.167992 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_56 RESULT=fail>
2154 10:53:17.168985 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_56 RESULT=fail
2156 10:53:17.260528 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_56_nvmem-layout RESULT=skip>
2157 10:53:17.261431 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_56_nvmem-layout RESULT=skip
2159 10:53:17.348059 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_57 RESULT=fail>
2160 10:53:17.348948 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_57 RESULT=fail
2162 10:53:17.441011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_57_nvmem-layout RESULT=skip>
2163 10:53:17.441952 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_57_nvmem-layout RESULT=skip
2165 10:53:17.539813 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass>
2166 10:53:17.540770 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass
2168 10:53:17.632789 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass>
2169 10:53:17.633728 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass
2171 10:53:17.723626 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass>
2172 10:53:17.724531 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass
2174 10:53:17.815476 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass>
2175 10:53:17.816638 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass
2177 10:53:17.908230 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass>
2178 10:53:17.909203 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass
2180 10:53:18.001305 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass>
2181 10:53:18.002206 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass
2183 10:53:18.091971 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass>
2184 10:53:18.092844 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass
2186 10:53:18.186138 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass>
2187 10:53:18.187057 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass
2189 10:53:18.277785 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass>
2190 10:53:18.278676 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass
2192 10:53:18.370532 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass>
2193 10:53:18.371436 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass
2195 10:53:18.464932 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass>
2196 10:53:18.465851 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass
2198 10:53:18.557626 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass>
2199 10:53:18.558341 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass
2201 10:53:18.646478 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass>
2202 10:53:18.647188 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass
2204 10:53:18.739300 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass>
2205 10:53:18.739982 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass
2207 10:53:18.831438 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip>
2208 10:53:18.832131 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip
2210 10:53:18.922036 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass>
2211 10:53:18.922753 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass
2213 10:53:19.014879 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass>
2214 10:53:19.015572 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass
2216 10:53:19.108065 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass>
2217 10:53:19.108770 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass
2219 10:53:19.200880 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass>
2220 10:53:19.201594 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass
2222 10:53:19.294300 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass>
2223 10:53:19.294979 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass
2225 10:53:19.385949 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass>
2226 10:53:19.386644 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass
2228 10:53:19.477460 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass>
2229 10:53:19.478196 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass
2231 10:53:19.567287 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail>
2232 10:53:19.568007 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail
2234 10:53:19.657305 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass>
2235 10:53:19.658224 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass
2237 10:53:19.749659 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass>
2238 10:53:19.750504 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass
2240 10:53:19.843261 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass>
2241 10:53:19.844070 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass
2243 10:53:19.935596 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass>
2244 10:53:19.936409 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass
2246 10:53:20.030085 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass>
2247 10:53:20.030961 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass
2249 10:53:20.130006 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass>
2250 10:53:20.130540 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass
2252 10:53:20.222321 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail>
2253 10:53:20.223141 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail
2255 10:53:20.314716 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip>
2256 10:53:20.315534 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip
2258 10:53:20.410248 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail>
2259 10:53:20.411133 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail
2261 10:53:20.500545 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip>
2262 10:53:20.501416 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip
2264 10:53:20.589513 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail>
2265 10:53:20.590385 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail
2267 10:53:20.681375 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail>
2268 10:53:20.682239 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail
2270 10:53:20.770202 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail>
2271 10:53:20.770999 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail
2273 10:53:20.861507 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail>
2274 10:53:20.862371 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail
2276 10:53:20.952590 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip>
2277 10:53:20.953397 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip
2279 10:53:21.043048 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass>
2280 10:53:21.044034 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass
2282 10:53:21.135315 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass>
2283 10:53:21.136183 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass
2285 10:53:21.227064 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip>
2286 10:53:21.227876 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip
2288 10:53:21.316515 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip
2290 10:53:21.319605 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip>
2291 10:53:21.408888 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass>
2292 10:53:21.409769 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass
2294 10:53:21.503525 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass>
2295 10:53:21.504390 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass
2297 10:53:21.594697 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass>
2298 10:53:21.595502 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass
2300 10:53:21.685243 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass>
2301 10:53:21.686047 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass
2303 10:53:21.776146 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass>
2304 10:53:21.776934 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass
2306 10:53:21.869298 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass>
2307 10:53:21.870152 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass
2309 10:53:21.963026 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass>
2310 10:53:21.963832 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass
2312 10:53:22.055054 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass>
2313 10:53:22.055904 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass
2315 10:53:22.147216 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass>
2316 10:53:22.148048 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass
2318 10:53:22.237975 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass>
2319 10:53:22.238816 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass
2321 10:53:22.330630 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass>
2322 10:53:22.331460 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass
2324 10:53:22.421671 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass>
2325 10:53:22.422789 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass
2327 10:53:22.515363 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass>
2328 10:53:22.516276 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass
2330 10:53:22.606599 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass>
2331 10:53:22.607445 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass
2333 10:53:22.698216 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass>
2334 10:53:22.699038 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass
2336 10:53:22.789075 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass>
2337 10:53:22.790035 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass
2339 10:53:22.880932 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail>
2340 10:53:22.881757 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail
2342 10:53:22.973307 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass>
2343 10:53:22.974179 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass
2345 10:53:23.065061 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass>
2346 10:53:23.065939 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass
2348 10:53:23.151054 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail>
2349 10:53:23.151877 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail
2351 10:53:23.241425 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass>
2352 10:53:23.242309 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass
2354 10:53:23.332767 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail>
2355 10:53:23.333666 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail
2357 10:53:23.424007 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass>
2358 10:53:23.424884 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass
2360 10:53:23.514841 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip>
2361 10:53:23.515740 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip
2363 10:53:23.601301 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip>
2364 10:53:23.602173 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip
2366 10:53:23.693419 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip>
2367 10:53:23.694297 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip
2369 10:53:23.784591 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass>
2370 10:53:23.785524 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass
2372 10:53:23.877145 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass>
2373 10:53:23.877985 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass
2375 10:53:23.973683 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass>
2376 10:53:23.974564 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass
2378 10:53:24.065592 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass>
2379 10:53:24.066518 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass
2381 10:53:24.154201 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail>
2382 10:53:24.154792 + set +x
2383 10:53:24.155563 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail
2385 10:53:24.158455 <LAVA_SIGNAL_ENDRUN 1_kselftest-dt 974617_1.6.2.4.5>
2386 10:53:24.159216 Received signal: <ENDRUN> 1_kselftest-dt 974617_1.6.2.4.5
2387 10:53:24.159712 Ending use of test pattern.
2388 10:53:24.160162 Ending test lava.1_kselftest-dt (974617_1.6.2.4.5), duration 86.87
2390 10:53:24.165102 <LAVA_TEST_RUNNER EXIT>
2391 10:53:24.165877 ok: lava_test_shell seems to have completed
2392 10:53:24.180146 dt_test_unprobed_devices_sh: fail
dt_test_unprobed_devices_sh_: skip
dt_test_unprobed_devices_sh_clk_mcasp0: pass
dt_test_unprobed_devices_sh_clk_mcasp0_fixed: skip
dt_test_unprobed_devices_sh_cpus_cpu_0: skip
dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate: skip
dt_test_unprobed_devices_sh_fixedregulator0: pass
dt_test_unprobed_devices_sh_leds: pass
dt_test_unprobed_devices_sh_ocp: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0: fail
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_eeprom_50: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_eeprom_50_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_54: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_54_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_55: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_55_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_56: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_56_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_57: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_57_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000: skip
dt_test_unprobed_devices_sh_ocp_target-module_47400000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800: pass
dt_test_unprobed_devices_sh_ocp_target-module_47810000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_50000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_53500000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_56000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0: skip
dt_test_unprobed_devices_sh_opp-table: skip
dt_test_unprobed_devices_sh_soc: skip
dt_test_unprobed_devices_sh_sound: pass
dt_test_unprobed_devices_sh_target-module_4b000000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0: pass
shardfile-dt: pass
2393 10:53:24.182238 end: 3.1 lava-test-shell (duration 00:01:28) [common]
2394 10:53:24.182867 end: 3 lava-test-retry (duration 00:01:28) [common]
2395 10:53:24.183482 start: 4 finalize (timeout 00:05:24) [common]
2396 10:53:24.184100 start: 4.1 power-off (timeout 00:00:30) [common]
2397 10:53:24.185153 Calling: 'curl' 'http://conserv3.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=beaglebone-black-03'
2398 10:53:24.234308 >> OK - accepted request
2399 10:53:24.236370 Returned 0 in 0 seconds
2400 10:53:24.337589 end: 4.1 power-off (duration 00:00:00) [common]
2402 10:53:24.339451 start: 4.2 read-feedback (timeout 00:05:24) [common]
2403 10:53:24.340670 Listened to connection for namespace 'common' for up to 1s
2404 10:53:24.341598 Listened to connection for namespace 'common' for up to 1s
2405 10:53:25.341407 Finalising connection for namespace 'common'
2406 10:53:25.342218 Disconnecting from shell: Finalise
2407 10:53:25.342787 / #
2408 10:53:25.443971 end: 4.2 read-feedback (duration 00:00:01) [common]
2409 10:53:25.444804 end: 4 finalize (duration 00:00:01) [common]
2410 10:53:25.445519 Cleaning after the job
2411 10:53:25.446264 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/974617/tftp-deploy-a39ntaez/ramdisk
2412 10:53:25.456294 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/974617/tftp-deploy-a39ntaez/kernel
2413 10:53:25.464012 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/974617/tftp-deploy-a39ntaez/dtb
2414 10:53:25.465355 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/974617/tftp-deploy-a39ntaez/nfsrootfs
2415 10:53:25.607333 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/974617/tftp-deploy-a39ntaez/modules
2416 10:53:25.616055 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/974617
2417 10:53:28.629745 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/974617
2418 10:53:28.630329 Job finished correctly