Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 10:58:07.196209 lava-dispatcher, installed at version: 2024.01
2 10:58:07.197011 start: 0 validate
3 10:58:07.197492 Start time: 2024-11-11 10:58:07.197461+00:00 (UTC)
4 10:58:07.198063 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 10:58:07.198605 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230703.0%2Farm64%2Frootfs.cpio.gz exists
6 10:58:07.243973 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 10:58:07.244602 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241111%2Farm64%2Fdefconfig%2Bdebug%2Fgcc-12%2Fkernel%2FImage exists
8 10:58:07.275792 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 10:58:07.276448 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241111%2Farm64%2Fdefconfig%2Bdebug%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 10:58:08.325154 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 10:58:08.325672 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241111%2Farm64%2Fdefconfig%2Bdebug%2Fgcc-12%2Fmodules.tar.xz exists
12 10:58:08.367080 validate duration: 1.17
14 10:58:08.367937 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 10:58:08.368305 start: 1.1 download-retry (timeout 00:10:00) [common]
16 10:58:08.368612 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 10:58:08.369186 Not decompressing ramdisk as can be used compressed.
18 10:58:08.369615 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230703.0/arm64/rootfs.cpio.gz
19 10:58:08.369855 saving as /var/lib/lava/dispatcher/tmp/974725/tftp-deploy-5bh5lpk1/ramdisk/rootfs.cpio.gz
20 10:58:08.370117 total size: 8181887 (7 MB)
21 10:58:08.415363 progress 0 % (0 MB)
22 10:58:08.423596 progress 5 % (0 MB)
23 10:58:08.431671 progress 10 % (0 MB)
24 10:58:08.439463 progress 15 % (1 MB)
25 10:58:08.446780 progress 20 % (1 MB)
26 10:58:08.454647 progress 25 % (1 MB)
27 10:58:08.462145 progress 30 % (2 MB)
28 10:58:08.469880 progress 35 % (2 MB)
29 10:58:08.477020 progress 40 % (3 MB)
30 10:58:08.484619 progress 45 % (3 MB)
31 10:58:08.491589 progress 50 % (3 MB)
32 10:58:08.499345 progress 55 % (4 MB)
33 10:58:08.506506 progress 60 % (4 MB)
34 10:58:08.514180 progress 65 % (5 MB)
35 10:58:08.521173 progress 70 % (5 MB)
36 10:58:08.528654 progress 75 % (5 MB)
37 10:58:08.535573 progress 80 % (6 MB)
38 10:58:08.543053 progress 85 % (6 MB)
39 10:58:08.549940 progress 90 % (7 MB)
40 10:58:08.557414 progress 95 % (7 MB)
41 10:58:08.563969 progress 100 % (7 MB)
42 10:58:08.564924 7 MB downloaded in 0.19 s (40.07 MB/s)
43 10:58:08.565701 end: 1.1.1 http-download (duration 00:00:00) [common]
45 10:58:08.566999 end: 1.1 download-retry (duration 00:00:00) [common]
46 10:58:08.567421 start: 1.2 download-retry (timeout 00:10:00) [common]
47 10:58:08.567853 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 10:58:08.568622 downloading http://storage.kernelci.org/next/master/next-20241111/arm64/defconfig+debug/gcc-12/kernel/Image
49 10:58:08.569021 saving as /var/lib/lava/dispatcher/tmp/974725/tftp-deploy-5bh5lpk1/kernel/Image
50 10:58:08.569336 total size: 172022272 (164 MB)
51 10:58:08.569683 No compression specified
52 10:58:08.609953 progress 0 % (0 MB)
53 10:58:08.741578 progress 5 % (8 MB)
54 10:58:08.873712 progress 10 % (16 MB)
55 10:58:09.004919 progress 15 % (24 MB)
56 10:58:09.134984 progress 20 % (32 MB)
57 10:58:09.266181 progress 25 % (41 MB)
58 10:58:09.398198 progress 30 % (49 MB)
59 10:58:09.530635 progress 35 % (57 MB)
60 10:58:09.661318 progress 40 % (65 MB)
61 10:58:09.792344 progress 45 % (73 MB)
62 10:58:09.922725 progress 50 % (82 MB)
63 10:58:10.053265 progress 55 % (90 MB)
64 10:58:10.183264 progress 60 % (98 MB)
65 10:58:10.317721 progress 65 % (106 MB)
66 10:58:10.451311 progress 70 % (114 MB)
67 10:58:10.580994 progress 75 % (123 MB)
68 10:58:10.708314 progress 80 % (131 MB)
69 10:58:10.837635 progress 85 % (139 MB)
70 10:58:10.967169 progress 90 % (147 MB)
71 10:58:11.096335 progress 95 % (155 MB)
72 10:58:11.224078 progress 100 % (164 MB)
73 10:58:11.224981 164 MB downloaded in 2.66 s (61.78 MB/s)
74 10:58:11.225604 end: 1.2.1 http-download (duration 00:00:03) [common]
76 10:58:11.226628 end: 1.2 download-retry (duration 00:00:03) [common]
77 10:58:11.227013 start: 1.3 download-retry (timeout 00:09:57) [common]
78 10:58:11.227365 start: 1.3.1 http-download (timeout 00:09:57) [common]
79 10:58:11.227915 downloading http://storage.kernelci.org/next/master/next-20241111/arm64/defconfig+debug/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
80 10:58:11.228327 saving as /var/lib/lava/dispatcher/tmp/974725/tftp-deploy-5bh5lpk1/dtb/meson-g12b-a311d-libretech-cc.dtb
81 10:58:11.228579 total size: 54703 (0 MB)
82 10:58:11.228864 No compression specified
83 10:58:11.268857 progress 59 % (0 MB)
84 10:58:11.269910 progress 100 % (0 MB)
85 10:58:11.270611 0 MB downloaded in 0.04 s (1.24 MB/s)
86 10:58:11.271282 end: 1.3.1 http-download (duration 00:00:00) [common]
88 10:58:11.272480 end: 1.3 download-retry (duration 00:00:00) [common]
89 10:58:11.272858 start: 1.4 download-retry (timeout 00:09:57) [common]
90 10:58:11.273322 start: 1.4.1 http-download (timeout 00:09:57) [common]
91 10:58:11.273989 downloading http://storage.kernelci.org/next/master/next-20241111/arm64/defconfig+debug/gcc-12/modules.tar.xz
92 10:58:11.274335 saving as /var/lib/lava/dispatcher/tmp/974725/tftp-deploy-5bh5lpk1/modules/modules.tar
93 10:58:11.274643 total size: 27877612 (26 MB)
94 10:58:11.274949 Using unxz to decompress xz
95 10:58:11.310003 progress 0 % (0 MB)
96 10:58:11.502726 progress 5 % (1 MB)
97 10:58:11.710653 progress 10 % (2 MB)
98 10:58:11.944955 progress 15 % (4 MB)
99 10:58:12.186213 progress 20 % (5 MB)
100 10:58:12.387586 progress 25 % (6 MB)
101 10:58:12.595684 progress 30 % (8 MB)
102 10:58:12.796570 progress 35 % (9 MB)
103 10:58:12.995378 progress 40 % (10 MB)
104 10:58:13.188605 progress 45 % (11 MB)
105 10:58:13.404394 progress 50 % (13 MB)
106 10:58:13.604578 progress 55 % (14 MB)
107 10:58:13.825472 progress 60 % (15 MB)
108 10:58:14.031033 progress 65 % (17 MB)
109 10:58:14.237964 progress 70 % (18 MB)
110 10:58:14.450946 progress 75 % (19 MB)
111 10:58:14.652391 progress 80 % (21 MB)
112 10:58:14.864207 progress 85 % (22 MB)
113 10:58:15.067900 progress 90 % (23 MB)
114 10:58:15.269593 progress 95 % (25 MB)
115 10:58:15.464600 progress 100 % (26 MB)
116 10:58:15.479647 26 MB downloaded in 4.20 s (6.32 MB/s)
117 10:58:15.480339 end: 1.4.1 http-download (duration 00:00:04) [common]
119 10:58:15.481258 end: 1.4 download-retry (duration 00:00:04) [common]
120 10:58:15.481546 start: 1.5 prepare-tftp-overlay (timeout 00:09:53) [common]
121 10:58:15.481826 start: 1.5.1 extract-nfsrootfs (timeout 00:09:53) [common]
122 10:58:15.482084 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 10:58:15.482686 start: 1.5.2 lava-overlay (timeout 00:09:53) [common]
124 10:58:15.483849 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/974725/lava-overlay-at2xo1hg
125 10:58:15.484543 makedir: /var/lib/lava/dispatcher/tmp/974725/lava-overlay-at2xo1hg/lava-974725/bin
126 10:58:15.484967 makedir: /var/lib/lava/dispatcher/tmp/974725/lava-overlay-at2xo1hg/lava-974725/tests
127 10:58:15.485513 makedir: /var/lib/lava/dispatcher/tmp/974725/lava-overlay-at2xo1hg/lava-974725/results
128 10:58:15.486271 Creating /var/lib/lava/dispatcher/tmp/974725/lava-overlay-at2xo1hg/lava-974725/bin/lava-add-keys
129 10:58:15.487368 Creating /var/lib/lava/dispatcher/tmp/974725/lava-overlay-at2xo1hg/lava-974725/bin/lava-add-sources
130 10:58:15.488471 Creating /var/lib/lava/dispatcher/tmp/974725/lava-overlay-at2xo1hg/lava-974725/bin/lava-background-process-start
131 10:58:15.489129 Creating /var/lib/lava/dispatcher/tmp/974725/lava-overlay-at2xo1hg/lava-974725/bin/lava-background-process-stop
132 10:58:15.489776 Creating /var/lib/lava/dispatcher/tmp/974725/lava-overlay-at2xo1hg/lava-974725/bin/lava-common-functions
133 10:58:15.490372 Creating /var/lib/lava/dispatcher/tmp/974725/lava-overlay-at2xo1hg/lava-974725/bin/lava-echo-ipv4
134 10:58:15.490955 Creating /var/lib/lava/dispatcher/tmp/974725/lava-overlay-at2xo1hg/lava-974725/bin/lava-install-packages
135 10:58:15.491533 Creating /var/lib/lava/dispatcher/tmp/974725/lava-overlay-at2xo1hg/lava-974725/bin/lava-installed-packages
136 10:58:15.492219 Creating /var/lib/lava/dispatcher/tmp/974725/lava-overlay-at2xo1hg/lava-974725/bin/lava-os-build
137 10:58:15.492837 Creating /var/lib/lava/dispatcher/tmp/974725/lava-overlay-at2xo1hg/lava-974725/bin/lava-probe-channel
138 10:58:15.493486 Creating /var/lib/lava/dispatcher/tmp/974725/lava-overlay-at2xo1hg/lava-974725/bin/lava-probe-ip
139 10:58:15.494110 Creating /var/lib/lava/dispatcher/tmp/974725/lava-overlay-at2xo1hg/lava-974725/bin/lava-target-ip
140 10:58:15.494725 Creating /var/lib/lava/dispatcher/tmp/974725/lava-overlay-at2xo1hg/lava-974725/bin/lava-target-mac
141 10:58:15.495330 Creating /var/lib/lava/dispatcher/tmp/974725/lava-overlay-at2xo1hg/lava-974725/bin/lava-target-storage
142 10:58:15.495966 Creating /var/lib/lava/dispatcher/tmp/974725/lava-overlay-at2xo1hg/lava-974725/bin/lava-test-case
143 10:58:15.496631 Creating /var/lib/lava/dispatcher/tmp/974725/lava-overlay-at2xo1hg/lava-974725/bin/lava-test-event
144 10:58:15.497258 Creating /var/lib/lava/dispatcher/tmp/974725/lava-overlay-at2xo1hg/lava-974725/bin/lava-test-feedback
145 10:58:15.497907 Creating /var/lib/lava/dispatcher/tmp/974725/lava-overlay-at2xo1hg/lava-974725/bin/lava-test-raise
146 10:58:15.498570 Creating /var/lib/lava/dispatcher/tmp/974725/lava-overlay-at2xo1hg/lava-974725/bin/lava-test-reference
147 10:58:15.499207 Creating /var/lib/lava/dispatcher/tmp/974725/lava-overlay-at2xo1hg/lava-974725/bin/lava-test-runner
148 10:58:15.499862 Creating /var/lib/lava/dispatcher/tmp/974725/lava-overlay-at2xo1hg/lava-974725/bin/lava-test-set
149 10:58:15.500528 Creating /var/lib/lava/dispatcher/tmp/974725/lava-overlay-at2xo1hg/lava-974725/bin/lava-test-shell
150 10:58:15.501177 Updating /var/lib/lava/dispatcher/tmp/974725/lava-overlay-at2xo1hg/lava-974725/bin/lava-install-packages (oe)
151 10:58:15.501874 Updating /var/lib/lava/dispatcher/tmp/974725/lava-overlay-at2xo1hg/lava-974725/bin/lava-installed-packages (oe)
152 10:58:15.502464 Creating /var/lib/lava/dispatcher/tmp/974725/lava-overlay-at2xo1hg/lava-974725/environment
153 10:58:15.502979 LAVA metadata
154 10:58:15.503331 - LAVA_JOB_ID=974725
155 10:58:15.503636 - LAVA_DISPATCHER_IP=192.168.6.2
156 10:58:15.504124 start: 1.5.2.1 ssh-authorize (timeout 00:09:53) [common]
157 10:58:15.505380 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 10:58:15.505785 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:53) [common]
159 10:58:15.506080 skipped lava-vland-overlay
160 10:58:15.506420 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 10:58:15.506777 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:53) [common]
162 10:58:15.507083 skipped lava-multinode-overlay
163 10:58:15.507425 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 10:58:15.507785 start: 1.5.2.4 test-definition (timeout 00:09:53) [common]
165 10:58:15.508142 Loading test definitions
166 10:58:15.508540 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:53) [common]
167 10:58:15.508864 Using /lava-974725 at stage 0
168 10:58:15.510287 uuid=974725_1.5.2.4.1 testdef=None
169 10:58:15.510686 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 10:58:15.511056 start: 1.5.2.4.2 test-overlay (timeout 00:09:53) [common]
171 10:58:15.513238 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 10:58:15.514196 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:53) [common]
174 10:58:15.517629 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 10:58:15.519255 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:53) [common]
177 10:58:15.521925 runner path: /var/lib/lava/dispatcher/tmp/974725/lava-overlay-at2xo1hg/lava-974725/0/tests/0_dmesg test_uuid 974725_1.5.2.4.1
178 10:58:15.522531 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 10:58:15.523334 Creating lava-test-runner.conf files
181 10:58:15.523538 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/974725/lava-overlay-at2xo1hg/lava-974725/0 for stage 0
182 10:58:15.523877 - 0_dmesg
183 10:58:15.524281 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 10:58:15.524576 start: 1.5.2.5 compress-overlay (timeout 00:09:53) [common]
185 10:58:15.548606 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 10:58:15.549060 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:53) [common]
187 10:58:15.549337 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 10:58:15.549610 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 10:58:15.549881 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:53) [common]
190 10:58:16.579316 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
191 10:58:16.579783 start: 1.5.4 extract-modules (timeout 00:09:52) [common]
192 10:58:16.580067 extracting modules file /var/lib/lava/dispatcher/tmp/974725/tftp-deploy-5bh5lpk1/modules/modules.tar to /var/lib/lava/dispatcher/tmp/974725/extract-overlay-ramdisk-z0oyj6m1/ramdisk
193 10:58:18.227164 end: 1.5.4 extract-modules (duration 00:00:02) [common]
194 10:58:18.227630 start: 1.5.5 apply-overlay-tftp (timeout 00:09:50) [common]
195 10:58:18.227906 [common] Applying overlay /var/lib/lava/dispatcher/tmp/974725/compress-overlay-dxk2g9j_/overlay-1.5.2.5.tar.gz to ramdisk
196 10:58:18.228146 [common] Applying overlay /var/lib/lava/dispatcher/tmp/974725/compress-overlay-dxk2g9j_/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/974725/extract-overlay-ramdisk-z0oyj6m1/ramdisk
197 10:58:18.257836 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 10:58:18.258232 start: 1.5.6 prepare-kernel (timeout 00:09:50) [common]
199 10:58:18.258499 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:50) [common]
200 10:58:18.258722 Converting downloaded kernel to a uImage
201 10:58:18.259021 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/974725/tftp-deploy-5bh5lpk1/kernel/Image /var/lib/lava/dispatcher/tmp/974725/tftp-deploy-5bh5lpk1/kernel/uImage
202 10:58:19.924557 output: Image Name:
203 10:58:19.924968 output: Created: Mon Nov 11 10:58:18 2024
204 10:58:19.925174 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 10:58:19.925377 output: Data Size: 172022272 Bytes = 167990.50 KiB = 164.05 MiB
206 10:58:19.925577 output: Load Address: 01080000
207 10:58:19.925774 output: Entry Point: 01080000
208 10:58:19.925969 output:
209 10:58:19.926294 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:02) [common]
210 10:58:19.926556 end: 1.5.6 prepare-kernel (duration 00:00:02) [common]
211 10:58:19.926820 start: 1.5.7 configure-preseed-file (timeout 00:09:48) [common]
212 10:58:19.927070 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 10:58:19.927325 start: 1.5.8 compress-ramdisk (timeout 00:09:48) [common]
214 10:58:19.927579 Building ramdisk /var/lib/lava/dispatcher/tmp/974725/extract-overlay-ramdisk-z0oyj6m1/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/974725/extract-overlay-ramdisk-z0oyj6m1/ramdisk
215 10:58:25.864293 >> 445546 blocks
216 10:58:47.820348 Adding RAMdisk u-boot header.
217 10:58:47.821027 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/974725/extract-overlay-ramdisk-z0oyj6m1/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/974725/extract-overlay-ramdisk-z0oyj6m1/ramdisk.cpio.gz.uboot
218 10:58:48.378655 output: Image Name:
219 10:58:48.379074 output: Created: Mon Nov 11 10:58:47 2024
220 10:58:48.379281 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 10:58:48.379483 output: Data Size: 54100430 Bytes = 52832.45 KiB = 51.59 MiB
222 10:58:48.379682 output: Load Address: 00000000
223 10:58:48.379879 output: Entry Point: 00000000
224 10:58:48.380210 output:
225 10:58:48.381247 rename /var/lib/lava/dispatcher/tmp/974725/extract-overlay-ramdisk-z0oyj6m1/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/974725/tftp-deploy-5bh5lpk1/ramdisk/ramdisk.cpio.gz.uboot
226 10:58:48.381996 end: 1.5.8 compress-ramdisk (duration 00:00:28) [common]
227 10:58:48.382579 end: 1.5 prepare-tftp-overlay (duration 00:00:33) [common]
228 10:58:48.383148 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:20) [common]
229 10:58:48.383664 No LXC device requested
230 10:58:48.384249 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 10:58:48.384810 start: 1.7 deploy-device-env (timeout 00:09:20) [common]
232 10:58:48.385349 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 10:58:48.385811 Checking files for TFTP limit of 4294967296 bytes.
234 10:58:48.388748 end: 1 tftp-deploy (duration 00:00:40) [common]
235 10:58:48.389370 start: 2 uboot-action (timeout 00:05:00) [common]
236 10:58:48.389940 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 10:58:48.390485 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 10:58:48.391080 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 10:58:48.391671 Using kernel file from prepare-kernel: 974725/tftp-deploy-5bh5lpk1/kernel/uImage
240 10:58:48.392372 substitutions:
241 10:58:48.392820 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 10:58:48.393260 - {DTB_ADDR}: 0x01070000
243 10:58:48.393696 - {DTB}: 974725/tftp-deploy-5bh5lpk1/dtb/meson-g12b-a311d-libretech-cc.dtb
244 10:58:48.394132 - {INITRD}: 974725/tftp-deploy-5bh5lpk1/ramdisk/ramdisk.cpio.gz.uboot
245 10:58:48.394568 - {KERNEL_ADDR}: 0x01080000
246 10:58:48.394995 - {KERNEL}: 974725/tftp-deploy-5bh5lpk1/kernel/uImage
247 10:58:48.395430 - {LAVA_MAC}: None
248 10:58:48.395903 - {PRESEED_CONFIG}: None
249 10:58:48.396373 - {PRESEED_LOCAL}: None
250 10:58:48.396801 - {RAMDISK_ADDR}: 0x08000000
251 10:58:48.397226 - {RAMDISK}: 974725/tftp-deploy-5bh5lpk1/ramdisk/ramdisk.cpio.gz.uboot
252 10:58:48.397657 - {ROOT_PART}: None
253 10:58:48.398087 - {ROOT}: None
254 10:58:48.398516 - {SERVER_IP}: 192.168.6.2
255 10:58:48.398948 - {TEE_ADDR}: 0x83000000
256 10:58:48.399375 - {TEE}: None
257 10:58:48.399800 Parsed boot commands:
258 10:58:48.400250 - setenv autoload no
259 10:58:48.400716 - setenv initrd_high 0xffffffff
260 10:58:48.401164 - setenv fdt_high 0xffffffff
261 10:58:48.401588 - dhcp
262 10:58:48.402011 - setenv serverip 192.168.6.2
263 10:58:48.402436 - tftpboot 0x01080000 974725/tftp-deploy-5bh5lpk1/kernel/uImage
264 10:58:48.402860 - tftpboot 0x08000000 974725/tftp-deploy-5bh5lpk1/ramdisk/ramdisk.cpio.gz.uboot
265 10:58:48.403284 - tftpboot 0x01070000 974725/tftp-deploy-5bh5lpk1/dtb/meson-g12b-a311d-libretech-cc.dtb
266 10:58:48.403707 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 10:58:48.404202 - bootm 0x01080000 0x08000000 0x01070000
268 10:58:48.404768 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 10:58:48.406393 start: 2.3 connect-device (timeout 00:05:00) [common]
271 10:58:48.406879 [common] connect-device Connecting to device using 'telnet conserv1 3007'
272 10:58:48.421890 Setting prompt string to ['lava-test: # ']
273 10:58:48.423520 end: 2.3 connect-device (duration 00:00:00) [common]
274 10:58:48.424226 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 10:58:48.424856 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 10:58:48.425440 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 10:58:48.426710 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
278 10:58:48.463536 >> OK - accepted request
279 10:58:48.465759 Returned 0 in 0 seconds
280 10:58:48.567024 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
282 10:58:48.568926 end: 2.4.1 reset-device (duration 00:00:00) [common]
283 10:58:48.569533 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
284 10:58:48.570088 Setting prompt string to ['Hit any key to stop autoboot']
285 10:58:48.570588 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 10:58:48.572424 Trying 192.168.56.21...
287 10:58:48.572972 Connected to conserv1.
288 10:58:48.573437 Escape character is '^]'.
289 10:58:48.573903
290 10:58:48.574371 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
291 10:58:48.574855
292 10:58:59.990906 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
293 10:58:59.991590 bl2_stage_init 0x01
294 10:58:59.992116 bl2_stage_init 0x81
295 10:58:59.996395 hw id: 0x0000 - pwm id 0x01
296 10:58:59.996896 bl2_stage_init 0xc1
297 10:58:59.997346 bl2_stage_init 0x02
298 10:58:59.997789
299 10:59:00.001961 L0:00000000
300 10:59:00.002485 L1:20000703
301 10:59:00.002918 L2:00008067
302 10:59:00.003343 L3:14000000
303 10:59:00.007544 B2:00402000
304 10:59:00.008045 B1:e0f83180
305 10:59:00.008483
306 10:59:00.008911 TE: 58124
307 10:59:00.009337
308 10:59:00.013192 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
309 10:59:00.013661
310 10:59:00.014096 Board ID = 1
311 10:59:00.018713 Set A53 clk to 24M
312 10:59:00.019186 Set A73 clk to 24M
313 10:59:00.019613 Set clk81 to 24M
314 10:59:00.024360 A53 clk: 1200 MHz
315 10:59:00.024848 A73 clk: 1200 MHz
316 10:59:00.025280 CLK81: 166.6M
317 10:59:00.025708 smccc: 00012a92
318 10:59:00.029991 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
319 10:59:00.035574 board id: 1
320 10:59:00.041455 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
321 10:59:00.052082 fw parse done
322 10:59:00.058065 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
323 10:59:00.100617 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
324 10:59:00.111470 PIEI prepare done
325 10:59:00.111784 fastboot data load
326 10:59:00.112187 fastboot data verify
327 10:59:00.117257 verify result: 266
328 10:59:00.122884 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
329 10:59:00.123481 LPDDR4 probe
330 10:59:00.124068 ddr clk to 1584MHz
331 10:59:00.130819 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
332 10:59:00.168400
333 10:59:00.169486 dmc_version 0001
334 10:59:00.174789 Check phy result
335 10:59:00.180672 INFO : End of CA training
336 10:59:00.181680 INFO : End of initialization
337 10:59:00.186341 INFO : Training has run successfully!
338 10:59:00.187243 Check phy result
339 10:59:00.191904 INFO : End of initialization
340 10:59:00.192776 INFO : End of read enable training
341 10:59:00.197492 INFO : End of fine write leveling
342 10:59:00.203059 INFO : End of Write leveling coarse delay
343 10:59:00.203930 INFO : Training has run successfully!
344 10:59:00.204833 Check phy result
345 10:59:00.208673 INFO : End of initialization
346 10:59:00.209534 INFO : End of read dq deskew training
347 10:59:00.214219 INFO : End of MPR read delay center optimization
348 10:59:00.219824 INFO : End of write delay center optimization
349 10:59:00.225463 INFO : End of read delay center optimization
350 10:59:00.226279 INFO : End of max read latency training
351 10:59:00.231029 INFO : Training has run successfully!
352 10:59:00.231873 1D training succeed
353 10:59:00.240436 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
354 10:59:00.287909 Check phy result
355 10:59:00.288793 INFO : End of initialization
356 10:59:00.309740 INFO : End of 2D read delay Voltage center optimization
357 10:59:00.329902 INFO : End of 2D read delay Voltage center optimization
358 10:59:00.382046 INFO : End of 2D write delay Voltage center optimization
359 10:59:00.431313 INFO : End of 2D write delay Voltage center optimization
360 10:59:00.436815 INFO : Training has run successfully!
361 10:59:00.437611
362 10:59:00.438322 channel==0
363 10:59:00.442434 RxClkDly_Margin_A0==88 ps 9
364 10:59:00.443232 TxDqDly_Margin_A0==98 ps 10
365 10:59:00.445707 RxClkDly_Margin_A1==88 ps 9
366 10:59:00.446545 TxDqDly_Margin_A1==98 ps 10
367 10:59:00.451385 TrainedVREFDQ_A0==74
368 10:59:00.452369 TrainedVREFDQ_A1==74
369 10:59:00.453246 VrefDac_Margin_A0==25
370 10:59:00.456967 DeviceVref_Margin_A0==40
371 10:59:00.457802 VrefDac_Margin_A1==25
372 10:59:00.463279 DeviceVref_Margin_A1==40
373 10:59:00.464167
374 10:59:00.465002
375 10:59:00.465883 channel==1
376 10:59:00.466697 RxClkDly_Margin_A0==98 ps 10
377 10:59:00.467798 TxDqDly_Margin_A0==88 ps 9
378 10:59:00.471490 RxClkDly_Margin_A1==88 ps 9
379 10:59:00.472296 TxDqDly_Margin_A1==88 ps 9
380 10:59:00.473034 TrainedVREFDQ_A0==75
381 10:59:00.477129 TrainedVREFDQ_A1==77
382 10:59:00.478022 VrefDac_Margin_A0==22
383 10:59:00.482844 DeviceVref_Margin_A0==38
384 10:59:00.484310 VrefDac_Margin_A1==24
385 10:59:00.485702 DeviceVref_Margin_A1==37
386 10:59:00.486993
387 10:59:00.491667 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
388 10:59:00.492608
389 10:59:00.517422 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000018 00000018 00000016 00000017 00000016 00000018 00000018 00000018 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
390 10:59:00.522963 2D training succeed
391 10:59:00.528577 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
392 10:59:00.534183 auto size-- 65535DDR cs0 size: 2048MB
393 10:59:00.534721 DDR cs1 size: 2048MB
394 10:59:00.535090 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
395 10:59:00.539765 cs0 DataBus test pass
396 10:59:00.540225 cs1 DataBus test pass
397 10:59:00.545442 cs0 AddrBus test pass
398 10:59:00.545991 cs1 AddrBus test pass
399 10:59:00.546392
400 10:59:00.546731 100bdlr_step_size ps== 432
401 10:59:00.551772 result report
402 10:59:00.552352 boot times 0Enable ddr reg access
403 10:59:00.559629 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
404 10:59:00.572994 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
405 10:59:01.146806 0.0;M3 CHK:0;cm4_sp_mode 0
406 10:59:01.147936 MVN_1=0x00000000
407 10:59:01.152235 MVN_2=0x00000000
408 10:59:01.157905 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
409 10:59:01.158717 OPS=0x10
410 10:59:01.159462 ring efuse init
411 10:59:01.160196 chipver efuse init
412 10:59:01.163510 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
413 10:59:01.169134 [0.018961 Inits done]
414 10:59:01.169924 secure task start!
415 10:59:01.170594 high task start!
416 10:59:01.173786 low task start!
417 10:59:01.174512 run into bl31
418 10:59:01.180505 NOTICE: BL31: v1.3(release):4fc40b1
419 10:59:01.188172 NOTICE: BL31: Built : 15:58:17, May 22 2019
420 10:59:01.188942 NOTICE: BL31: G12A normal boot!
421 10:59:01.213562 NOTICE: BL31: BL33 decompress pass
422 10:59:01.219227 ERROR: Error initializing runtime service opteed_fast
423 10:59:02.452052
424 10:59:02.452477
425 10:59:02.460391 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
426 10:59:02.460714
427 10:59:02.460943 Model: Libre Computer AML-A311D-CC Alta
428 10:59:02.668974 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
429 10:59:02.692204 DRAM: 2 GiB (effective 3.8 GiB)
430 10:59:02.835275 Core: 408 devices, 31 uclasses, devicetree: separate
431 10:59:02.841104 WDT: Not starting watchdog@f0d0
432 10:59:02.873374 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
433 10:59:02.885795 Loading Environment from FAT... Card did not respond to voltage select! : -110
434 10:59:02.890739 ** Bad device specification mmc 0 **
435 10:59:02.901087 Card did not respond to voltage select! : -110
436 10:59:02.908828 ** Bad device specification mmc 0 **
437 10:59:02.909348 Couldn't find partition mmc 0
438 10:59:02.917113 Card did not respond to voltage select! : -110
439 10:59:02.922616 ** Bad device specification mmc 0 **
440 10:59:02.923076 Couldn't find partition mmc 0
441 10:59:02.927678 Error: could not access storage.
442 10:59:04.191287 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
443 10:59:04.191934 bl2_stage_init 0x01
444 10:59:04.192434 bl2_stage_init 0x81
445 10:59:04.196862 hw id: 0x0000 - pwm id 0x01
446 10:59:04.197360 bl2_stage_init 0xc1
447 10:59:04.197809 bl2_stage_init 0x02
448 10:59:04.198251
449 10:59:04.202320 L0:00000000
450 10:59:04.202820 L1:20000703
451 10:59:04.203265 L2:00008067
452 10:59:04.203699 L3:14000000
453 10:59:04.207955 B2:00402000
454 10:59:04.208462 B1:e0f83180
455 10:59:04.208898
456 10:59:04.209338 TE: 58124
457 10:59:04.209779
458 10:59:04.213524 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
459 10:59:04.214023
460 10:59:04.214466 Board ID = 1
461 10:59:04.219106 Set A53 clk to 24M
462 10:59:04.219580 Set A73 clk to 24M
463 10:59:04.220053 Set clk81 to 24M
464 10:59:04.224782 A53 clk: 1200 MHz
465 10:59:04.225261 A73 clk: 1200 MHz
466 10:59:04.225695 CLK81: 166.6M
467 10:59:04.226123 smccc: 00012a92
468 10:59:04.230310 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
469 10:59:04.235947 board id: 1
470 10:59:04.241861 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
471 10:59:04.252461 fw parse done
472 10:59:04.258413 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
473 10:59:04.300823 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
474 10:59:04.312022 PIEI prepare done
475 10:59:04.312488 fastboot data load
476 10:59:04.312923 fastboot data verify
477 10:59:04.317654 verify result: 266
478 10:59:04.323196 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
479 10:59:04.323656 LPDDR4 probe
480 10:59:04.324123 ddr clk to 1584MHz
481 10:59:04.331204 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
482 10:59:04.368449
483 10:59:04.368951 dmc_version 0001
484 10:59:04.375188 Check phy result
485 10:59:04.381030 INFO : End of CA training
486 10:59:04.381523 INFO : End of initialization
487 10:59:04.386587 INFO : Training has run successfully!
488 10:59:04.387069 Check phy result
489 10:59:04.392232 INFO : End of initialization
490 10:59:04.392744 INFO : End of read enable training
491 10:59:04.397843 INFO : End of fine write leveling
492 10:59:04.403446 INFO : End of Write leveling coarse delay
493 10:59:04.404066 INFO : Training has run successfully!
494 10:59:04.404519 Check phy result
495 10:59:04.409103 INFO : End of initialization
496 10:59:04.409737 INFO : End of read dq deskew training
497 10:59:04.414783 INFO : End of MPR read delay center optimization
498 10:59:04.420290 INFO : End of write delay center optimization
499 10:59:04.425913 INFO : End of read delay center optimization
500 10:59:04.426420 INFO : End of max read latency training
501 10:59:04.431394 INFO : Training has run successfully!
502 10:59:04.431888 1D training succeed
503 10:59:04.440610 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
504 10:59:04.488354 Check phy result
505 10:59:04.488928 INFO : End of initialization
506 10:59:04.510075 INFO : End of 2D read delay Voltage center optimization
507 10:59:04.530283 INFO : End of 2D read delay Voltage center optimization
508 10:59:04.582353 INFO : End of 2D write delay Voltage center optimization
509 10:59:04.631669 INFO : End of 2D write delay Voltage center optimization
510 10:59:04.638455 INFO : Training has run successfully!
511 10:59:04.638996
512 10:59:04.643314 channel==0
513 10:59:04.644086 RxClkDly_Margin_A0==88 ps 9
514 10:59:04.644556 TxDqDly_Margin_A0==98 ps 10
515 10:59:04.648571 RxClkDly_Margin_A1==88 ps 9
516 10:59:04.649130 TxDqDly_Margin_A1==98 ps 10
517 10:59:04.649583 TrainedVREFDQ_A0==74
518 10:59:04.654048 TrainedVREFDQ_A1==74
519 10:59:04.654591 VrefDac_Margin_A0==25
520 10:59:04.654995 DeviceVref_Margin_A0==40
521 10:59:04.659605 VrefDac_Margin_A1==24
522 10:59:04.660140 DeviceVref_Margin_A1==40
523 10:59:04.660577
524 10:59:04.660978
525 10:59:04.665221 channel==1
526 10:59:04.665705 RxClkDly_Margin_A0==98 ps 10
527 10:59:04.666103 TxDqDly_Margin_A0==88 ps 9
528 10:59:04.670837 RxClkDly_Margin_A1==98 ps 10
529 10:59:04.671330 TxDqDly_Margin_A1==88 ps 9
530 10:59:04.676511 TrainedVREFDQ_A0==77
531 10:59:04.677042 TrainedVREFDQ_A1==77
532 10:59:04.677487 VrefDac_Margin_A0==22
533 10:59:04.682047 DeviceVref_Margin_A0==37
534 10:59:04.682550 VrefDac_Margin_A1==24
535 10:59:04.687611 DeviceVref_Margin_A1==37
536 10:59:04.688139
537 10:59:04.688549 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
538 10:59:04.688945
539 10:59:04.721312 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000019 00000017 00000019 00000018 0000001a 0000001a 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
540 10:59:04.721865 2D training succeed
541 10:59:04.726943 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
542 10:59:04.732470 auto size-- 65535DDR cs0 size: 2048MB
543 10:59:04.732984 DDR cs1 size: 2048MB
544 10:59:04.738103 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
545 10:59:04.738618 cs0 DataBus test pass
546 10:59:04.743696 cs1 DataBus test pass
547 10:59:04.744260 cs0 AddrBus test pass
548 10:59:04.744698 cs1 AddrBus test pass
549 10:59:04.745098
550 10:59:04.749304 100bdlr_step_size ps== 420
551 10:59:04.749815 result report
552 10:59:04.754919 boot times 0Enable ddr reg access
553 10:59:04.760257 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
554 10:59:04.773728 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
555 10:59:05.347316 0.0;M3 CHK:0;cm4_sp_mode 0
556 10:59:05.347921 MVN_1=0x00000000
557 10:59:05.352841 MVN_2=0x00000000
558 10:59:05.358565 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
559 10:59:05.359055 OPS=0x10
560 10:59:05.359463 ring efuse init
561 10:59:05.359854 chipver efuse init
562 10:59:05.364228 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
563 10:59:05.369689 [0.018961 Inits done]
564 10:59:05.370174 secure task start!
565 10:59:05.370572 high task start!
566 10:59:05.374261 low task start!
567 10:59:05.374734 run into bl31
568 10:59:05.381045 NOTICE: BL31: v1.3(release):4fc40b1
569 10:59:05.388782 NOTICE: BL31: Built : 15:58:17, May 22 2019
570 10:59:05.389284 NOTICE: BL31: G12A normal boot!
571 10:59:05.414182 NOTICE: BL31: BL33 decompress pass
572 10:59:05.419883 ERROR: Error initializing runtime service opteed_fast
573 10:59:06.652803
574 10:59:06.653406
575 10:59:06.661410 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
576 10:59:06.661915
577 10:59:06.662351 Model: Libre Computer AML-A311D-CC Alta
578 10:59:06.869818 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
579 10:59:06.893159 DRAM: 2 GiB (effective 3.8 GiB)
580 10:59:07.036060 Core: 408 devices, 31 uclasses, devicetree: separate
581 10:59:07.042000 WDT: Not starting watchdog@f0d0
582 10:59:07.074223 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
583 10:59:07.086642 Loading Environment from FAT... Card did not respond to voltage select! : -110
584 10:59:07.091671 ** Bad device specification mmc 0 **
585 10:59:07.101917 Card did not respond to voltage select! : -110
586 10:59:07.109722 ** Bad device specification mmc 0 **
587 10:59:07.110228 Couldn't find partition mmc 0
588 10:59:07.117859 Card did not respond to voltage select! : -110
589 10:59:07.123410 ** Bad device specification mmc 0 **
590 10:59:07.123912 Couldn't find partition mmc 0
591 10:59:07.128535 Error: could not access storage.
592 10:59:07.471068 Net: eth0: ethernet@ff3f0000
593 10:59:07.471681 starting USB...
594 10:59:07.722934 Bus usb@ff500000: Register 3000140 NbrPorts 3
595 10:59:07.723523 Starting the controller
596 10:59:07.729850 USB XHCI 1.10
597 10:59:09.440391 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
598 10:59:09.440849 bl2_stage_init 0x01
599 10:59:09.441094 bl2_stage_init 0x81
600 10:59:09.445727 hw id: 0x0000 - pwm id 0x01
601 10:59:09.446048 bl2_stage_init 0xc1
602 10:59:09.446289 bl2_stage_init 0x02
603 10:59:09.446520
604 10:59:09.451311 L0:00000000
605 10:59:09.451613 L1:20000703
606 10:59:09.451842 L2:00008067
607 10:59:09.452114 L3:14000000
608 10:59:09.456927 B2:00402000
609 10:59:09.457232 B1:e0f83180
610 10:59:09.457463
611 10:59:09.457700 TE: 58167
612 10:59:09.457939
613 10:59:09.462491 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
614 10:59:09.462795
615 10:59:09.463018 Board ID = 1
616 10:59:09.468069 Set A53 clk to 24M
617 10:59:09.468380 Set A73 clk to 24M
618 10:59:09.468616 Set clk81 to 24M
619 10:59:09.473588 A53 clk: 1200 MHz
620 10:59:09.473884 A73 clk: 1200 MHz
621 10:59:09.474112 CLK81: 166.6M
622 10:59:09.474330 smccc: 00012abe
623 10:59:09.479252 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
624 10:59:09.485096 board id: 1
625 10:59:09.490788 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
626 10:59:09.501808 fw parse done
627 10:59:09.507397 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
628 10:59:09.550113 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
629 10:59:09.560950 PIEI prepare done
630 10:59:09.561457 fastboot data load
631 10:59:09.561731 fastboot data verify
632 10:59:09.566502 verify result: 266
633 10:59:09.572182 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
634 10:59:09.572551 LPDDR4 probe
635 10:59:09.572792 ddr clk to 1584MHz
636 10:59:09.580424 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
637 10:59:09.617544
638 10:59:09.618181 dmc_version 0001
639 10:59:09.623419 Check phy result
640 10:59:09.629976 INFO : End of CA training
641 10:59:09.630544 INFO : End of initialization
642 10:59:09.635516 INFO : Training has run successfully!
643 10:59:09.636158 Check phy result
644 10:59:09.641137 INFO : End of initialization
645 10:59:09.641678 INFO : End of read enable training
646 10:59:09.646698 INFO : End of fine write leveling
647 10:59:09.652380 INFO : End of Write leveling coarse delay
648 10:59:09.652935 INFO : Training has run successfully!
649 10:59:09.653385 Check phy result
650 10:59:09.657997 INFO : End of initialization
651 10:59:09.658544 INFO : End of read dq deskew training
652 10:59:09.663544 INFO : End of MPR read delay center optimization
653 10:59:09.669067 INFO : End of write delay center optimization
654 10:59:09.674719 INFO : End of read delay center optimization
655 10:59:09.675256 INFO : End of max read latency training
656 10:59:09.680277 INFO : Training has run successfully!
657 10:59:09.680835 1D training succeed
658 10:59:09.689465 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
659 10:59:09.737113 Check phy result
660 10:59:09.737701 INFO : End of initialization
661 10:59:09.758763 INFO : End of 2D read delay Voltage center optimization
662 10:59:09.778783 INFO : End of 2D read delay Voltage center optimization
663 10:59:09.830845 INFO : End of 2D write delay Voltage center optimization
664 10:59:09.879933 INFO : End of 2D write delay Voltage center optimization
665 10:59:09.885529 INFO : Training has run successfully!
666 10:59:09.886012
667 10:59:09.886435 channel==0
668 10:59:09.891056 RxClkDly_Margin_A0==88 ps 9
669 10:59:09.891523 TxDqDly_Margin_A0==98 ps 10
670 10:59:09.896659 RxClkDly_Margin_A1==88 ps 9
671 10:59:09.897133 TxDqDly_Margin_A1==98 ps 10
672 10:59:09.897576 TrainedVREFDQ_A0==74
673 10:59:09.902287 TrainedVREFDQ_A1==74
674 10:59:09.902788 VrefDac_Margin_A0==25
675 10:59:09.903205 DeviceVref_Margin_A0==40
676 10:59:09.907840 VrefDac_Margin_A1==25
677 10:59:09.908348 DeviceVref_Margin_A1==40
678 10:59:09.908765
679 10:59:09.909174
680 10:59:09.913526 channel==1
681 10:59:09.913996 RxClkDly_Margin_A0==98 ps 10
682 10:59:09.914414 TxDqDly_Margin_A0==98 ps 10
683 10:59:09.919054 RxClkDly_Margin_A1==98 ps 10
684 10:59:09.919534 TxDqDly_Margin_A1==88 ps 9
685 10:59:09.924629 TrainedVREFDQ_A0==77
686 10:59:09.925107 TrainedVREFDQ_A1==77
687 10:59:09.925518 VrefDac_Margin_A0==22
688 10:59:09.930247 DeviceVref_Margin_A0==37
689 10:59:09.930727 VrefDac_Margin_A1==24
690 10:59:09.935910 DeviceVref_Margin_A1==37
691 10:59:09.936420
692 10:59:09.936836 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
693 10:59:09.941520
694 10:59:09.969530 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000018 00000018 00000016 00000018 00000015 00000018 00000019 00000018 00000019 00000018 00000019 0000001a 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
695 10:59:09.970061 2D training succeed
696 10:59:09.975162 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
697 10:59:09.980665 auto size-- 65535DDR cs0 size: 2048MB
698 10:59:09.981160 DDR cs1 size: 2048MB
699 10:59:09.986291 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
700 10:59:09.986760 cs0 DataBus test pass
701 10:59:09.991946 cs1 DataBus test pass
702 10:59:09.992456 cs0 AddrBus test pass
703 10:59:09.992873 cs1 AddrBus test pass
704 10:59:09.993275
705 10:59:09.997471 100bdlr_step_size ps== 420
706 10:59:09.997947 result report
707 10:59:10.003123 boot times 0Enable ddr reg access
708 10:59:10.008532 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
709 10:59:10.021993 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
710 10:59:10.593931 0.0;M3 CHK:0;cm4_sp_mode 0
711 10:59:10.594543 MVN_1=0x00000000
712 10:59:10.599409 MVN_2=0x00000000
713 10:59:10.605195 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
714 10:59:10.605539 OPS=0x10
715 10:59:10.605756 ring efuse init
716 10:59:10.605958 chipver efuse init
717 10:59:10.610868 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
718 10:59:10.616409 [0.018961 Inits done]
719 10:59:10.616880 secure task start!
720 10:59:10.617299 high task start!
721 10:59:10.620987 low task start!
722 10:59:10.621432 run into bl31
723 10:59:10.627770 NOTICE: BL31: v1.3(release):4fc40b1
724 10:59:10.635476 NOTICE: BL31: Built : 15:58:17, May 22 2019
725 10:59:10.636026 NOTICE: BL31: G12A normal boot!
726 10:59:10.660915 NOTICE: BL31: BL33 decompress pass
727 10:59:10.666533 ERROR: Error initializing runtime service opteed_fast
728 10:59:11.899445
729 10:59:11.900170
730 10:59:11.907878 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
731 10:59:11.908438
732 10:59:11.908911 Model: Libre Computer AML-A311D-CC Alta
733 10:59:12.116614 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
734 10:59:12.139766 DRAM: 2 GiB (effective 3.8 GiB)
735 10:59:12.282779 Core: 408 devices, 31 uclasses, devicetree: separate
736 10:59:12.288624 WDT: Not starting watchdog@f0d0
737 10:59:12.320879 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
738 10:59:12.333362 Loading Environment from FAT... Card did not respond to voltage select! : -110
739 10:59:12.338294 ** Bad device specification mmc 0 **
740 10:59:12.348638 Card did not respond to voltage select! : -110
741 10:59:12.356289 ** Bad device specification mmc 0 **
742 10:59:12.356801 Couldn't find partition mmc 0
743 10:59:12.364610 Card did not respond to voltage select! : -110
744 10:59:12.370171 ** Bad device specification mmc 0 **
745 10:59:12.370733 Couldn't find partition mmc 0
746 10:59:12.375228 Error: could not access storage.
747 10:59:12.718715 Net: eth0: ethernet@ff3f0000
748 10:59:12.719367 starting USB...
749 10:59:12.970499 Bus usb@ff500000: Register 3000140 NbrPorts 3
750 10:59:12.971157 Starting the controller
751 10:59:12.977457 USB XHCI 1.10
752 10:59:15.141058 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
753 10:59:15.141709 bl2_stage_init 0x01
754 10:59:15.142180 bl2_stage_init 0x81
755 10:59:15.146592 hw id: 0x0000 - pwm id 0x01
756 10:59:15.147096 bl2_stage_init 0xc1
757 10:59:15.147552 bl2_stage_init 0x02
758 10:59:15.148038
759 10:59:15.152166 L0:00000000
760 10:59:15.152651 L1:20000703
761 10:59:15.153104 L2:00008067
762 10:59:15.153547 L3:14000000
763 10:59:15.155111 B2:00402000
764 10:59:15.155588 B1:e0f83180
765 10:59:15.156113
766 10:59:15.156574 TE: 58159
767 10:59:15.157020
768 10:59:15.166233 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
769 10:59:15.166750
770 10:59:15.167209 Board ID = 1
771 10:59:15.167654 Set A53 clk to 24M
772 10:59:15.168132 Set A73 clk to 24M
773 10:59:15.171777 Set clk81 to 24M
774 10:59:15.172293 A53 clk: 1200 MHz
775 10:59:15.172742 A73 clk: 1200 MHz
776 10:59:15.177689 CLK81: 166.6M
777 10:59:15.178181 smccc: 00012ab5
778 10:59:15.183069 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
779 10:59:15.183564 board id: 1
780 10:59:15.191668 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
781 10:59:15.202309 fw parse done
782 10:59:15.208197 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
783 10:59:15.250797 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
784 10:59:15.261653 PIEI prepare done
785 10:59:15.262146 fastboot data load
786 10:59:15.262599 fastboot data verify
787 10:59:15.267285 verify result: 266
788 10:59:15.272859 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
789 10:59:15.273339 LPDDR4 probe
790 10:59:15.273784 ddr clk to 1584MHz
791 10:59:15.280859 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
792 10:59:15.318124
793 10:59:15.318630 dmc_version 0001
794 10:59:15.324786 Check phy result
795 10:59:15.330670 INFO : End of CA training
796 10:59:15.331148 INFO : End of initialization
797 10:59:15.336304 INFO : Training has run successfully!
798 10:59:15.336776 Check phy result
799 10:59:15.341848 INFO : End of initialization
800 10:59:15.342327 INFO : End of read enable training
801 10:59:15.347418 INFO : End of fine write leveling
802 10:59:15.353047 INFO : End of Write leveling coarse delay
803 10:59:15.353527 INFO : Training has run successfully!
804 10:59:15.353973 Check phy result
805 10:59:15.358683 INFO : End of initialization
806 10:59:15.359157 INFO : End of read dq deskew training
807 10:59:15.364286 INFO : End of MPR read delay center optimization
808 10:59:15.369844 INFO : End of write delay center optimization
809 10:59:15.375449 INFO : End of read delay center optimization
810 10:59:15.376038 INFO : End of max read latency training
811 10:59:15.381088 INFO : Training has run successfully!
812 10:59:15.381584 1D training succeed
813 10:59:15.390258 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
814 10:59:15.437886 Check phy result
815 10:59:15.438494 INFO : End of initialization
816 10:59:15.458807 INFO : End of 2D read delay Voltage center optimization
817 10:59:15.479586 INFO : End of 2D read delay Voltage center optimization
818 10:59:15.531466 INFO : End of 2D write delay Voltage center optimization
819 10:59:15.580670 INFO : End of 2D write delay Voltage center optimization
820 10:59:15.586248 INFO : Training has run successfully!
821 10:59:15.586742
822 10:59:15.587199 channel==0
823 10:59:15.591757 RxClkDly_Margin_A0==88 ps 9
824 10:59:15.592284 TxDqDly_Margin_A0==98 ps 10
825 10:59:15.597479 RxClkDly_Margin_A1==88 ps 9
826 10:59:15.597967 TxDqDly_Margin_A1==98 ps 10
827 10:59:15.598438 TrainedVREFDQ_A0==74
828 10:59:15.603114 TrainedVREFDQ_A1==74
829 10:59:15.603659 VrefDac_Margin_A0==25
830 10:59:15.604147 DeviceVref_Margin_A0==40
831 10:59:15.608660 VrefDac_Margin_A1==25
832 10:59:15.609183 DeviceVref_Margin_A1==40
833 10:59:15.609610
834 10:59:15.610037
835 10:59:15.614252 channel==1
836 10:59:15.614714 RxClkDly_Margin_A0==98 ps 10
837 10:59:15.615144 TxDqDly_Margin_A0==98 ps 10
838 10:59:15.619828 RxClkDly_Margin_A1==98 ps 10
839 10:59:15.620317 TxDqDly_Margin_A1==88 ps 9
840 10:59:15.625526 TrainedVREFDQ_A0==77
841 10:59:15.625991 TrainedVREFDQ_A1==77
842 10:59:15.626422 VrefDac_Margin_A0==22
843 10:59:15.630972 DeviceVref_Margin_A0==37
844 10:59:15.631428 VrefDac_Margin_A1==23
845 10:59:15.636674 DeviceVref_Margin_A1==37
846 10:59:15.637131
847 10:59:15.637557 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
848 10:59:15.642333
849 10:59:15.670239 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000018 00000018 00000016 00000017 00000015 00000017 00000019 00000018 00000019 00000018 0000001a 0000001a 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
850 10:59:15.670742 2D training succeed
851 10:59:15.675842 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
852 10:59:15.681405 auto size-- 65535DDR cs0 size: 2048MB
853 10:59:15.681865 DDR cs1 size: 2048MB
854 10:59:15.686952 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
855 10:59:15.687410 cs0 DataBus test pass
856 10:59:15.692573 cs1 DataBus test pass
857 10:59:15.693027 cs0 AddrBus test pass
858 10:59:15.693453 cs1 AddrBus test pass
859 10:59:15.693875
860 10:59:15.698176 100bdlr_step_size ps== 420
861 10:59:15.698640 result report
862 10:59:15.703741 boot times 0Enable ddr reg access
863 10:59:15.709181 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
864 10:59:15.722664 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
865 10:59:16.294885 0.0;M3 CHK:0;cm4_sp_mode 0
866 10:59:16.295553 MVN_1=0x00000000
867 10:59:16.300213 MVN_2=0x00000000
868 10:59:16.305950 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
869 10:59:16.306474 OPS=0x10
870 10:59:16.306929 ring efuse init
871 10:59:16.307372 chipver efuse init
872 10:59:16.314200 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
873 10:59:16.314717 [0.018961 Inits done]
874 10:59:16.321825 secure task start!
875 10:59:16.322302 high task start!
876 10:59:16.322721 low task start!
877 10:59:16.323128 run into bl31
878 10:59:16.328494 NOTICE: BL31: v1.3(release):4fc40b1
879 10:59:16.336239 NOTICE: BL31: Built : 15:58:17, May 22 2019
880 10:59:16.336735 NOTICE: BL31: G12A normal boot!
881 10:59:16.361726 NOTICE: BL31: BL33 decompress pass
882 10:59:16.366379 ERROR: Error initializing runtime service opteed_fast
883 10:59:17.600222
884 10:59:17.600844
885 10:59:17.608546 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
886 10:59:17.609038
887 10:59:17.609459 Model: Libre Computer AML-A311D-CC Alta
888 10:59:17.816981 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
889 10:59:17.840348 DRAM: 2 GiB (effective 3.8 GiB)
890 10:59:17.983367 Core: 408 devices, 31 uclasses, devicetree: separate
891 10:59:17.988295 WDT: Not starting watchdog@f0d0
892 10:59:18.021503 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
893 10:59:18.033890 Loading Environment from FAT... Card did not respond to voltage select! : -110
894 10:59:18.038919 ** Bad device specification mmc 0 **
895 10:59:18.049262 Card did not respond to voltage select! : -110
896 10:59:18.056928 ** Bad device specification mmc 0 **
897 10:59:18.057418 Couldn't find partition mmc 0
898 10:59:18.065253 Card did not respond to voltage select! : -110
899 10:59:18.070824 ** Bad device specification mmc 0 **
900 10:59:18.071307 Couldn't find partition mmc 0
901 10:59:18.075907 Error: could not access storage.
902 10:59:18.418286 Net: eth0: ethernet@ff3f0000
903 10:59:18.418870 starting USB...
904 10:59:18.670120 Bus usb@ff500000: Register 3000140 NbrPorts 3
905 10:59:18.670737 Starting the controller
906 10:59:18.677072 USB XHCI 1.10
907 10:59:20.529966 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
908 10:59:20.530394 bl2_stage_init 0x01
909 10:59:20.530629 bl2_stage_init 0x81
910 10:59:20.535469 hw id: 0x0000 - pwm id 0x01
911 10:59:20.535808 bl2_stage_init 0xc1
912 10:59:20.536078 bl2_stage_init 0x02
913 10:59:20.536319
914 10:59:20.541179 L0:00000000
915 10:59:20.541709 L1:20000703
916 10:59:20.542131 L2:00008067
917 10:59:20.542544 L3:14000000
918 10:59:20.544020 B2:00402000
919 10:59:20.544492 B1:e0f83180
920 10:59:20.544906
921 10:59:20.545315 TE: 58124
922 10:59:20.545719
923 10:59:20.555131 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
924 10:59:20.555614
925 10:59:20.556069 Board ID = 1
926 10:59:20.556485 Set A53 clk to 24M
927 10:59:20.556887 Set A73 clk to 24M
928 10:59:20.560708 Set clk81 to 24M
929 10:59:20.561180 A53 clk: 1200 MHz
930 10:59:20.561592 A73 clk: 1200 MHz
931 10:59:20.566360 CLK81: 166.6M
932 10:59:20.566847 smccc: 00012a92
933 10:59:20.572032 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
934 10:59:20.572507 board id: 1
935 10:59:20.580463 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
936 10:59:20.591155 fw parse done
937 10:59:20.596690 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
938 10:59:20.639807 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
939 10:59:20.650738 PIEI prepare done
940 10:59:20.651299 fastboot data load
941 10:59:20.651753 fastboot data verify
942 10:59:20.656313 verify result: 266
943 10:59:20.661923 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
944 10:59:20.662447 LPDDR4 probe
945 10:59:20.662846 ddr clk to 1584MHz
946 10:59:20.668917 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
947 10:59:20.706248
948 10:59:20.706848 dmc_version 0001
949 10:59:20.713232 Check phy result
950 10:59:20.720291 INFO : End of CA training
951 10:59:20.720797 INFO : End of initialization
952 10:59:20.725637 INFO : Training has run successfully!
953 10:59:20.726139 Check phy result
954 10:59:20.731238 INFO : End of initialization
955 10:59:20.731736 INFO : End of read enable training
956 10:59:20.734415 INFO : End of fine write leveling
957 10:59:20.740217 INFO : End of Write leveling coarse delay
958 10:59:20.746003 INFO : Training has run successfully!
959 10:59:20.746496 Check phy result
960 10:59:20.746894 INFO : End of initialization
961 10:59:20.751433 INFO : End of read dq deskew training
962 10:59:20.757004 INFO : End of MPR read delay center optimization
963 10:59:20.757525 INFO : End of write delay center optimization
964 10:59:20.762839 INFO : End of read delay center optimization
965 10:59:20.768061 INFO : End of max read latency training
966 10:59:20.768563 INFO : Training has run successfully!
967 10:59:20.773681 1D training succeed
968 10:59:20.778720 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
969 10:59:20.826928 Check phy result
970 10:59:20.827455 INFO : End of initialization
971 10:59:20.848581 INFO : End of 2D read delay Voltage center optimization
972 10:59:20.867809 INFO : End of 2D read delay Voltage center optimization
973 10:59:20.919719 INFO : End of 2D write delay Voltage center optimization
974 10:59:20.968973 INFO : End of 2D write delay Voltage center optimization
975 10:59:20.974555 INFO : Training has run successfully!
976 10:59:20.975075
977 10:59:20.975505 channel==0
978 10:59:20.980188 RxClkDly_Margin_A0==88 ps 9
979 10:59:20.980701 TxDqDly_Margin_A0==98 ps 10
980 10:59:20.985733 RxClkDly_Margin_A1==88 ps 9
981 10:59:20.986238 TxDqDly_Margin_A1==98 ps 10
982 10:59:20.986667 TrainedVREFDQ_A0==74
983 10:59:20.991323 TrainedVREFDQ_A1==74
984 10:59:20.991838 VrefDac_Margin_A0==25
985 10:59:20.992311 DeviceVref_Margin_A0==40
986 10:59:20.996932 VrefDac_Margin_A1==25
987 10:59:20.997435 DeviceVref_Margin_A1==40
988 10:59:20.997852
989 10:59:20.998260
990 10:59:21.002528 channel==1
991 10:59:21.003040 RxClkDly_Margin_A0==98 ps 10
992 10:59:21.003460 TxDqDly_Margin_A0==98 ps 10
993 10:59:21.008176 RxClkDly_Margin_A1==88 ps 9
994 10:59:21.008685 TxDqDly_Margin_A1==88 ps 9
995 10:59:21.013745 TrainedVREFDQ_A0==77
996 10:59:21.014263 TrainedVREFDQ_A1==77
997 10:59:21.014684 VrefDac_Margin_A0==23
998 10:59:21.019350 DeviceVref_Margin_A0==37
999 10:59:21.019871 VrefDac_Margin_A1==24
1000 10:59:21.024967 DeviceVref_Margin_A1==37
1001 10:59:21.025482
1002 10:59:21.025903 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
1003 10:59:21.026316
1004 10:59:21.058492 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000017 00000019 00000018 00000019 00000019 00000018 00000017 00000019 00000017 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
1005 10:59:21.059072 2D training succeed
1006 10:59:21.064196 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
1007 10:59:21.069709 auto size-- 65535DDR cs0 size: 2048MB
1008 10:59:21.070221 DDR cs1 size: 2048MB
1009 10:59:21.075317 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
1010 10:59:21.075823 cs0 DataBus test pass
1011 10:59:21.080913 cs1 DataBus test pass
1012 10:59:21.081415 cs0 AddrBus test pass
1013 10:59:21.081835 cs1 AddrBus test pass
1014 10:59:21.082242
1015 10:59:21.086542 100bdlr_step_size ps== 420
1016 10:59:21.087059 result report
1017 10:59:21.092169 boot times 0Enable ddr reg access
1018 10:59:21.097472 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
1019 10:59:21.110900 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
1020 10:59:21.683009 0.0;M3 CHK:0;cm4_sp_mode 0
1021 10:59:21.683646 MVN_1=0x00000000
1022 10:59:21.688473 MVN_2=0x00000000
1023 10:59:21.694232 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
1024 10:59:21.694723 OPS=0x10
1025 10:59:21.695141 ring efuse init
1026 10:59:21.695549 chipver efuse init
1027 10:59:21.699797 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
1028 10:59:21.705392 [0.018960 Inits done]
1029 10:59:21.705873 secure task start!
1030 10:59:21.706283 high task start!
1031 10:59:21.709976 low task start!
1032 10:59:21.710454 run into bl31
1033 10:59:21.716682 NOTICE: BL31: v1.3(release):4fc40b1
1034 10:59:21.724479 NOTICE: BL31: Built : 15:58:17, May 22 2019
1035 10:59:21.724981 NOTICE: BL31: G12A normal boot!
1036 10:59:21.750369 NOTICE: BL31: BL33 decompress pass
1037 10:59:21.756046 ERROR: Error initializing runtime service opteed_fast
1038 10:59:22.988885
1039 10:59:22.989479
1040 10:59:22.997284 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
1041 10:59:22.997779
1042 10:59:22.998196 Model: Libre Computer AML-A311D-CC Alta
1043 10:59:23.205552 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
1044 10:59:23.228262 DRAM: 2 GiB (effective 3.8 GiB)
1045 10:59:23.371972 Core: 408 devices, 31 uclasses, devicetree: separate
1046 10:59:23.376901 WDT: Not starting watchdog@f0d0
1047 10:59:23.410126 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
1048 10:59:23.422562 Loading Environment from FAT... Card did not respond to voltage select! : -110
1049 10:59:23.426608 ** Bad device specification mmc 0 **
1050 10:59:23.438037 Card did not respond to voltage select! : -110
1051 10:59:23.444620 ** Bad device specification mmc 0 **
1052 10:59:23.444919 Couldn't find partition mmc 0
1053 10:59:23.453977 Card did not respond to voltage select! : -110
1054 10:59:23.459459 ** Bad device specification mmc 0 **
1055 10:59:23.459732 Couldn't find partition mmc 0
1056 10:59:23.463598 Error: could not access storage.
1057 10:59:23.808068 Net: eth0: ethernet@ff3f0000
1058 10:59:23.808689 starting USB...
1059 10:59:24.059884 Bus usb@ff500000: Register 3000140 NbrPorts 3
1060 10:59:24.060495 Starting the controller
1061 10:59:24.066831 USB XHCI 1.10
1062 10:59:25.623038 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
1063 10:59:25.630421 scanning usb for storage devices... 0 Storage Device(s) found
1065 10:59:25.681939 Hit any key to stop autoboot: 1
1066 10:59:25.682987 end: 2.4.2 bootloader-interrupt (duration 00:00:37) [common]
1067 10:59:25.683611 start: 2.4.3 bootloader-commands (timeout 00:04:23) [common]
1068 10:59:25.684144 Setting prompt string to ['=>']
1069 10:59:25.684621 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:23)
1070 10:59:25.688779 0
1071 10:59:25.689689 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1072 10:59:25.690218 Sending with 10 millisecond of delay
1074 10:59:26.824889 => setenv autoload no
1075 10:59:26.835690 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:22)
1076 10:59:26.840608 setenv autoload no
1077 10:59:26.841345 Sending with 10 millisecond of delay
1079 10:59:28.638587 => setenv initrd_high 0xffffffff
1080 10:59:28.649340 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:20)
1081 10:59:28.650183 setenv initrd_high 0xffffffff
1082 10:59:28.650889 Sending with 10 millisecond of delay
1084 10:59:30.267483 => setenv fdt_high 0xffffffff
1085 10:59:30.278305 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1086 10:59:30.279212 setenv fdt_high 0xffffffff
1087 10:59:30.279936 Sending with 10 millisecond of delay
1089 10:59:30.571699 => dhcp
1090 10:59:30.582295 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1091 10:59:30.582773 dhcp
1092 10:59:30.583013 Speed: 1000, full duplex
1093 10:59:30.583223 BOOTP broadcast 1
1094 10:59:30.591057 DHCP client bound to address 192.168.6.27 (8 ms)
1095 10:59:30.591539 Sending with 10 millisecond of delay
1097 10:59:32.267607 => setenv serverip 192.168.6.2
1098 10:59:32.278405 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:16)
1099 10:59:32.279308 setenv serverip 192.168.6.2
1100 10:59:32.280028 Sending with 10 millisecond of delay
1102 10:59:36.003795 => tftpboot 0x01080000 974725/tftp-deploy-5bh5lpk1/kernel/uImage
1103 10:59:36.014606 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:12)
1104 10:59:36.015561 tftpboot 0x01080000 974725/tftp-deploy-5bh5lpk1/kernel/uImage
1105 10:59:36.016120 Speed: 1000, full duplex
1106 10:59:36.016632 Using ethernet@ff3f0000 device
1107 10:59:36.017248 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1108 10:59:36.022682 Filename '974725/tftp-deploy-5bh5lpk1/kernel/uImage'.
1109 10:59:36.025786 Load address: 0x1080000
1110 10:59:40.348664 Loading: *###################
1111 10:59:40.349281 TFTP error: trying to overwrite reserved memory...
1113 10:59:40.350678 end: 2.4.3 bootloader-commands (duration 00:00:15) [common]
1116 10:59:40.352569 end: 2.4 uboot-commands (duration 00:00:52) [common]
1118 10:59:40.353980 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'TFTP error: trying to overwrite reserved memory' (12)'
1120 10:59:40.355021 end: 2 uboot-action (duration 00:00:52) [common]
1122 10:59:40.356565 Cleaning after the job
1123 10:59:40.357124 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/974725/tftp-deploy-5bh5lpk1/ramdisk
1124 10:59:40.387164 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/974725/tftp-deploy-5bh5lpk1/kernel
1125 10:59:40.440034 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/974725/tftp-deploy-5bh5lpk1/dtb
1126 10:59:40.441175 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/974725/tftp-deploy-5bh5lpk1/modules
1127 10:59:40.496900 start: 4.1 power-off (timeout 00:00:30) [common]
1128 10:59:40.497603 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1129 10:59:40.535537 >> OK - accepted request
1130 10:59:40.537626 Returned 0 in 0 seconds
1131 10:59:40.638409 end: 4.1 power-off (duration 00:00:00) [common]
1133 10:59:40.639402 start: 4.2 read-feedback (timeout 00:10:00) [common]
1134 10:59:40.640091 Listened to connection for namespace 'common' for up to 1s
1135 10:59:41.640270 Finalising connection for namespace 'common'
1136 10:59:41.640789 Disconnecting from shell: Finalise
1137 10:59:41.641078 =>
1138 10:59:41.742101 end: 4.2 read-feedback (duration 00:00:01) [common]
1139 10:59:41.743014 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/974725
1140 10:59:42.138158 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/974725
1141 10:59:42.138805 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.