Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 10:16:06.353310 lava-dispatcher, installed at version: 2024.01
2 10:16:06.354127 start: 0 validate
3 10:16:06.354608 Start time: 2024-11-11 10:16:06.354576+00:00 (UTC)
4 10:16:06.355153 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 10:16:06.355706 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230703.0%2Farm64%2Frootfs.cpio.gz exists
6 10:16:06.394594 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 10:16:06.395150 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241111%2Farm64%2Fdefconfig%2Bkselftest%2Fgcc-12%2Fkernel%2FImage exists
8 10:16:07.433931 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 10:16:07.434609 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241111%2Farm64%2Fdefconfig%2Bkselftest%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 10:16:18.532047 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 10:16:18.532549 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241111%2Farm64%2Fdefconfig%2Bkselftest%2Fgcc-12%2Fmodules.tar.xz exists
12 10:16:18.580773 validate duration: 12.23
14 10:16:18.582184 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 10:16:18.582779 start: 1.1 download-retry (timeout 00:10:00) [common]
16 10:16:18.583319 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 10:16:18.584281 Not decompressing ramdisk as can be used compressed.
18 10:16:18.585156 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230703.0/arm64/rootfs.cpio.gz
19 10:16:18.585592 saving as /var/lib/lava/dispatcher/tmp/974368/tftp-deploy-jlpctpqp/ramdisk/rootfs.cpio.gz
20 10:16:18.586077 total size: 8181887 (7 MB)
21 10:16:18.629526 progress 0 % (0 MB)
22 10:16:18.640119 progress 5 % (0 MB)
23 10:16:18.650165 progress 10 % (0 MB)
24 10:16:18.660976 progress 15 % (1 MB)
25 10:16:18.667655 progress 20 % (1 MB)
26 10:16:18.673289 progress 25 % (1 MB)
27 10:16:18.678397 progress 30 % (2 MB)
28 10:16:18.683914 progress 35 % (2 MB)
29 10:16:18.689106 progress 40 % (3 MB)
30 10:16:18.694724 progress 45 % (3 MB)
31 10:16:18.699897 progress 50 % (3 MB)
32 10:16:18.705564 progress 55 % (4 MB)
33 10:16:18.710680 progress 60 % (4 MB)
34 10:16:18.716202 progress 65 % (5 MB)
35 10:16:18.721288 progress 70 % (5 MB)
36 10:16:18.726790 progress 75 % (5 MB)
37 10:16:18.731831 progress 80 % (6 MB)
38 10:16:18.737303 progress 85 % (6 MB)
39 10:16:18.742421 progress 90 % (7 MB)
40 10:16:18.748035 progress 95 % (7 MB)
41 10:16:18.752769 progress 100 % (7 MB)
42 10:16:18.753431 7 MB downloaded in 0.17 s (46.63 MB/s)
43 10:16:18.753969 end: 1.1.1 http-download (duration 00:00:00) [common]
45 10:16:18.754850 end: 1.1 download-retry (duration 00:00:00) [common]
46 10:16:18.755137 start: 1.2 download-retry (timeout 00:10:00) [common]
47 10:16:18.755403 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 10:16:18.755861 downloading http://storage.kernelci.org/next/master/next-20241111/arm64/defconfig+kselftest/gcc-12/kernel/Image
49 10:16:18.756133 saving as /var/lib/lava/dispatcher/tmp/974368/tftp-deploy-jlpctpqp/kernel/Image
50 10:16:18.756341 total size: 66980352 (63 MB)
51 10:16:18.756554 No compression specified
52 10:16:18.793036 progress 0 % (0 MB)
53 10:16:18.835463 progress 5 % (3 MB)
54 10:16:18.876981 progress 10 % (6 MB)
55 10:16:18.918435 progress 15 % (9 MB)
56 10:16:18.959655 progress 20 % (12 MB)
57 10:16:19.003717 progress 25 % (16 MB)
58 10:16:19.045075 progress 30 % (19 MB)
59 10:16:19.086005 progress 35 % (22 MB)
60 10:16:19.127139 progress 40 % (25 MB)
61 10:16:19.168350 progress 45 % (28 MB)
62 10:16:19.209381 progress 50 % (31 MB)
63 10:16:19.250270 progress 55 % (35 MB)
64 10:16:19.290837 progress 60 % (38 MB)
65 10:16:19.331851 progress 65 % (41 MB)
66 10:16:19.373174 progress 70 % (44 MB)
67 10:16:19.414279 progress 75 % (47 MB)
68 10:16:19.458590 progress 80 % (51 MB)
69 10:16:19.502973 progress 85 % (54 MB)
70 10:16:19.549112 progress 90 % (57 MB)
71 10:16:19.591089 progress 95 % (60 MB)
72 10:16:19.632166 progress 100 % (63 MB)
73 10:16:19.632732 63 MB downloaded in 0.88 s (72.89 MB/s)
74 10:16:19.633248 end: 1.2.1 http-download (duration 00:00:01) [common]
76 10:16:19.634115 end: 1.2 download-retry (duration 00:00:01) [common]
77 10:16:19.634419 start: 1.3 download-retry (timeout 00:09:59) [common]
78 10:16:19.634703 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 10:16:19.635179 downloading http://storage.kernelci.org/next/master/next-20241111/arm64/defconfig+kselftest/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
80 10:16:19.635472 saving as /var/lib/lava/dispatcher/tmp/974368/tftp-deploy-jlpctpqp/dtb/meson-g12b-a311d-libretech-cc.dtb
81 10:16:19.635690 total size: 54703 (0 MB)
82 10:16:19.635912 No compression specified
83 10:16:19.689771 progress 59 % (0 MB)
84 10:16:19.690678 progress 100 % (0 MB)
85 10:16:19.691304 0 MB downloaded in 0.06 s (0.94 MB/s)
86 10:16:19.691798 end: 1.3.1 http-download (duration 00:00:00) [common]
88 10:16:19.692694 end: 1.3 download-retry (duration 00:00:00) [common]
89 10:16:19.692985 start: 1.4 download-retry (timeout 00:09:59) [common]
90 10:16:19.693265 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 10:16:19.693752 downloading http://storage.kernelci.org/next/master/next-20241111/arm64/defconfig+kselftest/gcc-12/modules.tar.xz
92 10:16:19.694009 saving as /var/lib/lava/dispatcher/tmp/974368/tftp-deploy-jlpctpqp/modules/modules.tar
93 10:16:19.694224 total size: 16288464 (15 MB)
94 10:16:19.694445 Using unxz to decompress xz
95 10:16:19.732912 progress 0 % (0 MB)
96 10:16:19.841735 progress 5 % (0 MB)
97 10:16:19.958900 progress 10 % (1 MB)
98 10:16:20.086141 progress 15 % (2 MB)
99 10:16:20.222744 progress 20 % (3 MB)
100 10:16:20.375362 progress 25 % (3 MB)
101 10:16:20.488182 progress 30 % (4 MB)
102 10:16:20.595658 progress 35 % (5 MB)
103 10:16:20.716198 progress 40 % (6 MB)
104 10:16:20.870808 progress 45 % (7 MB)
105 10:16:20.989018 progress 50 % (7 MB)
106 10:16:21.104423 progress 55 % (8 MB)
107 10:16:21.227269 progress 60 % (9 MB)
108 10:16:21.342589 progress 65 % (10 MB)
109 10:16:21.461076 progress 70 % (10 MB)
110 10:16:21.591630 progress 75 % (11 MB)
111 10:16:21.710793 progress 80 % (12 MB)
112 10:16:21.827183 progress 85 % (13 MB)
113 10:16:21.941455 progress 90 % (14 MB)
114 10:16:22.049440 progress 95 % (14 MB)
115 10:16:22.168231 progress 100 % (15 MB)
116 10:16:22.178512 15 MB downloaded in 2.48 s (6.25 MB/s)
117 10:16:22.179159 end: 1.4.1 http-download (duration 00:00:02) [common]
119 10:16:22.180016 end: 1.4 download-retry (duration 00:00:02) [common]
120 10:16:22.180609 start: 1.5 prepare-tftp-overlay (timeout 00:09:56) [common]
121 10:16:22.181188 start: 1.5.1 extract-nfsrootfs (timeout 00:09:56) [common]
122 10:16:22.181732 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 10:16:22.182287 start: 1.5.2 lava-overlay (timeout 00:09:56) [common]
124 10:16:22.183366 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/974368/lava-overlay-06x7hwct
125 10:16:22.184340 makedir: /var/lib/lava/dispatcher/tmp/974368/lava-overlay-06x7hwct/lava-974368/bin
126 10:16:22.185058 makedir: /var/lib/lava/dispatcher/tmp/974368/lava-overlay-06x7hwct/lava-974368/tests
127 10:16:22.185739 makedir: /var/lib/lava/dispatcher/tmp/974368/lava-overlay-06x7hwct/lava-974368/results
128 10:16:22.186405 Creating /var/lib/lava/dispatcher/tmp/974368/lava-overlay-06x7hwct/lava-974368/bin/lava-add-keys
129 10:16:22.187422 Creating /var/lib/lava/dispatcher/tmp/974368/lava-overlay-06x7hwct/lava-974368/bin/lava-add-sources
130 10:16:22.188510 Creating /var/lib/lava/dispatcher/tmp/974368/lava-overlay-06x7hwct/lava-974368/bin/lava-background-process-start
131 10:16:22.189570 Creating /var/lib/lava/dispatcher/tmp/974368/lava-overlay-06x7hwct/lava-974368/bin/lava-background-process-stop
132 10:16:22.190657 Creating /var/lib/lava/dispatcher/tmp/974368/lava-overlay-06x7hwct/lava-974368/bin/lava-common-functions
133 10:16:22.191660 Creating /var/lib/lava/dispatcher/tmp/974368/lava-overlay-06x7hwct/lava-974368/bin/lava-echo-ipv4
134 10:16:22.192705 Creating /var/lib/lava/dispatcher/tmp/974368/lava-overlay-06x7hwct/lava-974368/bin/lava-install-packages
135 10:16:22.193705 Creating /var/lib/lava/dispatcher/tmp/974368/lava-overlay-06x7hwct/lava-974368/bin/lava-installed-packages
136 10:16:22.194685 Creating /var/lib/lava/dispatcher/tmp/974368/lava-overlay-06x7hwct/lava-974368/bin/lava-os-build
137 10:16:22.195669 Creating /var/lib/lava/dispatcher/tmp/974368/lava-overlay-06x7hwct/lava-974368/bin/lava-probe-channel
138 10:16:22.196929 Creating /var/lib/lava/dispatcher/tmp/974368/lava-overlay-06x7hwct/lava-974368/bin/lava-probe-ip
139 10:16:22.198000 Creating /var/lib/lava/dispatcher/tmp/974368/lava-overlay-06x7hwct/lava-974368/bin/lava-target-ip
140 10:16:22.199044 Creating /var/lib/lava/dispatcher/tmp/974368/lava-overlay-06x7hwct/lava-974368/bin/lava-target-mac
141 10:16:22.200120 Creating /var/lib/lava/dispatcher/tmp/974368/lava-overlay-06x7hwct/lava-974368/bin/lava-target-storage
142 10:16:22.201188 Creating /var/lib/lava/dispatcher/tmp/974368/lava-overlay-06x7hwct/lava-974368/bin/lava-test-case
143 10:16:22.202164 Creating /var/lib/lava/dispatcher/tmp/974368/lava-overlay-06x7hwct/lava-974368/bin/lava-test-event
144 10:16:22.203225 Creating /var/lib/lava/dispatcher/tmp/974368/lava-overlay-06x7hwct/lava-974368/bin/lava-test-feedback
145 10:16:22.204340 Creating /var/lib/lava/dispatcher/tmp/974368/lava-overlay-06x7hwct/lava-974368/bin/lava-test-raise
146 10:16:22.205381 Creating /var/lib/lava/dispatcher/tmp/974368/lava-overlay-06x7hwct/lava-974368/bin/lava-test-reference
147 10:16:22.206405 Creating /var/lib/lava/dispatcher/tmp/974368/lava-overlay-06x7hwct/lava-974368/bin/lava-test-runner
148 10:16:22.207409 Creating /var/lib/lava/dispatcher/tmp/974368/lava-overlay-06x7hwct/lava-974368/bin/lava-test-set
149 10:16:22.208445 Creating /var/lib/lava/dispatcher/tmp/974368/lava-overlay-06x7hwct/lava-974368/bin/lava-test-shell
150 10:16:22.209580 Updating /var/lib/lava/dispatcher/tmp/974368/lava-overlay-06x7hwct/lava-974368/bin/lava-install-packages (oe)
151 10:16:22.210684 Updating /var/lib/lava/dispatcher/tmp/974368/lava-overlay-06x7hwct/lava-974368/bin/lava-installed-packages (oe)
152 10:16:22.211626 Creating /var/lib/lava/dispatcher/tmp/974368/lava-overlay-06x7hwct/lava-974368/environment
153 10:16:22.212462 LAVA metadata
154 10:16:22.212997 - LAVA_JOB_ID=974368
155 10:16:22.213466 - LAVA_DISPATCHER_IP=192.168.6.2
156 10:16:22.214208 start: 1.5.2.1 ssh-authorize (timeout 00:09:56) [common]
157 10:16:22.216378 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 10:16:22.217004 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:56) [common]
159 10:16:22.217415 skipped lava-vland-overlay
160 10:16:22.217901 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 10:16:22.218404 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:56) [common]
162 10:16:22.218828 skipped lava-multinode-overlay
163 10:16:22.219311 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 10:16:22.219807 start: 1.5.2.4 test-definition (timeout 00:09:56) [common]
165 10:16:22.220226 Loading test definitions
166 10:16:22.220541 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:56) [common]
167 10:16:22.220771 Using /lava-974368 at stage 0
168 10:16:22.222056 uuid=974368_1.5.2.4.1 testdef=None
169 10:16:22.222396 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 10:16:22.222669 start: 1.5.2.4.2 test-overlay (timeout 00:09:56) [common]
171 10:16:22.224571 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 10:16:22.225427 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:56) [common]
174 10:16:22.227785 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 10:16:22.228691 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:56) [common]
177 10:16:22.230987 runner path: /var/lib/lava/dispatcher/tmp/974368/lava-overlay-06x7hwct/lava-974368/0/tests/0_dmesg test_uuid 974368_1.5.2.4.1
178 10:16:22.231598 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 10:16:22.232419 Creating lava-test-runner.conf files
181 10:16:22.232629 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/974368/lava-overlay-06x7hwct/lava-974368/0 for stage 0
182 10:16:22.233006 - 0_dmesg
183 10:16:22.233395 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 10:16:22.233689 start: 1.5.2.5 compress-overlay (timeout 00:09:56) [common]
185 10:16:22.259465 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 10:16:22.259904 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:56) [common]
187 10:16:22.260216 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 10:16:22.260498 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 10:16:22.260765 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:56) [common]
190 10:16:23.262968 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
191 10:16:23.263464 start: 1.5.4 extract-modules (timeout 00:09:55) [common]
192 10:16:23.263776 extracting modules file /var/lib/lava/dispatcher/tmp/974368/tftp-deploy-jlpctpqp/modules/modules.tar to /var/lib/lava/dispatcher/tmp/974368/extract-overlay-ramdisk-xtur0e_1/ramdisk
193 10:16:24.813064 end: 1.5.4 extract-modules (duration 00:00:02) [common]
194 10:16:24.813549 start: 1.5.5 apply-overlay-tftp (timeout 00:09:54) [common]
195 10:16:24.813822 [common] Applying overlay /var/lib/lava/dispatcher/tmp/974368/compress-overlay-k9smsodd/overlay-1.5.2.5.tar.gz to ramdisk
196 10:16:24.814034 [common] Applying overlay /var/lib/lava/dispatcher/tmp/974368/compress-overlay-k9smsodd/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/974368/extract-overlay-ramdisk-xtur0e_1/ramdisk
197 10:16:24.844875 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 10:16:24.845340 start: 1.5.6 prepare-kernel (timeout 00:09:54) [common]
199 10:16:24.845612 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:54) [common]
200 10:16:24.845842 Converting downloaded kernel to a uImage
201 10:16:24.846155 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/974368/tftp-deploy-jlpctpqp/kernel/Image /var/lib/lava/dispatcher/tmp/974368/tftp-deploy-jlpctpqp/kernel/uImage
202 10:16:25.632327 output: Image Name:
203 10:16:25.632754 output: Created: Mon Nov 11 10:16:24 2024
204 10:16:25.632968 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 10:16:25.633172 output: Data Size: 66980352 Bytes = 65410.50 KiB = 63.88 MiB
206 10:16:25.633372 output: Load Address: 01080000
207 10:16:25.633570 output: Entry Point: 01080000
208 10:16:25.633768 output:
209 10:16:25.634097 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:01) [common]
210 10:16:25.634361 end: 1.5.6 prepare-kernel (duration 00:00:01) [common]
211 10:16:25.634627 start: 1.5.7 configure-preseed-file (timeout 00:09:53) [common]
212 10:16:25.634876 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 10:16:25.635127 start: 1.5.8 compress-ramdisk (timeout 00:09:53) [common]
214 10:16:25.635380 Building ramdisk /var/lib/lava/dispatcher/tmp/974368/extract-overlay-ramdisk-xtur0e_1/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/974368/extract-overlay-ramdisk-xtur0e_1/ramdisk
215 10:16:29.616526 >> 258309 blocks
216 10:16:40.665109 Adding RAMdisk u-boot header.
217 10:16:40.665601 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/974368/extract-overlay-ramdisk-xtur0e_1/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/974368/extract-overlay-ramdisk-xtur0e_1/ramdisk.cpio.gz.uboot
218 10:16:41.037765 output: Image Name:
219 10:16:41.038222 output: Created: Mon Nov 11 10:16:40 2024
220 10:16:41.038772 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 10:16:41.039251 output: Data Size: 33952371 Bytes = 33156.61 KiB = 32.38 MiB
222 10:16:41.039705 output: Load Address: 00000000
223 10:16:41.040196 output: Entry Point: 00000000
224 10:16:41.040642 output:
225 10:16:41.041927 rename /var/lib/lava/dispatcher/tmp/974368/extract-overlay-ramdisk-xtur0e_1/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/974368/tftp-deploy-jlpctpqp/ramdisk/ramdisk.cpio.gz.uboot
226 10:16:41.042805 end: 1.5.8 compress-ramdisk (duration 00:00:15) [common]
227 10:16:41.043457 end: 1.5 prepare-tftp-overlay (duration 00:00:19) [common]
228 10:16:41.044185 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:38) [common]
229 10:16:41.044729 No LXC device requested
230 10:16:41.045312 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 10:16:41.045902 start: 1.7 deploy-device-env (timeout 00:09:38) [common]
232 10:16:41.046464 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 10:16:41.046937 Checking files for TFTP limit of 4294967296 bytes.
234 10:16:41.049984 end: 1 tftp-deploy (duration 00:00:22) [common]
235 10:16:41.050675 start: 2 uboot-action (timeout 00:05:00) [common]
236 10:16:41.051272 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 10:16:41.051839 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 10:16:41.052483 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 10:16:41.053110 Using kernel file from prepare-kernel: 974368/tftp-deploy-jlpctpqp/kernel/uImage
240 10:16:41.053851 substitutions:
241 10:16:41.054328 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 10:16:41.054780 - {DTB_ADDR}: 0x01070000
243 10:16:41.055231 - {DTB}: 974368/tftp-deploy-jlpctpqp/dtb/meson-g12b-a311d-libretech-cc.dtb
244 10:16:41.055680 - {INITRD}: 974368/tftp-deploy-jlpctpqp/ramdisk/ramdisk.cpio.gz.uboot
245 10:16:41.056167 - {KERNEL_ADDR}: 0x01080000
246 10:16:41.056621 - {KERNEL}: 974368/tftp-deploy-jlpctpqp/kernel/uImage
247 10:16:41.057073 - {LAVA_MAC}: None
248 10:16:41.057575 - {PRESEED_CONFIG}: None
249 10:16:41.058028 - {PRESEED_LOCAL}: None
250 10:16:41.058472 - {RAMDISK_ADDR}: 0x08000000
251 10:16:41.058909 - {RAMDISK}: 974368/tftp-deploy-jlpctpqp/ramdisk/ramdisk.cpio.gz.uboot
252 10:16:41.059349 - {ROOT_PART}: None
253 10:16:41.059788 - {ROOT}: None
254 10:16:41.060264 - {SERVER_IP}: 192.168.6.2
255 10:16:41.060711 - {TEE_ADDR}: 0x83000000
256 10:16:41.061149 - {TEE}: None
257 10:16:41.061587 Parsed boot commands:
258 10:16:41.062014 - setenv autoload no
259 10:16:41.062449 - setenv initrd_high 0xffffffff
260 10:16:41.062880 - setenv fdt_high 0xffffffff
261 10:16:41.063311 - dhcp
262 10:16:41.063742 - setenv serverip 192.168.6.2
263 10:16:41.064207 - tftpboot 0x01080000 974368/tftp-deploy-jlpctpqp/kernel/uImage
264 10:16:41.064653 - tftpboot 0x08000000 974368/tftp-deploy-jlpctpqp/ramdisk/ramdisk.cpio.gz.uboot
265 10:16:41.065088 - tftpboot 0x01070000 974368/tftp-deploy-jlpctpqp/dtb/meson-g12b-a311d-libretech-cc.dtb
266 10:16:41.065522 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 10:16:41.065971 - bootm 0x01080000 0x08000000 0x01070000
268 10:16:41.066561 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 10:16:41.068300 start: 2.3 connect-device (timeout 00:05:00) [common]
271 10:16:41.068822 [common] connect-device Connecting to device using 'telnet conserv1 3007'
272 10:16:41.083894 Setting prompt string to ['lava-test: # ']
273 10:16:41.085574 end: 2.3 connect-device (duration 00:00:00) [common]
274 10:16:41.086262 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 10:16:41.086876 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 10:16:41.087479 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 10:16:41.088823 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
278 10:16:41.126884 >> OK - accepted request
279 10:16:41.129120 Returned 0 in 0 seconds
280 10:16:41.230331 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
282 10:16:41.232320 end: 2.4.1 reset-device (duration 00:00:00) [common]
283 10:16:41.232983 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
284 10:16:41.233558 Setting prompt string to ['Hit any key to stop autoboot']
285 10:16:41.234078 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 10:16:41.235851 Trying 192.168.56.21...
287 10:16:41.236446 Connected to conserv1.
288 10:16:41.236926 Escape character is '^]'.
289 10:16:41.237402
290 10:16:41.237880 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
291 10:16:41.238351
292 10:16:53.544068 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
293 10:16:53.544777 bl2_stage_init 0x01
294 10:16:53.545299 bl2_stage_init 0x81
295 10:16:53.548640 hw id: 0x0000 - pwm id 0x01
296 10:16:53.549287 bl2_stage_init 0xc1
297 10:16:53.549833 bl2_stage_init 0x02
298 10:16:53.550309
299 10:16:53.554147 L0:00000000
300 10:16:53.554667 L1:20000703
301 10:16:53.555101 L2:00008067
302 10:16:53.555533 L3:14000000
303 10:16:53.559589 B2:00402000
304 10:16:53.560116 B1:e0f83180
305 10:16:53.560554
306 10:16:53.560986 TE: 58159
307 10:16:53.561416
308 10:16:53.565315 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
309 10:16:53.565804
310 10:16:53.566245 Board ID = 1
311 10:16:53.570839 Set A53 clk to 24M
312 10:16:53.571313 Set A73 clk to 24M
313 10:16:53.571741 Set clk81 to 24M
314 10:16:53.576866 A53 clk: 1200 MHz
315 10:16:53.577343 A73 clk: 1200 MHz
316 10:16:53.577772 CLK81: 166.6M
317 10:16:53.578200 smccc: 00012ab5
318 10:16:53.582195 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
319 10:16:53.587583 board id: 1
320 10:16:53.593655 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
321 10:16:53.604019 fw parse done
322 10:16:53.610097 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
323 10:16:53.652701 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
324 10:16:53.663616 PIEI prepare done
325 10:16:53.664168 fastboot data load
326 10:16:53.664637 fastboot data verify
327 10:16:53.669246 verify result: 266
328 10:16:53.674806 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
329 10:16:53.675283 LPDDR4 probe
330 10:16:53.675739 ddr clk to 1584MHz
331 10:16:53.682797 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
332 10:16:53.720081
333 10:16:53.720589 dmc_version 0001
334 10:16:53.726769 Check phy result
335 10:16:53.732805 INFO : End of CA training
336 10:16:53.733275 INFO : End of initialization
337 10:16:53.738281 INFO : Training has run successfully!
338 10:16:53.738747 Check phy result
339 10:16:53.743796 INFO : End of initialization
340 10:16:53.744292 INFO : End of read enable training
341 10:16:53.747101 INFO : End of fine write leveling
342 10:16:53.752653 INFO : End of Write leveling coarse delay
343 10:16:53.758248 INFO : Training has run successfully!
344 10:16:53.758708 Check phy result
345 10:16:53.759148 INFO : End of initialization
346 10:16:53.763867 INFO : End of read dq deskew training
347 10:16:53.769466 INFO : End of MPR read delay center optimization
348 10:16:53.769960 INFO : End of write delay center optimization
349 10:16:53.775094 INFO : End of read delay center optimization
350 10:16:53.780669 INFO : End of max read latency training
351 10:16:53.781138 INFO : Training has run successfully!
352 10:16:53.786243 1D training succeed
353 10:16:53.792253 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
354 10:16:53.839713 Check phy result
355 10:16:53.840307 INFO : End of initialization
356 10:16:53.862227 INFO : End of 2D read delay Voltage center optimization
357 10:16:53.882426 INFO : End of 2D read delay Voltage center optimization
358 10:16:53.934214 INFO : End of 2D write delay Voltage center optimization
359 10:16:53.983507 INFO : End of 2D write delay Voltage center optimization
360 10:16:53.989030 INFO : Training has run successfully!
361 10:16:53.989510
362 10:16:53.989950 channel==0
363 10:16:53.994638 RxClkDly_Margin_A0==88 ps 9
364 10:16:53.995176 TxDqDly_Margin_A0==98 ps 10
365 10:16:54.000244 RxClkDly_Margin_A1==88 ps 9
366 10:16:54.000715 TxDqDly_Margin_A1==98 ps 10
367 10:16:54.001157 TrainedVREFDQ_A0==74
368 10:16:54.005797 TrainedVREFDQ_A1==74
369 10:16:54.006259 VrefDac_Margin_A0==25
370 10:16:54.006692 DeviceVref_Margin_A0==40
371 10:16:54.011467 VrefDac_Margin_A1==25
372 10:16:54.011926 DeviceVref_Margin_A1==40
373 10:16:54.012399
374 10:16:54.012838
375 10:16:54.017037 channel==1
376 10:16:54.017506 RxClkDly_Margin_A0==98 ps 10
377 10:16:54.017944 TxDqDly_Margin_A0==88 ps 9
378 10:16:54.022598 RxClkDly_Margin_A1==98 ps 10
379 10:16:54.023067 TxDqDly_Margin_A1==98 ps 10
380 10:16:54.028204 TrainedVREFDQ_A0==76
381 10:16:54.028675 TrainedVREFDQ_A1==78
382 10:16:54.029113 VrefDac_Margin_A0==23
383 10:16:54.033803 DeviceVref_Margin_A0==38
384 10:16:54.034261 VrefDac_Margin_A1==22
385 10:16:54.039424 DeviceVref_Margin_A1==36
386 10:16:54.039886
387 10:16:54.040365 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
388 10:16:54.044972
389 10:16:54.073008 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000019 00000017 00000018 00000016 00000018 00000015 00000017 00000019 00000018 00000019 00000018 0000001a 0000001a 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
390 10:16:54.073611 2D training succeed
391 10:16:54.078586 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
392 10:16:54.084196 auto size-- 65535DDR cs0 size: 2048MB
393 10:16:54.084661 DDR cs1 size: 2048MB
394 10:16:54.089788 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
395 10:16:54.090245 cs0 DataBus test pass
396 10:16:54.095459 cs1 DataBus test pass
397 10:16:54.095916 cs0 AddrBus test pass
398 10:16:54.096397 cs1 AddrBus test pass
399 10:16:54.096829
400 10:16:54.100980 100bdlr_step_size ps== 420
401 10:16:54.101455 result report
402 10:16:54.106555 boot times 0Enable ddr reg access
403 10:16:54.112047 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
404 10:16:54.125497 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
405 10:16:54.697792 0.0;M3 CHK:0;cm4_sp_mode 0
406 10:16:54.698401 MVN_1=0x00000000
407 10:16:54.703069 MVN_2=0x00000000
408 10:16:54.708817 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
409 10:16:54.709297 OPS=0x10
410 10:16:54.709753 ring efuse init
411 10:16:54.710194 chipver efuse init
412 10:16:54.717116 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
413 10:16:54.717615 [0.018961 Inits done]
414 10:16:54.718063 secure task start!
415 10:16:54.724405 high task start!
416 10:16:54.724881 low task start!
417 10:16:54.725329 run into bl31
418 10:16:54.731264 NOTICE: BL31: v1.3(release):4fc40b1
419 10:16:54.739067 NOTICE: BL31: Built : 15:58:17, May 22 2019
420 10:16:54.739569 NOTICE: BL31: G12A normal boot!
421 10:16:54.764435 NOTICE: BL31: BL33 decompress pass
422 10:16:54.770115 ERROR: Error initializing runtime service opteed_fast
423 10:16:56.003131
424 10:16:56.003790
425 10:16:56.011390 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
426 10:16:56.011892
427 10:16:56.012399 Model: Libre Computer AML-A311D-CC Alta
428 10:16:56.220099 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
429 10:16:56.243198 DRAM: 2 GiB (effective 3.8 GiB)
430 10:16:56.386140 Core: 408 devices, 31 uclasses, devicetree: separate
431 10:16:56.392080 WDT: Not starting watchdog@f0d0
432 10:16:56.424463 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
433 10:16:56.436776 Loading Environment from FAT... Card did not respond to voltage select! : -110
434 10:16:56.441848 ** Bad device specification mmc 0 **
435 10:16:56.452085 Card did not respond to voltage select! : -110
436 10:16:56.459733 ** Bad device specification mmc 0 **
437 10:16:56.460257 Couldn't find partition mmc 0
438 10:16:56.468067 Card did not respond to voltage select! : -110
439 10:16:56.473652 ** Bad device specification mmc 0 **
440 10:16:56.474145 Couldn't find partition mmc 0
441 10:16:56.478646 Error: could not access storage.
442 10:16:57.742900 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
443 10:16:57.743310 bl2_stage_init 0x01
444 10:16:57.743530 bl2_stage_init 0x81
445 10:16:57.748481 hw id: 0x0000 - pwm id 0x01
446 10:16:57.749000 bl2_stage_init 0xc1
447 10:16:57.749431 bl2_stage_init 0x02
448 10:16:57.749847
449 10:16:57.754079 L0:00000000
450 10:16:57.754525 L1:20000703
451 10:16:57.754936 L2:00008067
452 10:16:57.755340 L3:14000000
453 10:16:57.759642 B2:00402000
454 10:16:57.760092 B1:e0f83180
455 10:16:57.760499
456 10:16:57.760904 TE: 58124
457 10:16:57.761306
458 10:16:57.765248 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
459 10:16:57.765696
460 10:16:57.766107 Board ID = 1
461 10:16:57.770890 Set A53 clk to 24M
462 10:16:57.771359 Set A73 clk to 24M
463 10:16:57.771775 Set clk81 to 24M
464 10:16:57.776477 A53 clk: 1200 MHz
465 10:16:57.777010 A73 clk: 1200 MHz
466 10:16:57.777447 CLK81: 166.6M
467 10:16:57.777865 smccc: 00012a92
468 10:16:57.782033 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
469 10:16:57.787643 board id: 1
470 10:16:57.793540 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
471 10:16:57.804218 fw parse done
472 10:16:57.810155 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
473 10:16:57.852855 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
474 10:16:57.863692 PIEI prepare done
475 10:16:57.864216 fastboot data load
476 10:16:57.864651 fastboot data verify
477 10:16:57.869367 verify result: 266
478 10:16:57.874989 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
479 10:16:57.875443 LPDDR4 probe
480 10:16:57.875859 ddr clk to 1584MHz
481 10:16:57.882945 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
482 10:16:57.920260
483 10:16:57.920819 dmc_version 0001
484 10:16:57.926936 Check phy result
485 10:16:57.932744 INFO : End of CA training
486 10:16:57.933192 INFO : End of initialization
487 10:16:57.938341 INFO : Training has run successfully!
488 10:16:57.938788 Check phy result
489 10:16:57.943972 INFO : End of initialization
490 10:16:57.944450 INFO : End of read enable training
491 10:16:57.949532 INFO : End of fine write leveling
492 10:16:57.955120 INFO : End of Write leveling coarse delay
493 10:16:57.955575 INFO : Training has run successfully!
494 10:16:57.956025 Check phy result
495 10:16:57.960736 INFO : End of initialization
496 10:16:57.961189 INFO : End of read dq deskew training
497 10:16:57.966304 INFO : End of MPR read delay center optimization
498 10:16:57.972019 INFO : End of write delay center optimization
499 10:16:57.977532 INFO : End of read delay center optimization
500 10:16:57.977978 INFO : End of max read latency training
501 10:16:57.983118 INFO : Training has run successfully!
502 10:16:57.983564 1D training succeed
503 10:16:57.992330 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
504 10:16:58.040068 Check phy result
505 10:16:58.040666 INFO : End of initialization
506 10:16:58.062541 INFO : End of 2D read delay Voltage center optimization
507 10:16:58.082747 INFO : End of 2D read delay Voltage center optimization
508 10:16:58.134876 INFO : End of 2D write delay Voltage center optimization
509 10:16:58.184225 INFO : End of 2D write delay Voltage center optimization
510 10:16:58.189781 INFO : Training has run successfully!
511 10:16:58.190257
512 10:16:58.190679 channel==0
513 10:16:58.195354 RxClkDly_Margin_A0==88 ps 9
514 10:16:58.195807 TxDqDly_Margin_A0==98 ps 10
515 10:16:58.201056 RxClkDly_Margin_A1==88 ps 9
516 10:16:58.201610 TxDqDly_Margin_A1==98 ps 10
517 10:16:58.202041 TrainedVREFDQ_A0==74
518 10:16:58.206534 TrainedVREFDQ_A1==74
519 10:16:58.207010 VrefDac_Margin_A0==25
520 10:16:58.207429 DeviceVref_Margin_A0==40
521 10:16:58.212201 VrefDac_Margin_A1==25
522 10:16:58.212668 DeviceVref_Margin_A1==40
523 10:16:58.213080
524 10:16:58.213483
525 10:16:58.217739 channel==1
526 10:16:58.218214 RxClkDly_Margin_A0==88 ps 9
527 10:16:58.218629 TxDqDly_Margin_A0==98 ps 10
528 10:16:58.223343 RxClkDly_Margin_A1==98 ps 10
529 10:16:58.223801 TxDqDly_Margin_A1==88 ps 9
530 10:16:58.229049 TrainedVREFDQ_A0==77
531 10:16:58.229523 TrainedVREFDQ_A1==77
532 10:16:58.229941 VrefDac_Margin_A0==23
533 10:16:58.234569 DeviceVref_Margin_A0==37
534 10:16:58.235028 VrefDac_Margin_A1==23
535 10:16:58.240188 DeviceVref_Margin_A1==37
536 10:16:58.240642
537 10:16:58.241057 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
538 10:16:58.241457
539 10:16:58.273762 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000017 00000018 00000015 00000018 00000019 00000018 00000019 00000018 00000019 0000001a 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000019 00000018 dram_vref_reg_value 0x 00000060
540 10:16:58.274298 2D training succeed
541 10:16:58.279314 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
542 10:16:58.285037 auto size-- 65535DDR cs0 size: 2048MB
543 10:16:58.285506 DDR cs1 size: 2048MB
544 10:16:58.290536 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
545 10:16:58.290998 cs0 DataBus test pass
546 10:16:58.296193 cs1 DataBus test pass
547 10:16:58.296646 cs0 AddrBus test pass
548 10:16:58.297058 cs1 AddrBus test pass
549 10:16:58.297480
550 10:16:58.301779 100bdlr_step_size ps== 420
551 10:16:58.302341 result report
552 10:16:58.307326 boot times 0Enable ddr reg access
553 10:16:58.312707 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
554 10:16:58.326158 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
555 10:16:58.900198 0.0;M3 CHK:0;cm4_sp_mode 0
556 10:16:58.900841 MVN_1=0x00000000
557 10:16:58.905457 MVN_2=0x00000000
558 10:16:58.911296 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
559 10:16:58.911846 OPS=0x10
560 10:16:58.912370 ring efuse init
561 10:16:58.912831 chipver efuse init
562 10:16:58.916884 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
563 10:16:58.922458 [0.018961 Inits done]
564 10:16:58.922903 secure task start!
565 10:16:58.923297 high task start!
566 10:16:58.927126 low task start!
567 10:16:58.927558 run into bl31
568 10:16:58.933688 NOTICE: BL31: v1.3(release):4fc40b1
569 10:16:58.941502 NOTICE: BL31: Built : 15:58:17, May 22 2019
570 10:16:58.941944 NOTICE: BL31: G12A normal boot!
571 10:16:58.966939 NOTICE: BL31: BL33 decompress pass
572 10:16:58.972559 ERROR: Error initializing runtime service opteed_fast
573 10:17:00.205565
574 10:17:00.206182
575 10:17:00.213924 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
576 10:17:00.214378
577 10:17:00.214782 Model: Libre Computer AML-A311D-CC Alta
578 10:17:00.422418 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
579 10:17:00.445665 DRAM: 2 GiB (effective 3.8 GiB)
580 10:17:00.588650 Core: 408 devices, 31 uclasses, devicetree: separate
581 10:17:00.594552 WDT: Not starting watchdog@f0d0
582 10:17:00.626912 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
583 10:17:00.639361 Loading Environment from FAT... Card did not respond to voltage select! : -110
584 10:17:00.644352 ** Bad device specification mmc 0 **
585 10:17:00.654621 Card did not respond to voltage select! : -110
586 10:17:00.662310 ** Bad device specification mmc 0 **
587 10:17:00.662831 Couldn't find partition mmc 0
588 10:17:00.670616 Card did not respond to voltage select! : -110
589 10:17:00.676076 ** Bad device specification mmc 0 **
590 10:17:00.676586 Couldn't find partition mmc 0
591 10:17:00.681151 Error: could not access storage.
592 10:17:01.023789 Net: eth0: ethernet@ff3f0000
593 10:17:01.024254 starting USB...
594 10:17:01.275626 Bus usb@ff500000: Register 3000140 NbrPorts 3
595 10:17:01.276084 Starting the controller
596 10:17:01.282392 USB XHCI 1.10
597 10:17:02.993563 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
598 10:17:02.994022 bl2_stage_init 0x01
599 10:17:02.994246 bl2_stage_init 0x81
600 10:17:02.999294 hw id: 0x0000 - pwm id 0x01
601 10:17:02.999729 bl2_stage_init 0xc1
602 10:17:03.000008 bl2_stage_init 0x02
603 10:17:03.000251
604 10:17:03.005147 L0:00000000
605 10:17:03.005693 L1:20000703
606 10:17:03.006100 L2:00008067
607 10:17:03.006384 L3:14000000
608 10:17:03.007547 B2:00402000
609 10:17:03.007965 B1:e0f83180
610 10:17:03.008236
611 10:17:03.008512 TE: 58167
612 10:17:03.008766
613 10:17:03.018773 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
614 10:17:03.019394
615 10:17:03.019837 Board ID = 1
616 10:17:03.020338 Set A53 clk to 24M
617 10:17:03.020825 Set A73 clk to 24M
618 10:17:03.024303 Set clk81 to 24M
619 10:17:03.024858 A53 clk: 1200 MHz
620 10:17:03.025327 A73 clk: 1200 MHz
621 10:17:03.027795 CLK81: 166.6M
622 10:17:03.028158 smccc: 00012abe
623 10:17:03.033304 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
624 10:17:03.038867 board id: 1
625 10:17:03.044355 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
626 10:17:03.054663 fw parse done
627 10:17:03.060665 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
628 10:17:03.103221 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
629 10:17:03.114247 PIEI prepare done
630 10:17:03.114649 fastboot data load
631 10:17:03.114874 fastboot data verify
632 10:17:03.119827 verify result: 266
633 10:17:03.125422 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
634 10:17:03.125992 LPDDR4 probe
635 10:17:03.126257 ddr clk to 1584MHz
636 10:17:03.133482 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
637 10:17:03.170803
638 10:17:03.171238 dmc_version 0001
639 10:17:03.176600 Check phy result
640 10:17:03.183248 INFO : End of CA training
641 10:17:03.183855 INFO : End of initialization
642 10:17:03.188830 INFO : Training has run successfully!
643 10:17:03.189257 Check phy result
644 10:17:03.194325 INFO : End of initialization
645 10:17:03.194694 INFO : End of read enable training
646 10:17:03.200002 INFO : End of fine write leveling
647 10:17:03.205643 INFO : End of Write leveling coarse delay
648 10:17:03.206035 INFO : Training has run successfully!
649 10:17:03.206251 Check phy result
650 10:17:03.211189 INFO : End of initialization
651 10:17:03.211717 INFO : End of read dq deskew training
652 10:17:03.216801 INFO : End of MPR read delay center optimization
653 10:17:03.222393 INFO : End of write delay center optimization
654 10:17:03.228029 INFO : End of read delay center optimization
655 10:17:03.228424 INFO : End of max read latency training
656 10:17:03.233664 INFO : Training has run successfully!
657 10:17:03.234065 1D training succeed
658 10:17:03.242808 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
659 10:17:03.290379 Check phy result
660 10:17:03.290812 INFO : End of initialization
661 10:17:03.313009 INFO : End of 2D read delay Voltage center optimization
662 10:17:03.335019 INFO : End of 2D read delay Voltage center optimization
663 10:17:03.385385 INFO : End of 2D write delay Voltage center optimization
664 10:17:03.434913 INFO : End of 2D write delay Voltage center optimization
665 10:17:03.440135 INFO : Training has run successfully!
666 10:17:03.440481
667 10:17:03.440748 channel==0
668 10:17:03.445800 RxClkDly_Margin_A0==88 ps 9
669 10:17:03.446140 TxDqDly_Margin_A0==98 ps 10
670 10:17:03.451361 RxClkDly_Margin_A1==88 ps 9
671 10:17:03.451940 TxDqDly_Margin_A1==98 ps 10
672 10:17:03.452488 TrainedVREFDQ_A0==74
673 10:17:03.456954 TrainedVREFDQ_A1==74
674 10:17:03.457580 VrefDac_Margin_A0==25
675 10:17:03.458060 DeviceVref_Margin_A0==40
676 10:17:03.462654 VrefDac_Margin_A1==25
677 10:17:03.463244 DeviceVref_Margin_A1==40
678 10:17:03.463525
679 10:17:03.463789
680 10:17:03.468203 channel==1
681 10:17:03.468607 RxClkDly_Margin_A0==98 ps 10
682 10:17:03.468863 TxDqDly_Margin_A0==98 ps 10
683 10:17:03.473761 RxClkDly_Margin_A1==98 ps 10
684 10:17:03.474126 TxDqDly_Margin_A1==98 ps 10
685 10:17:03.479381 TrainedVREFDQ_A0==77
686 10:17:03.479725 TrainedVREFDQ_A1==78
687 10:17:03.479943 VrefDac_Margin_A0==23
688 10:17:03.484978 DeviceVref_Margin_A0==37
689 10:17:03.485338 VrefDac_Margin_A1==23
690 10:17:03.490692 DeviceVref_Margin_A1==36
691 10:17:03.491060
692 10:17:03.491273 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
693 10:17:03.496829
694 10:17:03.524306 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000018 00000018 00000016 00000018 00000015 00000018 00000019 00000018 00000019 00000018 0000001a 0000001a 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
695 10:17:03.524880 2D training succeed
696 10:17:03.529721 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
697 10:17:03.535443 auto size-- 65535DDR cs0 size: 2048MB
698 10:17:03.535835 DDR cs1 size: 2048MB
699 10:17:03.541087 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
700 10:17:03.541513 cs0 DataBus test pass
701 10:17:03.546667 cs1 DataBus test pass
702 10:17:03.547163 cs0 AddrBus test pass
703 10:17:03.547440 cs1 AddrBus test pass
704 10:17:03.547678
705 10:17:03.552174 100bdlr_step_size ps== 420
706 10:17:03.552771 result report
707 10:17:03.557786 boot times 0Enable ddr reg access
708 10:17:03.563251 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
709 10:17:03.576875 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
710 10:17:04.150261 0.0;M3 CHK:0;cm4_sp_mode 0
711 10:17:04.150671 MVN_1=0x00000000
712 10:17:04.155848 MVN_2=0x00000000
713 10:17:04.161567 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
714 10:17:04.161902 OPS=0x10
715 10:17:04.162113 ring efuse init
716 10:17:04.162316 chipver efuse init
717 10:17:04.167149 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
718 10:17:04.172750 [0.018960 Inits done]
719 10:17:04.173081 secure task start!
720 10:17:04.173289 high task start!
721 10:17:04.177323 low task start!
722 10:17:04.177629 run into bl31
723 10:17:04.184040 NOTICE: BL31: v1.3(release):4fc40b1
724 10:17:04.191878 NOTICE: BL31: Built : 15:58:17, May 22 2019
725 10:17:04.192272 NOTICE: BL31: G12A normal boot!
726 10:17:04.217156 NOTICE: BL31: BL33 decompress pass
727 10:17:04.222959 ERROR: Error initializing runtime service opteed_fast
728 10:17:05.455696
729 10:17:05.456373
730 10:17:05.464064 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
731 10:17:05.464522
732 10:17:05.464930 Model: Libre Computer AML-A311D-CC Alta
733 10:17:05.672475 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
734 10:17:05.695812 DRAM: 2 GiB (effective 3.8 GiB)
735 10:17:05.838845 Core: 408 devices, 31 uclasses, devicetree: separate
736 10:17:05.844694 WDT: Not starting watchdog@f0d0
737 10:17:05.876970 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
738 10:17:05.889413 Loading Environment from FAT... Card did not respond to voltage select! : -110
739 10:17:05.894390 ** Bad device specification mmc 0 **
740 10:17:05.904733 Card did not respond to voltage select! : -110
741 10:17:05.912346 ** Bad device specification mmc 0 **
742 10:17:05.912773 Couldn't find partition mmc 0
743 10:17:05.920696 Card did not respond to voltage select! : -110
744 10:17:05.926222 ** Bad device specification mmc 0 **
745 10:17:05.926671 Couldn't find partition mmc 0
746 10:17:05.931368 Error: could not access storage.
747 10:17:06.273819 Net: eth0: ethernet@ff3f0000
748 10:17:06.274447 starting USB...
749 10:17:06.525621 Bus usb@ff500000: Register 3000140 NbrPorts 3
750 10:17:06.526251 Starting the controller
751 10:17:06.532479 USB XHCI 1.10
752 10:17:08.694781 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
753 10:17:08.695414 bl2_stage_init 0x01
754 10:17:08.695847 bl2_stage_init 0x81
755 10:17:08.700484 hw id: 0x0000 - pwm id 0x01
756 10:17:08.700941 bl2_stage_init 0xc1
757 10:17:08.701354 bl2_stage_init 0x02
758 10:17:08.701769
759 10:17:08.706113 L0:00000000
760 10:17:08.706559 L1:20000703
761 10:17:08.706969 L2:00008067
762 10:17:08.707370 L3:14000000
763 10:17:08.711567 B2:00402000
764 10:17:08.712042 B1:e0f83180
765 10:17:08.712462
766 10:17:08.712869 TE: 58124
767 10:17:08.713270
768 10:17:08.717073 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
769 10:17:08.717523
770 10:17:08.717934 Board ID = 1
771 10:17:08.722670 Set A53 clk to 24M
772 10:17:08.723112 Set A73 clk to 24M
773 10:17:08.723519 Set clk81 to 24M
774 10:17:08.728266 A53 clk: 1200 MHz
775 10:17:08.728719 A73 clk: 1200 MHz
776 10:17:08.729121 CLK81: 166.6M
777 10:17:08.729515 smccc: 00012a92
778 10:17:08.733852 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
779 10:17:08.739429 board id: 1
780 10:17:08.745377 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
781 10:17:08.756031 fw parse done
782 10:17:08.762014 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
783 10:17:08.805307 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
784 10:17:08.815482 PIEI prepare done
785 10:17:08.815943 fastboot data load
786 10:17:08.816408 fastboot data verify
787 10:17:08.821111 verify result: 266
788 10:17:08.826754 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
789 10:17:08.827202 LPDDR4 probe
790 10:17:08.827610 ddr clk to 1584MHz
791 10:17:08.834715 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
792 10:17:08.872060
793 10:17:08.872551 dmc_version 0001
794 10:17:08.878613 Check phy result
795 10:17:08.884527 INFO : End of CA training
796 10:17:08.885002 INFO : End of initialization
797 10:17:09.182861 INFO : Training has run successfully!
798 10:17:09.183801 Check phy result
799 10:17:09.184322 INFO : End of initialization
800 10:17:09.184746 INFO : End of read enable training
801 10:17:09.185153 INFO : End of fine write leveling
802 10:17:09.185575 INFO : End of Write leveling coarse delay
803 10:17:09.185978 INFO : Training has run successfully!
804 10:17:09.186362 Check phy result
805 10:17:09.186746 INFO : End of initialization
806 10:17:09.187130 INFO : End of read dq deskew training
807 10:17:09.187525 INFO : End of MPR read delay center optimization
808 10:17:09.187929 INFO : End of write delay center optimization
809 10:17:09.188413 INFO : End of read delay center optimization
810 10:17:09.188822 INFO : End of max read latency training
811 10:17:09.189229 INFO : Training has run successfully!
812 10:17:09.189648 1D training succeed
813 10:17:09.190060 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
814 10:17:09.190448 Check phy result
815 10:17:09.190983 INFO : End of initialization
816 10:17:09.191389 INFO : End of 2D read delay Voltage center optimization
817 10:17:09.191775 INFO : End of 2D read delay Voltage center optimization
818 10:17:09.192191 INFO : End of 2D write delay Voltage center optimization
819 10:17:09.192576 INFO : End of 2D write delay Voltage center optimization
820 10:17:09.192953 INFO : Training has run successfully!
821 10:17:09.193331
822 10:17:09.193708 channel==0
823 10:17:09.194083 RxClkDly_Margin_A0==88 ps 9
824 10:17:09.194460 TxDqDly_Margin_A0==98 ps 10
825 10:17:09.194841 RxClkDly_Margin_A1==88 ps 9
826 10:17:09.195216 TxDqDly_Margin_A1==98 ps 10
827 10:17:09.195594 TrainedVREFDQ_A0==74
828 10:17:09.195972 TrainedVREFDQ_A1==74
829 10:17:09.196388 VrefDac_Margin_A0==25
830 10:17:09.196763 DeviceVref_Margin_A0==40
831 10:17:09.197136 VrefDac_Margin_A1==25
832 10:17:09.197506 DeviceVref_Margin_A1==40
833 10:17:09.197876
834 10:17:09.198249
835 10:17:09.198624 channel==1
836 10:17:09.198998 RxClkDly_Margin_A0==98 ps 10
837 10:17:09.199369 TxDqDly_Margin_A0==98 ps 10
838 10:17:09.199747 RxClkDly_Margin_A1==98 ps 10
839 10:17:09.200143 TxDqDly_Margin_A1==88 ps 9
840 10:17:09.200538 TrainedVREFDQ_A0==78
841 10:17:09.200916 TrainedVREFDQ_A1==77
842 10:17:09.201293 VrefDac_Margin_A0==22
843 10:17:09.201665 DeviceVref_Margin_A0==36
844 10:17:09.202036 VrefDac_Margin_A1==24
845 10:17:09.202406 DeviceVref_Margin_A1==37
846 10:17:09.202774
847 10:17:09.203238 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
848 10:17:09.203632
849 10:17:09.225248 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000018 00000019 00000018 00000019 00000018 0000001a 0000001a 00000018 00000017 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
850 10:17:09.225741 2D training succeed
851 10:17:09.230860 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
852 10:17:09.236490 auto size-- 65535DDR cs0 size: 2048MB
853 10:17:09.236970 DDR cs1 size: 2048MB
854 10:17:09.242069 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
855 10:17:09.242499 cs0 DataBus test pass
856 10:17:09.242888 cs1 DataBus test pass
857 10:17:09.247810 cs0 AddrBus test pass
858 10:17:09.248274 cs1 AddrBus test pass
859 10:17:09.248663
860 10:17:09.253422 100bdlr_step_size ps== 420
861 10:17:09.253863 result report
862 10:17:09.254249 boot times 0Enable ddr reg access
863 10:17:09.263228 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
864 10:17:09.276722 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
865 10:17:09.848987 0.0;M3 CHK:0;cm4_sp_mode 0
866 10:17:09.849608 MVN_1=0x00000000
867 10:17:09.854286 MVN_2=0x00000000
868 10:17:09.860062 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
869 10:17:09.860520 OPS=0x10
870 10:17:09.860939 ring efuse init
871 10:17:09.861357 chipver efuse init
872 10:17:09.868545 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
873 10:17:09.869012 [0.018961 Inits done]
874 10:17:09.869424 secure task start!
875 10:17:09.875830 high task start!
876 10:17:09.876305 low task start!
877 10:17:09.876718 run into bl31
878 10:17:09.882304 NOTICE: BL31: v1.3(release):4fc40b1
879 10:17:09.890242 NOTICE: BL31: Built : 15:58:17, May 22 2019
880 10:17:09.890683 NOTICE: BL31: G12A normal boot!
881 10:17:09.915624 NOTICE: BL31: BL33 decompress pass
882 10:17:09.921240 ERROR: Error initializing runtime service opteed_fast
883 10:17:11.154224
884 10:17:11.154869
885 10:17:11.162613 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
886 10:17:11.163075
887 10:17:11.163494 Model: Libre Computer AML-A311D-CC Alta
888 10:17:11.371240 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
889 10:17:11.394544 DRAM: 2 GiB (effective 3.8 GiB)
890 10:17:11.537391 Core: 408 devices, 31 uclasses, devicetree: separate
891 10:17:11.543183 WDT: Not starting watchdog@f0d0
892 10:17:11.575537 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
893 10:17:11.587940 Loading Environment from FAT... Card did not respond to voltage select! : -110
894 10:17:11.593058 ** Bad device specification mmc 0 **
895 10:17:11.603187 Card did not respond to voltage select! : -110
896 10:17:11.611062 ** Bad device specification mmc 0 **
897 10:17:11.611536 Couldn't find partition mmc 0
898 10:17:11.619183 Card did not respond to voltage select! : -110
899 10:17:11.624856 ** Bad device specification mmc 0 **
900 10:17:11.625301 Couldn't find partition mmc 0
901 10:17:11.629919 Error: could not access storage.
902 10:17:11.972363 Net: eth0: ethernet@ff3f0000
903 10:17:11.972931 starting USB...
904 10:17:12.224438 Bus usb@ff500000: Register 3000140 NbrPorts 3
905 10:17:12.225096 Starting the controller
906 10:17:12.231352 USB XHCI 1.10
907 10:17:13.785393 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
908 10:17:13.793573 scanning usb for storage devices... 0 Storage Device(s) found
910 10:17:13.845035 Hit any key to stop autoboot: 1
911 10:17:13.845810 end: 2.4.2 bootloader-interrupt (duration 00:00:33) [common]
912 10:17:13.846386 start: 2.4.3 bootloader-commands (timeout 00:04:27) [common]
913 10:17:13.846860 Setting prompt string to ['=>']
914 10:17:13.847340 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:27)
915 10:17:13.861045 0
916 10:17:13.861887 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
917 10:17:13.862380 Sending with 10 millisecond of delay
919 10:17:14.997106 => setenv autoload no
920 10:17:15.007891 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:26)
921 10:17:15.012874 setenv autoload no
922 10:17:15.013607 Sending with 10 millisecond of delay
924 10:17:16.811329 => setenv initrd_high 0xffffffff
925 10:17:16.822226 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:24)
926 10:17:16.823188 setenv initrd_high 0xffffffff
927 10:17:16.823958 Sending with 10 millisecond of delay
929 10:17:18.441026 => setenv fdt_high 0xffffffff
930 10:17:18.451875 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:23)
931 10:17:18.452826 setenv fdt_high 0xffffffff
932 10:17:18.453596 Sending with 10 millisecond of delay
934 10:17:18.745543 => dhcp
935 10:17:18.756112 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:22)
936 10:17:18.756647 dhcp
937 10:17:18.756906 Speed: 1000, full duplex
938 10:17:18.757144 BOOTP broadcast 1
939 10:17:18.771679 DHCP client bound to address 192.168.6.27 (16 ms)
940 10:17:18.772246 Sending with 10 millisecond of delay
942 10:17:20.450196 => setenv serverip 192.168.6.2
943 10:17:20.460756 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:21)
944 10:17:20.461311 setenv serverip 192.168.6.2
945 10:17:20.461776 Sending with 10 millisecond of delay
947 10:17:24.185314 => tftpboot 0x01080000 974368/tftp-deploy-jlpctpqp/kernel/uImage
948 10:17:24.196128 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:17)
949 10:17:24.196969 tftpboot 0x01080000 974368/tftp-deploy-jlpctpqp/kernel/uImage
950 10:17:24.197423 Speed: 1000, full duplex
951 10:17:24.197839 Using ethernet@ff3f0000 device
952 10:17:24.198845 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
953 10:17:24.204297 Filename '974368/tftp-deploy-jlpctpqp/kernel/uImage'.
954 10:17:24.208260 Load address: 0x1080000
955 10:17:28.477279 Loading: *#################################################
956 10:17:28.477913 TFTP error: trying to overwrite reserved memory...
958 10:17:28.479568 end: 2.4.3 bootloader-commands (duration 00:00:15) [common]
961 10:17:28.481562 end: 2.4 uboot-commands (duration 00:00:47) [common]
963 10:17:28.482984 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'TFTP error: trying to overwrite reserved memory' (12)'
965 10:17:28.484110 end: 2 uboot-action (duration 00:00:47) [common]
967 10:17:28.485626 Cleaning after the job
968 10:17:28.486161 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/974368/tftp-deploy-jlpctpqp/ramdisk
969 10:17:28.501134 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/974368/tftp-deploy-jlpctpqp/kernel
970 10:17:28.504279 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/974368/tftp-deploy-jlpctpqp/dtb
971 10:17:28.505067 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/974368/tftp-deploy-jlpctpqp/modules
972 10:17:28.529144 start: 4.1 power-off (timeout 00:00:30) [common]
973 10:17:28.529857 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
974 10:17:28.566192 >> OK - accepted request
975 10:17:28.568481 Returned 0 in 0 seconds
976 10:17:28.669366 end: 4.1 power-off (duration 00:00:00) [common]
978 10:17:28.670411 start: 4.2 read-feedback (timeout 00:10:00) [common]
979 10:17:28.671082 Listened to connection for namespace 'common' for up to 1s
980 10:17:29.671445 Finalising connection for namespace 'common'
981 10:17:29.672182 Disconnecting from shell: Finalise
982 10:17:29.672702 =>
983 10:17:29.773668 end: 4.2 read-feedback (duration 00:00:01) [common]
984 10:17:29.774223 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/974368
985 10:17:30.092450 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/974368
986 10:17:30.093065 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.