Boot log: meson-sm1-s905d3-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 10:16:06.534495 lava-dispatcher, installed at version: 2024.01
2 10:16:06.535319 start: 0 validate
3 10:16:06.535796 Start time: 2024-11-11 10:16:06.535765+00:00 (UTC)
4 10:16:06.536395 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 10:16:06.536943 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230703.0%2Farm64%2Frootfs.cpio.gz exists
6 10:16:06.572865 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 10:16:06.573439 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241111%2Farm64%2Fdefconfig%2Bkselftest%2Fgcc-12%2Fkernel%2FImage exists
8 10:16:06.602631 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 10:16:06.603249 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241111%2Farm64%2Fdefconfig%2Bkselftest%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-sm1-s905d3-libretech-cc.dtb exists
10 10:16:15.690130 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 10:16:15.690896 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241111%2Farm64%2Fdefconfig%2Bkselftest%2Fgcc-12%2Fmodules.tar.xz exists
12 10:16:18.757781 validate duration: 12.22
14 10:16:18.758671 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 10:16:18.759030 start: 1.1 download-retry (timeout 00:10:00) [common]
16 10:16:18.759363 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 10:16:18.760077 Not decompressing ramdisk as can be used compressed.
18 10:16:18.760534 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230703.0/arm64/rootfs.cpio.gz
19 10:16:18.760821 saving as /var/lib/lava/dispatcher/tmp/974352/tftp-deploy-7ehb0nqp/ramdisk/rootfs.cpio.gz
20 10:16:18.761115 total size: 8181887 (7 MB)
21 10:16:18.808068 progress 0 % (0 MB)
22 10:16:18.813857 progress 5 % (0 MB)
23 10:16:18.819860 progress 10 % (0 MB)
24 10:16:18.826101 progress 15 % (1 MB)
25 10:16:18.831606 progress 20 % (1 MB)
26 10:16:18.837653 progress 25 % (1 MB)
27 10:16:18.843082 progress 30 % (2 MB)
28 10:16:18.849126 progress 35 % (2 MB)
29 10:16:18.854532 progress 40 % (3 MB)
30 10:16:18.862631 progress 45 % (3 MB)
31 10:16:18.868067 progress 50 % (3 MB)
32 10:16:18.873806 progress 55 % (4 MB)
33 10:16:18.879070 progress 60 % (4 MB)
34 10:16:18.884862 progress 65 % (5 MB)
35 10:16:18.890240 progress 70 % (5 MB)
36 10:16:18.896193 progress 75 % (5 MB)
37 10:16:18.901577 progress 80 % (6 MB)
38 10:16:18.908180 progress 85 % (6 MB)
39 10:16:18.913887 progress 90 % (7 MB)
40 10:16:18.919931 progress 95 % (7 MB)
41 10:16:18.924946 progress 100 % (7 MB)
42 10:16:18.925659 7 MB downloaded in 0.16 s (47.43 MB/s)
43 10:16:18.926241 end: 1.1.1 http-download (duration 00:00:00) [common]
45 10:16:18.927178 end: 1.1 download-retry (duration 00:00:00) [common]
46 10:16:18.927502 start: 1.2 download-retry (timeout 00:10:00) [common]
47 10:16:18.927800 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 10:16:18.928332 downloading http://storage.kernelci.org/next/master/next-20241111/arm64/defconfig+kselftest/gcc-12/kernel/Image
49 10:16:18.928661 saving as /var/lib/lava/dispatcher/tmp/974352/tftp-deploy-7ehb0nqp/kernel/Image
50 10:16:18.928910 total size: 66980352 (63 MB)
51 10:16:18.929162 No compression specified
52 10:16:18.979770 progress 0 % (0 MB)
53 10:16:19.020318 progress 5 % (3 MB)
54 10:16:19.061274 progress 10 % (6 MB)
55 10:16:19.102786 progress 15 % (9 MB)
56 10:16:19.143155 progress 20 % (12 MB)
57 10:16:19.183434 progress 25 % (16 MB)
58 10:16:19.225991 progress 30 % (19 MB)
59 10:16:19.267026 progress 35 % (22 MB)
60 10:16:19.307614 progress 40 % (25 MB)
61 10:16:19.349698 progress 45 % (28 MB)
62 10:16:19.392651 progress 50 % (31 MB)
63 10:16:19.432738 progress 55 % (35 MB)
64 10:16:19.474141 progress 60 % (38 MB)
65 10:16:19.513603 progress 65 % (41 MB)
66 10:16:19.552693 progress 70 % (44 MB)
67 10:16:19.592930 progress 75 % (47 MB)
68 10:16:19.633905 progress 80 % (51 MB)
69 10:16:19.675287 progress 85 % (54 MB)
70 10:16:19.717022 progress 90 % (57 MB)
71 10:16:19.756610 progress 95 % (60 MB)
72 10:16:19.795771 progress 100 % (63 MB)
73 10:16:19.796381 63 MB downloaded in 0.87 s (73.64 MB/s)
74 10:16:19.796908 end: 1.2.1 http-download (duration 00:00:01) [common]
76 10:16:19.797780 end: 1.2 download-retry (duration 00:00:01) [common]
77 10:16:19.798076 start: 1.3 download-retry (timeout 00:09:59) [common]
78 10:16:19.798354 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 10:16:19.798855 downloading http://storage.kernelci.org/next/master/next-20241111/arm64/defconfig+kselftest/gcc-12/dtbs/amlogic/meson-sm1-s905d3-libretech-cc.dtb
80 10:16:19.799147 saving as /var/lib/lava/dispatcher/tmp/974352/tftp-deploy-7ehb0nqp/dtb/meson-sm1-s905d3-libretech-cc.dtb
81 10:16:19.799367 total size: 53209 (0 MB)
82 10:16:19.799586 No compression specified
83 10:16:19.843255 progress 61 % (0 MB)
84 10:16:19.844321 progress 100 % (0 MB)
85 10:16:19.845033 0 MB downloaded in 0.05 s (1.11 MB/s)
86 10:16:19.845677 end: 1.3.1 http-download (duration 00:00:00) [common]
88 10:16:19.846824 end: 1.3 download-retry (duration 00:00:00) [common]
89 10:16:19.847206 start: 1.4 download-retry (timeout 00:09:59) [common]
90 10:16:19.847587 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 10:16:19.848309 downloading http://storage.kernelci.org/next/master/next-20241111/arm64/defconfig+kselftest/gcc-12/modules.tar.xz
92 10:16:19.848672 saving as /var/lib/lava/dispatcher/tmp/974352/tftp-deploy-7ehb0nqp/modules/modules.tar
93 10:16:19.848949 total size: 16288464 (15 MB)
94 10:16:19.849255 Using unxz to decompress xz
95 10:16:19.893068 progress 0 % (0 MB)
96 10:16:20.003449 progress 5 % (0 MB)
97 10:16:20.119108 progress 10 % (1 MB)
98 10:16:20.245287 progress 15 % (2 MB)
99 10:16:20.378496 progress 20 % (3 MB)
100 10:16:20.521265 progress 25 % (3 MB)
101 10:16:20.634938 progress 30 % (4 MB)
102 10:16:20.742822 progress 35 % (5 MB)
103 10:16:20.857959 progress 40 % (6 MB)
104 10:16:20.966731 progress 45 % (7 MB)
105 10:16:21.086828 progress 50 % (7 MB)
106 10:16:21.201717 progress 55 % (8 MB)
107 10:16:21.320781 progress 60 % (9 MB)
108 10:16:21.437683 progress 65 % (10 MB)
109 10:16:21.548125 progress 70 % (10 MB)
110 10:16:21.667186 progress 75 % (11 MB)
111 10:16:21.786030 progress 80 % (12 MB)
112 10:16:21.902438 progress 85 % (13 MB)
113 10:16:22.018832 progress 90 % (14 MB)
114 10:16:22.125477 progress 95 % (14 MB)
115 10:16:22.244592 progress 100 % (15 MB)
116 10:16:22.254855 15 MB downloaded in 2.41 s (6.46 MB/s)
117 10:16:22.255484 end: 1.4.1 http-download (duration 00:00:02) [common]
119 10:16:22.256709 end: 1.4 download-retry (duration 00:00:02) [common]
120 10:16:22.257256 start: 1.5 prepare-tftp-overlay (timeout 00:09:57) [common]
121 10:16:22.257775 start: 1.5.1 extract-nfsrootfs (timeout 00:09:57) [common]
122 10:16:22.258263 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 10:16:22.258760 start: 1.5.2 lava-overlay (timeout 00:09:56) [common]
124 10:16:22.259714 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/974352/lava-overlay-fc2q2hwj
125 10:16:22.260601 makedir: /var/lib/lava/dispatcher/tmp/974352/lava-overlay-fc2q2hwj/lava-974352/bin
126 10:16:22.261251 makedir: /var/lib/lava/dispatcher/tmp/974352/lava-overlay-fc2q2hwj/lava-974352/tests
127 10:16:22.261864 makedir: /var/lib/lava/dispatcher/tmp/974352/lava-overlay-fc2q2hwj/lava-974352/results
128 10:16:22.262477 Creating /var/lib/lava/dispatcher/tmp/974352/lava-overlay-fc2q2hwj/lava-974352/bin/lava-add-keys
129 10:16:22.263461 Creating /var/lib/lava/dispatcher/tmp/974352/lava-overlay-fc2q2hwj/lava-974352/bin/lava-add-sources
130 10:16:22.264451 Creating /var/lib/lava/dispatcher/tmp/974352/lava-overlay-fc2q2hwj/lava-974352/bin/lava-background-process-start
131 10:16:22.265418 Creating /var/lib/lava/dispatcher/tmp/974352/lava-overlay-fc2q2hwj/lava-974352/bin/lava-background-process-stop
132 10:16:22.266408 Creating /var/lib/lava/dispatcher/tmp/974352/lava-overlay-fc2q2hwj/lava-974352/bin/lava-common-functions
133 10:16:22.267443 Creating /var/lib/lava/dispatcher/tmp/974352/lava-overlay-fc2q2hwj/lava-974352/bin/lava-echo-ipv4
134 10:16:22.268418 Creating /var/lib/lava/dispatcher/tmp/974352/lava-overlay-fc2q2hwj/lava-974352/bin/lava-install-packages
135 10:16:22.269332 Creating /var/lib/lava/dispatcher/tmp/974352/lava-overlay-fc2q2hwj/lava-974352/bin/lava-installed-packages
136 10:16:22.270240 Creating /var/lib/lava/dispatcher/tmp/974352/lava-overlay-fc2q2hwj/lava-974352/bin/lava-os-build
137 10:16:22.271170 Creating /var/lib/lava/dispatcher/tmp/974352/lava-overlay-fc2q2hwj/lava-974352/bin/lava-probe-channel
138 10:16:22.272115 Creating /var/lib/lava/dispatcher/tmp/974352/lava-overlay-fc2q2hwj/lava-974352/bin/lava-probe-ip
139 10:16:22.273057 Creating /var/lib/lava/dispatcher/tmp/974352/lava-overlay-fc2q2hwj/lava-974352/bin/lava-target-ip
140 10:16:22.273950 Creating /var/lib/lava/dispatcher/tmp/974352/lava-overlay-fc2q2hwj/lava-974352/bin/lava-target-mac
141 10:16:22.274865 Creating /var/lib/lava/dispatcher/tmp/974352/lava-overlay-fc2q2hwj/lava-974352/bin/lava-target-storage
142 10:16:22.275815 Creating /var/lib/lava/dispatcher/tmp/974352/lava-overlay-fc2q2hwj/lava-974352/bin/lava-test-case
143 10:16:22.276805 Creating /var/lib/lava/dispatcher/tmp/974352/lava-overlay-fc2q2hwj/lava-974352/bin/lava-test-event
144 10:16:22.277698 Creating /var/lib/lava/dispatcher/tmp/974352/lava-overlay-fc2q2hwj/lava-974352/bin/lava-test-feedback
145 10:16:22.278734 Creating /var/lib/lava/dispatcher/tmp/974352/lava-overlay-fc2q2hwj/lava-974352/bin/lava-test-raise
146 10:16:22.279663 Creating /var/lib/lava/dispatcher/tmp/974352/lava-overlay-fc2q2hwj/lava-974352/bin/lava-test-reference
147 10:16:22.280640 Creating /var/lib/lava/dispatcher/tmp/974352/lava-overlay-fc2q2hwj/lava-974352/bin/lava-test-runner
148 10:16:22.281535 Creating /var/lib/lava/dispatcher/tmp/974352/lava-overlay-fc2q2hwj/lava-974352/bin/lava-test-set
149 10:16:22.282439 Creating /var/lib/lava/dispatcher/tmp/974352/lava-overlay-fc2q2hwj/lava-974352/bin/lava-test-shell
150 10:16:22.283337 Updating /var/lib/lava/dispatcher/tmp/974352/lava-overlay-fc2q2hwj/lava-974352/bin/lava-install-packages (oe)
151 10:16:22.284434 Updating /var/lib/lava/dispatcher/tmp/974352/lava-overlay-fc2q2hwj/lava-974352/bin/lava-installed-packages (oe)
152 10:16:22.285291 Creating /var/lib/lava/dispatcher/tmp/974352/lava-overlay-fc2q2hwj/lava-974352/environment
153 10:16:22.286010 LAVA metadata
154 10:16:22.286490 - LAVA_JOB_ID=974352
155 10:16:22.286910 - LAVA_DISPATCHER_IP=192.168.6.2
156 10:16:22.287579 start: 1.5.2.1 ssh-authorize (timeout 00:09:56) [common]
157 10:16:22.289572 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 10:16:22.290173 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:56) [common]
159 10:16:22.290582 skipped lava-vland-overlay
160 10:16:22.291063 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 10:16:22.291563 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:56) [common]
162 10:16:22.292128 skipped lava-multinode-overlay
163 10:16:22.292418 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 10:16:22.292682 start: 1.5.2.4 test-definition (timeout 00:09:56) [common]
165 10:16:22.292947 Loading test definitions
166 10:16:22.293251 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:56) [common]
167 10:16:22.293480 Using /lava-974352 at stage 0
168 10:16:22.294715 uuid=974352_1.5.2.4.1 testdef=None
169 10:16:22.295027 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 10:16:22.295292 start: 1.5.2.4.2 test-overlay (timeout 00:09:56) [common]
171 10:16:22.297240 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 10:16:22.298059 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:56) [common]
174 10:16:22.300455 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 10:16:22.301317 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:56) [common]
177 10:16:22.303587 runner path: /var/lib/lava/dispatcher/tmp/974352/lava-overlay-fc2q2hwj/lava-974352/0/tests/0_dmesg test_uuid 974352_1.5.2.4.1
178 10:16:22.304242 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 10:16:22.305034 Creating lava-test-runner.conf files
181 10:16:22.305239 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/974352/lava-overlay-fc2q2hwj/lava-974352/0 for stage 0
182 10:16:22.305667 - 0_dmesg
183 10:16:22.306099 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 10:16:22.306405 start: 1.5.2.5 compress-overlay (timeout 00:09:56) [common]
185 10:16:22.331014 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 10:16:22.331465 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:56) [common]
187 10:16:22.331731 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 10:16:22.332021 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 10:16:22.332298 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:56) [common]
190 10:16:23.357020 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
191 10:16:23.357519 start: 1.5.4 extract-modules (timeout 00:09:55) [common]
192 10:16:23.357794 extracting modules file /var/lib/lava/dispatcher/tmp/974352/tftp-deploy-7ehb0nqp/modules/modules.tar to /var/lib/lava/dispatcher/tmp/974352/extract-overlay-ramdisk-ag9ehwmn/ramdisk
193 10:16:24.910560 end: 1.5.4 extract-modules (duration 00:00:02) [common]
194 10:16:24.911078 start: 1.5.5 apply-overlay-tftp (timeout 00:09:54) [common]
195 10:16:24.911359 [common] Applying overlay /var/lib/lava/dispatcher/tmp/974352/compress-overlay-lnxv2a5m/overlay-1.5.2.5.tar.gz to ramdisk
196 10:16:24.911572 [common] Applying overlay /var/lib/lava/dispatcher/tmp/974352/compress-overlay-lnxv2a5m/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/974352/extract-overlay-ramdisk-ag9ehwmn/ramdisk
197 10:16:24.944949 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 10:16:24.945405 start: 1.5.6 prepare-kernel (timeout 00:09:54) [common]
199 10:16:24.945670 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:54) [common]
200 10:16:24.945894 Converting downloaded kernel to a uImage
201 10:16:24.946202 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/974352/tftp-deploy-7ehb0nqp/kernel/Image /var/lib/lava/dispatcher/tmp/974352/tftp-deploy-7ehb0nqp/kernel/uImage
202 10:16:25.770308 output: Image Name:
203 10:16:25.770729 output: Created: Mon Nov 11 10:16:24 2024
204 10:16:25.770951 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 10:16:25.771162 output: Data Size: 66980352 Bytes = 65410.50 KiB = 63.88 MiB
206 10:16:25.771367 output: Load Address: 01080000
207 10:16:25.771567 output: Entry Point: 01080000
208 10:16:25.771766 output:
209 10:16:25.772133 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:01) [common]
210 10:16:25.772420 end: 1.5.6 prepare-kernel (duration 00:00:01) [common]
211 10:16:25.772701 start: 1.5.7 configure-preseed-file (timeout 00:09:53) [common]
212 10:16:25.772963 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 10:16:25.773228 start: 1.5.8 compress-ramdisk (timeout 00:09:53) [common]
214 10:16:25.773494 Building ramdisk /var/lib/lava/dispatcher/tmp/974352/extract-overlay-ramdisk-ag9ehwmn/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/974352/extract-overlay-ramdisk-ag9ehwmn/ramdisk
215 10:16:29.785676 >> 258309 blocks
216 10:16:40.857350 Adding RAMdisk u-boot header.
217 10:16:40.857806 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/974352/extract-overlay-ramdisk-ag9ehwmn/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/974352/extract-overlay-ramdisk-ag9ehwmn/ramdisk.cpio.gz.uboot
218 10:16:41.225783 output: Image Name:
219 10:16:41.226213 output: Created: Mon Nov 11 10:16:40 2024
220 10:16:41.226420 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 10:16:41.226621 output: Data Size: 33951380 Bytes = 33155.64 KiB = 32.38 MiB
222 10:16:41.226818 output: Load Address: 00000000
223 10:16:41.227013 output: Entry Point: 00000000
224 10:16:41.227206 output:
225 10:16:41.227858 rename /var/lib/lava/dispatcher/tmp/974352/extract-overlay-ramdisk-ag9ehwmn/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/974352/tftp-deploy-7ehb0nqp/ramdisk/ramdisk.cpio.gz.uboot
226 10:16:41.228551 end: 1.5.8 compress-ramdisk (duration 00:00:15) [common]
227 10:16:41.229085 end: 1.5 prepare-tftp-overlay (duration 00:00:19) [common]
228 10:16:41.229599 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:38) [common]
229 10:16:41.230045 No LXC device requested
230 10:16:41.230537 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 10:16:41.231037 start: 1.7 deploy-device-env (timeout 00:09:38) [common]
232 10:16:41.231524 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 10:16:41.231920 Checking files for TFTP limit of 4294967296 bytes.
234 10:16:41.234778 end: 1 tftp-deploy (duration 00:00:22) [common]
235 10:16:41.235400 start: 2 uboot-action (timeout 00:05:00) [common]
236 10:16:41.235920 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 10:16:41.236457 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 10:16:41.236952 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 10:16:41.237480 Using kernel file from prepare-kernel: 974352/tftp-deploy-7ehb0nqp/kernel/uImage
240 10:16:41.238111 substitutions:
241 10:16:41.238516 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 10:16:41.238913 - {DTB_ADDR}: 0x01070000
243 10:16:41.239305 - {DTB}: 974352/tftp-deploy-7ehb0nqp/dtb/meson-sm1-s905d3-libretech-cc.dtb
244 10:16:41.239695 - {INITRD}: 974352/tftp-deploy-7ehb0nqp/ramdisk/ramdisk.cpio.gz.uboot
245 10:16:41.240118 - {KERNEL_ADDR}: 0x01080000
246 10:16:41.240512 - {KERNEL}: 974352/tftp-deploy-7ehb0nqp/kernel/uImage
247 10:16:41.240901 - {LAVA_MAC}: None
248 10:16:41.241328 - {PRESEED_CONFIG}: None
249 10:16:41.241716 - {PRESEED_LOCAL}: None
250 10:16:41.242099 - {RAMDISK_ADDR}: 0x08000000
251 10:16:41.242479 - {RAMDISK}: 974352/tftp-deploy-7ehb0nqp/ramdisk/ramdisk.cpio.gz.uboot
252 10:16:41.242866 - {ROOT_PART}: None
253 10:16:41.243248 - {ROOT}: None
254 10:16:41.243632 - {SERVER_IP}: 192.168.6.2
255 10:16:41.244044 - {TEE_ADDR}: 0x83000000
256 10:16:41.244432 - {TEE}: None
257 10:16:41.244815 Parsed boot commands:
258 10:16:41.245190 - setenv autoload no
259 10:16:41.245570 - setenv initrd_high 0xffffffff
260 10:16:41.245949 - setenv fdt_high 0xffffffff
261 10:16:41.246326 - dhcp
262 10:16:41.246703 - setenv serverip 192.168.6.2
263 10:16:41.247081 - tftpboot 0x01080000 974352/tftp-deploy-7ehb0nqp/kernel/uImage
264 10:16:41.247461 - tftpboot 0x08000000 974352/tftp-deploy-7ehb0nqp/ramdisk/ramdisk.cpio.gz.uboot
265 10:16:41.247838 - tftpboot 0x01070000 974352/tftp-deploy-7ehb0nqp/dtb/meson-sm1-s905d3-libretech-cc.dtb
266 10:16:41.248243 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 10:16:41.248631 - bootm 0x01080000 0x08000000 0x01070000
268 10:16:41.249132 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 10:16:41.250598 start: 2.3 connect-device (timeout 00:05:00) [common]
271 10:16:41.251032 [common] connect-device Connecting to device using 'telnet conserv1 3008'
272 10:16:41.264927 Setting prompt string to ['lava-test: # ']
273 10:16:41.266459 end: 2.3 connect-device (duration 00:00:00) [common]
274 10:16:41.267049 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 10:16:41.267606 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 10:16:41.268305 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 10:16:41.269527 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=solitude-01'
278 10:16:41.304710 >> OK - accepted request
279 10:16:41.306728 Returned 0 in 0 seconds
280 10:16:41.407902 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
282 10:16:41.409706 end: 2.4.1 reset-device (duration 00:00:00) [common]
283 10:16:41.410289 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
284 10:16:41.410799 Setting prompt string to ['Hit any key to stop autoboot']
285 10:16:41.411253 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 10:16:41.412930 Trying 192.168.56.21...
287 10:16:41.413433 Connected to conserv1.
288 10:16:41.413851 Escape character is '^]'.
289 10:16:41.414268
290 10:16:41.414686 ser2net port telnet,3008 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.3.3:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
291 10:16:41.415107
292 10:16:50.379905 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
293 10:16:50.380730 bl2_stage_init 0x01
294 10:16:50.381162 bl2_stage_init 0x81
295 10:16:50.385429 hw id: 0x0000 - pwm id 0x01
296 10:16:50.385879 bl2_stage_init 0xc1
297 10:16:50.386283 bl2_stage_init 0x02
298 10:16:50.386675
299 10:16:50.391090 L0:00000000
300 10:16:50.391522 L1:00000703
301 10:16:50.391913 L2:00008067
302 10:16:50.392339 L3:15000000
303 10:16:50.392728 S1:00000000
304 10:16:50.396593 B2:20282000
305 10:16:50.397019 B1:a0f83180
306 10:16:50.397407
307 10:16:50.397795 TE: 69813
308 10:16:50.398182
309 10:16:50.402116 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
310 10:16:50.402538
311 10:16:50.407885 Board ID = 1
312 10:16:50.408423 Set cpu clk to 24M
313 10:16:50.408814 Set clk81 to 24M
314 10:16:50.413376 Use GP1_pll as DSU clk.
315 10:16:50.413834 DSU clk: 1200 Mhz
316 10:16:50.414227 CPU clk: 1200 MHz
317 10:16:50.414616 Set clk81 to 166.6M
318 10:16:50.424542 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
319 10:16:50.425072 board id: 1
320 10:16:50.430902 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
321 10:16:50.441574 fw parse done
322 10:16:50.447530 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
323 10:16:50.490274 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
324 10:16:50.501121 PIEI prepare done
325 10:16:50.501578 fastboot data load
326 10:16:50.501971 fastboot data verify
327 10:16:50.506721 verify result: 266
328 10:16:50.512350 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
329 10:16:50.512775 LPDDR4 probe
330 10:16:50.513162 ddr clk to 1584MHz
331 10:16:50.520317 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
332 10:16:50.557641
333 10:16:50.558137 dmc_version 0001
334 10:16:50.564290 Check phy result
335 10:16:50.570103 INFO : End of CA training
336 10:16:50.570543 INFO : End of initialization
337 10:16:50.575732 INFO : Training has run successfully!
338 10:16:50.576200 Check phy result
339 10:16:50.581369 INFO : End of initialization
340 10:16:50.581790 INFO : End of read enable training
341 10:16:50.586921 INFO : End of fine write leveling
342 10:16:50.592527 INFO : End of Write leveling coarse delay
343 10:16:50.592946 INFO : Training has run successfully!
344 10:16:50.593332 Check phy result
345 10:16:50.598121 INFO : End of initialization
346 10:16:50.598534 INFO : End of read dq deskew training
347 10:16:50.603693 INFO : End of MPR read delay center optimization
348 10:16:50.609369 INFO : End of write delay center optimization
349 10:16:50.614870 INFO : End of read delay center optimization
350 10:16:50.615291 INFO : End of max read latency training
351 10:16:50.620565 INFO : Training has run successfully!
352 10:16:50.621012 1D training succeed
353 10:16:50.629695 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
354 10:16:50.677308 Check phy result
355 10:16:50.677754 INFO : End of initialization
356 10:16:50.699674 INFO : End of 2D read delay Voltage center optimization
357 10:16:50.718947 INFO : End of 2D read delay Voltage center optimization
358 10:16:50.770856 INFO : End of 2D write delay Voltage center optimization
359 10:16:50.820030 INFO : End of 2D write delay Voltage center optimization
360 10:16:50.825556 INFO : Training has run successfully!
361 10:16:50.825998
362 10:16:50.826393 channel==0
363 10:16:50.831160 RxClkDly_Margin_A0==88 ps 9
364 10:16:50.831574 TxDqDly_Margin_A0==98 ps 10
365 10:16:50.836662 RxClkDly_Margin_A1==88 ps 9
366 10:16:50.837101 TxDqDly_Margin_A1==98 ps 10
367 10:16:50.837491 TrainedVREFDQ_A0==74
368 10:16:50.842375 TrainedVREFDQ_A1==74
369 10:16:50.842792 VrefDac_Margin_A0==24
370 10:16:50.843173 DeviceVref_Margin_A0==40
371 10:16:50.848036 VrefDac_Margin_A1==23
372 10:16:50.848552 DeviceVref_Margin_A1==40
373 10:16:50.848972
374 10:16:50.849377
375 10:16:50.853627 channel==1
376 10:16:50.854141 RxClkDly_Margin_A0==78 ps 8
377 10:16:50.854538 TxDqDly_Margin_A0==78 ps 8
378 10:16:50.859167 RxClkDly_Margin_A1==88 ps 9
379 10:16:50.859594 TxDqDly_Margin_A1==88 ps 9
380 10:16:50.864786 TrainedVREFDQ_A0==77
381 10:16:50.865227 TrainedVREFDQ_A1==75
382 10:16:50.865617 VrefDac_Margin_A0==22
383 10:16:50.870386 DeviceVref_Margin_A0==37
384 10:16:50.870804 VrefDac_Margin_A1==23
385 10:16:50.875954 DeviceVref_Margin_A1==38
386 10:16:50.876402
387 10:16:50.876796 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
388 10:16:50.877182
389 10:16:50.909580 soc_vref_reg_value 0x 0000001a 00000019 00000019 00000017 00000019 00000015 00000018 00000016 00000018 00000017 00000017 00000018 00000017 00000018 00000018 00000019 00000019 00000018 00000019 00000016 00000018 00000015 00000016 00000017 00000018 00000019 00000018 00000018 0000001d 00000018 00000016 00000017 dram_vref_reg_value 0x 00000061
390 10:16:50.910164 2D training succeed
391 10:16:50.915161 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
392 10:16:50.920688 auto size-- 65535DDR cs0 size: 2048MB
393 10:16:50.921144 DDR cs1 size: 2048MB
394 10:16:50.926270 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
395 10:16:50.926716 cs0 DataBus test pass
396 10:16:50.931876 cs1 DataBus test pass
397 10:16:50.932370 cs0 AddrBus test pass
398 10:16:50.932757 cs1 AddrBus test pass
399 10:16:50.933137
400 10:16:50.937464 100bdlr_step_size ps== 478
401 10:16:50.937901 result report
402 10:16:50.943114 boot times 0Enable ddr reg access
403 10:16:50.948288 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
404 10:16:50.962225 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
405 10:16:51.617014 bl2z: ptr: 05129330, size: 00001e40
406 10:16:51.624077 0.0;M3 CHK:0;cm4_sp_mode 0
407 10:16:51.624529 MVN_1=0x00000000
408 10:16:51.624918 MVN_2=0x00000000
409 10:16:51.635631 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
410 10:16:51.636085 OPS=0x04
411 10:16:51.636478 ring efuse init
412 10:16:51.638548 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
413 10:16:51.644656 [0.017319 Inits done]
414 10:16:51.645104 secure task start!
415 10:16:51.645497 high task start!
416 10:16:51.645881 low task start!
417 10:16:51.649030 run into bl31
418 10:16:51.657592 NOTICE: BL31: v1.3(release):4fc40b1
419 10:16:51.665447 NOTICE: BL31: Built : 15:57:33, May 22 2019
420 10:16:51.665887 NOTICE: BL31: G12A normal boot!
421 10:16:51.680967 NOTICE: BL31: BL33 decompress pass
422 10:16:51.686736 ERROR: Error initializing runtime service opteed_fast
423 10:16:54.429477 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0; SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
424 10:16:54.429918 bl2_stage_init 0x01
425 10:16:54.430128 bl2_stage_init 0x81
426 10:16:54.434985 hw id: 0x0000 - pwm id 0x01
427 10:16:54.435355 bl2_stage_init 0xc1
428 10:16:54.440580 bl2_stage_init 0x02
429 10:16:54.440938
430 10:16:54.441256 L0:00000000
431 10:16:54.441558 L1:00000703
432 10:16:54.441780 L2:00008067
433 10:16:54.441978 L3:15000000
434 10:16:54.446183 S1:00000000
435 10:16:54.446554 B2:20282000
436 10:16:54.446872 B1:a0f83180
437 10:16:54.447169
438 10:16:54.447475 TE: 68909
439 10:16:54.447771
440 10:16:54.451776 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
441 10:16:54.452059
442 10:16:54.457372 Board ID = 1
443 10:16:54.457637 Set cpu clk to 24M
444 10:16:54.457843 Set clk81 to 24M
445 10:16:54.462974 Use GP1_pll as DSU clk.
446 10:16:54.463335 DSU clk: 1200 Mhz
447 10:16:54.463654 CPU clk: 1200 MHz
448 10:16:54.468596 Set clk81 to 166.6M
449 10:16:54.474163 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
450 10:16:54.474546 board id: 1
451 10:16:54.481367 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
452 10:16:54.492311 fw parse done
453 10:16:54.498270 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
454 10:16:54.542021 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
455 10:16:54.552713 PIEI prepare done
456 10:16:54.553243 fastboot data load
457 10:16:54.553506 fastboot data verify
458 10:16:54.558201 verify result: 266
459 10:16:54.563777 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
460 10:16:54.564156 LPDDR4 probe
461 10:16:54.564371 ddr clk to 1584MHz
462 10:16:54.571732 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
463 10:16:54.609612
464 10:16:54.610094 dmc_version 0001
465 10:16:54.616435 Check phy result
466 10:16:54.622396 INFO : End of CA training
467 10:16:54.622666 INFO : End of initialization
468 10:16:54.628015 INFO : Training has run successfully!
469 10:16:54.628401 Check phy result
470 10:16:54.633648 INFO : End of initialization
471 10:16:54.633933 INFO : End of read enable training
472 10:16:54.639227 INFO : End of fine write leveling
473 10:16:54.644831 INFO : End of Write leveling coarse delay
474 10:16:54.645251 INFO : Training has run successfully!
475 10:16:54.645491 Check phy result
476 10:16:54.650444 INFO : End of initialization
477 10:16:54.650736 INFO : End of read dq deskew training
478 10:16:54.656041 INFO : End of MPR read delay center optimization
479 10:16:54.661651 INFO : End of write delay center optimization
480 10:16:54.667231 INFO : End of read delay center optimization
481 10:16:54.667526 INFO : End of max read latency training
482 10:16:54.672830 INFO : Training has run successfully!
483 10:16:54.673145 1D training succeed
484 10:16:54.682015 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
485 10:16:54.729426 Check phy result
486 10:16:54.729798 INFO : End of initialization
487 10:16:54.757815 INFO : End of 2D read delay Voltage center optimization
488 10:16:54.781908 INFO : End of 2D read delay Voltage center optimization
489 10:16:54.838623 INFO : End of 2D write delay Voltage center optimization
490 10:16:54.892640 INFO : End of 2D write delay Voltage center optimization
491 10:16:54.898146 INFO : Training has run successfully!
492 10:16:54.898448
493 10:16:54.898656 channel==0
494 10:16:54.903730 RxClkDly_Margin_A0==69 ps 7
495 10:16:54.904024 TxDqDly_Margin_A0==88 ps 9
496 10:16:54.909321 RxClkDly_Margin_A1==88 ps 9
497 10:16:54.909610 TxDqDly_Margin_A1==98 ps 10
498 10:16:54.909822 TrainedVREFDQ_A0==74
499 10:16:54.914932 TrainedVREFDQ_A1==74
500 10:16:54.915243 VrefDac_Margin_A0==24
501 10:16:54.915454 DeviceVref_Margin_A0==40
502 10:16:54.920542 VrefDac_Margin_A1==23
503 10:16:54.920839 DeviceVref_Margin_A1==40
504 10:16:54.921054
505 10:16:54.921260
506 10:16:54.921457 channel==1
507 10:16:54.926102 RxClkDly_Margin_A0==88 ps 9
508 10:16:54.926387 TxDqDly_Margin_A0==98 ps 10
509 10:16:54.931723 RxClkDly_Margin_A1==78 ps 8
510 10:16:54.932042 TxDqDly_Margin_A1==98 ps 10
511 10:16:54.937344 TrainedVREFDQ_A0==78
512 10:16:54.937692 TrainedVREFDQ_A1==77
513 10:16:54.937909 VrefDac_Margin_A0==23
514 10:16:54.942965 DeviceVref_Margin_A0==36
515 10:16:54.943265 VrefDac_Margin_A1==22
516 10:16:54.948541 DeviceVref_Margin_A1==37
517 10:16:54.948828
518 10:16:54.949040 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
519 10:16:54.949244
520 10:16:54.982144 soc_vref_reg_value 0x 00000019 00000019 00000019 00000017 00000019 00000016 00000019 00000016 00000017 00000018 00000017 00000018 00000018 00000018 00000018 00000019 00000018 00000017 00000019 00000015 00000017 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001b 00000017 00000016 00000017 dram_vref_reg_value 0x 00000061
521 10:16:54.982544 2D training succeed
522 10:16:54.987747 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
523 10:16:54.993323 auto size-- 65535DDR cs0 size: 2048MB
524 10:16:54.993600 DDR cs1 size: 2048MB
525 10:16:54.998935 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
526 10:16:54.999217 cs0 DataBus test pass
527 10:16:55.004532 cs1 DataBus test pass
528 10:16:55.004833 cs0 AddrBus test pass
529 10:16:55.005043 cs1 AddrBus test pass
530 10:16:55.005247
531 10:16:55.010126 100bdlr_step_size ps== 478
532 10:16:55.010408 result report
533 10:16:55.015806 boot times 0Enable ddr reg access
534 10:16:55.021008 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
535 10:16:55.034848 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
536 10:16:55.695540 bl2z: ptr: 05129330, size: 00001e40
537 10:16:55.704473 0.0;M3 CHK:0;cm4_sp_mode 0
538 10:16:55.704774 MVN_1=0x00000000
539 10:16:55.704979 MVN_2=0x00000000
540 10:16:55.715972 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
541 10:16:55.716423 OPS=0x04
542 10:16:55.716753 ring efuse init
543 10:16:55.721576 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
544 10:16:55.721854 [0.017354 Inits done]
545 10:16:55.722074 secure task start!
546 10:16:55.729406 high task start!
547 10:16:55.729791 low task start!
548 10:16:55.730105 run into bl31
549 10:16:55.738030 NOTICE: BL31: v1.3(release):4fc40b1
550 10:16:55.745845 NOTICE: BL31: Built : 15:57:33, May 22 2019
551 10:16:55.746118 NOTICE: BL31: G12A normal boot!
552 10:16:55.761505 NOTICE: BL31: BL33 decompress pass
553 10:16:55.767088 ERROR: Error initializing runtime service opteed_fast
554 10:16:57.130221 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
555 10:16:57.130647 bl2_stage_init 0x01
556 10:16:57.130863 bl2_stage_init 0x81
557 10:16:57.135767 hw id: 0x0000 - pwm id 0x01
558 10:16:57.136104 bl2_stage_init 0xc1
559 10:16:57.141359 bl2_stage_init 0x02
560 10:16:57.141673
561 10:16:57.141915 L0:00000000
562 10:16:57.142156 L1:00000703
563 10:16:57.142389 L2:00008067
564 10:16:57.142623 L3:15000000
565 10:16:57.146975 S1:00000000
566 10:16:57.147271 B2:20282000
567 10:16:57.147516 B1:a0f83180
568 10:16:57.147749
569 10:16:57.148012 TE: 70836
570 10:16:57.148265
571 10:16:57.152560 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
572 10:16:57.152849
573 10:16:57.158166 Board ID = 1
574 10:16:57.158466 Set cpu clk to 24M
575 10:16:57.158710 Set clk81 to 24M
576 10:16:57.163779 Use GP1_pll as DSU clk.
577 10:16:57.164259 DSU clk: 1200 Mhz
578 10:16:57.164797 CPU clk: 1200 MHz
579 10:16:57.169380 Set clk81 to 166.6M
580 10:16:57.174998 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
581 10:16:57.175476 board id: 1
582 10:16:57.182206 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
583 10:16:57.193109 fw parse done
584 10:16:57.199076 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
585 10:16:57.242209 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
586 10:16:57.253355 PIEI prepare done
587 10:16:57.253846 fastboot data load
588 10:16:57.254289 fastboot data verify
589 10:16:57.259038 verify result: 266
590 10:16:57.264530 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
591 10:16:57.265013 LPDDR4 probe
592 10:16:57.265450 ddr clk to 1584MHz
593 10:16:57.272508 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
594 10:16:57.310293
595 10:16:57.310896 dmc_version 0001
596 10:16:57.317271 Check phy result
597 10:16:57.323322 INFO : End of CA training
598 10:16:57.323891 INFO : End of initialization
599 10:16:57.328871 INFO : Training has run successfully!
600 10:16:57.329382 Check phy result
601 10:16:57.334468 INFO : End of initialization
602 10:16:57.334981 INFO : End of read enable training
603 10:16:57.340088 INFO : End of fine write leveling
604 10:16:57.345681 INFO : End of Write leveling coarse delay
605 10:16:57.346183 INFO : Training has run successfully!
606 10:16:57.346645 Check phy result
607 10:16:57.351288 INFO : End of initialization
608 10:16:57.351783 INFO : End of read dq deskew training
609 10:16:57.356860 INFO : End of MPR read delay center optimization
610 10:16:57.362435 INFO : End of write delay center optimization
611 10:16:57.368092 INFO : End of read delay center optimization
612 10:16:57.368601 INFO : End of max read latency training
613 10:16:57.373708 INFO : Training has run successfully!
614 10:16:57.374212 1D training succeed
615 10:16:57.382865 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
616 10:16:57.431402 Check phy result
617 10:16:57.432101 INFO : End of initialization
618 10:16:57.458552 INFO : End of 2D read delay Voltage center optimization
619 10:16:57.482727 INFO : End of 2D read delay Voltage center optimization
620 10:16:57.539562 INFO : End of 2D write delay Voltage center optimization
621 10:16:57.593573 INFO : End of 2D write delay Voltage center optimization
622 10:16:57.599062 INFO : Training has run successfully!
623 10:16:57.599554
624 10:16:57.600045 channel==0
625 10:16:57.604572 RxClkDly_Margin_A0==78 ps 8
626 10:16:57.605064 TxDqDly_Margin_A0==88 ps 9
627 10:16:57.610228 RxClkDly_Margin_A1==88 ps 9
628 10:16:57.610741 TxDqDly_Margin_A1==98 ps 10
629 10:16:57.611197 TrainedVREFDQ_A0==74
630 10:16:57.615833 TrainedVREFDQ_A1==74
631 10:16:57.616366 VrefDac_Margin_A0==24
632 10:16:57.616820 DeviceVref_Margin_A0==40
633 10:16:57.621371 VrefDac_Margin_A1==23
634 10:16:57.621866 DeviceVref_Margin_A1==40
635 10:16:57.622314
636 10:16:57.622755
637 10:16:57.623192 channel==1
638 10:16:57.627079 RxClkDly_Margin_A0==88 ps 9
639 10:16:57.627573 TxDqDly_Margin_A0==98 ps 10
640 10:16:57.632587 RxClkDly_Margin_A1==88 ps 9
641 10:16:57.633084 TxDqDly_Margin_A1==88 ps 9
642 10:16:57.638172 TrainedVREFDQ_A0==78
643 10:16:57.638663 TrainedVREFDQ_A1==77
644 10:16:57.639112 VrefDac_Margin_A0==23
645 10:16:57.643834 DeviceVref_Margin_A0==36
646 10:16:57.644390 VrefDac_Margin_A1==22
647 10:16:57.649379 DeviceVref_Margin_A1==37
648 10:16:57.649878
649 10:16:57.650330 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
650 10:16:57.650775
651 10:16:57.683074 soc_vref_reg_value 0x 0000001a 00000019 00000019 00000017 00000019 00000016 00000018 00000016 00000017 00000017 00000018 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000018 00000015 00000018 00000015 00000015 00000017 00000018 00000019 00000018 00000019 0000001c 00000018 00000016 00000017 dram_vref_reg_value 0x 00000061
652 10:16:57.683621 2D training succeed
653 10:16:57.688579 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
654 10:16:57.694172 auto size-- 65535DDR cs0 size: 2048MB
655 10:16:57.694672 DDR cs1 size: 2048MB
656 10:16:57.699864 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
657 10:16:57.700394 cs0 DataBus test pass
658 10:16:57.705391 cs1 DataBus test pass
659 10:16:57.705887 cs0 AddrBus test pass
660 10:16:57.706338 cs1 AddrBus test pass
661 10:16:57.706778
662 10:16:57.711095 100bdlr_step_size ps== 471
663 10:16:57.711592 result report
664 10:16:57.716584 boot times 0Enable ddr reg access
665 10:16:57.721760 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
666 10:16:57.735615 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
667 10:16:58.394975 bl2z: ptr: 05129330, size: 00001e40
668 10:16:58.403647 0.0;M3 CHK:0;cm4_sp_mode 0
669 10:16:58.404240 MVN_1=0x00000000
670 10:16:58.404709 MVN_2=0x00000000
671 10:16:58.415299 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
672 10:16:58.415975 OPS=0x04
673 10:16:58.416535 ring efuse init
674 10:16:58.420781 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
675 10:16:58.421309 [0.017354 Inits done]
676 10:16:58.421764 secure task start!
677 10:16:58.428231 high task start!
678 10:16:58.428742 low task start!
679 10:16:58.429197 run into bl31
680 10:16:58.436803 NOTICE: BL31: v1.3(release):4fc40b1
681 10:16:58.444606 NOTICE: BL31: Built : 15:57:33, May 22 2019
682 10:16:58.445117 NOTICE: BL31: G12A normal boot!
683 10:16:58.460251 NOTICE: BL31: BL33 decompress pass
684 10:16:58.465944 ERROR: Error initializing runtime service opteed_fast
685 10:16:59.261520
686 10:16:59.261966
687 10:16:59.266714 U-Boot 2024.01-rc4+ (Dec 14 2023 - 02:26:00 -0500) Libre Computer AML-S905D3-CC
688 10:16:59.267172
689 10:16:59.270335 Model: Libre Computer AML-S905D3-CC Solitude
690 10:16:59.417449 SoC: Amlogic Meson SM1 (S905D3) Revision 2b:c (4:2)
691 10:16:59.432681 DRAM: 2 GiB (effective 3.8 GiB)
692 10:16:59.533538 Core: 406 devices, 33 uclasses, devicetree: separate
693 10:16:59.539587 WDT: Not starting watchdog@f0d0
694 10:16:59.564549 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
695 10:16:59.576874 Loading Environment from FAT... Card did not respond to voltage select! : -110
696 10:16:59.581844 ** Bad device specification mmc 0 **
697 10:16:59.591870 Card did not respond to voltage select! : -110
698 10:16:59.599594 ** Bad device specification mmc 0 **
699 10:16:59.599911 Couldn't find partition mmc 0
700 10:16:59.607821 Card did not respond to voltage select! : -110
701 10:16:59.613379 ** Bad device specification mmc 0 **
702 10:16:59.613880 Couldn't find partition mmc 0
703 10:16:59.618452 Error: could not access storage.
704 10:16:59.916022 Net: eth0: ethernet@ff3f0000
705 10:16:59.916567 starting USB...
706 10:17:00.160707 Bus usb@ff500000: Register 3000140 NbrPorts 3
707 10:17:00.161280 Starting the controller
708 10:17:00.167574 USB XHCI 1.10
709 10:17:01.721599 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
710 10:17:01.729982 scanning usb for storage devices... 0 Storage Device(s) found
712 10:17:01.781251 Hit any key to stop autoboot: 1
713 10:17:01.782054 end: 2.4.2 bootloader-interrupt (duration 00:00:20) [common]
714 10:17:01.782411 start: 2.4.3 bootloader-commands (timeout 00:04:39) [common]
715 10:17:01.782674 Setting prompt string to ['=>']
716 10:17:01.782964 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:39)
717 10:17:01.795966 0
718 10:17:01.796717 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
720 10:17:01.897557 => setenv autoload no
721 10:17:01.898564 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:39)
722 10:17:01.902952 setenv autoload no
724 10:17:02.004127 => setenv initrd_high 0xffffffff
725 10:17:02.004851 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:39)
726 10:17:02.009356 setenv initrd_high 0xffffffff
728 10:17:02.110556 => setenv fdt_high 0xffffffff
729 10:17:02.111334 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:39)
730 10:17:02.115977 setenv fdt_high 0xffffffff
732 10:17:02.217575 => dhcp
733 10:17:02.219396 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:39)
734 10:17:02.222073 dhcp
735 10:17:03.179412 ethernet@ff3f0000 Waiting for PHY auto negotiation to complete.. done
736 10:17:03.179850 Speed: 1000, full duplex
737 10:17:03.180123 BOOTP broadcast 1
738 10:17:03.193573 DHCP client bound to address 192.168.6.21 (15 ms)
740 10:17:03.296696 => setenv serverip 192.168.6.2
741 10:17:03.298829 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:38)
742 10:17:03.302446 setenv serverip 192.168.6.2
744 10:17:03.403657 => tftpboot 0x01080000 974352/tftp-deploy-7ehb0nqp/kernel/uImage
745 10:17:03.404474 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:38)
746 10:17:03.410875 tftpboot 0x01080000 974352/tftp-deploy-7ehb0nqp/kernel/uImage
747 10:17:03.411297 Speed: 1000, full duplex
748 10:17:03.411523 Using ethernet@ff3f0000 device
749 10:17:03.416372 TFTP from server 192.168.6.2; our IP address is 192.168.6.21
750 10:17:03.421836 Filename '974352/tftp-deploy-7ehb0nqp/kernel/uImage'.
751 10:17:03.425666 Load address: 0x1080000
752 10:17:07.660960 Loading: *#################################################
753 10:17:07.661644 TFTP error: trying to overwrite reserved memory...
755 10:17:07.663135 end: 2.4.3 bootloader-commands (duration 00:00:06) [common]
758 10:17:07.665199 end: 2.4 uboot-commands (duration 00:00:26) [common]
760 10:17:07.666693 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'TFTP error: trying to overwrite reserved memory' (12)'
762 10:17:07.667891 end: 2 uboot-action (duration 00:00:26) [common]
764 10:17:07.669695 Cleaning after the job
765 10:17:07.670328 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/974352/tftp-deploy-7ehb0nqp/ramdisk
766 10:17:07.690924 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/974352/tftp-deploy-7ehb0nqp/kernel
767 10:17:07.702619 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/974352/tftp-deploy-7ehb0nqp/dtb
768 10:17:07.704158 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/974352/tftp-deploy-7ehb0nqp/modules
769 10:17:07.738475 start: 4.1 power-off (timeout 00:00:30) [common]
770 10:17:07.739127 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=solitude-01'
771 10:17:07.769572 >> OK - accepted request
772 10:17:07.771596 Returned 0 in 0 seconds
773 10:17:07.872412 end: 4.1 power-off (duration 00:00:00) [common]
775 10:17:07.873410 start: 4.2 read-feedback (timeout 00:10:00) [common]
776 10:17:07.874062 Listened to connection for namespace 'common' for up to 1s
777 10:17:08.875035 Finalising connection for namespace 'common'
778 10:17:08.875812 Disconnecting from shell: Finalise
779 10:17:08.876417 =>
780 10:17:08.977530 end: 4.2 read-feedback (duration 00:00:01) [common]
781 10:17:08.978306 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/974352
782 10:17:09.346881 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/974352
783 10:17:09.347914 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.