Boot log: beaglebone-black
- Warnings: 2
- Kernel Warnings: 27
- Errors: 0
- Boot result: PASS
- Kernel Errors: 65
1 08:03:35.368525 lava-dispatcher, installed at version: 2024.01
2 08:03:35.369349 start: 0 validate
3 08:03:35.369842 Start time: 2024-11-12 08:03:35.369811+00:00 (UTC)
4 08:03:35.370403 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 08:03:35.370932 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farmhf%2Finitrd.cpio.gz exists
6 08:03:35.412220 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 08:03:35.412738 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241112%2Farm%2Fmulti_v7_defconfig%2Fclang-17%2Fkernel%2FzImage exists
8 08:03:35.443633 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 08:03:35.444434 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241112%2Farm%2Fmulti_v7_defconfig%2Fclang-17%2Fdtbs%2Fti%2Fomap%2Fam335x-boneblack.dtb exists
10 08:03:35.481425 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 08:03:35.481944 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farmhf%2Ffull.rootfs.tar.xz exists
12 08:03:35.516619 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 08:03:35.517100 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241112%2Farm%2Fmulti_v7_defconfig%2Fclang-17%2Fmodules.tar.xz exists
14 08:03:35.555578 validate duration: 0.19
16 08:03:35.556774 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 08:03:35.557139 start: 1.1 download-retry (timeout 00:10:00) [common]
18 08:03:35.557460 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 08:03:35.558076 Not decompressing ramdisk as can be used compressed.
20 08:03:35.558516 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/initrd.cpio.gz
21 08:03:35.558789 saving as /var/lib/lava/dispatcher/tmp/978559/tftp-deploy-6gevtrq_/ramdisk/initrd.cpio.gz
22 08:03:35.559065 total size: 4775763 (4 MB)
23 08:03:35.600101 progress 0 % (0 MB)
24 08:03:35.607310 progress 5 % (0 MB)
25 08:03:35.613030 progress 10 % (0 MB)
26 08:03:35.617018 progress 15 % (0 MB)
27 08:03:35.620916 progress 20 % (0 MB)
28 08:03:35.624282 progress 25 % (1 MB)
29 08:03:35.627611 progress 30 % (1 MB)
30 08:03:35.631297 progress 35 % (1 MB)
31 08:03:35.634576 progress 40 % (1 MB)
32 08:03:35.637912 progress 45 % (2 MB)
33 08:03:35.641243 progress 50 % (2 MB)
34 08:03:35.644991 progress 55 % (2 MB)
35 08:03:35.648347 progress 60 % (2 MB)
36 08:03:35.651738 progress 65 % (2 MB)
37 08:03:35.655446 progress 70 % (3 MB)
38 08:03:35.658734 progress 75 % (3 MB)
39 08:03:35.662189 progress 80 % (3 MB)
40 08:03:35.665426 progress 85 % (3 MB)
41 08:03:35.669172 progress 90 % (4 MB)
42 08:03:35.672331 progress 95 % (4 MB)
43 08:03:35.675282 progress 100 % (4 MB)
44 08:03:35.675939 4 MB downloaded in 0.12 s (38.98 MB/s)
45 08:03:35.676537 end: 1.1.1 http-download (duration 00:00:00) [common]
47 08:03:35.677473 end: 1.1 download-retry (duration 00:00:00) [common]
48 08:03:35.677786 start: 1.2 download-retry (timeout 00:10:00) [common]
49 08:03:35.678070 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 08:03:35.678543 downloading http://storage.kernelci.org/next/master/next-20241112/arm/multi_v7_defconfig/clang-17/kernel/zImage
51 08:03:35.678797 saving as /var/lib/lava/dispatcher/tmp/978559/tftp-deploy-6gevtrq_/kernel/zImage
52 08:03:35.679016 total size: 12132864 (11 MB)
53 08:03:35.679235 No compression specified
54 08:03:35.720510 progress 0 % (0 MB)
55 08:03:35.728639 progress 5 % (0 MB)
56 08:03:35.737227 progress 10 % (1 MB)
57 08:03:35.745241 progress 15 % (1 MB)
58 08:03:35.753623 progress 20 % (2 MB)
59 08:03:35.761590 progress 25 % (2 MB)
60 08:03:35.770162 progress 30 % (3 MB)
61 08:03:35.778308 progress 35 % (4 MB)
62 08:03:35.786870 progress 40 % (4 MB)
63 08:03:35.795148 progress 45 % (5 MB)
64 08:03:35.803511 progress 50 % (5 MB)
65 08:03:35.811674 progress 55 % (6 MB)
66 08:03:35.824205 progress 60 % (6 MB)
67 08:03:35.832071 progress 65 % (7 MB)
68 08:03:35.840180 progress 70 % (8 MB)
69 08:03:35.848532 progress 75 % (8 MB)
70 08:03:35.857298 progress 80 % (9 MB)
71 08:03:35.865258 progress 85 % (9 MB)
72 08:03:35.873690 progress 90 % (10 MB)
73 08:03:35.881634 progress 95 % (11 MB)
74 08:03:35.889735 progress 100 % (11 MB)
75 08:03:35.890336 11 MB downloaded in 0.21 s (54.76 MB/s)
76 08:03:35.890874 end: 1.2.1 http-download (duration 00:00:00) [common]
78 08:03:35.891778 end: 1.2 download-retry (duration 00:00:00) [common]
79 08:03:35.892116 start: 1.3 download-retry (timeout 00:10:00) [common]
80 08:03:35.892442 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 08:03:35.893051 downloading http://storage.kernelci.org/next/master/next-20241112/arm/multi_v7_defconfig/clang-17/dtbs/ti/omap/am335x-boneblack.dtb
82 08:03:35.893358 saving as /var/lib/lava/dispatcher/tmp/978559/tftp-deploy-6gevtrq_/dtb/am335x-boneblack.dtb
83 08:03:35.893581 total size: 70544 (0 MB)
84 08:03:35.893804 No compression specified
85 08:03:35.934323 progress 46 % (0 MB)
86 08:03:35.935172 progress 92 % (0 MB)
87 08:03:35.935902 progress 100 % (0 MB)
88 08:03:35.936426 0 MB downloaded in 0.04 s (1.57 MB/s)
89 08:03:35.936964 end: 1.3.1 http-download (duration 00:00:00) [common]
91 08:03:35.937840 end: 1.3 download-retry (duration 00:00:00) [common]
92 08:03:35.938121 start: 1.4 download-retry (timeout 00:10:00) [common]
93 08:03:35.938563 start: 1.4.1 http-download (timeout 00:10:00) [common]
94 08:03:35.939084 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/full.rootfs.tar.xz
95 08:03:35.939362 saving as /var/lib/lava/dispatcher/tmp/978559/tftp-deploy-6gevtrq_/nfsrootfs/full.rootfs.tar
96 08:03:35.939586 total size: 117747780 (112 MB)
97 08:03:35.939817 Using unxz to decompress xz
98 08:03:35.976017 progress 0 % (0 MB)
99 08:03:36.750395 progress 5 % (5 MB)
100 08:03:37.552345 progress 10 % (11 MB)
101 08:03:38.380750 progress 15 % (16 MB)
102 08:03:39.146544 progress 20 % (22 MB)
103 08:03:39.762035 progress 25 % (28 MB)
104 08:03:40.620926 progress 30 % (33 MB)
105 08:03:41.476866 progress 35 % (39 MB)
106 08:03:41.831557 progress 40 % (44 MB)
107 08:03:42.198212 progress 45 % (50 MB)
108 08:03:42.859653 progress 50 % (56 MB)
109 08:03:43.667437 progress 55 % (61 MB)
110 08:03:44.390355 progress 60 % (67 MB)
111 08:03:45.097239 progress 65 % (73 MB)
112 08:03:45.898143 progress 70 % (78 MB)
113 08:03:46.723713 progress 75 % (84 MB)
114 08:03:47.507374 progress 80 % (89 MB)
115 08:03:48.261614 progress 85 % (95 MB)
116 08:03:49.103542 progress 90 % (101 MB)
117 08:03:49.929326 progress 95 % (106 MB)
118 08:03:50.794717 progress 100 % (112 MB)
119 08:03:50.809206 112 MB downloaded in 14.87 s (7.55 MB/s)
120 08:03:50.810281 end: 1.4.1 http-download (duration 00:00:15) [common]
122 08:03:50.812151 end: 1.4 download-retry (duration 00:00:15) [common]
123 08:03:50.812749 start: 1.5 download-retry (timeout 00:09:45) [common]
124 08:03:50.813337 start: 1.5.1 http-download (timeout 00:09:45) [common]
125 08:03:50.814217 downloading http://storage.kernelci.org/next/master/next-20241112/arm/multi_v7_defconfig/clang-17/modules.tar.xz
126 08:03:50.814733 saving as /var/lib/lava/dispatcher/tmp/978559/tftp-deploy-6gevtrq_/modules/modules.tar
127 08:03:50.815199 total size: 6937076 (6 MB)
128 08:03:50.815666 Using unxz to decompress xz
129 08:03:50.872671 progress 0 % (0 MB)
130 08:03:50.908911 progress 5 % (0 MB)
131 08:03:50.956976 progress 10 % (0 MB)
132 08:03:51.001102 progress 15 % (1 MB)
133 08:03:51.050201 progress 20 % (1 MB)
134 08:03:51.097150 progress 25 % (1 MB)
135 08:03:51.145409 progress 30 % (2 MB)
136 08:03:51.193674 progress 35 % (2 MB)
137 08:03:51.237667 progress 40 % (2 MB)
138 08:03:51.285710 progress 45 % (3 MB)
139 08:03:51.330016 progress 50 % (3 MB)
140 08:03:51.377505 progress 55 % (3 MB)
141 08:03:51.428347 progress 60 % (4 MB)
142 08:03:51.470593 progress 65 % (4 MB)
143 08:03:51.522138 progress 70 % (4 MB)
144 08:03:51.566634 progress 75 % (4 MB)
145 08:03:51.614453 progress 80 % (5 MB)
146 08:03:51.659420 progress 85 % (5 MB)
147 08:03:51.708375 progress 90 % (5 MB)
148 08:03:51.756741 progress 95 % (6 MB)
149 08:03:51.800990 progress 100 % (6 MB)
150 08:03:51.814083 6 MB downloaded in 1.00 s (6.62 MB/s)
151 08:03:51.814698 end: 1.5.1 http-download (duration 00:00:01) [common]
153 08:03:51.815520 end: 1.5 download-retry (duration 00:00:01) [common]
154 08:03:51.815790 start: 1.6 prepare-tftp-overlay (timeout 00:09:44) [common]
155 08:03:51.816156 start: 1.6.1 extract-nfsrootfs (timeout 00:09:44) [common]
156 08:04:08.473004 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/978559/extract-nfsrootfs-6ad1fgfi
157 08:04:08.473620 end: 1.6.1 extract-nfsrootfs (duration 00:00:17) [common]
158 08:04:08.473907 start: 1.6.2 lava-overlay (timeout 00:09:27) [common]
159 08:04:08.474689 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/978559/lava-overlay-6qm0nigf
160 08:04:08.475231 makedir: /var/lib/lava/dispatcher/tmp/978559/lava-overlay-6qm0nigf/lava-978559/bin
161 08:04:08.475647 makedir: /var/lib/lava/dispatcher/tmp/978559/lava-overlay-6qm0nigf/lava-978559/tests
162 08:04:08.476054 makedir: /var/lib/lava/dispatcher/tmp/978559/lava-overlay-6qm0nigf/lava-978559/results
163 08:04:08.476414 Creating /var/lib/lava/dispatcher/tmp/978559/lava-overlay-6qm0nigf/lava-978559/bin/lava-add-keys
164 08:04:08.476951 Creating /var/lib/lava/dispatcher/tmp/978559/lava-overlay-6qm0nigf/lava-978559/bin/lava-add-sources
165 08:04:08.477468 Creating /var/lib/lava/dispatcher/tmp/978559/lava-overlay-6qm0nigf/lava-978559/bin/lava-background-process-start
166 08:04:08.478000 Creating /var/lib/lava/dispatcher/tmp/978559/lava-overlay-6qm0nigf/lava-978559/bin/lava-background-process-stop
167 08:04:08.478531 Creating /var/lib/lava/dispatcher/tmp/978559/lava-overlay-6qm0nigf/lava-978559/bin/lava-common-functions
168 08:04:08.479049 Creating /var/lib/lava/dispatcher/tmp/978559/lava-overlay-6qm0nigf/lava-978559/bin/lava-echo-ipv4
169 08:04:08.479607 Creating /var/lib/lava/dispatcher/tmp/978559/lava-overlay-6qm0nigf/lava-978559/bin/lava-install-packages
170 08:04:08.480130 Creating /var/lib/lava/dispatcher/tmp/978559/lava-overlay-6qm0nigf/lava-978559/bin/lava-installed-packages
171 08:04:08.480638 Creating /var/lib/lava/dispatcher/tmp/978559/lava-overlay-6qm0nigf/lava-978559/bin/lava-os-build
172 08:04:08.481127 Creating /var/lib/lava/dispatcher/tmp/978559/lava-overlay-6qm0nigf/lava-978559/bin/lava-probe-channel
173 08:04:08.481633 Creating /var/lib/lava/dispatcher/tmp/978559/lava-overlay-6qm0nigf/lava-978559/bin/lava-probe-ip
174 08:04:08.482115 Creating /var/lib/lava/dispatcher/tmp/978559/lava-overlay-6qm0nigf/lava-978559/bin/lava-target-ip
175 08:04:08.482596 Creating /var/lib/lava/dispatcher/tmp/978559/lava-overlay-6qm0nigf/lava-978559/bin/lava-target-mac
176 08:04:08.483077 Creating /var/lib/lava/dispatcher/tmp/978559/lava-overlay-6qm0nigf/lava-978559/bin/lava-target-storage
177 08:04:08.483568 Creating /var/lib/lava/dispatcher/tmp/978559/lava-overlay-6qm0nigf/lava-978559/bin/lava-test-case
178 08:04:08.484087 Creating /var/lib/lava/dispatcher/tmp/978559/lava-overlay-6qm0nigf/lava-978559/bin/lava-test-event
179 08:04:08.484588 Creating /var/lib/lava/dispatcher/tmp/978559/lava-overlay-6qm0nigf/lava-978559/bin/lava-test-feedback
180 08:04:08.485075 Creating /var/lib/lava/dispatcher/tmp/978559/lava-overlay-6qm0nigf/lava-978559/bin/lava-test-raise
181 08:04:08.485562 Creating /var/lib/lava/dispatcher/tmp/978559/lava-overlay-6qm0nigf/lava-978559/bin/lava-test-reference
182 08:04:08.486050 Creating /var/lib/lava/dispatcher/tmp/978559/lava-overlay-6qm0nigf/lava-978559/bin/lava-test-runner
183 08:04:08.486556 Creating /var/lib/lava/dispatcher/tmp/978559/lava-overlay-6qm0nigf/lava-978559/bin/lava-test-set
184 08:04:08.487052 Creating /var/lib/lava/dispatcher/tmp/978559/lava-overlay-6qm0nigf/lava-978559/bin/lava-test-shell
185 08:04:08.487558 Updating /var/lib/lava/dispatcher/tmp/978559/lava-overlay-6qm0nigf/lava-978559/bin/lava-add-keys (debian)
186 08:04:08.488127 Updating /var/lib/lava/dispatcher/tmp/978559/lava-overlay-6qm0nigf/lava-978559/bin/lava-add-sources (debian)
187 08:04:08.488661 Updating /var/lib/lava/dispatcher/tmp/978559/lava-overlay-6qm0nigf/lava-978559/bin/lava-install-packages (debian)
188 08:04:08.489169 Updating /var/lib/lava/dispatcher/tmp/978559/lava-overlay-6qm0nigf/lava-978559/bin/lava-installed-packages (debian)
189 08:04:08.489736 Updating /var/lib/lava/dispatcher/tmp/978559/lava-overlay-6qm0nigf/lava-978559/bin/lava-os-build (debian)
190 08:04:08.490182 Creating /var/lib/lava/dispatcher/tmp/978559/lava-overlay-6qm0nigf/lava-978559/environment
191 08:04:08.490561 LAVA metadata
192 08:04:08.490819 - LAVA_JOB_ID=978559
193 08:04:08.491037 - LAVA_DISPATCHER_IP=192.168.6.2
194 08:04:08.491408 start: 1.6.2.1 ssh-authorize (timeout 00:09:27) [common]
195 08:04:08.492425 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
196 08:04:08.492743 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:27) [common]
197 08:04:08.492951 skipped lava-vland-overlay
198 08:04:08.493191 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
199 08:04:08.493442 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:27) [common]
200 08:04:08.493662 skipped lava-multinode-overlay
201 08:04:08.493903 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
202 08:04:08.494152 start: 1.6.2.4 test-definition (timeout 00:09:27) [common]
203 08:04:08.494398 Loading test definitions
204 08:04:08.494672 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:27) [common]
205 08:04:08.494893 Using /lava-978559 at stage 0
206 08:04:08.495968 uuid=978559_1.6.2.4.1 testdef=None
207 08:04:08.496316 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
208 08:04:08.496581 start: 1.6.2.4.2 test-overlay (timeout 00:09:27) [common]
209 08:04:08.498187 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
211 08:04:08.498978 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:27) [common]
212 08:04:08.500929 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
214 08:04:08.501755 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:27) [common]
215 08:04:08.503619 runner path: /var/lib/lava/dispatcher/tmp/978559/lava-overlay-6qm0nigf/lava-978559/0/tests/0_timesync-off test_uuid 978559_1.6.2.4.1
216 08:04:08.504216 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
218 08:04:08.505050 start: 1.6.2.4.5 git-repo-action (timeout 00:09:27) [common]
219 08:04:08.505305 Using /lava-978559 at stage 0
220 08:04:08.505687 Fetching tests from https://github.com/kernelci/test-definitions.git
221 08:04:08.505979 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/978559/lava-overlay-6qm0nigf/lava-978559/0/tests/1_kselftest-dt'
222 08:04:11.834520 Running '/usr/bin/git checkout kernelci.org
223 08:04:12.281580 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/978559/lava-overlay-6qm0nigf/lava-978559/0/tests/1_kselftest-dt/automated/linux/kselftest/kselftest.yaml
224 08:04:12.283344 uuid=978559_1.6.2.4.5 testdef=None
225 08:04:12.283773 end: 1.6.2.4.5 git-repo-action (duration 00:00:04) [common]
227 08:04:12.284736 start: 1.6.2.4.6 test-overlay (timeout 00:09:23) [common]
228 08:04:12.288210 end: 1.6.2.4.6 test-overlay (duration 00:00:00) [common]
230 08:04:12.289238 start: 1.6.2.4.7 test-install-overlay (timeout 00:09:23) [common]
231 08:04:12.293796 end: 1.6.2.4.7 test-install-overlay (duration 00:00:00) [common]
233 08:04:12.294859 start: 1.6.2.4.8 test-runscript-overlay (timeout 00:09:23) [common]
234 08:04:12.299260 runner path: /var/lib/lava/dispatcher/tmp/978559/lava-overlay-6qm0nigf/lava-978559/0/tests/1_kselftest-dt test_uuid 978559_1.6.2.4.5
235 08:04:12.299622 BOARD='beaglebone-black'
236 08:04:12.299875 BRANCH='next'
237 08:04:12.300143 SKIPFILE='/dev/null'
238 08:04:12.300387 SKIP_INSTALL='True'
239 08:04:12.300627 TESTPROG_URL='http://storage.kernelci.org/next/master/next-20241112/arm/multi_v7_defconfig/clang-17/kselftest.tar.xz'
240 08:04:12.300862 TST_CASENAME=''
241 08:04:12.301100 TST_CMDFILES='dt'
242 08:04:12.301813 end: 1.6.2.4.8 test-runscript-overlay (duration 00:00:00) [common]
244 08:04:12.302794 Creating lava-test-runner.conf files
245 08:04:12.303045 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/978559/lava-overlay-6qm0nigf/lava-978559/0 for stage 0
246 08:04:12.303476 - 0_timesync-off
247 08:04:12.303785 - 1_kselftest-dt
248 08:04:12.304225 end: 1.6.2.4 test-definition (duration 00:00:04) [common]
249 08:04:12.304587 start: 1.6.2.5 compress-overlay (timeout 00:09:23) [common]
250 08:04:36.110729 end: 1.6.2.5 compress-overlay (duration 00:00:24) [common]
251 08:04:36.111178 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:08:59) [common]
252 08:04:36.111444 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
253 08:04:36.111715 end: 1.6.2 lava-overlay (duration 00:00:28) [common]
254 08:04:36.111997 start: 1.6.3 extract-overlay-ramdisk (timeout 00:08:59) [common]
255 08:04:36.498100 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
256 08:04:36.498577 start: 1.6.4 extract-modules (timeout 00:08:59) [common]
257 08:04:36.498833 extracting modules file /var/lib/lava/dispatcher/tmp/978559/tftp-deploy-6gevtrq_/modules/modules.tar to /var/lib/lava/dispatcher/tmp/978559/extract-nfsrootfs-6ad1fgfi
258 08:04:37.405083 extracting modules file /var/lib/lava/dispatcher/tmp/978559/tftp-deploy-6gevtrq_/modules/modules.tar to /var/lib/lava/dispatcher/tmp/978559/extract-overlay-ramdisk-2uh1yz8d/ramdisk
259 08:04:38.326034 end: 1.6.4 extract-modules (duration 00:00:02) [common]
260 08:04:38.326492 start: 1.6.5 apply-overlay-tftp (timeout 00:08:57) [common]
261 08:04:38.326773 [common] Applying overlay to NFS
262 08:04:38.326991 [common] Applying overlay /var/lib/lava/dispatcher/tmp/978559/compress-overlay-s60i7f5i/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/978559/extract-nfsrootfs-6ad1fgfi
263 08:04:41.067792 end: 1.6.5 apply-overlay-tftp (duration 00:00:03) [common]
264 08:04:41.068276 start: 1.6.6 prepare-kernel (timeout 00:08:54) [common]
265 08:04:41.068555 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:08:54) [common]
266 08:04:41.068836 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
267 08:04:41.069112 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
268 08:04:41.069427 start: 1.6.7 configure-preseed-file (timeout 00:08:54) [common]
269 08:04:41.069739 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
270 08:04:41.070053 start: 1.6.8 compress-ramdisk (timeout 00:08:54) [common]
271 08:04:41.070349 Building ramdisk /var/lib/lava/dispatcher/tmp/978559/extract-overlay-ramdisk-2uh1yz8d/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/978559/extract-overlay-ramdisk-2uh1yz8d/ramdisk
272 08:04:42.136514 >> 79399 blocks
273 08:04:47.142271 Adding RAMdisk u-boot header.
274 08:04:47.142770 mkimage -A arm -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/978559/extract-overlay-ramdisk-2uh1yz8d/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/978559/extract-overlay-ramdisk-2uh1yz8d/ramdisk.cpio.gz.uboot
275 08:04:47.300481 output: Image Name:
276 08:04:47.300913 output: Created: Tue Nov 12 08:04:47 2024
277 08:04:47.301126 output: Image Type: ARM Linux RAMDisk Image (uncompressed)
278 08:04:47.301330 output: Data Size: 15388886 Bytes = 15028.21 KiB = 14.68 MiB
279 08:04:47.301533 output: Load Address: 00000000
280 08:04:47.301731 output: Entry Point: 00000000
281 08:04:47.301930 output:
282 08:04:47.302731 rename /var/lib/lava/dispatcher/tmp/978559/extract-overlay-ramdisk-2uh1yz8d/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/978559/tftp-deploy-6gevtrq_/ramdisk/ramdisk.cpio.gz.uboot
283 08:04:47.303205 end: 1.6.8 compress-ramdisk (duration 00:00:06) [common]
284 08:04:47.303534 end: 1.6 prepare-tftp-overlay (duration 00:00:55) [common]
285 08:04:47.303868 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:48) [common]
286 08:04:47.304175 No LXC device requested
287 08:04:47.304473 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
288 08:04:47.304770 start: 1.8 deploy-device-env (timeout 00:08:48) [common]
289 08:04:47.305057 end: 1.8 deploy-device-env (duration 00:00:00) [common]
290 08:04:47.305295 Checking files for TFTP limit of 4294967296 bytes.
291 08:04:47.306831 end: 1 tftp-deploy (duration 00:01:12) [common]
292 08:04:47.307195 start: 2 uboot-action (timeout 00:05:00) [common]
293 08:04:47.307508 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
294 08:04:47.307794 end: 2.1 uboot-from-media (duration 00:00:00) [common]
295 08:04:47.308109 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
296 08:04:47.308548 substitutions:
297 08:04:47.308797 - {BOOTX}: bootz 0x82000000 0x83000000 0x88000000
298 08:04:47.309023 - {DTB_ADDR}: 0x88000000
299 08:04:47.309250 - {DTB}: 978559/tftp-deploy-6gevtrq_/dtb/am335x-boneblack.dtb
300 08:04:47.309469 - {INITRD}: 978559/tftp-deploy-6gevtrq_/ramdisk/ramdisk.cpio.gz.uboot
301 08:04:47.309683 - {KERNEL_ADDR}: 0x82000000
302 08:04:47.309902 - {KERNEL}: 978559/tftp-deploy-6gevtrq_/kernel/zImage
303 08:04:47.310112 - {LAVA_MAC}: None
304 08:04:47.310354 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/978559/extract-nfsrootfs-6ad1fgfi
305 08:04:47.310573 - {NFS_SERVER_IP}: 192.168.6.2
306 08:04:47.310784 - {PRESEED_CONFIG}: None
307 08:04:47.310993 - {PRESEED_LOCAL}: None
308 08:04:47.311201 - {RAMDISK_ADDR}: 0x83000000
309 08:04:47.311406 - {RAMDISK}: 978559/tftp-deploy-6gevtrq_/ramdisk/ramdisk.cpio.gz.uboot
310 08:04:47.311615 - {ROOT_PART}: None
311 08:04:47.311821 - {ROOT}: None
312 08:04:47.312057 - {SERVER_IP}: 192.168.6.2
313 08:04:47.312269 - {TEE_ADDR}: 0x83000000
314 08:04:47.312475 - {TEE}: None
315 08:04:47.312679 Parsed boot commands:
316 08:04:47.312891 - setenv autoload no
317 08:04:47.313102 - setenv initrd_high 0xffffffff
318 08:04:47.313308 - setenv fdt_high 0xffffffff
319 08:04:47.313511 - dhcp
320 08:04:47.313713 - setenv serverip 192.168.6.2
321 08:04:47.313916 - tftp 0x82000000 978559/tftp-deploy-6gevtrq_/kernel/zImage
322 08:04:47.314121 - tftp 0x83000000 978559/tftp-deploy-6gevtrq_/ramdisk/ramdisk.cpio.gz.uboot
323 08:04:47.314328 - setenv initrd_size ${filesize}
324 08:04:47.314529 - tftp 0x88000000 978559/tftp-deploy-6gevtrq_/dtb/am335x-boneblack.dtb
325 08:04:47.314732 - setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/978559/extract-nfsrootfs-6ad1fgfi,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
326 08:04:47.314946 - bootz 0x82000000 0x83000000 0x88000000
327 08:04:47.315230 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
329 08:04:47.316075 start: 2.3 connect-device (timeout 00:05:00) [common]
330 08:04:47.316321 [common] connect-device Connecting to device using 'telnet conserv3 3001'
331 08:04:47.328828 Setting prompt string to ['lava-test: # ']
332 08:04:47.329814 end: 2.3 connect-device (duration 00:00:00) [common]
333 08:04:47.330194 start: 2.4 uboot-commands (timeout 00:05:00) [common]
334 08:04:47.330526 start: 2.4.1 reset-device (timeout 00:05:00) [common]
335 08:04:47.330841 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
336 08:04:47.331534 Calling: 'curl' 'http://conserv3.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=beaglebone-black-04'
337 08:04:47.367690 >> OK - accepted request
338 08:04:47.369273 Returned 0 in 0 seconds
339 08:04:47.470239 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
341 08:04:47.472121 end: 2.4.1 reset-device (duration 00:00:00) [common]
342 08:04:47.472744 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
343 08:04:47.473296 Setting prompt string to ['Hit any key to stop autoboot']
344 08:04:47.473796 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
345 08:04:47.475486 Trying 192.168.56.22...
346 08:04:47.476041 Connected to conserv3.
347 08:04:47.476496 Escape character is '^]'.
348 08:04:47.476940
349 08:04:47.477404 ser2net port telnet,3001 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.2.4:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
350 08:04:47.477863
351 08:05:25.473770
352 08:05:25.480530 U-Boot SPL 2023.01-rc4-00047-g3089d12a02 (Jan 01 2023 - 22:23:32 +0000)
353 08:05:25.481101 Trying to boot from MMC1
354 08:05:26.056277
355 08:05:26.056922
356 08:05:26.061890 U-Boot 2023.01-rc4-00047-g3089d12a02 (Jan 01 2023 - 22:23:32 +0000)
357 08:05:26.062410
358 08:05:26.062881 CPU : AM335X-GP rev 2.0
359 08:05:26.065871 Model: TI AM335x BeagleBone Black
360 08:05:26.066390 DRAM: 512 MiB
361 08:05:26.151129 Core: 160 devices, 18 uclasses, devicetree: separate
362 08:05:26.165012 WDT: Started wdt@44e35000 with servicing every 1000ms (60s timeout)
363 08:05:26.565934 NAND: 0 MiB
364 08:05:26.576014 MMC: OMAP SD/MMC: 0, OMAP SD/MMC: 1
365 08:05:26.650605 Loading Environment from FAT... Unable to read "uboot.env" from mmc0:1...
366 08:05:26.671959 <ethaddr> not set. Validating first E-fuse MAC
367 08:05:26.701766 Net: eth2: ethernet@4a100000, eth3: usb_ether
369 08:05:26.760270 Hit any key to stop autoboot: 2
370 08:05:26.761198 end: 2.4.2 bootloader-interrupt (duration 00:00:39) [common]
371 08:05:26.761897 start: 2.4.3 bootloader-commands (timeout 00:04:21) [common]
372 08:05:26.762464 Setting prompt string to ['=>']
373 08:05:26.763051 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:21)
374 08:05:26.770171 0
375 08:05:26.771148 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
376 08:05:26.771764 Sending with 10 millisecond of delay
378 08:05:27.907081 => setenv autoload no
379 08:05:27.917945 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:19)
380 08:05:27.923371 setenv autoload no
381 08:05:27.924194 Sending with 10 millisecond of delay
383 08:05:29.721613 => setenv initrd_high 0xffffffff
384 08:05:29.732443 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
385 08:05:29.733335 setenv initrd_high 0xffffffff
386 08:05:29.734098 Sending with 10 millisecond of delay
388 08:05:31.350475 => setenv fdt_high 0xffffffff
389 08:05:31.361297 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:16)
390 08:05:31.362282 setenv fdt_high 0xffffffff
391 08:05:31.363024 Sending with 10 millisecond of delay
393 08:05:31.655048 => dhcp
394 08:05:31.665836 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:16)
395 08:05:31.666706 dhcp
396 08:05:31.668688 link up on port 0, speed 100, full duplex
397 08:05:31.669183 BOOTP broadcast 1
398 08:05:31.782293 DHCP client bound to address 192.168.6.16 (110 ms)
399 08:05:31.783185 Sending with 10 millisecond of delay
401 08:05:33.459928 => setenv serverip 192.168.6.2
402 08:05:33.470772 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:14)
403 08:05:33.471637 setenv serverip 192.168.6.2
404 08:05:33.472443 Sending with 10 millisecond of delay
406 08:05:36.956115 => tftp 0x82000000 978559/tftp-deploy-6gevtrq_/kernel/zImage
407 08:05:36.966918 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:10)
408 08:05:36.967824 tftp 0x82000000 978559/tftp-deploy-6gevtrq_/kernel/zImage
409 08:05:36.968534 link up on port 0, speed 100, full duplex
410 08:05:36.971720 Using ethernet@4a100000 device
411 08:05:36.977401 TFTP from server 192.168.6.2; our IP address is 192.168.6.16
412 08:05:36.977884 Filename '978559/tftp-deploy-6gevtrq_/kernel/zImage'.
413 08:05:36.980756 Load address: 0x82000000
414 08:05:39.390417 Loading: *################################################## 11.6 MiB
415 08:05:39.391041 4.8 MiB/s
416 08:05:39.391459 done
417 08:05:39.393991 Bytes transferred = 12132864 (b92200 hex)
418 08:05:39.394719 Sending with 10 millisecond of delay
420 08:05:43.842796 => tftp 0x83000000 978559/tftp-deploy-6gevtrq_/ramdisk/ramdisk.cpio.gz.uboot
421 08:05:43.853596 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:03)
422 08:05:43.854454 tftp 0x83000000 978559/tftp-deploy-6gevtrq_/ramdisk/ramdisk.cpio.gz.uboot
423 08:05:43.854910 link up on port 0, speed 100, full duplex
424 08:05:43.858567 Using ethernet@4a100000 device
425 08:05:43.864044 TFTP from server 192.168.6.2; our IP address is 192.168.6.16
426 08:05:43.867550 Filename '978559/tftp-deploy-6gevtrq_/ramdisk/ramdisk.cpio.gz.uboot'.
427 08:05:43.872612 Load address: 0x83000000
428 08:05:46.690782 Loading: *################################################## 14.7 MiB
429 08:05:46.691403 5.2 MiB/s
430 08:05:46.691840 done
431 08:05:46.693871 Bytes transferred = 15388950 (ead116 hex)
432 08:05:46.694626 Sending with 10 millisecond of delay
434 08:05:48.552377 => setenv initrd_size ${filesize}
435 08:05:48.563176 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:03:59)
436 08:05:48.564052 setenv initrd_size ${filesize}
437 08:05:48.564768 Sending with 10 millisecond of delay
439 08:05:52.710580 => tftp 0x88000000 978559/tftp-deploy-6gevtrq_/dtb/am335x-boneblack.dtb
440 08:05:52.721352 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:03:55)
441 08:05:52.722118 tftp 0x88000000 978559/tftp-deploy-6gevtrq_/dtb/am335x-boneblack.dtb
442 08:05:52.722543 link up on port 0, speed 100, full duplex
443 08:05:52.726489 Using ethernet@4a100000 device
444 08:05:52.731891 TFTP from server 192.168.6.2; our IP address is 192.168.6.16
445 08:05:52.743643 Filename '978559/tftp-deploy-6gevtrq_/dtb/am335x-boneblack.dtb'.
446 08:05:52.744114 Load address: 0x88000000
447 08:05:52.754045 Loading: *################################################## 68.9 KiB
448 08:05:52.754476 4.5 MiB/s
449 08:05:52.762295 done
450 08:05:52.762756 Bytes transferred = 70544 (11390 hex)
451 08:05:52.763418 Sending with 10 millisecond of delay
453 08:06:05.940353 => setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/978559/extract-nfsrootfs-6ad1fgfi,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
454 08:06:05.951197 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:03:41)
455 08:06:05.952176 setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/978559/extract-nfsrootfs-6ad1fgfi,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
456 08:06:05.952952 Sending with 10 millisecond of delay
458 08:06:08.292075 => bootz 0x82000000 0x83000000 0x88000000
459 08:06:08.302964 Setting prompt string to ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
460 08:06:08.303649 bootloader-commands: Wait for prompt ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:03:39)
461 08:06:08.304777 bootz 0x82000000 0x83000000 0x88000000
462 08:06:08.305279 Kernel image @ 0x82000000 [ 0x000000 - 0xb92200 ]
463 08:06:08.305826 ## Loading init Ramdisk from Legacy Image at 83000000 ...
464 08:06:08.310662 Image Name:
465 08:06:08.311191 Created: 2024-11-12 8:04:47 UTC
466 08:06:08.319638 Image Type: ARM Linux RAMDisk Image (uncompressed)
467 08:06:08.320186 Data Size: 15388886 Bytes = 14.7 MiB
468 08:06:08.327940 Load Address: 00000000
469 08:06:08.328479 Entry Point: 00000000
470 08:06:08.503043 Verifying Checksum ... OK
471 08:06:08.503583 ## Flattened Device Tree blob at 88000000
472 08:06:08.509428 Booting using the fdt blob at 0x88000000
473 08:06:08.509933 Working FDT set to 88000000
474 08:06:08.514952 Using Device Tree in place at 88000000, end 8801438f
475 08:06:08.519329 Working FDT set to 88000000
476 08:06:08.532576
477 08:06:08.533072 Starting kernel ...
478 08:06:08.533523
479 08:06:08.534447 end: 2.4.3 bootloader-commands (duration 00:00:42) [common]
480 08:06:08.535088 start: 2.4.4 auto-login-action (timeout 00:03:39) [common]
481 08:06:08.535600 Setting prompt string to ['Linux version [0-9]']
482 08:06:08.536149 Setting prompt string to ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
483 08:06:08.536665 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:05:00)
484 08:06:09.451177 [ 0.000000] Booting Linux on physical CPU 0x0
485 08:06:09.457213 start: 2.4.4.1 login-action (timeout 00:03:38) [common]
486 08:06:09.457916 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
487 08:06:09.458486 Setting prompt string to []
488 08:06:09.459051 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
489 08:06:09.459599 Using line separator: #'\n'#
490 08:06:09.460164 No login prompt set.
491 08:06:09.460718 Parsing kernel messages
492 08:06:09.461215 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
493 08:06:09.462152 [login-action] Waiting for messages, (timeout 00:03:38)
494 08:06:09.462722 Waiting using forced prompt support (timeout 00:01:49)
495 08:06:09.473879 [ 0.000000] Linux version 6.12.0-rc7-next-20241112 (KernelCI@build-j373760-arm-clang-17-multi-v7-defconfig-964p7) (Debian clang version 17.0.6 (++20231208085813+6009708b4367-1~exp1~20231208085906.81), Debian LLD 17.0.6) #1 SMP Tue Nov 12 07:33:51 UTC 2024
496 08:06:09.485530 [ 0.000000] CPU: ARMv7 Processor [413fc082] revision 2 (ARMv7), cr=10c5387d
497 08:06:09.491092 [ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
498 08:06:09.496891 [ 0.000000] OF: fdt: Machine model: TI AM335x BeagleBone Black
499 08:06:09.502459 [ 0.000000] earlycon: omap8250 at MMIO 0x44e09000 (options '')
500 08:06:09.508151 [ 0.000000] printk: legacy bootconsole [omap8250] enabled
501 08:06:09.514864 [ 0.000000] Memory policy: Data cache writeback
502 08:06:09.515454 [ 0.000000] efi: UEFI not found.
503 08:06:09.523119 [ 0.000000] cma: Reserved 64 MiB at 0x9b800000 on node -1
504 08:06:09.528795 [ 0.000000] Zone ranges:
505 08:06:09.534501 [ 0.000000] DMA [mem 0x0000000080000000-0x000000009fdfffff]
506 08:06:09.540275 [ 0.000000] Normal empty
507 08:06:09.540839 [ 0.000000] HighMem empty
508 08:06:09.546065 [ 0.000000] Movable zone start for each node
509 08:06:09.546594 [ 0.000000] Early memory node ranges
510 08:06:09.557577 [ 0.000000] node 0: [mem 0x0000000080000000-0x000000009fdfffff]
511 08:06:09.562830 [ 0.000000] Initmem setup node 0 [mem 0x0000000080000000-0x000000009fdfffff]
512 08:06:09.576207 [ 0.000000] OF: reserved mem: Reserved memory: No reserved-memory node in the DT
513 08:06:09.589621 [ 0.000000] CPU: All CPU(s) started in SVC mode.
514 08:06:09.595285 [ 0.000000] AM335X ES2.0 (sgx neon)
515 08:06:09.607026 [ 0.000000] percpu: Embedded 17 pages/cpu s40140 r8192 d21300 u69632
516 08:06:09.624618 [ 0.000000] Kernel command line: console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/978559/extract-nfsrootfs-6ad1fgfi,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp
517 08:06:09.636401 <6>[ 0.000000] printk: log buffer data + meta data: 131072 + 409600 = 540672 bytes
518 08:06:09.642110 <6>[ 0.000000] Dentry cache hash table entries: 65536 (order: 6, 262144 bytes, linear)
519 08:06:09.653483 <6>[ 0.000000] Inode-cache hash table entries: 32768 (order: 5, 131072 bytes, linear)
520 08:06:09.659342 <6>[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 130560
521 08:06:09.665629 <6>[ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
522 08:06:09.694828 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
523 08:06:09.700785 <6>[ 0.000000] trace event string verifier disabled
524 08:06:09.701337 <6>[ 0.000000] rcu: Hierarchical RCU implementation.
525 08:06:09.706610 <6>[ 0.000000] rcu: RCU event tracing is enabled.
526 08:06:09.717961 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=16 to nr_cpu_ids=1.
527 08:06:09.718560 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
528 08:06:09.729424 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 10 jiffies.
529 08:06:09.735225 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=1
530 08:06:09.745981 <6>[ 0.000000] RCU Tasks Trace: Setting shift to 0 and lim to 1 rcu_task_cb_adjust=1 rcu_task_cpu_ids=1.
531 08:06:09.761139 <6>[ 0.000000] NR_IRQS: 16, nr_irqs: 16, preallocated irqs: 16
532 08:06:09.779422 <6>[ 0.000000] IRQ: Found an INTC at 0x(ptrval) (revision 5.0) with 128 interrupts
533 08:06:09.785300 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
534 08:06:09.888996 <6>[ 0.000000] TI gptimer clocksource: always-on /ocp/interconnect@44c00000/segment@200000/target-module@31000
535 08:06:09.900381 <6>[ 0.000003] sched_clock: 32 bits at 24MHz, resolution 41ns, wraps every 89478484971ns
536 08:06:09.907346 <6>[ 0.008336] clocksource: dmtimer: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 79635851949 ns
537 08:06:09.919504 <6>[ 0.019232] TI gptimer clockevent: 24000000 Hz at /ocp/interconnect@48000000/segment@0/target-module@40000
538 08:06:09.928089 <6>[ 0.034462] Console: colour dummy device 80x30
539 08:06:09.934219 Matched prompt #6: WARNING:
540 08:06:09.934796 Setting prompt string to ['end trace[^\\r]*\\r', '/ #', 'Login timed out', 'Login incorrect']
541 08:06:09.939685 <3>[ 0.039364] WARNING: Your 'console=ttyO0' has been replaced by 'ttyS0'
542 08:06:09.945418 <3>[ 0.046438] This ensures that you still see kernel messages. Please
543 08:06:09.947766 <3>[ 0.053165] update your kernel commandline.
544 08:06:09.988794 <6>[ 0.057774] Calibrating delay loop... 996.14 BogoMIPS (lpj=4980736)
545 08:06:09.994647 <6>[ 0.096239] CPU: Testing write buffer coherency: ok
546 08:06:09.997422 <6>[ 0.101603] CPU0: Spectre v2: using BPIALL workaround
547 08:06:10.003259 <6>[ 0.107067] pid_max: default: 32768 minimum: 301
548 08:06:10.008984 <6>[ 0.112270] Mount-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
549 08:06:10.017753 <6>[ 0.120096] Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
550 08:06:10.025001 <6>[ 0.129567] CPU0: thread -1, cpu 0, socket -1, mpidr 0
551 08:06:10.033539 <6>[ 0.136649] Setting up static identity map for 0x80300000 - 0x803000ac
552 08:06:10.040116 <6>[ 0.146456] rcu: Hierarchical SRCU implementation.
553 08:06:10.047282 <6>[ 0.151746] rcu: Max phase no-delay instances is 1000.
554 08:06:10.057184 <6>[ 0.163236] EFI services will not be available.
555 08:06:10.062987 <6>[ 0.168527] smp: Bringing up secondary CPUs ...
556 08:06:10.068753 <6>[ 0.173582] smp: Brought up 1 node, 1 CPU
557 08:06:10.076971 <6>[ 0.177982] SMP: Total of 1 processors activated (996.14 BogoMIPS).
558 08:06:10.082953 <6>[ 0.184752] CPU: All CPU(s) started in SVC mode.
559 08:06:10.100692 <6>[ 0.189949] Memory: 404368K/522240K available (17408K kernel code, 2537K rwdata, 6740K rodata, 2048K init, 430K bss, 50676K reserved, 65536K cma-reserved, 0K highmem)
560 08:06:10.101261 <6>[ 0.206255] devtmpfs: initialized
561 08:06:10.124077 <6>[ 0.224347] VFP support v0.3: implementor 41 architecture 3 part 30 variant c rev 3
562 08:06:10.135571 <6>[ 0.232958] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
563 08:06:10.140738 <6>[ 0.243414] futex hash table entries: 256 (order: 2, 16384 bytes, linear)
564 08:06:10.152241 <6>[ 0.255674] pinctrl core: initialized pinctrl subsystem
565 08:06:10.161920 <6>[ 0.266674] DMI not present or invalid.
566 08:06:10.170255 <6>[ 0.272558] NET: Registered PF_NETLINK/PF_ROUTE protocol family
567 08:06:10.179037 <6>[ 0.281569] DMA: preallocated 256 KiB pool for atomic coherent allocations
568 08:06:10.194168 <6>[ 0.293278] thermal_sys: Registered thermal governor 'step_wise'
569 08:06:10.194754 <6>[ 0.293474] cpuidle: using governor menu
570 08:06:10.234635 <6>[ 0.322866] /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70: Fixed dependency cycle(s) with /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
571 08:06:10.254728 <6>[ 0.341690] /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
572 08:06:10.255347 <6>[ 0.362338] No ATAGs?
573 08:06:10.262014 <6>[ 0.364973] hw-breakpoint: debug architecture 0x4 unsupported.
574 08:06:10.271635 <6>[ 0.377245] Serial: AMBA PL011 UART driver
575 08:06:10.309611 <6>[ 0.415948] iommu: Default domain type: Translated
576 08:06:10.318666 <6>[ 0.421302] iommu: DMA domain TLB invalidation policy: strict mode
577 08:06:10.345329 <5>[ 0.450996] SCSI subsystem initialized
578 08:06:10.351120 <6>[ 0.455894] usbcore: registered new interface driver usbfs
579 08:06:10.356986 <6>[ 0.461951] usbcore: registered new interface driver hub
580 08:06:10.365584 <6>[ 0.467734] usbcore: registered new device driver usb
581 08:06:10.371469 <6>[ 0.474316] pps_core: LinuxPPS API ver. 1 registered
582 08:06:10.377098 <6>[ 0.479746] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
583 08:06:10.383026 <6>[ 0.489431] PTP clock support registered
584 08:06:10.388141 <6>[ 0.493896] EDAC MC: Ver: 3.0.0
585 08:06:10.440097 <6>[ 0.543857] scmi_core: SCMI protocol bus registered
586 08:06:10.464252 <6>[ 0.569925] vgaarb: loaded
587 08:06:10.470425 <6>[ 0.573708] clocksource: Switched to clocksource dmtimer
588 08:06:10.497325 <6>[ 0.603260] NET: Registered PF_INET protocol family
589 08:06:10.509964 <6>[ 0.608986] IP idents hash table entries: 8192 (order: 4, 65536 bytes, linear)
590 08:06:10.515814 <6>[ 0.618024] tcp_listen_portaddr_hash hash table entries: 512 (order: 0, 4096 bytes, linear)
591 08:06:10.527217 <6>[ 0.626969] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
592 08:06:10.533080 <6>[ 0.635233] TCP established hash table entries: 4096 (order: 2, 16384 bytes, linear)
593 08:06:10.544509 <6>[ 0.643504] TCP bind hash table entries: 4096 (order: 4, 65536 bytes, linear)
594 08:06:10.550603 <6>[ 0.651222] TCP: Hash tables configured (established 4096 bind 4096)
595 08:06:10.556372 <6>[ 0.658143] UDP hash table entries: 256 (order: 1, 8192 bytes, linear)
596 08:06:10.562182 <6>[ 0.665180] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes, linear)
597 08:06:10.569714 <6>[ 0.672771] NET: Registered PF_UNIX/PF_LOCAL protocol family
598 08:06:10.666554 <6>[ 0.767345] RPC: Registered named UNIX socket transport module.
599 08:06:10.666966 <6>[ 0.773773] RPC: Registered udp transport module.
600 08:06:10.672427 <6>[ 0.778879] RPC: Registered tcp transport module.
601 08:06:10.681347 <6>[ 0.784007] RPC: Registered tcp-with-tls transport module.
602 08:06:10.687128 <6>[ 0.789916] RPC: Registered tcp NFSv4.1 backchannel transport module.
603 08:06:10.694001 <6>[ 0.796836] PCI: CLS 0 bytes, default 64
604 08:06:10.696251 <5>[ 0.802684] Initialise system trusted keyrings
605 08:06:10.717312 <6>[ 0.820668] Trying to unpack rootfs image as initramfs...
606 08:06:10.773780 <6>[ 0.874069] workingset: timestamp_bits=30 max_order=17 bucket_order=0
607 08:06:10.778641 <6>[ 0.881592] squashfs: version 4.0 (2009/01/31) Phillip Lougher
608 08:06:10.808050 <5>[ 0.914398] NFS: Registering the id_resolver key type
609 08:06:10.813816 <5>[ 0.919985] Key type id_resolver registered
610 08:06:10.819730 <5>[ 0.924675] Key type id_legacy registered
611 08:06:10.828087 <6>[ 0.929114] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
612 08:06:10.834971 <6>[ 0.936314] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
613 08:06:10.907729 <5>[ 1.014058] Key type asymmetric registered
614 08:06:10.913631 <5>[ 1.018588] Asymmetric key parser 'x509' registered
615 08:06:10.925024 <6>[ 1.024079] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 246)
616 08:06:10.925608 <6>[ 1.031967] io scheduler mq-deadline registered
617 08:06:10.930745 <6>[ 1.036927] io scheduler kyber registered
618 08:06:10.936364 <6>[ 1.041379] io scheduler bfq registered
619 08:06:11.072987 <6>[ 1.175738] ledtrig-cpu: registered to indicate activity on CPUs
620 08:06:11.354259 <6>[ 1.456880] Serial: 8250/16550 driver, 5 ports, IRQ sharing enabled
621 08:06:11.383371 <6>[ 1.489379] msm_serial: driver initialized
622 08:06:11.389246 <6>[ 1.494468] SuperH (H)SCI(F) driver initialized
623 08:06:11.395188 <6>[ 1.499604] STMicroelectronics ASC driver initialized
624 08:06:11.400413 <6>[ 1.505297] STM32 USART driver initialized
625 08:06:11.529339 <6>[ 1.634985] brd: module loaded
626 08:06:11.559947 <6>[ 1.665528] loop: module loaded
627 08:06:11.604930 <6>[ 1.710150] CAN device driver interface
628 08:06:11.611085 <6>[ 1.715450] bgmac_bcma: Broadcom 47xx GBit MAC driver loaded
629 08:06:11.616837 <6>[ 1.722410] e1000e: Intel(R) PRO/1000 Network Driver
630 08:06:11.623651 <6>[ 1.727867] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
631 08:06:11.629493 <6>[ 1.734319] igb: Intel(R) Gigabit Ethernet Network Driver
632 08:06:11.636752 <6>[ 1.740141] igb: Copyright (c) 2007-2014 Intel Corporation.
633 08:06:11.648822 <6>[ 1.749523] pegasus: Pegasus/Pegasus II USB Ethernet driver
634 08:06:11.654633 <6>[ 1.755685] usbcore: registered new interface driver pegasus
635 08:06:11.660350 <6>[ 1.761817] usbcore: registered new interface driver asix
636 08:06:11.666043 <6>[ 1.767702] usbcore: registered new interface driver ax88179_178a
637 08:06:11.671821 <6>[ 1.774295] usbcore: registered new interface driver cdc_ether
638 08:06:11.677588 <6>[ 1.780590] usbcore: registered new interface driver smsc75xx
639 08:06:11.683372 <6>[ 1.786831] usbcore: registered new interface driver smsc95xx
640 08:06:11.689118 <6>[ 1.793039] usbcore: registered new interface driver net1080
641 08:06:11.694907 <6>[ 1.799189] usbcore: registered new interface driver cdc_subset
642 08:06:11.700710 <6>[ 1.805598] usbcore: registered new interface driver zaurus
643 08:06:11.708376 <6>[ 1.811639] usbcore: registered new interface driver cdc_ncm
644 08:06:11.718390 <6>[ 1.821280] usbcore: registered new interface driver usb-storage
645 08:06:11.727903 <6>[ 1.832574] i2c_dev: i2c /dev entries driver
646 08:06:11.753286 <5>[ 1.851840] cpuidle: enable-method property 'ti,am3352' found operations
647 08:06:11.759241 <6>[ 1.861408] sdhci: Secure Digital Host Controller Interface driver
648 08:06:11.766793 <6>[ 1.868164] sdhci: Copyright(c) Pierre Ossman
649 08:06:11.773971 <6>[ 1.874795] Synopsys Designware Multimedia Card Interface Driver
650 08:06:11.779542 <6>[ 1.882738] sdhci-pltfm: SDHCI platform and OF driver helper
651 08:06:11.793851 <6>[ 1.892823] usbcore: registered new interface driver usbhid
652 08:06:11.794659 <6>[ 1.898938] usbhid: USB HID core driver
653 08:06:11.807034 <6>[ 1.910899] NET: Registered PF_INET6 protocol family
654 08:06:12.270786 <6>[ 2.376667] Segment Routing with IPv6
655 08:06:12.276045 <6>[ 2.380816] In-situ OAM (IOAM) with IPv6
656 08:06:12.282892 <6>[ 2.385338] sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver
657 08:06:12.290269 <6>[ 2.392725] NET: Registered PF_PACKET protocol family
658 08:06:12.296139 <6>[ 2.398281] can: controller area network core
659 08:06:12.296817 <6>[ 2.403115] NET: Registered PF_CAN protocol family
660 08:06:12.301873 <6>[ 2.408346] can: raw protocol
661 08:06:12.307630 <6>[ 2.411671] can: broadcast manager protocol
662 08:06:12.314023 <6>[ 2.416281] can: netlink gateway - max_hops=1
663 08:06:12.314640 <5>[ 2.421789] Key type dns_resolver registered
664 08:06:12.320134 <6>[ 2.426863] ThumbEE CPU extension supported.
665 08:06:12.326376 <5>[ 2.431558] Registering SWP/SWPB emulation handler
666 08:06:12.334609 <3>[ 2.437270] omap_voltage_late_init: Voltage driver support not added
667 08:06:12.551871 <5>[ 2.655832] Loading compiled-in X.509 certificates
668 08:06:12.610998 <6>[ 2.702669] /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70: Fixed dependency cycle(s) with /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
669 08:06:12.640867 <6>[ 2.732587] /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70: Fixed dependency cycle(s) with /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
670 08:06:12.792463 <6>[ 2.880102] /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70: Fixed dependency cycle(s) with /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
671 08:06:12.808044 <6>[ 2.899734] /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70: Fixed dependency cycle(s) with /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
672 08:06:12.835049 <6>[ 2.926534] /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800/clkout2-pins
673 08:06:12.844952 <6>[ 2.948107] pinctrl-single 44e10800.pinmux: 142 pins, size 568
674 08:06:12.871119 <3>[ 2.972551] ti-sysc 44e31000.target-module: probe with driver ti-sysc failed with error -16
675 08:06:13.145980 <6>[ 3.237691] /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
676 08:06:13.172927 <3>[ 3.273493] ti-sysc 48040000.target-module: probe with driver ti-sysc failed with error -16
677 08:06:13.389734 <6>[ 3.494567] OMAP GPIO hardware version 0.1
678 08:06:13.410886 <6>[ 3.513827] omap-mailbox 480c8000.mailbox: omap mailbox rev 0x400
679 08:06:13.472811 <4>[ 3.575503] at24 2-0054: supply vcc not found, using dummy regulator
680 08:06:13.507325 <4>[ 3.609989] at24 2-0055: supply vcc not found, using dummy regulator
681 08:06:13.544962 <4>[ 3.647599] at24 2-0056: supply vcc not found, using dummy regulator
682 08:06:13.585639 <4>[ 3.688277] at24 2-0057: supply vcc not found, using dummy regulator
683 08:06:13.621497 <6>[ 3.726454] Freeing initrd memory: 15032K
684 08:06:13.631547 <6>[ 3.734980] omap_i2c 4819c000.i2c: bus 2 rev0.11 at 100 kHz
685 08:06:13.667772 <3>[ 3.767200] 48000000.interconnect:segment@200000:target-module@0:mpu@0:fck: device ID is greater than 24
686 08:06:13.689948 <6>[ 3.781656] /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
687 08:06:13.717299 <6>[ 3.805295] /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
688 08:06:13.734770 <6>[ 3.824622] /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70: Fixed dependency cycle(s) with /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
689 08:06:13.750860 <6>[ 3.842585] /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
690 08:06:13.773227 <4>[ 3.873265] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
691 08:06:13.780836 <4>[ 3.882369] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
692 08:06:13.789481 <6>[ 3.892299] omap_rng 48310000.rng: Random Number Generator ver. 20
693 08:06:13.813903 <5>[ 3.919545] random: crng init done
694 08:06:13.862375 <6>[ 3.963709] davinci_mdio 4a101000.mdio: davinci mdio revision 1.6, bus freq 1000000
695 08:06:13.945888 <6>[ 4.046159] davinci_mdio 4a101000.mdio: phy[0]: device 4a101000.mdio:00, driver SMSC LAN8710/LAN8720
696 08:06:13.951590 <6>[ 4.056509] cpsw-switch 4a100000.switch: initialized cpsw ale version 1.4
697 08:06:13.959887 <6>[ 4.063844] cpsw-switch 4a100000.switch: ALE Table size 1024, Policers 0
698 08:06:13.971352 <6>[ 4.071291] cpsw-switch 4a100000.switch: cpts: overflow check period 500 (jiffies)
699 08:06:13.982972 <6>[ 4.079435] cpsw-switch 4a100000.switch: CPTS: ref_clk_freq:250000000 calc_mult:2147483648 calc_shift:29 error:0 nsec/sec
700 08:06:13.990421 <6>[ 4.091090] cpsw-switch 4a100000.switch: Detected MACID = c8:a0:30:c2:c5:7d
701 08:06:14.001333 <5>[ 4.100255] cpsw-switch 4a100000.switch: initialized (regs 0x4a100000, pool size 256) hw_ver:0019010C 1.12 (0)
702 08:06:14.029952 <3>[ 4.130810] debugfs: Directory '49000000.dma' with parent 'dmaengine' already present!
703 08:06:14.035670 <6>[ 4.139419] edma 49000000.dma: TI EDMA DMA engine driver
704 08:06:14.108905 <3>[ 4.209092] target-module@4b000000:target-module@140000:pmu@0:fck: device ID is greater than 24
705 08:06:14.123696 <6>[ 4.223588] hw perfevents: enabled with armv7_cortex_a8 PMU driver, 5 (8000000f) counters available
706 08:06:14.135799 <3>[ 4.240767] l3-aon-clkctrl:0000:0: failed to disable
707 08:06:14.191662 <6>[ 4.292387] 44e09000.serial: ttyS0 at MMIO 0x44e09000 (irq = 36, base_baud = 3000000) is a 8250
708 08:06:14.197274 <6>[ 4.301904] printk: legacy console [ttyS0] enabled
709 08:06:14.202896 <6>[ 4.301904] printk: legacy console [ttyS0] enabled
710 08:06:14.208560 <6>[ 4.312233] printk: legacy bootconsole [omap8250] disabled
711 08:06:14.214372 <6>[ 4.312233] printk: legacy bootconsole [omap8250] disabled
712 08:06:14.244698 <4>[ 4.344550] tps65217-pmic: Failed to locate of_node [id: -1]
713 08:06:14.248323 <4>[ 4.351960] tps65217-bl: Failed to locate of_node [id: -1]
714 08:06:14.265282 <6>[ 4.372156] tps65217 0-0024: TPS65217 ID 0xe version 1.2
715 08:06:14.289400 <6>[ 4.379164] /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
716 08:06:14.306668 <6>[ 4.396814] /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70: Fixed dependency cycle(s) with /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
717 08:06:14.311066 <6>[ 4.414666] omap_i2c 44e0b000.i2c: bus 0 rev0.11 at 400 kHz
718 08:06:14.333861 <6>[ 4.435040] omap_gpio 44e07000.gpio: Could not set line 6 debounce to 200000 microseconds (-22)
719 08:06:14.339659 <6>[ 4.444208] sdhci-omap 48060000.mmc: Got CD GPIO
720 08:06:14.346775 <4>[ 4.449334] sdhci-omap 48060000.mmc: supply pbias not found, using dummy regulator
721 08:06:14.362719 <4>[ 4.463030] sdhci-omap 48060000.mmc: supply vqmmc not found, using dummy regulator
722 08:06:14.369004 <4>[ 4.471849] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
723 08:06:14.377979 <4>[ 4.480519] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
724 08:06:14.422729 <6>[ 4.523519] at24 0-0050: 32768 byte 24c256 EEPROM, writable, 1 bytes/write
725 08:06:14.429840 <6>[ 4.531222] mmc1: SDHCI controller on 481d8000.mmc [481d8000.mmc] using External DMA
726 08:06:14.440954 <6>[ 4.542294] mmc0: SDHCI controller on 48060000.mmc [48060000.mmc] using External DMA
727 08:06:14.467793 <6>[ 4.570400] cpsw-switch 4a100000.switch: starting ndev. mode: dual_mac
728 08:06:14.496340 <6>[ 4.592866] mmc0: new high speed SDHC card at address 0001
729 08:06:14.497001 <6>[ 4.601001] mmcblk0: mmc0:0001 EB1QT 29.8 GiB
730 08:06:14.503889 <6>[ 4.610255] mmcblk0: p1
731 08:06:14.522834 <4>[ 4.622172] mmc1: unexpected status 0x2000980 after switch
732 08:06:14.529306 <4>[ 4.629780] mmc1: unexpected status 0x2000900 after switch
733 08:06:14.530923 <4>[ 4.636350] mmc1: unexpected status 0x2000900 after switch
734 08:06:14.542171 <4>[ 4.643300] mmc1: unexpected status 0x2000900 after switch
735 08:06:14.552397 <6>[ 4.649171] mmc1: new high speed MMC card at address 0001
736 08:06:14.552742 <6>[ 4.656524] mmcblk1: mmc1:0001 MMC02G 1.79 GiB
737 08:06:14.565772 <6>[ 4.664177] SMSC LAN8710/LAN8720 4a101000.mdio:00: attached PHY driver (mii_bus:phy_addr=4a101000.mdio:00, irq=POLL)
738 08:06:16.247489 <4>[ 6.346862] mmc1: unexpected status 0x2000980 after switch
739 08:06:16.253529 <4>[ 6.354524] mmc1: unexpected status 0x2000900 after switch
740 08:06:16.255106 <4>[ 6.360802] mmc1: unexpected status 0x2000900 after switch
741 08:06:16.263097 <4>[ 6.367723] mmc1: unexpected status 0x2000900 after switch
742 08:06:16.662886 <6>[ 6.764771] cpsw-switch 4a100000.switch eth0: Link is Up - 100Mbps/Full - flow control off
743 08:06:16.787204 <5>[ 6.793722] Sending DHCP requests ., OK
744 08:06:16.798597 <6>[ 6.898169] IP-Config: Got DHCP answer from 192.168.6.1, my address is 192.168.6.16
745 08:06:16.799148 <6>[ 6.906350] IP-Config: Complete:
746 08:06:16.809893 <6>[ 6.909888] device=eth0, hwaddr=c8:a0:30:c2:c5:7d, ipaddr=192.168.6.16, mask=255.255.255.0, gw=192.168.6.1
747 08:06:16.815529 <6>[ 6.920411] host=192.168.6.16, domain=, nis-domain=(none)
748 08:06:16.827851 <6>[ 6.926641] bootserver=192.168.6.1, rootserver=192.168.6.2, rootpath=
749 08:06:16.828356 <6>[ 6.926678] nameserver0=10.255.253.1
750 08:06:16.833956 <6>[ 6.939234] clk: Disabling unused clocks
751 08:06:16.839741 <6>[ 6.943967] PM: genpd: Disabling unused power domains
752 08:06:16.856519 <6>[ 6.960751] Freeing unused kernel image (initmem) memory: 2048K
753 08:06:16.864044 <6>[ 6.970627] Run /init as init process
754 08:06:16.890644 Loading, please wait...
755 08:06:17.023450 <3>[ 7.123210] I/O error, dev mmcblk1, sector 0 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
756 08:06:17.027597 Starting systemd-udevd version 252.22-1~deb12u1
757 08:06:17.793248 <3>[ 7.894076] I/O error, dev mmcblk1, sector 1 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
758 08:06:18.562394 <3>[ 8.664053] I/O error, dev mmcblk1, sector 2 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
759 08:06:19.328292 <3>[ 9.429123] I/O error, dev mmcblk1, sector 3 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
760 08:06:20.143117 <3>[ 10.244094] I/O error, dev mmcblk1, sector 4 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
761 08:06:20.276558 <4>[ 10.377069] am335x-phy-driver 47401300.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
762 08:06:20.433448 <4>[ 10.533051] am335x-phy-driver 47401b00.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
763 08:06:20.588177 <6>[ 10.695252] musb-hdrc musb-hdrc.1: MUSB HDRC host driver
764 08:06:20.598844 <6>[ 10.700933] musb-hdrc musb-hdrc.1: new USB bus registered, assigned bus number 1
765 08:06:20.908284 <6>[ 11.013915] hub 1-0:1.0: USB hub found
766 08:06:20.925929 <6>[ 11.032616] hub 1-0:1.0: 1 port detected
767 08:06:20.936480 <3>[ 11.037335] I/O error, dev mmcblk1, sector 5 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
768 08:06:21.097105 <6>[ 11.202186] tda998x 0-0070: found TDA19988
769 08:06:21.702295 <3>[ 11.803022] I/O error, dev mmcblk1, sector 6 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
770 08:06:21.901978 <6>[ 12.004739] usb 1-1: new low-speed USB device number 2 using musb-hdrc
771 08:06:22.079382 <3>[ 12.183937] usb 1-1: device descriptor read/64, error -71
772 08:06:22.486475 <3>[ 12.590336] usb 1-1: device descriptor read/64, error -71
773 08:06:22.498824 <3>[ 12.600272] I/O error, dev mmcblk1, sector 7 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
774 08:06:22.506084 <3>[ 12.609253] Buffer I/O error on dev mmcblk1, logical block 0, async page read
775 08:06:22.761256 <6>[ 12.864039] usb 1-1: new low-speed USB device number 3 using musb-hdrc
776 08:06:22.929851 <3>[ 13.033985] usb 1-1: device descriptor read/64, error -71
777 08:06:23.169175 <3>[ 13.274066] usb 1-1: device descriptor read/64, error -71
778 08:06:23.334226 <6>[ 13.438848] usb usb1-port1: attempt power cycle
779 08:06:23.521300 <6>[ 13.624017] usb 1-1: new low-speed USB device number 4 using musb-hdrc
780 08:06:24.157253 <6>[ 14.260008] usb 1-1: new low-speed USB device number 5 using musb-hdrc
781 08:06:25.734843 <3>[ 15.835865] I/O error, dev mmcblk1, sector 0 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
782 08:06:26.503240 <3>[ 16.604316] I/O error, dev mmcblk1, sector 1 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
783 08:06:27.271519 <3>[ 17.372594] I/O error, dev mmcblk1, sector 2 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
784 08:06:28.039915 <3>[ 18.141039] I/O error, dev mmcblk1, sector 3 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
785 08:06:28.808328 <3>[ 18.909460] I/O error, dev mmcblk1, sector 4 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
786 08:06:29.576931 <3>[ 19.677849] I/O error, dev mmcblk1, sector 5 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
787 08:06:30.345129 <3>[ 20.446209] I/O error, dev mmcblk1, sector 6 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
788 08:06:31.112876 <3>[ 21.214630] I/O error, dev mmcblk1, sector 7 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
789 08:06:31.118939 <3>[ 21.223477] Buffer I/O error on dev mmcblk1, logical block 0, async page read
790 08:06:31.126602 <6>[ 21.231187] mmcblk1: unable to read partition table
791 08:06:31.139523 <6>[ 21.244301] mmcblk1boot0: mmc1:0001 MMC02G 1.00 MiB
792 08:06:31.157283 <6>[ 21.261907] mmcblk1boot1: mmc1:0001 MMC02G 1.00 MiB
793 08:06:31.174718 <6>[ 21.278051] mmcblk1rpmb: mmc1:0001 MMC02G 128 KiB, chardev (236:0)
794 08:06:34.411473 <3>[ 24.511782] I/O error, dev mmcblk1, sector 3751808 op 0x0:(READ) flags 0x80700 phys_seg 1 prio class 0
795 08:06:35.180793 <3>[ 25.281084] I/O error, dev mmcblk1, sector 3751809 op 0x0:(READ) flags 0x80700 phys_seg 1 prio class 0
796 08:06:35.949887 <3>[ 26.050327] I/O error, dev mmcblk1, sector 3751810 op 0x0:(READ) flags 0x80700 phys_seg 1 prio class 0
797 08:06:36.719213 <3>[ 26.819557] I/O error, dev mmcblk1, sector 3751811 op 0x0:(READ) flags 0x80700 phys_seg 1 prio class 0
798 08:06:37.488643 <3>[ 27.588976] I/O error, dev mmcblk1, sector 3751812 op 0x0:(READ) flags 0x80700 phys_seg 1 prio class 0
799 08:06:38.257844 <3>[ 28.358246] I/O error, dev mmcblk1, sector 3751813 op 0x0:(READ) flags 0x80700 phys_seg 1 prio class 0
800 08:06:39.027145 <3>[ 29.127478] I/O error, dev mmcblk1, sector 3751814 op 0x0:(READ) flags 0x80700 phys_seg 1 prio class 0
801 08:06:39.796185 <3>[ 29.896723] I/O error, dev mmcblk1, sector 3751815 op 0x0:(READ) flags 0x80700 phys_seg 1 prio class 0
802 08:06:43.026335 <3>[ 33.127047] I/O error, dev mmcblk1, sector 3751808 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
803 08:06:43.794928 <3>[ 33.895953] I/O error, dev mmcblk1, sector 3751809 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
804 08:06:44.563857 <3>[ 34.664840] I/O error, dev mmcblk1, sector 3751810 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
805 08:06:45.332690 <3>[ 35.433760] I/O error, dev mmcblk1, sector 3751811 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
806 08:06:46.101708 <3>[ 36.202531] I/O error, dev mmcblk1, sector 3751812 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
807 08:06:46.870341 <3>[ 36.971389] I/O error, dev mmcblk1, sector 3751813 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
808 08:06:47.638292 <3>[ 37.740262] I/O error, dev mmcblk1, sector 3751814 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
809 08:06:48.407053 <3>[ 38.509201] I/O error, dev mmcblk1, sector 3751815 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
810 08:06:48.416205 <3>[ 38.518647] Buffer I/O error on dev mmcblk1, logical block 468976, async page read
811 08:06:48.486005 Begin: Loading essential drivers ... done.
812 08:06:48.491462 Begin: Running /scripts/init-premount ... done.
813 08:06:48.497054 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
814 08:06:48.506053 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
815 08:06:48.510949 Device /sys/class/net/eth0 found
816 08:06:48.511429 done.
817 08:06:48.567180 Begin: Waiting up to 180 secs for any network device to become available ... done.
818 08:06:48.639360 IP-Config: eth0 hardware address c8:a0:30:c2:c5:7d mtu 1500 DHCP
819 08:06:48.756487 IP-Config: eth0 guessed broadcast address 192.168.6.255
820 08:06:48.762022 IP-Config: eth0 complete (dhcp from 192.168.6.1):
821 08:06:48.767683 address: 192.168.6.16 broadcast: 192.168.6.255 netmask: 255.255.255.0
822 08:06:48.776770 gateway: 192.168.6.1 dns0 : 10.255.253.1 dns1 : 0.0.0.0
823 08:06:48.781453 rootserver: 192.168.6.1 rootpath:
824 08:06:48.782025 filename :
825 08:06:48.932806 done.
826 08:06:48.940183 Begin: Running /scripts/nfs-bottom ... done.
827 08:06:49.004681 Begin: Running /scripts/init-bottom ... done.
828 08:06:50.479291 <30>[ 40.582855] systemd[1]: System time before build time, advancing clock.
829 08:06:50.648887 <30>[ 40.728478] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
830 08:06:50.656706 <30>[ 40.762072] systemd[1]: Detected architecture arm.
831 08:06:50.668965
832 08:06:50.669541 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
833 08:06:50.669978
834 08:06:50.699887 <30>[ 40.804026] systemd[1]: Hostname set to <debian-bookworm-armhf>.
835 08:06:52.838526 <30>[ 42.941557] systemd[1]: Queued start job for default target graphical.target.
836 08:06:52.855767 <30>[ 42.956590] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
837 08:06:52.862387 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
838 08:06:52.885177 <30>[ 42.986544] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
839 08:06:52.893686 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
840 08:06:52.915888 <30>[ 43.017110] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
841 08:06:52.924561 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
842 08:06:52.944102 <30>[ 43.045674] systemd[1]: Created slice user.slice - User and Session Slice.
843 08:06:52.950751 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
844 08:06:52.979405 <30>[ 43.075107] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
845 08:06:52.985397 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
846 08:06:53.003310 <30>[ 43.104886] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
847 08:06:53.014274 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
848 08:06:53.044200 <30>[ 43.134824] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
849 08:06:53.050755 <30>[ 43.155368] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
850 08:06:53.059302 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
851 08:06:53.082371 <30>[ 43.184210] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
852 08:06:53.090675 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
853 08:06:53.113172 <30>[ 43.214596] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
854 08:06:53.121540 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
855 08:06:53.143205 <30>[ 43.244976] systemd[1]: Reached target paths.target - Path Units.
856 08:06:53.148392 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
857 08:06:53.172659 <30>[ 43.274388] systemd[1]: Reached target remote-fs.target - Remote File Systems.
858 08:06:53.180093 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
859 08:06:53.202569 <30>[ 43.304296] systemd[1]: Reached target slices.target - Slice Units.
860 08:06:53.208062 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
861 08:06:53.232737 <30>[ 43.334514] systemd[1]: Reached target swap.target - Swaps.
862 08:06:53.236844 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
863 08:06:53.263156 <30>[ 43.364682] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
864 08:06:53.271077 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
865 08:06:53.294060 <30>[ 43.395466] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
866 08:06:53.302274 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
867 08:06:53.384633 <30>[ 43.481360] systemd[1]: systemd-journald-audit.socket - Journal Audit Socket was skipped because of an unmet condition check (ConditionSecurity=audit).
868 08:06:53.397480 <30>[ 43.498747] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
869 08:06:53.405807 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
870 08:06:53.434617 <30>[ 43.535491] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
871 08:06:53.442079 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
872 08:06:53.466755 <30>[ 43.568067] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
873 08:06:53.474982 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
874 08:06:53.509536 <30>[ 43.611677] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
875 08:06:53.522979 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
876 08:06:53.544448 <30>[ 43.645661] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
877 08:06:53.552987 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
878 08:06:53.579901 <30>[ 43.675434] systemd[1]: dev-hugepages.mount - Huge Pages File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/mm/hugepages).
879 08:06:53.596534 <30>[ 43.692027] systemd[1]: dev-mqueue.mount - POSIX Message Queue File System was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/mqueue).
880 08:06:53.645805 <30>[ 43.749129] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
881 08:06:53.672784 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
882 08:06:53.702517 <30>[ 43.804293] systemd[1]: Mounting sys-kernel-tracing.mount - Kernel Trace File System...
883 08:06:53.710188 Mounting [0;1;39msys-kernel-tracin…[0m - Kernel Trace File System...
884 08:06:53.765935 <30>[ 43.867239] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
885 08:06:53.793469 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
886 08:06:53.845594 <30>[ 43.947546] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
887 08:06:53.871585 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
888 08:06:53.923269 <30>[ 44.025527] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
889 08:06:53.942540 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
890 08:06:54.002730 <30>[ 44.105155] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
891 08:06:54.013689 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
892 08:06:54.074634 <30>[ 44.175017] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
893 08:06:54.084370 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
894 08:06:54.122475 <30>[ 44.225134] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
895 08:06:54.154137 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
896 08:06:54.208265 <30>[ 44.304959] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
897 08:06:54.222096 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
898 08:06:54.251684 <28>[ 44.346211] systemd[1]: systemd-journald.service: unit configures an IP firewall, but the local system does not support BPF/cgroup firewalling.
899 08:06:54.262718 <28>[ 44.364472] systemd[1]: (This warning is only shown for the first unit using IP firewalling.)
900 08:06:54.304956 <30>[ 44.407940] systemd[1]: Starting systemd-journald.service - Journal Service...
901 08:06:54.322087 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
902 08:06:54.414188 <30>[ 44.516503] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
903 08:06:54.437613 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
904 08:06:54.504520 <30>[ 44.607131] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
905 08:06:54.552095 Starting [0;1;39msystemd-network-g… units from Kernel command line...
906 08:06:54.618493 <30>[ 44.719395] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
907 08:06:54.667361 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
908 08:06:54.727431 <30>[ 44.829764] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
909 08:06:54.777913 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
910 08:06:54.854590 <30>[ 44.957346] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
911 08:06:54.893702 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
912 08:06:54.913233 <30>[ 45.015936] systemd[1]: Mounted sys-kernel-tracing.mount - Kernel Trace File System.
913 08:06:54.952982 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-tracing…nt[0m - Kernel Trace File System.
914 08:06:54.976913 <30>[ 45.078507] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
915 08:06:55.007228 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
916 08:06:55.172970 <30>[ 45.276349] systemd[1]: modprobe@configfs.service: Deactivated successfully.
917 08:06:55.197124 <30>[ 45.299314] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
918 08:06:55.228673 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
919 08:06:55.263227 <30>[ 45.365279] systemd[1]: Started systemd-journald.service - Journal Service.
920 08:06:55.269510 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
921 08:06:55.312696 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
922 08:06:55.343734 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
923 08:06:55.368270 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
924 08:06:55.404359 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
925 08:06:55.433702 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
926 08:06:55.455855 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
927 08:06:55.486090 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
928 08:06:55.514834 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
929 08:06:55.542248 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
930 08:06:55.595714 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
931 08:06:55.666311 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
932 08:06:55.725177 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
933 08:06:55.813823 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
934 08:06:55.894745 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
935 08:06:56.032352 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
936 08:06:56.062226 <46>[ 46.164991] systemd-journald[165]: Received client request to flush runtime journal.
937 08:06:56.159465 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
938 08:06:57.026374 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
939 08:06:57.412041 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
940 08:06:57.474562 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
941 08:06:57.847019 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
942 08:06:58.076086 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
943 08:06:58.093696 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
944 08:06:58.112237 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
945 08:06:58.195147 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
946 08:06:58.233424 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
947 08:06:59.135444 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
948 08:06:59.207972 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
949 08:06:59.480894 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
950 08:06:59.611719 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
951 08:06:59.685170 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
952 08:07:01.049077 <4>[ 51.153995] mmc1: unexpected status 0x2000980 after switch
953 08:07:01.114099 <4>[ 51.219985] mmc1: unexpected status 0x2000900 after switch
954 08:07:01.189005 <4>[ 51.294116] mmc1: unexpected status 0x2000900 after switch
955 08:07:01.278955 <4>[ 51.383983] mmc1: unexpected status 0x2000900 after switch
956 08:07:01.625254 [[0m[0;31m* [0m] (1 of 5) Job systemd-networkd.service/start running (8s / 1min 36s)
957 08:07:01.805865 M
[K[[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
958 08:07:01.835263 [K[[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
959 08:07:02.742885 <5>[ 52.846430] cfg80211: Loading compiled-in X.509 certificates for regulatory database
960 08:07:02.921029 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
961 08:07:04.290335 <5>[ 54.396216] Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
962 08:07:04.360755 <5>[ 54.462059] Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
963 08:07:04.366349 <4>[ 54.471029] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
964 08:07:04.373914 <6>[ 54.480122] cfg80211: failed to load regulatory.db
965 08:07:04.543791 <3>[ 54.645152] I/O error, dev mmcblk1, sector 3751808 op 0x0:(READ) flags 0x80700 phys_seg 1 prio class 0
966 08:07:04.705671 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
967 08:07:04.832749 <46>[ 54.926713] systemd-journald[165]: Oldest entry in /var/log/journal/658c871cd7314ccea6115dc5728f8992/system.journal is older than the configured file retention duration (1month), suggesting rotation.
968 08:07:04.953369 <46>[ 55.049322] systemd-journald[165]: /var/log/journal/658c871cd7314ccea6115dc5728f8992/system.journal: Journal header limits reached or header out-of-date, rotating.
969 08:07:04.983732 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
970 08:07:05.326985 <3>[ 55.428335] I/O error, dev mmcblk1, sector 3751809 op 0x0:(READ) flags 0x80700 phys_seg 1 prio class 0
971 08:07:06.112791 <3>[ 56.214262] I/O error, dev mmcblk1, sector 3751810 op 0x0:(READ) flags 0x80700 phys_seg 1 prio class 0
972 08:07:06.892641 <3>[ 56.993987] I/O error, dev mmcblk1, sector 3751811 op 0x0:(READ) flags 0x80700 phys_seg 1 prio class 0
973 08:07:07.670679 <3>[ 57.772322] I/O error, dev mmcblk1, sector 3751812 op 0x0:(READ) flags 0x80700 phys_seg 1 prio class 0
974 08:07:08.442348 <3>[ 58.544015] I/O error, dev mmcblk1, sector 3751813 op 0x0:(READ) flags 0x80700 phys_seg 1 prio class 0
975 08:07:09.219803 <3>[ 59.321494] I/O error, dev mmcblk1, sector 3751814 op 0x0:(READ) flags 0x80700 phys_seg 1 prio class 0
976 08:07:10.021835 <3>[ 60.124424] I/O error, dev mmcblk1, sector 3751815 op 0x0:(READ) flags 0x80700 phys_seg 1 prio class 0
977 08:07:13.277105 <3>[ 63.379081] I/O error, dev mmcblk1, sector 3751808 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
978 08:07:14.035913 <3>[ 64.137984] I/O error, dev mmcblk1, sector 3751809 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
979 08:07:14.328223 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
980 08:07:14.334292 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
981 08:07:14.363540 [[0;32m OK [0m] Reached target [0;1;39musb-gadget.…m - Hardware activated USB gadget.
982 08:07:14.384606 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
983 08:07:14.442480 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
984 08:07:14.492359 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
985 08:07:14.555440 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
986 08:07:14.605561 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
987 08:07:14.658307 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
988 08:07:14.690542 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
989 08:07:14.719733 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
990 08:07:14.796731 <3>[ 64.898820] I/O error, dev mmcblk1, sector 3751810 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
991 08:07:14.813244 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
992 08:07:14.835669 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
993 08:07:14.882883 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
994 08:07:14.912889 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
995 08:07:14.925436 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
996 08:07:14.943540 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
997 08:07:14.967571 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
998 08:07:14.993855 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
999 08:07:15.014778 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
1000 08:07:15.062719 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
1001 08:07:15.080788 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
1002 08:07:15.104804 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
1003 08:07:15.182499 Starting [0;1;39malsa-restore.serv…- Save/Restore Sound Card State...
1004 08:07:15.261487 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
1005 08:07:15.350163 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
1006 08:07:15.435930 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
1007 08:07:15.473265 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
1008 08:07:15.566943 [[0;32m OK [0m] Finished [0;1;39malsa-restore.serv…m - Sa<3>[ 65.669784] I/O error, dev mmcblk1, sector 3751811 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
1009 08:07:15.570798 ve/Restore Sound Card State.
1010 08:07:15.591802 [[0;32m OK [0m] Reached target [0;1;39msound.target[0m - Sound Card.
1011 08:07:15.843938 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
1012 08:07:15.912331 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
1013 08:07:15.974398 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
1014 08:07:15.992428 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
1015 08:07:16.016316 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
1016 08:07:16.237985 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
1017 08:07:16.327115 <3>[ 66.429377] I/O error, dev mmcblk1, sector 3751812 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
1018 08:07:16.619450 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
1019 08:07:16.669746 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
1020 08:07:16.696350 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
1021 08:07:16.790955 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
1022 08:07:16.961948 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
1023 08:07:17.088811 <3>[ 67.190813] I/O error, dev mmcblk1, sector 3751813 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
1024 08:07:17.144642
1025 08:07:17.148145 Debian GNU/Linux 12 debiworm-armhf login: root (automatic login)
1026 08:07:17.148702
1027 08:07:17.480872 Linux debian-bookworm-armhf 6.12.0-rc7-next-20241112 #1 SMP Tue Nov 12 07:33:51 UTC 2024 armv7l
1028 08:07:17.481389
1029 08:07:17.486475 The programs included with the Debian GNU/Linux system are free software;
1030 08:07:17.492082 the exact distribution terms for each program are described in the
1031 08:07:17.497674 individual files in /usr/share/doc/*/copyright.
1032 08:07:17.498062
1033 08:07:17.503281 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
1034 08:07:17.506849 permitted by applicable law.
1035 08:07:17.860973 <3>[ 67.964030] I/O error, dev mmcblk1, sector 3751814 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
1036 08:07:18.619355 <3>[ 68.722872] I/O error, dev mmcblk1, sector 3751815 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
1037 08:07:18.628361 <3>[ 68.732241] Buffer I/O error on dev mmcblk1, logical block 468976, async page read
1038 08:07:22.354157 Unable to match end of the kernel message
1040 08:07:22.355701 Setting prompt string to ['/ #']
1041 08:07:22.356346 end: 2.4.4.1 login-action (duration 00:01:13) [common]
1043 08:07:22.357763 end: 2.4.4 auto-login-action (duration 00:01:14) [common]
1044 08:07:22.358330 start: 2.4.5 expect-shell-connection (timeout 00:02:25) [common]
1045 08:07:22.358887 Setting prompt string to ['/ #']
1046 08:07:22.359342 Forcing a shell prompt, looking for ['/ #']
1048 08:07:22.410369 / #
1049 08:07:22.411037 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
1050 08:07:22.411508 Waiting using forced prompt support (timeout 00:02:30)
1051 08:07:22.416015
1052 08:07:22.422001 end: 2.4.5 expect-shell-connection (duration 00:00:00) [common]
1053 08:07:22.422610 start: 2.4.6 export-device-env (timeout 00:02:25) [common]
1054 08:07:22.423090 Sending with 10 millisecond of delay
1056 08:07:27.413853 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/978559/extract-nfsrootfs-6ad1fgfi'
1057 08:07:27.425082 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/978559/extract-nfsrootfs-6ad1fgfi'
1058 08:07:27.426721 Sending with 10 millisecond of delay
1060 08:07:29.524555 / # export NFS_SERVER_IP='192.168.6.2'
1061 08:07:29.535461 export NFS_SERVER_IP='192.168.6.2'
1062 08:07:29.536931 end: 2.4.6 export-device-env (duration 00:00:07) [common]
1063 08:07:29.537533 end: 2.4 uboot-commands (duration 00:02:42) [common]
1064 08:07:29.538113 end: 2 uboot-action (duration 00:02:42) [common]
1065 08:07:29.538692 start: 3 lava-test-retry (timeout 00:06:06) [common]
1066 08:07:29.539270 start: 3.1 lava-test-shell (timeout 00:06:06) [common]
1067 08:07:29.539733 Using namespace: common
1069 08:07:29.641011 / # #
1070 08:07:29.641718 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
1071 08:07:29.646119 #
1072 08:07:29.652473 Using /lava-978559
1074 08:07:29.753608 / # export SHELL=/bin/bash
1075 08:07:29.758635 export SHELL=/bin/bash
1077 08:07:29.866061 / # . /lava-978559/environment
1078 08:07:29.871123 . /lava-978559/environment
1080 08:07:29.984726 / # /lava-978559/bin/lava-test-runner /lava-978559/0
1081 08:07:29.985368 Test shell timeout: 10s (minimum of the action and connection timeout)
1082 08:07:29.989706 /lava-978559/bin/lava-test-runner /lava-978559/0
1083 08:07:30.433783 + export TESTRUN_ID=0_timesync-off
1084 08:07:30.441684 + TESTRUN_ID=0_timesync-off
1085 08:07:30.442187 + cd /lava-978559/0/tests/0_timesync-off
1086 08:07:30.442611 ++ cat uuid
1087 08:07:30.458708 + UUID=978559_1.6.2.4.1
1088 08:07:30.459199 + set +x
1089 08:07:30.467206 <LAVA_SIGNAL_STARTRUN 0_timesync-off 978559_1.6.2.4.1>
1090 08:07:30.467680 + systemctl stop systemd-timesyncd
1091 08:07:30.468437 Received signal: <STARTRUN> 0_timesync-off 978559_1.6.2.4.1
1092 08:07:30.468889 Starting test lava.0_timesync-off (978559_1.6.2.4.1)
1093 08:07:30.469426 Skipping test definition patterns.
1094 08:07:30.775846 + set +x
1095 08:07:30.776471 <LAVA_SIGNAL_ENDRUN 0_timesync-off 978559_1.6.2.4.1>
1096 08:07:30.777158 Received signal: <ENDRUN> 0_timesync-off 978559_1.6.2.4.1
1097 08:07:30.777655 Ending use of test pattern.
1098 08:07:30.778067 Ending test lava.0_timesync-off (978559_1.6.2.4.1), duration 0.31
1100 08:07:30.968949 + export TESTRUN_ID=1_kselftest-dt
1101 08:07:30.976834 + TESTRUN_ID=1_kselftest-dt
1102 08:07:30.977297 + cd /lava-978559/0/tests/1_kselftest-dt
1103 08:07:30.977717 ++ cat uuid
1104 08:07:30.993480 + UUID=978559_1.6.2.4.5
1105 08:07:30.993935 + set +x
1106 08:07:30.999096 <LAVA_SIGNAL_STARTRUN 1_kselftest-dt 978559_1.6.2.4.5>
1107 08:07:30.999554 + cd ./automated/linux/kselftest/
1108 08:07:31.000292 Received signal: <STARTRUN> 1_kselftest-dt 978559_1.6.2.4.5
1109 08:07:31.000739 Starting test lava.1_kselftest-dt (978559_1.6.2.4.5)
1110 08:07:31.001237 Skipping test definition patterns.
1111 08:07:31.025533 + ./kselftest.sh -c dt -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/next/master/next-20241112/arm/multi_v7_defconfig/clang-17/kselftest.tar.xz -L '' -S /dev/null -b beaglebone-black -g next -e '' -p /opt/kselftests/mainline/ -n 1 -i 1 -E ''
1112 08:07:31.149567 INFO: install_deps skipped
1113 08:07:31.967266 --2024-11-12 08:07:31-- http://storage.kernelci.org/next/master/next-20241112/arm/multi_v7_defconfig/clang-17/kselftest.tar.xz
1114 08:07:31.998707 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
1115 08:07:32.138731 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
1116 08:07:32.276250 HTTP request sent, awaiting response... 200 OK
1117 08:07:32.276931 Length: 2367488 (2.3M) [application/octet-stream]
1118 08:07:32.281737 Saving to: 'kselftest_armhf.tar.gz'
1119 08:07:32.282319
1120 08:07:34.527824
kselftest_armhf.tar 0%[ ] 0 --.-KB/s
kselftest_armhf.tar 2%[ ] 49.92K 183KB/s
kselftest_armhf.tar 8%[> ] 194.76K 355KB/s
kselftest_armhf.tar 16%[==> ] 373.35K 453KB/s
kselftest_armhf.tar 35%[======> ] 815.35K 746KB/s
kselftest_armhf.tar 46%[========> ] 1.04M 708KB/s
kselftest_armhf.tar 68%[============> ] 1.54M 927KB/s
kselftest_armhf.tar 76%[==============> ] 1.73M 928KB/s
kselftest_armhf.tar 93%[=================> ] 2.12M 1.00MB/s
kselftest_armhf.tar 100%[===================>] 2.26M 1.01MB/s in 2.2s
1121 08:07:34.528269
1122 08:07:34.773642 2024-11-12 08:07:34 (1.01 MB/s) - 'kselftest_armhf.tar.gz' saved [2367488/2367488]
1123 08:07:34.774043
1124 08:07:45.377429 skiplist:
1125 08:07:45.377865 ========================================
1126 08:07:45.383108 ========================================
1127 08:07:45.481639 dt:test_unprobed_devices.sh
1128 08:07:45.512532 ============== Tests to run ===============
1129 08:07:45.522033 dt:test_unprobed_devices.sh
1130 08:07:45.526036 ===========End Tests to run ===============
1131 08:07:45.534884 shardfile-dt pass
1132 08:07:45.765314 <12>[ 95.873233] kselftest: Running tests in dt
1133 08:07:45.794147 TAP version 13
1134 08:07:45.817246 1..1
1135 08:07:45.872570 # timeout set to 45
1136 08:07:45.873259 # selftests: dt: test_unprobed_devices.sh
1137 08:07:46.697282 # TAP version 13
1138 08:08:12.005217 # 1..257
1139 08:08:12.178332 # ok 1 / # SKIP
1140 08:08:12.209124 # ok 2 /clk_mcasp0
1141 08:08:12.274519 # ok 3 /clk_mcasp0_fixed # SKIP
1142 08:08:12.350453 # ok 4 /cpus/cpu@0 # SKIP
1143 08:08:12.418966 # ok 5 /cpus/idle-states/mpu_gate # SKIP
1144 08:08:12.442749 # ok 6 /fixedregulator0
1145 08:08:12.461877 # ok 7 /leds
1146 08:08:12.488194 # ok 8 /ocp
1147 08:08:12.507186 # ok 9 /ocp/interconnect@44c00000
1148 08:08:12.534664 # ok 10 /ocp/interconnect@44c00000/segment@0
1149 08:08:12.558795 # ok 11 /ocp/interconnect@44c00000/segment@100000
1150 08:08:12.584642 # ok 12 /ocp/interconnect@44c00000/segment@100000/target-module@0
1151 08:08:12.656439 # not ok 13 /ocp/interconnect@44c00000/segment@100000/target-module@0/cpu@0
1152 08:08:12.674784 # ok 14 /ocp/interconnect@44c00000/segment@200000
1153 08:08:12.702444 # ok 15 /ocp/interconnect@44c00000/segment@200000/target-module@0
1154 08:08:12.807421 # not ok 16 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0
1155 08:08:12.884506 # ok 17 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0 # SKIP
1156 08:08:12.958446 # ok 18 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@0 # SKIP
1157 08:08:13.027118 # ok 19 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@120 # SKIP
1158 08:08:13.100201 # ok 20 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@14c # SKIP
1159 08:08:13.173501 # ok 21 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@18 # SKIP
1160 08:08:13.246756 # ok 22 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@1c # SKIP
1161 08:08:13.324462 # ok 23 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@24 # SKIP
1162 08:08:13.393276 # ok 24 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@38 # SKIP
1163 08:08:13.466019 # ok 25 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@e8 # SKIP
1164 08:08:13.543357 # ok 26 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400 # SKIP
1165 08:08:13.617361 # ok 27 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@0 # SKIP
1166 08:08:13.689121 # ok 28 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@14 # SKIP
1167 08:08:13.761361 # ok 29 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@b0 # SKIP
1168 08:08:13.831171 # ok 30 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600 # SKIP
1169 08:08:13.905582 # ok 31 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600/clock@0 # SKIP
1170 08:08:13.977813 # ok 32 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800 # SKIP
1171 08:08:14.051531 # ok 33 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800/clock@0 # SKIP
1172 08:08:14.123051 # ok 34 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900 # SKIP
1173 08:08:14.196616 # ok 35 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900/clock@0 # SKIP
1174 08:08:14.269401 # ok 36 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00 # SKIP
1175 08:08:14.343201 # ok 37 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00/clock@0 # SKIP
1176 08:08:14.416254 # ok 38 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-24mhz # SKIP
1177 08:08:14.490725 # ok 39 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-32768 # SKIP
1178 08:08:14.563419 # ok 40 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-rc32k # SKIP
1179 08:08:14.636212 # ok 41 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clkdiv32k # SKIP
1180 08:08:14.710233 # ok 42 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-125mhz-gclk # SKIP
1181 08:08:14.782747 # ok 43 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-cpts-rft@520 # SKIP
1182 08:08:14.856796 # ok 44 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4-div2 # SKIP
1183 08:08:14.930053 # ok 45 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4@480 # SKIP
1184 08:08:15.007003 # ok 46 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m5@484 # SKIP
1185 08:08:15.080095 # ok 47 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m6@4d8 # SKIP
1186 08:08:15.150825 # ok 48 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-x2 # SKIP
1187 08:08:15.223069 # ok 49 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2-div2 # SKIP
1188 08:08:15.296663 # ok 50 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2@4a0 # SKIP
1189 08:08:15.373058 # ok 51 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-disp-m2@4a4 # SKIP
1190 08:08:15.444335 # ok 52 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-mpu-m2@4a8 # SKIP
1191 08:08:15.518506 # ok 53 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4 # SKIP
1192 08:08:15.597625 # ok 54 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4-wkupdm # SKIP
1193 08:08:15.669986 # ok 55 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2@4ac # SKIP
1194 08:08:15.740411 # ok 56 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-gpio0-dbclk-mux@53c # SKIP
1195 08:08:15.813127 # ok 57 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-ieee5000-fck-1@e4 # SKIP
1196 08:08:15.886077 # ok 58 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3-gclk # SKIP
1197 08:08:15.966096 # ok 59 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3s-gclk # SKIP
1198 08:08:16.039498 # ok 60 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4-rtc-gclk # SKIP
1199 08:08:16.109468 # ok 61 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4fw-gclk # SKIP
1200 08:08:16.187254 # ok 62 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4hs-gclk # SKIP
1201 08:08:16.259557 # ok 63 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4ls-gclk # SKIP
1202 08:08:16.332983 # ok 64 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-lcd-gclk@534 # SKIP
1203 08:08:16.406262 # ok 65 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmc # SKIP
1204 08:08:16.481112 # ok 66 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmu-fck-1@914 # SKIP
1205 08:08:16.555201 # ok 67 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-pruss-ocp-gclk@530 # SKIP
1206 08:08:16.627410 # ok 68 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-sysclk-div # SKIP
1207 08:08:16.705722 # ok 69 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-tclkin # SKIP
1208 08:08:16.784745 # ok 70 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer1-fck@528 # SKIP
1209 08:08:16.854816 # ok 71 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer2-fck@508 # SKIP
1210 08:08:16.928344 # ok 72 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer3-fck@50c # SKIP
1211 08:08:17.006519 # ok 73 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer4-fck@510 # SKIP
1212 08:08:17.079866 # ok 74 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer5-fck@518 # SKIP
1213 08:08:17.149600 # ok 75 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer6-fck@51c # SKIP
1214 08:08:17.227385 # ok 76 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer7-fck@504 # SKIP
1215 08:08:17.299926 # ok 77 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-usbotg-fck-8@47c # SKIP
1216 08:08:17.372781 # ok 78 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-19200000 # SKIP
1217 08:08:17.442644 # ok 79 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-24000000 # SKIP
1218 08:08:17.516644 # ok 80 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-25000000 # SKIP
1219 08:08:17.593890 # ok 81 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-26000000 # SKIP
1220 08:08:17.664222 # ok 82 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-wdt1-fck@538 # SKIP
1221 08:08:17.736647 # ok 83 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@488 # SKIP
1222 08:08:17.810182 # ok 84 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@48c # SKIP
1223 08:08:17.882986 # ok 85 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@490 # SKIP
1224 08:08:17.958354 # ok 86 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@494 # SKIP
1225 08:08:18.034841 # ok 87 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@498 # SKIP
1226 08:08:18.108794 # ok 88 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c # SKIP
1227 08:08:18.179659 # ok 89 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fck-div@0 # SKIP
1228 08:08:18.254459 # ok 90 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fclk-clksel@1 # SKIP
1229 08:08:18.325329 # ok 91 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700 # SKIP
1230 08:08:18.402110 # ok 92 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2-div@3 # SKIP
1231 08:08:18.473722 # ok 93 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2@7 # SKIP
1232 08:08:18.548425 # ok 94 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-sysclkout-pre@0 # SKIP
1233 08:08:18.569896 # ok 95 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1000
1234 08:08:18.593876 # ok 96 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1100
1235 08:08:18.623922 # ok 97 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1200
1236 08:08:18.647532 # ok 98 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@c00
1237 08:08:18.668242 # ok 99 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@d00
1238 08:08:18.692532 # ok 100 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@e00
1239 08:08:18.716527 # ok 101 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@f00
1240 08:08:18.739018 # ok 102 /ocp/interconnect@44c00000/segment@200000/target-module@10000
1241 08:08:18.851671 # not ok 103 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0
1242 08:08:18.877558 # ok 104 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/control@620
1243 08:08:18.902712 # ok 105 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/dma-router@f90
1244 08:08:18.926699 # ok 106 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800
1245 08:08:19.034292 # not ok 107 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0
1246 08:08:19.110951 # ok 108 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-adc-tsc-fck # SKIP
1247 08:08:19.180454 # ok 109 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-aes0-fck # SKIP
1248 08:08:19.253410 # ok 110 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan0-fck # SKIP
1249 08:08:19.327760 # ok 111 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan1-fck # SKIP
1250 08:08:19.406430 # ok 112 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp0-fck # SKIP
1251 08:08:19.476013 # ok 113 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp1-fck # SKIP
1252 08:08:19.553865 # ok 114 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-rng-fck # SKIP
1253 08:08:19.624032 # ok 115 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sha0-fck # SKIP
1254 08:08:19.697907 # ok 116 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex0-fck # SKIP
1255 08:08:19.775401 # ok 117 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex1-fck # SKIP
1256 08:08:19.845620 # ok 118 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sys-clkin-22@40 # SKIP
1257 08:08:19.918522 # ok 119 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664 # SKIP
1258 08:08:19.998651 # ok 120 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm0-tbclk@0 # SKIP
1259 08:08:20.071134 # ok 121 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm1-tbclk@1 # SKIP
1260 08:08:20.142179 # ok 122 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm2-tbclk@2 # SKIP
1261 08:08:20.164021 # ok 123 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/phy-gmii-sel
1262 08:08:20.235518 # not ok 124 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/wkup_m3_ipc@1324
1263 08:08:20.306351 # not ok 125 /ocp/interconnect@44c00000/segment@200000/target-module@31000
1264 08:08:20.380361 # ok 126 /ocp/interconnect@44c00000/segment@200000/target-module@31000/timer@0 # SKIP
1265 08:08:20.402255 # ok 127 /ocp/interconnect@44c00000/segment@200000/target-module@35000
1266 08:08:20.475648 # not ok 128 /ocp/interconnect@44c00000/segment@200000/target-module@35000/wdt@0
1267 08:08:20.503064 # ok 129 /ocp/interconnect@44c00000/segment@200000/target-module@3e000
1268 08:08:20.576083 # not ok 130 /ocp/interconnect@44c00000/segment@200000/target-module@3e000/rtc@0
1269 08:08:20.596497 # ok 131 /ocp/interconnect@44c00000/segment@200000/target-module@7000
1270 08:08:20.619582 # ok 132 /ocp/interconnect@44c00000/segment@200000/target-module@7000/gpio@0
1271 08:08:20.642333 # ok 133 /ocp/interconnect@44c00000/segment@200000/target-module@9000
1272 08:08:20.672116 # ok 134 /ocp/interconnect@44c00000/segment@200000/target-module@9000/serial@0
1273 08:08:20.690967 # ok 135 /ocp/interconnect@44c00000/segment@200000/target-module@b000
1274 08:08:20.715367 # ok 136 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0
1275 08:08:20.741035 # ok 137 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/eeprom@50
1276 08:08:20.819662 # ok 138 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/eeprom@50/nvmem-layout # SKIP
1277 08:08:20.838841 # ok 139 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
1278 08:08:20.862549 # ok 140 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24
1279 08:08:20.935883 # not ok 141 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/charger
1280 08:08:21.008276 # not ok 142 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/pwrbutton
1281 08:08:21.034617 # ok 143 /ocp/interconnect@44c00000/segment@200000/target-module@d000
1282 08:08:21.133983 # not ok 144 /ocp/interconnect@47c00000
1283 08:08:21.210932 # not ok 145 /ocp/interconnect@47c00000/segment@0
1284 08:08:21.232254 # ok 146 /ocp/interconnect@48000000
1285 08:08:21.250803 # ok 147 /ocp/interconnect@48000000/segment@0
1286 08:08:21.277182 # ok 148 /ocp/interconnect@48000000/segment@0/target-module@22000
1287 08:08:21.305022 # ok 149 /ocp/interconnect@48000000/segment@0/target-module@24000
1288 08:08:21.326227 # ok 150 /ocp/interconnect@48000000/segment@0/target-module@2a000
1289 08:08:21.352523 # ok 151 /ocp/interconnect@48000000/segment@0/target-module@30000
1290 08:08:21.376012 # ok 152 /ocp/interconnect@48000000/segment@0/target-module@38000
1291 08:08:21.395667 # ok 153 /ocp/interconnect@48000000/segment@0/target-module@38000/mcasp@0
1292 08:08:21.418537 # ok 154 /ocp/interconnect@48000000/segment@0/target-module@3c000
1293 08:08:21.496338 # not ok 155 /ocp/interconnect@48000000/segment@0/target-module@40000
1294 08:08:21.565708 # ok 156 /ocp/interconnect@48000000/segment@0/target-module@40000/timer@0 # SKIP
1295 08:08:21.587493 # ok 157 /ocp/interconnect@48000000/segment@0/target-module@42000
1296 08:08:21.612665 # ok 158 /ocp/interconnect@48000000/segment@0/target-module@42000/timer@0
1297 08:08:21.635587 # ok 159 /ocp/interconnect@48000000/segment@0/target-module@44000
1298 08:08:21.660535 # ok 160 /ocp/interconnect@48000000/segment@0/target-module@44000/timer@0
1299 08:08:21.683356 # ok 161 /ocp/interconnect@48000000/segment@0/target-module@46000
1300 08:08:21.712536 # ok 162 /ocp/interconnect@48000000/segment@0/target-module@46000/timer@0
1301 08:08:21.736120 # ok 163 /ocp/interconnect@48000000/segment@0/target-module@48000
1302 08:08:21.755676 # ok 164 /ocp/interconnect@48000000/segment@0/target-module@48000/timer@0
1303 08:08:21.785007 # ok 165 /ocp/interconnect@48000000/segment@0/target-module@4a000
1304 08:08:21.809970 # ok 166 /ocp/interconnect@48000000/segment@0/target-module@4a000/timer@0
1305 08:08:21.828926 # ok 167 /ocp/interconnect@48000000/segment@0/target-module@4c000
1306 08:08:21.853190 # ok 168 /ocp/interconnect@48000000/segment@0/target-module@4c000/gpio@0
1307 08:08:21.876257 # ok 169 /ocp/interconnect@48000000/segment@0/target-module@60000
1308 08:08:21.905979 # ok 170 /ocp/interconnect@48000000/segment@0/target-module@60000/mmc@0
1309 08:08:21.927611 # ok 171 /ocp/interconnect@48000000/segment@0/target-module@c8000
1310 08:08:21.949245 # ok 172 /ocp/interconnect@48000000/segment@0/target-module@c8000/mailbox@0
1311 08:08:21.972562 # ok 173 /ocp/interconnect@48000000/segment@0/target-module@ca000
1312 08:08:21.998874 # ok 174 /ocp/interconnect@48000000/segment@0/target-module@ca000/spinlock@0
1313 08:08:22.022911 # ok 175 /ocp/interconnect@48000000/segment@100000
1314 08:08:22.046655 # ok 176 /ocp/interconnect@48000000/segment@100000/target-module@9c000
1315 08:08:22.069367 # ok 177 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0
1316 08:08:22.143457 # not ok 178 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/eeprom@54
1317 08:08:22.218370 # ok 179 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/eeprom@54/nvmem-layout # SKIP
1318 08:08:22.289295 # not ok 180 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/eeprom@55
1319 08:08:22.364503 # ok 181 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/eeprom@55/nvmem-layout # SKIP
1320 08:08:22.434576 # not ok 182 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/eeprom@56
1321 08:08:22.513837 # ok 183 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/eeprom@56/nvmem-layout # SKIP
1322 08:08:22.582430 # not ok 184 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/eeprom@57
1323 08:08:22.659408 # ok 185 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/eeprom@57/nvmem-layout # SKIP
1324 08:08:22.678267 # ok 186 /ocp/interconnect@48000000/segment@100000/target-module@a0000
1325 08:08:22.703492 # ok 187 /ocp/interconnect@48000000/segment@100000/target-module@a6000
1326 08:08:22.725575 # ok 188 /ocp/interconnect@48000000/segment@100000/target-module@a8000
1327 08:08:22.748770 # ok 189 /ocp/interconnect@48000000/segment@100000/target-module@aa000
1328 08:08:22.776445 # ok 190 /ocp/interconnect@48000000/segment@100000/target-module@ac000
1329 08:08:22.798796 # ok 191 /ocp/interconnect@48000000/segment@100000/target-module@ac000/gpio@0
1330 08:08:22.821921 # ok 192 /ocp/interconnect@48000000/segment@100000/target-module@ae000
1331 08:08:22.846225 # ok 193 /ocp/interconnect@48000000/segment@100000/target-module@ae000/gpio@0
1332 08:08:22.869626 # ok 194 /ocp/interconnect@48000000/segment@100000/target-module@cc000
1333 08:08:22.892866 # ok 195 /ocp/interconnect@48000000/segment@100000/target-module@d0000
1334 08:08:22.921873 # ok 196 /ocp/interconnect@48000000/segment@100000/target-module@d8000
1335 08:08:22.941881 # ok 197 /ocp/interconnect@48000000/segment@100000/target-module@d8000/mmc@0
1336 08:08:22.961438 # ok 198 /ocp/interconnect@48000000/segment@200000
1337 08:08:22.989021 # ok 199 /ocp/interconnect@48000000/segment@200000/target-module@0
1338 08:08:23.066184 # ok 200 /ocp/interconnect@48000000/segment@200000/target-module@0/mpu@0 # SKIP
1339 08:08:23.084823 # ok 201 /ocp/interconnect@48000000/segment@300000
1340 08:08:23.108216 # ok 202 /ocp/interconnect@48000000/segment@300000/target-module@0
1341 08:08:23.135926 # ok 203 /ocp/interconnect@48000000/segment@300000/target-module@10000
1342 08:08:23.156817 # ok 204 /ocp/interconnect@48000000/segment@300000/target-module@10000/rng@0
1343 08:08:23.183878 # ok 205 /ocp/interconnect@48000000/segment@300000/target-module@2000
1344 08:08:23.205346 # ok 206 /ocp/interconnect@48000000/segment@300000/target-module@4000
1345 08:08:23.230649 # ok 207 /ocp/interconnect@48000000/segment@300000/target-module@e000
1346 08:08:23.300895 # not ok 208 /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
1347 08:08:23.319313 # ok 209 /ocp/interconnect@4a000000
1348 08:08:23.344494 # ok 210 /ocp/interconnect@4a000000/segment@0
1349 08:08:23.368517 # ok 211 /ocp/interconnect@4a000000/segment@0/target-module@100000
1350 08:08:23.392357 # ok 212 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0
1351 08:08:23.418538 # ok 213 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0/mdio@1000
1352 08:08:23.440272 # ok 214 /ocp/interconnect@4a000000/segment@0/target-module@300000
1353 08:08:23.516485 # not ok 215 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0
1354 08:08:23.621539 # ok 216 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/cfg@26000 # SKIP
1355 08:08:23.697826 # not ok 217 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/interrupt-controller@20000
1356 08:08:23.805504 # ok 218 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/mii-rt@32000 # SKIP
1357 08:08:23.876776 # not ok 219 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@34000
1358 08:08:24.208750 # not ok 220 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@38000
1359 08:08:24.209976 # not ok 221 /ocp/interconnect@4b140000
1360 08:08:24.210476 # not ok 222 /ocp/interconnect@4b140000/segment@0
1361 08:08:24.210988 # ok 223 /ocp/interrupt-controller@48200000 # SKIP
1362 08:08:24.213840 # ok 224 /ocp/target-module@40300000
1363 08:08:24.241370 # ok 225 /ocp/target-module@40300000/sram@0
1364 08:08:24.316189 # ok 226 /ocp/target-module@40300000/sram@0/pm-code-sram@0 # SKIP
1365 08:08:24.390219 # ok 227 /ocp/target-module@40300000/sram@0/pm-data-sram@1000 # SKIP
1366 08:08:24.410617 # ok 228 /ocp/target-module@47400000
1367 08:08:24.435260 # ok 229 /ocp/target-module@47400000/dma-controller@2000
1368 08:08:24.457072 # ok 230 /ocp/target-module@47400000/usb-phy@1300
1369 08:08:24.482115 # ok 231 /ocp/target-module@47400000/usb-phy@1b00
1370 08:08:24.504265 # ok 232 /ocp/target-module@47400000/usb@1400
1371 08:08:24.530540 # ok 233 /ocp/target-module@47400000/usb@1800
1372 08:08:24.545901 # ok 234 /ocp/target-module@47810000
1373 08:08:24.569356 # ok 235 /ocp/target-module@49000000
1374 08:08:24.594046 # ok 236 /ocp/target-module@49000000/dma@0
1375 08:08:24.615118 # ok 237 /ocp/target-module@49800000
1376 08:08:24.638258 # ok 238 /ocp/target-module@49800000/dma@0
1377 08:08:24.663382 # ok 239 /ocp/target-module@49900000
1378 08:08:24.688027 # ok 240 /ocp/target-module@49900000/dma@0
1379 08:08:24.711147 # ok 241 /ocp/target-module@49a00000
1380 08:08:24.734079 # ok 242 /ocp/target-module@49a00000/dma@0
1381 08:08:24.760054 # ok 243 /ocp/target-module@4c000000
1382 08:08:24.827230 # not ok 244 /ocp/target-module@4c000000/emif@0
1383 08:08:24.848593 # ok 245 /ocp/target-module@50000000
1384 08:08:24.873324 # ok 246 /ocp/target-module@53100000
1385 08:08:24.946604 # not ok 247 /ocp/target-module@53100000/sham@0
1386 08:08:24.970507 # ok 248 /ocp/target-module@53500000
1387 08:08:25.044792 # not ok 249 /ocp/target-module@53500000/aes@0
1388 08:08:25.060685 # ok 250 /ocp/target-module@56000000
1389 08:08:25.171619 # ok 251 /ocp/target-module@56000000/gpu@0 # SKIP
1390 08:08:25.237226 # ok 252 /opp-table # SKIP
1391 08:08:25.311969 # ok 253 /soc # SKIP
1392 08:08:25.329011 # ok 254 /sound
1393 08:08:25.358682 # ok 255 /target-module@4b000000
1394 08:08:25.378829 # ok 256 /target-module@4b000000/target-module@140000
1395 08:08:25.400694 # ok 257 /target-module@4b000000/target-module@140000/pmu@0
1396 08:08:25.409020 # # Totals: pass:117 fail:27 xfail:0 xpass:0 skip:113 error:0
1397 08:08:25.417407 not ok 1 selftests: dt: test_unprobed_devices.sh # exit=1
1398 08:08:27.528112 dt_test_unprobed_devices_sh_ skip
1399 08:08:27.533536 dt_test_unprobed_devices_sh_clk_mcasp0 pass
1400 08:08:27.539174 dt_test_unprobed_devices_sh_clk_mcasp0_fixed skip
1401 08:08:27.539701 dt_test_unprobed_devices_sh_cpus_cpu_0 skip
1402 08:08:27.544963 dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate skip
1403 08:08:27.550306 dt_test_unprobed_devices_sh_fixedregulator0 pass
1404 08:08:27.555953 dt_test_unprobed_devices_sh_leds pass
1405 08:08:27.556587 dt_test_unprobed_devices_sh_ocp pass
1406 08:08:27.561424 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 pass
1407 08:08:27.567064 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 pass
1408 08:08:27.572735 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 pass
1409 08:08:27.583873 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 pass
1410 08:08:27.589443 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 fail
1411 08:08:27.595052 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 pass
1412 08:08:27.606258 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 pass
1413 08:08:27.611916 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 fail
1414 08:08:27.623127 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 skip
1415 08:08:27.634300 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 skip
1416 08:08:27.645819 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 skip
1417 08:08:27.651072 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c skip
1418 08:08:27.662322 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 skip
1419 08:08:27.673587 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c skip
1420 08:08:27.684721 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 skip
1421 08:08:27.695905 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 skip
1422 08:08:27.701680 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 skip
1423 08:08:27.712676 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 skip
1424 08:08:27.723859 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 skip
1425 08:08:27.735174 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 skip
1426 08:08:27.746330 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 skip
1427 08:08:27.751920 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 skip
1428 08:08:27.763057 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 skip
1429 08:08:27.774229 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 skip
1430 08:08:27.785467 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 skip
1431 08:08:27.791070 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 skip
1432 08:08:27.802232 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 skip
1433 08:08:27.813407 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 skip
1434 08:08:27.824758 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 skip
1435 08:08:27.835785 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz skip
1436 08:08:27.841443 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 skip
1437 08:08:27.852594 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k skip
1438 08:08:27.863795 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k skip
1439 08:08:27.874979 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk skip
1440 08:08:27.886181 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 skip
1441 08:08:27.897382 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 skip
1442 08:08:27.908773 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 skip
1443 08:08:27.919764 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 skip
1444 08:08:27.930933 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 skip
1445 08:08:27.942197 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 skip
1446 08:08:27.953375 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 skip
1447 08:08:27.964636 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 skip
1448 08:08:27.975755 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 skip
1449 08:08:27.986922 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 skip
1450 08:08:27.998346 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 skip
1451 08:08:28.009389 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm skip
1452 08:08:28.020630 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac skip
1453 08:08:28.031702 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c skip
1454 08:08:28.042877 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 skip
1455 08:08:28.054068 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk skip
1456 08:08:28.065266 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk skip
1457 08:08:28.076444 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk skip
1458 08:08:28.087874 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk skip
1459 08:08:28.098830 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk skip
1460 08:08:28.110023 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk skip
1461 08:08:28.121222 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 skip
1462 08:08:28.126885 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc skip
1463 08:08:28.138008 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 skip
1464 08:08:28.149198 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 skip
1465 08:08:28.160432 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div skip
1466 08:08:28.171627 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin skip
1467 08:08:28.182896 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 skip
1468 08:08:28.194146 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 skip
1469 08:08:28.205285 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c skip
1470 08:08:28.216378 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 skip
1471 08:08:28.227644 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 skip
1472 08:08:28.238769 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c skip
1473 08:08:28.249983 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 skip
1474 08:08:28.261154 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c skip
1475 08:08:28.272404 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 skip
1476 08:08:28.283648 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 skip
1477 08:08:28.294717 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 skip
1478 08:08:28.305903 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 skip
1479 08:08:28.317081 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 skip
1480 08:08:28.322766 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 skip
1481 08:08:28.333874 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c skip
1482 08:08:28.345264 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 skip
1483 08:08:28.356312 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 skip
1484 08:08:28.367456 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 skip
1485 08:08:28.373167 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c skip
1486 08:08:28.389820 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 skip
1487 08:08:28.401074 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 skip
1488 08:08:28.406745 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 skip
1489 08:08:28.423441 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 skip
1490 08:08:28.434737 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 skip
1491 08:08:28.445903 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 skip
1492 08:08:28.451561 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 pass
1493 08:08:28.462705 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 pass
1494 08:08:28.473871 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 pass
1495 08:08:28.479536 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 pass
1496 08:08:28.490685 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 pass
1497 08:08:28.501895 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 pass
1498 08:08:28.507582 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 pass
1499 08:08:28.518727 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 pass
1500 08:08:28.524376 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 fail
1501 08:08:28.535493 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 pass
1502 08:08:28.546691 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 pass
1503 08:08:28.557866 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 pass
1504 08:08:28.569071 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 fail
1505 08:08:28.580394 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck skip
1506 08:08:28.591493 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck skip
1507 08:08:28.602693 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck skip
1508 08:08:28.613880 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck skip
1509 08:08:28.625144 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck skip
1510 08:08:28.636340 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck skip
1511 08:08:28.647521 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck skip
1512 08:08:28.658744 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck skip
1513 08:08:28.675742 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck skip
1514 08:08:28.686781 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck skip
1515 08:08:28.697916 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 skip
1516 08:08:28.709130 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 skip
1517 08:08:28.720304 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 skip
1518 08:08:28.737121 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 skip
1519 08:08:28.748329 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 skip
1520 08:08:28.759462 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel pass
1521 08:08:28.770773 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 fail
1522 08:08:28.776371 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 fail
1523 08:08:28.787512 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 skip
1524 08:08:28.798776 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 pass
1525 08:08:28.804357 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 fail
1526 08:08:28.815497 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 pass
1527 08:08:28.821118 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 fail
1528 08:08:28.832356 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 pass
1529 08:08:28.837968 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 pass
1530 08:08:28.849121 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 pass
1531 08:08:28.854787 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 pass
1532 08:08:28.865976 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 pass
1533 08:08:28.871587 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 pass
1534 08:08:28.882792 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_eeprom_50 pass
1535 08:08:28.893979 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_eeprom_50_nvmem-layout skip
1536 08:08:28.905234 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 pass
1537 08:08:28.910787 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 pass
1538 08:08:28.921909 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger fail
1539 08:08:28.933225 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton fail
1540 08:08:28.939382 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 pass
1541 08:08:28.945427 dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 fail
1542 08:08:28.955568 dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 fail
1543 08:08:28.956196 dt_test_unprobed_devices_sh_ocp_interconnect_48000000 pass
1544 08:08:28.966789 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 pass
1545 08:08:28.972350 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 pass
1546 08:08:28.977926 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 pass
1547 08:08:28.989062 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 pass
1548 08:08:28.994784 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 pass
1549 08:08:29.005942 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 pass
1550 08:08:29.011563 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 pass
1551 08:08:29.022827 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 pass
1552 08:08:29.028342 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 fail
1553 08:08:29.033856 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 skip
1554 08:08:29.044994 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 pass
1555 08:08:29.050637 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 pass
1556 08:08:29.061924 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 pass
1557 08:08:29.067476 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 pass
1558 08:08:29.078581 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 pass
1559 08:08:29.084273 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 pass
1560 08:08:29.095604 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 pass
1561 08:08:29.101122 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 pass
1562 08:08:29.112268 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 pass
1563 08:08:29.117885 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 pass
1564 08:08:29.129044 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 pass
1565 08:08:29.134821 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 pass
1566 08:08:29.140327 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 pass
1567 08:08:29.151407 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 pass
1568 08:08:29.157070 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 pass
1569 08:08:29.168269 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 pass
1570 08:08:29.173866 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 pass
1571 08:08:29.185000 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 pass
1572 08:08:29.190650 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 pass
1573 08:08:29.201843 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 pass
1574 08:08:29.207395 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 pass
1575 08:08:29.218605 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_54 fail
1576 08:08:29.229794 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_54_nvmem-layout skip
1577 08:08:29.241069 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_55 fail
1578 08:08:29.252184 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_55_nvmem-layout skip
1579 08:08:29.257818 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_56 fail
1580 08:08:29.268974 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_56_nvmem-layout skip
1581 08:08:29.280217 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_57 fail
1582 08:08:29.291341 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_57_nvmem-layout skip
1583 08:08:29.296969 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 pass
1584 08:08:29.308193 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 pass
1585 08:08:29.313776 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 pass
1586 08:08:29.324899 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 pass
1587 08:08:29.330510 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 pass
1588 08:08:29.342013 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 pass
1589 08:08:29.347519 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 pass
1590 08:08:29.358599 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 pass
1591 08:08:29.364158 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 pass
1592 08:08:29.375271 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 pass
1593 08:08:29.380888 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 pass
1594 08:08:29.392091 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 pass
1595 08:08:29.397686 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 pass
1596 08:08:29.408861 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 pass
1597 08:08:29.414487 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 skip
1598 08:08:29.420081 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 pass
1599 08:08:29.431188 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 pass
1600 08:08:29.436950 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 pass
1601 08:08:29.448068 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 pass
1602 08:08:29.453671 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 pass
1603 08:08:29.464828 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 pass
1604 08:08:29.470466 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 pass
1605 08:08:29.481643 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 fail
1606 08:08:29.487243 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 pass
1607 08:08:29.492903 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 pass
1608 08:08:29.498443 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 pass
1609 08:08:29.509582 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 pass
1610 08:08:29.515209 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 pass
1611 08:08:29.526414 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 pass
1612 08:08:29.532074 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 fail
1613 08:08:29.543134 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 skip
1614 08:08:29.554358 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 fail
1615 08:08:29.565584 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 skip
1616 08:08:29.576857 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 fail
1617 08:08:29.582394 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 fail
1618 08:08:29.588047 dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 fail
1619 08:08:29.593640 dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 fail
1620 08:08:29.599285 dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 skip
1621 08:08:29.604882 dt_test_unprobed_devices_sh_ocp_target-module_40300000 pass
1622 08:08:29.610435 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 pass
1623 08:08:29.621566 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 skip
1624 08:08:29.627217 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 skip
1625 08:08:29.632905 dt_test_unprobed_devices_sh_ocp_target-module_47400000 pass
1626 08:08:29.638395 dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 pass
1627 08:08:29.644028 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 pass
1628 08:08:29.655199 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 pass
1629 08:08:29.660903 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 pass
1630 08:08:29.666399 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 pass
1631 08:08:29.672068 dt_test_unprobed_devices_sh_ocp_target-module_47810000 pass
1632 08:08:29.677668 dt_test_unprobed_devices_sh_ocp_target-module_49000000 pass
1633 08:08:29.683258 dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 pass
1634 08:08:29.688893 dt_test_unprobed_devices_sh_ocp_target-module_49800000 pass
1635 08:08:29.694480 dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 pass
1636 08:08:29.700078 dt_test_unprobed_devices_sh_ocp_target-module_49900000 pass
1637 08:08:29.705662 dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 pass
1638 08:08:29.711260 dt_test_unprobed_devices_sh_ocp_target-module_49a00000 pass
1639 08:08:29.716936 dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 pass
1640 08:08:29.722445 dt_test_unprobed_devices_sh_ocp_target-module_4c000000 pass
1641 08:08:29.728041 dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 fail
1642 08:08:29.733626 dt_test_unprobed_devices_sh_ocp_target-module_50000000 pass
1643 08:08:29.739262 dt_test_unprobed_devices_sh_ocp_target-module_53100000 pass
1644 08:08:29.744936 dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 fail
1645 08:08:29.750445 dt_test_unprobed_devices_sh_ocp_target-module_53500000 pass
1646 08:08:29.756079 dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 fail
1647 08:08:29.761678 dt_test_unprobed_devices_sh_ocp_target-module_56000000 pass
1648 08:08:29.767242 dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 skip
1649 08:08:29.767793 dt_test_unprobed_devices_sh_opp-table skip
1650 08:08:29.772942 dt_test_unprobed_devices_sh_soc skip
1651 08:08:29.778444 dt_test_unprobed_devices_sh_sound pass
1652 08:08:29.778974 dt_test_unprobed_devices_sh_target-module_4b000000 pass
1653 08:08:29.789639 dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 pass
1654 08:08:29.795259 dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 pass
1655 08:08:29.800977 dt_test_unprobed_devices_sh fail
1656 08:08:29.801538 + ../../utils/send-to-lava.sh ./output/result.txt
1657 08:08:29.808410 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-dt RESULT=pass>
1658 08:08:29.809447 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-dt RESULT=pass
1660 08:08:29.829222 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip>
1661 08:08:29.830079 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip
1663 08:08:29.916019 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass>
1664 08:08:29.916968 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass
1666 08:08:30.007785 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip>
1667 08:08:30.008747 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip
1669 08:08:30.099041 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip>
1670 08:08:30.100024 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip
1672 08:08:30.189956 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip>
1673 08:08:30.190583 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip
1675 08:08:30.274399 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass>
1676 08:08:30.275322 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass
1678 08:08:30.361169 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass>
1679 08:08:30.362113 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass
1681 08:08:30.453191 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass>
1682 08:08:30.454092 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass
1684 08:08:30.541621 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass>
1685 08:08:30.542523 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass
1687 08:08:30.628876 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass>
1688 08:08:30.630073 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass
1690 08:08:30.718134 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass>
1691 08:08:30.719035 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass
1693 08:08:30.813166 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass>
1694 08:08:30.814052 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass
1696 08:08:30.905587 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail>
1697 08:08:30.906446 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail
1699 08:08:30.989401 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass>
1700 08:08:30.990073 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass
1702 08:08:31.078209 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass>
1703 08:08:31.079112 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass
1705 08:08:31.171692 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail>
1706 08:08:31.172589 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail
1708 08:08:31.264910 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip>
1709 08:08:31.265778 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip
1711 08:08:31.359167 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip>
1712 08:08:31.360087 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip
1714 08:08:31.447184 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip>
1715 08:08:31.448077 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip
1717 08:08:31.539942 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip>
1718 08:08:31.540833 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip
1720 08:08:31.627869 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip>
1721 08:08:31.628804 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip
1723 08:08:31.715206 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip>
1724 08:08:31.716084 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip
1726 08:08:31.807061 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip>
1727 08:08:31.807926 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip
1729 08:08:31.900724 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip>
1730 08:08:31.901648 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip
1732 08:08:31.988424 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip>
1733 08:08:31.989441 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip
1735 08:08:32.081599 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip>
1736 08:08:32.083134 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip
1738 08:08:32.174422 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip>
1739 08:08:32.175222 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip
1741 08:08:32.267072 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip>
1742 08:08:32.267875 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip
1744 08:08:32.355412 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip>
1745 08:08:32.356227 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip
1747 08:08:32.447277 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip>
1748 08:08:32.448079 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip
1750 08:08:32.540646 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip>
1751 08:08:32.541486 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip
1753 08:08:32.627631 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip>
1754 08:08:32.628495 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip
1756 08:08:32.716206 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip>
1757 08:08:32.716993 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip
1759 08:08:32.808680 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip>
1760 08:08:32.809475 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip
1762 08:08:32.896674 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip>
1763 08:08:32.897456 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip
1765 08:08:32.982575 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip>
1766 08:08:32.983343 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip
1768 08:08:33.072938 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip>
1769 08:08:33.073704 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip
1771 08:08:33.161786 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip>
1772 08:08:33.162571 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip
1774 08:08:33.255380 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip>
1775 08:08:33.256135 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip
1777 08:08:33.349705 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip>
1778 08:08:33.350518 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip
1780 08:08:33.442088 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip>
1781 08:08:33.442903 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip
1783 08:08:33.529948 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip>
1784 08:08:33.530784 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip
1786 08:08:33.622149 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip>
1787 08:08:33.622947 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip
1789 08:08:33.710574 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip>
1790 08:08:33.711476 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip
1792 08:08:33.804090 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip>
1793 08:08:33.804899 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip
1795 08:08:33.891378 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip>
1796 08:08:33.892235 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip
1798 08:08:33.983442 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip>
1799 08:08:33.984336 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip
1801 08:08:34.075131 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip>
1802 08:08:34.076045 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip
1804 08:08:34.166290 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip>
1805 08:08:34.167087 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip
1807 08:08:34.252309 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip>
1808 08:08:34.253116 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip
1810 08:08:34.346059 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip>
1811 08:08:34.347019 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip
1813 08:08:34.438050 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip>
1814 08:08:34.438963 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip
1816 08:08:34.526431 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip>
1817 08:08:34.527313 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip
1819 08:08:34.617832 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip>
1820 08:08:34.618752 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip
1822 08:08:34.706771 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip>
1823 08:08:34.707641 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip
1825 08:08:34.800097 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip>
1826 08:08:34.800964 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip
1828 08:08:34.889978 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip>
1829 08:08:34.890815 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip
1831 08:08:34.982007 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip>
1832 08:08:34.982841 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip
1834 08:08:35.075613 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip>
1835 08:08:35.076879 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip
1837 08:08:35.168410 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip>
1838 08:08:35.169491 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip
1840 08:08:35.253968 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip>
1841 08:08:35.255013 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip
1843 08:08:35.340057 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip>
1844 08:08:35.341099 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip
1846 08:08:35.427621 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip>
1847 08:08:35.428721 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip
1849 08:08:35.519398 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip>
1850 08:08:35.520428 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip
1852 08:08:35.605112 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip>
1853 08:08:35.606248 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip
1855 08:08:35.700676 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip>
1856 08:08:35.701777 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip
1858 08:08:35.794142 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip>
1859 08:08:35.795128 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip
1861 08:08:35.888471 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip>
1862 08:08:35.889447 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip
1864 08:08:35.979896 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip>
1865 08:08:35.980828 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip
1867 08:08:36.068654 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip>
1868 08:08:36.069587 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip
1870 08:08:36.154786 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip>
1871 08:08:36.155672 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip
1873 08:08:36.242256 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip>
1874 08:08:36.243154 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip
1876 08:08:36.335977 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip>
1877 08:08:36.337003 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip
1879 08:08:36.428225 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip>
1880 08:08:36.429206 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip
1882 08:08:36.521055 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip>
1883 08:08:36.522076 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip
1885 08:08:36.608241 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip>
1886 08:08:36.609040 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip
1888 08:08:36.696112 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip>
1889 08:08:36.696969 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip
1891 08:08:36.787192 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip>
1892 08:08:36.787945 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip
1894 08:08:36.873584 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip>
1895 08:08:36.874324 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip
1897 08:08:36.959613 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip>
1898 08:08:36.960488 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip
1900 08:08:37.046641 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip>
1901 08:08:37.047587 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip
1903 08:08:37.134565 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip>
1904 08:08:37.135332 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip
1906 08:08:37.227782 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip>
1907 08:08:37.228612 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip
1909 08:08:37.320653 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip>
1910 08:08:37.321700 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip
1912 08:08:37.407402 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip>
1913 08:08:37.408521 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip
1915 08:08:37.495244 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip>
1916 08:08:37.496170 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip
1918 08:08:37.586771 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip>
1919 08:08:37.587612 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip
1921 08:08:37.672649 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip>
1922 08:08:37.673495 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip
1924 08:08:37.765663 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip>
1925 08:08:37.766444 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip
1927 08:08:37.853209 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip>
1928 08:08:37.854026 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip
1930 08:08:37.937284 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip>
1931 08:08:37.938106 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip
1933 08:08:38.024987 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip>
1934 08:08:38.025841 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip
1936 08:08:38.111553 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip>
1937 08:08:38.112428 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip
1939 08:08:38.199582 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip>
1940 08:08:38.200433 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip
1942 08:08:38.286000 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass>
1943 08:08:38.286846 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass
1945 08:08:38.377430 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass>
1946 08:08:38.378339 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass
1948 08:08:38.470017 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass>
1949 08:08:38.470852 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass
1951 08:08:38.557659 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass>
1952 08:08:38.558487 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass
1954 08:08:38.644736 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass>
1955 08:08:38.645538 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass
1957 08:08:38.736908 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass>
1958 08:08:38.737710 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass
1960 08:08:38.824570 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass>
1961 08:08:38.825362 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass
1963 08:08:38.913963 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass>
1964 08:08:38.914770 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass
1966 08:08:39.001384 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail>
1967 08:08:39.002181 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail
1969 08:08:39.090491 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass>
1970 08:08:39.091313 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass
1972 08:08:39.183230 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass>
1973 08:08:39.184052 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass
1975 08:08:39.277938 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass>
1976 08:08:39.278728 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass
1978 08:08:39.370179 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail>
1979 08:08:39.371093 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail
1981 08:08:39.459684 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip>
1982 08:08:39.460567 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip
1984 08:08:39.551487 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip>
1985 08:08:39.552352 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip
1987 08:08:39.639114 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip>
1988 08:08:39.639926 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip
1990 08:08:39.726536 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip>
1991 08:08:39.727326 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip
1993 08:08:39.819506 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip>
1994 08:08:39.820327 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip
1996 08:08:39.912281 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip>
1997 08:08:39.913070 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip
1999 08:08:39.999229 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip>
2000 08:08:40.000063 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip
2002 08:08:40.086486 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip>
2003 08:08:40.087293 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip
2005 08:08:40.179644 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip>
2006 08:08:40.180478 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip
2008 08:08:40.266537 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip>
2009 08:08:40.267324 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip
2011 08:08:40.359569 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip>
2012 08:08:40.360519 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip
2014 08:08:40.460307 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip>
2015 08:08:40.461243 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip
2017 08:08:40.591464 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip
2019 08:08:40.594526 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip>
2020 08:08:40.735310 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip
2022 08:08:40.738537 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip>
2023 08:08:40.877114 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip
2025 08:08:40.880354 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip>
2026 08:08:40.974932 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass>
2027 08:08:40.975841 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass
2029 08:08:41.081698 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail>
2030 08:08:41.082597 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail
2032 08:08:41.175420 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail>
2033 08:08:41.176265 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail
2035 08:08:41.267852 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip>
2036 08:08:41.268727 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip
2038 08:08:41.353971 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass>
2039 08:08:41.354866 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass
2041 08:08:41.441269 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail>
2042 08:08:41.442123 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail
2044 08:08:41.528011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass>
2045 08:08:41.528845 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass
2047 08:08:41.621425 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail>
2048 08:08:41.622241 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail
2050 08:08:41.712747 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass>
2051 08:08:41.713546 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass
2053 08:08:41.800084 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass>
2054 08:08:41.800879 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass
2056 08:08:41.885166 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass>
2057 08:08:41.885952 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass
2059 08:08:41.978501 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass>
2060 08:08:41.979291 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass
2062 08:08:42.064076 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass>
2063 08:08:42.064896 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass
2065 08:08:42.151095 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass>
2066 08:08:42.151902 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass
2068 08:08:42.238981 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_eeprom_50 RESULT=pass>
2069 08:08:42.239803 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_eeprom_50 RESULT=pass
2071 08:08:42.335744 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_eeprom_50_nvmem-layout RESULT=skip>
2072 08:08:42.336677 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_eeprom_50_nvmem-layout RESULT=skip
2074 08:08:42.428068 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass>
2075 08:08:42.428988 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass
2077 08:08:42.520406 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass>
2078 08:08:42.521311 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass
2080 08:08:42.614410 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail>
2081 08:08:42.615302 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail
2083 08:08:42.707686 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail>
2084 08:08:42.708624 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail
2086 08:08:42.792677 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass>
2087 08:08:42.793519 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass
2089 08:08:42.887349 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail>
2090 08:08:42.888186 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail
2092 08:08:42.981775 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail>
2093 08:08:42.982597 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail
2095 08:08:43.073190 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass>
2096 08:08:43.074028 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass
2098 08:08:43.168265 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass>
2099 08:08:43.169067 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass
2101 08:08:43.262211 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass>
2102 08:08:43.263076 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass
2104 08:08:43.354514 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass>
2105 08:08:43.355414 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass
2107 08:08:43.441778 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass>
2108 08:08:43.442632 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass
2110 08:08:43.536908 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass>
2111 08:08:43.537726 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass
2113 08:08:43.629896 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass>
2114 08:08:43.630739 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass
2116 08:08:43.725682 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass>
2117 08:08:43.726545 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass
2119 08:08:43.818454 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass>
2120 08:08:43.819285 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass
2122 08:08:43.906912 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail>
2123 08:08:43.907735 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail
2125 08:08:43.995696 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip>
2126 08:08:43.996555 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip
2128 08:08:44.087856 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass>
2129 08:08:44.088769 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass
2131 08:08:44.175885 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass>
2132 08:08:44.176752 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass
2134 08:08:44.262873 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass>
2135 08:08:44.263706 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass
2137 08:08:44.350782 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass>
2138 08:08:44.351713 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass
2140 08:08:44.443408 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass>
2141 08:08:44.444275 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass
2143 08:08:44.531731 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass>
2144 08:08:44.532631 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass
2146 08:08:44.624288 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass>
2147 08:08:44.625099 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass
2149 08:08:44.717924 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass>
2150 08:08:44.718783 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass
2152 08:08:44.804812 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass>
2153 08:08:44.805627 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass
2155 08:08:44.891966 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass>
2156 08:08:44.892819 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass
2158 08:08:44.977687 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass>
2159 08:08:44.978520 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass
2161 08:08:45.072987 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass>
2162 08:08:45.073792 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass
2164 08:08:45.163002 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass>
2165 08:08:45.163798 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass
2167 08:08:45.249643 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass>
2168 08:08:45.250451 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass
2170 08:08:45.344435 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass>
2171 08:08:45.345309 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass
2173 08:08:45.437872 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass>
2174 08:08:45.438716 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass
2176 08:08:45.525602 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass>
2177 08:08:45.526399 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass
2179 08:08:45.613872 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass>
2180 08:08:45.614622 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass
2182 08:08:45.704869 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass>
2183 08:08:45.705716 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass
2185 08:08:45.803019 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass>
2186 08:08:45.803836 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass
2188 08:08:45.889574 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass>
2189 08:08:45.890465 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass
2191 08:08:45.984696 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_54 RESULT=fail>
2192 08:08:45.985642 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_54 RESULT=fail
2194 08:08:46.073795 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_54_nvmem-layout RESULT=skip>
2195 08:08:46.074635 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_54_nvmem-layout RESULT=skip
2197 08:08:46.165517 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_55 RESULT=fail>
2198 08:08:46.166361 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_55 RESULT=fail
2200 08:08:46.254134 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_55_nvmem-layout RESULT=skip>
2201 08:08:46.255009 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_55_nvmem-layout RESULT=skip
2203 08:08:46.346364 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_56 RESULT=fail>
2204 08:08:46.347321 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_56 RESULT=fail
2206 08:08:46.440150 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_56_nvmem-layout RESULT=skip>
2207 08:08:46.440794 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_56_nvmem-layout RESULT=skip
2209 08:08:46.527035 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_57 RESULT=fail>
2210 08:08:46.527661 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_57 RESULT=fail
2212 08:08:46.615092 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_57_nvmem-layout RESULT=skip>
2213 08:08:46.615742 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_57_nvmem-layout RESULT=skip
2215 08:08:46.703808 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass>
2216 08:08:46.704462 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass
2218 08:08:46.790785 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass>
2219 08:08:46.791412 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass
2221 08:08:46.886805 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass>
2222 08:08:46.887625 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass
2224 08:08:46.980069 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass>
2225 08:08:46.980661 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass
2227 08:08:47.072631 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass>
2228 08:08:47.073451 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass
2230 08:08:47.159758 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass>
2231 08:08:47.160418 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass
2233 08:08:47.253360 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass>
2234 08:08:47.254248 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass
2236 08:08:47.346078 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass>
2237 08:08:47.346953 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass
2239 08:08:47.439154 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass>
2240 08:08:47.440040 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass
2242 08:08:47.526518 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass>
2243 08:08:47.527384 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass
2245 08:08:47.616302 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass>
2246 08:08:47.617163 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass
2248 08:08:47.708557 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass>
2249 08:08:47.709416 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass
2251 08:08:47.793679 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass>
2252 08:08:47.794533 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass
2254 08:08:47.882338 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass>
2255 08:08:47.883214 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass
2257 08:08:47.970405 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip>
2258 08:08:47.971454 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip
2260 08:08:48.057322 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass>
2261 08:08:48.058183 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass
2263 08:08:48.152335 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass>
2264 08:08:48.153215 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass
2266 08:08:48.248221 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass>
2267 08:08:48.249257 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass
2269 08:08:48.347478 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass>
2270 08:08:48.348437 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass
2272 08:08:48.442602 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass>
2273 08:08:48.443466 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass
2275 08:08:48.529765 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass>
2276 08:08:48.530584 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass
2278 08:08:48.617983 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass>
2279 08:08:48.618733 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass
2281 08:08:48.713795 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail>
2282 08:08:48.714547 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail
2284 08:08:48.801673 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass>
2285 08:08:48.802380 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass
2287 08:08:48.891881 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass>
2288 08:08:48.892648 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass
2290 08:08:48.984803 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass>
2291 08:08:48.985645 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass
2293 08:08:49.078827 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass>
2294 08:08:49.079699 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass
2296 08:08:49.168071 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass>
2297 08:08:49.168918 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass
2299 08:08:49.258744 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass>
2300 08:08:49.259566 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass
2302 08:08:49.352536 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail>
2303 08:08:49.353448 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail
2305 08:08:49.446655 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip>
2306 08:08:49.447516 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip
2308 08:08:49.540868 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail>
2309 08:08:49.541718 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail
2311 08:08:49.627076 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip>
2312 08:08:49.628017 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip
2314 08:08:49.714698 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail>
2315 08:08:49.715548 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail
2317 08:08:49.801942 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail>
2318 08:08:49.802795 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail
2320 08:08:49.885716 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail>
2321 08:08:49.886534 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail
2323 08:08:49.980548 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail>
2324 08:08:49.981416 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail
2326 08:08:50.072746 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip>
2327 08:08:50.073609 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip
2329 08:08:50.164240 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass>
2330 08:08:50.165086 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass
2332 08:08:50.251216 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass>
2333 08:08:50.252078 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass
2335 08:08:50.339854 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip>
2336 08:08:50.340772 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip
2338 08:08:50.423244 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip
2340 08:08:50.426458 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip>
2341 08:08:50.517491 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass>
2342 08:08:50.518340 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass
2344 08:08:50.613693 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass>
2345 08:08:50.614577 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass
2347 08:08:50.705826 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass>
2348 08:08:50.706769 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass
2350 08:08:50.793556 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass>
2351 08:08:50.794473 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass
2353 08:08:50.880578 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass>
2354 08:08:50.881476 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass
2356 08:08:50.971448 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass>
2357 08:08:50.972409 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass
2359 08:08:51.060341 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass>
2360 08:08:51.061254 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass
2362 08:08:51.152693 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass>
2363 08:08:51.153593 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass
2365 08:08:51.247853 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass>
2366 08:08:51.249025 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass
2368 08:08:51.341030 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass>
2369 08:08:51.342026 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass
2371 08:08:51.434209 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass>
2372 08:08:51.435139 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass
2374 08:08:51.519951 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass>
2375 08:08:51.520854 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass
2377 08:08:51.607383 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass>
2378 08:08:51.608339 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass
2380 08:08:51.701145 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass>
2381 08:08:51.701994 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass
2383 08:08:51.792313 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass>
2384 08:08:51.793214 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass
2386 08:08:51.883242 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass>
2387 08:08:51.884131 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass
2389 08:08:51.970487 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail>
2390 08:08:51.971359 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail
2392 08:08:52.055547 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass>
2393 08:08:52.056229 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass
2395 08:08:52.142160 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass>
2396 08:08:52.142809 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass
2398 08:08:52.232933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail>
2399 08:08:52.233805 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail
2401 08:08:52.317362 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass>
2402 08:08:52.318217 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass
2404 08:08:52.411063 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail>
2405 08:08:52.411691 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail
2407 08:08:52.501816 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass>
2408 08:08:52.502415 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass
2410 08:08:52.590689 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip>
2411 08:08:52.591559 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip
2413 08:08:52.680447 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip>
2414 08:08:52.681982 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip
2416 08:08:52.772607 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip>
2417 08:08:52.773450 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip
2419 08:08:52.861502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass>
2420 08:08:52.862317 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass
2422 08:08:52.948974 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass>
2423 08:08:52.949790 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass
2425 08:08:53.038518 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass>
2426 08:08:53.039307 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass
2428 08:08:53.127053 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass>
2429 08:08:53.127729 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass
2431 08:08:53.219314 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail>
2432 08:08:53.219947 + set +x
2433 08:08:53.220693 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail
2435 08:08:53.227503 <LAVA_SIGNAL_ENDRUN 1_kselftest-dt 978559_1.6.2.4.5>
2436 08:08:53.228039 <LAVA_TEST_RUNNER EXIT>
2437 08:08:53.228712 Received signal: <ENDRUN> 1_kselftest-dt 978559_1.6.2.4.5
2438 08:08:53.229177 Ending use of test pattern.
2439 08:08:53.229597 Ending test lava.1_kselftest-dt (978559_1.6.2.4.5), duration 82.23
2441 08:08:53.231105 ok: lava_test_shell seems to have completed
2442 08:08:53.243707 dt_test_unprobed_devices_sh: fail
dt_test_unprobed_devices_sh_: skip
dt_test_unprobed_devices_sh_clk_mcasp0: pass
dt_test_unprobed_devices_sh_clk_mcasp0_fixed: skip
dt_test_unprobed_devices_sh_cpus_cpu_0: skip
dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate: skip
dt_test_unprobed_devices_sh_fixedregulator0: pass
dt_test_unprobed_devices_sh_leds: pass
dt_test_unprobed_devices_sh_ocp: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0: fail
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_eeprom_50: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_eeprom_50_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_54: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_54_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_55: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_55_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_56: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_56_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_57: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_57_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000: skip
dt_test_unprobed_devices_sh_ocp_target-module_47400000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800: pass
dt_test_unprobed_devices_sh_ocp_target-module_47810000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_50000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_53500000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_56000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0: skip
dt_test_unprobed_devices_sh_opp-table: skip
dt_test_unprobed_devices_sh_soc: skip
dt_test_unprobed_devices_sh_sound: pass
dt_test_unprobed_devices_sh_target-module_4b000000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0: pass
shardfile-dt: pass
2443 08:08:53.245748 end: 3.1 lava-test-shell (duration 00:01:24) [common]
2444 08:08:53.246370 end: 3 lava-test-retry (duration 00:01:24) [common]
2445 08:08:53.246933 start: 4 finalize (timeout 00:04:42) [common]
2446 08:08:53.247500 start: 4.1 power-off (timeout 00:00:30) [common]
2447 08:08:53.248520 Calling: 'curl' 'http://conserv3.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=beaglebone-black-04'
2448 08:08:53.286929 >> OK - accepted request
2449 08:08:53.288831 Returned 0 in 0 seconds
2450 08:08:53.390099 end: 4.1 power-off (duration 00:00:00) [common]
2452 08:08:53.391886 start: 4.2 read-feedback (timeout 00:04:42) [common]
2453 08:08:53.393199 Listened to connection for namespace 'common' for up to 1s
2454 08:08:53.394272 Listened to connection for namespace 'common' for up to 1s
2455 08:08:54.394055 Finalising connection for namespace 'common'
2456 08:08:54.395124 Disconnecting from shell: Finalise
2457 08:08:54.395895 / #
2458 08:08:54.497314 end: 4.2 read-feedback (duration 00:00:01) [common]
2459 08:08:54.498169 end: 4 finalize (duration 00:00:01) [common]
2460 08:08:54.498844 Cleaning after the job
2461 08:08:54.499440 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/978559/tftp-deploy-6gevtrq_/ramdisk
2462 08:08:54.508666 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/978559/tftp-deploy-6gevtrq_/kernel
2463 08:08:54.510607 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/978559/tftp-deploy-6gevtrq_/dtb
2464 08:08:54.511724 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/978559/tftp-deploy-6gevtrq_/nfsrootfs
2465 08:08:54.551000 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/978559/tftp-deploy-6gevtrq_/modules
2466 08:08:54.555334 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/978559
2467 08:08:57.545674 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/978559
2468 08:08:57.546236 Job finished correctly