Boot log: beaglebone-black
- Warnings: 2
- Kernel Warnings: 15
- Errors: 0
- Boot result: PASS
- Kernel Errors: 10
1 07:41:35.381321 lava-dispatcher, installed at version: 2024.01
2 07:41:35.382173 start: 0 validate
3 07:41:35.382694 Start time: 2024-11-12 07:41:35.382660+00:00 (UTC)
4 07:41:35.383306 Using caching service: 'http://192.168.6.3:8001/api/v1/fetch?url=%s'
5 07:41:35.384004 Validating that http://192.168.6.3:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farmhf%2Finitrd.cpio.gz exists
6 07:41:35.420772 Using caching service: 'http://192.168.6.3:8001/api/v1/fetch?url=%s'
7 07:41:35.421369 Validating that http://192.168.6.3:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241112%2Farm%2Fmulti_v7_defconfig%2Fgcc-12%2Fkernel%2FzImage exists
8 07:41:35.447078 Using caching service: 'http://192.168.6.3:8001/api/v1/fetch?url=%s'
9 07:41:35.447775 Validating that http://192.168.6.3:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241112%2Farm%2Fmulti_v7_defconfig%2Fgcc-12%2Fdtbs%2Fti%2Fomap%2Fam335x-boneblack.dtb exists
10 07:41:35.472830 Using caching service: 'http://192.168.6.3:8001/api/v1/fetch?url=%s'
11 07:41:35.473396 Validating that http://192.168.6.3:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farmhf%2Ffull.rootfs.tar.xz exists
12 07:41:35.497374 Using caching service: 'http://192.168.6.3:8001/api/v1/fetch?url=%s'
13 07:41:35.497915 Validating that http://192.168.6.3:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241112%2Farm%2Fmulti_v7_defconfig%2Fgcc-12%2Fmodules.tar.xz exists
14 07:41:35.527129 validate duration: 0.14
16 07:41:35.528088 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 07:41:35.528404 start: 1.1 download-retry (timeout 00:10:00) [common]
18 07:41:35.528685 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 07:41:35.529265 Not decompressing ramdisk as can be used compressed.
20 07:41:35.529726 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/initrd.cpio.gz
21 07:41:35.530021 saving as /var/lib/lava/dispatcher/tmp/978505/tftp-deploy-as9cs3pz/ramdisk/initrd.cpio.gz
22 07:41:35.530273 total size: 4775763 (4 MB)
23 07:41:35.561964 progress 0 % (0 MB)
24 07:41:35.566932 progress 5 % (0 MB)
25 07:41:35.570419 progress 10 % (0 MB)
26 07:41:35.573881 progress 15 % (0 MB)
27 07:41:35.577644 progress 20 % (0 MB)
28 07:41:35.581047 progress 25 % (1 MB)
29 07:41:35.584676 progress 30 % (1 MB)
30 07:41:35.588735 progress 35 % (1 MB)
31 07:41:35.592149 progress 40 % (1 MB)
32 07:41:35.595631 progress 45 % (2 MB)
33 07:41:35.598946 progress 50 % (2 MB)
34 07:41:35.602592 progress 55 % (2 MB)
35 07:41:35.605970 progress 60 % (2 MB)
36 07:41:35.609243 progress 65 % (2 MB)
37 07:41:35.612872 progress 70 % (3 MB)
38 07:41:35.616677 progress 75 % (3 MB)
39 07:41:35.620213 progress 80 % (3 MB)
40 07:41:35.623931 progress 85 % (3 MB)
41 07:41:35.627689 progress 90 % (4 MB)
42 07:41:35.631010 progress 95 % (4 MB)
43 07:41:35.634204 progress 100 % (4 MB)
44 07:41:35.634884 4 MB downloaded in 0.10 s (43.55 MB/s)
45 07:41:35.635465 end: 1.1.1 http-download (duration 00:00:00) [common]
47 07:41:35.636417 end: 1.1 download-retry (duration 00:00:00) [common]
48 07:41:35.636768 start: 1.2 download-retry (timeout 00:10:00) [common]
49 07:41:35.637087 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 07:41:35.637559 downloading http://storage.kernelci.org/next/master/next-20241112/arm/multi_v7_defconfig/gcc-12/kernel/zImage
51 07:41:35.637845 saving as /var/lib/lava/dispatcher/tmp/978505/tftp-deploy-as9cs3pz/kernel/zImage
52 07:41:35.638095 total size: 11514368 (10 MB)
53 07:41:35.638341 No compression specified
54 07:41:35.675027 progress 0 % (0 MB)
55 07:41:35.683902 progress 5 % (0 MB)
56 07:41:35.692269 progress 10 % (1 MB)
57 07:41:35.700186 progress 15 % (1 MB)
58 07:41:35.708946 progress 20 % (2 MB)
59 07:41:35.717358 progress 25 % (2 MB)
60 07:41:35.725316 progress 30 % (3 MB)
61 07:41:35.732657 progress 35 % (3 MB)
62 07:41:35.740701 progress 40 % (4 MB)
63 07:41:35.748100 progress 45 % (4 MB)
64 07:41:35.755093 progress 50 % (5 MB)
65 07:41:35.762475 progress 55 % (6 MB)
66 07:41:35.769433 progress 60 % (6 MB)
67 07:41:35.776778 progress 65 % (7 MB)
68 07:41:35.783913 progress 70 % (7 MB)
69 07:41:35.791335 progress 75 % (8 MB)
70 07:41:35.798635 progress 80 % (8 MB)
71 07:41:35.805597 progress 85 % (9 MB)
72 07:41:35.812978 progress 90 % (9 MB)
73 07:41:35.819749 progress 95 % (10 MB)
74 07:41:35.826472 progress 100 % (10 MB)
75 07:41:35.827012 10 MB downloaded in 0.19 s (58.13 MB/s)
76 07:41:35.827483 end: 1.2.1 http-download (duration 00:00:00) [common]
78 07:41:35.828282 end: 1.2 download-retry (duration 00:00:00) [common]
79 07:41:35.828555 start: 1.3 download-retry (timeout 00:10:00) [common]
80 07:41:35.828813 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 07:41:35.829287 downloading http://storage.kernelci.org/next/master/next-20241112/arm/multi_v7_defconfig/gcc-12/dtbs/ti/omap/am335x-boneblack.dtb
82 07:41:35.829535 saving as /var/lib/lava/dispatcher/tmp/978505/tftp-deploy-as9cs3pz/dtb/am335x-boneblack.dtb
83 07:41:35.829735 total size: 70544 (0 MB)
84 07:41:35.829972 No compression specified
85 07:41:35.864204 progress 46 % (0 MB)
86 07:41:35.865038 progress 92 % (0 MB)
87 07:41:35.865693 progress 100 % (0 MB)
88 07:41:35.866107 0 MB downloaded in 0.04 s (1.85 MB/s)
89 07:41:35.866551 end: 1.3.1 http-download (duration 00:00:00) [common]
91 07:41:35.867348 end: 1.3 download-retry (duration 00:00:00) [common]
92 07:41:35.867606 start: 1.4 download-retry (timeout 00:10:00) [common]
93 07:41:35.867862 start: 1.4.1 http-download (timeout 00:10:00) [common]
94 07:41:35.868321 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/full.rootfs.tar.xz
95 07:41:35.868563 saving as /var/lib/lava/dispatcher/tmp/978505/tftp-deploy-as9cs3pz/nfsrootfs/full.rootfs.tar
96 07:41:35.868763 total size: 117747780 (112 MB)
97 07:41:35.868968 Using unxz to decompress xz
98 07:41:35.894516 progress 0 % (0 MB)
99 07:41:36.607020 progress 5 % (5 MB)
100 07:41:37.344533 progress 10 % (11 MB)
101 07:41:38.102883 progress 15 % (16 MB)
102 07:41:38.815896 progress 20 % (22 MB)
103 07:41:39.389949 progress 25 % (28 MB)
104 07:41:40.188883 progress 30 % (33 MB)
105 07:41:40.989356 progress 35 % (39 MB)
106 07:41:41.334790 progress 40 % (44 MB)
107 07:41:41.681304 progress 45 % (50 MB)
108 07:41:42.342790 progress 50 % (56 MB)
109 07:41:43.151708 progress 55 % (61 MB)
110 07:41:43.882858 progress 60 % (67 MB)
111 07:41:44.596294 progress 65 % (73 MB)
112 07:41:45.374219 progress 70 % (78 MB)
113 07:41:46.130930 progress 75 % (84 MB)
114 07:41:46.866054 progress 80 % (89 MB)
115 07:41:47.566680 progress 85 % (95 MB)
116 07:41:48.348461 progress 90 % (101 MB)
117 07:41:49.101449 progress 95 % (106 MB)
118 07:41:49.918240 progress 100 % (112 MB)
119 07:41:49.930689 112 MB downloaded in 14.06 s (7.99 MB/s)
120 07:41:49.931308 end: 1.4.1 http-download (duration 00:00:14) [common]
122 07:41:49.932130 end: 1.4 download-retry (duration 00:00:14) [common]
123 07:41:49.932391 start: 1.5 download-retry (timeout 00:09:46) [common]
124 07:41:49.932647 start: 1.5.1 http-download (timeout 00:09:46) [common]
125 07:41:49.933259 downloading http://storage.kernelci.org/next/master/next-20241112/arm/multi_v7_defconfig/gcc-12/modules.tar.xz
126 07:41:49.933523 saving as /var/lib/lava/dispatcher/tmp/978505/tftp-deploy-as9cs3pz/modules/modules.tar
127 07:41:49.933730 total size: 6628132 (6 MB)
128 07:41:49.934123 Using unxz to decompress xz
129 07:41:49.968955 progress 0 % (0 MB)
130 07:41:50.008623 progress 5 % (0 MB)
131 07:41:50.062500 progress 10 % (0 MB)
132 07:41:50.115900 progress 15 % (0 MB)
133 07:41:50.170089 progress 20 % (1 MB)
134 07:41:50.227846 progress 25 % (1 MB)
135 07:41:50.277488 progress 30 % (1 MB)
136 07:41:50.321441 progress 35 % (2 MB)
137 07:41:50.365714 progress 40 % (2 MB)
138 07:41:50.414145 progress 45 % (2 MB)
139 07:41:50.458052 progress 50 % (3 MB)
140 07:41:50.500912 progress 55 % (3 MB)
141 07:41:50.546849 progress 60 % (3 MB)
142 07:41:50.593629 progress 65 % (4 MB)
143 07:41:50.642484 progress 70 % (4 MB)
144 07:41:50.688555 progress 75 % (4 MB)
145 07:41:50.731895 progress 80 % (5 MB)
146 07:41:50.774776 progress 85 % (5 MB)
147 07:41:50.822045 progress 90 % (5 MB)
148 07:41:50.865033 progress 95 % (6 MB)
149 07:41:50.909348 progress 100 % (6 MB)
150 07:41:50.920584 6 MB downloaded in 0.99 s (6.41 MB/s)
151 07:41:50.921180 end: 1.5.1 http-download (duration 00:00:01) [common]
153 07:41:50.922281 end: 1.5 download-retry (duration 00:00:01) [common]
154 07:41:50.922870 start: 1.6 prepare-tftp-overlay (timeout 00:09:45) [common]
155 07:41:50.923437 start: 1.6.1 extract-nfsrootfs (timeout 00:09:45) [common]
156 07:42:07.350845 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/978505/extract-nfsrootfs-kr0x50hc
157 07:42:07.351459 end: 1.6.1 extract-nfsrootfs (duration 00:00:16) [common]
158 07:42:07.351743 start: 1.6.2 lava-overlay (timeout 00:09:28) [common]
159 07:42:07.352351 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/978505/lava-overlay-jr_lufjn
160 07:42:07.352764 makedir: /var/lib/lava/dispatcher/tmp/978505/lava-overlay-jr_lufjn/lava-978505/bin
161 07:42:07.353078 makedir: /var/lib/lava/dispatcher/tmp/978505/lava-overlay-jr_lufjn/lava-978505/tests
162 07:42:07.353386 makedir: /var/lib/lava/dispatcher/tmp/978505/lava-overlay-jr_lufjn/lava-978505/results
163 07:42:07.353718 Creating /var/lib/lava/dispatcher/tmp/978505/lava-overlay-jr_lufjn/lava-978505/bin/lava-add-keys
164 07:42:07.354289 Creating /var/lib/lava/dispatcher/tmp/978505/lava-overlay-jr_lufjn/lava-978505/bin/lava-add-sources
165 07:42:07.354787 Creating /var/lib/lava/dispatcher/tmp/978505/lava-overlay-jr_lufjn/lava-978505/bin/lava-background-process-start
166 07:42:07.355283 Creating /var/lib/lava/dispatcher/tmp/978505/lava-overlay-jr_lufjn/lava-978505/bin/lava-background-process-stop
167 07:42:07.355795 Creating /var/lib/lava/dispatcher/tmp/978505/lava-overlay-jr_lufjn/lava-978505/bin/lava-common-functions
168 07:42:07.356277 Creating /var/lib/lava/dispatcher/tmp/978505/lava-overlay-jr_lufjn/lava-978505/bin/lava-echo-ipv4
169 07:42:07.356780 Creating /var/lib/lava/dispatcher/tmp/978505/lava-overlay-jr_lufjn/lava-978505/bin/lava-install-packages
170 07:42:07.357245 Creating /var/lib/lava/dispatcher/tmp/978505/lava-overlay-jr_lufjn/lava-978505/bin/lava-installed-packages
171 07:42:07.357729 Creating /var/lib/lava/dispatcher/tmp/978505/lava-overlay-jr_lufjn/lava-978505/bin/lava-os-build
172 07:42:07.358249 Creating /var/lib/lava/dispatcher/tmp/978505/lava-overlay-jr_lufjn/lava-978505/bin/lava-probe-channel
173 07:42:07.358721 Creating /var/lib/lava/dispatcher/tmp/978505/lava-overlay-jr_lufjn/lava-978505/bin/lava-probe-ip
174 07:42:07.359186 Creating /var/lib/lava/dispatcher/tmp/978505/lava-overlay-jr_lufjn/lava-978505/bin/lava-target-ip
175 07:42:07.359646 Creating /var/lib/lava/dispatcher/tmp/978505/lava-overlay-jr_lufjn/lava-978505/bin/lava-target-mac
176 07:42:07.360111 Creating /var/lib/lava/dispatcher/tmp/978505/lava-overlay-jr_lufjn/lava-978505/bin/lava-target-storage
177 07:42:07.360581 Creating /var/lib/lava/dispatcher/tmp/978505/lava-overlay-jr_lufjn/lava-978505/bin/lava-test-case
178 07:42:07.361044 Creating /var/lib/lava/dispatcher/tmp/978505/lava-overlay-jr_lufjn/lava-978505/bin/lava-test-event
179 07:42:07.361522 Creating /var/lib/lava/dispatcher/tmp/978505/lava-overlay-jr_lufjn/lava-978505/bin/lava-test-feedback
180 07:42:07.362033 Creating /var/lib/lava/dispatcher/tmp/978505/lava-overlay-jr_lufjn/lava-978505/bin/lava-test-raise
181 07:42:07.362543 Creating /var/lib/lava/dispatcher/tmp/978505/lava-overlay-jr_lufjn/lava-978505/bin/lava-test-reference
182 07:42:07.363012 Creating /var/lib/lava/dispatcher/tmp/978505/lava-overlay-jr_lufjn/lava-978505/bin/lava-test-runner
183 07:42:07.363480 Creating /var/lib/lava/dispatcher/tmp/978505/lava-overlay-jr_lufjn/lava-978505/bin/lava-test-set
184 07:42:07.363945 Creating /var/lib/lava/dispatcher/tmp/978505/lava-overlay-jr_lufjn/lava-978505/bin/lava-test-shell
185 07:42:07.364414 Updating /var/lib/lava/dispatcher/tmp/978505/lava-overlay-jr_lufjn/lava-978505/bin/lava-add-keys (debian)
186 07:42:07.364933 Updating /var/lib/lava/dispatcher/tmp/978505/lava-overlay-jr_lufjn/lava-978505/bin/lava-add-sources (debian)
187 07:42:07.365426 Updating /var/lib/lava/dispatcher/tmp/978505/lava-overlay-jr_lufjn/lava-978505/bin/lava-install-packages (debian)
188 07:42:07.365926 Updating /var/lib/lava/dispatcher/tmp/978505/lava-overlay-jr_lufjn/lava-978505/bin/lava-installed-packages (debian)
189 07:42:07.366410 Updating /var/lib/lava/dispatcher/tmp/978505/lava-overlay-jr_lufjn/lava-978505/bin/lava-os-build (debian)
190 07:42:07.366829 Creating /var/lib/lava/dispatcher/tmp/978505/lava-overlay-jr_lufjn/lava-978505/environment
191 07:42:07.367249 LAVA metadata
192 07:42:07.367508 - LAVA_JOB_ID=978505
193 07:42:07.367718 - LAVA_DISPATCHER_IP=192.168.6.3
194 07:42:07.368063 start: 1.6.2.1 ssh-authorize (timeout 00:09:28) [common]
195 07:42:07.368963 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
196 07:42:07.369259 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:28) [common]
197 07:42:07.369461 skipped lava-vland-overlay
198 07:42:07.369696 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
199 07:42:07.370008 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:28) [common]
200 07:42:07.370210 skipped lava-multinode-overlay
201 07:42:07.370444 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
202 07:42:07.370686 start: 1.6.2.4 test-definition (timeout 00:09:28) [common]
203 07:42:07.370927 Loading test definitions
204 07:42:07.371192 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:28) [common]
205 07:42:07.371422 Using /lava-978505 at stage 0
206 07:42:07.372467 uuid=978505_1.6.2.4.1 testdef=None
207 07:42:07.372757 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
208 07:42:07.373014 start: 1.6.2.4.2 test-overlay (timeout 00:09:28) [common]
209 07:42:07.374557 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
211 07:42:07.375320 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:28) [common]
212 07:42:07.377192 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
214 07:42:07.378014 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:28) [common]
215 07:42:07.379764 runner path: /var/lib/lava/dispatcher/tmp/978505/lava-overlay-jr_lufjn/lava-978505/0/tests/0_timesync-off test_uuid 978505_1.6.2.4.1
216 07:42:07.380304 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
218 07:42:07.381101 start: 1.6.2.4.5 git-repo-action (timeout 00:09:28) [common]
219 07:42:07.381319 Using /lava-978505 at stage 0
220 07:42:07.381661 Fetching tests from https://github.com/kernelci/test-definitions.git
221 07:42:07.381966 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/978505/lava-overlay-jr_lufjn/lava-978505/0/tests/1_kselftest-dt'
222 07:42:10.824094 Running '/usr/bin/git checkout kernelci.org
223 07:42:11.268412 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/978505/lava-overlay-jr_lufjn/lava-978505/0/tests/1_kselftest-dt/automated/linux/kselftest/kselftest.yaml
224 07:42:11.269884 uuid=978505_1.6.2.4.5 testdef=None
225 07:42:11.270239 end: 1.6.2.4.5 git-repo-action (duration 00:00:04) [common]
227 07:42:11.270975 start: 1.6.2.4.6 test-overlay (timeout 00:09:24) [common]
228 07:42:11.273745 end: 1.6.2.4.6 test-overlay (duration 00:00:00) [common]
230 07:42:11.274572 start: 1.6.2.4.7 test-install-overlay (timeout 00:09:24) [common]
231 07:42:11.278260 end: 1.6.2.4.7 test-install-overlay (duration 00:00:00) [common]
233 07:42:11.279102 start: 1.6.2.4.8 test-runscript-overlay (timeout 00:09:24) [common]
234 07:42:11.282647 runner path: /var/lib/lava/dispatcher/tmp/978505/lava-overlay-jr_lufjn/lava-978505/0/tests/1_kselftest-dt test_uuid 978505_1.6.2.4.5
235 07:42:11.282951 BOARD='beaglebone-black'
236 07:42:11.283157 BRANCH='next'
237 07:42:11.283349 SKIPFILE='/dev/null'
238 07:42:11.283544 SKIP_INSTALL='True'
239 07:42:11.283738 TESTPROG_URL='http://storage.kernelci.org/next/master/next-20241112/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz'
240 07:42:11.283933 TST_CASENAME=''
241 07:42:11.284124 TST_CMDFILES='dt'
242 07:42:11.284654 end: 1.6.2.4.8 test-runscript-overlay (duration 00:00:00) [common]
244 07:42:11.285423 Creating lava-test-runner.conf files
245 07:42:11.285623 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/978505/lava-overlay-jr_lufjn/lava-978505/0 for stage 0
246 07:42:11.285994 - 0_timesync-off
247 07:42:11.286239 - 1_kselftest-dt
248 07:42:11.286567 end: 1.6.2.4 test-definition (duration 00:00:04) [common]
249 07:42:11.286842 start: 1.6.2.5 compress-overlay (timeout 00:09:24) [common]
250 07:42:34.822487 end: 1.6.2.5 compress-overlay (duration 00:00:24) [common]
251 07:42:34.822903 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:09:01) [common]
252 07:42:34.823165 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
253 07:42:34.823431 end: 1.6.2 lava-overlay (duration 00:00:27) [common]
254 07:42:34.823693 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:01) [common]
255 07:42:35.234453 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
256 07:42:35.234924 start: 1.6.4 extract-modules (timeout 00:09:00) [common]
257 07:42:35.235169 extracting modules file /var/lib/lava/dispatcher/tmp/978505/tftp-deploy-as9cs3pz/modules/modules.tar to /var/lib/lava/dispatcher/tmp/978505/extract-nfsrootfs-kr0x50hc
258 07:42:36.135676 extracting modules file /var/lib/lava/dispatcher/tmp/978505/tftp-deploy-as9cs3pz/modules/modules.tar to /var/lib/lava/dispatcher/tmp/978505/extract-overlay-ramdisk-gc5m6r45/ramdisk
259 07:42:37.059026 end: 1.6.4 extract-modules (duration 00:00:02) [common]
260 07:42:37.059493 start: 1.6.5 apply-overlay-tftp (timeout 00:08:58) [common]
261 07:42:37.059765 [common] Applying overlay to NFS
262 07:42:37.059973 [common] Applying overlay /var/lib/lava/dispatcher/tmp/978505/compress-overlay-7nflkyhq/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/978505/extract-nfsrootfs-kr0x50hc
263 07:42:39.792822 end: 1.6.5 apply-overlay-tftp (duration 00:00:03) [common]
264 07:42:39.793299 start: 1.6.6 prepare-kernel (timeout 00:08:56) [common]
265 07:42:39.793570 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:08:56) [common]
266 07:42:39.793903 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
267 07:42:39.794173 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
268 07:42:39.794431 start: 1.6.7 configure-preseed-file (timeout 00:08:56) [common]
269 07:42:39.794680 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
270 07:42:39.794935 start: 1.6.8 compress-ramdisk (timeout 00:08:56) [common]
271 07:42:39.795158 Building ramdisk /var/lib/lava/dispatcher/tmp/978505/extract-overlay-ramdisk-gc5m6r45/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/978505/extract-overlay-ramdisk-gc5m6r45/ramdisk
272 07:42:40.904368 >> 75326 blocks
273 07:42:45.482234 Adding RAMdisk u-boot header.
274 07:42:45.483003 mkimage -A arm -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/978505/extract-overlay-ramdisk-gc5m6r45/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/978505/extract-overlay-ramdisk-gc5m6r45/ramdisk.cpio.gz.uboot
275 07:42:45.642133 output: Image Name:
276 07:42:45.642945 output: Created: Tue Nov 12 07:42:45 2024
277 07:42:45.643499 output: Image Type: ARM Linux RAMDisk Image (uncompressed)
278 07:42:45.644038 output: Data Size: 14831477 Bytes = 14483.86 KiB = 14.14 MiB
279 07:42:45.644579 output: Load Address: 00000000
280 07:42:45.645106 output: Entry Point: 00000000
281 07:42:45.645663 output:
282 07:42:45.647375 rename /var/lib/lava/dispatcher/tmp/978505/extract-overlay-ramdisk-gc5m6r45/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/978505/tftp-deploy-as9cs3pz/ramdisk/ramdisk.cpio.gz.uboot
283 07:42:45.648351 end: 1.6.8 compress-ramdisk (duration 00:00:06) [common]
284 07:42:45.649099 end: 1.6 prepare-tftp-overlay (duration 00:00:55) [common]
285 07:42:45.649855 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:50) [common]
286 07:42:45.650491 No LXC device requested
287 07:42:45.651187 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
288 07:42:45.651934 start: 1.8 deploy-device-env (timeout 00:08:50) [common]
289 07:42:45.652668 end: 1.8 deploy-device-env (duration 00:00:00) [common]
290 07:42:45.653250 Checking files for TFTP limit of 4294967296 bytes.
291 07:42:45.656914 end: 1 tftp-deploy (duration 00:01:10) [common]
292 07:42:45.657735 start: 2 uboot-action (timeout 00:05:00) [common]
293 07:42:45.658504 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
294 07:42:45.659229 end: 2.1 uboot-from-media (duration 00:00:00) [common]
295 07:42:45.659956 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
296 07:42:45.660980 substitutions:
297 07:42:45.661549 - {BOOTX}: bootz 0x82000000 0x83000000 0x88000000
298 07:42:45.662152 - {DTB_ADDR}: 0x88000000
299 07:42:45.662695 - {DTB}: 978505/tftp-deploy-as9cs3pz/dtb/am335x-boneblack.dtb
300 07:42:45.663230 - {INITRD}: 978505/tftp-deploy-as9cs3pz/ramdisk/ramdisk.cpio.gz.uboot
301 07:42:45.663756 - {KERNEL_ADDR}: 0x82000000
302 07:42:45.664281 - {KERNEL}: 978505/tftp-deploy-as9cs3pz/kernel/zImage
303 07:42:45.664808 - {LAVA_MAC}: None
304 07:42:45.665386 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/978505/extract-nfsrootfs-kr0x50hc
305 07:42:45.665965 - {NFS_SERVER_IP}: 192.168.6.3
306 07:42:45.666500 - {PRESEED_CONFIG}: None
307 07:42:45.667027 - {PRESEED_LOCAL}: None
308 07:42:45.667541 - {RAMDISK_ADDR}: 0x83000000
309 07:42:45.668068 - {RAMDISK}: 978505/tftp-deploy-as9cs3pz/ramdisk/ramdisk.cpio.gz.uboot
310 07:42:45.668596 - {ROOT_PART}: None
311 07:42:45.669116 - {ROOT}: None
312 07:42:45.669637 - {SERVER_IP}: 192.168.6.3
313 07:42:45.670187 - {TEE_ADDR}: 0x83000000
314 07:42:45.670701 - {TEE}: None
315 07:42:45.671230 Parsed boot commands:
316 07:42:45.671736 - setenv autoload no
317 07:42:45.672255 - setenv initrd_high 0xffffffff
318 07:42:45.672767 - setenv fdt_high 0xffffffff
319 07:42:45.673291 - dhcp
320 07:42:45.673802 - setenv serverip 192.168.6.3
321 07:42:45.674379 - tftp 0x82000000 978505/tftp-deploy-as9cs3pz/kernel/zImage
322 07:42:45.674899 - tftp 0x83000000 978505/tftp-deploy-as9cs3pz/ramdisk/ramdisk.cpio.gz.uboot
323 07:42:45.675428 - setenv initrd_size ${filesize}
324 07:42:45.675946 - tftp 0x88000000 978505/tftp-deploy-as9cs3pz/dtb/am335x-boneblack.dtb
325 07:42:45.676460 - setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.3:/var/lib/lava/dispatcher/tmp/978505/extract-nfsrootfs-kr0x50hc,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
326 07:42:45.676997 - bootz 0x82000000 0x83000000 0x88000000
327 07:42:45.677685 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
329 07:42:45.679763 start: 2.3 connect-device (timeout 00:05:00) [common]
330 07:42:45.680339 [common] connect-device Connecting to device using 'telnet conserv3 3002'
331 07:42:45.696890 Setting prompt string to ['lava-test: # ']
332 07:42:45.698889 end: 2.3 connect-device (duration 00:00:00) [common]
333 07:42:45.699712 start: 2.4 uboot-commands (timeout 00:05:00) [common]
334 07:42:45.700437 start: 2.4.1 reset-device (timeout 00:05:00) [common]
335 07:42:45.701161 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
336 07:42:45.702789 Calling: 'curl' 'http://conserv3.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=beaglebone-black-05'
337 07:42:45.741449 >> OK - accepted request
338 07:42:45.743732 Returned 0 in 0 seconds
339 07:42:45.845178 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
341 07:42:45.847456 end: 2.4.1 reset-device (duration 00:00:00) [common]
342 07:42:45.848296 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
343 07:42:45.849077 Setting prompt string to ['Hit any key to stop autoboot']
344 07:42:45.849695 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
345 07:42:45.851813 Trying 192.168.56.22...
346 07:42:45.852475 Connected to conserv3.
347 07:42:45.853047 Escape character is '^]'.
348 07:42:45.853616
349 07:42:45.854229 ser2net port telnet,3002 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.3:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
350 07:42:45.854816
351 07:42:54.258165
352 07:42:54.265013 U-Boot SPL 2023.04-rc1-00202-gce52d133f3 (Feb 06 2023 - 14:59:32 +0000)
353 07:42:54.265631 Trying to boot from MMC1
354 07:42:54.848233
355 07:42:54.849029
356 07:42:54.853770 U-Boot 2023.04-rc1-00202-gce52d133f3 (Feb 06 2023 - 14:59:32 +0000)
357 07:42:54.854401
358 07:42:54.854967 CPU : AM335X-GP rev 2.0
359 07:42:54.858882 Model: TI AM335x BeagleBone Black
360 07:42:54.859459 DRAM: 512 MiB
361 07:42:58.310350
362 07:42:58.317118 U-Boot SPL 2023.04-rc1-00202-gce52d133f3 (Feb 06 2023 - 14:59:32 +0000)
363 07:42:58.317867 Trying to boot from MMC1
364 07:42:58.900727
365 07:42:58.901526
366 07:42:58.906177 U-Boot 2023.04-rc1-00202-gce52d133f3 (Feb 06 2023 - 14:59:32 +0000)
367 07:42:58.906776
368 07:42:58.907341 CPU : AM335X-GP rev 2.0
369 07:42:58.911350 Model: TI AM335x BeagleBone Black
370 07:42:58.911937 DRAM: 512 MiB
371 07:43:01.149063
372 07:43:01.155559 U-Boot SPL 2023.04-rc1-00202-gce52d133f3 (Feb 06 2023 - 14:59:32 +0000)
373 07:43:01.156177 Trying to boot from MMC1
374 07:43:01.739554
375 07:43:01.740354
376 07:43:01.744906 U-Boot 2023.04-rc1-00202-gce52d133f3 (Feb 06 2023 - 14:59:32 +0000)
377 07:43:01.745509
378 07:43:01.746127 CPU : AM335X-GP rev 2.0
379 07:43:01.750087 Model: TI AM335x BeagleBone Black
380 07:43:01.750675 DRAM: 512 MiB
381 07:43:01.829842 Core: 160 devices, 18 uclasses, devicetree: separate
382 07:43:01.843823 WDT: Started wdt@44e35000 with servicing every 1000ms (60s timeout)
383 07:43:02.243864 NAND: 0 MiB
384 07:43:02.254949 MMC: OMAP SD/MMC: 0, OMAP SD/MMC: 1
385 07:43:02.382920 Loading Environment from FAT... Unable to read "uboot.env" from mmc0:1...
386 07:43:02.404236 <ethaddr> not set. Validating first E-fuse MAC
387 07:43:02.433923 Net: eth2: ethernet@4a100000, eth3: usb_ether
389 07:43:02.493525 Hit any key to stop autoboot: 2
390 07:43:02.494688 end: 2.4.2 bootloader-interrupt (duration 00:00:17) [common]
391 07:43:02.495494 start: 2.4.3 bootloader-commands (timeout 00:04:43) [common]
392 07:43:02.496146 Setting prompt string to ['=>']
393 07:43:02.496797 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:43)
394 07:43:02.502430 0
395 07:43:02.503560 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
396 07:43:02.504234 Sending with 10 millisecond of delay
398 07:43:03.639782 => setenv autoload no
399 07:43:03.650847 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:42)
400 07:43:03.657541 setenv autoload no
401 07:43:03.658538 Sending with 10 millisecond of delay
403 07:43:05.456532 => setenv initrd_high 0xffffffff
404 07:43:05.467598 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
405 07:43:05.468782 setenv initrd_high 0xffffffff
406 07:43:05.469683 Sending with 10 millisecond of delay
408 07:43:07.086381 => setenv fdt_high 0xffffffff
409 07:43:07.097151 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:39)
410 07:43:07.098028 setenv fdt_high 0xffffffff
411 07:43:07.098742 Sending with 10 millisecond of delay
413 07:43:07.390492 => dhcp
414 07:43:07.401204 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:38)
415 07:43:07.402061 dhcp
416 07:43:07.402796 link up on port 0, speed 100, full duplex
417 07:43:07.403221 BOOTP broadcast 1
418 07:43:07.698625 BOOTP broadcast 2
419 07:43:08.157757 BOOTP broadcast 3
420 07:43:09.159092 BOOTP broadcast 4
421 07:43:09.237632 DHCP client bound to address 192.168.6.8 (1831 ms)
422 07:43:09.238454 Sending with 10 millisecond of delay
424 07:43:10.915195 => setenv serverip 192.168.6.3
425 07:43:10.926251 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:35)
426 07:43:10.927334 setenv serverip 192.168.6.3
427 07:43:10.928260 Sending with 10 millisecond of delay
429 07:43:14.413147 => tftp 0x82000000 978505/tftp-deploy-as9cs3pz/kernel/zImage
430 07:43:14.423942 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:31)
431 07:43:14.424878 tftp 0x82000000 978505/tftp-deploy-as9cs3pz/kernel/zImage
432 07:43:14.425310 link up on port 0, speed 100, full duplex
433 07:43:14.428702 Using ethernet@4a100000 device
434 07:43:14.434340 TFTP from server 192.168.6.3; our IP address is 192.168.6.8
435 07:43:14.441346 Filename '978505/tftp-deploy-as9cs3pz/kernel/zImage'.
436 07:43:14.441845 Load address: 0x82000000
437 07:43:16.592222 Loading: *################################################## 11 MiB
438 07:43:16.592611 5.1 MiB/s
439 07:43:16.592831 done
440 07:43:16.596299 Bytes transferred = 11514368 (afb200 hex)
441 07:43:16.596800 Sending with 10 millisecond of delay
443 07:43:21.044744 => tftp 0x83000000 978505/tftp-deploy-as9cs3pz/ramdisk/ramdisk.cpio.gz.uboot
444 07:43:21.055572 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:25)
445 07:43:21.056453 tftp 0x83000000 978505/tftp-deploy-as9cs3pz/ramdisk/ramdisk.cpio.gz.uboot
446 07:43:21.056880 link up on port 0, speed 100, full duplex
447 07:43:21.060354 Using ethernet@4a100000 device
448 07:43:21.065873 TFTP from server 192.168.6.3; our IP address is 192.168.6.8
449 07:43:21.074596 Filename '978505/tftp-deploy-as9cs3pz/ramdisk/ramdisk.cpio.gz.uboot'.
450 07:43:21.075095 Load address: 0x83000000
451 07:43:23.904976 Loading: *################################################## 14.1 MiB
452 07:43:23.905404 5 MiB/s
453 07:43:23.905619 done
454 07:43:23.909059 Bytes transferred = 14831541 (e24fb5 hex)
455 07:43:23.909581 Sending with 10 millisecond of delay
457 07:43:25.766169 => setenv initrd_size ${filesize}
458 07:43:25.776736 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:20)
459 07:43:25.777250 setenv initrd_size ${filesize}
460 07:43:25.777709 Sending with 10 millisecond of delay
462 07:43:29.921920 => tftp 0x88000000 978505/tftp-deploy-as9cs3pz/dtb/am335x-boneblack.dtb
463 07:43:29.932931 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:16)
464 07:43:29.933846 tftp 0x88000000 978505/tftp-deploy-as9cs3pz/dtb/am335x-boneblack.dtb
465 07:43:29.934320 link up on port 0, speed 100, full duplex
466 07:43:29.937187 Using ethernet@4a100000 device
467 07:43:29.942766 TFTP from server 192.168.6.3; our IP address is 192.168.6.8
468 07:43:29.955818 Filename '978505/tftp-deploy-as9cs3pz/dtb/am335x-boneblack.dtb'.
469 07:43:29.956353 Load address: 0x88000000
470 07:43:29.963590 Loading: *################################################## 68.9 KiB
471 07:43:29.973117 4.5 MiB/s
472 07:43:29.973602 done
473 07:43:29.974065 Bytes transferred = 70544 (11390 hex)
474 07:43:29.974757 Sending with 10 millisecond of delay
476 07:43:43.150112 => setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.3:/var/lib/lava/dispatcher/tmp/978505/extract-nfsrootfs-kr0x50hc,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
477 07:43:43.160893 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:02)
478 07:43:43.161740 setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.3:/var/lib/lava/dispatcher/tmp/978505/extract-nfsrootfs-kr0x50hc,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
479 07:43:43.162500 Sending with 10 millisecond of delay
481 07:43:45.501238 => bootz 0x82000000 0x83000000 0x88000000
482 07:43:45.512145 Setting prompt string to ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
483 07:43:45.512710 bootloader-commands: Wait for prompt ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:00)
484 07:43:45.513682 bootz 0x82000000 0x83000000 0x88000000
485 07:43:45.514168 Kernel image @ 0x82000000 [ 0x000000 - 0xafb200 ]
486 07:43:45.514662 ## Loading init Ramdisk from Legacy Image at 83000000 ...
487 07:43:45.519636 Image Name:
488 07:43:45.520071 Created: 2024-11-12 7:42:45 UTC
489 07:43:45.528660 Image Type: ARM Linux RAMDisk Image (uncompressed)
490 07:43:45.529096 Data Size: 14831477 Bytes = 14.1 MiB
491 07:43:45.536971 Load Address: 00000000
492 07:43:45.537404 Entry Point: 00000000
493 07:43:45.705703 Verifying Checksum ... OK
494 07:43:45.706252 ## Flattened Device Tree blob at 88000000
495 07:43:45.712305 Booting using the fdt blob at 0x88000000
496 07:43:45.712748 Working FDT set to 88000000
497 07:43:45.717864 Using Device Tree in place at 88000000, end 8801438f
498 07:43:45.722288 Working FDT set to 88000000
499 07:43:45.735741
500 07:43:45.736181 Starting kernel ...
501 07:43:45.736584
502 07:43:45.737451 end: 2.4.3 bootloader-commands (duration 00:00:43) [common]
503 07:43:45.738067 start: 2.4.4 auto-login-action (timeout 00:04:00) [common]
504 07:43:45.738524 Setting prompt string to ['Linux version [0-9]']
505 07:43:45.738976 Setting prompt string to ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
506 07:43:45.739430 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:05:00)
507 07:43:46.585234 [ 0.000000] Booting Linux on physical CPU 0x0
508 07:43:46.591317 start: 2.4.4.1 login-action (timeout 00:03:59) [common]
509 07:43:46.591854 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
510 07:43:46.592324 Setting prompt string to []
511 07:43:46.592825 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
512 07:43:46.593285 Using line separator: #'\n'#
513 07:43:46.593692 No login prompt set.
514 07:43:46.594162 Parsing kernel messages
515 07:43:46.594561 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
516 07:43:46.595367 [login-action] Waiting for messages, (timeout 00:03:59)
517 07:43:46.595806 Waiting using forced prompt support (timeout 00:02:00)
518 07:43:46.607924 [ 0.000000] Linux version 6.12.0-rc7-next-20241112 (KernelCI@build-j373744-arm-gcc-12-multi-v7-defconfig-ztj4f) (arm-linux-gnueabihf-gcc (Debian 12.2.0-14) 12.2.0, GNU ld (GNU Binutils for Debian) 2.40) #1 SMP Tue Nov 12 07:21:30 UTC 2024
519 07:43:46.613629 [ 0.000000] CPU: ARMv7 Processor [413fc082] revision 2 (ARMv7), cr=10c5387d
520 07:43:46.625065 [ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
521 07:43:46.630886 [ 0.000000] OF: fdt: Machine model: TI AM335x BeagleBone Black
522 07:43:46.636537 [ 0.000000] earlycon: omap8250 at MMIO 0x44e09000 (options '')
523 07:43:46.642286 [ 0.000000] printk: legacy bootconsole [omap8250] enabled
524 07:43:46.648932 [ 0.000000] Memory policy: Data cache writeback
525 07:43:46.649360 [ 0.000000] efi: UEFI not found.
526 07:43:46.657713 [ 0.000000] cma: Reserved 64 MiB at 0x9b800000 on node -1
527 07:43:46.663477 [ 0.000000] Zone ranges:
528 07:43:46.669180 [ 0.000000] DMA [mem 0x0000000080000000-0x000000009fdfffff]
529 07:43:46.669610 [ 0.000000] Normal empty
530 07:43:46.674906 [ 0.000000] HighMem empty
531 07:43:46.675336 [ 0.000000] Movable zone start for each node
532 07:43:46.680672 [ 0.000000] Early memory node ranges
533 07:43:46.686384 [ 0.000000] node 0: [mem 0x0000000080000000-0x000000009fdfffff]
534 07:43:46.694399 [ 0.000000] Initmem setup node 0 [mem 0x0000000080000000-0x000000009fdfffff]
535 07:43:46.716983 [ 0.000000] OF: reserved mem: Reserved memory: No reserved-memory node in the DT
536 07:43:46.729315 [ 0.000000] CPU: All CPU(s) started in SVC mode.
537 07:43:46.735006 [ 0.000000] AM335X ES2.0 (sgx neon)
538 07:43:46.746690 [ 0.000000] percpu: Embedded 17 pages/cpu s40140 r8192 d21300 u69632
539 07:43:46.764191 [ 0.000000] Kernel command line: console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.3:/var/lib/lava/dispatcher/tmp/978505/extract-nfsrootfs-kr0x50hc,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp
540 07:43:46.775859 <6>[ 0.000000] printk: log buffer data + meta data: 131072 + 409600 = 540672 bytes
541 07:43:46.781705 <6>[ 0.000000] Dentry cache hash table entries: 65536 (order: 6, 262144 bytes, linear)
542 07:43:46.793044 <6>[ 0.000000] Inode-cache hash table entries: 32768 (order: 5, 131072 bytes, linear)
543 07:43:46.799031 <6>[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 130560
544 07:43:46.804218 <6>[ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
545 07:43:46.834158 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
546 07:43:46.840121 <6>[ 0.000000] trace event string verifier disabled
547 07:43:46.840543 <6>[ 0.000000] rcu: Hierarchical RCU implementation.
548 07:43:46.845980 <6>[ 0.000000] rcu: RCU event tracing is enabled.
549 07:43:46.857300 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=16 to nr_cpu_ids=1.
550 07:43:46.857727 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
551 07:43:46.868747 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 10 jiffies.
552 07:43:46.874543 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=1
553 07:43:46.884845 <6>[ 0.000000] RCU Tasks Trace: Setting shift to 0 and lim to 1 rcu_task_cb_adjust=1 rcu_task_cpu_ids=1.
554 07:43:46.899422 <6>[ 0.000000] NR_IRQS: 16, nr_irqs: 16, preallocated irqs: 16
555 07:43:46.917798 <6>[ 0.000000] IRQ: Found an INTC at 0x(ptrval) (revision 5.0) with 128 interrupts
556 07:43:46.923535 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
557 07:43:47.016823 <6>[ 0.000000] TI gptimer clocksource: always-on /ocp/interconnect@44c00000/segment@200000/target-module@31000
558 07:43:47.025274 <6>[ 0.000003] sched_clock: 32 bits at 24MHz, resolution 41ns, wraps every 89478484971ns
559 07:43:47.037839 <6>[ 0.008338] clocksource: dmtimer: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 79635851949 ns
560 07:43:47.046035 <6>[ 0.019158] TI gptimer clockevent: 24000000 Hz at /ocp/interconnect@48000000/segment@0/target-module@40000
561 07:43:47.055396 <6>[ 0.034032] Console: colour dummy device 80x30
562 07:43:47.061466 Matched prompt #6: WARNING:
563 07:43:47.061965 Setting prompt string to ['end trace[^\\r]*\\r', '/ #', 'Login timed out', 'Login incorrect']
564 07:43:47.066955 <3>[ 0.038931] WARNING: Your 'console=ttyO0' has been replaced by 'ttyS0'
565 07:43:47.072594 <3>[ 0.046004] This ensures that you still see kernel messages. Please
566 07:43:47.075832 <3>[ 0.052731] update your kernel commandline.
567 07:43:47.116460 <6>[ 0.057343] Calibrating delay loop... 996.14 BogoMIPS (lpj=4980736)
568 07:43:47.122226 <6>[ 0.096166] CPU: Testing write buffer coherency: ok
569 07:43:47.125008 <6>[ 0.101539] CPU0: Spectre v2: using BPIALL workaround
570 07:43:47.130985 <6>[ 0.107001] pid_max: default: 32768 minimum: 301
571 07:43:47.136780 <6>[ 0.112198] Mount-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
572 07:43:47.149365 <6>[ 0.120014] Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
573 07:43:47.156652 <6>[ 0.129385] CPU0: thread -1, cpu 0, socket -1, mpidr 0
574 07:43:47.165007 <6>[ 0.136559] Setting up static identity map for 0x80300000 - 0x803000ac
575 07:43:47.171004 <6>[ 0.146224] rcu: Hierarchical SRCU implementation.
576 07:43:47.175746 <6>[ 0.151510] rcu: Max phase no-delay instances is 1000.
577 07:43:47.184242 <6>[ 0.162613] EFI services will not be available.
578 07:43:47.190057 <6>[ 0.167890] smp: Bringing up secondary CPUs ...
579 07:43:47.195760 <6>[ 0.172940] smp: Brought up 1 node, 1 CPU
580 07:43:47.201584 <6>[ 0.177343] SMP: Total of 1 processors activated (996.14 BogoMIPS).
581 07:43:47.207474 <6>[ 0.184113] CPU: All CPU(s) started in SVC mode.
582 07:43:47.227871 <6>[ 0.189302] Memory: 405936K/522240K available (16384K kernel code, 2541K rwdata, 6828K rodata, 2048K init, 429K bss, 49108K reserved, 65536K cma-reserved, 0K highmem)
583 07:43:47.228336 <6>[ 0.205608] devtmpfs: initialized
584 07:43:47.250129 <6>[ 0.222726] VFP support v0.3: implementor 41 architecture 3 part 30 variant c rev 3
585 07:43:47.261646 <6>[ 0.231316] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
586 07:43:47.267587 <6>[ 0.241776] futex hash table entries: 256 (order: 2, 16384 bytes, linear)
587 07:43:47.278336 <6>[ 0.254117] pinctrl core: initialized pinctrl subsystem
588 07:43:47.287766 <6>[ 0.264822] DMI not present or invalid.
589 07:43:47.296144 <6>[ 0.270682] NET: Registered PF_NETLINK/PF_ROUTE protocol family
590 07:43:47.304920 <6>[ 0.279741] DMA: preallocated 256 KiB pool for atomic coherent allocations
591 07:43:47.320823 <6>[ 0.291291] thermal_sys: Registered thermal governor 'step_wise'
592 07:43:47.321286 <6>[ 0.291460] cpuidle: using governor menu
593 07:43:47.365267 <6>[ 0.325667] /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70: Fixed dependency cycle(s) with /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
594 07:43:47.379897 <6>[ 0.344480] /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
595 07:43:47.386424 <6>[ 0.365170] No ATAGs?
596 07:43:47.392627 <6>[ 0.367806] hw-breakpoint: debug architecture 0x4 unsupported.
597 07:43:47.403080 <6>[ 0.379902] Serial: AMBA PL011 UART driver
598 07:43:47.437023 <6>[ 0.415608] iommu: Default domain type: Translated
599 07:43:47.445191 <6>[ 0.420956] iommu: DMA domain TLB invalidation policy: strict mode
600 07:43:47.472835 <5>[ 0.450806] SCSI subsystem initialized
601 07:43:47.478695 <6>[ 0.455690] usbcore: registered new interface driver usbfs
602 07:43:47.484412 <6>[ 0.461729] usbcore: registered new interface driver hub
603 07:43:47.493181 <6>[ 0.467509] usbcore: registered new device driver usb
604 07:43:47.499087 <6>[ 0.474048] pps_core: LinuxPPS API ver. 1 registered
605 07:43:47.504900 <6>[ 0.479485] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
606 07:43:47.510730 <6>[ 0.489169] PTP clock support registered
607 07:43:47.515814 <6>[ 0.493633] EDAC MC: Ver: 3.0.0
608 07:43:47.563451 <6>[ 0.540448] scmi_core: SCMI protocol bus registered
609 07:43:47.579619 <6>[ 0.557892] vgaarb: loaded
610 07:43:47.592285 <6>[ 0.570970] clocksource: Switched to clocksource dmtimer
611 07:43:47.629308 <6>[ 0.607577] NET: Registered PF_INET protocol family
612 07:43:47.641917 <6>[ 0.613277] IP idents hash table entries: 8192 (order: 4, 65536 bytes, linear)
613 07:43:47.649106 <6>[ 0.622159] tcp_listen_portaddr_hash hash table entries: 512 (order: 0, 4096 bytes, linear)
614 07:43:47.660498 <6>[ 0.631052] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
615 07:43:47.666424 <6>[ 0.639338] TCP established hash table entries: 4096 (order: 2, 16384 bytes, linear)
616 07:43:47.672190 <6>[ 0.647631] TCP bind hash table entries: 4096 (order: 4, 65536 bytes, linear)
617 07:43:47.678158 <6>[ 0.655351] TCP: Hash tables configured (established 4096 bind 4096)
618 07:43:47.689481 <6>[ 0.662278] UDP hash table entries: 256 (order: 1, 8192 bytes, linear)
619 07:43:47.695444 <6>[ 0.669291] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes, linear)
620 07:43:47.701653 <6>[ 0.676901] NET: Registered PF_UNIX/PF_LOCAL protocol family
621 07:43:47.778874 <6>[ 0.751845] RPC: Registered named UNIX socket transport module.
622 07:43:47.779431 <6>[ 0.758229] RPC: Registered udp transport module.
623 07:43:47.784705 <6>[ 0.763370] RPC: Registered tcp transport module.
624 07:43:47.793229 <6>[ 0.768476] RPC: Registered tcp-with-tls transport module.
625 07:43:47.799180 <6>[ 0.774404] RPC: Registered tcp NFSv4.1 backchannel transport module.
626 07:43:47.806262 <6>[ 0.781312] PCI: CLS 0 bytes, default 64
627 07:43:47.808601 <5>[ 0.787093] Initialise system trusted keyrings
628 07:43:47.831063 <6>[ 0.807345] Trying to unpack rootfs image as initramfs...
629 07:43:47.909765 <6>[ 0.882125] workingset: timestamp_bits=30 max_order=17 bucket_order=0
630 07:43:47.913614 <6>[ 0.889643] squashfs: version 4.0 (2009/01/31) Phillip Lougher
631 07:43:47.954373 <5>[ 0.932931] NFS: Registering the id_resolver key type
632 07:43:47.960261 <5>[ 0.938523] Key type id_resolver registered
633 07:43:47.966199 <5>[ 0.943215] Key type id_legacy registered
634 07:43:47.971802 <6>[ 0.947656] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
635 07:43:47.980366 <6>[ 0.954875] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
636 07:43:48.053971 <5>[ 1.032453] Key type asymmetric registered
637 07:43:48.059784 <5>[ 1.036980] Asymmetric key parser 'x509' registered
638 07:43:48.068176 <6>[ 1.042469] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 246)
639 07:43:48.073956 <6>[ 1.050355] io scheduler mq-deadline registered
640 07:43:48.082674 <6>[ 1.055320] io scheduler kyber registered
641 07:43:48.083229 <6>[ 1.059773] io scheduler bfq registered
642 07:43:48.187264 <6>[ 1.162155] ledtrig-cpu: registered to indicate activity on CPUs
643 07:43:48.492079 <6>[ 1.466733] Serial: 8250/16550 driver, 5 ports, IRQ sharing enabled
644 07:43:48.527756 <6>[ 1.506132] msm_serial: driver initialized
645 07:43:48.533892 <6>[ 1.510928] SuperH (H)SCI(F) driver initialized
646 07:43:48.539799 <6>[ 1.516237] STMicroelectronics ASC driver initialized
647 07:43:48.545084 <6>[ 1.521917] STM32 USART driver initialized
648 07:43:48.657956 <6>[ 1.635861] brd: module loaded
649 07:43:48.693025 <6>[ 1.671864] loop: module loaded
650 07:43:48.721735 <6>[ 1.699315] CAN device driver interface
651 07:43:48.728279 <6>[ 1.704637] bgmac_bcma: Broadcom 47xx GBit MAC driver loaded
652 07:43:48.734107 <6>[ 1.711577] e1000e: Intel(R) PRO/1000 Network Driver
653 07:43:48.740788 <6>[ 1.717048] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
654 07:43:48.746556 <6>[ 1.723502] igb: Intel(R) Gigabit Ethernet Network Driver
655 07:43:48.753933 <6>[ 1.729331] igb: Copyright (c) 2007-2014 Intel Corporation.
656 07:43:48.765690 <6>[ 1.738574] pegasus: Pegasus/Pegasus II USB Ethernet driver
657 07:43:48.771550 <6>[ 1.744740] usbcore: registered new interface driver pegasus
658 07:43:48.777460 <6>[ 1.750880] usbcore: registered new interface driver asix
659 07:43:48.783178 <6>[ 1.756771] usbcore: registered new interface driver ax88179_178a
660 07:43:48.789010 <6>[ 1.763360] usbcore: registered new interface driver cdc_ether
661 07:43:48.795044 <6>[ 1.769658] usbcore: registered new interface driver smsc75xx
662 07:43:48.800571 <6>[ 1.775887] usbcore: registered new interface driver smsc95xx
663 07:43:48.807099 <6>[ 1.782119] usbcore: registered new interface driver net1080
664 07:43:48.812421 <6>[ 1.788243] usbcore: registered new interface driver cdc_subset
665 07:43:48.818006 <6>[ 1.794657] usbcore: registered new interface driver zaurus
666 07:43:48.825404 <6>[ 1.800699] usbcore: registered new interface driver cdc_ncm
667 07:43:48.834250 <6>[ 1.810162] usbcore: registered new interface driver usb-storage
668 07:43:48.843587 <6>[ 1.821232] i2c_dev: i2c /dev entries driver
669 07:43:48.864856 <5>[ 1.840073] cpuidle: enable-method property 'ti,am3352' found operations
670 07:43:48.878617 <6>[ 1.849600] sdhci: Secure Digital Host Controller Interface driver
671 07:43:48.879203 <6>[ 1.856357] sdhci: Copyright(c) Pierre Ossman
672 07:43:48.885306 <6>[ 1.862995] Synopsys Designware Multimedia Card Interface Driver
673 07:43:48.894861 <6>[ 1.870858] sdhci-pltfm: SDHCI platform and OF driver helper
674 07:43:48.909843 <6>[ 1.880839] usbcore: registered new interface driver usbhid
675 07:43:48.910517 <6>[ 1.886957] usbhid: USB HID core driver
676 07:43:48.921781 <6>[ 1.898728] NET: Registered PF_INET6 protocol family
677 07:43:49.384996 <6>[ 2.363609] Segment Routing with IPv6
678 07:43:49.390847 <6>[ 2.367762] In-situ OAM (IOAM) with IPv6
679 07:43:49.397548 <6>[ 2.372281] sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver
680 07:43:49.405166 <6>[ 2.379617] NET: Registered PF_PACKET protocol family
681 07:43:49.410896 <6>[ 2.385193] can: controller area network core
682 07:43:49.411448 <6>[ 2.390019] NET: Registered PF_CAN protocol family
683 07:43:49.416638 <6>[ 2.395244] can: raw protocol
684 07:43:49.422372 <6>[ 2.398573] can: broadcast manager protocol
685 07:43:49.429334 <6>[ 2.403169] can: netlink gateway - max_hops=1
686 07:43:49.430068 <5>[ 2.408664] Key type dns_resolver registered
687 07:43:49.435239 <6>[ 2.413735] ThumbEE CPU extension supported.
688 07:43:49.441336 <5>[ 2.418419] Registering SWP/SWPB emulation handler
689 07:43:49.448607 <3>[ 2.424119] omap_voltage_late_init: Voltage driver support not added
690 07:43:49.664993 <5>[ 2.642129] Loading compiled-in X.509 certificates
691 07:43:49.737287 <6>[ 2.700370] /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70: Fixed dependency cycle(s) with /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
692 07:43:49.766189 <6>[ 2.729913] /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70: Fixed dependency cycle(s) with /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
693 07:43:49.916153 <6>[ 2.880570] /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70: Fixed dependency cycle(s) with /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
694 07:43:49.936665 <6>[ 2.900210] /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70: Fixed dependency cycle(s) with /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
695 07:43:49.963273 <6>[ 2.926775] /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800/clkout2-pins
696 07:43:49.973147 <6>[ 2.948322] pinctrl-single 44e10800.pinmux: 142 pins, size 568
697 07:43:49.999947 <3>[ 2.972470] ti-sysc 44e31000.target-module: probe with driver ti-sysc failed with error -16
698 07:43:50.272645 <6>[ 3.236485] /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
699 07:43:50.298692 <3>[ 3.271468] ti-sysc 48040000.target-module: probe with driver ti-sysc failed with error -16
700 07:43:50.525923 <6>[ 3.502781] OMAP GPIO hardware version 0.1
701 07:43:50.546558 <6>[ 3.521573] omap-mailbox 480c8000.mailbox: omap mailbox rev 0x400
702 07:43:50.648756 <4>[ 3.623423] at24 2-0054: supply vcc not found, using dummy regulator
703 07:43:50.685400 <4>[ 3.660043] at24 2-0055: supply vcc not found, using dummy regulator
704 07:43:50.722842 <4>[ 3.697570] at24 2-0056: supply vcc not found, using dummy regulator
705 07:43:50.762137 <4>[ 3.736826] at24 2-0057: supply vcc not found, using dummy regulator
706 07:43:50.800293 <6>[ 3.775758] omap_i2c 4819c000.i2c: bus 2 rev0.11 at 100 kHz
707 07:43:50.853691 <3>[ 3.825185] 48000000.interconnect:segment@200000:target-module@0:mpu@0:fck: device ID is greater than 24
708 07:43:50.875741 <6>[ 3.839510] /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
709 07:43:50.902867 <6>[ 3.862964] /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
710 07:43:50.920249 <6>[ 3.882209] /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70: Fixed dependency cycle(s) with /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
711 07:43:50.936412 <6>[ 3.900151] /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
712 07:43:50.957084 <4>[ 3.930528] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
713 07:43:50.986691 <6>[ 3.964792] Freeing initrd memory: 14484K
714 07:43:50.996145 <4>[ 3.969626] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
715 07:43:51.030715 <6>[ 4.005481] omap_rng 48310000.rng: Random Number Generator ver. 20
716 07:43:51.054712 <5>[ 4.032281] random: crng init done
717 07:43:51.108412 <6>[ 4.081779] davinci_mdio 4a101000.mdio: davinci mdio revision 1.6, bus freq 1000000
718 07:43:51.191679 <6>[ 4.164166] davinci_mdio 4a101000.mdio: phy[0]: device 4a101000.mdio:00, driver SMSC LAN8710/LAN8720
719 07:43:51.197640 <6>[ 4.174473] cpsw-switch 4a100000.switch: initialized cpsw ale version 1.4
720 07:43:51.209308 <6>[ 4.181811] cpsw-switch 4a100000.switch: ALE Table size 1024, Policers 0
721 07:43:51.215049 <6>[ 4.189275] cpsw-switch 4a100000.switch: cpts: overflow check period 500 (jiffies)
722 07:43:51.226640 <6>[ 4.197410] cpsw-switch 4a100000.switch: CPTS: ref_clk_freq:250000000 calc_mult:2147483648 calc_shift:29 error:0 nsec/sec
723 07:43:51.234040 <6>[ 4.209056] cpsw-switch 4a100000.switch: Detected MACID = 90:59:af:5b:00:92
724 07:43:51.247223 <5>[ 4.218099] cpsw-switch 4a100000.switch: initialized (regs 0x4a100000, pool size 256) hw_ver:0019010C 1.12 (0)
725 07:43:51.275115 <3>[ 4.248078] debugfs: Directory '49000000.dma' with parent 'dmaengine' already present!
726 07:43:51.279937 <6>[ 4.256690] edma 49000000.dma: TI EDMA DMA engine driver
727 07:43:51.352727 <3>[ 4.324802] target-module@4b000000:target-module@140000:pmu@0:fck: device ID is greater than 24
728 07:43:51.367276 <6>[ 4.339159] hw perfevents: enabled with armv7_cortex_a8 PMU driver, 5 (8000000f) counters available
729 07:43:51.379266 <3>[ 4.356238] l3-aon-clkctrl:0000:0: failed to disable
730 07:43:51.430037 <6>[ 4.402898] 44e09000.serial: ttyS0 at MMIO 0x44e09000 (irq = 36, base_baud = 3000000) is a 8250
731 07:43:51.435856 <6>[ 4.412370] printk: legacy console [ttyS0] enabled
732 07:43:51.438570 <6>[ 4.412370] printk: legacy console [ttyS0] enabled
733 07:43:51.449695 <6>[ 4.422704] printk: legacy bootconsole [omap8250] disabled
734 07:43:51.452980 <6>[ 4.422704] printk: legacy bootconsole [omap8250] disabled
735 07:43:51.490661 <4>[ 4.462538] tps65217-pmic: Failed to locate of_node [id: -1]
736 07:43:51.493381 <4>[ 4.469923] tps65217-bl: Failed to locate of_node [id: -1]
737 07:43:51.510734 <6>[ 4.489592] tps65217 0-0024: TPS65217 ID 0xe version 1.2
738 07:43:51.531101 <6>[ 4.496553] /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
739 07:43:51.548560 <6>[ 4.514199] /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70: Fixed dependency cycle(s) with /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
740 07:43:51.556178 <6>[ 4.532051] omap_i2c 44e0b000.i2c: bus 0 rev0.11 at 400 kHz
741 07:43:51.579072 <6>[ 4.552140] omap_gpio 44e07000.gpio: Could not set line 6 debounce to 200000 microseconds (-22)
742 07:43:51.584965 <6>[ 4.561197] sdhci-omap 48060000.mmc: Got CD GPIO
743 07:43:51.593063 <4>[ 4.566391] sdhci-omap 48060000.mmc: supply pbias not found, using dummy regulator
744 07:43:51.607685 <4>[ 4.580050] sdhci-omap 48060000.mmc: supply vqmmc not found, using dummy regulator
745 07:43:51.614123 <4>[ 4.588847] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
746 07:43:51.623403 <4>[ 4.597543] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
747 07:43:51.696864 <6>[ 4.672106] at24 0-0050: 32768 byte 24c256 EEPROM, writable, 1 bytes/write
748 07:43:51.732008 <6>[ 4.705393] mmc0: SDHCI controller on 48060000.mmc [48060000.mmc] using External DMA
749 07:43:51.752658 <6>[ 4.724996] mmc1: SDHCI controller on 481d8000.mmc [481d8000.mmc] using External DMA
750 07:43:51.759350 <6>[ 4.733911] cpsw-switch 4a100000.switch: starting ndev. mode: dual_mac
751 07:43:51.829722 <6>[ 4.798969] mmc1: new high speed MMC card at address 0001
752 07:43:51.830407 <6>[ 4.806347] mmcblk1: mmc1:0001 MMC02G 1.79 GiB
753 07:43:51.840539 <6>[ 4.816469] mmcblk1boot0: mmc1:0001 MMC02G 1.00 MiB
754 07:43:51.847279 <6>[ 4.824531] mmcblk1boot1: mmc1:0001 MMC02G 1.00 MiB
755 07:43:51.859744 <6>[ 4.830828] SMSC LAN8710/LAN8720 4a101000.mdio:00: attached PHY driver (mii_bus:phy_addr=4a101000.mdio:00, irq=POLL)
756 07:43:51.868997 <6>[ 4.843866] mmcblk1rpmb: mmc1:0001 MMC02G 128 KiB, chardev (236:0)
757 07:43:51.934437 <6>[ 4.902589] mmc0: new high speed SDHC card at address aaaa
758 07:43:51.935037 <6>[ 4.911121] mmcblk0: mmc0:aaaa SU16G 14.8 GiB
759 07:43:51.968445 <6>[ 4.945014] mmcblk0: p1 p2 p3 p4 < p5 p6 p7 >
760 07:43:53.970203 <6>[ 6.942806] cpsw-switch 4a100000.switch eth0: Link is Up - 100Mbps/Full - flow control off
761 07:43:54.093421 <5>[ 6.971763] Sending DHCP requests ., OK
762 07:43:54.104681 <6>[ 7.076239] IP-Config: Got DHCP answer from 192.168.6.1, my address is 192.168.6.8
763 07:43:54.105355 <6>[ 7.084275] IP-Config: Complete:
764 07:43:54.119117 <6>[ 7.087812] device=eth0, hwaddr=90:59:af:5b:00:92, ipaddr=192.168.6.8, mask=255.255.255.0, gw=192.168.6.1
765 07:43:54.124827 <6>[ 7.098266] host=192.168.6.8, domain=, nis-domain=(none)
766 07:43:54.130419 <6>[ 7.104391] bootserver=192.168.6.1, rootserver=192.168.6.3, rootpath=
767 07:43:54.137442 <6>[ 7.104427] nameserver0=10.255.253.1
768 07:43:54.137995 <6>[ 7.116990] clk: Disabling unused clocks
769 07:43:54.145600 <6>[ 7.121591] PM: genpd: Disabling unused power domains
770 07:43:54.165256 <6>[ 7.140311] Freeing unused kernel image (initmem) memory: 2048K
771 07:43:54.172914 <6>[ 7.150362] Run /init as init process
772 07:43:54.195220 Loading, please wait...
773 07:43:54.271831 Starting systemd-udevd version 252.22-1~deb12u1
774 07:43:57.348074 <4>[ 10.319645] am335x-phy-driver 47401300.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
775 07:43:57.492935 <4>[ 10.464515] am335x-phy-driver 47401b00.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
776 07:43:57.671627 <6>[ 10.650641] musb-hdrc musb-hdrc.1: MUSB HDRC host driver
777 07:43:57.682695 <6>[ 10.656465] musb-hdrc musb-hdrc.1: new USB bus registered, assigned bus number 1
778 07:43:57.935219 <6>[ 10.912182] hub 1-0:1.0: USB hub found
779 07:43:57.965576 <6>[ 10.942753] hub 1-0:1.0: 1 port detected
780 07:43:58.167078 <6>[ 11.143826] tda998x 0-0070: found TDA19988
781 07:44:01.167975 Begin: Loading essential drivers ... done.
782 07:44:01.173399 Begin: Running /scripts/init-premount ... done.
783 07:44:01.179030 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
784 07:44:01.189564 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
785 07:44:01.194539 Device /sys/class/net/eth0 found
786 07:44:01.195042 done.
787 07:44:01.275134 Begin: Waiting up to 180 secs for any network device to become available ... done.
788 07:44:01.346071 IP-Config: eth0 hardware address 90:59:af:5b:00:92 mtu 1500 DHCP
789 07:44:01.465748 IP-Config: eth0 guessed broadcast address 192.168.6.255
790 07:44:01.471312 IP-Config: eth0 complete (dhcp from 192.168.6.1):
791 07:44:01.476981 address: 192.168.6.8 broadcast: 192.168.6.255 netmask: 255.255.255.0
792 07:44:01.485857 gateway: 192.168.6.1 dns0 : 10.255.253.1 dns1 : 0.0.0.0
793 07:44:01.491714 rootserver: 192.168.6.1 rootpath:
794 07:44:01.492299 filename :
795 07:44:01.577584 done.
796 07:44:01.588424 Begin: Running /scripts/nfs-bottom ... done.
797 07:44:01.660076 Begin: Running /scripts/init-bottom ... done.
798 07:44:03.128504 <30>[ 16.103049] systemd[1]: System time before build time, advancing clock.
799 07:44:03.323120 <30>[ 16.270467] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
800 07:44:03.326830 <30>[ 16.304314] systemd[1]: Detected architecture arm.
801 07:44:03.339994
802 07:44:03.340524 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
803 07:44:03.341002
804 07:44:03.365791 <30>[ 16.341128] systemd[1]: Hostname set to <debian-bookworm-armhf>.
805 07:44:05.481011 <30>[ 18.455182] systemd[1]: Queued start job for default target graphical.target.
806 07:44:05.497666 <30>[ 18.469827] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
807 07:44:05.505305 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
808 07:44:05.536136 <30>[ 18.507883] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
809 07:44:05.543743 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
810 07:44:05.575433 <30>[ 18.548057] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
811 07:44:05.588443 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
812 07:44:05.610592 <30>[ 18.583598] systemd[1]: Created slice user.slice - User and Session Slice.
813 07:44:05.617351 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
814 07:44:05.646237 <30>[ 18.613131] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
815 07:44:05.652367 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
816 07:44:05.670162 <30>[ 18.642905] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
817 07:44:05.678128 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
818 07:44:05.711253 <30>[ 18.673009] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
819 07:44:05.717726 <30>[ 18.693489] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
820 07:44:05.726260 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
821 07:44:05.749273 <30>[ 18.722273] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
822 07:44:05.757524 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
823 07:44:05.780032 <30>[ 18.752673] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
824 07:44:05.787815 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
825 07:44:05.809844 <30>[ 18.782729] systemd[1]: Reached target paths.target - Path Units.
826 07:44:05.814029 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
827 07:44:05.839464 <30>[ 18.812440] systemd[1]: Reached target remote-fs.target - Remote File Systems.
828 07:44:05.846897 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
829 07:44:05.869273 <30>[ 18.842249] systemd[1]: Reached target slices.target - Slice Units.
830 07:44:05.874766 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
831 07:44:05.899723 <30>[ 18.872691] systemd[1]: Reached target swap.target - Swaps.
832 07:44:05.903828 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
833 07:44:05.930726 <30>[ 18.903760] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
834 07:44:05.942829 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
835 07:44:05.971322 <30>[ 18.943076] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
836 07:44:05.978246 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
837 07:44:06.058294 <30>[ 19.026217] systemd[1]: systemd-journald-audit.socket - Journal Audit Socket was skipped because of an unmet condition check (ConditionSecurity=audit).
838 07:44:06.071026 <30>[ 19.043830] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
839 07:44:06.079481 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
840 07:44:06.102642 <30>[ 19.074508] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
841 07:44:06.109353 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
842 07:44:06.132051 <30>[ 19.104814] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
843 07:44:06.140256 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
844 07:44:06.165336 <30>[ 19.136784] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
845 07:44:06.170951 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
846 07:44:06.198984 <30>[ 19.173465] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
847 07:44:06.211001 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
848 07:44:06.236860 <30>[ 19.203604] systemd[1]: dev-hugepages.mount - Huge Pages File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/mm/hugepages).
849 07:44:06.255569 <30>[ 19.222187] systemd[1]: dev-mqueue.mount - POSIX Message Queue File System was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/mqueue).
850 07:44:06.299883 <30>[ 19.273480] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
851 07:44:06.319458 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
852 07:44:06.356766 <30>[ 19.330290] systemd[1]: Mounting sys-kernel-tracing.mount - Kernel Trace File System...
853 07:44:06.381549 Mounting [0;1;39msys-kernel-tracin…[0m - Kernel Trace File System...
854 07:44:06.737731 <30>[ 19.419165] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
855 07:44:06.738450 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
856 07:44:06.739045 <30>[ 19.503338] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
857 07:44:06.739525 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
858 07:44:06.740059 <30>[ 19.583584] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
859 07:44:06.740596 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
860 07:44:06.741119 <30>[ 19.655137] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
861 07:44:06.742618 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
862 07:44:06.750169 <30>[ 19.723007] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
863 07:44:06.778232 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
864 07:44:06.820888 <30>[ 19.795169] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
865 07:44:06.847798 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
866 07:44:06.889095 <30>[ 19.862956] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
867 07:44:06.900870 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
868 07:44:06.924860 <28>[ 19.894487] systemd[1]: systemd-journald.service: unit configures an IP firewall, but the local system does not support BPF/cgroup firewalling.
869 07:44:06.945004 <28>[ 19.917976] systemd[1]: (This warning is only shown for the first unit using IP firewalling.)
870 07:44:06.991239 <30>[ 19.965576] systemd[1]: Starting systemd-journald.service - Journal Service...
871 07:44:07.009005 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
872 07:44:07.080442 <30>[ 20.054013] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
873 07:44:07.094097 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
874 07:44:07.120726 <30>[ 20.094548] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
875 07:44:07.176802 Starting [0;1;39msystemd-network-g… units from Kernel command line...
876 07:44:07.249961 <30>[ 20.223223] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
877 07:44:07.298244 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
878 07:44:07.364266 <30>[ 20.337599] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
879 07:44:07.418679 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
880 07:44:07.496459 <30>[ 20.470412] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
881 07:44:07.549155 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
882 07:44:07.571560 <30>[ 20.545313] systemd[1]: Mounted sys-kernel-tracing.mount - Kernel Trace File System.
883 07:44:07.606034 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-tracing…nt[0m - Kernel Trace File System.
884 07:44:07.635067 <30>[ 20.608728] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
885 07:44:07.667696 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
886 07:44:07.792519 <30>[ 20.767055] systemd[1]: modprobe@configfs.service: Deactivated successfully.
887 07:44:07.830102 <30>[ 20.803482] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
888 07:44:07.858190 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
889 07:44:07.880292 <30>[ 20.853456] systemd[1]: Started systemd-journald.service - Journal Service.
890 07:44:07.887181 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
891 07:44:07.908738 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
892 07:44:07.939278 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
893 07:44:07.970431 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
894 07:44:08.000528 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
895 07:44:08.033195 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
896 07:44:08.062937 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
897 07:44:08.081680 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
898 07:44:08.102687 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
899 07:44:08.133898 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
900 07:44:08.198015 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
901 07:44:08.241049 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
902 07:44:08.321198 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
903 07:44:08.368548 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
904 07:44:08.443393 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
905 07:44:08.593601 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
906 07:44:08.649846 <46>[ 21.623644] systemd-journald[165]: Received client request to flush runtime journal.
907 07:44:08.771220 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
908 07:44:08.859423 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
909 07:44:09.664419 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
910 07:44:09.731615 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
911 07:44:10.332641 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
912 07:44:10.502530 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
913 07:44:10.530572 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
914 07:44:10.549872 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
915 07:44:10.620097 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
916 07:44:10.683422 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
917 07:44:11.621163 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
918 07:44:11.690546 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
919 07:44:11.764149 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
920 07:44:11.850052 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
921 07:44:11.891033 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
922 07:44:12.743572 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
923 07:44:13.942284 <5>[ 26.916225] cfg80211: Loading compiled-in X.509 certificates for regulatory database
924 07:44:15.016291 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
925 07:44:15.277659 <5>[ 28.254424] Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
926 07:44:15.352518 <5>[ 28.327998] Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
927 07:44:15.379227 <4>[ 28.353031] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
928 07:44:15.384226 <6>[ 28.362151] cfg80211: failed to load regulatory.db
929 07:44:15.458950 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
930 07:44:15.737508 <46>[ 28.701910] systemd-journald[165]: Oldest entry in /var/log/journal/658c871cd7314ccea6115dc5728f8992/system.journal is older than the configured file retention duration (1month), suggesting rotation.
931 07:44:15.834305 <46>[ 28.801491] systemd-journald[165]: /var/log/journal/658c871cd7314ccea6115dc5728f8992/system.journal: Journal header limits reached or header out-of-date, rotating.
932 07:44:15.896147 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
933 07:44:16.366793 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
934 07:44:26.163057 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
935 07:44:26.189398 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
936 07:44:26.210724 [[0;32m OK [0m] Reached target [0;1;39musb-gadget.…m - Hardware activated USB gadget.
937 07:44:26.230917 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
938 07:44:26.303715 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
939 07:44:26.350305 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
940 07:44:26.429441 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
941 07:44:26.497988 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
942 07:44:26.535099 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
943 07:44:26.569029 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
944 07:44:26.593276 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
945 07:44:26.625527 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
946 07:44:26.665281 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
947 07:44:26.696450 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
948 07:44:26.732933 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
949 07:44:26.753058 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
950 07:44:26.783203 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
951 07:44:26.816487 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
952 07:44:26.840599 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
953 07:44:26.861043 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
954 07:44:26.895848 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
955 07:44:26.922396 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
956 07:44:26.951392 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
957 07:44:27.018305 Starting [0;1;39malsa-restore.serv…- Save/Restore Sound Card State...
958 07:44:27.057399 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
959 07:44:27.167060 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
960 07:44:27.241239 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
961 07:44:27.323132 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
962 07:44:27.362201 [[0;32m OK [0m] Finished [0;1;39malsa-restore.serv…m - Save/Restore Sound Card State.
963 07:44:27.379144 [[0;32m OK [0m] Reached target [0;1;39msound.target[0m - Sound Card.
964 07:44:27.570650 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
965 07:44:27.630127 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
966 07:44:27.695967 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
967 07:44:27.717654 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
968 07:44:27.758777 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
969 07:44:27.976312 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
970 07:44:28.345935 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
971 07:44:28.381180 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
972 07:44:28.414005 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
973 07:44:28.503502 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
974 07:44:28.675184 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
975 07:44:28.826083
976 07:44:28.828779 Debian GNU/Linux 12 deworm-armhf login: root (automatic login)
977 07:44:28.829287
978 07:44:29.125480 Linux debian-bookworm-armhf 6.12.0-rc7-next-20241112 #1 SMP Tue Nov 12 07:21:30 UTC 2024 armv7l
979 07:44:29.126200
980 07:44:29.131210 The programs included with the Debian GNU/Linux system are free software;
981 07:44:29.139919 the exact distribution terms for each program are described in the
982 07:44:29.140455 individual files in /usr/share/doc/*/copyright.
983 07:44:29.140911
984 07:44:29.150511 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
985 07:44:29.151052 permitted by applicable law.
986 07:44:34.177222 Unable to match end of the kernel message
988 07:44:34.178918 Setting prompt string to ['/ #']
989 07:44:34.179519 end: 2.4.4.1 login-action (duration 00:00:48) [common]
991 07:44:34.180997 end: 2.4.4 auto-login-action (duration 00:00:48) [common]
992 07:44:34.181575 start: 2.4.5 expect-shell-connection (timeout 00:03:11) [common]
993 07:44:34.182099 Setting prompt string to ['/ #']
994 07:44:34.182544 Forcing a shell prompt, looking for ['/ #']
996 07:44:34.233574 / #
997 07:44:34.234354 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
998 07:44:34.234905 Waiting using forced prompt support (timeout 00:02:30)
999 07:44:34.238180
1000 07:44:34.245383 end: 2.4.5 expect-shell-connection (duration 00:00:00) [common]
1001 07:44:34.246040 start: 2.4.6 export-device-env (timeout 00:03:11) [common]
1002 07:44:34.246571 Sending with 10 millisecond of delay
1004 07:44:39.237068 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/978505/extract-nfsrootfs-kr0x50hc'
1005 07:44:39.248120 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/978505/extract-nfsrootfs-kr0x50hc'
1006 07:44:39.249055 Sending with 10 millisecond of delay
1008 07:44:41.348089 / # export NFS_SERVER_IP='192.168.6.3'
1009 07:44:41.359128 export NFS_SERVER_IP='192.168.6.3'
1010 07:44:41.360350 end: 2.4.6 export-device-env (duration 00:00:07) [common]
1011 07:44:41.361006 end: 2.4 uboot-commands (duration 00:01:56) [common]
1012 07:44:41.361646 end: 2 uboot-action (duration 00:01:56) [common]
1013 07:44:41.362324 start: 3 lava-test-retry (timeout 00:06:54) [common]
1014 07:44:41.362967 start: 3.1 lava-test-shell (timeout 00:06:54) [common]
1015 07:44:41.363474 Using namespace: common
1017 07:44:41.464962 / # #
1018 07:44:41.465701 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
1019 07:44:41.469430 #
1020 07:44:41.476259 Using /lava-978505
1022 07:44:41.577562 / # export SHELL=/bin/bash
1023 07:44:41.583087 export SHELL=/bin/bash
1025 07:44:41.689752 / # . /lava-978505/environment
1026 07:44:41.695299 . /lava-978505/environment
1028 07:44:41.808062 / # /lava-978505/bin/lava-test-runner /lava-978505/0
1029 07:44:41.808778 Test shell timeout: 10s (minimum of the action and connection timeout)
1030 07:44:41.813404 /lava-978505/bin/lava-test-runner /lava-978505/0
1031 07:44:42.190560 + export TESTRUN_ID=0_timesync-off
1032 07:44:42.198434 + TESTRUN_ID=0_timesync-off
1033 07:44:42.198840 + cd /lava-978505/0/tests/0_timesync-off
1034 07:44:42.199106 ++ cat uuid
1035 07:44:42.213887 + UUID=978505_1.6.2.4.1
1036 07:44:42.214305 + set +x
1037 07:44:42.222418 <LAVA_SIGNAL_STARTRUN 0_timesync-off 978505_1.6.2.4.1>
1038 07:44:42.222797 + systemctl stop systemd-timesyncd
1039 07:44:42.223294 Received signal: <STARTRUN> 0_timesync-off 978505_1.6.2.4.1
1040 07:44:42.223579 Starting test lava.0_timesync-off (978505_1.6.2.4.1)
1041 07:44:42.223886 Skipping test definition patterns.
1042 07:44:42.529378 + set +x
1043 07:44:42.529848 <LAVA_SIGNAL_ENDRUN 0_timesync-off 978505_1.6.2.4.1>
1044 07:44:42.530344 Received signal: <ENDRUN> 0_timesync-off 978505_1.6.2.4.1
1045 07:44:42.530654 Ending use of test pattern.
1046 07:44:42.530887 Ending test lava.0_timesync-off (978505_1.6.2.4.1), duration 0.31
1048 07:44:42.699886 + export TESTRUN_ID=1_kselftest-dt
1049 07:44:42.707759 + TESTRUN_ID=1_kselftest-dt
1050 07:44:42.708055 + cd /lava-978505/0/tests/1_kselftest-dt
1051 07:44:42.708269 ++ cat uuid
1052 07:44:42.723793 + UUID=978505_1.6.2.4.5
1053 07:44:42.724127 + set +x
1054 07:44:42.729369 <LAVA_SIGNAL_STARTRUN 1_kselftest-dt 978505_1.6.2.4.5>
1055 07:44:42.729665 + cd ./automated/linux/kselftest/
1056 07:44:42.730138 Received signal: <STARTRUN> 1_kselftest-dt 978505_1.6.2.4.5
1057 07:44:42.730376 Starting test lava.1_kselftest-dt (978505_1.6.2.4.5)
1058 07:44:42.730633 Skipping test definition patterns.
1059 07:44:42.755595 + ./kselftest.sh -c dt -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/next/master/next-20241112/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz -L '' -S /dev/null -b beaglebone-black -g next -e '' -p /opt/kselftests/mainline/ -n 1 -i 1 -E ''
1060 07:44:42.856884 INFO: install_deps skipped
1061 07:44:43.489010 --2024-11-12 07:44:43-- http://storage.kernelci.org/next/master/next-20241112/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz
1062 07:44:43.755892 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
1063 07:44:43.895647 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
1064 07:44:44.034464 HTTP request sent, awaiting response... 200 OK
1065 07:44:44.034872 Length: 3602988 (3.4M) [application/octet-stream]
1066 07:44:44.039987 Saving to: 'kselftest_armhf.tar.gz'
1067 07:44:44.040396
1068 07:44:45.494562
kselftest_armhf.tar 0%[ ] 0 --.-KB/s
kselftest_armhf.tar 1%[ ] 49.92K 182KB/s
kselftest_armhf.tar 6%[> ] 216.29K 397KB/s
kselftest_armhf.tar 22%[===> ] 804.10K 897KB/s
kselftest_armhf.tar 48%[========> ] 1.67M 1.52MB/s
kselftest_armhf.tar 80%[===============> ] 2.76M 2.12MB/s
kselftest_armhf.tar 100%[===================>] 3.44M 2.36MB/s in 1.5s
1069 07:44:45.495003
1070 07:44:46.204720 2024-11-12 07:44:45 (2.36 MB/s) - 'kselftest_armhf.tar.gz' saved [3602988/3602988]
1071 07:44:46.205156
1072 07:45:00.127591 skiplist:
1073 07:45:00.128256 ========================================
1074 07:45:00.133269 ========================================
1075 07:45:00.233967 dt:test_unprobed_devices.sh
1076 07:45:00.283000 ============== Tests to run ===============
1077 07:45:00.291309 dt:test_unprobed_devices.sh
1078 07:45:00.295259 ===========End Tests to run ===============
1079 07:45:00.303232 shardfile-dt pass
1080 07:45:00.536894 <12>[ 73.515863] kselftest: Running tests in dt
1081 07:45:00.566064 TAP version 13
1082 07:45:00.589488 1..1
1083 07:45:00.642347 # timeout set to 45
1084 07:45:00.642947 # selftests: dt: test_unprobed_devices.sh
1085 07:45:01.464335 # TAP version 13
1086 07:45:26.264654 # 1..257
1087 07:45:26.434386 # ok 1 / # SKIP
1088 07:45:26.456602 # ok 2 /clk_mcasp0
1089 07:45:26.527615 # ok 3 /clk_mcasp0_fixed # SKIP
1090 07:45:26.600166 # ok 4 /cpus/cpu@0 # SKIP
1091 07:45:26.670512 # ok 5 /cpus/idle-states/mpu_gate # SKIP
1092 07:45:26.694254 # ok 6 /fixedregulator0
1093 07:45:26.710483 # ok 7 /leds
1094 07:45:26.735446 # ok 8 /ocp
1095 07:45:26.758649 # ok 9 /ocp/interconnect@44c00000
1096 07:45:26.781679 # ok 10 /ocp/interconnect@44c00000/segment@0
1097 07:45:26.802154 # ok 11 /ocp/interconnect@44c00000/segment@100000
1098 07:45:26.830620 # ok 12 /ocp/interconnect@44c00000/segment@100000/target-module@0
1099 07:45:26.901075 # not ok 13 /ocp/interconnect@44c00000/segment@100000/target-module@0/cpu@0
1100 07:45:26.921151 # ok 14 /ocp/interconnect@44c00000/segment@200000
1101 07:45:26.943817 # ok 15 /ocp/interconnect@44c00000/segment@200000/target-module@0
1102 07:45:27.046855 # not ok 16 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0
1103 07:45:27.118669 # ok 17 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0 # SKIP
1104 07:45:27.191715 # ok 18 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@0 # SKIP
1105 07:45:27.263185 # ok 19 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@120 # SKIP
1106 07:45:27.334721 # ok 20 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@14c # SKIP
1107 07:45:27.407387 # ok 21 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@18 # SKIP
1108 07:45:27.479382 # ok 22 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@1c # SKIP
1109 07:45:27.551685 # ok 23 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@24 # SKIP
1110 07:45:27.625842 # ok 24 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@38 # SKIP
1111 07:45:27.703048 # ok 25 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@e8 # SKIP
1112 07:45:27.775938 # ok 26 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400 # SKIP
1113 07:45:27.849921 # ok 27 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@0 # SKIP
1114 07:45:27.919963 # ok 28 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@14 # SKIP
1115 07:45:27.994729 # ok 29 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@b0 # SKIP
1116 07:45:28.065733 # ok 30 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600 # SKIP
1117 07:45:28.135702 # ok 31 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600/clock@0 # SKIP
1118 07:45:28.208195 # ok 32 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800 # SKIP
1119 07:45:28.286439 # ok 33 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800/clock@0 # SKIP
1120 07:45:28.354584 # ok 34 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900 # SKIP
1121 07:45:28.433551 # ok 35 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900/clock@0 # SKIP
1122 07:45:28.503075 # ok 36 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00 # SKIP
1123 07:45:28.575509 # ok 37 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00/clock@0 # SKIP
1124 07:45:28.651095 # ok 38 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-24mhz # SKIP
1125 07:45:28.733888 # ok 39 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-32768 # SKIP
1126 07:45:28.812763 # ok 40 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-rc32k # SKIP
1127 07:45:28.885566 # ok 41 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clkdiv32k # SKIP
1128 07:45:28.961616 # ok 42 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-125mhz-gclk # SKIP
1129 07:45:29.029933 # ok 43 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-cpts-rft@520 # SKIP
1130 07:45:29.103063 # ok 44 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4-div2 # SKIP
1131 07:45:29.174230 # ok 45 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4@480 # SKIP
1132 07:45:29.245598 # ok 46 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m5@484 # SKIP
1133 07:45:29.319272 # ok 47 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m6@4d8 # SKIP
1134 07:45:29.388869 # ok 48 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-x2 # SKIP
1135 07:45:29.462237 # ok 49 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2-div2 # SKIP
1136 07:45:29.536620 # ok 50 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2@4a0 # SKIP
1137 07:45:29.606248 # ok 51 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-disp-m2@4a4 # SKIP
1138 07:45:29.678946 # ok 52 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-mpu-m2@4a8 # SKIP
1139 07:45:29.748717 # ok 53 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4 # SKIP
1140 07:45:29.824468 # ok 54 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4-wkupdm # SKIP
1141 07:45:29.894734 # ok 55 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2@4ac # SKIP
1142 07:45:29.967532 # ok 56 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-gpio0-dbclk-mux@53c # SKIP
1143 07:45:30.036402 # ok 57 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-ieee5000-fck-1@e4 # SKIP
1144 07:45:30.106093 # ok 58 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3-gclk # SKIP
1145 07:45:30.177158 # ok 59 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3s-gclk # SKIP
1146 07:45:30.253331 # ok 60 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4-rtc-gclk # SKIP
1147 07:45:30.325066 # ok 61 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4fw-gclk # SKIP
1148 07:45:30.396771 # ok 62 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4hs-gclk # SKIP
1149 07:45:30.472021 # ok 63 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4ls-gclk # SKIP
1150 07:45:30.548245 # ok 64 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-lcd-gclk@534 # SKIP
1151 07:45:30.617036 # ok 65 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmc # SKIP
1152 07:45:30.690699 # ok 66 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmu-fck-1@914 # SKIP
1153 07:45:30.762022 # ok 67 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-pruss-ocp-gclk@530 # SKIP
1154 07:45:30.833901 # ok 68 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-sysclk-div # SKIP
1155 07:45:30.905448 # ok 69 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-tclkin # SKIP
1156 07:45:30.981400 # ok 70 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer1-fck@528 # SKIP
1157 07:45:31.050602 # ok 71 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer2-fck@508 # SKIP
1158 07:45:31.123892 # ok 72 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer3-fck@50c # SKIP
1159 07:45:31.196701 # ok 73 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer4-fck@510 # SKIP
1160 07:45:31.268833 # ok 74 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer5-fck@518 # SKIP
1161 07:45:31.339358 # ok 75 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer6-fck@51c # SKIP
1162 07:45:31.411730 # ok 76 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer7-fck@504 # SKIP
1163 07:45:31.483123 # ok 77 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-usbotg-fck-8@47c # SKIP
1164 07:45:31.555146 # ok 78 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-19200000 # SKIP
1165 07:45:31.627090 # ok 79 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-24000000 # SKIP
1166 07:45:31.703391 # ok 80 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-25000000 # SKIP
1167 07:45:31.775877 # ok 81 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-26000000 # SKIP
1168 07:45:31.846080 # ok 82 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-wdt1-fck@538 # SKIP
1169 07:45:31.914183 # ok 83 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@488 # SKIP
1170 07:45:31.986060 # ok 84 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@48c # SKIP
1171 07:45:32.057340 # ok 85 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@490 # SKIP
1172 07:45:32.128235 # ok 86 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@494 # SKIP
1173 07:45:32.200452 # ok 87 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@498 # SKIP
1174 07:45:32.276408 # ok 88 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c # SKIP
1175 07:45:32.346260 # ok 89 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fck-div@0 # SKIP
1176 07:45:32.420862 # ok 90 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fclk-clksel@1 # SKIP
1177 07:45:32.492238 # ok 91 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700 # SKIP
1178 07:45:32.565328 # ok 92 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2-div@3 # SKIP
1179 07:45:32.637534 # ok 93 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2@7 # SKIP
1180 07:45:32.705208 # ok 94 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-sysclkout-pre@0 # SKIP
1181 07:45:32.730543 # ok 95 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1000
1182 07:45:32.754737 # ok 96 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1100
1183 07:45:32.779921 # ok 97 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1200
1184 07:45:32.798599 # ok 98 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@c00
1185 07:45:32.824673 # ok 99 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@d00
1186 07:45:32.847250 # ok 100 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@e00
1187 07:45:32.869608 # ok 101 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@f00
1188 07:45:32.892869 # ok 102 /ocp/interconnect@44c00000/segment@200000/target-module@10000
1189 07:45:32.998526 # not ok 103 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0
1190 07:45:33.022977 # ok 104 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/control@620
1191 07:45:33.051970 # ok 105 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/dma-router@f90
1192 07:45:33.075306 # ok 106 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800
1193 07:45:33.176761 # not ok 107 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0
1194 07:45:33.255112 # ok 108 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-adc-tsc-fck # SKIP
1195 07:45:33.323955 # ok 109 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-aes0-fck # SKIP
1196 07:45:33.396023 # ok 110 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan0-fck # SKIP
1197 07:45:33.469466 # ok 111 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan1-fck # SKIP
1198 07:45:33.544775 # ok 112 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp0-fck # SKIP
1199 07:45:33.618084 # ok 113 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp1-fck # SKIP
1200 07:45:33.687751 # ok 114 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-rng-fck # SKIP
1201 07:45:33.757369 # ok 115 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sha0-fck # SKIP
1202 07:45:33.830237 # ok 116 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex0-fck # SKIP
1203 07:45:33.906501 # ok 117 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex1-fck # SKIP
1204 07:45:33.974555 # ok 118 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sys-clkin-22@40 # SKIP
1205 07:45:34.045228 # ok 119 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664 # SKIP
1206 07:45:34.124817 # ok 120 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm0-tbclk@0 # SKIP
1207 07:45:34.193027 # ok 121 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm1-tbclk@1 # SKIP
1208 07:45:34.265541 # ok 122 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm2-tbclk@2 # SKIP
1209 07:45:34.294051 # ok 123 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/phy-gmii-sel
1210 07:45:34.363315 # not ok 124 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/wkup_m3_ipc@1324
1211 07:45:34.433536 # not ok 125 /ocp/interconnect@44c00000/segment@200000/target-module@31000
1212 07:45:34.505144 # ok 126 /ocp/interconnect@44c00000/segment@200000/target-module@31000/timer@0 # SKIP
1213 07:45:34.530981 # ok 127 /ocp/interconnect@44c00000/segment@200000/target-module@35000
1214 07:45:34.602321 # not ok 128 /ocp/interconnect@44c00000/segment@200000/target-module@35000/wdt@0
1215 07:45:34.623849 # ok 129 /ocp/interconnect@44c00000/segment@200000/target-module@3e000
1216 07:45:34.691751 # not ok 130 /ocp/interconnect@44c00000/segment@200000/target-module@3e000/rtc@0
1217 07:45:34.718899 # ok 131 /ocp/interconnect@44c00000/segment@200000/target-module@7000
1218 07:45:34.738711 # ok 132 /ocp/interconnect@44c00000/segment@200000/target-module@7000/gpio@0
1219 07:45:34.761229 # ok 133 /ocp/interconnect@44c00000/segment@200000/target-module@9000
1220 07:45:34.790547 # ok 134 /ocp/interconnect@44c00000/segment@200000/target-module@9000/serial@0
1221 07:45:34.813063 # ok 135 /ocp/interconnect@44c00000/segment@200000/target-module@b000
1222 07:45:34.833347 # ok 136 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0
1223 07:45:34.862616 # ok 137 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/eeprom@50
1224 07:45:34.936575 # ok 138 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/eeprom@50/nvmem-layout # SKIP
1225 07:45:34.954066 # ok 139 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
1226 07:45:34.982021 # ok 140 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24
1227 07:45:35.053177 # not ok 141 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/charger
1228 07:45:35.123658 # not ok 142 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/pwrbutton
1229 07:45:35.143505 # ok 143 /ocp/interconnect@44c00000/segment@200000/target-module@d000
1230 07:45:35.239538 # not ok 144 /ocp/interconnect@47c00000
1231 07:45:35.311383 # not ok 145 /ocp/interconnect@47c00000/segment@0
1232 07:45:35.332559 # ok 146 /ocp/interconnect@48000000
1233 07:45:35.359667 # ok 147 /ocp/interconnect@48000000/segment@0
1234 07:45:35.383486 # ok 148 /ocp/interconnect@48000000/segment@0/target-module@22000
1235 07:45:35.408205 # ok 149 /ocp/interconnect@48000000/segment@0/target-module@24000
1236 07:45:35.431012 # ok 150 /ocp/interconnect@48000000/segment@0/target-module@2a000
1237 07:45:35.453262 # ok 151 /ocp/interconnect@48000000/segment@0/target-module@30000
1238 07:45:35.474158 # ok 152 /ocp/interconnect@48000000/segment@0/target-module@38000
1239 07:45:35.502513 # ok 153 /ocp/interconnect@48000000/segment@0/target-module@38000/mcasp@0
1240 07:45:35.523466 # ok 154 /ocp/interconnect@48000000/segment@0/target-module@3c000
1241 07:45:35.592021 # not ok 155 /ocp/interconnect@48000000/segment@0/target-module@40000
1242 07:45:35.664232 # ok 156 /ocp/interconnect@48000000/segment@0/target-module@40000/timer@0 # SKIP
1243 07:45:35.690561 # ok 157 /ocp/interconnect@48000000/segment@0/target-module@42000
1244 07:45:35.713944 # ok 158 /ocp/interconnect@48000000/segment@0/target-module@42000/timer@0
1245 07:45:35.734083 # ok 159 /ocp/interconnect@48000000/segment@0/target-module@44000
1246 07:45:35.757950 # ok 160 /ocp/interconnect@48000000/segment@0/target-module@44000/timer@0
1247 07:45:35.780248 # ok 161 /ocp/interconnect@48000000/segment@0/target-module@46000
1248 07:45:35.809361 # ok 162 /ocp/interconnect@48000000/segment@0/target-module@46000/timer@0
1249 07:45:35.827309 # ok 163 /ocp/interconnect@48000000/segment@0/target-module@48000
1250 07:45:35.851338 # ok 164 /ocp/interconnect@48000000/segment@0/target-module@48000/timer@0
1251 07:45:35.878177 # ok 165 /ocp/interconnect@48000000/segment@0/target-module@4a000
1252 07:45:35.901768 # ok 166 /ocp/interconnect@48000000/segment@0/target-module@4a000/timer@0
1253 07:45:35.923465 # ok 167 /ocp/interconnect@48000000/segment@0/target-module@4c000
1254 07:45:35.945913 # ok 168 /ocp/interconnect@48000000/segment@0/target-module@4c000/gpio@0
1255 07:45:35.973336 # ok 169 /ocp/interconnect@48000000/segment@0/target-module@60000
1256 07:45:36.001161 # ok 170 /ocp/interconnect@48000000/segment@0/target-module@60000/mmc@0
1257 07:45:36.016713 # ok 171 /ocp/interconnect@48000000/segment@0/target-module@c8000
1258 07:45:36.042305 # ok 172 /ocp/interconnect@48000000/segment@0/target-module@c8000/mailbox@0
1259 07:45:36.068836 # ok 173 /ocp/interconnect@48000000/segment@0/target-module@ca000
1260 07:45:36.093490 # ok 174 /ocp/interconnect@48000000/segment@0/target-module@ca000/spinlock@0
1261 07:45:36.112075 # ok 175 /ocp/interconnect@48000000/segment@100000
1262 07:45:36.139851 # ok 176 /ocp/interconnect@48000000/segment@100000/target-module@9c000
1263 07:45:36.164220 # ok 177 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0
1264 07:45:36.232995 # not ok 178 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/eeprom@54
1265 07:45:36.306259 # ok 179 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/eeprom@54/nvmem-layout # SKIP
1266 07:45:36.380910 # not ok 180 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/eeprom@55
1267 07:45:36.452640 # ok 181 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/eeprom@55/nvmem-layout # SKIP
1268 07:45:36.522531 # not ok 182 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/eeprom@56
1269 07:45:36.595989 # ok 183 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/eeprom@56/nvmem-layout # SKIP
1270 07:45:36.666415 # not ok 184 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/eeprom@57
1271 07:45:36.740153 # ok 185 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/eeprom@57/nvmem-layout # SKIP
1272 07:45:36.760212 # ok 186 /ocp/interconnect@48000000/segment@100000/target-module@a0000
1273 07:45:36.787553 # ok 187 /ocp/interconnect@48000000/segment@100000/target-module@a6000
1274 07:45:36.806437 # ok 188 /ocp/interconnect@48000000/segment@100000/target-module@a8000
1275 07:45:36.830444 # ok 189 /ocp/interconnect@48000000/segment@100000/target-module@aa000
1276 07:45:36.860859 # ok 190 /ocp/interconnect@48000000/segment@100000/target-module@ac000
1277 07:45:36.878183 # ok 191 /ocp/interconnect@48000000/segment@100000/target-module@ac000/gpio@0
1278 07:45:36.901272 # ok 192 /ocp/interconnect@48000000/segment@100000/target-module@ae000
1279 07:45:36.930746 # ok 193 /ocp/interconnect@48000000/segment@100000/target-module@ae000/gpio@0
1280 07:45:36.953399 # ok 194 /ocp/interconnect@48000000/segment@100000/target-module@cc000
1281 07:45:36.973699 # ok 195 /ocp/interconnect@48000000/segment@100000/target-module@d0000
1282 07:45:36.994652 # ok 196 /ocp/interconnect@48000000/segment@100000/target-module@d8000
1283 07:45:37.020019 # ok 197 /ocp/interconnect@48000000/segment@100000/target-module@d8000/mmc@0
1284 07:45:37.042170 # ok 198 /ocp/interconnect@48000000/segment@200000
1285 07:45:37.064990 # ok 199 /ocp/interconnect@48000000/segment@200000/target-module@0
1286 07:45:37.138629 # ok 200 /ocp/interconnect@48000000/segment@200000/target-module@0/mpu@0 # SKIP
1287 07:45:37.158547 # ok 201 /ocp/interconnect@48000000/segment@300000
1288 07:45:37.183081 # ok 202 /ocp/interconnect@48000000/segment@300000/target-module@0
1289 07:45:37.211261 # ok 203 /ocp/interconnect@48000000/segment@300000/target-module@10000
1290 07:45:37.234240 # ok 204 /ocp/interconnect@48000000/segment@300000/target-module@10000/rng@0
1291 07:45:37.262114 # ok 205 /ocp/interconnect@48000000/segment@300000/target-module@2000
1292 07:45:37.283033 # ok 206 /ocp/interconnect@48000000/segment@300000/target-module@4000
1293 07:45:37.308499 # ok 207 /ocp/interconnect@48000000/segment@300000/target-module@e000
1294 07:45:37.380092 # not ok 208 /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
1295 07:45:37.399300 # ok 209 /ocp/interconnect@4a000000
1296 07:45:37.418636 # ok 210 /ocp/interconnect@4a000000/segment@0
1297 07:45:37.448318 # ok 211 /ocp/interconnect@4a000000/segment@0/target-module@100000
1298 07:45:37.472720 # ok 212 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0
1299 07:45:37.495214 # ok 213 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0/mdio@1000
1300 07:45:37.515373 # ok 214 /ocp/interconnect@4a000000/segment@0/target-module@300000
1301 07:45:37.590731 # not ok 215 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0
1302 07:45:37.695611 # ok 216 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/cfg@26000 # SKIP
1303 07:45:37.764608 # not ok 217 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/interrupt-controller@20000
1304 07:45:37.869195 # ok 218 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/mii-rt@32000 # SKIP
1305 07:45:37.939650 # not ok 219 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@34000
1306 07:45:38.010504 # not ok 220 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@38000
1307 07:45:38.109425 # not ok 221 /ocp/interconnect@4b140000
1308 07:45:38.180941 # not ok 222 /ocp/interconnect@4b140000/segment@0
1309 07:45:38.253430 # ok 223 /ocp/interrupt-controller@48200000 # SKIP
1310 07:45:38.277546 # ok 224 /ocp/target-module@40300000
1311 07:45:38.300478 # ok 225 /ocp/target-module@40300000/sram@0
1312 07:45:38.368781 # ok 226 /ocp/target-module@40300000/sram@0/pm-code-sram@0 # SKIP
1313 07:45:38.443585 # ok 227 /ocp/target-module@40300000/sram@0/pm-data-sram@1000 # SKIP
1314 07:45:38.462177 # ok 228 /ocp/target-module@47400000
1315 07:45:38.481857 # ok 229 /ocp/target-module@47400000/dma-controller@2000
1316 07:45:38.504966 # ok 230 /ocp/target-module@47400000/usb-phy@1300
1317 07:45:38.527290 # ok 231 /ocp/target-module@47400000/usb-phy@1b00
1318 07:45:38.548986 # ok 232 /ocp/target-module@47400000/usb@1400
1319 07:45:38.576006 # ok 233 /ocp/target-module@47400000/usb@1800
1320 07:45:38.592676 # ok 234 /ocp/target-module@47810000
1321 07:45:38.619845 # ok 235 /ocp/target-module@49000000
1322 07:45:38.641261 # ok 236 /ocp/target-module@49000000/dma@0
1323 07:45:38.666119 # ok 237 /ocp/target-module@49800000
1324 07:45:38.683188 # ok 238 /ocp/target-module@49800000/dma@0
1325 07:45:38.709403 # ok 239 /ocp/target-module@49900000
1326 07:45:38.731212 # ok 240 /ocp/target-module@49900000/dma@0
1327 07:45:38.754125 # ok 241 /ocp/target-module@49a00000
1328 07:45:38.777638 # ok 242 /ocp/target-module@49a00000/dma@0
1329 07:45:38.799623 # ok 243 /ocp/target-module@4c000000
1330 07:45:38.866750 # not ok 244 /ocp/target-module@4c000000/emif@0
1331 07:45:38.890684 # ok 245 /ocp/target-module@50000000
1332 07:45:38.914419 # ok 246 /ocp/target-module@53100000
1333 07:45:38.986303 # not ok 247 /ocp/target-module@53100000/sham@0
1334 07:45:39.003214 # ok 248 /ocp/target-module@53500000
1335 07:45:39.077669 # not ok 249 /ocp/target-module@53500000/aes@0
1336 07:45:39.094193 # ok 250 /ocp/target-module@56000000
1337 07:45:39.201786 # ok 251 /ocp/target-module@56000000/gpu@0 # SKIP
1338 07:45:39.267070 # ok 252 /opp-table # SKIP
1339 07:45:39.336887 # ok 253 /soc # SKIP
1340 07:45:39.358967 # ok 254 /sound
1341 07:45:39.381183 # ok 255 /target-module@4b000000
1342 07:45:39.411131 # ok 256 /target-module@4b000000/target-module@140000
1343 07:45:39.428333 # ok 257 /target-module@4b000000/target-module@140000/pmu@0
1344 07:45:39.436754 # # Totals: pass:117 fail:27 xfail:0 xpass:0 skip:113 error:0
1345 07:45:39.445435 not ok 1 selftests: dt: test_unprobed_devices.sh # exit=1
1346 07:45:41.531958 dt_test_unprobed_devices_sh_ skip
1347 07:45:41.537421 dt_test_unprobed_devices_sh_clk_mcasp0 pass
1348 07:45:41.543126 dt_test_unprobed_devices_sh_clk_mcasp0_fixed skip
1349 07:45:41.543459 dt_test_unprobed_devices_sh_cpus_cpu_0 skip
1350 07:45:41.548785 dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate skip
1351 07:45:41.554364 dt_test_unprobed_devices_sh_fixedregulator0 pass
1352 07:45:41.559989 dt_test_unprobed_devices_sh_leds pass
1353 07:45:41.560334 dt_test_unprobed_devices_sh_ocp pass
1354 07:45:41.565541 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 pass
1355 07:45:41.571171 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 pass
1356 07:45:41.576864 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 pass
1357 07:45:41.588042 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 pass
1358 07:45:41.593410 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 fail
1359 07:45:41.599030 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 pass
1360 07:45:41.610218 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 pass
1361 07:45:41.615985 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 fail
1362 07:45:41.627061 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 skip
1363 07:45:41.638721 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 skip
1364 07:45:41.649521 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 skip
1365 07:45:41.655134 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c skip
1366 07:45:41.666341 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 skip
1367 07:45:41.677543 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c skip
1368 07:45:41.688886 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 skip
1369 07:45:41.699998 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 skip
1370 07:45:41.705607 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 skip
1371 07:45:41.716799 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 skip
1372 07:45:41.728036 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 skip
1373 07:45:41.739275 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 skip
1374 07:45:41.750399 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 skip
1375 07:45:41.755967 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 skip
1376 07:45:41.767217 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 skip
1377 07:45:41.778413 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 skip
1378 07:45:41.789670 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 skip
1379 07:45:41.795234 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 skip
1380 07:45:41.806432 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 skip
1381 07:45:41.817643 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 skip
1382 07:45:41.828748 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 skip
1383 07:45:41.840000 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz skip
1384 07:45:41.845560 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 skip
1385 07:45:41.856727 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k skip
1386 07:45:41.867904 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k skip
1387 07:45:41.879130 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk skip
1388 07:45:41.890292 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 skip
1389 07:45:41.901534 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 skip
1390 07:45:41.912790 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 skip
1391 07:45:41.923874 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 skip
1392 07:45:41.935031 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 skip
1393 07:45:41.946280 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 skip
1394 07:45:41.957442 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 skip
1395 07:45:41.968648 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 skip
1396 07:45:41.979852 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 skip
1397 07:45:41.990980 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 skip
1398 07:45:42.002230 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 skip
1399 07:45:42.013443 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm skip
1400 07:45:42.024655 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac skip
1401 07:45:42.035955 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c skip
1402 07:45:42.046950 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 skip
1403 07:45:42.058118 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk skip
1404 07:45:42.069332 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk skip
1405 07:45:42.080515 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk skip
1406 07:45:42.091740 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk skip
1407 07:45:42.102905 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk skip
1408 07:45:42.114119 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk skip
1409 07:45:42.125608 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 skip
1410 07:45:42.130847 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc skip
1411 07:45:42.142102 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 skip
1412 07:45:42.153555 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 skip
1413 07:45:42.164479 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div skip
1414 07:45:42.175662 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin skip
1415 07:45:42.186852 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 skip
1416 07:45:42.198091 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 skip
1417 07:45:42.209254 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c skip
1418 07:45:42.220399 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 skip
1419 07:45:42.231633 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 skip
1420 07:45:42.242828 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c skip
1421 07:45:42.254049 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 skip
1422 07:45:42.265194 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c skip
1423 07:45:42.276350 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 skip
1424 07:45:42.287570 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 skip
1425 07:45:42.298789 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 skip
1426 07:45:42.309995 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 skip
1427 07:45:42.321115 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 skip
1428 07:45:42.326769 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 skip
1429 07:45:42.337898 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c skip
1430 07:45:42.349086 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 skip
1431 07:45:42.360344 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 skip
1432 07:45:42.371482 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 skip
1433 07:45:42.377111 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c skip
1434 07:45:42.393884 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 skip
1435 07:45:42.405073 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 skip
1436 07:45:42.410681 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 skip
1437 07:45:42.427511 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 skip
1438 07:45:42.438782 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 skip
1439 07:45:42.449982 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 skip
1440 07:45:42.455647 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 pass
1441 07:45:42.466836 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 pass
1442 07:45:42.478095 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 pass
1443 07:45:42.483657 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 pass
1444 07:45:42.494868 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 pass
1445 07:45:42.506057 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 pass
1446 07:45:42.511695 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 pass
1447 07:45:42.522957 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 pass
1448 07:45:42.528726 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 fail
1449 07:45:42.539718 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 pass
1450 07:45:42.550950 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 pass
1451 07:45:42.562136 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 pass
1452 07:45:42.573378 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 fail
1453 07:45:42.584617 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck skip
1454 07:45:42.595954 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck skip
1455 07:45:42.607065 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck skip
1456 07:45:42.618315 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck skip
1457 07:45:42.629526 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck skip
1458 07:45:42.640719 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck skip
1459 07:45:42.651923 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck skip
1460 07:45:42.663158 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck skip
1461 07:45:42.679931 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck skip
1462 07:45:42.691147 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck skip
1463 07:45:42.702344 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 skip
1464 07:45:42.713525 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 skip
1465 07:45:42.724757 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 skip
1466 07:45:42.741525 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 skip
1467 07:45:42.752747 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 skip
1468 07:45:42.763891 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel pass
1469 07:45:42.775135 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 fail
1470 07:45:42.780761 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 fail
1471 07:45:42.791909 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 skip
1472 07:45:42.803114 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 pass
1473 07:45:42.808740 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 fail
1474 07:45:42.819929 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 pass
1475 07:45:42.825539 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 fail
1476 07:45:42.836740 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 pass
1477 07:45:42.842345 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 pass
1478 07:45:42.853569 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 pass
1479 07:45:42.859192 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 pass
1480 07:45:42.870375 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 pass
1481 07:45:42.875911 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 pass
1482 07:45:42.887177 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_eeprom_50 pass
1483 07:45:42.898271 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_eeprom_50_nvmem-layout skip
1484 07:45:42.909526 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 pass
1485 07:45:42.915104 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 pass
1486 07:45:42.926291 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger fail
1487 07:45:42.937476 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton fail
1488 07:45:42.943054 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 pass
1489 07:45:42.948656 dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 fail
1490 07:45:42.959947 dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 fail
1491 07:45:42.960352 dt_test_unprobed_devices_sh_ocp_interconnect_48000000 pass
1492 07:45:42.971446 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 pass
1493 07:45:42.976760 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 pass
1494 07:45:42.982792 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 pass
1495 07:45:42.993724 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 pass
1496 07:45:42.999255 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 pass
1497 07:45:43.010370 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 pass
1498 07:45:43.016078 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 pass
1499 07:45:43.027022 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 pass
1500 07:45:43.032636 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 fail
1501 07:45:43.038580 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 skip
1502 07:45:43.049393 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 pass
1503 07:45:43.054983 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 pass
1504 07:45:43.066174 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 pass
1505 07:45:43.071796 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 pass
1506 07:45:43.082983 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 pass
1507 07:45:43.088534 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 pass
1508 07:45:43.100222 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 pass
1509 07:45:43.105342 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 pass
1510 07:45:43.116532 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 pass
1511 07:45:43.122144 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 pass
1512 07:45:43.133504 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 pass
1513 07:45:43.138992 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 pass
1514 07:45:43.144525 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 pass
1515 07:45:43.155734 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 pass
1516 07:45:43.161331 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 pass
1517 07:45:43.172603 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 pass
1518 07:45:43.178135 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 pass
1519 07:45:43.189290 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 pass
1520 07:45:43.194994 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 pass
1521 07:45:43.206093 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 pass
1522 07:45:43.211660 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 pass
1523 07:45:43.222879 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_54 fail
1524 07:45:43.234057 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_54_nvmem-layout skip
1525 07:45:43.245245 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_55 fail
1526 07:45:43.256430 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_55_nvmem-layout skip
1527 07:45:43.262048 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_56 fail
1528 07:45:43.273238 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_56_nvmem-layout skip
1529 07:45:43.284498 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_57 fail
1530 07:45:43.295687 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_57_nvmem-layout skip
1531 07:45:43.301278 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 pass
1532 07:45:43.312540 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 pass
1533 07:45:43.318171 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 pass
1534 07:45:43.329200 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 pass
1535 07:45:43.334878 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 pass
1536 07:45:43.345999 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 pass
1537 07:45:43.351610 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 pass
1538 07:45:43.362950 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 pass
1539 07:45:43.368405 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 pass
1540 07:45:43.379561 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 pass
1541 07:45:43.385225 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 pass
1542 07:45:43.396331 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 pass
1543 07:45:43.402067 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 pass
1544 07:45:43.413109 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 pass
1545 07:45:43.418767 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 skip
1546 07:45:43.424366 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 pass
1547 07:45:43.435506 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 pass
1548 07:45:43.441169 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 pass
1549 07:45:43.452353 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 pass
1550 07:45:43.458031 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 pass
1551 07:45:43.469111 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 pass
1552 07:45:43.474785 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 pass
1553 07:45:43.486190 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 fail
1554 07:45:43.491504 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 pass
1555 07:45:43.497117 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 pass
1556 07:45:43.502683 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 pass
1557 07:45:43.513882 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 pass
1558 07:45:43.519503 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 pass
1559 07:45:43.530819 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 pass
1560 07:45:43.536271 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 fail
1561 07:45:43.547455 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 skip
1562 07:45:43.558679 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 fail
1563 07:45:43.569898 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 skip
1564 07:45:43.581120 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 fail
1565 07:45:43.586719 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 fail
1566 07:45:43.592363 dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 fail
1567 07:45:43.598016 dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 fail
1568 07:45:43.603590 dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 skip
1569 07:45:43.609231 dt_test_unprobed_devices_sh_ocp_target-module_40300000 pass
1570 07:45:43.615017 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 pass
1571 07:45:43.626148 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 skip
1572 07:45:43.631773 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 skip
1573 07:45:43.637363 dt_test_unprobed_devices_sh_ocp_target-module_47400000 pass
1574 07:45:43.643028 dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 pass
1575 07:45:43.648594 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 pass
1576 07:45:43.659693 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 pass
1577 07:45:43.665359 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 pass
1578 07:45:43.671047 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 pass
1579 07:45:43.676551 dt_test_unprobed_devices_sh_ocp_target-module_47810000 pass
1580 07:45:43.682139 dt_test_unprobed_devices_sh_ocp_target-module_49000000 pass
1581 07:45:43.687731 dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 pass
1582 07:45:43.693514 dt_test_unprobed_devices_sh_ocp_target-module_49800000 pass
1583 07:45:43.699072 dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 pass
1584 07:45:43.704530 dt_test_unprobed_devices_sh_ocp_target-module_49900000 pass
1585 07:45:43.710190 dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 pass
1586 07:45:43.715815 dt_test_unprobed_devices_sh_ocp_target-module_49a00000 pass
1587 07:45:43.721347 dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 pass
1588 07:45:43.727042 dt_test_unprobed_devices_sh_ocp_target-module_4c000000 pass
1589 07:45:43.732536 dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 fail
1590 07:45:43.738182 dt_test_unprobed_devices_sh_ocp_target-module_50000000 pass
1591 07:45:43.743824 dt_test_unprobed_devices_sh_ocp_target-module_53100000 pass
1592 07:45:43.749345 dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 fail
1593 07:45:43.755048 dt_test_unprobed_devices_sh_ocp_target-module_53500000 pass
1594 07:45:43.760569 dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 fail
1595 07:45:43.766202 dt_test_unprobed_devices_sh_ocp_target-module_56000000 pass
1596 07:45:43.771787 dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 skip
1597 07:45:43.772381 dt_test_unprobed_devices_sh_opp-table skip
1598 07:45:43.777385 dt_test_unprobed_devices_sh_soc skip
1599 07:45:43.783039 dt_test_unprobed_devices_sh_sound pass
1600 07:45:43.783659 dt_test_unprobed_devices_sh_target-module_4b000000 pass
1601 07:45:43.794170 dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 pass
1602 07:45:43.799825 dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 pass
1603 07:45:43.805317 dt_test_unprobed_devices_sh fail
1604 07:45:43.805660 + ../../utils/send-to-lava.sh ./output/result.txt
1605 07:45:43.813862 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-dt RESULT=pass>
1606 07:45:43.814502 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-dt RESULT=pass
1608 07:45:43.819629 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip
1610 07:45:43.822608 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip>
1611 07:45:43.913754 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass>
1612 07:45:43.914396 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass
1614 07:45:44.006117 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip>
1615 07:45:44.006759 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip
1617 07:45:44.098435 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip>
1618 07:45:44.099389 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip
1620 07:45:44.200825 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip>
1621 07:45:44.201757 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip
1623 07:45:44.292455 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass>
1624 07:45:44.293399 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass
1626 07:45:44.383886 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass>
1627 07:45:44.384817 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass
1629 07:45:44.476135 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass>
1630 07:45:44.476779 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass
1632 07:45:44.568475 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass>
1633 07:45:44.569404 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass
1635 07:45:44.659259 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass>
1636 07:45:44.660120 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass
1638 07:45:44.748960 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass>
1639 07:45:44.749854 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass
1641 07:45:44.842529 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass>
1642 07:45:44.843410 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass
1644 07:45:44.934386 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail>
1645 07:45:44.935228 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail
1647 07:45:45.024501 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass>
1648 07:45:45.025180 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass
1650 07:45:45.117019 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass>
1651 07:45:45.117653 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass
1653 07:45:45.207984 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail>
1654 07:45:45.208629 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail
1656 07:45:45.299204 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip>
1657 07:45:45.299837 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip
1659 07:45:45.392214 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip>
1660 07:45:45.392841 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip
1662 07:45:45.483778 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip>
1663 07:45:45.484399 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip
1665 07:45:45.574519 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip>
1666 07:45:45.575153 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip
1668 07:45:45.664695 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip>
1669 07:45:45.665337 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip
1671 07:45:45.749303 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip>
1672 07:45:45.749973 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip
1674 07:45:45.864738 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip>
1675 07:45:45.865432 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip
1677 07:45:45.958026 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip>
1678 07:45:45.958676 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip
1680 07:45:46.051823 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip>
1681 07:45:46.052477 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip
1683 07:45:46.144620 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip>
1684 07:45:46.145225 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip
1686 07:45:46.234664 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip>
1687 07:45:46.235313 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip
1689 07:45:46.324661 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip>
1690 07:45:46.325667 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip
1692 07:45:46.410174 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip>
1693 07:45:46.411174 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip
1695 07:45:46.501729 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip>
1696 07:45:46.502412 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip
1698 07:45:46.593997 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip>
1699 07:45:46.595069 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip
1701 07:45:46.685052 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip>
1702 07:45:46.685695 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip
1704 07:45:46.778978 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip>
1705 07:45:46.779613 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip
1707 07:45:46.869625 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip>
1708 07:45:46.870293 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip
1710 07:45:46.962293 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip>
1711 07:45:46.962943 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip
1713 07:45:47.050883 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip>
1714 07:45:47.051529 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip
1716 07:45:47.142307 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip>
1717 07:45:47.142954 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip
1719 07:45:47.235597 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip>
1720 07:45:47.236244 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip
1722 07:45:47.326041 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip>
1723 07:45:47.326683 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip
1725 07:45:47.417635 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip>
1726 07:45:47.418822 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip
1728 07:45:47.510219 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip>
1729 07:45:47.511358 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip
1731 07:45:47.602354 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip>
1732 07:45:47.603242 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip
1734 07:45:47.692850 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip>
1735 07:45:47.693762 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip
1737 07:45:47.788431 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip>
1738 07:45:47.789165 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip
1740 07:45:47.880851 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip>
1741 07:45:47.881543 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip
1743 07:45:47.972813 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip>
1744 07:45:47.973511 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip
1746 07:45:48.064126 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip>
1747 07:45:48.064820 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip
1749 07:45:48.155372 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip>
1750 07:45:48.156063 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip
1752 07:45:48.248791 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip>
1753 07:45:48.249486 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip
1755 07:45:48.340650 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip>
1756 07:45:48.341290 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip
1758 07:45:48.434948 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip>
1759 07:45:48.435606 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip
1761 07:45:48.524410 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip>
1762 07:45:48.525039 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip
1764 07:45:48.615816 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip>
1765 07:45:48.616493 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip
1767 07:45:48.706631 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip>
1768 07:45:48.707312 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip
1770 07:45:48.792082 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip>
1771 07:45:48.792870 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip
1773 07:45:48.889342 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip>
1774 07:45:48.890085 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip
1776 07:45:48.978059 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip>
1777 07:45:48.978742 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip
1779 07:45:49.070134 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip>
1780 07:45:49.070827 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip
1782 07:45:49.162136 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip>
1783 07:45:49.162797 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip
1785 07:45:49.252554 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip>
1786 07:45:49.253215 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip
1788 07:45:49.342840 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip>
1789 07:45:49.343492 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip
1791 07:45:49.435556 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip>
1792 07:45:49.436261 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip
1794 07:45:49.547474 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip>
1795 07:45:49.548096 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip
1797 07:45:49.638328 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip>
1798 07:45:49.639203 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip
1800 07:45:49.739862 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip>
1801 07:45:49.740800 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip
1803 07:45:49.833293 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip>
1804 07:45:49.834286 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip
1806 07:45:49.925075 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip>
1807 07:45:49.926052 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip
1809 07:45:50.017242 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip>
1810 07:45:50.017901 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip
1812 07:45:50.110053 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip>
1813 07:45:50.110934 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip
1815 07:45:50.203075 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip>
1816 07:45:50.203728 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip
1818 07:45:50.297485 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip>
1819 07:45:50.298264 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip
1821 07:45:50.391722 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip>
1822 07:45:50.392805 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip
1824 07:45:50.486765 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip>
1825 07:45:50.487789 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip
1827 07:45:50.579991 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip>
1828 07:45:50.580921 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip
1830 07:45:50.674027 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip>
1831 07:45:50.674799 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip
1833 07:45:50.765437 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip>
1834 07:45:50.766283 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip
1836 07:45:50.859570 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip>
1837 07:45:50.860286 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip
1839 07:45:50.955984 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip>
1840 07:45:50.956933 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip
1842 07:45:51.051546 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip>
1843 07:45:51.052148 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip
1845 07:45:51.145116 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip>
1846 07:45:51.145710 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip
1848 07:45:51.236612 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip>
1849 07:45:51.237208 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip
1851 07:45:51.329345 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip>
1852 07:45:51.329949 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip
1854 07:45:51.420552 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip>
1855 07:45:51.421169 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip
1857 07:45:51.513005 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip>
1858 07:45:51.513980 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip
1860 07:45:51.605029 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip>
1861 07:45:51.605913 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip
1863 07:45:51.697362 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip>
1864 07:45:51.698227 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip
1866 07:45:51.789028 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip>
1867 07:45:51.789891 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip
1869 07:45:51.883612 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip>
1870 07:45:51.884460 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip
1872 07:45:51.975410 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip>
1873 07:45:51.976006 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip
1875 07:45:52.067357 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip>
1876 07:45:52.068596 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip
1878 07:45:52.157077 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip>
1879 07:45:52.158450 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip
1881 07:45:52.261191 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip>
1882 07:45:52.262444 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip
1884 07:45:52.372770 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip>
1885 07:45:52.373648 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip
1887 07:45:52.465604 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip>
1888 07:45:52.466526 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip
1890 07:45:52.555222 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass>
1891 07:45:52.556181 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass
1893 07:45:52.649344 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass>
1894 07:45:52.650262 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass
1896 07:45:52.741287 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass>
1897 07:45:52.742134 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass
1899 07:45:52.833790 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass>
1900 07:45:52.834457 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass
1902 07:45:52.925731 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass>
1903 07:45:52.926351 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass
1905 07:45:53.017586 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass>
1906 07:45:53.018231 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass
1908 07:45:53.119387 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass>
1909 07:45:53.120051 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass
1911 07:45:53.210741 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass>
1912 07:45:53.211736 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass
1914 07:45:53.303337 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail>
1915 07:45:53.304651 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail
1917 07:45:53.394385 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass>
1918 07:45:53.395029 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass
1920 07:45:53.484760 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass>
1921 07:45:53.485672 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass
1923 07:45:53.577443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass>
1924 07:45:53.578207 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass
1926 07:45:53.678873 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail>
1927 07:45:53.679844 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail
1929 07:45:53.781988 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip>
1930 07:45:53.782640 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip
1932 07:45:53.873652 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip>
1933 07:45:53.874404 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip
1935 07:45:53.963989 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip>
1936 07:45:53.964878 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip
1938 07:45:54.055793 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip>
1939 07:45:54.056385 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip
1941 07:45:54.143819 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip>
1942 07:45:54.144463 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip
1944 07:45:54.230574 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip>
1945 07:45:54.231470 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip
1947 07:45:54.324854 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip>
1948 07:45:54.325480 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip
1950 07:45:54.416986 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip>
1951 07:45:54.417623 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip
1953 07:45:54.507538 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip>
1954 07:45:54.508417 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip
1956 07:45:54.599874 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip>
1957 07:45:54.600709 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip
1959 07:45:54.694877 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip>
1960 07:45:54.695720 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip
1962 07:45:54.785417 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip>
1963 07:45:54.786249 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip
1965 07:45:54.877694 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip
1967 07:45:54.880766 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip>
1968 07:45:54.970491 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip
1970 07:45:54.973577 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip>
1971 07:45:55.064674 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip
1973 07:45:55.067805 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip>
1974 07:45:55.155594 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass>
1975 07:45:55.156371 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass
1977 07:45:55.242995 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail>
1978 07:45:55.243810 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail
1980 07:45:55.333548 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail>
1981 07:45:55.334244 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail
1983 07:45:55.428441 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip>
1984 07:45:55.429149 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip
1986 07:45:55.520730 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass>
1987 07:45:55.521425 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass
1989 07:45:55.610971 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail>
1990 07:45:55.611565 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail
1992 07:45:55.700357 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass>
1993 07:45:55.700961 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass
1995 07:45:55.792249 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail>
1996 07:45:55.792877 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail
1998 07:45:55.882647 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass>
1999 07:45:55.883296 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass
2001 07:45:55.976458 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass>
2002 07:45:55.977116 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass
2004 07:45:56.068242 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass>
2005 07:45:56.068899 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass
2007 07:45:56.162315 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass>
2008 07:45:56.162953 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass
2010 07:45:56.252369 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass>
2011 07:45:56.253006 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass
2013 07:45:56.343572 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass>
2014 07:45:56.344232 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass
2016 07:45:56.436639 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_eeprom_50 RESULT=pass>
2017 07:45:56.437287 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_eeprom_50 RESULT=pass
2019 07:45:56.529753 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_eeprom_50_nvmem-layout RESULT=skip>
2020 07:45:56.530415 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_eeprom_50_nvmem-layout RESULT=skip
2022 07:45:56.620098 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass>
2023 07:45:56.620773 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass
2025 07:45:56.713139 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass>
2026 07:45:56.713842 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass
2028 07:45:56.805106 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail>
2029 07:45:56.805729 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail
2031 07:45:56.897249 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail>
2032 07:45:56.897885 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail
2034 07:45:57.172464 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass>
2035 07:45:57.173107 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass
2037 07:45:57.274394 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail>
2038 07:45:57.275002 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail
2040 07:45:57.365745 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail>
2041 07:45:57.366383 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail
2043 07:45:57.455490 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass>
2044 07:45:57.456104 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass
2046 07:45:57.548234 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass>
2047 07:45:57.548862 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass
2049 07:45:57.641044 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass>
2050 07:45:57.641666 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass
2052 07:45:57.731753 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass>
2053 07:45:57.732378 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass
2055 07:45:57.821316 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass>
2056 07:45:57.821928 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass
2058 07:45:57.906479 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass>
2059 07:45:57.907104 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass
2061 07:45:57.997297 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass>
2062 07:45:57.997924 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass
2064 07:45:58.088387 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass>
2065 07:45:58.088958 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass
2067 07:45:58.178369 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass>
2068 07:45:58.178974 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass
2070 07:45:58.269229 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail>
2071 07:45:58.269786 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail
2073 07:45:58.361609 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip>
2074 07:45:58.362260 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip
2076 07:45:58.451234 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass>
2077 07:45:58.451871 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass
2079 07:45:58.540977 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass>
2080 07:45:58.541584 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass
2082 07:45:58.630630 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass>
2083 07:45:58.631239 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass
2085 07:45:58.721640 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass>
2086 07:45:58.722273 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass
2088 07:45:58.812144 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass>
2089 07:45:58.812679 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass
2091 07:45:58.901647 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass>
2092 07:45:58.902263 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass
2094 07:45:58.985741 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass>
2095 07:45:58.986390 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass
2097 07:45:59.081485 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass>
2098 07:45:59.082118 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass
2100 07:45:59.169937 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass>
2101 07:45:59.170491 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass
2103 07:45:59.262873 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass>
2104 07:45:59.263500 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass
2106 07:45:59.353069 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass>
2107 07:45:59.353652 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass
2109 07:45:59.444389 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass>
2110 07:45:59.444992 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass
2112 07:45:59.534357 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass>
2113 07:45:59.535038 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass
2115 07:45:59.624719 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass>
2116 07:45:59.625350 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass
2118 07:45:59.717924 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass>
2119 07:45:59.718545 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass
2121 07:45:59.810100 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass>
2122 07:45:59.810778 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass
2124 07:45:59.899416 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass>
2125 07:45:59.900039 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass
2127 07:45:59.992355 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass>
2128 07:45:59.992978 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass
2130 07:46:00.078958 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass>
2131 07:46:00.079575 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass
2133 07:46:00.173217 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass>
2134 07:46:00.173870 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass
2136 07:46:00.268127 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass>
2137 07:46:00.268721 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass
2139 07:46:00.362079 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_54 RESULT=fail>
2140 07:46:00.362732 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_54 RESULT=fail
2142 07:46:00.454387 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_54_nvmem-layout RESULT=skip>
2143 07:46:00.455050 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_54_nvmem-layout RESULT=skip
2145 07:46:00.542147 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_55 RESULT=fail>
2146 07:46:00.542820 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_55 RESULT=fail
2148 07:46:00.631842 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_55_nvmem-layout RESULT=skip>
2149 07:46:00.632524 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_55_nvmem-layout RESULT=skip
2151 07:46:00.721003 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_56 RESULT=fail>
2152 07:46:00.721635 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_56 RESULT=fail
2154 07:46:00.813763 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_56_nvmem-layout RESULT=skip>
2155 07:46:00.814463 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_56_nvmem-layout RESULT=skip
2157 07:46:00.904909 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_57 RESULT=fail>
2158 07:46:00.905539 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_57 RESULT=fail
2160 07:46:00.999411 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_57_nvmem-layout RESULT=skip>
2161 07:46:01.000086 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_57_nvmem-layout RESULT=skip
2163 07:46:01.092525 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass>
2164 07:46:01.093292 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass
2166 07:46:01.185744 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass>
2167 07:46:01.186425 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass
2169 07:46:01.285148 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass>
2170 07:46:01.285855 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass
2172 07:46:01.381868 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass>
2173 07:46:01.382528 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass
2175 07:46:01.474032 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass>
2176 07:46:01.474669 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass
2178 07:46:01.566954 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass>
2179 07:46:01.567605 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass
2181 07:46:01.658046 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass>
2182 07:46:01.658678 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass
2184 07:46:01.748868 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass>
2185 07:46:01.749527 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass
2187 07:46:01.839195 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass>
2188 07:46:01.839816 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass
2190 07:46:01.931529 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass>
2191 07:46:01.932197 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass
2193 07:46:02.025975 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass>
2194 07:46:02.026930 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass
2196 07:46:02.119384 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass>
2197 07:46:02.120473 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass
2199 07:46:02.246410 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass>
2200 07:46:02.247311 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass
2202 07:46:02.374181 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass>
2203 07:46:02.375094 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass
2205 07:46:02.494883 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip>
2206 07:46:02.495777 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip
2208 07:46:02.592454 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass>
2209 07:46:02.593414 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass
2211 07:46:02.686545 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass>
2212 07:46:02.687458 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass
2214 07:46:02.777458 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass>
2215 07:46:02.778401 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass
2217 07:46:02.868584 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass>
2218 07:46:02.869431 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass
2220 07:46:02.958483 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass>
2221 07:46:02.959326 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass
2223 07:46:03.050750 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass>
2224 07:46:03.051681 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass
2226 07:46:03.140289 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass>
2227 07:46:03.141078 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass
2229 07:46:03.231547 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail>
2230 07:46:03.232437 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail
2232 07:46:03.318097 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass>
2233 07:46:03.319043 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass
2235 07:46:03.409245 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass>
2236 07:46:03.410192 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass
2238 07:46:03.501701 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass>
2239 07:46:03.502619 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass
2241 07:46:03.593704 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass>
2242 07:46:03.594639 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass
2244 07:46:03.695459 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass>
2245 07:46:03.696075 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass
2247 07:46:03.785179 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass>
2248 07:46:03.785761 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass
2250 07:46:03.879620 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail>
2251 07:46:03.880229 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail
2253 07:46:03.971866 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip>
2254 07:46:03.972486 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip
2256 07:46:04.063203 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail>
2257 07:46:04.064138 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail
2259 07:46:04.152741 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip>
2260 07:46:04.153535 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip
2262 07:46:04.240009 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail>
2263 07:46:04.240839 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail
2265 07:46:04.331971 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail>
2266 07:46:04.332839 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail
2268 07:46:04.416829 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail>
2269 07:46:04.417610 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail
2271 07:46:04.509006 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail>
2272 07:46:04.509886 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail
2274 07:46:04.592607 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip>
2275 07:46:04.593372 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip
2277 07:46:04.682315 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass>
2278 07:46:04.683095 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass
2280 07:46:04.776271 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass>
2281 07:46:04.777097 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass
2283 07:46:04.868883 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip>
2284 07:46:04.869677 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip
2286 07:46:04.957355 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip
2288 07:46:04.960380 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip>
2289 07:46:05.048676 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass>
2290 07:46:05.049343 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass
2292 07:46:05.141455 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass>
2293 07:46:05.142417 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass
2295 07:46:05.233695 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass>
2296 07:46:05.234585 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass
2298 07:46:05.325436 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass>
2299 07:46:05.326386 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass
2301 07:46:05.415998 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass>
2302 07:46:05.416825 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass
2304 07:46:05.507577 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass>
2305 07:46:05.508463 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass
2307 07:46:05.598424 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass>
2308 07:46:05.599269 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass
2310 07:46:05.689586 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass>
2311 07:46:05.690524 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass
2313 07:46:05.779102 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass>
2314 07:46:05.779929 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass
2316 07:46:05.868623 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass>
2317 07:46:05.869494 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass
2319 07:46:05.959287 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass>
2320 07:46:05.960170 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass
2322 07:46:06.048529 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass>
2323 07:46:06.049409 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass
2325 07:46:06.140365 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass>
2326 07:46:06.141238 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass
2328 07:46:06.229805 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass>
2329 07:46:06.230712 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass
2331 07:46:06.320953 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass>
2332 07:46:06.322185 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass
2334 07:46:06.411868 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass>
2335 07:46:06.412774 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass
2337 07:46:06.504925 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail>
2338 07:46:06.505851 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail
2340 07:46:06.594990 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass>
2341 07:46:06.595860 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass
2343 07:46:06.686813 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass>
2344 07:46:06.687704 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass
2346 07:46:06.777682 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail>
2347 07:46:06.778616 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail
2349 07:46:06.867051 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass>
2350 07:46:06.867925 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass
2352 07:46:06.966671 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail>
2353 07:46:06.967636 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail
2355 07:46:07.063827 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass>
2356 07:46:07.064806 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass
2358 07:46:07.154765 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip>
2359 07:46:07.155669 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip
2361 07:46:07.245338 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip>
2362 07:46:07.246041 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip
2364 07:46:07.339111 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip>
2365 07:46:07.340195 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip
2367 07:46:07.434260 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass>
2368 07:46:07.435159 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass
2370 07:46:07.525661 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass>
2371 07:46:07.526584 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass
2373 07:46:07.618486 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass>
2374 07:46:07.619388 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass
2376 07:46:07.710517 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass>
2377 07:46:07.711587 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass
2379 07:46:07.799393 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail>
2380 07:46:07.800014 + set +x
2381 07:46:07.800740 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail
2383 07:46:07.803568 <LAVA_SIGNAL_ENDRUN 1_kselftest-dt 978505_1.6.2.4.5>
2384 07:46:07.804327 Received signal: <ENDRUN> 1_kselftest-dt 978505_1.6.2.4.5
2385 07:46:07.804836 Ending use of test pattern.
2386 07:46:07.805299 Ending test lava.1_kselftest-dt (978505_1.6.2.4.5), duration 85.07
2388 07:46:07.809106 <LAVA_TEST_RUNNER EXIT>
2389 07:46:07.809883 ok: lava_test_shell seems to have completed
2390 07:46:07.823948 dt_test_unprobed_devices_sh: fail
dt_test_unprobed_devices_sh_: skip
dt_test_unprobed_devices_sh_clk_mcasp0: pass
dt_test_unprobed_devices_sh_clk_mcasp0_fixed: skip
dt_test_unprobed_devices_sh_cpus_cpu_0: skip
dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate: skip
dt_test_unprobed_devices_sh_fixedregulator0: pass
dt_test_unprobed_devices_sh_leds: pass
dt_test_unprobed_devices_sh_ocp: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0: fail
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_eeprom_50: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_eeprom_50_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_54: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_54_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_55: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_55_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_56: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_56_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_57: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_57_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000: skip
dt_test_unprobed_devices_sh_ocp_target-module_47400000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800: pass
dt_test_unprobed_devices_sh_ocp_target-module_47810000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_50000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_53500000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_56000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0: skip
dt_test_unprobed_devices_sh_opp-table: skip
dt_test_unprobed_devices_sh_soc: skip
dt_test_unprobed_devices_sh_sound: pass
dt_test_unprobed_devices_sh_target-module_4b000000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0: pass
shardfile-dt: pass
2391 07:46:07.826079 end: 3.1 lava-test-shell (duration 00:01:26) [common]
2392 07:46:07.826713 end: 3 lava-test-retry (duration 00:01:26) [common]
2393 07:46:07.827168 start: 4 finalize (timeout 00:05:28) [common]
2394 07:46:07.827507 start: 4.1 power-off (timeout 00:00:30) [common]
2395 07:46:07.828182 Calling: 'curl' 'http://conserv3.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=beaglebone-black-05'
2396 07:46:07.862385 >> OK - accepted request
2397 07:46:07.864022 Returned 0 in 0 seconds
2398 07:46:07.965104 end: 4.1 power-off (duration 00:00:00) [common]
2400 07:46:07.967063 start: 4.2 read-feedback (timeout 00:05:28) [common]
2401 07:46:07.968293 Listened to connection for namespace 'common' for up to 1s
2402 07:46:07.969243 Listened to connection for namespace 'common' for up to 1s
2403 07:46:08.969024 Finalising connection for namespace 'common'
2404 07:46:08.969531 Disconnecting from shell: Finalise
2405 07:46:08.969890 / #
2406 07:46:09.070634 end: 4.2 read-feedback (duration 00:00:01) [common]
2407 07:46:09.071120 end: 4 finalize (duration 00:00:01) [common]
2408 07:46:09.071486 Cleaning after the job
2409 07:46:09.071848 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/978505/tftp-deploy-as9cs3pz/ramdisk
2410 07:46:09.073256 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/978505/tftp-deploy-as9cs3pz/kernel
2411 07:46:09.074448 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/978505/tftp-deploy-as9cs3pz/dtb
2412 07:46:09.075302 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/978505/tftp-deploy-as9cs3pz/nfsrootfs
2413 07:46:09.111704 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/978505/tftp-deploy-as9cs3pz/modules
2414 07:46:09.116135 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/978505
2415 07:46:12.117641 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/978505
2416 07:46:12.118236 Job finished correctly