Boot log: meson-sm1-s905d3-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 07:16:34.927487 lava-dispatcher, installed at version: 2024.01
2 07:16:34.928284 start: 0 validate
3 07:16:34.928769 Start time: 2024-11-12 07:16:34.928738+00:00 (UTC)
4 07:16:34.929310 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 07:16:34.929849 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230703.0%2Farm64%2Frootfs.cpio.gz exists
6 07:16:34.970936 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 07:16:34.971480 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241112%2Farm64%2Fdefconfig%2BCONFIG_ARM64_64K_PAGES%3Dy%2Fclang-17%2Fkernel%2FImage exists
8 07:16:35.001729 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 07:16:35.002375 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241112%2Farm64%2Fdefconfig%2BCONFIG_ARM64_64K_PAGES%3Dy%2Fclang-17%2Fdtbs%2Famlogic%2Fmeson-sm1-s905d3-libretech-cc.dtb exists
10 07:16:41.077958 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 07:16:41.078437 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241112%2Farm64%2Fdefconfig%2BCONFIG_ARM64_64K_PAGES%3Dy%2Fclang-17%2Fmodules.tar.xz exists
12 07:16:42.127871 validate duration: 7.20
14 07:16:42.129460 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 07:16:42.130081 start: 1.1 download-retry (timeout 00:10:00) [common]
16 07:16:42.130715 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 07:16:42.131714 Not decompressing ramdisk as can be used compressed.
18 07:16:42.132500 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230703.0/arm64/rootfs.cpio.gz
19 07:16:42.133087 saving as /var/lib/lava/dispatcher/tmp/978302/tftp-deploy-5tqgi530/ramdisk/rootfs.cpio.gz
20 07:16:42.133411 total size: 8181887 (7 MB)
21 07:16:42.179284 progress 0 % (0 MB)
22 07:16:42.191550 progress 5 % (0 MB)
23 07:16:42.204042 progress 10 % (0 MB)
24 07:16:42.217615 progress 15 % (1 MB)
25 07:16:42.226274 progress 20 % (1 MB)
26 07:16:42.232225 progress 25 % (1 MB)
27 07:16:42.237909 progress 30 % (2 MB)
28 07:16:42.244057 progress 35 % (2 MB)
29 07:16:42.249698 progress 40 % (3 MB)
30 07:16:42.255758 progress 45 % (3 MB)
31 07:16:42.261693 progress 50 % (3 MB)
32 07:16:42.267995 progress 55 % (4 MB)
33 07:16:42.273730 progress 60 % (4 MB)
34 07:16:42.279799 progress 65 % (5 MB)
35 07:16:42.285906 progress 70 % (5 MB)
36 07:16:42.291971 progress 75 % (5 MB)
37 07:16:42.297930 progress 80 % (6 MB)
38 07:16:42.304130 progress 85 % (6 MB)
39 07:16:42.309775 progress 90 % (7 MB)
40 07:16:42.315790 progress 95 % (7 MB)
41 07:16:42.320853 progress 100 % (7 MB)
42 07:16:42.321565 7 MB downloaded in 0.19 s (41.47 MB/s)
43 07:16:42.322136 end: 1.1.1 http-download (duration 00:00:00) [common]
45 07:16:42.323070 end: 1.1 download-retry (duration 00:00:00) [common]
46 07:16:42.323381 start: 1.2 download-retry (timeout 00:10:00) [common]
47 07:16:42.323670 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 07:16:42.324199 downloading http://storage.kernelci.org/next/master/next-20241112/arm64/defconfig+CONFIG_ARM64_64K_PAGES=y/clang-17/kernel/Image
49 07:16:42.324476 saving as /var/lib/lava/dispatcher/tmp/978302/tftp-deploy-5tqgi530/kernel/Image
50 07:16:42.324703 total size: 39834112 (37 MB)
51 07:16:42.324937 No compression specified
52 07:16:42.361073 progress 0 % (0 MB)
53 07:16:42.390073 progress 5 % (1 MB)
54 07:16:42.416596 progress 10 % (3 MB)
55 07:16:42.442067 progress 15 % (5 MB)
56 07:16:42.467500 progress 20 % (7 MB)
57 07:16:42.492460 progress 25 % (9 MB)
58 07:16:42.519207 progress 30 % (11 MB)
59 07:16:42.545458 progress 35 % (13 MB)
60 07:16:42.571281 progress 40 % (15 MB)
61 07:16:42.597390 progress 45 % (17 MB)
62 07:16:42.622713 progress 50 % (19 MB)
63 07:16:42.648148 progress 55 % (20 MB)
64 07:16:42.673475 progress 60 % (22 MB)
65 07:16:42.699474 progress 65 % (24 MB)
66 07:16:42.725005 progress 70 % (26 MB)
67 07:16:42.751024 progress 75 % (28 MB)
68 07:16:42.776348 progress 80 % (30 MB)
69 07:16:42.802810 progress 85 % (32 MB)
70 07:16:42.831688 progress 90 % (34 MB)
71 07:16:42.856520 progress 95 % (36 MB)
72 07:16:42.881486 progress 100 % (37 MB)
73 07:16:42.882223 37 MB downloaded in 0.56 s (68.14 MB/s)
74 07:16:42.882728 end: 1.2.1 http-download (duration 00:00:01) [common]
76 07:16:42.883553 end: 1.2 download-retry (duration 00:00:01) [common]
77 07:16:42.883831 start: 1.3 download-retry (timeout 00:09:59) [common]
78 07:16:42.884143 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 07:16:42.884668 downloading http://storage.kernelci.org/next/master/next-20241112/arm64/defconfig+CONFIG_ARM64_64K_PAGES=y/clang-17/dtbs/amlogic/meson-sm1-s905d3-libretech-cc.dtb
80 07:16:42.884977 saving as /var/lib/lava/dispatcher/tmp/978302/tftp-deploy-5tqgi530/dtb/meson-sm1-s905d3-libretech-cc.dtb
81 07:16:42.885205 total size: 53209 (0 MB)
82 07:16:42.885538 No compression specified
83 07:16:42.924663 progress 61 % (0 MB)
84 07:16:42.925586 progress 100 % (0 MB)
85 07:16:42.926216 0 MB downloaded in 0.04 s (1.24 MB/s)
86 07:16:42.926783 end: 1.3.1 http-download (duration 00:00:00) [common]
88 07:16:42.927706 end: 1.3 download-retry (duration 00:00:00) [common]
89 07:16:42.928017 start: 1.4 download-retry (timeout 00:09:59) [common]
90 07:16:42.928309 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 07:16:42.928855 downloading http://storage.kernelci.org/next/master/next-20241112/arm64/defconfig+CONFIG_ARM64_64K_PAGES=y/clang-17/modules.tar.xz
92 07:16:42.929176 saving as /var/lib/lava/dispatcher/tmp/978302/tftp-deploy-5tqgi530/modules/modules.tar
93 07:16:42.929424 total size: 11828672 (11 MB)
94 07:16:42.929657 Using unxz to decompress xz
95 07:16:42.977097 progress 0 % (0 MB)
96 07:16:43.050459 progress 5 % (0 MB)
97 07:16:43.133603 progress 10 % (1 MB)
98 07:16:43.238153 progress 15 % (1 MB)
99 07:16:43.337824 progress 20 % (2 MB)
100 07:16:43.427068 progress 25 % (2 MB)
101 07:16:43.507137 progress 30 % (3 MB)
102 07:16:43.592309 progress 35 % (3 MB)
103 07:16:43.677575 progress 40 % (4 MB)
104 07:16:43.755702 progress 45 % (5 MB)
105 07:16:43.845847 progress 50 % (5 MB)
106 07:16:43.930638 progress 55 % (6 MB)
107 07:16:44.018661 progress 60 % (6 MB)
108 07:16:44.102077 progress 65 % (7 MB)
109 07:16:44.187594 progress 70 % (7 MB)
110 07:16:44.272480 progress 75 % (8 MB)
111 07:16:44.369181 progress 80 % (9 MB)
112 07:16:44.468904 progress 85 % (9 MB)
113 07:16:44.570963 progress 90 % (10 MB)
114 07:16:44.665801 progress 95 % (10 MB)
115 07:16:44.744485 progress 100 % (11 MB)
116 07:16:44.759312 11 MB downloaded in 1.83 s (6.16 MB/s)
117 07:16:44.760078 end: 1.4.1 http-download (duration 00:00:02) [common]
119 07:16:44.761708 end: 1.4 download-retry (duration 00:00:02) [common]
120 07:16:44.762232 start: 1.5 prepare-tftp-overlay (timeout 00:09:57) [common]
121 07:16:44.762750 start: 1.5.1 extract-nfsrootfs (timeout 00:09:57) [common]
122 07:16:44.763236 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 07:16:44.763733 start: 1.5.2 lava-overlay (timeout 00:09:57) [common]
124 07:16:44.764827 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/978302/lava-overlay-nny3tyi7
125 07:16:44.765650 makedir: /var/lib/lava/dispatcher/tmp/978302/lava-overlay-nny3tyi7/lava-978302/bin
126 07:16:44.766276 makedir: /var/lib/lava/dispatcher/tmp/978302/lava-overlay-nny3tyi7/lava-978302/tests
127 07:16:44.766883 makedir: /var/lib/lava/dispatcher/tmp/978302/lava-overlay-nny3tyi7/lava-978302/results
128 07:16:44.767497 Creating /var/lib/lava/dispatcher/tmp/978302/lava-overlay-nny3tyi7/lava-978302/bin/lava-add-keys
129 07:16:44.768494 Creating /var/lib/lava/dispatcher/tmp/978302/lava-overlay-nny3tyi7/lava-978302/bin/lava-add-sources
130 07:16:44.769486 Creating /var/lib/lava/dispatcher/tmp/978302/lava-overlay-nny3tyi7/lava-978302/bin/lava-background-process-start
131 07:16:44.770451 Creating /var/lib/lava/dispatcher/tmp/978302/lava-overlay-nny3tyi7/lava-978302/bin/lava-background-process-stop
132 07:16:44.771435 Creating /var/lib/lava/dispatcher/tmp/978302/lava-overlay-nny3tyi7/lava-978302/bin/lava-common-functions
133 07:16:44.772394 Creating /var/lib/lava/dispatcher/tmp/978302/lava-overlay-nny3tyi7/lava-978302/bin/lava-echo-ipv4
134 07:16:44.773300 Creating /var/lib/lava/dispatcher/tmp/978302/lava-overlay-nny3tyi7/lava-978302/bin/lava-install-packages
135 07:16:44.774190 Creating /var/lib/lava/dispatcher/tmp/978302/lava-overlay-nny3tyi7/lava-978302/bin/lava-installed-packages
136 07:16:44.775069 Creating /var/lib/lava/dispatcher/tmp/978302/lava-overlay-nny3tyi7/lava-978302/bin/lava-os-build
137 07:16:44.775960 Creating /var/lib/lava/dispatcher/tmp/978302/lava-overlay-nny3tyi7/lava-978302/bin/lava-probe-channel
138 07:16:44.776917 Creating /var/lib/lava/dispatcher/tmp/978302/lava-overlay-nny3tyi7/lava-978302/bin/lava-probe-ip
139 07:16:44.777818 Creating /var/lib/lava/dispatcher/tmp/978302/lava-overlay-nny3tyi7/lava-978302/bin/lava-target-ip
140 07:16:44.778705 Creating /var/lib/lava/dispatcher/tmp/978302/lava-overlay-nny3tyi7/lava-978302/bin/lava-target-mac
141 07:16:44.779630 Creating /var/lib/lava/dispatcher/tmp/978302/lava-overlay-nny3tyi7/lava-978302/bin/lava-target-storage
142 07:16:44.780677 Creating /var/lib/lava/dispatcher/tmp/978302/lava-overlay-nny3tyi7/lava-978302/bin/lava-test-case
143 07:16:44.781593 Creating /var/lib/lava/dispatcher/tmp/978302/lava-overlay-nny3tyi7/lava-978302/bin/lava-test-event
144 07:16:44.782471 Creating /var/lib/lava/dispatcher/tmp/978302/lava-overlay-nny3tyi7/lava-978302/bin/lava-test-feedback
145 07:16:44.783362 Creating /var/lib/lava/dispatcher/tmp/978302/lava-overlay-nny3tyi7/lava-978302/bin/lava-test-raise
146 07:16:44.784307 Creating /var/lib/lava/dispatcher/tmp/978302/lava-overlay-nny3tyi7/lava-978302/bin/lava-test-reference
147 07:16:44.785215 Creating /var/lib/lava/dispatcher/tmp/978302/lava-overlay-nny3tyi7/lava-978302/bin/lava-test-runner
148 07:16:44.786111 Creating /var/lib/lava/dispatcher/tmp/978302/lava-overlay-nny3tyi7/lava-978302/bin/lava-test-set
149 07:16:44.787028 Creating /var/lib/lava/dispatcher/tmp/978302/lava-overlay-nny3tyi7/lava-978302/bin/lava-test-shell
150 07:16:44.788045 Updating /var/lib/lava/dispatcher/tmp/978302/lava-overlay-nny3tyi7/lava-978302/bin/lava-install-packages (oe)
151 07:16:44.789144 Updating /var/lib/lava/dispatcher/tmp/978302/lava-overlay-nny3tyi7/lava-978302/bin/lava-installed-packages (oe)
152 07:16:44.789987 Creating /var/lib/lava/dispatcher/tmp/978302/lava-overlay-nny3tyi7/lava-978302/environment
153 07:16:44.790706 LAVA metadata
154 07:16:44.791187 - LAVA_JOB_ID=978302
155 07:16:44.791611 - LAVA_DISPATCHER_IP=192.168.6.2
156 07:16:44.792325 start: 1.5.2.1 ssh-authorize (timeout 00:09:57) [common]
157 07:16:44.794131 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 07:16:44.794724 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:57) [common]
159 07:16:44.795134 skipped lava-vland-overlay
160 07:16:44.795616 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 07:16:44.796189 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:57) [common]
162 07:16:44.796442 skipped lava-multinode-overlay
163 07:16:44.796695 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 07:16:44.796951 start: 1.5.2.4 test-definition (timeout 00:09:57) [common]
165 07:16:44.797215 Loading test definitions
166 07:16:44.797507 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:57) [common]
167 07:16:44.797735 Using /lava-978302 at stage 0
168 07:16:44.798984 uuid=978302_1.5.2.4.1 testdef=None
169 07:16:44.799311 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 07:16:44.799581 start: 1.5.2.4.2 test-overlay (timeout 00:09:57) [common]
171 07:16:44.801499 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 07:16:44.802319 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:57) [common]
174 07:16:44.804639 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 07:16:44.805485 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:57) [common]
177 07:16:44.807702 runner path: /var/lib/lava/dispatcher/tmp/978302/lava-overlay-nny3tyi7/lava-978302/0/tests/0_dmesg test_uuid 978302_1.5.2.4.1
178 07:16:44.808330 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 07:16:44.809109 Creating lava-test-runner.conf files
181 07:16:44.809313 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/978302/lava-overlay-nny3tyi7/lava-978302/0 for stage 0
182 07:16:44.809661 - 0_dmesg
183 07:16:44.810020 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 07:16:44.810303 start: 1.5.2.5 compress-overlay (timeout 00:09:57) [common]
185 07:16:44.834379 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 07:16:44.834804 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:57) [common]
187 07:16:44.835073 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 07:16:44.835344 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 07:16:44.835609 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:57) [common]
190 07:16:45.892503 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
191 07:16:45.893244 start: 1.5.4 extract-modules (timeout 00:09:56) [common]
192 07:16:45.893713 extracting modules file /var/lib/lava/dispatcher/tmp/978302/tftp-deploy-5tqgi530/modules/modules.tar to /var/lib/lava/dispatcher/tmp/978302/extract-overlay-ramdisk-_q4hmuwr/ramdisk
193 07:16:47.299261 end: 1.5.4 extract-modules (duration 00:00:01) [common]
194 07:16:47.299756 start: 1.5.5 apply-overlay-tftp (timeout 00:09:55) [common]
195 07:16:47.300073 [common] Applying overlay /var/lib/lava/dispatcher/tmp/978302/compress-overlay-iqefvjt2/overlay-1.5.2.5.tar.gz to ramdisk
196 07:16:47.300295 [common] Applying overlay /var/lib/lava/dispatcher/tmp/978302/compress-overlay-iqefvjt2/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/978302/extract-overlay-ramdisk-_q4hmuwr/ramdisk
197 07:16:47.334696 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 07:16:47.335212 start: 1.5.6 prepare-kernel (timeout 00:09:55) [common]
199 07:16:47.335545 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:55) [common]
200 07:16:47.335815 Converting downloaded kernel to a uImage
201 07:16:47.336220 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/978302/tftp-deploy-5tqgi530/kernel/Image /var/lib/lava/dispatcher/tmp/978302/tftp-deploy-5tqgi530/kernel/uImage
202 07:16:47.759162 output: Image Name:
203 07:16:47.759588 output: Created: Tue Nov 12 07:16:47 2024
204 07:16:47.759801 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 07:16:47.760047 output: Data Size: 39834112 Bytes = 38900.50 KiB = 37.99 MiB
206 07:16:47.760257 output: Load Address: 01080000
207 07:16:47.760454 output: Entry Point: 01080000
208 07:16:47.760651 output:
209 07:16:47.760984 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
210 07:16:47.761250 end: 1.5.6 prepare-kernel (duration 00:00:00) [common]
211 07:16:47.761520 start: 1.5.7 configure-preseed-file (timeout 00:09:54) [common]
212 07:16:47.761773 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 07:16:47.762030 start: 1.5.8 compress-ramdisk (timeout 00:09:54) [common]
214 07:16:47.762286 Building ramdisk /var/lib/lava/dispatcher/tmp/978302/extract-overlay-ramdisk-_q4hmuwr/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/978302/extract-overlay-ramdisk-_q4hmuwr/ramdisk
215 07:16:50.742050 >> 189689 blocks
216 07:16:59.123120 Adding RAMdisk u-boot header.
217 07:16:59.123567 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/978302/extract-overlay-ramdisk-_q4hmuwr/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/978302/extract-overlay-ramdisk-_q4hmuwr/ramdisk.cpio.gz.uboot
218 07:16:59.393557 output: Image Name:
219 07:16:59.393980 output: Created: Tue Nov 12 07:16:59 2024
220 07:16:59.394405 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 07:16:59.394822 output: Data Size: 26901491 Bytes = 26270.99 KiB = 25.66 MiB
222 07:16:59.395233 output: Load Address: 00000000
223 07:16:59.395631 output: Entry Point: 00000000
224 07:16:59.396123 output:
225 07:16:59.397145 rename /var/lib/lava/dispatcher/tmp/978302/extract-overlay-ramdisk-_q4hmuwr/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/978302/tftp-deploy-5tqgi530/ramdisk/ramdisk.cpio.gz.uboot
226 07:16:59.397876 end: 1.5.8 compress-ramdisk (duration 00:00:12) [common]
227 07:16:59.398431 end: 1.5 prepare-tftp-overlay (duration 00:00:15) [common]
228 07:16:59.398967 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:43) [common]
229 07:16:59.399426 No LXC device requested
230 07:16:59.399935 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 07:16:59.400500 start: 1.7 deploy-device-env (timeout 00:09:43) [common]
232 07:16:59.401004 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 07:16:59.401421 Checking files for TFTP limit of 4294967296 bytes.
234 07:16:59.404115 end: 1 tftp-deploy (duration 00:00:17) [common]
235 07:16:59.404720 start: 2 uboot-action (timeout 00:05:00) [common]
236 07:16:59.405252 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 07:16:59.405998 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 07:16:59.406564 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 07:16:59.407109 Using kernel file from prepare-kernel: 978302/tftp-deploy-5tqgi530/kernel/uImage
240 07:16:59.407723 substitutions:
241 07:16:59.408166 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 07:16:59.408576 - {DTB_ADDR}: 0x01070000
243 07:16:59.408977 - {DTB}: 978302/tftp-deploy-5tqgi530/dtb/meson-sm1-s905d3-libretech-cc.dtb
244 07:16:59.409380 - {INITRD}: 978302/tftp-deploy-5tqgi530/ramdisk/ramdisk.cpio.gz.uboot
245 07:16:59.409777 - {KERNEL_ADDR}: 0x01080000
246 07:16:59.410172 - {KERNEL}: 978302/tftp-deploy-5tqgi530/kernel/uImage
247 07:16:59.410569 - {LAVA_MAC}: None
248 07:16:59.411006 - {PRESEED_CONFIG}: None
249 07:16:59.411404 - {PRESEED_LOCAL}: None
250 07:16:59.411793 - {RAMDISK_ADDR}: 0x08000000
251 07:16:59.412219 - {RAMDISK}: 978302/tftp-deploy-5tqgi530/ramdisk/ramdisk.cpio.gz.uboot
252 07:16:59.412621 - {ROOT_PART}: None
253 07:16:59.413018 - {ROOT}: None
254 07:16:59.413412 - {SERVER_IP}: 192.168.6.2
255 07:16:59.413807 - {TEE_ADDR}: 0x83000000
256 07:16:59.414197 - {TEE}: None
257 07:16:59.414588 Parsed boot commands:
258 07:16:59.414968 - setenv autoload no
259 07:16:59.415357 - setenv initrd_high 0xffffffff
260 07:16:59.415744 - setenv fdt_high 0xffffffff
261 07:16:59.416165 - dhcp
262 07:16:59.416562 - setenv serverip 192.168.6.2
263 07:16:59.416955 - tftpboot 0x01080000 978302/tftp-deploy-5tqgi530/kernel/uImage
264 07:16:59.417347 - tftpboot 0x08000000 978302/tftp-deploy-5tqgi530/ramdisk/ramdisk.cpio.gz.uboot
265 07:16:59.417739 - tftpboot 0x01070000 978302/tftp-deploy-5tqgi530/dtb/meson-sm1-s905d3-libretech-cc.dtb
266 07:16:59.418129 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 07:16:59.418529 - bootm 0x01080000 0x08000000 0x01070000
268 07:16:59.419048 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 07:16:59.420767 start: 2.3 connect-device (timeout 00:05:00) [common]
271 07:16:59.421041 [common] connect-device Connecting to device using 'telnet conserv1 3008'
272 07:16:59.433108 Setting prompt string to ['lava-test: # ']
273 07:16:59.434079 end: 2.3 connect-device (duration 00:00:00) [common]
274 07:16:59.434446 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 07:16:59.434740 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 07:16:59.435008 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 07:16:59.435636 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=solitude-01'
278 07:16:59.484159 >> OK - accepted request
279 07:16:59.488137 Returned 0 in 0 seconds
280 07:16:59.589299 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
282 07:16:59.590922 end: 2.4.1 reset-device (duration 00:00:00) [common]
283 07:16:59.591511 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
284 07:16:59.592082 Setting prompt string to ['Hit any key to stop autoboot']
285 07:16:59.592555 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 07:16:59.594109 Trying 192.168.56.21...
287 07:16:59.594586 Connected to conserv1.
288 07:16:59.595015 Escape character is '^]'.
289 07:16:59.595431
290 07:16:59.595866 ser2net port telnet,3008 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.3.3:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
291 07:16:59.596348
292 07:17:09.574609 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
293 07:17:09.575033 bl2_stage_init 0x01
294 07:17:09.575274 bl2_stage_init 0x81
295 07:17:09.580165 hw id: 0x0000 - pwm id 0x01
296 07:17:09.580536 bl2_stage_init 0xc1
297 07:17:09.585737 bl2_stage_init 0x02
298 07:17:09.586076
299 07:17:09.586312 L0:00000000
300 07:17:09.586536 L1:00000703
301 07:17:09.586753 L2:00008067
302 07:17:09.586969 L3:15000000
303 07:17:09.591244 S1:00000000
304 07:17:09.591574 B2:20282000
305 07:17:09.591795 B1:a0f83180
306 07:17:09.592037
307 07:17:09.592262 TE: 69961
308 07:17:09.592474
309 07:17:09.596900 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
310 07:17:09.597221
311 07:17:09.602533 Board ID = 1
312 07:17:09.602855 Set cpu clk to 24M
313 07:17:09.603071 Set clk81 to 24M
314 07:17:09.608143 Use GP1_pll as DSU clk.
315 07:17:09.608463 DSU clk: 1200 Mhz
316 07:17:09.608675 CPU clk: 1200 MHz
317 07:17:09.613736 Set clk81 to 166.6M
318 07:17:09.619240 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
319 07:17:09.619564 board id: 1
320 07:17:09.626592 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
321 07:17:09.637524 fw parse done
322 07:17:09.643387 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
323 07:17:09.686403 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
324 07:17:09.697474 PIEI prepare done
325 07:17:09.697834 fastboot data load
326 07:17:09.698057 fastboot data verify
327 07:17:09.703055 verify result: 266
328 07:17:09.708651 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
329 07:17:09.708988 LPDDR4 probe
330 07:17:09.709207 ddr clk to 1584MHz
331 07:17:09.716635 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
332 07:17:09.754513
333 07:17:09.754926 dmc_version 0001
334 07:17:09.761450 Check phy result
335 07:17:09.767384 INFO : End of CA training
336 07:17:09.767712 INFO : End of initialization
337 07:17:09.773033 INFO : Training has run successfully!
338 07:17:09.773383 Check phy result
339 07:17:09.778605 INFO : End of initialization
340 07:17:09.778939 INFO : End of read enable training
341 07:17:09.784217 INFO : End of fine write leveling
342 07:17:09.789774 INFO : End of Write leveling coarse delay
343 07:17:09.790119 INFO : Training has run successfully!
344 07:17:09.790341 Check phy result
345 07:17:09.795415 INFO : End of initialization
346 07:17:09.795769 INFO : End of read dq deskew training
347 07:17:09.800993 INFO : End of MPR read delay center optimization
348 07:17:09.806594 INFO : End of write delay center optimization
349 07:17:09.812197 INFO : End of read delay center optimization
350 07:17:09.812520 INFO : End of max read latency training
351 07:17:09.817797 INFO : Training has run successfully!
352 07:17:09.818137 1D training succeed
353 07:17:09.826927 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
354 07:17:09.875419 Check phy result
355 07:17:09.875858 INFO : End of initialization
356 07:17:09.902761 INFO : End of 2D read delay Voltage center optimization
357 07:17:09.926960 INFO : End of 2D read delay Voltage center optimization
358 07:17:09.983656 INFO : End of 2D write delay Voltage center optimization
359 07:17:10.037600 INFO : End of 2D write delay Voltage center optimization
360 07:17:10.043193 INFO : Training has run successfully!
361 07:17:10.043610
362 07:17:10.043866 channel==0
363 07:17:10.048816 RxClkDly_Margin_A0==78 ps 8
364 07:17:10.049238 TxDqDly_Margin_A0==98 ps 10
365 07:17:10.054540 RxClkDly_Margin_A1==88 ps 9
366 07:17:10.054948 TxDqDly_Margin_A1==88 ps 9
367 07:17:10.055202 TrainedVREFDQ_A0==74
368 07:17:10.059946 TrainedVREFDQ_A1==74
369 07:17:10.060326 VrefDac_Margin_A0==25
370 07:17:10.060569 DeviceVref_Margin_A0==40
371 07:17:10.065877 VrefDac_Margin_A1==23
372 07:17:10.066292 DeviceVref_Margin_A1==40
373 07:17:10.066539
374 07:17:10.066774
375 07:17:10.067007 channel==1
376 07:17:10.071153 RxClkDly_Margin_A0==78 ps 8
377 07:17:10.071523 TxDqDly_Margin_A0==88 ps 9
378 07:17:10.076753 RxClkDly_Margin_A1==69 ps 7
379 07:17:10.077146 TxDqDly_Margin_A1==88 ps 9
380 07:17:10.084276 TrainedVREFDQ_A0==77
381 07:17:10.084932 TrainedVREFDQ_A1==78
382 07:17:10.085351 VrefDac_Margin_A0==22
383 07:17:10.088136 DeviceVref_Margin_A0==37
384 07:17:10.089159 VrefDac_Margin_A1==23
385 07:17:10.090026 DeviceVref_Margin_A1==36
386 07:17:10.093662
387 07:17:10.094464 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
388 07:17:10.095003
389 07:17:10.127173 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000015 00000018 00000017 00000017 00000017 00000018 00000018 00000018 00000019 00000019 00000018 00000019 00000016 00000018 00000015 00000016 00000017 00000019 00000019 00000018 00000018 0000001c 00000018 00000016 00000017 dram_vref_reg_value 0x 00000061
390 07:17:10.128091 2D training succeed
391 07:17:10.132677 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
392 07:17:10.138480 auto size-- 65535DDR cs0 size: 2048MB
393 07:17:10.139069 DDR cs1 size: 2048MB
394 07:17:10.143928 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
395 07:17:10.144562 cs0 DataBus test pass
396 07:17:10.149542 cs1 DataBus test pass
397 07:17:10.150130 cs0 AddrBus test pass
398 07:17:10.150644 cs1 AddrBus test pass
399 07:17:10.151160
400 07:17:10.155110 100bdlr_step_size ps== 478
401 07:17:10.155716 result report
402 07:17:10.160838 boot times 0Enable ddr reg access
403 07:17:10.165854 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
404 07:17:10.179652 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
405 07:17:10.839040 bl2z: ptr: 05129330, size: 00001e40
406 07:17:10.847783 0.0;M3 CHK:0;cm4_sp_mode 0
407 07:17:10.848402 MVN_1=0x00000000
408 07:17:10.848933 MVN_2=0x00000000
409 07:17:10.859291 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
410 07:17:10.859920 OPS=0x04
411 07:17:10.860498 ring efuse init
412 07:17:10.862225 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
413 07:17:10.867845 [0.017354 Inits done]
414 07:17:10.868521 secure task start!
415 07:17:10.869063 high task start!
416 07:17:10.869584 low task start!
417 07:17:10.872152 run into bl31
418 07:17:10.880787 NOTICE: BL31: v1.3(release):4fc40b1
419 07:17:10.888617 NOTICE: BL31: Built : 15:57:33, May 22 2019
420 07:17:10.889204 NOTICE: BL31: G12A normal boot!
421 07:17:10.904215 NOTICE: BL31: BL33 decompress pass
422 07:17:10.909876 ERROR: Error initializing runtime service opteed_fast
423 07:17:13.628510 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0; SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
424 07:17:13.629346 bl2_stage_init 0x01
425 07:17:13.629904 bl2_stage_init 0x81
426 07:17:13.633935 hw id: 0x0000 - pwm id 0x01
427 07:17:13.634523 bl2_stage_init 0xc1
428 07:17:13.639574 bl2_stage_init 0x02
429 07:17:13.640280
430 07:17:13.640863 L0:00000000
431 07:17:13.641382 L1:00000703
432 07:17:13.641902 L2:00008067
433 07:17:13.642411 L3:15000000
434 07:17:13.645129 S1:00000000
435 07:17:13.645686 B2:20282000
436 07:17:13.646219 B1:a0f83180
437 07:17:13.646733
438 07:17:13.647252 TE: 72560
439 07:17:13.647776
440 07:17:13.650768 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
441 07:17:13.651325
442 07:17:13.656379 Board ID = 1
443 07:17:13.656960 Set cpu clk to 24M
444 07:17:13.657494 Set clk81 to 24M
445 07:17:13.661998 Use GP1_pll as DSU clk.
446 07:17:13.662554 DSU clk: 1200 Mhz
447 07:17:13.663081 CPU clk: 1200 MHz
448 07:17:13.667596 Set clk81 to 166.6M
449 07:17:13.673161 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
450 07:17:13.673727 board id: 1
451 07:17:13.680398 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
452 07:17:13.691095 fw parse done
453 07:17:13.697043 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
454 07:17:13.738816 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
455 07:17:13.750579 PIEI prepare done
456 07:17:13.751168 fastboot data load
457 07:17:13.751720 fastboot data verify
458 07:17:13.756152 verify result: 266
459 07:17:13.761875 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
460 07:17:13.762448 LPDDR4 probe
461 07:17:13.762974 ddr clk to 1584MHz
462 07:17:13.769885 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
463 07:17:13.806064
464 07:17:13.806665 dmc_version 0001
465 07:17:13.813300 Check phy result
466 07:17:13.819684 INFO : End of CA training
467 07:17:13.820357 INFO : End of initialization
468 07:17:13.825165 INFO : Training has run successfully!
469 07:17:13.825721 Check phy result
470 07:17:13.830904 INFO : End of initialization
471 07:17:13.831475 INFO : End of read enable training
472 07:17:13.836354 INFO : End of fine write leveling
473 07:17:13.841946 INFO : End of Write leveling coarse delay
474 07:17:13.842503 INFO : Training has run successfully!
475 07:17:13.843029 Check phy result
476 07:17:13.847636 INFO : End of initialization
477 07:17:13.848209 INFO : End of read dq deskew training
478 07:17:13.853162 INFO : End of MPR read delay center optimization
479 07:17:13.858916 INFO : End of write delay center optimization
480 07:17:13.864398 INFO : End of read delay center optimization
481 07:17:13.864991 INFO : End of max read latency training
482 07:17:13.869968 INFO : Training has run successfully!
483 07:17:13.870536 1D training succeed
484 07:17:13.879181 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
485 07:17:13.926857 Check phy result
486 07:17:13.927534 INFO : End of initialization
487 07:17:13.949139 INFO : End of 2D read delay Voltage center optimization
488 07:17:13.968261 INFO : End of 2D read delay Voltage center optimization
489 07:17:14.020336 INFO : End of 2D write delay Voltage center optimization
490 07:17:14.069435 INFO : End of 2D write delay Voltage center optimization
491 07:17:14.074944 INFO : Training has run successfully!
492 07:17:14.075509
493 07:17:14.076093 channel==0
494 07:17:14.080487 RxClkDly_Margin_A0==78 ps 8
495 07:17:14.081037 TxDqDly_Margin_A0==88 ps 9
496 07:17:14.086089 RxClkDly_Margin_A1==88 ps 9
497 07:17:14.086635 TxDqDly_Margin_A1==98 ps 10
498 07:17:14.087155 TrainedVREFDQ_A0==74
499 07:17:14.091698 TrainedVREFDQ_A1==74
500 07:17:14.092284 VrefDac_Margin_A0==24
501 07:17:14.092803 DeviceVref_Margin_A0==40
502 07:17:14.097304 VrefDac_Margin_A1==23
503 07:17:14.097856 DeviceVref_Margin_A1==40
504 07:17:14.098386
505 07:17:14.098901
506 07:17:14.099413 channel==1
507 07:17:14.102923 RxClkDly_Margin_A0==88 ps 9
508 07:17:14.103487 TxDqDly_Margin_A0==88 ps 9
509 07:17:14.108504 RxClkDly_Margin_A1==88 ps 9
510 07:17:14.109075 TxDqDly_Margin_A1==98 ps 10
511 07:17:14.114104 TrainedVREFDQ_A0==75
512 07:17:14.114673 TrainedVREFDQ_A1==78
513 07:17:14.115209 VrefDac_Margin_A0==23
514 07:17:14.119720 DeviceVref_Margin_A0==39
515 07:17:14.120371 VrefDac_Margin_A1==21
516 07:17:14.125310 DeviceVref_Margin_A1==36
517 07:17:14.125864
518 07:17:14.126388 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
519 07:17:14.126898
520 07:17:14.158948 soc_vref_reg_value 0x 0000001a 00000019 00000018 00000017 00000018 00000015 00000018 00000016 00000017 00000017 00000017 00000018 00000018 00000018 00000018 00000019 00000018 00000017 00000018 00000015 00000017 00000014 00000015 00000017 00000018 00000019 00000018 00000018 0000001c 00000017 00000016 00000016 dram_vref_reg_value 0x 00000061
521 07:17:14.159576 2D training succeed
522 07:17:14.164503 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
523 07:17:14.170019 auto size-- 65535DDR cs0 size: 2048MB
524 07:17:14.170616 DDR cs1 size: 2048MB
525 07:17:14.176980 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
526 07:17:14.177635 cs0 DataBus test pass
527 07:17:14.181380 cs1 DataBus test pass
528 07:17:14.181942 cs0 AddrBus test pass
529 07:17:14.182471 cs1 AddrBus test pass
530 07:17:14.182988
531 07:17:14.186984 100bdlr_step_size ps== 478
532 07:17:14.187547 result report
533 07:17:14.192526 boot times 0Enable ddr reg access
534 07:17:14.197667 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
535 07:17:14.211545 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
536 07:17:14.866918 bl2z: ptr: 05129330, size: 00001e40
537 07:17:14.876366 0.0;M3 CHK:0;cm4_sp_mode 0
538 07:17:14.877044 MVN_1=0x00000000
539 07:17:14.877623 MVN_2=0x00000000
540 07:17:14.887920 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
541 07:17:14.888616 OPS=0x04
542 07:17:14.889136 ring efuse init
543 07:17:14.890726 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
544 07:17:14.896521 [0.017310 Inits done]
545 07:17:14.897087 secure task start!
546 07:17:14.897614 high task start!
547 07:17:14.898137 low task start!
548 07:17:14.900775 run into bl31
549 07:17:14.909481 NOTICE: BL31: v1.3(release):4fc40b1
550 07:17:14.917348 NOTICE: BL31: Built : 15:57:33, May 22 2019
551 07:17:14.917913 NOTICE: BL31: G12A normal boot!
552 07:17:14.932732 NOTICE: BL31: BL33 decompress pass
553 07:17:14.937460 ERROR: Error initializing runtime service opteed_fast
554 07:17:16.325574 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
555 07:17:16.326087 bl2_stage_init 0x01
556 07:17:16.326382 bl2_stage_init 0x81
557 07:17:16.330750 hw id: 0x0000 - pwm id 0x01
558 07:17:16.331085 bl2_stage_init 0xc1
559 07:17:16.335817 bl2_stage_init 0x02
560 07:17:16.336210
561 07:17:16.336475 L0:00000000
562 07:17:16.336729 L1:00000703
563 07:17:16.336980 L2:00008067
564 07:17:16.341511 L3:15000000
565 07:17:16.341890 S1:00000000
566 07:17:16.342181 B2:20282000
567 07:17:16.342445 B1:a0f83180
568 07:17:16.342728
569 07:17:16.343008 TE: 70628
570 07:17:16.343271
571 07:17:16.352527 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
572 07:17:16.352856
573 07:17:16.353281 Board ID = 1
574 07:17:16.353701 Set cpu clk to 24M
575 07:17:16.354109 Set clk81 to 24M
576 07:17:16.356067 Use GP1_pll as DSU clk.
577 07:17:16.356516 DSU clk: 1200 Mhz
578 07:17:16.361627 CPU clk: 1200 MHz
579 07:17:16.362102 Set clk81 to 166.6M
580 07:17:16.367248 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
581 07:17:16.367703 board id: 1
582 07:17:16.377140 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
583 07:17:16.388138 fw parse done
584 07:17:16.394135 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
585 07:17:16.437337 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
586 07:17:16.448388 PIEI prepare done
587 07:17:16.448835 fastboot data load
588 07:17:16.449256 fastboot data verify
589 07:17:16.454000 verify result: 266
590 07:17:16.459650 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
591 07:17:16.460131 LPDDR4 probe
592 07:17:16.460542 ddr clk to 1584MHz
593 07:17:16.467559 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
594 07:17:16.505422
595 07:17:16.505922 dmc_version 0001
596 07:17:16.512338 Check phy result
597 07:17:16.518382 INFO : End of CA training
598 07:17:16.518842 INFO : End of initialization
599 07:17:16.523958 INFO : Training has run successfully!
600 07:17:16.524436 Check phy result
601 07:17:16.529546 INFO : End of initialization
602 07:17:16.529995 INFO : End of read enable training
603 07:17:16.532765 INFO : End of fine write leveling
604 07:17:16.538368 INFO : End of Write leveling coarse delay
605 07:17:16.544020 INFO : Training has run successfully!
606 07:17:16.544476 Check phy result
607 07:17:16.544882 INFO : End of initialization
608 07:17:16.549554 INFO : End of read dq deskew training
609 07:17:16.552965 INFO : End of MPR read delay center optimization
610 07:17:16.558503 INFO : End of write delay center optimization
611 07:17:16.564152 INFO : End of read delay center optimization
612 07:17:16.564603 INFO : End of max read latency training
613 07:17:16.569713 INFO : Training has run successfully!
614 07:17:16.570151 1D training succeed
615 07:17:16.577882 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
616 07:17:16.626288 Check phy result
617 07:17:16.626858 INFO : End of initialization
618 07:17:16.653362 INFO : End of 2D read delay Voltage center optimization
619 07:17:16.677853 INFO : End of 2D read delay Voltage center optimization
620 07:17:16.733842 INFO : End of 2D write delay Voltage center optimization
621 07:17:16.788654 INFO : End of 2D write delay Voltage center optimization
622 07:17:16.794346 INFO : Training has run successfully!
623 07:17:16.794895
624 07:17:16.795372 channel==0
625 07:17:16.799779 RxClkDly_Margin_A0==88 ps 9
626 07:17:16.800397 TxDqDly_Margin_A0==98 ps 10
627 07:17:16.803085 RxClkDly_Margin_A1==88 ps 9
628 07:17:16.803632 TxDqDly_Margin_A1==98 ps 10
629 07:17:16.808600 TrainedVREFDQ_A0==74
630 07:17:16.809135 TrainedVREFDQ_A1==74
631 07:17:16.814358 VrefDac_Margin_A0==24
632 07:17:16.814888 DeviceVref_Margin_A0==40
633 07:17:16.815352 VrefDac_Margin_A1==22
634 07:17:16.819868 DeviceVref_Margin_A1==40
635 07:17:16.820437
636 07:17:16.820900
637 07:17:16.821352 channel==1
638 07:17:16.821794 RxClkDly_Margin_A0==88 ps 9
639 07:17:16.823344 TxDqDly_Margin_A0==78 ps 8
640 07:17:16.828971 RxClkDly_Margin_A1==78 ps 8
641 07:17:16.829507 TxDqDly_Margin_A1==88 ps 9
642 07:17:16.829977 TrainedVREFDQ_A0==75
643 07:17:16.834527 TrainedVREFDQ_A1==78
644 07:17:16.835066 VrefDac_Margin_A0==23
645 07:17:16.840032 DeviceVref_Margin_A0==38
646 07:17:16.840567 VrefDac_Margin_A1==23
647 07:17:16.841024 DeviceVref_Margin_A1==36
648 07:17:16.841470
649 07:17:16.845660 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
650 07:17:16.846202
651 07:17:16.879128 soc_vref_reg_value 0x 00000019 00000019 00000019 00000017 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000018 00000017 00000019 00000019 00000018 00000019 00000016 00000018 00000015 00000015 00000017 00000018 00000019 00000018 00000018 0000001c 00000018 00000016 00000016 dram_vref_reg_value 0x 00000061
652 07:17:16.879739 2D training succeed
653 07:17:16.884771 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
654 07:17:16.890257 auto size-- 65535DDR cs0 size: 2048MB
655 07:17:16.890783 DDR cs1 size: 2048MB
656 07:17:16.895888 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
657 07:17:16.896463 cs0 DataBus test pass
658 07:17:16.896930 cs1 DataBus test pass
659 07:17:16.901486 cs0 AddrBus test pass
660 07:17:16.902025 cs1 AddrBus test pass
661 07:17:16.902485
662 07:17:16.907076 100bdlr_step_size ps== 471
663 07:17:16.907609 result report
664 07:17:16.908118 boot times 0Enable ddr reg access
665 07:17:16.915740 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
666 07:17:16.930621 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
667 07:17:17.589922 bl2z: ptr: 05129330, size: 00001e40
668 07:17:17.598581 0.0;M3 CHK:0;cm4_sp_mode 0
669 07:17:17.599120 MVN_1=0x00000000
670 07:17:17.599579 MVN_2=0x00000000
671 07:17:17.610139 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
672 07:17:17.610659 OPS=0x04
673 07:17:17.611121 ring efuse init
674 07:17:17.613034 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
675 07:17:17.618810 [0.017355 Inits done]
676 07:17:17.619303 secure task start!
677 07:17:17.619754 high task start!
678 07:17:17.620238 low task start!
679 07:17:17.623125 run into bl31
680 07:17:17.631740 NOTICE: BL31: v1.3(release):4fc40b1
681 07:17:17.639546 NOTICE: BL31: Built : 15:57:33, May 22 2019
682 07:17:17.640091 NOTICE: BL31: G12A normal boot!
683 07:17:17.655069 NOTICE: BL31: BL33 decompress pass
684 07:17:17.660777 ERROR: Error initializing runtime service opteed_fast
685 07:17:18.456257
686 07:17:18.456872
687 07:17:18.461541 U-Boot 2024.01-rc4+ (Dec 14 2023 - 02:26:00 -0500) Libre Computer AML-S905D3-CC
688 07:17:18.461988
689 07:17:18.465030 Model: Libre Computer AML-S905D3-CC Solitude
690 07:17:18.612071 SoC: Amlogic Meson SM1 (S905D3) Revision 2b:c (4:2)
691 07:17:18.627723 DRAM: 2 GiB (effective 3.8 GiB)
692 07:17:18.728706 Core: 406 devices, 33 uclasses, devicetree: separate
693 07:17:18.734505 WDT: Not starting watchdog@f0d0
694 07:17:18.759496 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
695 07:17:18.771732 Loading Environment from FAT... Card did not respond to voltage select! : -110
696 07:17:18.776743 ** Bad device specification mmc 0 **
697 07:17:18.786792 Card did not respond to voltage select! : -110
698 07:17:18.794483 ** Bad device specification mmc 0 **
699 07:17:18.794980 Couldn't find partition mmc 0
700 07:17:18.802794 Card did not respond to voltage select! : -110
701 07:17:18.808309 ** Bad device specification mmc 0 **
702 07:17:18.808809 Couldn't find partition mmc 0
703 07:17:18.813356 Error: could not access storage.
704 07:17:19.109641 Net: eth0: ethernet@ff3f0000
705 07:17:19.110065 starting USB...
706 07:17:19.354323 Bus usb@ff500000: Register 3000140 NbrPorts 3
707 07:17:19.354933 Starting the controller
708 07:17:19.361356 USB XHCI 1.10
709 07:17:20.915361 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
710 07:17:20.923794 scanning usb for storage devices... 0 Storage Device(s) found
712 07:17:20.975473 Hit any key to stop autoboot: 1
713 07:17:20.976564 end: 2.4.2 bootloader-interrupt (duration 00:00:21) [common]
714 07:17:20.977197 start: 2.4.3 bootloader-commands (timeout 00:04:38) [common]
715 07:17:20.977664 Setting prompt string to ['=>']
716 07:17:20.978134 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:38)
717 07:17:20.989803 0
718 07:17:20.990725 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
720 07:17:21.091890 => setenv autoload no
721 07:17:21.092624 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:38)
722 07:17:21.097784 setenv autoload no
724 07:17:21.199286 => setenv initrd_high 0xffffffff
725 07:17:21.200265 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:38)
726 07:17:21.204549 setenv initrd_high 0xffffffff
728 07:17:21.306020 => setenv fdt_high 0xffffffff
729 07:17:21.306900 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:38)
730 07:17:21.311175 setenv fdt_high 0xffffffff
732 07:17:21.412781 => dhcp
733 07:17:21.413787 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:38)
734 07:17:21.417760 dhcp
735 07:17:22.272563 ethernet@ff3f0000 Waiting for PHY auto negotiation to complete.. done
736 07:17:22.273161 Speed: 1000, full duplex
737 07:17:22.273635 BOOTP broadcast 1
738 07:17:22.281114 DHCP client bound to address 192.168.6.21 (8 ms)
740 07:17:22.382702 => setenv serverip 192.168.6.2
741 07:17:22.383447 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:37)
742 07:17:22.387918 setenv serverip 192.168.6.2
744 07:17:22.489395 => tftpboot 0x01080000 978302/tftp-deploy-5tqgi530/kernel/uImage
745 07:17:22.490093 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:37)
746 07:17:22.496660 tftpboot 0x01080000 978302/tftp-deploy-5tqgi530/kernel/uImage
747 07:17:22.497155 Speed: 1000, full duplex
748 07:17:22.497560 Using ethernet@ff3f0000 device
749 07:17:22.502150 TFTP from server 192.168.6.2; our IP address is 192.168.6.21
750 07:17:22.507682 Filename '978302/tftp-deploy-5tqgi530/kernel/uImage'.
751 07:17:22.511093 Load address: 0x1080000
752 07:17:24.937266 Loading: *################################################## 38 MiB
753 07:17:24.937857 15.6 MiB/s
754 07:17:24.938269 done
755 07:17:24.941612 Bytes transferred = 39834176 (25fd240 hex)
757 07:17:25.043071 => tftpboot 0x08000000 978302/tftp-deploy-5tqgi530/ramdisk/ramdisk.cpio.gz.uboot
758 07:17:25.043749 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:34)
759 07:17:25.050420 tftpboot 0x08000000 978302/tftp-deploy-5tqgi530/ramdisk/ramdisk.cpio.gz.uboot
760 07:17:25.050906 Speed: 1000, full duplex
761 07:17:25.051308 Using ethernet@ff3f0000 device
762 07:17:25.055905 TFTP from server 192.168.6.2; our IP address is 192.168.6.21
763 07:17:25.065652 Filename '978302/tftp-deploy-5tqgi530/ramdisk/ramdisk.cpio.gz.uboot'.
764 07:17:25.066138 Load address: 0x8000000
765 07:17:26.153778 Loading: *################################# UDP wrong checksum 000000ff 0000b87c
766 07:17:26.194081 # UDP wrong checksum 000000ff 0000446f
767 07:17:26.701821 ############### UDP wrong checksum 00000005 000042bf
768 07:17:31.701702 T UDP wrong checksum 00000005 000042bf
769 07:17:41.704056 T T UDP wrong checksum 00000005 000042bf
770 07:18:01.709054 T T T T UDP wrong checksum 00000005 000042bf
771 07:18:10.269372 T UDP wrong checksum 000000ff 0000fe84
772 07:18:10.281537 UDP wrong checksum 000000ff 00008777
773 07:18:21.713644 T T
774 07:18:21.714078 Retry count exceeded; starting again
776 07:18:21.714936 end: 2.4.3 bootloader-commands (duration 00:01:01) [common]
779 07:18:21.715843 end: 2.4 uboot-commands (duration 00:01:22) [common]
781 07:18:21.717362 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
783 07:18:21.718497 end: 2 uboot-action (duration 00:01:22) [common]
785 07:18:21.720147 Cleaning after the job
786 07:18:21.720710 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/978302/tftp-deploy-5tqgi530/ramdisk
787 07:18:21.721810 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/978302/tftp-deploy-5tqgi530/kernel
788 07:18:21.761862 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/978302/tftp-deploy-5tqgi530/dtb
789 07:18:21.763115 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/978302/tftp-deploy-5tqgi530/modules
790 07:18:21.783390 start: 4.1 power-off (timeout 00:00:30) [common]
791 07:18:21.784089 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=solitude-01'
792 07:18:21.817307 >> OK - accepted request
793 07:18:21.819310 Returned 0 in 0 seconds
794 07:18:21.920124 end: 4.1 power-off (duration 00:00:00) [common]
796 07:18:21.921164 start: 4.2 read-feedback (timeout 00:10:00) [common]
797 07:18:21.921860 Listened to connection for namespace 'common' for up to 1s
798 07:18:22.922140 Finalising connection for namespace 'common'
799 07:18:22.922861 Disconnecting from shell: Finalise
800 07:18:22.923397 =>
801 07:18:23.024473 end: 4.2 read-feedback (duration 00:00:01) [common]
802 07:18:23.025132 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/978302
803 07:18:23.314034 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/978302
804 07:18:23.314650 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.