Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 07:24:14.066174 lava-dispatcher, installed at version: 2024.01
2 07:24:14.067017 start: 0 validate
3 07:24:14.067473 Start time: 2024-11-12 07:24:14.067444+00:00 (UTC)
4 07:24:14.068029 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 07:24:14.068605 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 07:24:14.105876 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 07:24:14.106430 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241112%2Farm64%2Fdefconfig%2BCONFIG_RANDOMIZE_BASE%3Dy%2Fgcc-12%2Fkernel%2FImage exists
8 07:24:14.136783 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 07:24:14.137395 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241112%2Farm64%2Fdefconfig%2BCONFIG_RANDOMIZE_BASE%3Dy%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 07:24:14.167183 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 07:24:14.167674 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 07:24:14.199035 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 07:24:14.199512 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241112%2Farm64%2Fdefconfig%2BCONFIG_RANDOMIZE_BASE%3Dy%2Fgcc-12%2Fmodules.tar.xz exists
14 07:24:14.236088 validate duration: 0.17
16 07:24:14.236934 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 07:24:14.237247 start: 1.1 download-retry (timeout 00:10:00) [common]
18 07:24:14.237555 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 07:24:14.238308 Not decompressing ramdisk as can be used compressed.
20 07:24:14.239122 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm/20240313.0/arm64/initrd.cpio.gz
21 07:24:14.239658 saving as /var/lib/lava/dispatcher/tmp/978361/tftp-deploy-ho5liheu/ramdisk/initrd.cpio.gz
22 07:24:14.240221 total size: 5628182 (5 MB)
23 07:24:14.279864 progress 0 % (0 MB)
24 07:24:14.287388 progress 5 % (0 MB)
25 07:24:14.295210 progress 10 % (0 MB)
26 07:24:14.302192 progress 15 % (0 MB)
27 07:24:14.309102 progress 20 % (1 MB)
28 07:24:14.312709 progress 25 % (1 MB)
29 07:24:14.316661 progress 30 % (1 MB)
30 07:24:14.320684 progress 35 % (1 MB)
31 07:24:14.324350 progress 40 % (2 MB)
32 07:24:14.328316 progress 45 % (2 MB)
33 07:24:14.331865 progress 50 % (2 MB)
34 07:24:14.335864 progress 55 % (2 MB)
35 07:24:14.340167 progress 60 % (3 MB)
36 07:24:14.344123 progress 65 % (3 MB)
37 07:24:14.348184 progress 70 % (3 MB)
38 07:24:14.351816 progress 75 % (4 MB)
39 07:24:14.355813 progress 80 % (4 MB)
40 07:24:14.359388 progress 85 % (4 MB)
41 07:24:14.363326 progress 90 % (4 MB)
42 07:24:14.367066 progress 95 % (5 MB)
43 07:24:14.370307 progress 100 % (5 MB)
44 07:24:14.370965 5 MB downloaded in 0.13 s (41.05 MB/s)
45 07:24:14.371527 end: 1.1.1 http-download (duration 00:00:00) [common]
47 07:24:14.372458 end: 1.1 download-retry (duration 00:00:00) [common]
48 07:24:14.372758 start: 1.2 download-retry (timeout 00:10:00) [common]
49 07:24:14.373030 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 07:24:14.373635 downloading http://storage.kernelci.org/next/master/next-20241112/arm64/defconfig+CONFIG_RANDOMIZE_BASE=y/gcc-12/kernel/Image
51 07:24:14.373937 saving as /var/lib/lava/dispatcher/tmp/978361/tftp-deploy-ho5liheu/kernel/Image
52 07:24:14.374163 total size: 46121472 (43 MB)
53 07:24:14.374384 No compression specified
54 07:24:14.412039 progress 0 % (0 MB)
55 07:24:14.441152 progress 5 % (2 MB)
56 07:24:14.470097 progress 10 % (4 MB)
57 07:24:14.499587 progress 15 % (6 MB)
58 07:24:14.528510 progress 20 % (8 MB)
59 07:24:14.557770 progress 25 % (11 MB)
60 07:24:14.587070 progress 30 % (13 MB)
61 07:24:14.616187 progress 35 % (15 MB)
62 07:24:14.645657 progress 40 % (17 MB)
63 07:24:14.674675 progress 45 % (19 MB)
64 07:24:14.703823 progress 50 % (22 MB)
65 07:24:14.733277 progress 55 % (24 MB)
66 07:24:14.762659 progress 60 % (26 MB)
67 07:24:14.791696 progress 65 % (28 MB)
68 07:24:14.821027 progress 70 % (30 MB)
69 07:24:14.850164 progress 75 % (33 MB)
70 07:24:14.879834 progress 80 % (35 MB)
71 07:24:14.909036 progress 85 % (37 MB)
72 07:24:14.938170 progress 90 % (39 MB)
73 07:24:14.967705 progress 95 % (41 MB)
74 07:24:14.996425 progress 100 % (43 MB)
75 07:24:14.997063 43 MB downloaded in 0.62 s (70.61 MB/s)
76 07:24:14.997539 end: 1.2.1 http-download (duration 00:00:01) [common]
78 07:24:14.998354 end: 1.2 download-retry (duration 00:00:01) [common]
79 07:24:14.998628 start: 1.3 download-retry (timeout 00:09:59) [common]
80 07:24:14.998894 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 07:24:14.999487 downloading http://storage.kernelci.org/next/master/next-20241112/arm64/defconfig+CONFIG_RANDOMIZE_BASE=y/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
82 07:24:14.999795 saving as /var/lib/lava/dispatcher/tmp/978361/tftp-deploy-ho5liheu/dtb/meson-g12b-a311d-libretech-cc.dtb
83 07:24:15.000040 total size: 54703 (0 MB)
84 07:24:15.000266 No compression specified
85 07:24:15.038288 progress 59 % (0 MB)
86 07:24:15.039491 progress 100 % (0 MB)
87 07:24:15.040082 0 MB downloaded in 0.04 s (1.30 MB/s)
88 07:24:15.040560 end: 1.3.1 http-download (duration 00:00:00) [common]
90 07:24:15.041374 end: 1.3 download-retry (duration 00:00:00) [common]
91 07:24:15.041642 start: 1.4 download-retry (timeout 00:09:59) [common]
92 07:24:15.041909 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 07:24:15.042379 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm/20240313.0/arm64/full.rootfs.tar.xz
94 07:24:15.042630 saving as /var/lib/lava/dispatcher/tmp/978361/tftp-deploy-ho5liheu/nfsrootfs/full.rootfs.tar
95 07:24:15.042837 total size: 107552908 (102 MB)
96 07:24:15.043048 Using unxz to decompress xz
97 07:24:15.076967 progress 0 % (0 MB)
98 07:24:15.715612 progress 5 % (5 MB)
99 07:24:16.439086 progress 10 % (10 MB)
100 07:24:17.153957 progress 15 % (15 MB)
101 07:24:17.910074 progress 20 % (20 MB)
102 07:24:18.487476 progress 25 % (25 MB)
103 07:24:19.115698 progress 30 % (30 MB)
104 07:24:19.864077 progress 35 % (35 MB)
105 07:24:20.211282 progress 40 % (41 MB)
106 07:24:20.639782 progress 45 % (46 MB)
107 07:24:21.366946 progress 50 % (51 MB)
108 07:24:22.203555 progress 55 % (56 MB)
109 07:24:23.032420 progress 60 % (61 MB)
110 07:24:23.785928 progress 65 % (66 MB)
111 07:24:24.517401 progress 70 % (71 MB)
112 07:24:25.279975 progress 75 % (76 MB)
113 07:24:25.953886 progress 80 % (82 MB)
114 07:24:26.702908 progress 85 % (87 MB)
115 07:24:27.464273 progress 90 % (92 MB)
116 07:24:28.187287 progress 95 % (97 MB)
117 07:24:28.925037 progress 100 % (102 MB)
118 07:24:28.936823 102 MB downloaded in 13.89 s (7.38 MB/s)
119 07:24:28.937759 end: 1.4.1 http-download (duration 00:00:14) [common]
121 07:24:28.939543 end: 1.4 download-retry (duration 00:00:14) [common]
122 07:24:28.940165 start: 1.5 download-retry (timeout 00:09:45) [common]
123 07:24:28.940740 start: 1.5.1 http-download (timeout 00:09:45) [common]
124 07:24:28.941720 downloading http://storage.kernelci.org/next/master/next-20241112/arm64/defconfig+CONFIG_RANDOMIZE_BASE=y/gcc-12/modules.tar.xz
125 07:24:28.942234 saving as /var/lib/lava/dispatcher/tmp/978361/tftp-deploy-ho5liheu/modules/modules.tar
126 07:24:28.942683 total size: 11681648 (11 MB)
127 07:24:28.943143 Using unxz to decompress xz
128 07:24:28.988290 progress 0 % (0 MB)
129 07:24:29.054644 progress 5 % (0 MB)
130 07:24:29.128863 progress 10 % (1 MB)
131 07:24:29.224249 progress 15 % (1 MB)
132 07:24:29.320303 progress 20 % (2 MB)
133 07:24:29.399796 progress 25 % (2 MB)
134 07:24:29.471447 progress 30 % (3 MB)
135 07:24:29.549407 progress 35 % (3 MB)
136 07:24:29.627121 progress 40 % (4 MB)
137 07:24:29.703186 progress 45 % (5 MB)
138 07:24:29.786877 progress 50 % (5 MB)
139 07:24:29.868184 progress 55 % (6 MB)
140 07:24:29.949130 progress 60 % (6 MB)
141 07:24:30.029177 progress 65 % (7 MB)
142 07:24:30.109873 progress 70 % (7 MB)
143 07:24:30.197239 progress 75 % (8 MB)
144 07:24:30.280889 progress 80 % (8 MB)
145 07:24:30.362244 progress 85 % (9 MB)
146 07:24:30.441083 progress 90 % (10 MB)
147 07:24:30.518933 progress 95 % (10 MB)
148 07:24:30.595331 progress 100 % (11 MB)
149 07:24:30.607592 11 MB downloaded in 1.66 s (6.69 MB/s)
150 07:24:30.608317 end: 1.5.1 http-download (duration 00:00:02) [common]
152 07:24:30.609930 end: 1.5 download-retry (duration 00:00:02) [common]
153 07:24:30.610453 start: 1.6 prepare-tftp-overlay (timeout 00:09:44) [common]
154 07:24:30.610971 start: 1.6.1 extract-nfsrootfs (timeout 00:09:44) [common]
155 07:24:40.246800 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/978361/extract-nfsrootfs-d63fdvs3
156 07:24:40.247406 end: 1.6.1 extract-nfsrootfs (duration 00:00:10) [common]
157 07:24:40.247695 start: 1.6.2 lava-overlay (timeout 00:09:34) [common]
158 07:24:40.248454 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/978361/lava-overlay-buz99b7_
159 07:24:40.248916 makedir: /var/lib/lava/dispatcher/tmp/978361/lava-overlay-buz99b7_/lava-978361/bin
160 07:24:40.249246 makedir: /var/lib/lava/dispatcher/tmp/978361/lava-overlay-buz99b7_/lava-978361/tests
161 07:24:40.249564 makedir: /var/lib/lava/dispatcher/tmp/978361/lava-overlay-buz99b7_/lava-978361/results
162 07:24:40.249899 Creating /var/lib/lava/dispatcher/tmp/978361/lava-overlay-buz99b7_/lava-978361/bin/lava-add-keys
163 07:24:40.250423 Creating /var/lib/lava/dispatcher/tmp/978361/lava-overlay-buz99b7_/lava-978361/bin/lava-add-sources
164 07:24:40.250927 Creating /var/lib/lava/dispatcher/tmp/978361/lava-overlay-buz99b7_/lava-978361/bin/lava-background-process-start
165 07:24:40.251417 Creating /var/lib/lava/dispatcher/tmp/978361/lava-overlay-buz99b7_/lava-978361/bin/lava-background-process-stop
166 07:24:40.251954 Creating /var/lib/lava/dispatcher/tmp/978361/lava-overlay-buz99b7_/lava-978361/bin/lava-common-functions
167 07:24:40.252524 Creating /var/lib/lava/dispatcher/tmp/978361/lava-overlay-buz99b7_/lava-978361/bin/lava-echo-ipv4
168 07:24:40.253017 Creating /var/lib/lava/dispatcher/tmp/978361/lava-overlay-buz99b7_/lava-978361/bin/lava-install-packages
169 07:24:40.253510 Creating /var/lib/lava/dispatcher/tmp/978361/lava-overlay-buz99b7_/lava-978361/bin/lava-installed-packages
170 07:24:40.253988 Creating /var/lib/lava/dispatcher/tmp/978361/lava-overlay-buz99b7_/lava-978361/bin/lava-os-build
171 07:24:40.254460 Creating /var/lib/lava/dispatcher/tmp/978361/lava-overlay-buz99b7_/lava-978361/bin/lava-probe-channel
172 07:24:40.254933 Creating /var/lib/lava/dispatcher/tmp/978361/lava-overlay-buz99b7_/lava-978361/bin/lava-probe-ip
173 07:24:40.255403 Creating /var/lib/lava/dispatcher/tmp/978361/lava-overlay-buz99b7_/lava-978361/bin/lava-target-ip
174 07:24:40.255898 Creating /var/lib/lava/dispatcher/tmp/978361/lava-overlay-buz99b7_/lava-978361/bin/lava-target-mac
175 07:24:40.256456 Creating /var/lib/lava/dispatcher/tmp/978361/lava-overlay-buz99b7_/lava-978361/bin/lava-target-storage
176 07:24:40.256952 Creating /var/lib/lava/dispatcher/tmp/978361/lava-overlay-buz99b7_/lava-978361/bin/lava-test-case
177 07:24:40.257439 Creating /var/lib/lava/dispatcher/tmp/978361/lava-overlay-buz99b7_/lava-978361/bin/lava-test-event
178 07:24:40.257915 Creating /var/lib/lava/dispatcher/tmp/978361/lava-overlay-buz99b7_/lava-978361/bin/lava-test-feedback
179 07:24:40.258449 Creating /var/lib/lava/dispatcher/tmp/978361/lava-overlay-buz99b7_/lava-978361/bin/lava-test-raise
180 07:24:40.258931 Creating /var/lib/lava/dispatcher/tmp/978361/lava-overlay-buz99b7_/lava-978361/bin/lava-test-reference
181 07:24:40.259402 Creating /var/lib/lava/dispatcher/tmp/978361/lava-overlay-buz99b7_/lava-978361/bin/lava-test-runner
182 07:24:40.259900 Creating /var/lib/lava/dispatcher/tmp/978361/lava-overlay-buz99b7_/lava-978361/bin/lava-test-set
183 07:24:40.260439 Creating /var/lib/lava/dispatcher/tmp/978361/lava-overlay-buz99b7_/lava-978361/bin/lava-test-shell
184 07:24:40.260929 Updating /var/lib/lava/dispatcher/tmp/978361/lava-overlay-buz99b7_/lava-978361/bin/lava-install-packages (oe)
185 07:24:40.261458 Updating /var/lib/lava/dispatcher/tmp/978361/lava-overlay-buz99b7_/lava-978361/bin/lava-installed-packages (oe)
186 07:24:40.261895 Creating /var/lib/lava/dispatcher/tmp/978361/lava-overlay-buz99b7_/lava-978361/environment
187 07:24:40.262257 LAVA metadata
188 07:24:40.262516 - LAVA_JOB_ID=978361
189 07:24:40.262731 - LAVA_DISPATCHER_IP=192.168.6.2
190 07:24:40.263080 start: 1.6.2.1 ssh-authorize (timeout 00:09:34) [common]
191 07:24:40.264029 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
192 07:24:40.264340 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:34) [common]
193 07:24:40.264552 skipped lava-vland-overlay
194 07:24:40.264797 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
195 07:24:40.265052 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:34) [common]
196 07:24:40.265272 skipped lava-multinode-overlay
197 07:24:40.265515 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
198 07:24:40.265768 start: 1.6.2.4 test-definition (timeout 00:09:34) [common]
199 07:24:40.266015 Loading test definitions
200 07:24:40.266293 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:34) [common]
201 07:24:40.266513 Using /lava-978361 at stage 0
202 07:24:40.267685 uuid=978361_1.6.2.4.1 testdef=None
203 07:24:40.268013 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
204 07:24:40.268289 start: 1.6.2.4.2 test-overlay (timeout 00:09:34) [common]
205 07:24:40.270068 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
207 07:24:40.270861 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:34) [common]
208 07:24:40.273097 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
210 07:24:40.273927 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:34) [common]
211 07:24:40.276105 runner path: /var/lib/lava/dispatcher/tmp/978361/lava-overlay-buz99b7_/lava-978361/0/tests/0_dmesg test_uuid 978361_1.6.2.4.1
212 07:24:40.276660 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
214 07:24:40.277420 Creating lava-test-runner.conf files
215 07:24:40.277624 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/978361/lava-overlay-buz99b7_/lava-978361/0 for stage 0
216 07:24:40.277956 - 0_dmesg
217 07:24:40.278293 end: 1.6.2.4 test-definition (duration 00:00:00) [common]
218 07:24:40.278566 start: 1.6.2.5 compress-overlay (timeout 00:09:34) [common]
219 07:24:40.300105 end: 1.6.2.5 compress-overlay (duration 00:00:00) [common]
220 07:24:40.300458 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:09:34) [common]
221 07:24:40.300718 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
222 07:24:40.300984 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
223 07:24:40.301247 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:34) [common]
224 07:24:40.911053 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:01) [common]
225 07:24:40.911523 start: 1.6.4 extract-modules (timeout 00:09:33) [common]
226 07:24:40.911775 extracting modules file /var/lib/lava/dispatcher/tmp/978361/tftp-deploy-ho5liheu/modules/modules.tar to /var/lib/lava/dispatcher/tmp/978361/extract-nfsrootfs-d63fdvs3
227 07:24:42.289666 extracting modules file /var/lib/lava/dispatcher/tmp/978361/tftp-deploy-ho5liheu/modules/modules.tar to /var/lib/lava/dispatcher/tmp/978361/extract-overlay-ramdisk-2fjzvrmg/ramdisk
228 07:24:43.702363 end: 1.6.4 extract-modules (duration 00:00:03) [common]
229 07:24:43.702850 start: 1.6.5 apply-overlay-tftp (timeout 00:09:31) [common]
230 07:24:43.703134 [common] Applying overlay to NFS
231 07:24:43.703349 [common] Applying overlay /var/lib/lava/dispatcher/tmp/978361/compress-overlay-mybr21au/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/978361/extract-nfsrootfs-d63fdvs3
232 07:24:43.732636 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
233 07:24:43.733065 start: 1.6.6 prepare-kernel (timeout 00:09:31) [common]
234 07:24:43.733340 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:09:31) [common]
235 07:24:43.733572 Converting downloaded kernel to a uImage
236 07:24:43.733881 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/978361/tftp-deploy-ho5liheu/kernel/Image /var/lib/lava/dispatcher/tmp/978361/tftp-deploy-ho5liheu/kernel/uImage
237 07:24:44.220588 output: Image Name:
238 07:24:44.221010 output: Created: Tue Nov 12 07:24:43 2024
239 07:24:44.221219 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
240 07:24:44.221423 output: Data Size: 46121472 Bytes = 45040.50 KiB = 43.98 MiB
241 07:24:44.221622 output: Load Address: 01080000
242 07:24:44.221819 output: Entry Point: 01080000
243 07:24:44.222013 output:
244 07:24:44.222353 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
245 07:24:44.222619 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
246 07:24:44.222884 start: 1.6.7 configure-preseed-file (timeout 00:09:30) [common]
247 07:24:44.223134 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
248 07:24:44.223390 start: 1.6.8 compress-ramdisk (timeout 00:09:30) [common]
249 07:24:44.223654 Building ramdisk /var/lib/lava/dispatcher/tmp/978361/extract-overlay-ramdisk-2fjzvrmg/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/978361/extract-overlay-ramdisk-2fjzvrmg/ramdisk
250 07:24:46.345885 >> 168134 blocks
251 07:24:54.170466 Adding RAMdisk u-boot header.
252 07:24:54.170920 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/978361/extract-overlay-ramdisk-2fjzvrmg/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/978361/extract-overlay-ramdisk-2fjzvrmg/ramdisk.cpio.gz.uboot
253 07:24:54.482497 output: Image Name:
254 07:24:54.482935 output: Created: Tue Nov 12 07:24:54 2024
255 07:24:54.483150 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
256 07:24:54.483358 output: Data Size: 23565332 Bytes = 23013.02 KiB = 22.47 MiB
257 07:24:54.483560 output: Load Address: 00000000
258 07:24:54.483761 output: Entry Point: 00000000
259 07:24:54.483960 output:
260 07:24:54.485007 rename /var/lib/lava/dispatcher/tmp/978361/extract-overlay-ramdisk-2fjzvrmg/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/978361/tftp-deploy-ho5liheu/ramdisk/ramdisk.cpio.gz.uboot
261 07:24:54.485751 end: 1.6.8 compress-ramdisk (duration 00:00:10) [common]
262 07:24:54.486298 end: 1.6 prepare-tftp-overlay (duration 00:00:24) [common]
263 07:24:54.486830 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:20) [common]
264 07:24:54.487288 No LXC device requested
265 07:24:54.487798 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
266 07:24:54.488365 start: 1.8 deploy-device-env (timeout 00:09:20) [common]
267 07:24:54.488866 end: 1.8 deploy-device-env (duration 00:00:00) [common]
268 07:24:54.489280 Checking files for TFTP limit of 4294967296 bytes.
269 07:24:54.492057 end: 1 tftp-deploy (duration 00:00:40) [common]
270 07:24:54.492673 start: 2 uboot-action (timeout 00:05:00) [common]
271 07:24:54.493205 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
272 07:24:54.493703 end: 2.1 uboot-from-media (duration 00:00:00) [common]
273 07:24:54.494204 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
274 07:24:54.494733 Using kernel file from prepare-kernel: 978361/tftp-deploy-ho5liheu/kernel/uImage
275 07:24:54.495361 substitutions:
276 07:24:54.495769 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
277 07:24:54.496209 - {DTB_ADDR}: 0x01070000
278 07:24:54.496609 - {DTB}: 978361/tftp-deploy-ho5liheu/dtb/meson-g12b-a311d-libretech-cc.dtb
279 07:24:54.497007 - {INITRD}: 978361/tftp-deploy-ho5liheu/ramdisk/ramdisk.cpio.gz.uboot
280 07:24:54.497402 - {KERNEL_ADDR}: 0x01080000
281 07:24:54.497794 - {KERNEL}: 978361/tftp-deploy-ho5liheu/kernel/uImage
282 07:24:54.498184 - {LAVA_MAC}: None
283 07:24:54.498631 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/978361/extract-nfsrootfs-d63fdvs3
284 07:24:54.499028 - {NFS_SERVER_IP}: 192.168.6.2
285 07:24:54.499417 - {PRESEED_CONFIG}: None
286 07:24:54.499802 - {PRESEED_LOCAL}: None
287 07:24:54.500219 - {RAMDISK_ADDR}: 0x08000000
288 07:24:54.500608 - {RAMDISK}: 978361/tftp-deploy-ho5liheu/ramdisk/ramdisk.cpio.gz.uboot
289 07:24:54.500997 - {ROOT_PART}: None
290 07:24:54.501385 - {ROOT}: None
291 07:24:54.501769 - {SERVER_IP}: 192.168.6.2
292 07:24:54.502154 - {TEE_ADDR}: 0x83000000
293 07:24:54.502537 - {TEE}: None
294 07:24:54.502921 Parsed boot commands:
295 07:24:54.503296 - setenv autoload no
296 07:24:54.503678 - setenv initrd_high 0xffffffff
297 07:24:54.504090 - setenv fdt_high 0xffffffff
298 07:24:54.504476 - dhcp
299 07:24:54.504858 - setenv serverip 192.168.6.2
300 07:24:54.505242 - tftpboot 0x01080000 978361/tftp-deploy-ho5liheu/kernel/uImage
301 07:24:54.505626 - tftpboot 0x08000000 978361/tftp-deploy-ho5liheu/ramdisk/ramdisk.cpio.gz.uboot
302 07:24:54.506013 - tftpboot 0x01070000 978361/tftp-deploy-ho5liheu/dtb/meson-g12b-a311d-libretech-cc.dtb
303 07:24:54.506398 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/978361/extract-nfsrootfs-d63fdvs3,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
304 07:24:54.506796 - bootm 0x01080000 0x08000000 0x01070000
305 07:24:54.507302 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
307 07:24:54.508832 start: 2.3 connect-device (timeout 00:05:00) [common]
308 07:24:54.509255 [common] connect-device Connecting to device using 'telnet conserv1 3007'
309 07:24:54.524149 Setting prompt string to ['lava-test: # ']
310 07:24:54.525680 end: 2.3 connect-device (duration 00:00:00) [common]
311 07:24:54.526283 start: 2.4 uboot-commands (timeout 00:05:00) [common]
312 07:24:54.526834 start: 2.4.1 reset-device (timeout 00:05:00) [common]
313 07:24:54.527348 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
314 07:24:54.528515 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
315 07:24:54.565505 >> OK - accepted request
316 07:24:54.567261 Returned 0 in 0 seconds
317 07:24:54.668408 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
319 07:24:54.670074 end: 2.4.1 reset-device (duration 00:00:00) [common]
320 07:24:54.670656 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
321 07:24:54.671160 Setting prompt string to ['Hit any key to stop autoboot']
322 07:24:54.671616 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
323 07:24:54.673241 Trying 192.168.56.21...
324 07:24:54.673723 Connected to conserv1.
325 07:24:54.674138 Escape character is '^]'.
326 07:24:54.674557
327 07:24:54.674978 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
328 07:24:54.675400
329 07:25:06.293498 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
330 07:25:06.293992 bl2_stage_init 0x01
331 07:25:06.294225 bl2_stage_init 0x81
332 07:25:06.299015 hw id: 0x0000 - pwm id 0x01
333 07:25:06.299607 bl2_stage_init 0xc1
334 07:25:06.300068 bl2_stage_init 0x02
335 07:25:06.300475
336 07:25:06.304625 L0:00000000
337 07:25:06.305153 L1:20000703
338 07:25:06.305564 L2:00008067
339 07:25:06.305967 L3:14000000
340 07:25:06.310150 B2:00402000
341 07:25:06.310625 B1:e0f83180
342 07:25:06.311032
343 07:25:06.311426 TE: 58124
344 07:25:06.311819
345 07:25:06.315640 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
346 07:25:06.316105
347 07:25:06.316525 Board ID = 1
348 07:25:06.321316 Set A53 clk to 24M
349 07:25:06.321790 Set A73 clk to 24M
350 07:25:06.322184 Set clk81 to 24M
351 07:25:06.326905 A53 clk: 1200 MHz
352 07:25:06.327340 A73 clk: 1200 MHz
353 07:25:06.327730 CLK81: 166.6M
354 07:25:06.328152 smccc: 00012a92
355 07:25:06.332652 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
356 07:25:06.338101 board id: 1
357 07:25:06.344203 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
358 07:25:06.354581 fw parse done
359 07:25:06.360451 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
360 07:25:06.403107 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
361 07:25:06.414004 PIEI prepare done
362 07:25:06.414507 fastboot data load
363 07:25:06.414925 fastboot data verify
364 07:25:06.419849 verify result: 266
365 07:25:06.425303 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
366 07:25:06.425775 LPDDR4 probe
367 07:25:06.426193 ddr clk to 1584MHz
368 07:25:06.433317 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
369 07:25:06.470669
370 07:25:06.471174 dmc_version 0001
371 07:25:06.477282 Check phy result
372 07:25:06.483043 INFO : End of CA training
373 07:25:06.483507 INFO : End of initialization
374 07:25:06.488756 INFO : Training has run successfully!
375 07:25:06.489199 Check phy result
376 07:25:06.494239 INFO : End of initialization
377 07:25:06.494665 INFO : End of read enable training
378 07:25:06.499857 INFO : End of fine write leveling
379 07:25:06.505506 INFO : End of Write leveling coarse delay
380 07:25:06.505934 INFO : Training has run successfully!
381 07:25:06.506332 Check phy result
382 07:25:06.511052 INFO : End of initialization
383 07:25:06.511489 INFO : End of read dq deskew training
384 07:25:06.516646 INFO : End of MPR read delay center optimization
385 07:25:06.522276 INFO : End of write delay center optimization
386 07:25:06.527864 INFO : End of read delay center optimization
387 07:25:06.528323 INFO : End of max read latency training
388 07:25:06.533498 INFO : Training has run successfully!
389 07:25:06.533918 1D training succeed
390 07:25:06.541654 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
391 07:25:06.590248 Check phy result
392 07:25:06.590768 INFO : End of initialization
393 07:25:06.611854 INFO : End of 2D read delay Voltage center optimization
394 07:25:06.631963 INFO : End of 2D read delay Voltage center optimization
395 07:25:06.683837 INFO : End of 2D write delay Voltage center optimization
396 07:25:06.733115 INFO : End of 2D write delay Voltage center optimization
397 07:25:06.738688 INFO : Training has run successfully!
398 07:25:06.739128
399 07:25:06.739527 channel==0
400 07:25:06.744323 RxClkDly_Margin_A0==88 ps 9
401 07:25:06.744770 TxDqDly_Margin_A0==98 ps 10
402 07:25:06.749893 RxClkDly_Margin_A1==88 ps 9
403 07:25:06.750318 TxDqDly_Margin_A1==98 ps 10
404 07:25:06.750722 TrainedVREFDQ_A0==74
405 07:25:06.755581 TrainedVREFDQ_A1==74
406 07:25:06.756046 VrefDac_Margin_A0==25
407 07:25:06.756444 DeviceVref_Margin_A0==40
408 07:25:06.761155 VrefDac_Margin_A1==25
409 07:25:06.761611 DeviceVref_Margin_A1==40
410 07:25:06.762003
411 07:25:06.762395
412 07:25:06.766708 channel==1
413 07:25:06.767134 RxClkDly_Margin_A0==98 ps 10
414 07:25:06.767530 TxDqDly_Margin_A0==98 ps 10
415 07:25:06.772347 RxClkDly_Margin_A1==88 ps 9
416 07:25:06.772831 TxDqDly_Margin_A1==88 ps 9
417 07:25:06.777832 TrainedVREFDQ_A0==77
418 07:25:06.778265 TrainedVREFDQ_A1==77
419 07:25:06.778659 VrefDac_Margin_A0==22
420 07:25:06.783516 DeviceVref_Margin_A0==37
421 07:25:06.783944 VrefDac_Margin_A1==24
422 07:25:06.789059 DeviceVref_Margin_A1==37
423 07:25:06.789487
424 07:25:06.789886 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
425 07:25:06.790275
426 07:25:06.822675 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000018 00000017 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000017 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
427 07:25:06.823185 2D training succeed
428 07:25:06.828262 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
429 07:25:06.833892 auto size-- 65535DDR cs0 size: 2048MB
430 07:25:06.834315 DDR cs1 size: 2048MB
431 07:25:06.839524 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
432 07:25:06.839941 cs0 DataBus test pass
433 07:25:06.845099 cs1 DataBus test pass
434 07:25:06.845573 cs0 AddrBus test pass
435 07:25:06.845965 cs1 AddrBus test pass
436 07:25:06.846357
437 07:25:06.850656 100bdlr_step_size ps== 420
438 07:25:06.851093 result report
439 07:25:06.856263 boot times 0Enable ddr reg access
440 07:25:06.861655 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
441 07:25:06.875094 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
442 07:25:07.447155 0.0;M3 CHK:0;cm4_sp_mode 0
443 07:25:07.447776 MVN_1=0x00000000
444 07:25:07.452555 MVN_2=0x00000000
445 07:25:07.458302 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
446 07:25:07.458744 OPS=0x10
447 07:25:07.459149 ring efuse init
448 07:25:07.459542 chipver efuse init
449 07:25:07.466585 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
450 07:25:07.467025 [0.018961 Inits done]
451 07:25:07.467422 secure task start!
452 07:25:07.474084 high task start!
453 07:25:07.474521 low task start!
454 07:25:07.474920 run into bl31
455 07:25:07.480745 NOTICE: BL31: v1.3(release):4fc40b1
456 07:25:07.488641 NOTICE: BL31: Built : 15:58:17, May 22 2019
457 07:25:07.489088 NOTICE: BL31: G12A normal boot!
458 07:25:07.514653 NOTICE: BL31: BL33 decompress pass
459 07:25:07.520255 ERROR: Error initializing runtime service opteed_fast
460 07:25:08.753201
461 07:25:08.753807
462 07:25:08.761543 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
463 07:25:08.762025
464 07:25:08.762443 Model: Libre Computer AML-A311D-CC Alta
465 07:25:08.970026 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
466 07:25:08.993551 DRAM: 2 GiB (effective 3.8 GiB)
467 07:25:09.136841 Core: 408 devices, 31 uclasses, devicetree: separate
468 07:25:09.142203 WDT: Not starting watchdog@f0d0
469 07:25:09.174525 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
470 07:25:09.187016 Loading Environment from FAT... Card did not respond to voltage select! : -110
471 07:25:09.191953 ** Bad device specification mmc 0 **
472 07:25:09.202310 Card did not respond to voltage select! : -110
473 07:25:09.209965 ** Bad device specification mmc 0 **
474 07:25:09.210316 Couldn't find partition mmc 0
475 07:25:09.218288 Card did not respond to voltage select! : -110
476 07:25:09.223875 ** Bad device specification mmc 0 **
477 07:25:09.224257 Couldn't find partition mmc 0
478 07:25:09.228899 Error: could not access storage.
479 07:25:10.493826 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
480 07:25:10.494507 bl2_stage_init 0x01
481 07:25:10.494987 bl2_stage_init 0x81
482 07:25:10.499345 hw id: 0x0000 - pwm id 0x01
483 07:25:10.499828 bl2_stage_init 0xc1
484 07:25:10.500364 bl2_stage_init 0x02
485 07:25:10.500823
486 07:25:10.505054 L0:00000000
487 07:25:10.505540 L1:20000703
488 07:25:10.505993 L2:00008067
489 07:25:10.506436 L3:14000000
490 07:25:10.510562 B2:00402000
491 07:25:10.511062 B1:e0f83180
492 07:25:10.511513
493 07:25:10.511956 TE: 58167
494 07:25:10.512445
495 07:25:10.516178 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
496 07:25:10.516687
497 07:25:10.517139 Board ID = 1
498 07:25:10.521743 Set A53 clk to 24M
499 07:25:10.522223 Set A73 clk to 24M
500 07:25:10.522672 Set clk81 to 24M
501 07:25:10.527332 A53 clk: 1200 MHz
502 07:25:10.527807 A73 clk: 1200 MHz
503 07:25:10.528288 CLK81: 166.6M
504 07:25:10.528738 smccc: 00012abe
505 07:25:10.533031 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
506 07:25:10.538560 board id: 1
507 07:25:10.544445 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
508 07:25:10.555108 fw parse done
509 07:25:10.561131 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
510 07:25:10.603690 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
511 07:25:10.614577 PIEI prepare done
512 07:25:10.615078 fastboot data load
513 07:25:10.615534 fastboot data verify
514 07:25:10.620215 verify result: 266
515 07:25:10.625769 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
516 07:25:10.626248 LPDDR4 probe
517 07:25:10.626698 ddr clk to 1584MHz
518 07:25:10.633736 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
519 07:25:10.671076
520 07:25:10.671671 dmc_version 0001
521 07:25:10.677685 Check phy result
522 07:25:10.683551 INFO : End of CA training
523 07:25:10.684054 INFO : End of initialization
524 07:25:10.689164 INFO : Training has run successfully!
525 07:25:10.689633 Check phy result
526 07:25:10.694755 INFO : End of initialization
527 07:25:10.695241 INFO : End of read enable training
528 07:25:10.698093 INFO : End of fine write leveling
529 07:25:10.703688 INFO : End of Write leveling coarse delay
530 07:25:10.709285 INFO : Training has run successfully!
531 07:25:10.709764 Check phy result
532 07:25:10.710213 INFO : End of initialization
533 07:25:10.714942 INFO : End of read dq deskew training
534 07:25:10.720495 INFO : End of MPR read delay center optimization
535 07:25:10.720973 INFO : End of write delay center optimization
536 07:25:10.726071 INFO : End of read delay center optimization
537 07:25:10.731688 INFO : End of max read latency training
538 07:25:10.732212 INFO : Training has run successfully!
539 07:25:10.737280 1D training succeed
540 07:25:10.743191 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
541 07:25:10.790725 Check phy result
542 07:25:10.791249 INFO : End of initialization
543 07:25:10.812470 INFO : End of 2D read delay Voltage center optimization
544 07:25:10.832678 INFO : End of 2D read delay Voltage center optimization
545 07:25:10.884764 INFO : End of 2D write delay Voltage center optimization
546 07:25:10.934160 INFO : End of 2D write delay Voltage center optimization
547 07:25:10.939688 INFO : Training has run successfully!
548 07:25:10.940280
549 07:25:10.940757 channel==0
550 07:25:10.945257 RxClkDly_Margin_A0==88 ps 9
551 07:25:10.945740 TxDqDly_Margin_A0==98 ps 10
552 07:25:10.950855 RxClkDly_Margin_A1==88 ps 9
553 07:25:10.951345 TxDqDly_Margin_A1==98 ps 10
554 07:25:10.951797 TrainedVREFDQ_A0==74
555 07:25:10.956446 TrainedVREFDQ_A1==74
556 07:25:10.956926 VrefDac_Margin_A0==25
557 07:25:10.957371 DeviceVref_Margin_A0==40
558 07:25:10.962114 VrefDac_Margin_A1==25
559 07:25:10.962582 DeviceVref_Margin_A1==40
560 07:25:10.963027
561 07:25:10.963467
562 07:25:10.967658 channel==1
563 07:25:10.968170 RxClkDly_Margin_A0==98 ps 10
564 07:25:10.968622 TxDqDly_Margin_A0==98 ps 10
565 07:25:10.973267 RxClkDly_Margin_A1==88 ps 9
566 07:25:10.973762 TxDqDly_Margin_A1==98 ps 10
567 07:25:10.978862 TrainedVREFDQ_A0==77
568 07:25:10.979358 TrainedVREFDQ_A1==77
569 07:25:10.979809 VrefDac_Margin_A0==22
570 07:25:10.984457 DeviceVref_Margin_A0==37
571 07:25:10.984940 VrefDac_Margin_A1==24
572 07:25:10.990128 DeviceVref_Margin_A1==37
573 07:25:10.990605
574 07:25:10.991053 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
575 07:25:10.995657
576 07:25:11.023634 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000017 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000017 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
577 07:25:11.024215 2D training succeed
578 07:25:11.029268 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
579 07:25:11.034872 auto size-- 65535DDR cs0 size: 2048MB
580 07:25:11.035366 DDR cs1 size: 2048MB
581 07:25:11.040484 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
582 07:25:11.041017 cs0 DataBus test pass
583 07:25:11.046142 cs1 DataBus test pass
584 07:25:11.046640 cs0 AddrBus test pass
585 07:25:11.047088 cs1 AddrBus test pass
586 07:25:11.047531
587 07:25:11.051651 100bdlr_step_size ps== 420
588 07:25:11.052183 result report
589 07:25:11.057295 boot times 0Enable ddr reg access
590 07:25:11.062733 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
591 07:25:11.076223 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
592 07:25:11.650256 0.0;M3 CHK:0;cm4_sp_mode 0
593 07:25:11.650944 MVN_1=0x00000000
594 07:25:11.655612 MVN_2=0x00000000
595 07:25:11.661435 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
596 07:25:11.661962 OPS=0x10
597 07:25:11.662449 ring efuse init
598 07:25:11.662910 chipver efuse init
599 07:25:11.666949 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
600 07:25:11.672700 [0.018961 Inits done]
601 07:25:11.673244 secure task start!
602 07:25:11.673692 high task start!
603 07:25:11.677346 low task start!
604 07:25:11.677896 run into bl31
605 07:25:11.683858 NOTICE: BL31: v1.3(release):4fc40b1
606 07:25:11.691668 NOTICE: BL31: Built : 15:58:17, May 22 2019
607 07:25:11.692227 NOTICE: BL31: G12A normal boot!
608 07:25:11.717043 NOTICE: BL31: BL33 decompress pass
609 07:25:11.722703 ERROR: Error initializing runtime service opteed_fast
610 07:25:12.955722
611 07:25:12.956437
612 07:25:12.964009 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
613 07:25:12.964514
614 07:25:12.964940 Model: Libre Computer AML-A311D-CC Alta
615 07:25:13.172469 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
616 07:25:13.195910 DRAM: 2 GiB (effective 3.8 GiB)
617 07:25:13.338853 Core: 408 devices, 31 uclasses, devicetree: separate
618 07:25:13.344987 WDT: Not starting watchdog@f0d0
619 07:25:13.376950 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
620 07:25:13.389258 Loading Environment from FAT... Card did not respond to voltage select! : -110
621 07:25:13.394473 ** Bad device specification mmc 0 **
622 07:25:13.404724 Card did not respond to voltage select! : -110
623 07:25:13.412372 ** Bad device specification mmc 0 **
624 07:25:13.412885 Couldn't find partition mmc 0
625 07:25:13.420717 Card did not respond to voltage select! : -110
626 07:25:13.426152 ** Bad device specification mmc 0 **
627 07:25:13.426665 Couldn't find partition mmc 0
628 07:25:13.431365 Error: could not access storage.
629 07:25:13.773801 Net: eth0: ethernet@ff3f0000
630 07:25:13.774410 starting USB...
631 07:25:14.026289 Bus usb@ff500000: Register 3000140 NbrPorts 3
632 07:25:14.026724 Starting the controller
633 07:25:14.032446 USB XHCI 1.10
634 07:25:15.742493 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
635 07:25:15.743186 bl2_stage_init 0x01
636 07:25:15.743661 bl2_stage_init 0x81
637 07:25:15.748159 hw id: 0x0000 - pwm id 0x01
638 07:25:15.748628 bl2_stage_init 0xc1
639 07:25:15.749042 bl2_stage_init 0x02
640 07:25:15.749453
641 07:25:15.753681 L0:00000000
642 07:25:15.754176 L1:20000703
643 07:25:15.754630 L2:00008067
644 07:25:15.755076 L3:14000000
645 07:25:15.759231 B2:00402000
646 07:25:15.759718 B1:e0f83180
647 07:25:15.760211
648 07:25:15.760664 TE: 58167
649 07:25:15.761113
650 07:25:15.765012 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
651 07:25:15.765509
652 07:25:15.765963 Board ID = 1
653 07:25:15.770304 Set A53 clk to 24M
654 07:25:15.771345 Set A73 clk to 24M
655 07:25:15.771852 Set clk81 to 24M
656 07:25:15.772366 A53 clk: 1200 MHz
657 07:25:15.776888 A73 clk: 1200 MHz
658 07:25:15.777389 CLK81: 166.6M
659 07:25:15.777848 smccc: 00012abe
660 07:25:15.782575 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
661 07:25:15.788165 board id: 1
662 07:25:15.791203 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
663 07:25:15.803785 fw parse done
664 07:25:15.809722 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
665 07:25:15.852288 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
666 07:25:15.863352 PIEI prepare done
667 07:25:15.863869 fastboot data load
668 07:25:15.864393 fastboot data verify
669 07:25:15.868905 verify result: 266
670 07:25:15.874502 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
671 07:25:15.875008 LPDDR4 probe
672 07:25:15.875466 ddr clk to 1584MHz
673 07:25:15.882447 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
674 07:25:15.919846
675 07:25:15.920475 dmc_version 0001
676 07:25:15.926488 Check phy result
677 07:25:15.932387 INFO : End of CA training
678 07:25:15.932898 INFO : End of initialization
679 07:25:15.937957 INFO : Training has run successfully!
680 07:25:15.938535 Check phy result
681 07:25:15.943544 INFO : End of initialization
682 07:25:15.944089 INFO : End of read enable training
683 07:25:15.949122 INFO : End of fine write leveling
684 07:25:15.954744 INFO : End of Write leveling coarse delay
685 07:25:15.955245 INFO : Training has run successfully!
686 07:25:15.955698 Check phy result
687 07:25:15.960383 INFO : End of initialization
688 07:25:15.960890 INFO : End of read dq deskew training
689 07:25:15.965979 INFO : End of MPR read delay center optimization
690 07:25:15.971540 INFO : End of write delay center optimization
691 07:25:15.977182 INFO : End of read delay center optimization
692 07:25:15.977683 INFO : End of max read latency training
693 07:25:15.982797 INFO : Training has run successfully!
694 07:25:15.983303 1D training succeed
695 07:25:15.992042 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
696 07:25:16.039492 Check phy result
697 07:25:16.040090 INFO : End of initialization
698 07:25:16.062063 INFO : End of 2D read delay Voltage center optimization
699 07:25:16.082259 INFO : End of 2D read delay Voltage center optimization
700 07:25:16.134336 INFO : End of 2D write delay Voltage center optimization
701 07:25:16.183668 INFO : End of 2D write delay Voltage center optimization
702 07:25:16.189203 INFO : Training has run successfully!
703 07:25:16.189718
704 07:25:16.190192 channel==0
705 07:25:16.194916 RxClkDly_Margin_A0==88 ps 9
706 07:25:16.195443 TxDqDly_Margin_A0==98 ps 10
707 07:25:16.200435 RxClkDly_Margin_A1==88 ps 9
708 07:25:16.200945 TxDqDly_Margin_A1==98 ps 10
709 07:25:16.201405 TrainedVREFDQ_A0==74
710 07:25:16.206022 TrainedVREFDQ_A1==74
711 07:25:16.206529 VrefDac_Margin_A0==25
712 07:25:16.206984 DeviceVref_Margin_A0==40
713 07:25:16.211629 VrefDac_Margin_A1==26
714 07:25:16.212165 DeviceVref_Margin_A1==40
715 07:25:16.212620
716 07:25:16.213066
717 07:25:16.217229 channel==1
718 07:25:16.217733 RxClkDly_Margin_A0==98 ps 10
719 07:25:16.218185 TxDqDly_Margin_A0==88 ps 9
720 07:25:16.222913 RxClkDly_Margin_A1==98 ps 10
721 07:25:16.223419 TxDqDly_Margin_A1==98 ps 10
722 07:25:16.228425 TrainedVREFDQ_A0==77
723 07:25:16.228938 TrainedVREFDQ_A1==77
724 07:25:16.229392 VrefDac_Margin_A0==22
725 07:25:16.234042 DeviceVref_Margin_A0==37
726 07:25:16.234539 VrefDac_Margin_A1==22
727 07:25:16.239602 DeviceVref_Margin_A1==37
728 07:25:16.240129
729 07:25:16.240587 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
730 07:25:16.245194
731 07:25:16.273167 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000017 00000018 00000015 00000018 00000019 00000017 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
732 07:25:16.273746 2D training succeed
733 07:25:16.278938 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
734 07:25:16.284418 auto size-- 65535DDR cs0 size: 2048MB
735 07:25:16.284918 DDR cs1 size: 2048MB
736 07:25:16.290023 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
737 07:25:16.290523 cs0 DataBus test pass
738 07:25:16.295615 cs1 DataBus test pass
739 07:25:16.296159 cs0 AddrBus test pass
740 07:25:16.296616 cs1 AddrBus test pass
741 07:25:16.297062
742 07:25:16.301218 100bdlr_step_size ps== 426
743 07:25:16.301746 result report
744 07:25:16.306941 boot times 0Enable ddr reg access
745 07:25:16.312328 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
746 07:25:16.325786 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
747 07:25:16.899406 0.0;M3 CHK:0;cm4_sp_mode 0
748 07:25:16.900106 MVN_1=0x00000000
749 07:25:16.904862 MVN_2=0x00000000
750 07:25:16.910577 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
751 07:25:16.911122 OPS=0x10
752 07:25:16.911566 ring efuse init
753 07:25:16.912034 chipver efuse init
754 07:25:16.916151 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
755 07:25:16.921818 [0.018961 Inits done]
756 07:25:16.922286 secure task start!
757 07:25:16.922723 high task start!
758 07:25:16.926344 low task start!
759 07:25:16.926808 run into bl31
760 07:25:16.932966 NOTICE: BL31: v1.3(release):4fc40b1
761 07:25:16.940906 NOTICE: BL31: Built : 15:58:17, May 22 2019
762 07:25:16.941384 NOTICE: BL31: G12A normal boot!
763 07:25:16.966152 NOTICE: BL31: BL33 decompress pass
764 07:25:16.971897 ERROR: Error initializing runtime service opteed_fast
765 07:25:18.204844
766 07:25:18.205485
767 07:25:18.213279 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
768 07:25:18.213872
769 07:25:18.214344 Model: Libre Computer AML-A311D-CC Alta
770 07:25:18.421645 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
771 07:25:18.445088 DRAM: 2 GiB (effective 3.8 GiB)
772 07:25:18.588081 Core: 408 devices, 31 uclasses, devicetree: separate
773 07:25:18.594089 WDT: Not starting watchdog@f0d0
774 07:25:18.626246 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
775 07:25:18.638663 Loading Environment from FAT... Card did not respond to voltage select! : -110
776 07:25:18.643602 ** Bad device specification mmc 0 **
777 07:25:18.653977 Card did not respond to voltage select! : -110
778 07:25:18.661565 ** Bad device specification mmc 0 **
779 07:25:18.662102 Couldn't find partition mmc 0
780 07:25:18.669960 Card did not respond to voltage select! : -110
781 07:25:18.675495 ** Bad device specification mmc 0 **
782 07:25:18.676078 Couldn't find partition mmc 0
783 07:25:18.680506 Error: could not access storage.
784 07:25:19.022954 Net: eth0: ethernet@ff3f0000
785 07:25:19.023369 starting USB...
786 07:25:19.274887 Bus usb@ff500000: Register 3000140 NbrPorts 3
787 07:25:19.275325 Starting the controller
788 07:25:19.281733 USB XHCI 1.10
789 07:25:21.442744 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
790 07:25:21.443356 bl2_stage_init 0x01
791 07:25:21.443621 bl2_stage_init 0x81
792 07:25:21.448198 hw id: 0x0000 - pwm id 0x01
793 07:25:21.448728 bl2_stage_init 0xc1
794 07:25:21.449078 bl2_stage_init 0x02
795 07:25:21.449328
796 07:25:21.453753 L0:00000000
797 07:25:21.454090 L1:20000703
798 07:25:21.454311 L2:00008067
799 07:25:21.454522 L3:14000000
800 07:25:21.459300 B2:00402000
801 07:25:21.459861 B1:e0f83180
802 07:25:21.460281
803 07:25:21.460631 TE: 58167
804 07:25:21.460963
805 07:25:21.465021 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
806 07:25:21.465492
807 07:25:21.465767 Board ID = 1
808 07:25:21.470474 Set A53 clk to 24M
809 07:25:21.470807 Set A73 clk to 24M
810 07:25:21.471029 Set clk81 to 24M
811 07:25:21.476072 A53 clk: 1200 MHz
812 07:25:21.476621 A73 clk: 1200 MHz
813 07:25:21.476984 CLK81: 166.6M
814 07:25:21.477334 smccc: 00012abd
815 07:25:21.481570 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
816 07:25:21.487238 board id: 1
817 07:25:21.493155 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
818 07:25:21.503838 fw parse done
819 07:25:21.509710 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
820 07:25:21.552402 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
821 07:25:21.563258 PIEI prepare done
822 07:25:21.563683 fastboot data load
823 07:25:21.563927 fastboot data verify
824 07:25:21.568910 verify result: 266
825 07:25:21.574570 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
826 07:25:21.574971 LPDDR4 probe
827 07:25:21.575233 ddr clk to 1584MHz
828 07:25:21.582550 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
829 07:25:21.619811
830 07:25:21.620427 dmc_version 0001
831 07:25:21.626573 Check phy result
832 07:25:21.632328 INFO : End of CA training
833 07:25:21.632845 INFO : End of initialization
834 07:25:21.637925 INFO : Training has run successfully!
835 07:25:21.638309 Check phy result
836 07:25:21.643583 INFO : End of initialization
837 07:25:21.644137 INFO : End of read enable training
838 07:25:21.646793 INFO : End of fine write leveling
839 07:25:21.652352 INFO : End of Write leveling coarse delay
840 07:25:21.658062 INFO : Training has run successfully!
841 07:25:21.658669 Check phy result
842 07:25:21.659146 INFO : End of initialization
843 07:25:21.663690 INFO : End of read dq deskew training
844 07:25:21.669242 INFO : End of MPR read delay center optimization
845 07:25:21.669808 INFO : End of write delay center optimization
846 07:25:21.674819 INFO : End of read delay center optimization
847 07:25:21.680418 INFO : End of max read latency training
848 07:25:21.680998 INFO : Training has run successfully!
849 07:25:21.686018 1D training succeed
850 07:25:21.692009 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
851 07:25:21.739576 Check phy result
852 07:25:21.740079 INFO : End of initialization
853 07:25:21.761338 INFO : End of 2D read delay Voltage center optimization
854 07:25:21.781513 INFO : End of 2D read delay Voltage center optimization
855 07:25:21.833639 INFO : End of 2D write delay Voltage center optimization
856 07:25:21.882969 INFO : End of 2D write delay Voltage center optimization
857 07:25:21.888548 INFO : Training has run successfully!
858 07:25:21.888919
859 07:25:21.889147 channel==0
860 07:25:21.894053 RxClkDly_Margin_A0==88 ps 9
861 07:25:21.894423 TxDqDly_Margin_A0==98 ps 10
862 07:25:21.899888 RxClkDly_Margin_A1==88 ps 9
863 07:25:21.904094 TxDqDly_Margin_A1==88 ps 9
864 07:25:21.904527 TrainedVREFDQ_A0==74
865 07:25:21.905303 TrainedVREFDQ_A1==74
866 07:25:21.905644 VrefDac_Margin_A0==25
867 07:25:21.905932 DeviceVref_Margin_A0==40
868 07:25:21.910880 VrefDac_Margin_A1==25
869 07:25:21.911283 DeviceVref_Margin_A1==40
870 07:25:21.911572
871 07:25:21.911855
872 07:25:21.912199 channel==1
873 07:25:21.916368 RxClkDly_Margin_A0==98 ps 10
874 07:25:21.916756 TxDqDly_Margin_A0==88 ps 9
875 07:25:21.921990 RxClkDly_Margin_A1==88 ps 9
876 07:25:21.922394 TxDqDly_Margin_A1==88 ps 9
877 07:25:21.927711 TrainedVREFDQ_A0==76
878 07:25:21.928127 TrainedVREFDQ_A1==77
879 07:25:21.928420 VrefDac_Margin_A0==22
880 07:25:21.933319 DeviceVref_Margin_A0==38
881 07:25:21.933709 VrefDac_Margin_A1==24
882 07:25:21.938871 DeviceVref_Margin_A1==37
883 07:25:21.939275
884 07:25:21.939558 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
885 07:25:21.939821
886 07:25:21.972846 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000019 00000018 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 0000001a 00000018 00000017 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
887 07:25:21.973351 2D training succeed
888 07:25:21.977994 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
889 07:25:21.983595 auto size-- 65535DDR cs0 size: 2048MB
890 07:25:21.984057 DDR cs1 size: 2048MB
891 07:25:21.989182 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
892 07:25:21.989554 cs0 DataBus test pass
893 07:25:21.994789 cs1 DataBus test pass
894 07:25:21.995198 cs0 AddrBus test pass
895 07:25:21.995475 cs1 AddrBus test pass
896 07:25:21.995735
897 07:25:22.000482 100bdlr_step_size ps== 420
898 07:25:22.000879 result report
899 07:25:22.005967 boot times 0Enable ddr reg access
900 07:25:22.011272 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
901 07:25:22.024584 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
902 07:25:22.597883 0.0;M3 CHK:0;cm4_sp_mode 0
903 07:25:22.598788 MVN_1=0x00000000
904 07:25:22.603241 MVN_2=0x00000000
905 07:25:22.608966 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
906 07:25:22.609840 OPS=0x10
907 07:25:22.610480 ring efuse init
908 07:25:22.611034 chipver efuse init
909 07:25:22.614567 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
910 07:25:22.620303 [0.018960 Inits done]
911 07:25:22.621049 secure task start!
912 07:25:22.621610 high task start!
913 07:25:22.624841 low task start!
914 07:25:22.625531 run into bl31
915 07:25:22.631440 NOTICE: BL31: v1.3(release):4fc40b1
916 07:25:22.639199 NOTICE: BL31: Built : 15:58:17, May 22 2019
917 07:25:22.639943 NOTICE: BL31: G12A normal boot!
918 07:25:22.664527 NOTICE: BL31: BL33 decompress pass
919 07:25:22.670140 ERROR: Error initializing runtime service opteed_fast
920 07:25:23.903082
921 07:25:23.903519
922 07:25:23.911499 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
923 07:25:23.911891
924 07:25:23.912158 Model: Libre Computer AML-A311D-CC Alta
925 07:25:24.120039 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
926 07:25:24.143360 DRAM: 2 GiB (effective 3.8 GiB)
927 07:25:24.286357 Core: 408 devices, 31 uclasses, devicetree: separate
928 07:25:24.292241 WDT: Not starting watchdog@f0d0
929 07:25:24.324428 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
930 07:25:24.336914 Loading Environment from FAT... Card did not respond to voltage select! : -110
931 07:25:24.342008 ** Bad device specification mmc 0 **
932 07:25:24.352250 Card did not respond to voltage select! : -110
933 07:25:24.359884 ** Bad device specification mmc 0 **
934 07:25:24.360257 Couldn't find partition mmc 0
935 07:25:24.368166 Card did not respond to voltage select! : -110
936 07:25:24.373745 ** Bad device specification mmc 0 **
937 07:25:24.374053 Couldn't find partition mmc 0
938 07:25:24.377793 Error: could not access storage.
939 07:25:24.721278 Net: eth0: ethernet@ff3f0000
940 07:25:24.721875 starting USB...
941 07:25:24.973191 Bus usb@ff500000: Register 3000140 NbrPorts 3
942 07:25:24.973789 Starting the controller
943 07:25:24.980179 USB XHCI 1.10
944 07:25:26.792115 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
945 07:25:26.792747 bl2_stage_init 0x01
946 07:25:26.793173 bl2_stage_init 0x81
947 07:25:26.797746 hw id: 0x0000 - pwm id 0x01
948 07:25:26.798306 bl2_stage_init 0xc1
949 07:25:26.798734 bl2_stage_init 0x02
950 07:25:26.799146
951 07:25:26.803298 L0:00000000
952 07:25:26.803788 L1:20000703
953 07:25:26.804239 L2:00008067
954 07:25:26.804646 L3:14000000
955 07:25:26.806255 B2:00402000
956 07:25:26.807435 B1:e0f83180
957 07:25:26.807906
958 07:25:26.808367 TE: 58124
959 07:25:26.808785
960 07:25:26.817322 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
961 07:25:26.817890
962 07:25:26.818316 Board ID = 1
963 07:25:26.818720 Set A53 clk to 24M
964 07:25:26.819122 Set A73 clk to 24M
965 07:25:26.822953 Set clk81 to 24M
966 07:25:26.823481 A53 clk: 1200 MHz
967 07:25:26.823948 A73 clk: 1200 MHz
968 07:25:26.828563 CLK81: 166.6M
969 07:25:26.829069 smccc: 00012a92
970 07:25:26.834117 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
971 07:25:26.834586 board id: 1
972 07:25:26.842763 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
973 07:25:26.853460 fw parse done
974 07:25:26.859323 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
975 07:25:26.902018 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
976 07:25:26.912885 PIEI prepare done
977 07:25:26.913418 fastboot data load
978 07:25:26.913823 fastboot data verify
979 07:25:26.918507 verify result: 266
980 07:25:26.924148 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
981 07:25:26.924644 LPDDR4 probe
982 07:25:26.925084 ddr clk to 1584MHz
983 07:25:26.932143 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
984 07:25:26.969624
985 07:25:26.970152 dmc_version 0001
986 07:25:26.976182 Check phy result
987 07:25:26.982064 INFO : End of CA training
988 07:25:26.982570 INFO : End of initialization
989 07:25:26.987562 INFO : Training has run successfully!
990 07:25:26.988075 Check phy result
991 07:25:26.993201 INFO : End of initialization
992 07:25:26.993680 INFO : End of read enable training
993 07:25:26.996578 INFO : End of fine write leveling
994 07:25:27.002041 INFO : End of Write leveling coarse delay
995 07:25:27.007881 INFO : Training has run successfully!
996 07:25:27.008225 Check phy result
997 07:25:27.008470 INFO : End of initialization
998 07:25:27.013443 INFO : End of read dq deskew training
999 07:25:27.016653 INFO : End of MPR read delay center optimization
1000 07:25:27.022336 INFO : End of write delay center optimization
1001 07:25:27.028199 INFO : End of read delay center optimization
1002 07:25:27.028596 INFO : End of max read latency training
1003 07:25:27.033463 INFO : Training has run successfully!
1004 07:25:27.033790 1D training succeed
1005 07:25:27.041562 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
1006 07:25:27.089047 Check phy result
1007 07:25:27.089481 INFO : End of initialization
1008 07:25:27.111015 INFO : End of 2D read delay Voltage center optimization
1009 07:25:27.131118 INFO : End of 2D read delay Voltage center optimization
1010 07:25:27.183196 INFO : End of 2D write delay Voltage center optimization
1011 07:25:27.232636 INFO : End of 2D write delay Voltage center optimization
1012 07:25:27.238076 INFO : Training has run successfully!
1013 07:25:27.238400
1014 07:25:27.238631 channel==0
1015 07:25:27.243633 RxClkDly_Margin_A0==88 ps 9
1016 07:25:27.243953 TxDqDly_Margin_A0==98 ps 10
1017 07:25:27.249298 RxClkDly_Margin_A1==88 ps 9
1018 07:25:27.249605 TxDqDly_Margin_A1==98 ps 10
1019 07:25:27.249829 TrainedVREFDQ_A0==74
1020 07:25:27.254791 TrainedVREFDQ_A1==74
1021 07:25:27.255103 VrefDac_Margin_A0==25
1022 07:25:27.255329 DeviceVref_Margin_A0==40
1023 07:25:27.260435 VrefDac_Margin_A1==25
1024 07:25:27.260738 DeviceVref_Margin_A1==40
1025 07:25:27.260953
1026 07:25:27.261163
1027 07:25:27.266021 channel==1
1028 07:25:27.266326 RxClkDly_Margin_A0==98 ps 10
1029 07:25:27.266548 TxDqDly_Margin_A0==88 ps 9
1030 07:25:27.271646 RxClkDly_Margin_A1==88 ps 9
1031 07:25:27.271952 TxDqDly_Margin_A1==88 ps 9
1032 07:25:27.277331 TrainedVREFDQ_A0==76
1033 07:25:27.277642 TrainedVREFDQ_A1==77
1034 07:25:27.277855 VrefDac_Margin_A0==22
1035 07:25:27.282816 DeviceVref_Margin_A0==38
1036 07:25:27.283114 VrefDac_Margin_A1==24
1037 07:25:27.288408 DeviceVref_Margin_A1==37
1038 07:25:27.288714
1039 07:25:27.288930 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
1040 07:25:27.289139
1041 07:25:27.321997 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000018 00000019 00000018 00000019 00000018 0000001a 0000001a 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
1042 07:25:27.322392 2D training succeed
1043 07:25:27.327675 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
1044 07:25:27.333226 auto size-- 65535DDR cs0 size: 2048MB
1045 07:25:27.333551 DDR cs1 size: 2048MB
1046 07:25:27.338896 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
1047 07:25:27.339280 cs0 DataBus test pass
1048 07:25:27.344546 cs1 DataBus test pass
1049 07:25:27.345096 cs0 AddrBus test pass
1050 07:25:27.345995 cs1 AddrBus test pass
1051 07:25:27.346626
1052 07:25:27.350081 100bdlr_step_size ps== 420
1053 07:25:27.350583 result report
1054 07:25:27.355680 boot times 0Enable ddr reg access
1055 07:25:27.360964 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
1056 07:25:27.374766 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
1057 07:25:27.948136 0.0;M3 CHK:0;cm4_sp_mode 0
1058 07:25:27.948739 MVN_1=0x00000000
1059 07:25:27.953476 MVN_2=0x00000000
1060 07:25:27.959227 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
1061 07:25:27.959566 OPS=0x10
1062 07:25:27.959892 ring efuse init
1063 07:25:27.960221 chipver efuse init
1064 07:25:27.967550 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
1065 07:25:27.968035 [0.018961 Inits done]
1066 07:25:27.968569 secure task start!
1067 07:25:27.974983 high task start!
1068 07:25:27.975310 low task start!
1069 07:25:27.975639 run into bl31
1070 07:25:27.981661 NOTICE: BL31: v1.3(release):4fc40b1
1071 07:25:27.989476 NOTICE: BL31: Built : 15:58:17, May 22 2019
1072 07:25:27.989960 NOTICE: BL31: G12A normal boot!
1073 07:25:28.015454 NOTICE: BL31: BL33 decompress pass
1074 07:25:28.021148 ERROR: Error initializing runtime service opteed_fast
1075 07:25:29.253919
1076 07:25:29.254503
1077 07:25:29.262553 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
1078 07:25:29.263126
1079 07:25:29.263537 Model: Libre Computer AML-A311D-CC Alta
1080 07:25:29.470870 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
1081 07:25:29.494250 DRAM: 2 GiB (effective 3.8 GiB)
1082 07:25:29.637192 Core: 408 devices, 31 uclasses, devicetree: separate
1083 07:25:29.642989 WDT: Not starting watchdog@f0d0
1084 07:25:29.675286 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
1085 07:25:29.687740 Loading Environment from FAT... Card did not respond to voltage select! : -110
1086 07:25:29.691812 ** Bad device specification mmc 0 **
1087 07:25:29.703036 Card did not respond to voltage select! : -110
1088 07:25:29.709729 ** Bad device specification mmc 0 **
1089 07:25:29.710045 Couldn't find partition mmc 0
1090 07:25:29.718977 Card did not respond to voltage select! : -110
1091 07:25:29.724643 ** Bad device specification mmc 0 **
1092 07:25:29.724997 Couldn't find partition mmc 0
1093 07:25:29.728743 Error: could not access storage.
1094 07:25:30.072095 Net: eth0: ethernet@ff3f0000
1095 07:25:30.072518 starting USB...
1096 07:25:30.323975 Bus usb@ff500000: Register 3000140 NbrPorts 3
1097 07:25:30.324452 Starting the controller
1098 07:25:30.329954 USB XHCI 1.10
1099 07:25:31.885131 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
1100 07:25:31.893335 scanning usb for storage devices... 0 Storage Device(s) found
1102 07:25:31.945138 Hit any key to stop autoboot: 1
1103 07:25:31.946214 end: 2.4.2 bootloader-interrupt (duration 00:00:37) [common]
1104 07:25:31.947005 start: 2.4.3 bootloader-commands (timeout 00:04:23) [common]
1105 07:25:31.947552 Setting prompt string to ['=>']
1106 07:25:31.948122 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:23)
1107 07:25:31.960754 0
1108 07:25:31.961787 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1109 07:25:31.962272 Sending with 10 millisecond of delay
1111 07:25:33.097353 => setenv autoload no
1112 07:25:33.108150 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:21)
1113 07:25:33.113095 setenv autoload no
1114 07:25:33.113852 Sending with 10 millisecond of delay
1116 07:25:34.911667 => setenv initrd_high 0xffffffff
1117 07:25:34.922448 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:20)
1118 07:25:34.923019 setenv initrd_high 0xffffffff
1119 07:25:34.923476 Sending with 10 millisecond of delay
1121 07:25:36.539941 => setenv fdt_high 0xffffffff
1122 07:25:36.550853 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1123 07:25:36.551768 setenv fdt_high 0xffffffff
1124 07:25:36.552579 Sending with 10 millisecond of delay
1126 07:25:36.844484 => dhcp
1127 07:25:36.855045 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1128 07:25:36.855584 dhcp
1129 07:25:36.855824 Speed: 1000, full duplex
1130 07:25:36.856086 BOOTP broadcast 1
1131 07:25:36.863899 DHCP client bound to address 192.168.6.27 (9 ms)
1132 07:25:36.864430 Sending with 10 millisecond of delay
1134 07:25:38.542133 => setenv serverip 192.168.6.2
1135 07:25:38.552733 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:16)
1136 07:25:38.553350 setenv serverip 192.168.6.2
1137 07:25:38.553841 Sending with 10 millisecond of delay
1139 07:25:42.277750 => tftpboot 0x01080000 978361/tftp-deploy-ho5liheu/kernel/uImage
1140 07:25:42.288584 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:12)
1141 07:25:42.289450 tftpboot 0x01080000 978361/tftp-deploy-ho5liheu/kernel/uImage
1142 07:25:42.289950 Speed: 1000, full duplex
1143 07:25:42.290414 Using ethernet@ff3f0000 device
1144 07:25:42.291301 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1145 07:25:42.296922 Filename '978361/tftp-deploy-ho5liheu/kernel/uImage'.
1146 07:25:42.300877 Load address: 0x1080000
1147 07:25:45.278661 Loading: *################################################## 44 MiB
1148 07:25:45.279206 14.8 MiB/s
1149 07:25:45.279455 done
1150 07:25:45.282805 Bytes transferred = 46121536 (2bfc240 hex)
1151 07:25:45.283575 Sending with 10 millisecond of delay
1153 07:25:49.981394 => tftpboot 0x08000000 978361/tftp-deploy-ho5liheu/ramdisk/ramdisk.cpio.gz.uboot
1154 07:25:49.992142 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:05)
1155 07:25:49.992945 tftpboot 0x08000000 978361/tftp-deploy-ho5liheu/ramdisk/ramdisk.cpio.gz.uboot
1156 07:25:49.993381 Speed: 1000, full duplex
1157 07:25:49.993785 Using ethernet@ff3f0000 device
1158 07:25:49.995025 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1159 07:25:50.004758 Filename '978361/tftp-deploy-ho5liheu/ramdisk/ramdisk.cpio.gz.uboot'.
1160 07:25:50.005234 Load address: 0x8000000
1161 07:25:56.474357 Loading: *#############T ##################################### 22.5 MiB
1162 07:25:56.474961 3.5 MiB/s
1163 07:25:56.475369 done
1164 07:25:56.478737 Bytes transferred = 23565396 (1679454 hex)
1165 07:25:56.479511 Sending with 10 millisecond of delay
1167 07:26:01.648753 => tftpboot 0x01070000 978361/tftp-deploy-ho5liheu/dtb/meson-g12b-a311d-libretech-cc.dtb
1168 07:26:01.659580 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:03:53)
1169 07:26:01.660478 tftpboot 0x01070000 978361/tftp-deploy-ho5liheu/dtb/meson-g12b-a311d-libretech-cc.dtb
1170 07:26:01.660966 Speed: 1000, full duplex
1171 07:26:01.661425 Using ethernet@ff3f0000 device
1172 07:26:01.664523 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1173 07:26:01.676863 Filename '978361/tftp-deploy-ho5liheu/dtb/meson-g12b-a311d-libretech-cc.dtb'.
1174 07:26:01.677452 Load address: 0x1070000
1175 07:26:01.693187 Loading: *################################################## 53.4 KiB
1176 07:26:01.693720 2.9 MiB/s
1177 07:26:01.694182 done
1178 07:26:01.699458 Bytes transferred = 54703 (d5af hex)
1179 07:26:01.700211 Sending with 10 millisecond of delay
1181 07:26:15.000223 => setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/978361/extract-nfsrootfs-d63fdvs3,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
1182 07:26:15.011080 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:03:39)
1183 07:26:15.012096 setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/978361/extract-nfsrootfs-d63fdvs3,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
1184 07:26:15.012875 Sending with 10 millisecond of delay
1186 07:26:17.354247 => bootm 0x01080000 0x08000000 0x01070000
1187 07:26:17.365465 Setting prompt string to ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1188 07:26:17.366172 bootloader-commands: Wait for prompt ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:03:37)
1189 07:26:17.367256 bootm 0x01080000 0x08000000 0x01070000
1190 07:26:17.367751 Wrong Image Format for bootm command
1191 07:26:17.368358 ERROR: can't get kernel image!
1193 07:26:17.369945 end: 2.4.3 bootloader-commands (duration 00:00:45) [common]
1196 07:26:17.372110 end: 2.4 uboot-commands (duration 00:01:23) [common]
1198 07:26:17.373731 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Wrong Image Format for boot' (14)'
1200 07:26:17.374905 end: 2 uboot-action (duration 00:01:23) [common]
1202 07:26:17.376655 Cleaning after the job
1203 07:26:17.377281 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/978361/tftp-deploy-ho5liheu/ramdisk
1204 07:26:17.391401 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/978361/tftp-deploy-ho5liheu/kernel
1205 07:26:17.421485 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/978361/tftp-deploy-ho5liheu/dtb
1206 07:26:17.422352 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/978361/tftp-deploy-ho5liheu/nfsrootfs
1207 07:26:17.576779 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/978361/tftp-deploy-ho5liheu/modules
1208 07:26:17.599050 start: 4.1 power-off (timeout 00:00:30) [common]
1209 07:26:17.599783 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1210 07:26:17.636704 >> OK - accepted request
1211 07:26:17.638352 Returned 0 in 0 seconds
1212 07:26:17.739157 end: 4.1 power-off (duration 00:00:00) [common]
1214 07:26:17.740198 start: 4.2 read-feedback (timeout 00:10:00) [common]
1215 07:26:17.740854 Listened to connection for namespace 'common' for up to 1s
1216 07:26:18.741072 Finalising connection for namespace 'common'
1217 07:26:18.741618 Disconnecting from shell: Finalise
1218 07:26:18.741968 =>
1219 07:26:18.842809 end: 4.2 read-feedback (duration 00:00:01) [common]
1220 07:26:18.843389 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/978361
1221 07:26:20.644549 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/978361
1222 07:26:20.645153 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.