Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 07:26:54.318024 lava-dispatcher, installed at version: 2024.01
2 07:26:54.318794 start: 0 validate
3 07:26:54.319274 Start time: 2024-11-12 07:26:54.319244+00:00 (UTC)
4 07:26:54.319816 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 07:26:54.320397 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230703.0%2Farm64%2Frootfs.cpio.gz exists
6 07:26:54.363129 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 07:26:54.363795 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241112%2Farm64%2Fdefconfig%2Bkselftest%2Fgcc-12%2Fkernel%2FImage exists
8 07:26:54.395656 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 07:26:54.396498 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241112%2Farm64%2Fdefconfig%2Bkselftest%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 07:26:55.447588 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 07:26:55.448237 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241112%2Farm64%2Fdefconfig%2Bkselftest%2Fgcc-12%2Fmodules.tar.xz exists
12 07:26:55.489150 validate duration: 1.17
14 07:26:55.490001 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 07:26:55.490342 start: 1.1 download-retry (timeout 00:10:00) [common]
16 07:26:55.490648 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 07:26:55.491222 Not decompressing ramdisk as can be used compressed.
18 07:26:55.491646 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230703.0/arm64/rootfs.cpio.gz
19 07:26:55.491886 saving as /var/lib/lava/dispatcher/tmp/978419/tftp-deploy-5p14solb/ramdisk/rootfs.cpio.gz
20 07:26:55.492166 total size: 8181887 (7 MB)
21 07:26:55.530392 progress 0 % (0 MB)
22 07:26:55.541848 progress 5 % (0 MB)
23 07:26:55.552550 progress 10 % (0 MB)
24 07:26:55.561244 progress 15 % (1 MB)
25 07:26:55.567103 progress 20 % (1 MB)
26 07:26:55.573175 progress 25 % (1 MB)
27 07:26:55.578748 progress 30 % (2 MB)
28 07:26:55.585140 progress 35 % (2 MB)
29 07:26:55.591028 progress 40 % (3 MB)
30 07:26:55.596855 progress 45 % (3 MB)
31 07:26:55.602378 progress 50 % (3 MB)
32 07:26:55.608207 progress 55 % (4 MB)
33 07:26:55.613661 progress 60 % (4 MB)
34 07:26:55.619406 progress 65 % (5 MB)
35 07:26:55.624856 progress 70 % (5 MB)
36 07:26:55.630712 progress 75 % (5 MB)
37 07:26:55.636107 progress 80 % (6 MB)
38 07:26:55.641917 progress 85 % (6 MB)
39 07:26:55.647243 progress 90 % (7 MB)
40 07:26:55.652975 progress 95 % (7 MB)
41 07:26:55.657931 progress 100 % (7 MB)
42 07:26:55.658601 7 MB downloaded in 0.17 s (46.89 MB/s)
43 07:26:55.659144 end: 1.1.1 http-download (duration 00:00:00) [common]
45 07:26:55.660060 end: 1.1 download-retry (duration 00:00:00) [common]
46 07:26:55.660361 start: 1.2 download-retry (timeout 00:10:00) [common]
47 07:26:55.660633 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 07:26:55.661099 downloading http://storage.kernelci.org/next/master/next-20241112/arm64/defconfig+kselftest/gcc-12/kernel/Image
49 07:26:55.661343 saving as /var/lib/lava/dispatcher/tmp/978419/tftp-deploy-5p14solb/kernel/Image
50 07:26:55.661551 total size: 66982400 (63 MB)
51 07:26:55.661760 No compression specified
52 07:26:55.696978 progress 0 % (0 MB)
53 07:26:55.737793 progress 5 % (3 MB)
54 07:26:55.778477 progress 10 % (6 MB)
55 07:26:55.819067 progress 15 % (9 MB)
56 07:26:55.859328 progress 20 % (12 MB)
57 07:26:55.900500 progress 25 % (16 MB)
58 07:26:55.940613 progress 30 % (19 MB)
59 07:26:55.981172 progress 35 % (22 MB)
60 07:26:56.021133 progress 40 % (25 MB)
61 07:26:56.062101 progress 45 % (28 MB)
62 07:26:56.103266 progress 50 % (31 MB)
63 07:26:56.144467 progress 55 % (35 MB)
64 07:26:56.185689 progress 60 % (38 MB)
65 07:26:56.226619 progress 65 % (41 MB)
66 07:26:56.267912 progress 70 % (44 MB)
67 07:26:56.309474 progress 75 % (47 MB)
68 07:26:56.350819 progress 80 % (51 MB)
69 07:26:56.391862 progress 85 % (54 MB)
70 07:26:56.432659 progress 90 % (57 MB)
71 07:26:56.474098 progress 95 % (60 MB)
72 07:26:56.515276 progress 100 % (63 MB)
73 07:26:56.515881 63 MB downloaded in 0.85 s (74.77 MB/s)
74 07:26:56.516419 end: 1.2.1 http-download (duration 00:00:01) [common]
76 07:26:56.517245 end: 1.2 download-retry (duration 00:00:01) [common]
77 07:26:56.517522 start: 1.3 download-retry (timeout 00:09:59) [common]
78 07:26:56.517786 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 07:26:56.518256 downloading http://storage.kernelci.org/next/master/next-20241112/arm64/defconfig+kselftest/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
80 07:26:56.518545 saving as /var/lib/lava/dispatcher/tmp/978419/tftp-deploy-5p14solb/dtb/meson-g12b-a311d-libretech-cc.dtb
81 07:26:56.518756 total size: 54703 (0 MB)
82 07:26:56.518967 No compression specified
83 07:26:56.559565 progress 59 % (0 MB)
84 07:26:56.560515 progress 100 % (0 MB)
85 07:26:56.561103 0 MB downloaded in 0.04 s (1.23 MB/s)
86 07:26:56.561595 end: 1.3.1 http-download (duration 00:00:00) [common]
88 07:26:56.562427 end: 1.3 download-retry (duration 00:00:00) [common]
89 07:26:56.562696 start: 1.4 download-retry (timeout 00:09:59) [common]
90 07:26:56.562965 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 07:26:56.563432 downloading http://storage.kernelci.org/next/master/next-20241112/arm64/defconfig+kselftest/gcc-12/modules.tar.xz
92 07:26:56.563692 saving as /var/lib/lava/dispatcher/tmp/978419/tftp-deploy-5p14solb/modules/modules.tar
93 07:26:56.563900 total size: 16284560 (15 MB)
94 07:26:56.564188 Using unxz to decompress xz
95 07:26:56.602122 progress 0 % (0 MB)
96 07:26:56.718268 progress 5 % (0 MB)
97 07:26:56.832516 progress 10 % (1 MB)
98 07:26:56.956042 progress 15 % (2 MB)
99 07:26:57.087919 progress 20 % (3 MB)
100 07:26:57.231694 progress 25 % (3 MB)
101 07:26:57.344994 progress 30 % (4 MB)
102 07:26:57.453013 progress 35 % (5 MB)
103 07:26:57.571166 progress 40 % (6 MB)
104 07:26:57.690655 progress 45 % (7 MB)
105 07:26:57.819222 progress 50 % (7 MB)
106 07:26:57.943996 progress 55 % (8 MB)
107 07:26:58.074442 progress 60 % (9 MB)
108 07:26:58.201107 progress 65 % (10 MB)
109 07:26:58.313449 progress 70 % (10 MB)
110 07:26:58.434046 progress 75 % (11 MB)
111 07:26:58.552148 progress 80 % (12 MB)
112 07:26:58.667429 progress 85 % (13 MB)
113 07:26:58.781757 progress 90 % (14 MB)
114 07:26:58.887541 progress 95 % (14 MB)
115 07:26:59.002557 progress 100 % (15 MB)
116 07:26:59.016996 15 MB downloaded in 2.45 s (6.33 MB/s)
117 07:26:59.017632 end: 1.4.1 http-download (duration 00:00:02) [common]
119 07:26:59.018467 end: 1.4 download-retry (duration 00:00:02) [common]
120 07:26:59.018746 start: 1.5 prepare-tftp-overlay (timeout 00:09:56) [common]
121 07:26:59.019014 start: 1.5.1 extract-nfsrootfs (timeout 00:09:56) [common]
122 07:26:59.019265 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 07:26:59.019520 start: 1.5.2 lava-overlay (timeout 00:09:56) [common]
124 07:26:59.020219 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/978419/lava-overlay-4ch2etmx
125 07:26:59.021103 makedir: /var/lib/lava/dispatcher/tmp/978419/lava-overlay-4ch2etmx/lava-978419/bin
126 07:26:59.021758 makedir: /var/lib/lava/dispatcher/tmp/978419/lava-overlay-4ch2etmx/lava-978419/tests
127 07:26:59.022384 makedir: /var/lib/lava/dispatcher/tmp/978419/lava-overlay-4ch2etmx/lava-978419/results
128 07:26:59.022998 Creating /var/lib/lava/dispatcher/tmp/978419/lava-overlay-4ch2etmx/lava-978419/bin/lava-add-keys
129 07:26:59.023949 Creating /var/lib/lava/dispatcher/tmp/978419/lava-overlay-4ch2etmx/lava-978419/bin/lava-add-sources
130 07:26:59.025016 Creating /var/lib/lava/dispatcher/tmp/978419/lava-overlay-4ch2etmx/lava-978419/bin/lava-background-process-start
131 07:26:59.026053 Creating /var/lib/lava/dispatcher/tmp/978419/lava-overlay-4ch2etmx/lava-978419/bin/lava-background-process-stop
132 07:26:59.027164 Creating /var/lib/lava/dispatcher/tmp/978419/lava-overlay-4ch2etmx/lava-978419/bin/lava-common-functions
133 07:26:59.028137 Creating /var/lib/lava/dispatcher/tmp/978419/lava-overlay-4ch2etmx/lava-978419/bin/lava-echo-ipv4
134 07:26:59.029077 Creating /var/lib/lava/dispatcher/tmp/978419/lava-overlay-4ch2etmx/lava-978419/bin/lava-install-packages
135 07:26:59.029982 Creating /var/lib/lava/dispatcher/tmp/978419/lava-overlay-4ch2etmx/lava-978419/bin/lava-installed-packages
136 07:26:59.030869 Creating /var/lib/lava/dispatcher/tmp/978419/lava-overlay-4ch2etmx/lava-978419/bin/lava-os-build
137 07:26:59.031797 Creating /var/lib/lava/dispatcher/tmp/978419/lava-overlay-4ch2etmx/lava-978419/bin/lava-probe-channel
138 07:26:59.032786 Creating /var/lib/lava/dispatcher/tmp/978419/lava-overlay-4ch2etmx/lava-978419/bin/lava-probe-ip
139 07:26:59.033740 Creating /var/lib/lava/dispatcher/tmp/978419/lava-overlay-4ch2etmx/lava-978419/bin/lava-target-ip
140 07:26:59.034655 Creating /var/lib/lava/dispatcher/tmp/978419/lava-overlay-4ch2etmx/lava-978419/bin/lava-target-mac
141 07:26:59.035603 Creating /var/lib/lava/dispatcher/tmp/978419/lava-overlay-4ch2etmx/lava-978419/bin/lava-target-storage
142 07:26:59.036560 Creating /var/lib/lava/dispatcher/tmp/978419/lava-overlay-4ch2etmx/lava-978419/bin/lava-test-case
143 07:26:59.037557 Creating /var/lib/lava/dispatcher/tmp/978419/lava-overlay-4ch2etmx/lava-978419/bin/lava-test-event
144 07:26:59.038458 Creating /var/lib/lava/dispatcher/tmp/978419/lava-overlay-4ch2etmx/lava-978419/bin/lava-test-feedback
145 07:26:59.039392 Creating /var/lib/lava/dispatcher/tmp/978419/lava-overlay-4ch2etmx/lava-978419/bin/lava-test-raise
146 07:26:59.040379 Creating /var/lib/lava/dispatcher/tmp/978419/lava-overlay-4ch2etmx/lava-978419/bin/lava-test-reference
147 07:26:59.041296 Creating /var/lib/lava/dispatcher/tmp/978419/lava-overlay-4ch2etmx/lava-978419/bin/lava-test-runner
148 07:26:59.042253 Creating /var/lib/lava/dispatcher/tmp/978419/lava-overlay-4ch2etmx/lava-978419/bin/lava-test-set
149 07:26:59.043173 Creating /var/lib/lava/dispatcher/tmp/978419/lava-overlay-4ch2etmx/lava-978419/bin/lava-test-shell
150 07:26:59.044175 Updating /var/lib/lava/dispatcher/tmp/978419/lava-overlay-4ch2etmx/lava-978419/bin/lava-install-packages (oe)
151 07:26:59.045278 Updating /var/lib/lava/dispatcher/tmp/978419/lava-overlay-4ch2etmx/lava-978419/bin/lava-installed-packages (oe)
152 07:26:59.046176 Creating /var/lib/lava/dispatcher/tmp/978419/lava-overlay-4ch2etmx/lava-978419/environment
153 07:26:59.046938 LAVA metadata
154 07:26:59.047428 - LAVA_JOB_ID=978419
155 07:26:59.047852 - LAVA_DISPATCHER_IP=192.168.6.2
156 07:26:59.048573 start: 1.5.2.1 ssh-authorize (timeout 00:09:56) [common]
157 07:26:59.050397 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 07:26:59.050992 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:56) [common]
159 07:26:59.051401 skipped lava-vland-overlay
160 07:26:59.051884 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 07:26:59.052425 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:56) [common]
162 07:26:59.052851 skipped lava-multinode-overlay
163 07:26:59.053331 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 07:26:59.053830 start: 1.5.2.4 test-definition (timeout 00:09:56) [common]
165 07:26:59.054306 Loading test definitions
166 07:26:59.054852 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:56) [common]
167 07:26:59.055288 Using /lava-978419 at stage 0
168 07:26:59.057715 uuid=978419_1.5.2.4.1 testdef=None
169 07:26:59.058308 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 07:26:59.058824 start: 1.5.2.4.2 test-overlay (timeout 00:09:56) [common]
171 07:26:59.062363 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 07:26:59.063923 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:56) [common]
174 07:26:59.066406 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 07:26:59.067242 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:56) [common]
177 07:26:59.069570 runner path: /var/lib/lava/dispatcher/tmp/978419/lava-overlay-4ch2etmx/lava-978419/0/tests/0_dmesg test_uuid 978419_1.5.2.4.1
178 07:26:59.070210 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 07:26:59.070992 Creating lava-test-runner.conf files
181 07:26:59.071194 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/978419/lava-overlay-4ch2etmx/lava-978419/0 for stage 0
182 07:26:59.071550 - 0_dmesg
183 07:26:59.071912 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 07:26:59.072224 start: 1.5.2.5 compress-overlay (timeout 00:09:56) [common]
185 07:26:59.096577 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 07:26:59.097027 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:56) [common]
187 07:26:59.097293 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 07:26:59.097562 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 07:26:59.097823 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:56) [common]
190 07:27:00.220324 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
191 07:27:00.221064 start: 1.5.4 extract-modules (timeout 00:09:55) [common]
192 07:27:00.221561 extracting modules file /var/lib/lava/dispatcher/tmp/978419/tftp-deploy-5p14solb/modules/modules.tar to /var/lib/lava/dispatcher/tmp/978419/extract-overlay-ramdisk-dgsr4cq1/ramdisk
193 07:27:01.950734 end: 1.5.4 extract-modules (duration 00:00:02) [common]
194 07:27:01.951244 start: 1.5.5 apply-overlay-tftp (timeout 00:09:54) [common]
195 07:27:01.951531 [common] Applying overlay /var/lib/lava/dispatcher/tmp/978419/compress-overlay-l5wvm_5m/overlay-1.5.2.5.tar.gz to ramdisk
196 07:27:01.951749 [common] Applying overlay /var/lib/lava/dispatcher/tmp/978419/compress-overlay-l5wvm_5m/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/978419/extract-overlay-ramdisk-dgsr4cq1/ramdisk
197 07:27:01.982417 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 07:27:01.982926 start: 1.5.6 prepare-kernel (timeout 00:09:54) [common]
199 07:27:01.983209 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:54) [common]
200 07:27:01.983448 Converting downloaded kernel to a uImage
201 07:27:01.983795 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/978419/tftp-deploy-5p14solb/kernel/Image /var/lib/lava/dispatcher/tmp/978419/tftp-deploy-5p14solb/kernel/uImage
202 07:27:02.671661 output: Image Name:
203 07:27:02.672118 output: Created: Tue Nov 12 07:27:01 2024
204 07:27:02.672334 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 07:27:02.672539 output: Data Size: 66982400 Bytes = 65412.50 KiB = 63.88 MiB
206 07:27:02.672741 output: Load Address: 01080000
207 07:27:02.672942 output: Entry Point: 01080000
208 07:27:02.673138 output:
209 07:27:02.673472 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:01) [common]
210 07:27:02.673740 end: 1.5.6 prepare-kernel (duration 00:00:01) [common]
211 07:27:02.674009 start: 1.5.7 configure-preseed-file (timeout 00:09:53) [common]
212 07:27:02.674263 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 07:27:02.674518 start: 1.5.8 compress-ramdisk (timeout 00:09:53) [common]
214 07:27:02.674777 Building ramdisk /var/lib/lava/dispatcher/tmp/978419/extract-overlay-ramdisk-dgsr4cq1/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/978419/extract-overlay-ramdisk-dgsr4cq1/ramdisk
215 07:27:06.171386 >> 258323 blocks
216 07:27:17.392490 Adding RAMdisk u-boot header.
217 07:27:17.392916 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/978419/extract-overlay-ramdisk-dgsr4cq1/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/978419/extract-overlay-ramdisk-dgsr4cq1/ramdisk.cpio.gz.uboot
218 07:27:17.749535 output: Image Name:
219 07:27:17.749955 output: Created: Tue Nov 12 07:27:17 2024
220 07:27:17.750164 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 07:27:17.750367 output: Data Size: 33949245 Bytes = 33153.56 KiB = 32.38 MiB
222 07:27:17.750566 output: Load Address: 00000000
223 07:27:17.750763 output: Entry Point: 00000000
224 07:27:17.750958 output:
225 07:27:17.751613 rename /var/lib/lava/dispatcher/tmp/978419/extract-overlay-ramdisk-dgsr4cq1/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/978419/tftp-deploy-5p14solb/ramdisk/ramdisk.cpio.gz.uboot
226 07:27:17.752107 end: 1.5.8 compress-ramdisk (duration 00:00:15) [common]
227 07:27:17.752724 end: 1.5 prepare-tftp-overlay (duration 00:00:19) [common]
228 07:27:17.753297 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:38) [common]
229 07:27:17.753828 No LXC device requested
230 07:27:17.754378 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 07:27:17.754935 start: 1.7 deploy-device-env (timeout 00:09:38) [common]
232 07:27:17.755470 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 07:27:17.755917 Checking files for TFTP limit of 4294967296 bytes.
234 07:27:17.758857 end: 1 tftp-deploy (duration 00:00:22) [common]
235 07:27:17.759490 start: 2 uboot-action (timeout 00:05:00) [common]
236 07:27:17.760092 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 07:27:17.760649 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 07:27:17.761219 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 07:27:17.761802 Using kernel file from prepare-kernel: 978419/tftp-deploy-5p14solb/kernel/uImage
240 07:27:17.762461 substitutions:
241 07:27:17.762905 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 07:27:17.763349 - {DTB_ADDR}: 0x01070000
243 07:27:17.763785 - {DTB}: 978419/tftp-deploy-5p14solb/dtb/meson-g12b-a311d-libretech-cc.dtb
244 07:27:17.764261 - {INITRD}: 978419/tftp-deploy-5p14solb/ramdisk/ramdisk.cpio.gz.uboot
245 07:27:17.764699 - {KERNEL_ADDR}: 0x01080000
246 07:27:17.765133 - {KERNEL}: 978419/tftp-deploy-5p14solb/kernel/uImage
247 07:27:17.765566 - {LAVA_MAC}: None
248 07:27:17.766043 - {PRESEED_CONFIG}: None
249 07:27:17.766478 - {PRESEED_LOCAL}: None
250 07:27:17.766908 - {RAMDISK_ADDR}: 0x08000000
251 07:27:17.767337 - {RAMDISK}: 978419/tftp-deploy-5p14solb/ramdisk/ramdisk.cpio.gz.uboot
252 07:27:17.767770 - {ROOT_PART}: None
253 07:27:17.768252 - {ROOT}: None
254 07:27:17.768685 - {SERVER_IP}: 192.168.6.2
255 07:27:17.769117 - {TEE_ADDR}: 0x83000000
256 07:27:17.769543 - {TEE}: None
257 07:27:17.769970 Parsed boot commands:
258 07:27:17.770386 - setenv autoload no
259 07:27:17.770810 - setenv initrd_high 0xffffffff
260 07:27:17.771230 - setenv fdt_high 0xffffffff
261 07:27:17.771653 - dhcp
262 07:27:17.772106 - setenv serverip 192.168.6.2
263 07:27:17.772533 - tftpboot 0x01080000 978419/tftp-deploy-5p14solb/kernel/uImage
264 07:27:17.772959 - tftpboot 0x08000000 978419/tftp-deploy-5p14solb/ramdisk/ramdisk.cpio.gz.uboot
265 07:27:17.773382 - tftpboot 0x01070000 978419/tftp-deploy-5p14solb/dtb/meson-g12b-a311d-libretech-cc.dtb
266 07:27:17.773803 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 07:27:17.774234 - bootm 0x01080000 0x08000000 0x01070000
268 07:27:17.774778 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 07:27:17.776419 start: 2.3 connect-device (timeout 00:05:00) [common]
271 07:27:17.776907 [common] connect-device Connecting to device using 'telnet conserv1 3007'
272 07:27:17.792155 Setting prompt string to ['lava-test: # ']
273 07:27:17.793776 end: 2.3 connect-device (duration 00:00:00) [common]
274 07:27:17.794426 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 07:27:17.795020 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 07:27:17.795571 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 07:27:17.796869 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
278 07:27:17.833652 >> OK - accepted request
279 07:27:17.835793 Returned 0 in 0 seconds
280 07:27:17.937313 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
282 07:27:17.939049 end: 2.4.1 reset-device (duration 00:00:00) [common]
283 07:27:17.939655 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
284 07:27:17.940265 Setting prompt string to ['Hit any key to stop autoboot']
285 07:27:17.940767 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 07:27:17.942481 Trying 192.168.56.21...
287 07:27:17.942996 Connected to conserv1.
288 07:27:17.943451 Escape character is '^]'.
289 07:27:17.943913
290 07:27:17.944417 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
291 07:27:17.944891
292 07:27:29.294184 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
293 07:27:29.294804 bl2_stage_init 0x01
294 07:27:29.295231 bl2_stage_init 0x81
295 07:27:29.299679 hw id: 0x0000 - pwm id 0x01
296 07:27:29.300250 bl2_stage_init 0xc1
297 07:27:29.300671 bl2_stage_init 0x02
298 07:27:29.301081
299 07:27:29.305362 L0:00000000
300 07:27:29.305813 L1:20000703
301 07:27:29.306220 L2:00008067
302 07:27:29.306624 L3:14000000
303 07:27:29.308173 B2:00402000
304 07:27:29.308593 B1:e0f83180
305 07:27:29.308993
306 07:27:29.309382 TE: 58124
307 07:27:29.309771
308 07:27:29.319332 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
309 07:27:29.319761
310 07:27:29.320192 Board ID = 1
311 07:27:29.320582 Set A53 clk to 24M
312 07:27:29.320972 Set A73 clk to 24M
313 07:27:29.324866 Set clk81 to 24M
314 07:27:29.325281 A53 clk: 1200 MHz
315 07:27:29.325668 A73 clk: 1200 MHz
316 07:27:29.330474 CLK81: 166.6M
317 07:27:29.330892 smccc: 00012a92
318 07:27:29.336099 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
319 07:27:29.336520 board id: 1
320 07:27:29.344753 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
321 07:27:29.355338 fw parse done
322 07:27:29.361400 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
323 07:27:29.403889 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
324 07:27:29.414738 PIEI prepare done
325 07:27:29.415162 fastboot data load
326 07:27:29.415556 fastboot data verify
327 07:27:29.420465 verify result: 266
328 07:27:29.426055 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
329 07:27:29.426500 LPDDR4 probe
330 07:27:29.426887 ddr clk to 1584MHz
331 07:27:29.434150 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
332 07:27:29.471366
333 07:27:29.471805 dmc_version 0001
334 07:27:29.478152 Check phy result
335 07:27:29.483961 INFO : End of CA training
336 07:27:29.484424 INFO : End of initialization
337 07:27:29.489451 INFO : Training has run successfully!
338 07:27:29.489882 Check phy result
339 07:27:29.495045 INFO : End of initialization
340 07:27:29.495464 INFO : End of read enable training
341 07:27:29.500683 INFO : End of fine write leveling
342 07:27:29.506198 INFO : End of Write leveling coarse delay
343 07:27:29.506620 INFO : Training has run successfully!
344 07:27:29.507021 Check phy result
345 07:27:29.511869 INFO : End of initialization
346 07:27:29.512336 INFO : End of read dq deskew training
347 07:27:29.517416 INFO : End of MPR read delay center optimization
348 07:27:29.523063 INFO : End of write delay center optimization
349 07:27:29.528592 INFO : End of read delay center optimization
350 07:27:29.529011 INFO : End of max read latency training
351 07:27:29.534245 INFO : Training has run successfully!
352 07:27:29.534675 1D training succeed
353 07:27:29.543550 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
354 07:27:29.591085 Check phy result
355 07:27:29.591521 INFO : End of initialization
356 07:27:29.613693 INFO : End of 2D read delay Voltage center optimization
357 07:27:29.633871 INFO : End of 2D read delay Voltage center optimization
358 07:27:29.685913 INFO : End of 2D write delay Voltage center optimization
359 07:27:29.735314 INFO : End of 2D write delay Voltage center optimization
360 07:27:29.740843 INFO : Training has run successfully!
361 07:27:29.741276
362 07:27:29.741686 channel==0
363 07:27:29.746472 RxClkDly_Margin_A0==88 ps 9
364 07:27:29.746894 TxDqDly_Margin_A0==98 ps 10
365 07:27:29.752164 RxClkDly_Margin_A1==88 ps 9
366 07:27:29.752583 TxDqDly_Margin_A1==98 ps 10
367 07:27:29.752990 TrainedVREFDQ_A0==74
368 07:27:29.757594 TrainedVREFDQ_A1==74
369 07:27:29.758017 VrefDac_Margin_A0==25
370 07:27:29.758415 DeviceVref_Margin_A0==40
371 07:27:29.763255 VrefDac_Margin_A1==25
372 07:27:29.763677 DeviceVref_Margin_A1==40
373 07:27:29.764106
374 07:27:29.764514
375 07:27:29.768823 channel==1
376 07:27:29.769241 RxClkDly_Margin_A0==98 ps 10
377 07:27:29.769641 TxDqDly_Margin_A0==88 ps 9
378 07:27:29.774518 RxClkDly_Margin_A1==98 ps 10
379 07:27:29.774946 TxDqDly_Margin_A1==98 ps 10
380 07:27:29.780241 TrainedVREFDQ_A0==76
381 07:27:29.780676 TrainedVREFDQ_A1==77
382 07:27:29.781078 VrefDac_Margin_A0==22
383 07:27:29.785695 DeviceVref_Margin_A0==38
384 07:27:29.786115 VrefDac_Margin_A1==22
385 07:27:29.791246 DeviceVref_Margin_A1==37
386 07:27:29.791663
387 07:27:29.792097 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
388 07:27:29.796827
389 07:27:29.824839 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000018 00000019 00000017 00000019 00000018 00000019 00000019 00000018 00000017 00000018 00000018 0000001a 00000018 00000018 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
390 07:27:29.825325 2D training succeed
391 07:27:29.830461 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
392 07:27:29.836101 auto size-- 65535DDR cs0 size: 2048MB
393 07:27:29.836527 DDR cs1 size: 2048MB
394 07:27:29.841584 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
395 07:27:29.842003 cs0 DataBus test pass
396 07:27:29.847249 cs1 DataBus test pass
397 07:27:29.847668 cs0 AddrBus test pass
398 07:27:29.848106 cs1 AddrBus test pass
399 07:27:29.848504
400 07:27:29.852780 100bdlr_step_size ps== 420
401 07:27:29.853243 result report
402 07:27:29.858437 boot times 0Enable ddr reg access
403 07:27:29.863841 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
404 07:27:29.877361 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
405 07:27:30.451287 0.0;M3 CHK:0;cm4_sp_mode 0
406 07:27:30.451861 MVN_1=0x00000000
407 07:27:30.456646 MVN_2=0x00000000
408 07:27:30.462414 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
409 07:27:30.462844 OPS=0x10
410 07:27:30.463250 ring efuse init
411 07:27:30.463647 chipver efuse init
412 07:27:30.468000 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
413 07:27:30.473639 [0.018961 Inits done]
414 07:27:30.474060 secure task start!
415 07:27:30.474465 high task start!
416 07:27:30.478277 low task start!
417 07:27:30.478707 run into bl31
418 07:27:30.484803 NOTICE: BL31: v1.3(release):4fc40b1
419 07:27:30.492792 NOTICE: BL31: Built : 15:58:17, May 22 2019
420 07:27:30.493239 NOTICE: BL31: G12A normal boot!
421 07:27:30.518672 NOTICE: BL31: BL33 decompress pass
422 07:27:30.524204 ERROR: Error initializing runtime service opteed_fast
423 07:27:31.757094
424 07:27:31.757689
425 07:27:31.764654 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
426 07:27:31.765094
427 07:27:31.765509 Model: Libre Computer AML-A311D-CC Alta
428 07:27:31.974034 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
429 07:27:31.997334 DRAM: 2 GiB (effective 3.8 GiB)
430 07:27:32.140274 Core: 408 devices, 31 uclasses, devicetree: separate
431 07:27:32.146154 WDT: Not starting watchdog@f0d0
432 07:27:32.178443 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
433 07:27:32.190874 Loading Environment from FAT... Card did not respond to voltage select! : -110
434 07:27:32.195844 ** Bad device specification mmc 0 **
435 07:27:32.206181 Card did not respond to voltage select! : -110
436 07:27:32.213861 ** Bad device specification mmc 0 **
437 07:27:32.214302 Couldn't find partition mmc 0
438 07:27:32.222199 Card did not respond to voltage select! : -110
439 07:27:32.227645 ** Bad device specification mmc 0 **
440 07:27:32.228093 Couldn't find partition mmc 0
441 07:27:32.232709 Error: could not access storage.
442 07:27:33.494851 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.�!,K��х��}���с0x01
443 07:27:33.495284 bl2_stage_init 0x81
444 07:27:33.500346 hw id: 0x0000 - pwm id 0x01
445 07:27:33.500631 bl2_stage_init 0xc1
446 07:27:33.500879 bl2_stage_init 0x02
447 07:27:33.501110
448 07:27:33.506106 L0:00000000
449 07:27:33.506501 L1:20000703
450 07:27:33.506827 L2:00008067
451 07:27:33.507178 L3:14000000
452 07:27:33.507487 B2:00402000
453 07:27:33.511693 B1:e0f83180
454 07:27:33.512100
455 07:27:33.512420 TE: 58150
456 07:27:33.512773
457 07:27:33.517204 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
458 07:27:33.517593
459 07:27:33.517913 Board ID = 1
460 07:27:33.522882 Set A53 clk to 24M
461 07:27:33.523255 Set A73 clk to 24M
462 07:27:33.523534 Set clk81 to 24M
463 07:27:33.528421 A53 clk: 1200 MHz
464 07:27:33.528792 A73 clk: 1200 MHz
465 07:27:33.529109 CLK81: 166.6M
466 07:27:33.529416 smccc: 00012aab
467 07:27:33.534084 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
468 07:27:33.539702 board id: 1
469 07:27:33.545428 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
470 07:27:33.556089 fw parse done
471 07:27:33.561894 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
472 07:27:33.604515 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
473 07:27:33.615409 PIEI prepare done
474 07:27:33.615715 fastboot data load
475 07:27:33.615951 fastboot data verify
476 07:27:33.621038 verify result: 266
477 07:27:33.626584 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
478 07:27:33.626883 LPDDR4 probe
479 07:27:33.627122 ddr clk to 1584MHz
480 07:27:33.634590 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
481 07:27:33.671856
482 07:27:33.672417 dmc_version 0001
483 07:27:33.678503 Check phy result
484 07:27:33.684369 INFO : End of CA training
485 07:27:33.684678 INFO : End of initialization
486 07:27:33.689977 INFO : Training has run successfully!
487 07:27:33.690308 Check phy result
488 07:27:33.695583 INFO : End of initialization
489 07:27:33.695959 INFO : End of read enable training
490 07:27:33.701161 INFO : End of fine write leveling
491 07:27:33.706925 INFO : End of Write leveling coarse delay
492 07:27:33.707225 INFO : Training has run successfully!
493 07:27:33.707465 Check phy result
494 07:27:33.712339 INFO : End of initialization
495 07:27:33.712617 INFO : End of read dq deskew training
496 07:27:33.717975 INFO : End of MPR read delay center optimization
497 07:27:33.723573 INFO : End of write delay center optimization
498 07:27:33.729187 INFO : End of read delay center optimization
499 07:27:33.729486 INFO : End of max read latency training
500 07:27:33.734920 INFO : Training has run successfully!
501 07:27:33.735202 1D training succeed
502 07:27:33.743956 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
503 07:27:33.791579 Check phy result
504 07:27:33.792055 INFO : End of initialization
505 07:27:33.813261 INFO : End of 2D read delay Voltage center optimization
506 07:27:33.833139 INFO : End of 2D read delay Voltage center optimization
507 07:27:33.885203 INFO : End of 2D write delay Voltage center optimization
508 07:27:33.934398 INFO : End of 2D write delay Voltage center optimization
509 07:27:33.940013 INFO : Training has run successfully!
510 07:27:33.940294
511 07:27:33.940537 channel==0
512 07:27:33.945558 RxClkDly_Margin_A0==88 ps 9
513 07:27:33.945832 TxDqDly_Margin_A0==98 ps 10
514 07:27:33.948964 RxClkDly_Margin_A1==88 ps 9
515 07:27:33.949238 TxDqDly_Margin_A1==98 ps 10
516 07:27:33.954585 TrainedVREFDQ_A0==74
517 07:27:33.954926 TrainedVREFDQ_A1==75
518 07:27:33.955171 VrefDac_Margin_A0==24
519 07:27:33.960088 DeviceVref_Margin_A0==40
520 07:27:33.960413 VrefDac_Margin_A1==25
521 07:27:33.965721 DeviceVref_Margin_A1==39
522 07:27:33.966006
523 07:27:33.966248
524 07:27:33.966486 channel==1
525 07:27:33.966720 RxClkDly_Margin_A0==98 ps 10
526 07:27:33.969028 TxDqDly_Margin_A0==98 ps 10
527 07:27:33.974668 RxClkDly_Margin_A1==98 ps 10
528 07:27:33.975088 TxDqDly_Margin_A1==88 ps 9
529 07:27:33.975424 TrainedVREFDQ_A0==77
530 07:27:33.980251 TrainedVREFDQ_A1==77
531 07:27:33.980653 VrefDac_Margin_A0==22
532 07:27:33.985978 DeviceVref_Margin_A0==37
533 07:27:33.986366 VrefDac_Margin_A1==22
534 07:27:33.986644 DeviceVref_Margin_A1==37
535 07:27:33.986997
536 07:27:33.991473 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
537 07:27:33.991838
538 07:27:34.025027 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000018 00000018 00000016 00000018 00000015 00000018 00000019 00000017 00000019 00000018 00000019 0000001a 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
539 07:27:34.025497 2D training succeed
540 07:27:34.030650 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
541 07:27:34.036273 auto size-- 65535DDR cs0 size: 2048MB
542 07:27:34.036679 DDR cs1 size: 2048MB
543 07:27:34.042051 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
544 07:27:34.042680 cs0 DataBus test pass
545 07:27:34.043173 cs1 DataBus test pass
546 07:27:34.047592 cs0 AddrBus test pass
547 07:27:34.048201 cs1 AddrBus test pass
548 07:27:34.048660
549 07:27:34.053236 100bdlr_step_size ps== 420
550 07:27:34.053848 result report
551 07:27:34.054356 boot times 0Enable ddr reg access
552 07:27:34.063147 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
553 07:27:34.076627 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
554 07:27:34.648650 0.0;M3 CHK:0;cm4_sp_mode 0
555 07:27:34.649325 MVN_1=0x00000000
556 07:27:34.654182 MVN_2=0x00000000
557 07:27:34.659887 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
558 07:27:34.660473 OPS=0x10
559 07:27:34.660924 ring efuse init
560 07:27:34.661359 chipver efuse init
561 07:27:34.665459 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
562 07:27:34.671140 [0.018961 Inits done]
563 07:27:34.671656 secure task start!
564 07:27:34.672212 high task start!
565 07:27:34.675683 low task start!
566 07:27:34.676245 run into bl31
567 07:27:34.682298 NOTICE: BL31: v1.3(release):4fc40b1
568 07:27:34.690279 NOTICE: BL31: Built : 15:58:17, May 22 2019
569 07:27:34.690830 NOTICE: BL31: G12A normal boot!
570 07:27:34.715458 NOTICE: BL31: BL33 decompress pass
571 07:27:34.721210 ERROR: Error initializing runtime service opteed_fast
572 07:27:35.954025
573 07:27:35.954438
574 07:27:35.962280 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
575 07:27:35.962596
576 07:27:35.962817 Model: Libre Computer AML-A311D-CC Alta
577 07:27:36.169878 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
578 07:27:36.193314 DRAM: 2 GiB (effective 3.8 GiB)
579 07:27:36.337159 Core: 408 devices, 31 uclasses, devicetree: separate
580 07:27:36.343038 WDT: Not starting watchdog@f0d0
581 07:27:36.376203 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
582 07:27:36.387755 Loading Environment from FAT... Card did not respond to voltage select! : -110
583 07:27:36.392676 ** Bad device specification mmc 0 **
584 07:27:36.403011 Card did not respond to voltage select! : -110
585 07:27:36.410674 ** Bad device specification mmc 0 **
586 07:27:36.411175 Couldn't find partition mmc 0
587 07:27:36.419083 Card did not respond to voltage select! : -110
588 07:27:36.424599 ** Bad device specification mmc 0 **
589 07:27:36.425083 Couldn't find partition mmc 0
590 07:27:36.429619 Error: could not access storage.
591 07:27:36.772234 Net: eth0: ethernet@ff3f0000
592 07:27:36.772657 starting USB...
593 07:27:37.024099 Bus usb@ff500000: Register 3000140 NbrPorts 3
594 07:27:37.024736 Starting the controller
595 07:27:37.030900 USB XHCI 1.10
596 07:27:38.743547 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
597 07:27:38.744244 bl2_stage_init 0x01
598 07:27:38.744729 bl2_stage_init 0x81
599 07:27:38.749114 hw id: 0x0000 - pwm id 0x01
600 07:27:38.749611 bl2_stage_init 0xc1
601 07:27:38.750072 bl2_stage_init 0x02
602 07:27:38.750521
603 07:27:38.754471 L0:00000000
604 07:27:38.754963 L1:20000703
605 07:27:38.755419 L2:00008067
606 07:27:38.755867 L3:14000000
607 07:27:38.757300 B2:00402000
608 07:27:38.757944 B1:e0f83180
609 07:27:38.758411
610 07:27:38.758854 TE: 58124
611 07:27:38.759298
612 07:27:38.768357 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
613 07:27:38.768860
614 07:27:38.769314 Board ID = 1
615 07:27:38.769754 Set A53 clk to 24M
616 07:27:38.770191 Set A73 clk to 24M
617 07:27:38.774081 Set clk81 to 24M
618 07:27:38.774573 A53 clk: 1200 MHz
619 07:27:38.775022 A73 clk: 1200 MHz
620 07:27:38.777427 CLK81: 166.6M
621 07:27:38.777903 smccc: 00012a92
622 07:27:38.783004 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
623 07:27:38.788653 board id: 1
624 07:27:38.793334 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
625 07:27:38.804540 fw parse done
626 07:27:38.809463 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
627 07:27:38.852197 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
628 07:27:38.863976 PIEI prepare done
629 07:27:38.864512 fastboot data load
630 07:27:38.864977 fastboot data verify
631 07:27:38.869664 verify result: 266
632 07:27:38.875308 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
633 07:27:38.875827 LPDDR4 probe
634 07:27:38.876322 ddr clk to 1584MHz
635 07:27:38.882201 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
636 07:27:38.919503
637 07:27:38.920090 dmc_version 0001
638 07:27:38.926773 Check phy result
639 07:27:38.932990 INFO : End of CA training
640 07:27:38.933481 INFO : End of initialization
641 07:27:38.938675 INFO : Training has run successfully!
642 07:27:38.939167 Check phy result
643 07:27:38.944210 INFO : End of initialization
644 07:27:38.944695 INFO : End of read enable training
645 07:27:38.949796 INFO : End of fine write leveling
646 07:27:38.955375 INFO : End of Write leveling coarse delay
647 07:27:38.955860 INFO : Training has run successfully!
648 07:27:38.956355 Check phy result
649 07:27:38.961020 INFO : End of initialization
650 07:27:38.961509 INFO : End of read dq deskew training
651 07:27:38.966729 INFO : End of MPR read delay center optimization
652 07:27:38.972273 INFO : End of write delay center optimization
653 07:27:38.977819 INFO : End of read delay center optimization
654 07:27:38.978354 INFO : End of max read latency training
655 07:27:38.983450 INFO : Training has run successfully!
656 07:27:38.983944 1D training succeed
657 07:27:38.991812 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
658 07:27:39.039824 Check phy result
659 07:27:39.040451 INFO : End of initialization
660 07:27:39.060954 INFO : End of 2D read delay Voltage center optimization
661 07:27:39.082027 INFO : End of 2D read delay Voltage center optimization
662 07:27:39.133340 INFO : End of 2D write delay Voltage center optimization
663 07:27:39.183719 INFO : End of 2D write delay Voltage center optimization
664 07:27:39.189154 INFO : Training has run successfully!
665 07:27:39.189660
666 07:27:39.190117 channel==0
667 07:27:39.194728 RxClkDly_Margin_A0==88 ps 9
668 07:27:39.195220 TxDqDly_Margin_A0==98 ps 10
669 07:27:39.200364 RxClkDly_Margin_A1==88 ps 9
670 07:27:39.200868 TxDqDly_Margin_A1==98 ps 10
671 07:27:39.201342 TrainedVREFDQ_A0==74
672 07:27:39.205939 TrainedVREFDQ_A1==75
673 07:27:39.206463 VrefDac_Margin_A0==25
674 07:27:39.206904 DeviceVref_Margin_A0==40
675 07:27:39.211620 VrefDac_Margin_A1==25
676 07:27:39.212133 DeviceVref_Margin_A1==39
677 07:27:39.212572
678 07:27:39.213006
679 07:27:39.217102 channel==1
680 07:27:39.217577 RxClkDly_Margin_A0==98 ps 10
681 07:27:39.218016 TxDqDly_Margin_A0==98 ps 10
682 07:27:39.222848 RxClkDly_Margin_A1==88 ps 9
683 07:27:39.223325 TxDqDly_Margin_A1==98 ps 10
684 07:27:39.228336 TrainedVREFDQ_A0==77
685 07:27:39.228817 TrainedVREFDQ_A1==78
686 07:27:39.229256 VrefDac_Margin_A0==23
687 07:27:39.233938 DeviceVref_Margin_A0==37
688 07:27:39.234426 VrefDac_Margin_A1==24
689 07:27:39.239548 DeviceVref_Margin_A1==36
690 07:27:39.240049
691 07:27:39.240495 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
692 07:27:39.245136
693 07:27:39.273114 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000018 00000019 00000017 00000019 00000018 00000019 0000001a 00000018 00000017 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
694 07:27:39.273681 2D training succeed
695 07:27:39.278763 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
696 07:27:39.284335 auto size-- 65535DDR cs0 size: 2048MB
697 07:27:39.284818 DDR cs1 size: 2048MB
698 07:27:39.289940 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
699 07:27:39.290406 cs0 DataBus test pass
700 07:27:39.295637 cs1 DataBus test pass
701 07:27:39.296151 cs0 AddrBus test pass
702 07:27:39.296588 cs1 AddrBus test pass
703 07:27:39.297018
704 07:27:39.301122 100bdlr_step_size ps== 420
705 07:27:39.301608 result report
706 07:27:39.306763 boot times 0Enable ddr reg access
707 07:27:39.312223 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
708 07:27:39.324860 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
709 07:27:39.899337 0.0;M3 CHK:0;cm4_sp_mode 0
710 07:27:39.900051 MVN_1=0x00000000
711 07:27:39.904795 MVN_2=0x00000000
712 07:27:39.910523 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
713 07:27:39.911079 OPS=0x10
714 07:27:39.911561 ring efuse init
715 07:27:39.912078 chipver efuse init
716 07:27:39.916164 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
717 07:27:39.921763 [0.018961 Inits done]
718 07:27:39.922285 secure task start!
719 07:27:39.922754 high task start!
720 07:27:39.925408 low task start!
721 07:27:39.925915 run into bl31
722 07:27:39.933041 NOTICE: BL31: v1.3(release):4fc40b1
723 07:27:39.940404 NOTICE: BL31: Built : 15:58:17, May 22 2019
724 07:27:39.940933 NOTICE: BL31: G12A normal boot!
725 07:27:39.966204 NOTICE: BL31: BL33 decompress pass
726 07:27:39.971799 ERROR: Error initializing runtime service opteed_fast
727 07:27:41.204749
728 07:27:41.205401
729 07:27:41.213164 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
730 07:27:41.213679
731 07:27:41.214146 Model: Libre Computer AML-A311D-CC Alta
732 07:27:41.421766 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
733 07:27:41.445188 DRAM: 2 GiB (effective 3.8 GiB)
734 07:27:41.588220 Core: 408 devices, 31 uclasses, devicetree: separate
735 07:27:41.593884 WDT: Not starting watchdog@f0d0
736 07:27:41.626117 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
737 07:27:41.638594 Loading Environment from FAT... Card did not respond to voltage select! : -110
738 07:27:41.643464 ** Bad device specification mmc 0 **
739 07:27:41.653889 Card did not respond to voltage select! : -110
740 07:27:41.661592 ** Bad device specification mmc 0 **
741 07:27:41.662100 Couldn't find partition mmc 0
742 07:27:41.669871 Card did not respond to voltage select! : -110
743 07:27:41.675295 ** Bad device specification mmc 0 **
744 07:27:41.675760 Couldn't find partition mmc 0
745 07:27:41.679470 Error: could not access storage.
746 07:27:42.024050 Net: eth0: ethernet@ff3f0000
747 07:27:42.024670 starting USB...
748 07:27:42.276125 Bus usb@ff500000: Register 3000140 NbrPorts 3
749 07:27:42.276726 Starting the controller
750 07:27:42.284059 USB XHCI 1.10
751 07:27:44.443728 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
752 07:27:44.444389 bl2_stage_init 0x01
753 07:27:44.444818 bl2_stage_init 0x81
754 07:27:44.449085 hw id: 0x0000 - pwm id 0x01
755 07:27:44.449562 bl2_stage_init 0xc1
756 07:27:44.449984 bl2_stage_init 0x02
757 07:27:44.450391
758 07:27:44.454658 L0:00000000
759 07:27:44.455128 L1:20000703
760 07:27:44.455543 L2:00008067
761 07:27:44.455944 L3:14000000
762 07:27:44.460331 B2:00402000
763 07:27:44.460798 B1:e0f83180
764 07:27:44.461207
765 07:27:44.461616 TE: 58159
766 07:27:44.462018
767 07:27:44.465971 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
768 07:27:44.466501
769 07:27:44.466955 Board ID = 1
770 07:27:44.471562 Set A53 clk to 24M
771 07:27:44.472086 Set A73 clk to 24M
772 07:27:44.472511 Set clk81 to 24M
773 07:27:44.477195 A53 clk: 1200 MHz
774 07:27:44.477634 A73 clk: 1200 MHz
775 07:27:44.478038 CLK81: 166.6M
776 07:27:44.478433 smccc: 00012ab5
777 07:27:44.482629 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
778 07:27:44.488289 board id: 1
779 07:27:44.494104 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
780 07:27:44.504769 fw parse done
781 07:27:44.510727 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
782 07:27:44.553258 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
783 07:27:44.564224 PIEI prepare done
784 07:27:44.564680 fastboot data load
785 07:27:44.565098 fastboot data verify
786 07:27:44.569843 verify result: 266
787 07:27:44.575515 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
788 07:27:44.575955 LPDDR4 probe
789 07:27:44.576416 ddr clk to 1584MHz
790 07:27:44.583439 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
791 07:27:44.620716
792 07:27:44.621254 dmc_version 0001
793 07:27:44.627364 Check phy result
794 07:27:44.633296 INFO : End of CA training
795 07:27:44.633737 INFO : End of initialization
796 07:27:44.638848 INFO : Training has run successfully!
797 07:27:44.639343 Check phy result
798 07:27:44.645130 INFO : End of initialization
799 07:27:44.645634 INFO : End of read enable training
800 07:27:44.647722 INFO : End of fine write leveling
801 07:27:44.653224 INFO : End of Write leveling coarse delay
802 07:27:44.658981 INFO : Training has run successfully!
803 07:27:44.659416 Check phy result
804 07:27:44.659820 INFO : End of initialization
805 07:27:44.664684 INFO : End of read dq deskew training
806 07:27:44.667944 INFO : End of MPR read delay center optimization
807 07:27:44.673471 INFO : End of write delay center optimization
808 07:27:44.679105 INFO : End of read delay center optimization
809 07:27:44.679558 INFO : End of max read latency training
810 07:27:44.684712 INFO : Training has run successfully!
811 07:27:44.685162 1D training succeed
812 07:27:44.692890 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
813 07:27:44.739872 Check phy result
814 07:27:44.740449 INFO : End of initialization
815 07:27:44.762189 INFO : End of 2D read delay Voltage center optimization
816 07:27:44.782388 INFO : End of 2D read delay Voltage center optimization
817 07:27:44.834519 INFO : End of 2D write delay Voltage center optimization
818 07:27:44.883780 INFO : End of 2D write delay Voltage center optimization
819 07:27:44.889331 INFO : Training has run successfully!
820 07:27:44.889779
821 07:27:44.890196 channel==0
822 07:27:44.895089 RxClkDly_Margin_A0==88 ps 9
823 07:27:44.895564 TxDqDly_Margin_A0==98 ps 10
824 07:27:44.900692 RxClkDly_Margin_A1==88 ps 9
825 07:27:44.901190 TxDqDly_Margin_A1==98 ps 10
826 07:27:44.901629 TrainedVREFDQ_A0==74
827 07:27:44.906246 TrainedVREFDQ_A1==74
828 07:27:44.906747 VrefDac_Margin_A0==25
829 07:27:44.907164 DeviceVref_Margin_A0==40
830 07:27:44.911971 VrefDac_Margin_A1==25
831 07:27:44.912468 DeviceVref_Margin_A1==40
832 07:27:44.912862
833 07:27:44.913249
834 07:27:44.917339 channel==1
835 07:27:44.917770 RxClkDly_Margin_A0==98 ps 10
836 07:27:44.918161 TxDqDly_Margin_A0==98 ps 10
837 07:27:44.923058 RxClkDly_Margin_A1==98 ps 10
838 07:27:44.923523 TxDqDly_Margin_A1==88 ps 9
839 07:27:44.928634 TrainedVREFDQ_A0==77
840 07:27:44.929061 TrainedVREFDQ_A1==77
841 07:27:44.929451 VrefDac_Margin_A0==22
842 07:27:44.934262 DeviceVref_Margin_A0==37
843 07:27:44.934673 VrefDac_Margin_A1==23
844 07:27:44.939807 DeviceVref_Margin_A1==37
845 07:27:44.940269
846 07:27:44.940662 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
847 07:27:44.945531
848 07:27:44.973344 soc_vref_reg_value 0x 00000019 00000019 00000018 00000019 00000018 00000019 00000018 00000018 00000018 00000016 00000017 00000015 00000018 00000019 00000018 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
849 07:27:44.973830 2D training succeed
850 07:27:44.978914 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
851 07:27:44.984561 auto size-- 65535DDR cs0 size: 2048MB
852 07:27:44.985036 DDR cs1 size: 2048MB
853 07:27:44.990149 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
854 07:27:44.990572 cs0 DataBus test pass
855 07:27:44.995712 cs1 DataBus test pass
856 07:27:44.996164 cs0 AddrBus test pass
857 07:27:44.996557 cs1 AddrBus test pass
858 07:27:44.996943
859 07:27:45.001367 100bdlr_step_size ps== 420
860 07:27:45.001834 result report
861 07:27:45.006981 boot times 0Enable ddr reg access
862 07:27:45.012381 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
863 07:27:45.025884 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
864 07:27:45.599664 0.0;M3 CHK:0;cm4_sp_mode 0
865 07:27:45.600311 MVN_1=0x00000000
866 07:27:45.605055 MVN_2=0x00000000
867 07:27:45.611043 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
868 07:27:45.611524 OPS=0x10
869 07:27:45.611944 ring efuse init
870 07:27:45.612394 chipver efuse init
871 07:27:45.616450 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
872 07:27:45.622100 [0.018961 Inits done]
873 07:27:45.622533 secure task start!
874 07:27:45.622939 high task start!
875 07:27:45.626863 low task start!
876 07:27:45.627308 run into bl31
877 07:27:45.633316 NOTICE: BL31: v1.3(release):4fc40b1
878 07:27:45.641056 NOTICE: BL31: Built : 15:58:17, May 22 2019
879 07:27:45.641497 NOTICE: BL31: G12A normal boot!
880 07:27:45.666437 NOTICE: BL31: BL33 decompress pass
881 07:27:45.672288 ERROR: Error initializing runtime service opteed_fast
882 07:27:46.905033
883 07:27:46.905656
884 07:27:46.913389 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
885 07:27:46.913853
886 07:27:46.914296 Model: Libre Computer AML-A311D-CC Alta
887 07:27:47.121139 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
888 07:27:47.145197 DRAM: 2 GiB (effective 3.8 GiB)
889 07:27:47.521145 Core: 408 devices, 31 uclasses, devicetree: separate
890 07:27:47.521577 WDT: Not starting watchdog@f0d0
891 07:27:47.521803 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
892 07:27:47.522016 Loading Environment from FAT... Card did not respond to voltage select! : -110
893 07:27:47.522226 ** Bad device specification mmc 0 **
894 07:27:47.522434 Card did not respond to voltage select! : -110
895 07:27:47.522639 ** Bad device specification mmc 0 **
896 07:27:47.522846 Couldn't find partition mmc 0
897 07:27:47.523044 Card did not respond to voltage select! : -110
898 07:27:47.523272 ** Bad device specification mmc 0 **
899 07:27:47.523476 Couldn't find partition mmc 0
900 07:27:47.524013 Error: could not access storage.
901 07:27:47.723204 Net: eth0: ethernet@ff3f0000
902 07:27:47.723884 starting USB...
903 07:27:47.975073 Bus usb@ff500000: Register 3000140 NbrPorts 3
904 07:27:47.975714 Starting the controller
905 07:27:47.981960 USB XHCI 1.10
906 07:27:49.844190 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
907 07:27:49.844832 bl2_stage_init 0x01
908 07:27:49.845298 bl2_stage_init 0x81
909 07:27:49.849677 hw id: 0x0000 - pwm id 0x01
910 07:27:49.850216 bl2_stage_init 0xc1
911 07:27:49.850686 bl2_stage_init 0x02
912 07:27:49.851143
913 07:27:49.855254 L0:00000000
914 07:27:49.855769 L1:20000703
915 07:27:49.856279 L2:00008067
916 07:27:49.856733 L3:14000000
917 07:27:49.860886 B2:00402000
918 07:27:49.861397 B1:e0f83180
919 07:27:49.861854
920 07:27:49.862304 TE: 58159
921 07:27:49.862754
922 07:27:49.866469 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
923 07:27:49.866980
924 07:27:49.867441 Board ID = 1
925 07:27:49.872030 Set A53 clk to 24M
926 07:27:49.872551 Set A73 clk to 24M
927 07:27:49.873029 Set clk81 to 24M
928 07:27:49.877708 A53 clk: 1200 MHz
929 07:27:49.878245 A73 clk: 1200 MHz
930 07:27:49.878700 CLK81: 166.6M
931 07:27:49.879181 smccc: 00012ab5
932 07:27:49.883304 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
933 07:27:49.888862 board id: 1
934 07:27:49.894770 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
935 07:27:49.905394 fw parse done
936 07:27:49.911429 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
937 07:27:49.954139 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
938 07:27:49.964870 PIEI prepare done
939 07:27:49.965366 fastboot data load
940 07:27:49.965808 fastboot data verify
941 07:27:49.970569 verify result: 266
942 07:27:49.976235 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
943 07:27:49.976739 LPDDR4 probe
944 07:27:49.977169 ddr clk to 1584MHz
945 07:27:49.984263 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
946 07:27:50.021406
947 07:27:50.021963 dmc_version 0001
948 07:27:50.028117 Check phy result
949 07:27:50.033929 INFO : End of CA training
950 07:27:50.034426 INFO : End of initialization
951 07:27:50.039541 INFO : Training has run successfully!
952 07:27:50.040077 Check phy result
953 07:27:50.045198 INFO : End of initialization
954 07:27:50.045739 INFO : End of read enable training
955 07:27:50.048500 INFO : End of fine write leveling
956 07:27:50.053994 INFO : End of Write leveling coarse delay
957 07:27:50.059611 INFO : Training has run successfully!
958 07:27:50.060149 Check phy result
959 07:27:50.060602 INFO : End of initialization
960 07:27:50.065218 INFO : End of read dq deskew training
961 07:27:50.068612 INFO : End of MPR read delay center optimization
962 07:27:50.074222 INFO : End of write delay center optimization
963 07:27:50.079796 INFO : End of read delay center optimization
964 07:27:50.080334 INFO : End of max read latency training
965 07:27:50.086141 INFO : Training has run successfully!
966 07:27:50.086644 1D training succeed
967 07:27:50.092619 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
968 07:27:50.141243 Check phy result
969 07:27:50.141768 INFO : End of initialization
970 07:27:50.163667 INFO : End of 2D read delay Voltage center optimization
971 07:27:50.184067 INFO : End of 2D read delay Voltage center optimization
972 07:27:50.236061 INFO : End of 2D write delay Voltage center optimization
973 07:27:50.285394 INFO : End of 2D write delay Voltage center optimization
974 07:27:50.290955 INFO : Training has run successfully!
975 07:27:50.291466
976 07:27:50.291924 channel==0
977 07:27:50.296571 RxClkDly_Margin_A0==88 ps 9
978 07:27:50.297069 TxDqDly_Margin_A0==98 ps 10
979 07:27:50.302234 RxClkDly_Margin_A1==88 ps 9
980 07:27:50.302731 TxDqDly_Margin_A1==98 ps 10
981 07:27:50.303176 TrainedVREFDQ_A0==74
982 07:27:50.307756 TrainedVREFDQ_A1==74
983 07:27:50.308304 VrefDac_Margin_A0==25
984 07:27:50.308744 DeviceVref_Margin_A0==40
985 07:27:50.313327 VrefDac_Margin_A1==24
986 07:27:50.313826 DeviceVref_Margin_A1==40
987 07:27:50.314257
988 07:27:50.314690
989 07:27:50.318905 channel==1
990 07:27:50.319404 RxClkDly_Margin_A0==88 ps 9
991 07:27:50.319841 TxDqDly_Margin_A0==98 ps 10
992 07:27:50.324546 RxClkDly_Margin_A1==88 ps 9
993 07:27:50.325048 TxDqDly_Margin_A1==88 ps 9
994 07:27:50.330257 TrainedVREFDQ_A0==77
995 07:27:50.330765 TrainedVREFDQ_A1==77
996 07:27:50.331205 VrefDac_Margin_A0==22
997 07:27:50.335747 DeviceVref_Margin_A0==37
998 07:27:50.336286 VrefDac_Margin_A1==24
999 07:27:50.341373 DeviceVref_Margin_A1==37
1000 07:27:50.341896
1001 07:27:50.342336 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
1002 07:27:50.342770
1003 07:27:50.374911 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000019 00000017 00000019 00000018 0000001a 0000001a 00000018 00000016 00000018 00000017 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
1004 07:27:50.375530 2D training succeed
1005 07:27:50.380545 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
1006 07:27:50.386239 auto size-- 65535DDR cs0 size: 2048MB
1007 07:27:50.386792 DDR cs1 size: 2048MB
1008 07:27:50.391790 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
1009 07:27:50.392358 cs0 DataBus test pass
1010 07:27:50.397403 cs1 DataBus test pass
1011 07:27:50.397926 cs0 AddrBus test pass
1012 07:27:50.398387 cs1 AddrBus test pass
1013 07:27:50.398840
1014 07:27:50.402967 100bdlr_step_size ps== 420
1015 07:27:50.403498 result report
1016 07:27:50.408542 boot times 0Enable ddr reg access
1017 07:27:50.413814 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
1018 07:27:50.427272 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
1019 07:27:51.001026 0.0;M3 CHK:0;cm4_sp_mode 0
1020 07:27:51.001702 MVN_1=0x00000000
1021 07:27:51.006549 MVN_2=0x00000000
1022 07:27:51.012403 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
1023 07:27:51.012924 OPS=0x10
1024 07:27:51.013393 ring efuse init
1025 07:27:51.013847 chipver efuse init
1026 07:27:51.020635 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
1027 07:27:51.021366 [0.018961 Inits done]
1028 07:27:51.021846 secure task start!
1029 07:27:51.028119 high task start!
1030 07:27:51.028682 low task start!
1031 07:27:51.029145 run into bl31
1032 07:27:51.034713 NOTICE: BL31: v1.3(release):4fc40b1
1033 07:27:51.042615 NOTICE: BL31: Built : 15:58:17, May 22 2019
1034 07:27:51.043153 NOTICE: BL31: G12A normal boot!
1035 07:27:51.068026 NOTICE: BL31: BL33 decompress pass
1036 07:27:51.073601 ERROR: Error initializing runtime service opteed_fast
1037 07:27:52.306605
1038 07:27:52.307251
1039 07:27:52.314982 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
1040 07:27:52.315526
1041 07:27:52.316023 Model: Libre Computer AML-A311D-CC Alta
1042 07:27:52.523380 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
1043 07:27:52.546735 DRAM: 2 GiB (effective 3.8 GiB)
1044 07:27:52.689671 Core: 408 devices, 31 uclasses, devicetree: separate
1045 07:27:52.695001 WDT: Not starting watchdog@f0d0
1046 07:27:52.727939 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
1047 07:27:52.740456 Loading Environment from FAT... Card did not respond to voltage select! : -110
1048 07:27:52.745456 ** Bad device specification mmc 0 **
1049 07:27:52.755638 Card did not respond to voltage select! : -110
1050 07:27:52.763185 ** Bad device specification mmc 0 **
1051 07:27:52.763701 Couldn't find partition mmc 0
1052 07:27:52.771575 Card did not respond to voltage select! : -110
1053 07:27:52.777128 ** Bad device specification mmc 0 **
1054 07:27:52.777631 Couldn't find partition mmc 0
1055 07:27:52.782219 Error: could not access storage.
1056 07:27:53.124856 Net: eth0: ethernet@ff3f0000
1057 07:27:53.125516 starting USB...
1058 07:27:53.376595 Bus usb@ff500000: Register 3000140 NbrPorts 3
1059 07:27:53.377260 Starting the controller
1060 07:27:53.383886 USB XHCI 1.10
1061 07:27:54.937569 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
1062 07:27:54.945946 scanning usb for storage devices... 0 Storage Device(s) found
1064 07:27:54.997642 Hit any key to stop autoboot: 1
1065 07:27:54.998494 end: 2.4.2 bootloader-interrupt (duration 00:00:37) [common]
1066 07:27:54.999187 start: 2.4.3 bootloader-commands (timeout 00:04:23) [common]
1067 07:27:54.999701 Setting prompt string to ['=>']
1068 07:27:55.000285 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:23)
1069 07:27:55.013332 0
1070 07:27:55.014273 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1071 07:27:55.014801 Sending with 10 millisecond of delay
1073 07:27:56.150000 => setenv autoload no
1074 07:27:56.160862 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:22)
1075 07:27:56.166279 setenv autoload no
1076 07:27:56.167071 Sending with 10 millisecond of delay
1078 07:27:57.964533 => setenv initrd_high 0xffffffff
1079 07:27:57.975515 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:20)
1080 07:27:57.976151 setenv initrd_high 0xffffffff
1081 07:27:57.976680 Sending with 10 millisecond of delay
1083 07:27:59.596098 => setenv fdt_high 0xffffffff
1084 07:27:59.606898 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1085 07:27:59.607777 setenv fdt_high 0xffffffff
1086 07:27:59.608591 Sending with 10 millisecond of delay
1088 07:27:59.900530 => dhcp
1089 07:27:59.911333 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1090 07:27:59.912231 dhcp
1091 07:27:59.912713 Speed: 1000, full duplex
1092 07:27:59.913175 BOOTP broadcast 1
1093 07:28:00.045161 DHCP client bound to address 192.168.6.27 (134 ms)
1094 07:28:00.046006 Sending with 10 millisecond of delay
1096 07:28:01.723203 => setenv serverip 192.168.6.2
1097 07:28:01.734053 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:16)
1098 07:28:01.734996 setenv serverip 192.168.6.2
1099 07:28:01.735777 Sending with 10 millisecond of delay
1101 07:28:05.460350 => tftpboot 0x01080000 978419/tftp-deploy-5p14solb/kernel/uImage
1102 07:28:05.471230 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:12)
1103 07:28:05.472224 tftpboot 0x01080000 978419/tftp-deploy-5p14solb/kernel/uImage
1104 07:28:05.472706 Speed: 1000, full duplex
1105 07:28:05.473149 Using ethernet@ff3f0000 device
1106 07:28:05.474315 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1107 07:28:05.480089 Filename '978419/tftp-deploy-5p14solb/kernel/uImage'.
1108 07:28:05.484081 Load address: 0x1080000
1109 07:28:09.834251 Loading: *#################################################
1110 07:28:09.834892 TFTP error: trying to overwrite reserved memory...
1112 07:28:09.836445 end: 2.4.3 bootloader-commands (duration 00:00:15) [common]
1115 07:28:09.838458 end: 2.4 uboot-commands (duration 00:00:52) [common]
1117 07:28:09.839965 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'TFTP error: trying to overwrite reserved memory' (12)'
1119 07:28:09.841157 end: 2 uboot-action (duration 00:00:52) [common]
1121 07:28:09.842866 Cleaning after the job
1122 07:28:09.843480 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/978419/tftp-deploy-5p14solb/ramdisk
1123 07:28:09.863332 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/978419/tftp-deploy-5p14solb/kernel
1124 07:28:09.895053 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/978419/tftp-deploy-5p14solb/dtb
1125 07:28:09.895892 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/978419/tftp-deploy-5p14solb/modules
1126 07:28:09.924904 start: 4.1 power-off (timeout 00:00:30) [common]
1127 07:28:09.925589 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1128 07:28:09.956757 >> OK - accepted request
1129 07:28:09.958436 Returned 0 in 0 seconds
1130 07:28:10.059168 end: 4.1 power-off (duration 00:00:00) [common]
1132 07:28:10.060173 start: 4.2 read-feedback (timeout 00:10:00) [common]
1133 07:28:10.060828 Listened to connection for namespace 'common' for up to 1s
1134 07:28:11.061847 Finalising connection for namespace 'common'
1135 07:28:11.062571 Disconnecting from shell: Finalise
1136 07:28:11.063128 =>
1137 07:28:11.164230 end: 4.2 read-feedback (duration 00:00:01) [common]
1138 07:28:11.164932 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/978419
1139 07:28:11.525641 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/978419
1140 07:28:11.526255 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.