Boot log: meson-sm1-s905d3-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 07:24:54.024056 lava-dispatcher, installed at version: 2024.01
2 07:24:54.024875 start: 0 validate
3 07:24:54.025361 Start time: 2024-11-12 07:24:54.025331+00:00 (UTC)
4 07:24:54.025929 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 07:24:54.026479 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230703.0%2Farm64%2Frootfs.cpio.gz exists
6 07:24:54.065652 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 07:24:54.066249 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241112%2Farm64%2Fdefconfig%2Bkselftest%2Fgcc-12%2Fkernel%2FImage exists
8 07:24:54.095946 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 07:24:54.096651 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241112%2Farm64%2Fdefconfig%2Bkselftest%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-sm1-s905d3-libretech-cc.dtb exists
10 07:24:55.143086 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 07:24:55.143578 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241112%2Farm64%2Fdefconfig%2Bkselftest%2Fgcc-12%2Fmodules.tar.xz exists
12 07:24:55.184462 validate duration: 1.16
14 07:24:55.185322 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 07:24:55.185658 start: 1.1 download-retry (timeout 00:10:00) [common]
16 07:24:55.185970 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 07:24:55.186577 Not decompressing ramdisk as can be used compressed.
18 07:24:55.187001 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230703.0/arm64/rootfs.cpio.gz
19 07:24:55.187273 saving as /var/lib/lava/dispatcher/tmp/978415/tftp-deploy-ul4i6lnw/ramdisk/rootfs.cpio.gz
20 07:24:55.187546 total size: 8181887 (7 MB)
21 07:24:55.225371 progress 0 % (0 MB)
22 07:24:55.236197 progress 5 % (0 MB)
23 07:24:55.246265 progress 10 % (0 MB)
24 07:24:55.256692 progress 15 % (1 MB)
25 07:24:55.262136 progress 20 % (1 MB)
26 07:24:55.267623 progress 25 % (1 MB)
27 07:24:55.272766 progress 30 % (2 MB)
28 07:24:55.278260 progress 35 % (2 MB)
29 07:24:55.283376 progress 40 % (3 MB)
30 07:24:55.288907 progress 45 % (3 MB)
31 07:24:55.293990 progress 50 % (3 MB)
32 07:24:55.299570 progress 55 % (4 MB)
33 07:24:55.304682 progress 60 % (4 MB)
34 07:24:55.310175 progress 65 % (5 MB)
35 07:24:55.315421 progress 70 % (5 MB)
36 07:24:55.320877 progress 75 % (5 MB)
37 07:24:55.325978 progress 80 % (6 MB)
38 07:24:55.331428 progress 85 % (6 MB)
39 07:24:55.336519 progress 90 % (7 MB)
40 07:24:55.342036 progress 95 % (7 MB)
41 07:24:55.346857 progress 100 % (7 MB)
42 07:24:55.347544 7 MB downloaded in 0.16 s (48.78 MB/s)
43 07:24:55.348107 end: 1.1.1 http-download (duration 00:00:00) [common]
45 07:24:55.349008 end: 1.1 download-retry (duration 00:00:00) [common]
46 07:24:55.349299 start: 1.2 download-retry (timeout 00:10:00) [common]
47 07:24:55.349570 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 07:24:55.350051 downloading http://storage.kernelci.org/next/master/next-20241112/arm64/defconfig+kselftest/gcc-12/kernel/Image
49 07:24:55.350297 saving as /var/lib/lava/dispatcher/tmp/978415/tftp-deploy-ul4i6lnw/kernel/Image
50 07:24:55.350504 total size: 66982400 (63 MB)
51 07:24:55.350714 No compression specified
52 07:24:55.384767 progress 0 % (0 MB)
53 07:24:55.424780 progress 5 % (3 MB)
54 07:24:55.464971 progress 10 % (6 MB)
55 07:24:55.505293 progress 15 % (9 MB)
56 07:24:55.544745 progress 20 % (12 MB)
57 07:24:55.585017 progress 25 % (16 MB)
58 07:24:55.624343 progress 30 % (19 MB)
59 07:24:55.663995 progress 35 % (22 MB)
60 07:24:55.703121 progress 40 % (25 MB)
61 07:24:55.742524 progress 45 % (28 MB)
62 07:24:55.782835 progress 50 % (31 MB)
63 07:24:55.822524 progress 55 % (35 MB)
64 07:24:55.862396 progress 60 % (38 MB)
65 07:24:55.902269 progress 65 % (41 MB)
66 07:24:55.941892 progress 70 % (44 MB)
67 07:24:55.982132 progress 75 % (47 MB)
68 07:24:56.021774 progress 80 % (51 MB)
69 07:24:56.061425 progress 85 % (54 MB)
70 07:24:56.101277 progress 90 % (57 MB)
71 07:24:56.140658 progress 95 % (60 MB)
72 07:24:56.179894 progress 100 % (63 MB)
73 07:24:56.180479 63 MB downloaded in 0.83 s (76.97 MB/s)
74 07:24:56.180960 end: 1.2.1 http-download (duration 00:00:01) [common]
76 07:24:56.181772 end: 1.2 download-retry (duration 00:00:01) [common]
77 07:24:56.182045 start: 1.3 download-retry (timeout 00:09:59) [common]
78 07:24:56.182307 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 07:24:56.182764 downloading http://storage.kernelci.org/next/master/next-20241112/arm64/defconfig+kselftest/gcc-12/dtbs/amlogic/meson-sm1-s905d3-libretech-cc.dtb
80 07:24:56.183054 saving as /var/lib/lava/dispatcher/tmp/978415/tftp-deploy-ul4i6lnw/dtb/meson-sm1-s905d3-libretech-cc.dtb
81 07:24:56.183264 total size: 53209 (0 MB)
82 07:24:56.183472 No compression specified
83 07:24:56.218563 progress 61 % (0 MB)
84 07:24:56.219404 progress 100 % (0 MB)
85 07:24:56.219932 0 MB downloaded in 0.04 s (1.38 MB/s)
86 07:24:56.220433 end: 1.3.1 http-download (duration 00:00:00) [common]
88 07:24:56.221251 end: 1.3 download-retry (duration 00:00:00) [common]
89 07:24:56.221511 start: 1.4 download-retry (timeout 00:09:59) [common]
90 07:24:56.221771 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 07:24:56.222219 downloading http://storage.kernelci.org/next/master/next-20241112/arm64/defconfig+kselftest/gcc-12/modules.tar.xz
92 07:24:56.222455 saving as /var/lib/lava/dispatcher/tmp/978415/tftp-deploy-ul4i6lnw/modules/modules.tar
93 07:24:56.222658 total size: 16284560 (15 MB)
94 07:24:56.222864 Using unxz to decompress xz
95 07:24:56.257490 progress 0 % (0 MB)
96 07:24:56.357948 progress 5 % (0 MB)
97 07:24:56.471047 progress 10 % (1 MB)
98 07:24:56.592249 progress 15 % (2 MB)
99 07:24:56.721140 progress 20 % (3 MB)
100 07:24:56.863593 progress 25 % (3 MB)
101 07:24:56.974167 progress 30 % (4 MB)
102 07:24:57.079534 progress 35 % (5 MB)
103 07:24:57.192492 progress 40 % (6 MB)
104 07:24:57.299105 progress 45 % (7 MB)
105 07:24:57.416414 progress 50 % (7 MB)
106 07:24:57.529833 progress 55 % (8 MB)
107 07:24:57.646735 progress 60 % (9 MB)
108 07:24:57.760109 progress 65 % (10 MB)
109 07:24:57.869990 progress 70 % (10 MB)
110 07:24:57.988721 progress 75 % (11 MB)
111 07:24:58.105133 progress 80 % (12 MB)
112 07:24:58.220222 progress 85 % (13 MB)
113 07:24:58.335208 progress 90 % (14 MB)
114 07:24:58.442603 progress 95 % (14 MB)
115 07:24:58.556934 progress 100 % (15 MB)
116 07:24:58.571942 15 MB downloaded in 2.35 s (6.61 MB/s)
117 07:24:58.572662 end: 1.4.1 http-download (duration 00:00:02) [common]
119 07:24:58.573567 end: 1.4 download-retry (duration 00:00:02) [common]
120 07:24:58.573857 start: 1.5 prepare-tftp-overlay (timeout 00:09:57) [common]
121 07:24:58.574145 start: 1.5.1 extract-nfsrootfs (timeout 00:09:57) [common]
122 07:24:58.574428 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 07:24:58.574691 start: 1.5.2 lava-overlay (timeout 00:09:57) [common]
124 07:24:58.575408 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/978415/lava-overlay-wgw6sr5p
125 07:24:58.575958 makedir: /var/lib/lava/dispatcher/tmp/978415/lava-overlay-wgw6sr5p/lava-978415/bin
126 07:24:58.576453 makedir: /var/lib/lava/dispatcher/tmp/978415/lava-overlay-wgw6sr5p/lava-978415/tests
127 07:24:58.576874 makedir: /var/lib/lava/dispatcher/tmp/978415/lava-overlay-wgw6sr5p/lava-978415/results
128 07:24:58.577259 Creating /var/lib/lava/dispatcher/tmp/978415/lava-overlay-wgw6sr5p/lava-978415/bin/lava-add-keys
129 07:24:58.578626 Creating /var/lib/lava/dispatcher/tmp/978415/lava-overlay-wgw6sr5p/lava-978415/bin/lava-add-sources
130 07:24:58.580168 Creating /var/lib/lava/dispatcher/tmp/978415/lava-overlay-wgw6sr5p/lava-978415/bin/lava-background-process-start
131 07:24:58.581809 Creating /var/lib/lava/dispatcher/tmp/978415/lava-overlay-wgw6sr5p/lava-978415/bin/lava-background-process-stop
132 07:24:58.583588 Creating /var/lib/lava/dispatcher/tmp/978415/lava-overlay-wgw6sr5p/lava-978415/bin/lava-common-functions
133 07:24:58.585842 Creating /var/lib/lava/dispatcher/tmp/978415/lava-overlay-wgw6sr5p/lava-978415/bin/lava-echo-ipv4
134 07:24:58.587147 Creating /var/lib/lava/dispatcher/tmp/978415/lava-overlay-wgw6sr5p/lava-978415/bin/lava-install-packages
135 07:24:58.588928 Creating /var/lib/lava/dispatcher/tmp/978415/lava-overlay-wgw6sr5p/lava-978415/bin/lava-installed-packages
136 07:24:58.590643 Creating /var/lib/lava/dispatcher/tmp/978415/lava-overlay-wgw6sr5p/lava-978415/bin/lava-os-build
137 07:24:58.591590 Creating /var/lib/lava/dispatcher/tmp/978415/lava-overlay-wgw6sr5p/lava-978415/bin/lava-probe-channel
138 07:24:58.592576 Creating /var/lib/lava/dispatcher/tmp/978415/lava-overlay-wgw6sr5p/lava-978415/bin/lava-probe-ip
139 07:24:58.593179 Creating /var/lib/lava/dispatcher/tmp/978415/lava-overlay-wgw6sr5p/lava-978415/bin/lava-target-ip
140 07:24:58.593869 Creating /var/lib/lava/dispatcher/tmp/978415/lava-overlay-wgw6sr5p/lava-978415/bin/lava-target-mac
141 07:24:58.594477 Creating /var/lib/lava/dispatcher/tmp/978415/lava-overlay-wgw6sr5p/lava-978415/bin/lava-target-storage
142 07:24:58.595070 Creating /var/lib/lava/dispatcher/tmp/978415/lava-overlay-wgw6sr5p/lava-978415/bin/lava-test-case
143 07:24:58.595712 Creating /var/lib/lava/dispatcher/tmp/978415/lava-overlay-wgw6sr5p/lava-978415/bin/lava-test-event
144 07:24:58.596347 Creating /var/lib/lava/dispatcher/tmp/978415/lava-overlay-wgw6sr5p/lava-978415/bin/lava-test-feedback
145 07:24:58.596959 Creating /var/lib/lava/dispatcher/tmp/978415/lava-overlay-wgw6sr5p/lava-978415/bin/lava-test-raise
146 07:24:58.597571 Creating /var/lib/lava/dispatcher/tmp/978415/lava-overlay-wgw6sr5p/lava-978415/bin/lava-test-reference
147 07:24:58.598196 Creating /var/lib/lava/dispatcher/tmp/978415/lava-overlay-wgw6sr5p/lava-978415/bin/lava-test-runner
148 07:24:58.598815 Creating /var/lib/lava/dispatcher/tmp/978415/lava-overlay-wgw6sr5p/lava-978415/bin/lava-test-set
149 07:24:58.599435 Creating /var/lib/lava/dispatcher/tmp/978415/lava-overlay-wgw6sr5p/lava-978415/bin/lava-test-shell
150 07:24:58.600149 Updating /var/lib/lava/dispatcher/tmp/978415/lava-overlay-wgw6sr5p/lava-978415/bin/lava-install-packages (oe)
151 07:24:58.601487 Updating /var/lib/lava/dispatcher/tmp/978415/lava-overlay-wgw6sr5p/lava-978415/bin/lava-installed-packages (oe)
152 07:24:58.602127 Creating /var/lib/lava/dispatcher/tmp/978415/lava-overlay-wgw6sr5p/lava-978415/environment
153 07:24:58.602740 LAVA metadata
154 07:24:58.603132 - LAVA_JOB_ID=978415
155 07:24:58.603383 - LAVA_DISPATCHER_IP=192.168.6.2
156 07:24:58.603821 start: 1.5.2.1 ssh-authorize (timeout 00:09:57) [common]
157 07:24:58.605071 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 07:24:58.605477 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:57) [common]
159 07:24:58.605707 skipped lava-vland-overlay
160 07:24:58.605962 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 07:24:58.606226 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:57) [common]
162 07:24:58.606460 skipped lava-multinode-overlay
163 07:24:58.606720 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 07:24:58.606990 start: 1.5.2.4 test-definition (timeout 00:09:57) [common]
165 07:24:58.607267 Loading test definitions
166 07:24:58.607586 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:57) [common]
167 07:24:58.607836 Using /lava-978415 at stage 0
168 07:24:58.609311 uuid=978415_1.5.2.4.1 testdef=None
169 07:24:58.609716 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 07:24:58.610023 start: 1.5.2.4.2 test-overlay (timeout 00:09:57) [common]
171 07:24:58.612278 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 07:24:58.613186 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:57) [common]
174 07:24:58.615792 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 07:24:58.616742 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:57) [common]
177 07:24:58.619239 runner path: /var/lib/lava/dispatcher/tmp/978415/lava-overlay-wgw6sr5p/lava-978415/0/tests/0_dmesg test_uuid 978415_1.5.2.4.1
178 07:24:58.619959 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 07:24:58.620894 Creating lava-test-runner.conf files
181 07:24:58.621130 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/978415/lava-overlay-wgw6sr5p/lava-978415/0 for stage 0
182 07:24:58.621725 - 0_dmesg
183 07:24:58.622297 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 07:24:58.622667 start: 1.5.2.5 compress-overlay (timeout 00:09:57) [common]
185 07:24:58.650173 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 07:24:58.650662 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:57) [common]
187 07:24:58.650959 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 07:24:58.651255 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 07:24:58.651560 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:57) [common]
190 07:24:59.581369 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
191 07:24:59.581846 start: 1.5.4 extract-modules (timeout 00:09:56) [common]
192 07:24:59.582094 extracting modules file /var/lib/lava/dispatcher/tmp/978415/tftp-deploy-ul4i6lnw/modules/modules.tar to /var/lib/lava/dispatcher/tmp/978415/extract-overlay-ramdisk-ka_iu8wk/ramdisk
193 07:25:01.104829 end: 1.5.4 extract-modules (duration 00:00:02) [common]
194 07:25:01.105333 start: 1.5.5 apply-overlay-tftp (timeout 00:09:54) [common]
195 07:25:01.105614 [common] Applying overlay /var/lib/lava/dispatcher/tmp/978415/compress-overlay-s6vymyc_/overlay-1.5.2.5.tar.gz to ramdisk
196 07:25:01.105826 [common] Applying overlay /var/lib/lava/dispatcher/tmp/978415/compress-overlay-s6vymyc_/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/978415/extract-overlay-ramdisk-ka_iu8wk/ramdisk
197 07:25:01.135699 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 07:25:01.136137 start: 1.5.6 prepare-kernel (timeout 00:09:54) [common]
199 07:25:01.136411 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:54) [common]
200 07:25:01.136637 Converting downloaded kernel to a uImage
201 07:25:01.136943 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/978415/tftp-deploy-ul4i6lnw/kernel/Image /var/lib/lava/dispatcher/tmp/978415/tftp-deploy-ul4i6lnw/kernel/uImage
202 07:25:01.919568 output: Image Name:
203 07:25:01.920036 output: Created: Tue Nov 12 07:25:01 2024
204 07:25:01.920251 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 07:25:01.920455 output: Data Size: 66982400 Bytes = 65412.50 KiB = 63.88 MiB
206 07:25:01.920655 output: Load Address: 01080000
207 07:25:01.920854 output: Entry Point: 01080000
208 07:25:01.921051 output:
209 07:25:01.921391 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:01) [common]
210 07:25:01.921661 end: 1.5.6 prepare-kernel (duration 00:00:01) [common]
211 07:25:01.921933 start: 1.5.7 configure-preseed-file (timeout 00:09:53) [common]
212 07:25:01.922188 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 07:25:01.922447 start: 1.5.8 compress-ramdisk (timeout 00:09:53) [common]
214 07:25:01.922720 Building ramdisk /var/lib/lava/dispatcher/tmp/978415/extract-overlay-ramdisk-ka_iu8wk/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/978415/extract-overlay-ramdisk-ka_iu8wk/ramdisk
215 07:25:05.224791 >> 258323 blocks
216 07:25:16.422098 Adding RAMdisk u-boot header.
217 07:25:16.422540 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/978415/extract-overlay-ramdisk-ka_iu8wk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/978415/extract-overlay-ramdisk-ka_iu8wk/ramdisk.cpio.gz.uboot
218 07:25:16.784411 output: Image Name:
219 07:25:16.784836 output: Created: Tue Nov 12 07:25:16 2024
220 07:25:16.785042 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 07:25:16.785244 output: Data Size: 33949621 Bytes = 33153.93 KiB = 32.38 MiB
222 07:25:16.785444 output: Load Address: 00000000
223 07:25:16.785643 output: Entry Point: 00000000
224 07:25:16.785842 output:
225 07:25:16.786501 rename /var/lib/lava/dispatcher/tmp/978415/extract-overlay-ramdisk-ka_iu8wk/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/978415/tftp-deploy-ul4i6lnw/ramdisk/ramdisk.cpio.gz.uboot
226 07:25:16.787217 end: 1.5.8 compress-ramdisk (duration 00:00:15) [common]
227 07:25:16.787821 end: 1.5 prepare-tftp-overlay (duration 00:00:18) [common]
228 07:25:16.788485 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:38) [common]
229 07:25:16.788990 No LXC device requested
230 07:25:16.789571 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 07:25:16.790131 start: 1.7 deploy-device-env (timeout 00:09:38) [common]
232 07:25:16.790677 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 07:25:16.791139 Checking files for TFTP limit of 4294967296 bytes.
234 07:25:16.794015 end: 1 tftp-deploy (duration 00:00:22) [common]
235 07:25:16.794668 start: 2 uboot-action (timeout 00:05:00) [common]
236 07:25:16.795240 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 07:25:16.795744 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 07:25:16.796374 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 07:25:16.796941 Using kernel file from prepare-kernel: 978415/tftp-deploy-ul4i6lnw/kernel/uImage
240 07:25:16.797592 substitutions:
241 07:25:16.798032 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 07:25:16.798444 - {DTB_ADDR}: 0x01070000
243 07:25:16.798878 - {DTB}: 978415/tftp-deploy-ul4i6lnw/dtb/meson-sm1-s905d3-libretech-cc.dtb
244 07:25:16.799292 - {INITRD}: 978415/tftp-deploy-ul4i6lnw/ramdisk/ramdisk.cpio.gz.uboot
245 07:25:16.799695 - {KERNEL_ADDR}: 0x01080000
246 07:25:16.800159 - {KERNEL}: 978415/tftp-deploy-ul4i6lnw/kernel/uImage
247 07:25:16.800584 - {LAVA_MAC}: None
248 07:25:16.801035 - {PRESEED_CONFIG}: None
249 07:25:16.801481 - {PRESEED_LOCAL}: None
250 07:25:16.801889 - {RAMDISK_ADDR}: 0x08000000
251 07:25:16.802286 - {RAMDISK}: 978415/tftp-deploy-ul4i6lnw/ramdisk/ramdisk.cpio.gz.uboot
252 07:25:16.802713 - {ROOT_PART}: None
253 07:25:16.803124 - {ROOT}: None
254 07:25:16.803516 - {SERVER_IP}: 192.168.6.2
255 07:25:16.803943 - {TEE_ADDR}: 0x83000000
256 07:25:16.804393 - {TEE}: None
257 07:25:16.804789 Parsed boot commands:
258 07:25:16.805207 - setenv autoload no
259 07:25:16.805615 - setenv initrd_high 0xffffffff
260 07:25:16.806005 - setenv fdt_high 0xffffffff
261 07:25:16.806421 - dhcp
262 07:25:16.806834 - setenv serverip 192.168.6.2
263 07:25:16.807223 - tftpboot 0x01080000 978415/tftp-deploy-ul4i6lnw/kernel/uImage
264 07:25:16.807627 - tftpboot 0x08000000 978415/tftp-deploy-ul4i6lnw/ramdisk/ramdisk.cpio.gz.uboot
265 07:25:16.808068 - tftpboot 0x01070000 978415/tftp-deploy-ul4i6lnw/dtb/meson-sm1-s905d3-libretech-cc.dtb
266 07:25:16.808474 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 07:25:16.808880 - bootm 0x01080000 0x08000000 0x01070000
268 07:25:16.809424 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 07:25:16.810975 start: 2.3 connect-device (timeout 00:05:00) [common]
271 07:25:16.811443 [common] connect-device Connecting to device using 'telnet conserv1 3008'
272 07:25:16.826163 Setting prompt string to ['lava-test: # ']
273 07:25:16.827694 end: 2.3 connect-device (duration 00:00:00) [common]
274 07:25:16.828399 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 07:25:16.829034 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 07:25:16.829558 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 07:25:16.830739 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=solitude-01'
278 07:25:16.866993 >> OK - accepted request
279 07:25:16.869100 Returned 0 in 0 seconds
280 07:25:16.970321 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
282 07:25:16.971957 end: 2.4.1 reset-device (duration 00:00:00) [common]
283 07:25:16.972576 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
284 07:25:16.973090 Setting prompt string to ['Hit any key to stop autoboot']
285 07:25:16.973542 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 07:25:16.975099 Trying 192.168.56.21...
287 07:25:16.975562 Connected to conserv1.
288 07:25:16.975974 Escape character is '^]'.
289 07:25:16.976427
290 07:25:16.976854 ser2net port telnet,3008 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.3.3:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
291 07:25:16.977266
292 07:25:24.377884 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
293 07:25:24.378273 bl2_stage_init 0x01
294 07:25:24.378494 bl2_stage_init 0x81
295 07:25:24.383550 hw id: 0x0000 - pwm id 0x01
296 07:25:24.383893 bl2_stage_init 0xc1
297 07:25:24.389039 bl2_stage_init 0x02
298 07:25:24.389572
299 07:25:24.390045 L0:00000000
300 07:25:24.390499 L1:00000703
301 07:25:24.390942 L2:00008067
302 07:25:24.391382 L3:15000000
303 07:25:24.394626 S1:00000000
304 07:25:24.395104 B2:20282000
305 07:25:24.395542 B1:a0f83180
306 07:25:24.395969
307 07:25:24.396438 TE: 70230
308 07:25:24.396868
309 07:25:24.400276 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
310 07:25:24.400762
311 07:25:24.405840 Board ID = 1
312 07:25:24.406315 Set cpu clk to 24M
313 07:25:24.406747 Set clk81 to 24M
314 07:25:24.411486 Use GP1_pll as DSU clk.
315 07:25:24.412085 DSU clk: 1200 Mhz
316 07:25:24.412525 CPU clk: 1200 MHz
317 07:25:24.417070 Set clk81 to 166.6M
318 07:25:24.422635 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
319 07:25:24.423110 board id: 1
320 07:25:24.429887 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
321 07:25:24.440541 fw parse done
322 07:25:24.446472 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
323 07:25:24.489173 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
324 07:25:24.500111 PIEI prepare done
325 07:25:24.500587 fastboot data load
326 07:25:24.501024 fastboot data verify
327 07:25:24.505600 verify result: 266
328 07:25:24.511239 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
329 07:25:24.511816 LPDDR4 probe
330 07:25:24.512305 ddr clk to 1584MHz
331 07:25:24.519550 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
332 07:25:24.556648
333 07:25:24.557237 dmc_version 0001
334 07:25:24.563182 Check phy result
335 07:25:24.569035 INFO : End of CA training
336 07:25:24.569514 INFO : End of initialization
337 07:25:24.574583 INFO : Training has run successfully!
338 07:25:24.575049 Check phy result
339 07:25:24.580178 INFO : End of initialization
340 07:25:24.580653 INFO : End of read enable training
341 07:25:24.585784 INFO : End of fine write leveling
342 07:25:24.591397 INFO : End of Write leveling coarse delay
343 07:25:24.591862 INFO : Training has run successfully!
344 07:25:24.592351 Check phy result
345 07:25:24.597046 INFO : End of initialization
346 07:25:24.597511 INFO : End of read dq deskew training
347 07:25:24.602565 INFO : End of MPR read delay center optimization
348 07:25:24.608161 INFO : End of write delay center optimization
349 07:25:24.613832 INFO : End of read delay center optimization
350 07:25:24.614406 INFO : End of max read latency training
351 07:25:24.619405 INFO : Training has run successfully!
352 07:25:24.619886 1D training succeed
353 07:25:24.628542 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
354 07:25:24.675508 Check phy result
355 07:25:24.676165 INFO : End of initialization
356 07:25:24.698576 INFO : End of 2D read delay Voltage center optimization
357 07:25:24.716850 INFO : End of 2D read delay Voltage center optimization
358 07:25:24.769583 INFO : End of 2D write delay Voltage center optimization
359 07:25:24.818990 INFO : End of 2D write delay Voltage center optimization
360 07:25:24.824266 INFO : Training has run successfully!
361 07:25:24.824777
362 07:25:24.825216 channel==0
363 07:25:24.829856 RxClkDly_Margin_A0==78 ps 8
364 07:25:24.830347 TxDqDly_Margin_A0==98 ps 10
365 07:25:24.835472 RxClkDly_Margin_A1==88 ps 9
366 07:25:24.835938 TxDqDly_Margin_A1==88 ps 9
367 07:25:24.836427 TrainedVREFDQ_A0==76
368 07:25:24.841091 TrainedVREFDQ_A1==74
369 07:25:24.841564 VrefDac_Margin_A0==24
370 07:25:24.841993 DeviceVref_Margin_A0==38
371 07:25:24.846681 VrefDac_Margin_A1==23
372 07:25:24.847144 DeviceVref_Margin_A1==40
373 07:25:24.847577
374 07:25:24.848036
375 07:25:24.848469 channel==1
376 07:25:24.852280 RxClkDly_Margin_A0==88 ps 9
377 07:25:24.852754 TxDqDly_Margin_A0==98 ps 10
378 07:25:24.857879 RxClkDly_Margin_A1==78 ps 8
379 07:25:24.858346 TxDqDly_Margin_A1==98 ps 10
380 07:25:24.863504 TrainedVREFDQ_A0==78
381 07:25:24.863973 TrainedVREFDQ_A1==78
382 07:25:24.864433 VrefDac_Margin_A0==22
383 07:25:24.869072 DeviceVref_Margin_A0==36
384 07:25:24.869541 VrefDac_Margin_A1==22
385 07:25:24.874660 DeviceVref_Margin_A1==36
386 07:25:24.875123
387 07:25:24.875559 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
388 07:25:24.876018
389 07:25:24.908267 soc_vref_reg_value 0x 00000019 00000018 00000019 00000017 00000019 00000015 00000018 00000016 00000017 00000017 00000017 00000017 00000017 00000018 00000018 00000019 00000018 00000017 00000018 00000015 00000018 00000015 00000015 00000017 00000018 00000019 00000017 00000018 0000001c 00000017 00000016 00000016 dram_vref_reg_value 0x 00000060
390 07:25:24.908901 2D training succeed
391 07:25:24.913966 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
392 07:25:24.919479 auto size-- 65535DDR cs0 size: 2048MB
393 07:25:24.920087 DDR cs1 size: 2048MB
394 07:25:24.925111 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
395 07:25:24.925672 cs0 DataBus test pass
396 07:25:24.930934 cs1 DataBus test pass
397 07:25:24.931528 cs0 AddrBus test pass
398 07:25:24.932016 cs1 AddrBus test pass
399 07:25:24.932490
400 07:25:24.936274 100bdlr_step_size ps== 478
401 07:25:24.936854 result report
402 07:25:24.941897 boot times 0Enable ddr reg access
403 07:25:24.947185 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
404 07:25:24.961013 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
405 07:25:25.616059 bl2z: ptr: 05129330, size: 00001e40
406 07:25:25.624333 0.0;M3 CHK:0;cm4_sp_mode 0
407 07:25:25.624661 MVN_1=0x00000000
408 07:25:25.624875 MVN_2=0x00000000
409 07:25:25.635934 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
410 07:25:25.636303 OPS=0x04
411 07:25:25.636532 ring efuse init
412 07:25:25.641558 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
413 07:25:25.641842 [0.017310 Inits done]
414 07:25:25.642055 secure task start!
415 07:25:25.649255 high task start!
416 07:25:25.649551 low task start!
417 07:25:25.649765 run into bl31
418 07:25:25.657745 NOTICE: BL31: v1.3(release):4fc40b1
419 07:25:25.665579 NOTICE: BL31: Built : 15:57:33, May 22 2019
420 07:25:25.665905 NOTICE: BL31: G12A normal boot!
421 07:25:25.681186 NOTICE: BL31: BL33 decompress pass
422 07:25:25.686870 ERROR: Error initializing runtime service opteed_fast
423 07:25:28.427645 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0; SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
424 07:25:28.428121 bl2_stage_init 0x01
425 07:25:28.428338 bl2_stage_init 0x81
426 07:25:28.433178 hw id: 0x0000 - pwm id 0x01
427 07:25:28.433472 bl2_stage_init 0xc1
428 07:25:28.438366 bl2_stage_init 0x02
429 07:25:28.438672
430 07:25:28.438880 L0:00000000
431 07:25:28.439076 L1:00000703
432 07:25:28.439270 L2:00008067
433 07:25:28.443950 L3:15000000
434 07:25:28.444275 S1:00000000
435 07:25:28.444477 B2:20282000
436 07:25:28.444674 B1:a0f83180
437 07:25:28.444867
438 07:25:28.445060 TE: 68866
439 07:25:28.445253
440 07:25:28.449583 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
441 07:25:28.455167
442 07:25:28.455489 Board ID = 1
443 07:25:28.455704 Set cpu clk to 24M
444 07:25:28.455902 Set clk81 to 24M
445 07:25:28.460755 Use GP1_pll as DSU clk.
446 07:25:28.461056 DSU clk: 1200 Mhz
447 07:25:28.461258 CPU clk: 1200 MHz
448 07:25:28.466359 Set clk81 to 166.6M
449 07:25:28.471961 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
450 07:25:28.472293 board id: 1
451 07:25:28.479697 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
452 07:25:28.490426 fw parse done
453 07:25:28.496227 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
454 07:25:28.538913 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
455 07:25:28.549900 PIEI prepare done
456 07:25:28.550453 fastboot data load
457 07:25:28.550896 fastboot data verify
458 07:25:28.555477 verify result: 266
459 07:25:28.561017 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
460 07:25:28.561554 LPDDR4 probe
461 07:25:28.561953 ddr clk to 1584MHz
462 07:25:28.569093 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
463 07:25:28.606319
464 07:25:28.606908 dmc_version 0001
465 07:25:28.612904 Check phy result
466 07:25:28.618901 INFO : End of CA training
467 07:25:28.619484 INFO : End of initialization
468 07:25:28.624422 INFO : Training has run successfully!
469 07:25:28.624996 Check phy result
470 07:25:28.630050 INFO : End of initialization
471 07:25:28.630618 INFO : End of read enable training
472 07:25:28.635709 INFO : End of fine write leveling
473 07:25:28.641242 INFO : End of Write leveling coarse delay
474 07:25:28.641808 INFO : Training has run successfully!
475 07:25:28.642259 Check phy result
476 07:25:28.646844 INFO : End of initialization
477 07:25:28.647341 INFO : End of read dq deskew training
478 07:25:28.652408 INFO : End of MPR read delay center optimization
479 07:25:28.658023 INFO : End of write delay center optimization
480 07:25:28.663671 INFO : End of read delay center optimization
481 07:25:28.664233 INFO : End of max read latency training
482 07:25:28.669240 INFO : Training has run successfully!
483 07:25:28.669787 1D training succeed
484 07:25:28.678395 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
485 07:25:28.726229 Check phy result
486 07:25:28.726799 INFO : End of initialization
487 07:25:28.748359 INFO : End of 2D read delay Voltage center optimization
488 07:25:28.767573 INFO : End of 2D read delay Voltage center optimization
489 07:25:28.819402 INFO : End of 2D write delay Voltage center optimization
490 07:25:28.868750 INFO : End of 2D write delay Voltage center optimization
491 07:25:28.874131 INFO : Training has run successfully!
492 07:25:28.874608
493 07:25:28.875025 channel==0
494 07:25:28.879900 RxClkDly_Margin_A0==69 ps 7
495 07:25:28.880459 TxDqDly_Margin_A0==98 ps 10
496 07:25:28.885295 RxClkDly_Margin_A1==69 ps 7
497 07:25:28.885746 TxDqDly_Margin_A1==98 ps 10
498 07:25:28.886160 TrainedVREFDQ_A0==76
499 07:25:28.890881 TrainedVREFDQ_A1==75
500 07:25:28.891323 VrefDac_Margin_A0==23
501 07:25:28.891729 DeviceVref_Margin_A0==38
502 07:25:28.896530 VrefDac_Margin_A1==23
503 07:25:28.896973 DeviceVref_Margin_A1==39
504 07:25:28.897382
505 07:25:28.897781
506 07:25:28.902111 channel==1
507 07:25:28.902558 RxClkDly_Margin_A0==88 ps 9
508 07:25:28.902966 TxDqDly_Margin_A0==98 ps 10
509 07:25:28.907678 RxClkDly_Margin_A1==78 ps 8
510 07:25:28.908148 TxDqDly_Margin_A1==88 ps 9
511 07:25:28.913279 TrainedVREFDQ_A0==78
512 07:25:28.913718 TrainedVREFDQ_A1==77
513 07:25:28.914125 VrefDac_Margin_A0==22
514 07:25:28.918903 DeviceVref_Margin_A0==36
515 07:25:28.919341 VrefDac_Margin_A1==22
516 07:25:28.924511 DeviceVref_Margin_A1==37
517 07:25:28.924958
518 07:25:28.925366 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
519 07:25:28.925767
520 07:25:28.958107 soc_vref_reg_value 0x 00000019 00000018 00000018 00000016 00000018 00000014 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000017 00000017 00000018 00000019 00000017 00000018 00000015 00000018 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001c 00000017 00000015 00000017 dram_vref_reg_value 0x 00000061
521 07:25:28.958671 2D training succeed
522 07:25:28.963662 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
523 07:25:28.969265 auto size-- 65535DDR cs0 size: 2048MB
524 07:25:28.969713 DDR cs1 size: 2048MB
525 07:25:28.974874 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
526 07:25:28.975314 cs0 DataBus test pass
527 07:25:28.980446 cs1 DataBus test pass
528 07:25:28.980902 cs0 AddrBus test pass
529 07:25:28.981305 cs1 AddrBus test pass
530 07:25:28.981700
531 07:25:28.986112 100bdlr_step_size ps== 464
532 07:25:28.986735 result report
533 07:25:28.991716 boot times 0Enable ddr reg access
534 07:25:28.996929 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
535 07:25:29.010775 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
536 07:25:29.665913 bl2z: ptr: 05129330, size: 00001e40
537 07:25:29.673176 0.0;M3 CHK:0;cm4_sp_mode 0
538 07:25:29.673486 MVN_1=0x00000000
539 07:25:29.673700 MVN_2=0x00000000
540 07:25:29.684769 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
541 07:25:29.685162 OPS=0x04
542 07:25:29.685383 ring efuse init
543 07:25:29.687748 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
544 07:25:29.693930 [0.017319 Inits done]
545 07:25:29.694334 secure task start!
546 07:25:29.694580 high task start!
547 07:25:29.694802 low task start!
548 07:25:29.697746 run into bl31
549 07:25:29.706683 NOTICE: BL31: v1.3(release):4fc40b1
550 07:25:29.713734 NOTICE: BL31: Built : 15:57:33, May 22 2019
551 07:25:29.714091 NOTICE: BL31: G12A normal boot!
552 07:25:29.730141 NOTICE: BL31: BL33 decompress pass
553 07:25:29.735722 ERROR: Error initializing runtime service opteed_fast
554 07:25:31.129143 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
555 07:25:31.129833 bl2_stage_init 0x01
556 07:25:31.130318 bl2_stage_init 0x81
557 07:25:31.134720 hw id: 0x0000 - pwm id 0x01
558 07:25:31.135307 bl2_stage_init 0xc1
559 07:25:31.135783 bl2_stage_init 0x02
560 07:25:31.136307
561 07:25:31.140356 L0:00000000
562 07:25:31.140963 L1:00000703
563 07:25:31.141668 L2:00008067
564 07:25:31.142182 L3:15000000
565 07:25:31.142618 S1:00000000
566 07:25:31.143457 B2:20282000
567 07:25:31.147337 B1:a0f83180
568 07:25:31.147935
569 07:25:31.148462 TE: 70398
570 07:25:31.148915
571 07:25:31.153126 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
572 07:25:31.153771
573 07:25:31.154279 Board ID = 1
574 07:25:31.158616 Set cpu clk to 24M
575 07:25:31.159319 Set clk81 to 24M
576 07:25:31.159804 Use GP1_pll as DSU clk.
577 07:25:31.164354 DSU clk: 1200 Mhz
578 07:25:31.165088 CPU clk: 1200 MHz
579 07:25:31.165581 Set clk81 to 166.6M
580 07:25:31.169653 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
581 07:25:31.175354 board id: 1
582 07:25:31.180211 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
583 07:25:31.190859 fw parse done
584 07:25:31.196997 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
585 07:25:31.239582 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
586 07:25:31.250541 PIEI prepare done
587 07:25:31.251218 fastboot data load
588 07:25:31.251705 fastboot data verify
589 07:25:31.256199 verify result: 266
590 07:25:31.261558 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
591 07:25:31.261995 LPDDR4 probe
592 07:25:31.262491 ddr clk to 1584MHz
593 07:25:31.269689 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
594 07:25:31.307016
595 07:25:31.307682 dmc_version 0001
596 07:25:31.313580 Check phy result
597 07:25:31.319483 INFO : End of CA training
598 07:25:31.320132 INFO : End of initialization
599 07:25:31.325149 INFO : Training has run successfully!
600 07:25:31.325764 Check phy result
601 07:25:31.330629 INFO : End of initialization
602 07:25:31.331214 INFO : End of read enable training
603 07:25:31.336354 INFO : End of fine write leveling
604 07:25:31.342156 INFO : End of Write leveling coarse delay
605 07:25:31.342883 INFO : Training has run successfully!
606 07:25:31.343393 Check phy result
607 07:25:31.347909 INFO : End of initialization
608 07:25:31.348733 INFO : End of read dq deskew training
609 07:25:31.353152 INFO : End of MPR read delay center optimization
610 07:25:31.358627 INFO : End of write delay center optimization
611 07:25:31.364291 INFO : End of read delay center optimization
612 07:25:31.364941 INFO : End of max read latency training
613 07:25:31.369921 INFO : Training has run successfully!
614 07:25:31.370483 1D training succeed
615 07:25:31.378999 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
616 07:25:31.426654 Check phy result
617 07:25:31.427266 INFO : End of initialization
618 07:25:31.449035 INFO : End of 2D read delay Voltage center optimization
619 07:25:31.468196 INFO : End of 2D read delay Voltage center optimization
620 07:25:31.520046 INFO : End of 2D write delay Voltage center optimization
621 07:25:31.569280 INFO : End of 2D write delay Voltage center optimization
622 07:25:31.574752 INFO : Training has run successfully!
623 07:25:31.575270
624 07:25:31.575741 channel==0
625 07:25:31.580353 RxClkDly_Margin_A0==69 ps 7
626 07:25:31.580873 TxDqDly_Margin_A0==98 ps 10
627 07:25:31.585929 RxClkDly_Margin_A1==88 ps 9
628 07:25:31.586479 TxDqDly_Margin_A1==98 ps 10
629 07:25:31.586924 TrainedVREFDQ_A0==77
630 07:25:31.591583 TrainedVREFDQ_A1==74
631 07:25:31.592122 VrefDac_Margin_A0==25
632 07:25:31.592534 DeviceVref_Margin_A0==37
633 07:25:31.597187 VrefDac_Margin_A1==23
634 07:25:31.597676 DeviceVref_Margin_A1==40
635 07:25:31.598079
636 07:25:31.598477
637 07:25:31.602906 channel==1
638 07:25:31.604128 RxClkDly_Margin_A0==78 ps 8
639 07:25:31.604472 TxDqDly_Margin_A0==88 ps 9
640 07:25:31.608329 RxClkDly_Margin_A1==78 ps 8
641 07:25:31.608827 TxDqDly_Margin_A1==78 ps 8
642 07:25:31.613976 TrainedVREFDQ_A0==75
643 07:25:31.614486 TrainedVREFDQ_A1==77
644 07:25:31.614904 VrefDac_Margin_A0==22
645 07:25:31.619553 DeviceVref_Margin_A0==39
646 07:25:31.620112 VrefDac_Margin_A1==22
647 07:25:31.625225 DeviceVref_Margin_A1==37
648 07:25:31.625736
649 07:25:31.626136 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
650 07:25:31.626551
651 07:25:31.658758 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000016 00000017 00000017 00000017 00000017 00000017 00000018 00000017 00000019 00000018 00000017 00000018 00000015 00000017 00000014 00000015 00000016 00000018 00000019 00000017 00000018 0000001c 00000017 00000015 00000017 dram_vref_reg_value 0x 00000061
652 07:25:31.659354 2D training succeed
653 07:25:31.664368 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
654 07:25:31.669918 auto size-- 65535DDR cs0 size: 2048MB
655 07:25:31.670387 DDR cs1 size: 2048MB
656 07:25:31.675518 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
657 07:25:31.676009 cs0 DataBus test pass
658 07:25:31.681208 cs1 DataBus test pass
659 07:25:31.681692 cs0 AddrBus test pass
660 07:25:31.682081 cs1 AddrBus test pass
661 07:25:31.682468
662 07:25:31.686686 100bdlr_step_size ps== 478
663 07:25:31.687155 result report
664 07:25:31.692319 boot times 0Enable ddr reg access
665 07:25:31.697487 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
666 07:25:31.711285 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
667 07:25:32.366387 bl2z: ptr: 05129330, size: 00001e40
668 07:25:32.372719 0.0;M3 CHK:0;cm4_sp_mode 0
669 07:25:32.373235 MVN_1=0x00000000
670 07:25:32.373650 MVN_2=0x00000000
671 07:25:32.384374 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
672 07:25:32.384899 OPS=0x04
673 07:25:32.385313 ring efuse init
674 07:25:32.387067 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
675 07:25:32.392708 [0.017310 Inits done]
676 07:25:32.393177 secure task start!
677 07:25:32.393582 high task start!
678 07:25:32.393982 low task start!
679 07:25:32.396957 run into bl31
680 07:25:32.405446 NOTICE: BL31: v1.3(release):4fc40b1
681 07:25:32.413315 NOTICE: BL31: Built : 15:57:33, May 22 2019
682 07:25:32.413774 NOTICE: BL31: G12A normal boot!
683 07:25:32.428822 NOTICE: BL31: BL33 decompress pass
684 07:25:32.434461 ERROR: Error initializing runtime service opteed_fast
685 07:25:33.228724
686 07:25:33.229336
687 07:25:33.234131 U-Boot 2024.01-rc4+ (Dec 14 2023 - 02:26:00 -0500) Libre Computer AML-S905D3-CC
688 07:25:33.234594
689 07:25:33.237631 Model: Libre Computer AML-S905D3-CC Solitude
690 07:25:33.384552 SoC: Amlogic Meson SM1 (S905D3) Revision 2b:c (4:2)
691 07:25:33.399883 DRAM: 2 GiB (effective 3.8 GiB)
692 07:25:33.500842 Core: 406 devices, 33 uclasses, devicetree: separate
693 07:25:33.506629 WDT: Not starting watchdog@f0d0
694 07:25:33.531720 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
695 07:25:33.544032 Loading Environment from FAT... Card did not respond to voltage select! : -110
696 07:25:33.548903 ** Bad device specification mmc 0 **
697 07:25:33.558954 Card did not respond to voltage select! : -110
698 07:25:33.566648 ** Bad device specification mmc 0 **
699 07:25:33.567101 Couldn't find partition mmc 0
700 07:25:33.574932 Card did not respond to voltage select! : -110
701 07:25:33.580594 ** Bad device specification mmc 0 **
702 07:25:33.581033 Couldn't find partition mmc 0
703 07:25:33.585499 Error: could not access storage.
704 07:25:33.882247 Net: eth0: ethernet@ff3f0000
705 07:25:33.882840 starting USB...
706 07:25:34.126821 Bus usb@ff500000: Register 3000140 NbrPorts 3
707 07:25:34.127451 Starting the controller
708 07:25:34.132782 USB XHCI 1.10
709 07:25:35.689529 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
710 07:25:35.699139 scanning usb for storage devices... 0 Storage Device(s) found
712 07:25:35.750249 Hit any key to stop autoboot: 1
713 07:25:35.750899 end: 2.4.2 bootloader-interrupt (duration 00:00:19) [common]
714 07:25:35.751254 start: 2.4.3 bootloader-commands (timeout 00:04:41) [common]
715 07:25:35.751531 Setting prompt string to ['=>']
716 07:25:35.751830 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:41)
717 07:25:35.764019 0
718 07:25:35.764674 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
720 07:25:35.865474 => setenv autoload no
721 07:25:35.866198 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
722 07:25:35.870932 setenv autoload no
724 07:25:35.972126 => setenv initrd_high 0xffffffff
725 07:25:35.973616 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
726 07:25:35.977583 setenv initrd_high 0xffffffff
728 07:25:36.079024 => setenv fdt_high 0xffffffff
729 07:25:36.079789 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
730 07:25:36.084424 setenv fdt_high 0xffffffff
732 07:25:36.185899 => dhcp
733 07:25:36.186646 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
734 07:25:36.190023 dhcp
735 07:25:37.146768 ethernet@ff3f0000 Waiting for PHY auto negotiation to complete.. done
736 07:25:37.147384 Speed: 1000, full duplex
737 07:25:37.147790 BOOTP broadcast 1
738 07:25:37.394920 BOOTP broadcast 2
739 07:25:37.409072 DHCP client bound to address 192.168.6.21 (262 ms)
741 07:25:37.510515 => setenv serverip 192.168.6.2
742 07:25:37.511250 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:39)
743 07:25:37.516068 setenv serverip 192.168.6.2
745 07:25:37.617488 => tftpboot 0x01080000 978415/tftp-deploy-ul4i6lnw/kernel/uImage
746 07:25:37.618248 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:39)
747 07:25:37.625060 tftpboot 0x01080000 978415/tftp-deploy-ul4i6lnw/kernel/uImage
748 07:25:37.625524 Speed: 1000, full duplex
749 07:25:37.625918 Using ethernet@ff3f0000 device
750 07:25:37.630615 TFTP from server 192.168.6.2; our IP address is 192.168.6.21
751 07:25:37.636151 Filename '978415/tftp-deploy-ul4i6lnw/kernel/uImage'.
752 07:25:37.639865 Load address: 0x1080000
753 07:25:41.913697 Loading: *#################################################
754 07:25:41.914171 TFTP error: trying to overwrite reserved memory...
756 07:25:41.915166 end: 2.4.3 bootloader-commands (duration 00:00:06) [common]
759 07:25:41.916360 end: 2.4 uboot-commands (duration 00:00:25) [common]
761 07:25:41.917219 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'TFTP error: trying to overwrite reserved memory' (12)'
763 07:25:41.917902 end: 2 uboot-action (duration 00:00:25) [common]
765 07:25:41.918905 Cleaning after the job
766 07:25:41.919294 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/978415/tftp-deploy-ul4i6lnw/ramdisk
767 07:25:41.930071 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/978415/tftp-deploy-ul4i6lnw/kernel
768 07:25:41.949023 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/978415/tftp-deploy-ul4i6lnw/dtb
769 07:25:41.950121 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/978415/tftp-deploy-ul4i6lnw/modules
770 07:25:41.979339 start: 4.1 power-off (timeout 00:00:30) [common]
771 07:25:41.980050 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=solitude-01'
772 07:25:42.017840 >> OK - accepted request
773 07:25:42.019163 Returned 0 in 0 seconds
774 07:25:42.119948 end: 4.1 power-off (duration 00:00:00) [common]
776 07:25:42.120966 start: 4.2 read-feedback (timeout 00:10:00) [common]
777 07:25:42.121606 Listened to connection for namespace 'common' for up to 1s
778 07:25:43.122553 Finalising connection for namespace 'common'
779 07:25:43.123050 Disconnecting from shell: Finalise
780 07:25:43.123328 =>
781 07:25:43.224236 end: 4.2 read-feedback (duration 00:00:01) [common]
782 07:25:43.224921 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/978415
783 07:25:43.589832 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/978415
784 07:25:43.590471 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.