Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 07:28:34.117612 lava-dispatcher, installed at version: 2024.01
2 07:28:34.118397 start: 0 validate
3 07:28:34.118873 Start time: 2024-11-12 07:28:34.118844+00:00 (UTC)
4 07:28:34.119408 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 07:28:34.119940 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 07:28:34.162198 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 07:28:34.162766 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241112%2Farm64%2Fdefconfig%2Bkselftest%2Fgcc-12%2Fkernel%2FImage exists
8 07:28:34.195429 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 07:28:34.196323 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241112%2Farm64%2Fdefconfig%2Bkselftest%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 07:28:34.230050 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 07:28:34.230837 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 07:28:34.262894 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 07:28:34.263667 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241112%2Farm64%2Fdefconfig%2Bkselftest%2Fgcc-12%2Fmodules.tar.xz exists
14 07:28:34.302232 validate duration: 0.18
16 07:28:34.303165 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 07:28:34.303534 start: 1.1 download-retry (timeout 00:10:00) [common]
18 07:28:34.303894 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 07:28:34.305250 Not decompressing ramdisk as can be used compressed.
20 07:28:34.306126 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm/20240313.0/arm64/initrd.cpio.gz
21 07:28:34.306705 saving as /var/lib/lava/dispatcher/tmp/978425/tftp-deploy-dz3xfdac/ramdisk/initrd.cpio.gz
22 07:28:34.307249 total size: 5628182 (5 MB)
23 07:28:34.349962 progress 0 % (0 MB)
24 07:28:34.357856 progress 5 % (0 MB)
25 07:28:34.366328 progress 10 % (0 MB)
26 07:28:34.373769 progress 15 % (0 MB)
27 07:28:34.379226 progress 20 % (1 MB)
28 07:28:34.382952 progress 25 % (1 MB)
29 07:28:34.387049 progress 30 % (1 MB)
30 07:28:34.391231 progress 35 % (1 MB)
31 07:28:34.395233 progress 40 % (2 MB)
32 07:28:34.399824 progress 45 % (2 MB)
33 07:28:34.403632 progress 50 % (2 MB)
34 07:28:34.407847 progress 55 % (2 MB)
35 07:28:34.412016 progress 60 % (3 MB)
36 07:28:34.415746 progress 65 % (3 MB)
37 07:28:34.419878 progress 70 % (3 MB)
38 07:28:34.423749 progress 75 % (4 MB)
39 07:28:34.427859 progress 80 % (4 MB)
40 07:28:34.431654 progress 85 % (4 MB)
41 07:28:34.435783 progress 90 % (4 MB)
42 07:28:34.439794 progress 95 % (5 MB)
43 07:28:34.443143 progress 100 % (5 MB)
44 07:28:34.443810 5 MB downloaded in 0.14 s (39.31 MB/s)
45 07:28:34.444478 end: 1.1.1 http-download (duration 00:00:00) [common]
47 07:28:34.445400 end: 1.1 download-retry (duration 00:00:00) [common]
48 07:28:34.445695 start: 1.2 download-retry (timeout 00:10:00) [common]
49 07:28:34.445967 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 07:28:34.446443 downloading http://storage.kernelci.org/next/master/next-20241112/arm64/defconfig+kselftest/gcc-12/kernel/Image
51 07:28:34.446702 saving as /var/lib/lava/dispatcher/tmp/978425/tftp-deploy-dz3xfdac/kernel/Image
52 07:28:34.446912 total size: 66982400 (63 MB)
53 07:28:34.447124 No compression specified
54 07:28:34.485475 progress 0 % (0 MB)
55 07:28:34.527354 progress 5 % (3 MB)
56 07:28:34.568101 progress 10 % (6 MB)
57 07:28:34.609166 progress 15 % (9 MB)
58 07:28:34.649357 progress 20 % (12 MB)
59 07:28:34.690230 progress 25 % (16 MB)
60 07:28:34.730262 progress 30 % (19 MB)
61 07:28:34.770543 progress 35 % (22 MB)
62 07:28:34.810642 progress 40 % (25 MB)
63 07:28:34.850862 progress 45 % (28 MB)
64 07:28:34.891787 progress 50 % (31 MB)
65 07:28:34.932087 progress 55 % (35 MB)
66 07:28:34.972637 progress 60 % (38 MB)
67 07:28:35.013717 progress 65 % (41 MB)
68 07:28:35.054457 progress 70 % (44 MB)
69 07:28:35.095483 progress 75 % (47 MB)
70 07:28:35.135957 progress 80 % (51 MB)
71 07:28:35.176237 progress 85 % (54 MB)
72 07:28:35.216665 progress 90 % (57 MB)
73 07:28:35.256897 progress 95 % (60 MB)
74 07:28:35.297112 progress 100 % (63 MB)
75 07:28:35.297672 63 MB downloaded in 0.85 s (75.09 MB/s)
76 07:28:35.298148 end: 1.2.1 http-download (duration 00:00:01) [common]
78 07:28:35.298964 end: 1.2 download-retry (duration 00:00:01) [common]
79 07:28:35.299241 start: 1.3 download-retry (timeout 00:09:59) [common]
80 07:28:35.299509 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 07:28:35.299963 downloading http://storage.kernelci.org/next/master/next-20241112/arm64/defconfig+kselftest/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
82 07:28:35.300265 saving as /var/lib/lava/dispatcher/tmp/978425/tftp-deploy-dz3xfdac/dtb/meson-g12b-a311d-libretech-cc.dtb
83 07:28:35.300477 total size: 54703 (0 MB)
84 07:28:35.300687 No compression specified
85 07:28:35.337694 progress 59 % (0 MB)
86 07:28:35.338535 progress 100 % (0 MB)
87 07:28:35.339090 0 MB downloaded in 0.04 s (1.35 MB/s)
88 07:28:35.339577 end: 1.3.1 http-download (duration 00:00:00) [common]
90 07:28:35.340439 end: 1.3 download-retry (duration 00:00:00) [common]
91 07:28:35.340705 start: 1.4 download-retry (timeout 00:09:59) [common]
92 07:28:35.340972 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 07:28:35.341449 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm/20240313.0/arm64/full.rootfs.tar.xz
94 07:28:35.341710 saving as /var/lib/lava/dispatcher/tmp/978425/tftp-deploy-dz3xfdac/nfsrootfs/full.rootfs.tar
95 07:28:35.341915 total size: 107552908 (102 MB)
96 07:28:35.342126 Using unxz to decompress xz
97 07:28:35.379159 progress 0 % (0 MB)
98 07:28:36.029981 progress 5 % (5 MB)
99 07:28:36.761018 progress 10 % (10 MB)
100 07:28:37.490783 progress 15 % (15 MB)
101 07:28:38.253582 progress 20 % (20 MB)
102 07:28:38.826518 progress 25 % (25 MB)
103 07:28:39.454304 progress 30 % (30 MB)
104 07:28:40.196518 progress 35 % (35 MB)
105 07:28:40.561429 progress 40 % (41 MB)
106 07:28:40.994358 progress 45 % (46 MB)
107 07:28:41.685444 progress 50 % (51 MB)
108 07:28:42.371826 progress 55 % (56 MB)
109 07:28:43.126204 progress 60 % (61 MB)
110 07:28:43.883145 progress 65 % (66 MB)
111 07:28:44.617916 progress 70 % (71 MB)
112 07:28:45.380703 progress 75 % (76 MB)
113 07:28:46.058848 progress 80 % (82 MB)
114 07:28:46.763015 progress 85 % (87 MB)
115 07:28:47.481878 progress 90 % (92 MB)
116 07:28:48.179497 progress 95 % (97 MB)
117 07:28:48.907104 progress 100 % (102 MB)
118 07:28:48.918850 102 MB downloaded in 13.58 s (7.55 MB/s)
119 07:28:48.919810 end: 1.4.1 http-download (duration 00:00:14) [common]
121 07:28:48.921665 end: 1.4 download-retry (duration 00:00:14) [common]
122 07:28:48.922252 start: 1.5 download-retry (timeout 00:09:45) [common]
123 07:28:48.922829 start: 1.5.1 http-download (timeout 00:09:45) [common]
124 07:28:48.923696 downloading http://storage.kernelci.org/next/master/next-20241112/arm64/defconfig+kselftest/gcc-12/modules.tar.xz
125 07:28:48.924241 saving as /var/lib/lava/dispatcher/tmp/978425/tftp-deploy-dz3xfdac/modules/modules.tar
126 07:28:48.924703 total size: 16284560 (15 MB)
127 07:28:48.925173 Using unxz to decompress xz
128 07:28:48.968240 progress 0 % (0 MB)
129 07:28:49.068021 progress 5 % (0 MB)
130 07:28:49.189479 progress 10 % (1 MB)
131 07:28:49.318145 progress 15 % (2 MB)
132 07:28:49.450021 progress 20 % (3 MB)
133 07:28:49.591026 progress 25 % (3 MB)
134 07:28:49.701250 progress 30 % (4 MB)
135 07:28:49.806519 progress 35 % (5 MB)
136 07:28:49.919243 progress 40 % (6 MB)
137 07:28:50.025403 progress 45 % (7 MB)
138 07:28:50.141130 progress 50 % (7 MB)
139 07:28:50.253072 progress 55 % (8 MB)
140 07:28:50.370438 progress 60 % (9 MB)
141 07:28:50.484253 progress 65 % (10 MB)
142 07:28:50.591024 progress 70 % (10 MB)
143 07:28:50.706505 progress 75 % (11 MB)
144 07:28:50.820654 progress 80 % (12 MB)
145 07:28:50.933278 progress 85 % (13 MB)
146 07:28:51.044911 progress 90 % (14 MB)
147 07:28:51.147944 progress 95 % (14 MB)
148 07:28:51.260706 progress 100 % (15 MB)
149 07:28:51.274857 15 MB downloaded in 2.35 s (6.61 MB/s)
150 07:28:51.276183 end: 1.5.1 http-download (duration 00:00:02) [common]
152 07:28:51.278518 end: 1.5 download-retry (duration 00:00:02) [common]
153 07:28:51.279333 start: 1.6 prepare-tftp-overlay (timeout 00:09:43) [common]
154 07:28:51.280169 start: 1.6.1 extract-nfsrootfs (timeout 00:09:43) [common]
155 07:29:01.182062 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/978425/extract-nfsrootfs-ou3jbuah
156 07:29:01.182626 end: 1.6.1 extract-nfsrootfs (duration 00:00:10) [common]
157 07:29:01.182914 start: 1.6.2 lava-overlay (timeout 00:09:33) [common]
158 07:29:01.183496 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/978425/lava-overlay-nhhcnyx0
159 07:29:01.183932 makedir: /var/lib/lava/dispatcher/tmp/978425/lava-overlay-nhhcnyx0/lava-978425/bin
160 07:29:01.184308 makedir: /var/lib/lava/dispatcher/tmp/978425/lava-overlay-nhhcnyx0/lava-978425/tests
161 07:29:01.184635 makedir: /var/lib/lava/dispatcher/tmp/978425/lava-overlay-nhhcnyx0/lava-978425/results
162 07:29:01.184962 Creating /var/lib/lava/dispatcher/tmp/978425/lava-overlay-nhhcnyx0/lava-978425/bin/lava-add-keys
163 07:29:01.185485 Creating /var/lib/lava/dispatcher/tmp/978425/lava-overlay-nhhcnyx0/lava-978425/bin/lava-add-sources
164 07:29:01.185997 Creating /var/lib/lava/dispatcher/tmp/978425/lava-overlay-nhhcnyx0/lava-978425/bin/lava-background-process-start
165 07:29:01.186514 Creating /var/lib/lava/dispatcher/tmp/978425/lava-overlay-nhhcnyx0/lava-978425/bin/lava-background-process-stop
166 07:29:01.187060 Creating /var/lib/lava/dispatcher/tmp/978425/lava-overlay-nhhcnyx0/lava-978425/bin/lava-common-functions
167 07:29:01.187576 Creating /var/lib/lava/dispatcher/tmp/978425/lava-overlay-nhhcnyx0/lava-978425/bin/lava-echo-ipv4
168 07:29:01.188110 Creating /var/lib/lava/dispatcher/tmp/978425/lava-overlay-nhhcnyx0/lava-978425/bin/lava-install-packages
169 07:29:01.188637 Creating /var/lib/lava/dispatcher/tmp/978425/lava-overlay-nhhcnyx0/lava-978425/bin/lava-installed-packages
170 07:29:01.189166 Creating /var/lib/lava/dispatcher/tmp/978425/lava-overlay-nhhcnyx0/lava-978425/bin/lava-os-build
171 07:29:01.189668 Creating /var/lib/lava/dispatcher/tmp/978425/lava-overlay-nhhcnyx0/lava-978425/bin/lava-probe-channel
172 07:29:01.190154 Creating /var/lib/lava/dispatcher/tmp/978425/lava-overlay-nhhcnyx0/lava-978425/bin/lava-probe-ip
173 07:29:01.190631 Creating /var/lib/lava/dispatcher/tmp/978425/lava-overlay-nhhcnyx0/lava-978425/bin/lava-target-ip
174 07:29:01.191115 Creating /var/lib/lava/dispatcher/tmp/978425/lava-overlay-nhhcnyx0/lava-978425/bin/lava-target-mac
175 07:29:01.191614 Creating /var/lib/lava/dispatcher/tmp/978425/lava-overlay-nhhcnyx0/lava-978425/bin/lava-target-storage
176 07:29:01.192161 Creating /var/lib/lava/dispatcher/tmp/978425/lava-overlay-nhhcnyx0/lava-978425/bin/lava-test-case
177 07:29:01.192664 Creating /var/lib/lava/dispatcher/tmp/978425/lava-overlay-nhhcnyx0/lava-978425/bin/lava-test-event
178 07:29:01.193145 Creating /var/lib/lava/dispatcher/tmp/978425/lava-overlay-nhhcnyx0/lava-978425/bin/lava-test-feedback
179 07:29:01.193631 Creating /var/lib/lava/dispatcher/tmp/978425/lava-overlay-nhhcnyx0/lava-978425/bin/lava-test-raise
180 07:29:01.194108 Creating /var/lib/lava/dispatcher/tmp/978425/lava-overlay-nhhcnyx0/lava-978425/bin/lava-test-reference
181 07:29:01.194605 Creating /var/lib/lava/dispatcher/tmp/978425/lava-overlay-nhhcnyx0/lava-978425/bin/lava-test-runner
182 07:29:01.195099 Creating /var/lib/lava/dispatcher/tmp/978425/lava-overlay-nhhcnyx0/lava-978425/bin/lava-test-set
183 07:29:01.195581 Creating /var/lib/lava/dispatcher/tmp/978425/lava-overlay-nhhcnyx0/lava-978425/bin/lava-test-shell
184 07:29:01.196112 Updating /var/lib/lava/dispatcher/tmp/978425/lava-overlay-nhhcnyx0/lava-978425/bin/lava-install-packages (oe)
185 07:29:01.196662 Updating /var/lib/lava/dispatcher/tmp/978425/lava-overlay-nhhcnyx0/lava-978425/bin/lava-installed-packages (oe)
186 07:29:01.197111 Creating /var/lib/lava/dispatcher/tmp/978425/lava-overlay-nhhcnyx0/lava-978425/environment
187 07:29:01.197488 LAVA metadata
188 07:29:01.197748 - LAVA_JOB_ID=978425
189 07:29:01.197963 - LAVA_DISPATCHER_IP=192.168.6.2
190 07:29:01.198332 start: 1.6.2.1 ssh-authorize (timeout 00:09:33) [common]
191 07:29:01.199301 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
192 07:29:01.199622 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:33) [common]
193 07:29:01.199837 skipped lava-vland-overlay
194 07:29:01.200121 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
195 07:29:01.200384 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:33) [common]
196 07:29:01.200610 skipped lava-multinode-overlay
197 07:29:01.200856 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
198 07:29:01.201111 start: 1.6.2.4 test-definition (timeout 00:09:33) [common]
199 07:29:01.201363 Loading test definitions
200 07:29:01.201647 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:33) [common]
201 07:29:01.201872 Using /lava-978425 at stage 0
202 07:29:01.203075 uuid=978425_1.6.2.4.1 testdef=None
203 07:29:01.203395 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
204 07:29:01.203658 start: 1.6.2.4.2 test-overlay (timeout 00:09:33) [common]
205 07:29:01.205588 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
207 07:29:01.206385 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:33) [common]
208 07:29:01.208669 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
210 07:29:01.209516 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:33) [common]
211 07:29:01.211728 runner path: /var/lib/lava/dispatcher/tmp/978425/lava-overlay-nhhcnyx0/lava-978425/0/tests/0_dmesg test_uuid 978425_1.6.2.4.1
212 07:29:01.212369 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
214 07:29:01.213148 Creating lava-test-runner.conf files
215 07:29:01.213352 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/978425/lava-overlay-nhhcnyx0/lava-978425/0 for stage 0
216 07:29:01.213716 - 0_dmesg
217 07:29:01.214081 end: 1.6.2.4 test-definition (duration 00:00:00) [common]
218 07:29:01.214370 start: 1.6.2.5 compress-overlay (timeout 00:09:33) [common]
219 07:29:01.236213 end: 1.6.2.5 compress-overlay (duration 00:00:00) [common]
220 07:29:01.236636 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:09:33) [common]
221 07:29:01.236902 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
222 07:29:01.237173 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
223 07:29:01.237436 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:33) [common]
224 07:29:01.877293 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:01) [common]
225 07:29:01.877911 start: 1.6.4 extract-modules (timeout 00:09:32) [common]
226 07:29:01.878196 extracting modules file /var/lib/lava/dispatcher/tmp/978425/tftp-deploy-dz3xfdac/modules/modules.tar to /var/lib/lava/dispatcher/tmp/978425/extract-nfsrootfs-ou3jbuah
227 07:29:03.498614 extracting modules file /var/lib/lava/dispatcher/tmp/978425/tftp-deploy-dz3xfdac/modules/modules.tar to /var/lib/lava/dispatcher/tmp/978425/extract-overlay-ramdisk-b57mhqgb/ramdisk
228 07:29:05.087917 end: 1.6.4 extract-modules (duration 00:00:03) [common]
229 07:29:05.088422 start: 1.6.5 apply-overlay-tftp (timeout 00:09:29) [common]
230 07:29:05.088701 [common] Applying overlay to NFS
231 07:29:05.088914 [common] Applying overlay /var/lib/lava/dispatcher/tmp/978425/compress-overlay-f7ofkaq_/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/978425/extract-nfsrootfs-ou3jbuah
232 07:29:05.118014 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
233 07:29:05.118421 start: 1.6.6 prepare-kernel (timeout 00:09:29) [common]
234 07:29:05.118694 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:09:29) [common]
235 07:29:05.118923 Converting downloaded kernel to a uImage
236 07:29:05.119227 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/978425/tftp-deploy-dz3xfdac/kernel/Image /var/lib/lava/dispatcher/tmp/978425/tftp-deploy-dz3xfdac/kernel/uImage
237 07:29:05.891372 output: Image Name:
238 07:29:05.891798 output: Created: Tue Nov 12 07:29:05 2024
239 07:29:05.892043 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
240 07:29:05.892262 output: Data Size: 66982400 Bytes = 65412.50 KiB = 63.88 MiB
241 07:29:05.892465 output: Load Address: 01080000
242 07:29:05.892667 output: Entry Point: 01080000
243 07:29:05.892865 output:
244 07:29:05.893200 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:01) [common]
245 07:29:05.893466 end: 1.6.6 prepare-kernel (duration 00:00:01) [common]
246 07:29:05.893734 start: 1.6.7 configure-preseed-file (timeout 00:09:28) [common]
247 07:29:05.893988 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
248 07:29:05.894244 start: 1.6.8 compress-ramdisk (timeout 00:09:28) [common]
249 07:29:05.894496 Building ramdisk /var/lib/lava/dispatcher/tmp/978425/extract-overlay-ramdisk-b57mhqgb/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/978425/extract-overlay-ramdisk-b57mhqgb/ramdisk
250 07:29:09.577695 >> 243541 blocks
251 07:29:19.958344 Adding RAMdisk u-boot header.
252 07:29:19.958981 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/978425/extract-overlay-ramdisk-b57mhqgb/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/978425/extract-overlay-ramdisk-b57mhqgb/ramdisk.cpio.gz.uboot
253 07:29:20.273818 output: Image Name:
254 07:29:20.274236 output: Created: Tue Nov 12 07:29:19 2024
255 07:29:20.274449 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
256 07:29:20.274654 output: Data Size: 31329024 Bytes = 30594.75 KiB = 29.88 MiB
257 07:29:20.274856 output: Load Address: 00000000
258 07:29:20.275054 output: Entry Point: 00000000
259 07:29:20.275250 output:
260 07:29:20.275894 rename /var/lib/lava/dispatcher/tmp/978425/extract-overlay-ramdisk-b57mhqgb/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/978425/tftp-deploy-dz3xfdac/ramdisk/ramdisk.cpio.gz.uboot
261 07:29:20.276665 end: 1.6.8 compress-ramdisk (duration 00:00:14) [common]
262 07:29:20.277268 end: 1.6 prepare-tftp-overlay (duration 00:00:29) [common]
263 07:29:20.277852 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:14) [common]
264 07:29:20.278357 No LXC device requested
265 07:29:20.278912 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
266 07:29:20.279475 start: 1.8 deploy-device-env (timeout 00:09:14) [common]
267 07:29:20.280051 end: 1.8 deploy-device-env (duration 00:00:00) [common]
268 07:29:20.280520 Checking files for TFTP limit of 4294967296 bytes.
269 07:29:20.283469 end: 1 tftp-deploy (duration 00:00:46) [common]
270 07:29:20.284151 start: 2 uboot-action (timeout 00:05:00) [common]
271 07:29:20.284740 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
272 07:29:20.285292 end: 2.1 uboot-from-media (duration 00:00:00) [common]
273 07:29:20.285845 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
274 07:29:20.286422 Using kernel file from prepare-kernel: 978425/tftp-deploy-dz3xfdac/kernel/uImage
275 07:29:20.287112 substitutions:
276 07:29:20.287560 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
277 07:29:20.288045 - {DTB_ADDR}: 0x01070000
278 07:29:20.288488 - {DTB}: 978425/tftp-deploy-dz3xfdac/dtb/meson-g12b-a311d-libretech-cc.dtb
279 07:29:20.288928 - {INITRD}: 978425/tftp-deploy-dz3xfdac/ramdisk/ramdisk.cpio.gz.uboot
280 07:29:20.289365 - {KERNEL_ADDR}: 0x01080000
281 07:29:20.289798 - {KERNEL}: 978425/tftp-deploy-dz3xfdac/kernel/uImage
282 07:29:20.290233 - {LAVA_MAC}: None
283 07:29:20.290709 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/978425/extract-nfsrootfs-ou3jbuah
284 07:29:20.291145 - {NFS_SERVER_IP}: 192.168.6.2
285 07:29:20.291573 - {PRESEED_CONFIG}: None
286 07:29:20.292026 - {PRESEED_LOCAL}: None
287 07:29:20.292459 - {RAMDISK_ADDR}: 0x08000000
288 07:29:20.292887 - {RAMDISK}: 978425/tftp-deploy-dz3xfdac/ramdisk/ramdisk.cpio.gz.uboot
289 07:29:20.293317 - {ROOT_PART}: None
290 07:29:20.293746 - {ROOT}: None
291 07:29:20.294174 - {SERVER_IP}: 192.168.6.2
292 07:29:20.294602 - {TEE_ADDR}: 0x83000000
293 07:29:20.295026 - {TEE}: None
294 07:29:20.295455 Parsed boot commands:
295 07:29:20.295869 - setenv autoload no
296 07:29:20.296322 - setenv initrd_high 0xffffffff
297 07:29:20.296747 - setenv fdt_high 0xffffffff
298 07:29:20.297173 - dhcp
299 07:29:20.297594 - setenv serverip 192.168.6.2
300 07:29:20.298017 - tftpboot 0x01080000 978425/tftp-deploy-dz3xfdac/kernel/uImage
301 07:29:20.298447 - tftpboot 0x08000000 978425/tftp-deploy-dz3xfdac/ramdisk/ramdisk.cpio.gz.uboot
302 07:29:20.298878 - tftpboot 0x01070000 978425/tftp-deploy-dz3xfdac/dtb/meson-g12b-a311d-libretech-cc.dtb
303 07:29:20.299304 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/978425/extract-nfsrootfs-ou3jbuah,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
304 07:29:20.299743 - bootm 0x01080000 0x08000000 0x01070000
305 07:29:20.300333 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
307 07:29:20.301975 start: 2.3 connect-device (timeout 00:05:00) [common]
308 07:29:20.302433 [common] connect-device Connecting to device using 'telnet conserv1 3007'
309 07:29:20.317809 Setting prompt string to ['lava-test: # ']
310 07:29:20.319428 end: 2.3 connect-device (duration 00:00:00) [common]
311 07:29:20.320117 start: 2.4 uboot-commands (timeout 00:05:00) [common]
312 07:29:20.320751 start: 2.4.1 reset-device (timeout 00:05:00) [common]
313 07:29:20.321362 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
314 07:29:20.322646 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
315 07:29:20.359093 >> OK - accepted request
316 07:29:20.361432 Returned 0 in 0 seconds
317 07:29:20.462645 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
319 07:29:20.464544 end: 2.4.1 reset-device (duration 00:00:00) [common]
320 07:29:20.465207 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
321 07:29:20.465787 Setting prompt string to ['Hit any key to stop autoboot']
322 07:29:20.466310 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
323 07:29:20.468055 Trying 192.168.56.21...
324 07:29:20.468587 Connected to conserv1.
325 07:29:20.469065 Escape character is '^]'.
326 07:29:20.469542
327 07:29:20.470022 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
328 07:29:20.470509
329 07:29:32.023185 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
330 07:29:32.023606 bl2_stage_init 0x01
331 07:29:32.023841 bl2_stage_init 0x81
332 07:29:32.028779 hw id: 0x0000 - pwm id 0x01
333 07:29:32.029344 bl2_stage_init 0xc1
334 07:29:32.029784 bl2_stage_init 0x02
335 07:29:32.030215
336 07:29:32.034351 L0:00000000
337 07:29:32.034860 L1:20000703
338 07:29:32.035296 L2:00008067
339 07:29:32.035728 L3:14000000
340 07:29:32.039920 B2:00402000
341 07:29:32.040464 B1:e0f83180
342 07:29:32.040911
343 07:29:32.041345 TE: 58159
344 07:29:32.041782
345 07:29:32.045533 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
346 07:29:32.046034
347 07:29:32.046470 Board ID = 1
348 07:29:32.051222 Set A53 clk to 24M
349 07:29:32.051719 Set A73 clk to 24M
350 07:29:32.052199 Set clk81 to 24M
351 07:29:32.056764 A53 clk: 1200 MHz
352 07:29:32.057263 A73 clk: 1200 MHz
353 07:29:32.057696 CLK81: 166.6M
354 07:29:32.058125 smccc: 00012ab5
355 07:29:32.062344 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
356 07:29:32.067972 board id: 1
357 07:29:32.073794 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
358 07:29:32.084494 fw parse done
359 07:29:32.090451 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
360 07:29:32.133023 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
361 07:29:32.144041 PIEI prepare done
362 07:29:32.144540 fastboot data load
363 07:29:32.144979 fastboot data verify
364 07:29:32.149588 verify result: 266
365 07:29:32.155261 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
366 07:29:32.155752 LPDDR4 probe
367 07:29:32.156234 ddr clk to 1584MHz
368 07:29:32.163226 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
369 07:29:32.200407
370 07:29:32.200918 dmc_version 0001
371 07:29:32.207074 Check phy result
372 07:29:32.212976 INFO : End of CA training
373 07:29:32.213471 INFO : End of initialization
374 07:29:32.218610 INFO : Training has run successfully!
375 07:29:32.219111 Check phy result
376 07:29:32.224305 INFO : End of initialization
377 07:29:32.224806 INFO : End of read enable training
378 07:29:32.229791 INFO : End of fine write leveling
379 07:29:32.235422 INFO : End of Write leveling coarse delay
380 07:29:32.235927 INFO : Training has run successfully!
381 07:29:32.236421 Check phy result
382 07:29:32.240978 INFO : End of initialization
383 07:29:32.241496 INFO : End of read dq deskew training
384 07:29:32.246599 INFO : End of MPR read delay center optimization
385 07:29:32.252306 INFO : End of write delay center optimization
386 07:29:32.257777 INFO : End of read delay center optimization
387 07:29:32.258275 INFO : End of max read latency training
388 07:29:32.263412 INFO : Training has run successfully!
389 07:29:32.263911 1D training succeed
390 07:29:32.271638 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
391 07:29:32.320215 Check phy result
392 07:29:32.320831 INFO : End of initialization
393 07:29:32.342220 INFO : End of 2D read delay Voltage center optimization
394 07:29:32.362893 INFO : End of 2D read delay Voltage center optimization
395 07:29:32.413443 INFO : End of 2D write delay Voltage center optimization
396 07:29:32.463778 INFO : End of 2D write delay Voltage center optimization
397 07:29:32.469390 INFO : Training has run successfully!
398 07:29:32.469932
399 07:29:32.470424 channel==0
400 07:29:32.474870 RxClkDly_Margin_A0==88 ps 9
401 07:29:32.475516 TxDqDly_Margin_A0==98 ps 10
402 07:29:32.478318 RxClkDly_Margin_A1==88 ps 9
403 07:29:32.478832 TxDqDly_Margin_A1==98 ps 10
404 07:29:32.483767 TrainedVREFDQ_A0==74
405 07:29:32.484306 TrainedVREFDQ_A1==74
406 07:29:32.484749 VrefDac_Margin_A0==25
407 07:29:32.489413 DeviceVref_Margin_A0==40
408 07:29:32.489929 VrefDac_Margin_A1==25
409 07:29:32.495003 DeviceVref_Margin_A1==40
410 07:29:32.495507
411 07:29:32.496200
412 07:29:32.496876 channel==1
413 07:29:32.497341 RxClkDly_Margin_A0==98 ps 10
414 07:29:32.498513 TxDqDly_Margin_A0==88 ps 9
415 07:29:32.504068 RxClkDly_Margin_A1==88 ps 9
416 07:29:32.504584 TxDqDly_Margin_A1==88 ps 9
417 07:29:32.505028 TrainedVREFDQ_A0==77
418 07:29:32.509577 TrainedVREFDQ_A1==77
419 07:29:32.510075 VrefDac_Margin_A0==22
420 07:29:32.515232 DeviceVref_Margin_A0==37
421 07:29:32.515727 VrefDac_Margin_A1==24
422 07:29:32.516202 DeviceVref_Margin_A1==37
423 07:29:32.516639
424 07:29:32.520882 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
425 07:29:32.521377
426 07:29:32.554267 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000018 00000019 00000017 00000019 00000018 0000001a 0000001a 00000018 00000017 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
427 07:29:32.554859 2D training succeed
428 07:29:32.559939 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
429 07:29:32.565482 auto size-- 65535DDR cs0 size: 2048MB
430 07:29:32.565983 DDR cs1 size: 2048MB
431 07:29:32.571074 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
432 07:29:32.571568 cs0 DataBus test pass
433 07:29:32.572042 cs1 DataBus test pass
434 07:29:32.576711 cs0 AddrBus test pass
435 07:29:32.577205 cs1 AddrBus test pass
436 07:29:32.577640
437 07:29:32.582321 100bdlr_step_size ps== 420
438 07:29:32.582836 result report
439 07:29:32.583273 boot times 0Enable ddr reg access
440 07:29:32.591736 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
441 07:29:32.605555 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
442 07:29:33.179018 0.0;M3 CHK:0;cm4_sp_mode 0
443 07:29:33.179647 MVN_1=0x00000000
444 07:29:33.184539 MVN_2=0x00000000
445 07:29:33.190303 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
446 07:29:33.190805 OPS=0x10
447 07:29:33.191251 ring efuse init
448 07:29:33.191703 chipver efuse init
449 07:29:33.195928 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
450 07:29:33.201487 [0.018961 Inits done]
451 07:29:33.201977 secure task start!
452 07:29:33.202416 high task start!
453 07:29:33.206099 low task start!
454 07:29:33.206606 run into bl31
455 07:29:33.212722 NOTICE: BL31: v1.3(release):4fc40b1
456 07:29:33.220516 NOTICE: BL31: Built : 15:58:17, May 22 2019
457 07:29:33.221022 NOTICE: BL31: G12A normal boot!
458 07:29:33.245937 NOTICE: BL31: BL33 decompress pass
459 07:29:33.251629 ERROR: Error initializing runtime service opteed_fast
460 07:29:34.484409
461 07:29:34.484851
462 07:29:34.492886 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
463 07:29:34.493481
464 07:29:34.493892 Model: Libre Computer AML-A311D-CC Alta
465 07:29:34.701293 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
466 07:29:34.724678 DRAM: 2 GiB (effective 3.8 GiB)
467 07:29:34.867653 Core: 408 devices, 31 uclasses, devicetree: separate
468 07:29:34.872758 WDT: Not starting watchdog@f0d0
469 07:29:34.905797 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
470 07:29:34.918224 Loading Environment from FAT... Card did not respond to voltage select! : -110
471 07:29:34.922317 ** Bad device specification mmc 0 **
472 07:29:34.933600 Card did not respond to voltage select! : -110
473 07:29:34.940338 ** Bad device specification mmc 0 **
474 07:29:34.940892 Couldn't find partition mmc 0
475 07:29:34.949593 Card did not respond to voltage select! : -110
476 07:29:34.955108 ** Bad device specification mmc 0 **
477 07:29:34.955667 Couldn't find partition mmc 0
478 07:29:34.959159 Error: could not access storage.
479 07:29:36.223629 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
480 07:29:36.224250 bl2_stage_init 0x01
481 07:29:36.224517 bl2_stage_init 0x81
482 07:29:36.229369 hw id: 0x0000 - pwm id 0x01
483 07:29:36.229685 bl2_stage_init 0xc1
484 07:29:36.229893 bl2_stage_init 0x02
485 07:29:36.230095
486 07:29:36.234772 L0:00000000
487 07:29:36.235190 L1:20000703
488 07:29:36.235497 L2:00008067
489 07:29:36.235798 L3:14000000
490 07:29:36.240388 B2:00402000
491 07:29:36.240805 B1:e0f83180
492 07:29:36.241113
493 07:29:36.241412 TE: 58159
494 07:29:36.241636
495 07:29:36.245950 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
496 07:29:36.246262
497 07:29:36.246468 Board ID = 1
498 07:29:36.251587 Set A53 clk to 24M
499 07:29:36.252056 Set A73 clk to 24M
500 07:29:36.252394 Set clk81 to 24M
501 07:29:36.257176 A53 clk: 1200 MHz
502 07:29:36.257630 A73 clk: 1200 MHz
503 07:29:36.257885 CLK81: 166.6M
504 07:29:36.258103 smccc: 00012ab5
505 07:29:36.262700 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
506 07:29:36.268285 board id: 1
507 07:29:36.274212 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
508 07:29:36.284923 fw parse done
509 07:29:36.289888 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
510 07:29:36.332647 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
511 07:29:36.344446 PIEI prepare done
512 07:29:36.345004 fastboot data load
513 07:29:36.345267 fastboot data verify
514 07:29:36.350119 verify result: 266
515 07:29:36.355701 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
516 07:29:36.356108 LPDDR4 probe
517 07:29:36.356332 ddr clk to 1584MHz
518 07:29:36.363733 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
519 07:29:36.400001
520 07:29:36.400448 dmc_version 0001
521 07:29:36.407924 Check phy result
522 07:29:36.413501 INFO : End of CA training
523 07:29:36.414301 INFO : End of initialization
524 07:29:36.419089 INFO : Training has run successfully!
525 07:29:36.419657 Check phy result
526 07:29:36.424810 INFO : End of initialization
527 07:29:36.425370 INFO : End of read enable training
528 07:29:36.430328 INFO : End of fine write leveling
529 07:29:36.436132 INFO : End of Write leveling coarse delay
530 07:29:36.436784 INFO : Training has run successfully!
531 07:29:36.437345 Check phy result
532 07:29:36.441559 INFO : End of initialization
533 07:29:36.442155 INFO : End of read dq deskew training
534 07:29:36.447529 INFO : End of MPR read delay center optimization
535 07:29:36.452867 INFO : End of write delay center optimization
536 07:29:36.458440 INFO : End of read delay center optimization
537 07:29:36.459056 INFO : End of max read latency training
538 07:29:36.464039 INFO : Training has run successfully!
539 07:29:36.464615 1D training succeed
540 07:29:36.473078 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
541 07:29:36.519885 Check phy result
542 07:29:36.520507 INFO : End of initialization
543 07:29:36.542436 INFO : End of 2D read delay Voltage center optimization
544 07:29:36.562781 INFO : End of 2D read delay Voltage center optimization
545 07:29:36.614668 INFO : End of 2D write delay Voltage center optimization
546 07:29:36.664054 INFO : End of 2D write delay Voltage center optimization
547 07:29:36.669734 INFO : Training has run successfully!
548 07:29:36.670255
549 07:29:36.670722 channel==0
550 07:29:36.675213 RxClkDly_Margin_A0==88 ps 9
551 07:29:36.675728 TxDqDly_Margin_A0==98 ps 10
552 07:29:36.680723 RxClkDly_Margin_A1==88 ps 9
553 07:29:36.681242 TxDqDly_Margin_A1==88 ps 9
554 07:29:36.681708 TrainedVREFDQ_A0==74
555 07:29:36.686469 TrainedVREFDQ_A1==74
556 07:29:36.687004 VrefDac_Margin_A0==25
557 07:29:36.687470 DeviceVref_Margin_A0==40
558 07:29:36.692050 VrefDac_Margin_A1==25
559 07:29:36.692608 DeviceVref_Margin_A1==40
560 07:29:36.693072
561 07:29:36.693525
562 07:29:36.693972 channel==1
563 07:29:36.697727 RxClkDly_Margin_A0==98 ps 10
564 07:29:36.698250 TxDqDly_Margin_A0==88 ps 9
565 07:29:36.703203 RxClkDly_Margin_A1==98 ps 10
566 07:29:36.703716 TxDqDly_Margin_A1==88 ps 9
567 07:29:36.708839 TrainedVREFDQ_A0==76
568 07:29:36.709355 TrainedVREFDQ_A1==77
569 07:29:36.709816 VrefDac_Margin_A0==22
570 07:29:36.714450 DeviceVref_Margin_A0==38
571 07:29:36.715000 VrefDac_Margin_A1==22
572 07:29:36.720024 DeviceVref_Margin_A1==37
573 07:29:36.720550
574 07:29:36.721021 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
575 07:29:36.721476
576 07:29:36.753713 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000018 00000015 00000018 00000019 00000017 00000019 00000018 0000001a 0000001a 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
577 07:29:36.754313 2D training succeed
578 07:29:36.759222 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
579 07:29:36.764789 auto size-- 65535DDR cs0 size: 2048MB
580 07:29:36.765312 DDR cs1 size: 2048MB
581 07:29:36.770501 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
582 07:29:36.771022 cs0 DataBus test pass
583 07:29:36.776040 cs1 DataBus test pass
584 07:29:36.776560 cs0 AddrBus test pass
585 07:29:36.777015 cs1 AddrBus test pass
586 07:29:36.777464
587 07:29:36.781731 100bdlr_step_size ps== 420
588 07:29:36.782263 result report
589 07:29:36.787226 boot times 0Enable ddr reg access
590 07:29:36.792477 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
591 07:29:36.805936 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
592 07:29:37.379681 0.0;M3 CHK:0;cm4_sp_mode 0
593 07:29:37.380403 MVN_1=0x00000000
594 07:29:37.385209 MVN_2=0x00000000
595 07:29:37.390941 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
596 07:29:37.391502 OPS=0x10
597 07:29:37.392023 ring efuse init
598 07:29:37.392531 chipver efuse init
599 07:29:37.396524 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
600 07:29:37.402114 [0.018961 Inits done]
601 07:29:37.402634 secure task start!
602 07:29:37.403073 high task start!
603 07:29:37.406688 low task start!
604 07:29:37.407197 run into bl31
605 07:29:37.413346 NOTICE: BL31: v1.3(release):4fc40b1
606 07:29:37.421109 NOTICE: BL31: Built : 15:58:17, May 22 2019
607 07:29:37.421622 NOTICE: BL31: G12A normal boot!
608 07:29:37.446523 NOTICE: BL31: BL33 decompress pass
609 07:29:37.452231 ERROR: Error initializing runtime service opteed_fast
610 07:29:38.685115
611 07:29:38.685544
612 07:29:38.693490 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
613 07:29:38.694409
614 07:29:38.694694 Model: Libre Computer AML-A311D-CC Alta
615 07:29:38.902291 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
616 07:29:38.925422 DRAM: 2 GiB (effective 3.8 GiB)
617 07:29:39.068496 Core: 408 devices, 31 uclasses, devicetree: separate
618 07:29:39.074414 WDT: Not starting watchdog@f0d0
619 07:29:39.106540 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
620 07:29:39.119145 Loading Environment from FAT... Card did not respond to voltage select! : -110
621 07:29:39.124062 ** Bad device specification mmc 0 **
622 07:29:39.134457 Card did not respond to voltage select! : -110
623 07:29:39.142050 ** Bad device specification mmc 0 **
624 07:29:39.142570 Couldn't find partition mmc 0
625 07:29:39.150435 Card did not respond to voltage select! : -110
626 07:29:39.155876 ** Bad device specification mmc 0 **
627 07:29:39.156444 Couldn't find partition mmc 0
628 07:29:39.160991 Error: could not access storage.
629 07:29:39.503526 Net: eth0: ethernet@ff3f0000
630 07:29:39.504226 starting USB...
631 07:29:39.755360 Bus usb@ff500000: Register 3000140 NbrPorts 3
632 07:29:39.756042 Starting the controller
633 07:29:39.762387 USB XHCI 1.10
634 07:29:41.354071 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
635 07:29:41.354750 bl2_stage_init 0x01
636 07:29:41.355219 bl2_stage_init 0x81
637 07:29:41.359638 hw id: 0x0000 - pwm id 0x01
638 07:29:41.360228 bl2_stage_init 0xc1
639 07:29:41.360695 bl2_stage_init 0x02
640 07:29:41.361146
641 07:29:41.365235 L0:00000000
642 07:29:41.365749 L1:20000703
643 07:29:41.366203 L2:00008067
644 07:29:41.366651 L3:14000000
645 07:29:41.368105 B2:00402000
646 07:29:41.368613 B1:e0f83180
647 07:29:41.369066
648 07:29:41.369514 TE: 58159
649 07:29:41.369959
650 07:29:41.379135 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
651 07:29:41.379701
652 07:29:41.380199 Board ID = 1
653 07:29:41.380649 Set A53 clk to 24M
654 07:29:41.381094 Set A73 clk to 24M
655 07:29:41.384765 Set clk81 to 24M
656 07:29:41.385281 A53 clk: 1200 MHz
657 07:29:41.385732 A73 clk: 1200 MHz
658 07:29:41.390327 CLK81: 166.6M
659 07:29:41.390831 smccc: 00012ab5
660 07:29:41.395915 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
661 07:29:41.396467 board id: 1
662 07:29:41.403594 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
663 07:29:41.415127 fw parse done
664 07:29:41.420244 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
665 07:29:41.462782 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
666 07:29:41.474644 PIEI prepare done
667 07:29:41.475216 fastboot data load
668 07:29:41.475686 fastboot data verify
669 07:29:41.480304 verify result: 266
670 07:29:41.485900 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
671 07:29:41.486434 LPDDR4 probe
672 07:29:41.486902 ddr clk to 1584MHz
673 07:29:41.492923 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
674 07:29:41.531090
675 07:29:41.531673 dmc_version 0001
676 07:29:41.536825 Check phy result
677 07:29:41.543649 INFO : End of CA training
678 07:29:41.544207 INFO : End of initialization
679 07:29:41.549257 INFO : Training has run successfully!
680 07:29:41.549809 Check phy result
681 07:29:41.554856 INFO : End of initialization
682 07:29:41.555385 INFO : End of read enable training
683 07:29:41.561409 INFO : End of fine write leveling
684 07:29:41.566021 INFO : End of Write leveling coarse delay
685 07:29:41.566564 INFO : Training has run successfully!
686 07:29:41.567039 Check phy result
687 07:29:41.571671 INFO : End of initialization
688 07:29:41.572256 INFO : End of read dq deskew training
689 07:29:41.577252 INFO : End of MPR read delay center optimization
690 07:29:41.582848 INFO : End of write delay center optimization
691 07:29:41.588456 INFO : End of read delay center optimization
692 07:29:41.588988 INFO : End of max read latency training
693 07:29:41.594131 INFO : Training has run successfully!
694 07:29:41.594682 1D training succeed
695 07:29:41.602288 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
696 07:29:41.649916 Check phy result
697 07:29:41.650514 INFO : End of initialization
698 07:29:41.671634 INFO : End of 2D read delay Voltage center optimization
699 07:29:41.692528 INFO : End of 2D read delay Voltage center optimization
700 07:29:41.743613 INFO : End of 2D write delay Voltage center optimization
701 07:29:41.793699 INFO : End of 2D write delay Voltage center optimization
702 07:29:41.799285 INFO : Training has run successfully!
703 07:29:41.799817
704 07:29:41.800338 channel==0
705 07:29:41.804834 RxClkDly_Margin_A0==88 ps 9
706 07:29:41.805400 TxDqDly_Margin_A0==98 ps 10
707 07:29:41.810468 RxClkDly_Margin_A1==88 ps 9
708 07:29:41.810999 TxDqDly_Margin_A1==98 ps 10
709 07:29:41.811460 TrainedVREFDQ_A0==74
710 07:29:41.816128 TrainedVREFDQ_A1==74
711 07:29:41.816675 VrefDac_Margin_A0==25
712 07:29:41.817131 DeviceVref_Margin_A0==40
713 07:29:41.821707 VrefDac_Margin_A1==25
714 07:29:41.822249 DeviceVref_Margin_A1==40
715 07:29:41.822701
716 07:29:41.823140
717 07:29:41.827295 channel==1
718 07:29:41.827837 RxClkDly_Margin_A0==98 ps 10
719 07:29:41.828327 TxDqDly_Margin_A0==98 ps 10
720 07:29:41.832949 RxClkDly_Margin_A1==88 ps 9
721 07:29:41.833481 TxDqDly_Margin_A1==88 ps 9
722 07:29:41.838472 TrainedVREFDQ_A0==77
723 07:29:41.838990 TrainedVREFDQ_A1==77
724 07:29:41.839429 VrefDac_Margin_A0==22
725 07:29:41.844092 DeviceVref_Margin_A0==37
726 07:29:41.844609 VrefDac_Margin_A1==24
727 07:29:41.849663 DeviceVref_Margin_A1==37
728 07:29:41.850201
729 07:29:41.850662 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
730 07:29:41.851123
731 07:29:41.883273 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000017 00000019 00000018 00000019 00000018 00000019 0000001a 00000018 00000017 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
732 07:29:41.883860 2D training succeed
733 07:29:41.888810 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
734 07:29:41.894432 auto size-- 65535DDR cs0 size: 2048MB
735 07:29:41.894887 DDR cs1 size: 2048MB
736 07:29:41.899975 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
737 07:29:41.900461 cs0 DataBus test pass
738 07:29:41.905547 cs1 DataBus test pass
739 07:29:41.905985 cs0 AddrBus test pass
740 07:29:41.906383 cs1 AddrBus test pass
741 07:29:41.906776
742 07:29:41.911201 100bdlr_step_size ps== 420
743 07:29:41.911651 result report
744 07:29:41.916746 boot times 0Enable ddr reg access
745 07:29:41.922131 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
746 07:29:41.934665 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
747 07:29:42.507583 0.0;M3 CHK:0;cm4_sp_mode 0
748 07:29:42.508224 MVN_1=0x00000000
749 07:29:42.513062 MVN_2=0x00000000
750 07:29:42.518948 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
751 07:29:42.519477 OPS=0x10
752 07:29:42.519883 ring efuse init
753 07:29:42.520326 chipver efuse init
754 07:29:42.527168 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
755 07:29:42.527748 [0.018961 Inits done]
756 07:29:42.534696 secure task start!
757 07:29:42.535241 high task start!
758 07:29:42.535698 low task start!
759 07:29:42.536282 run into bl31
760 07:29:42.541336 NOTICE: BL31: v1.3(release):4fc40b1
761 07:29:42.549187 NOTICE: BL31: Built : 15:58:17, May 22 2019
762 07:29:42.549728 NOTICE: BL31: G12A normal boot!
763 07:29:42.574628 NOTICE: BL31: BL33 decompress pass
764 07:29:42.580213 ERROR: Error initializing runtime service opteed_fast
765 07:29:43.813019
766 07:29:43.813609
767 07:29:43.821428 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
768 07:29:43.821928
769 07:29:43.822335 Model: Libre Computer AML-A311D-CC Alta
770 07:29:44.028998 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
771 07:29:44.052363 DRAM: 2 GiB (effective 3.8 GiB)
772 07:29:44.196277 Core: 408 devices, 31 uclasses, devicetree: separate
773 07:29:44.201707 WDT: Not starting watchdog@f0d0
774 07:29:44.234312 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
775 07:29:44.246781 Loading Environment from FAT... Card did not respond to voltage select! : -110
776 07:29:44.251762 ** Bad device specification mmc 0 **
777 07:29:44.262131 Card did not respond to voltage select! : -110
778 07:29:44.269002 ** Bad device specification mmc 0 **
779 07:29:44.269502 Couldn't find partition mmc 0
780 07:29:44.278101 Card did not respond to voltage select! : -110
781 07:29:44.283696 ** Bad device specification mmc 0 **
782 07:29:44.284169 Couldn't find partition mmc 0
783 07:29:44.288751 Error: could not access storage.
784 07:29:44.631217 Net: eth0: ethernet@ff3f0000
785 07:29:44.631793 starting USB...
786 07:29:44.883049 Bus usb@ff500000: Register 3000140 NbrPorts 3
787 07:29:44.883614 Starting the controller
788 07:29:44.889919 USB XHCI 1.10
789 07:29:47.231480 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
790 07:29:47.232125 bl2_stage_init 0x01
791 07:29:47.232563 bl2_stage_init 0x81
792 07:29:47.232983 hw id: 0x0000 - pwm id 0x01
793 07:29:47.233395 bl2_stage_init 0xc1
794 07:29:47.233801 bl2_stage_init 0x02
795 07:29:47.234202
796 07:29:47.235021 L0:00000000
797 07:29:47.235456 L1:20000703
798 07:29:47.235866 L2:00008067
799 07:29:47.236317 L3:14000000
800 07:29:47.236725 B2:00402000
801 07:29:47.237121 B1:e0f83180
802 07:29:47.237515
803 07:29:47.237914 TE: 58124
804 07:29:47.238308
805 07:29:47.238706 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
806 07:29:47.239104
807 07:29:47.239496 Board ID = 1
808 07:29:47.239884 Set A53 clk to 24M
809 07:29:47.240311 Set A73 clk to 24M
810 07:29:47.240711 Set clk81 to 24M
811 07:29:47.241103 A53 clk: 1200 MHz
812 07:29:47.241498 A73 clk: 1200 MHz
813 07:29:47.241886 CLK81: 166.6M
814 07:29:47.242276 smccc: 00012a92
815 07:29:47.242666 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
816 07:29:47.243057 board id: 1
817 07:29:47.243446 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
818 07:29:47.243843 fw parse done
819 07:29:47.244271 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
820 07:29:47.244674 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
821 07:29:47.245069 PIEI prepare done
822 07:29:47.245455 fastboot data load
823 07:29:47.245848 fastboot data verify
824 07:29:47.246236 verify result: 266
825 07:29:47.246622 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
826 07:29:47.247009 LPDDR4 probe
827 07:29:47.247393 ddr clk to 1584MHz
828 07:29:47.247874 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
829 07:29:47.248314
830 07:29:47.248709 dmc_version 0001
831 07:29:47.249099 Check phy result
832 07:29:47.249488 INFO : End of CA training
833 07:29:47.249876 INFO : End of initialization
834 07:29:47.251384 INFO : Training has run successfully!
835 07:29:47.251831 Check phy result
836 07:29:47.256257 INFO : End of initialization
837 07:29:47.256710 INFO : End of read enable training
838 07:29:47.259588 INFO : End of fine write leveling
839 07:29:47.265091 INFO : End of Write leveling coarse delay
840 07:29:47.270693 INFO : Training has run successfully!
841 07:29:47.271129 Check phy result
842 07:29:47.271536 INFO : End of initialization
843 07:29:47.276268 INFO : End of read dq deskew training
844 07:29:47.281862 INFO : End of MPR read delay center optimization
845 07:29:47.282304 INFO : End of write delay center optimization
846 07:29:47.287494 INFO : End of read delay center optimization
847 07:29:47.293104 INFO : End of max read latency training
848 07:29:47.293618 INFO : Training has run successfully!
849 07:29:47.298692 1D training succeed
850 07:29:47.304732 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
851 07:29:47.351162 Check phy result
852 07:29:47.351677 INFO : End of initialization
853 07:29:47.373886 INFO : End of 2D read delay Voltage center optimization
854 07:29:47.394456 INFO : End of 2D read delay Voltage center optimization
855 07:29:47.446321 INFO : End of 2D write delay Voltage center optimization
856 07:29:47.495694 INFO : End of 2D write delay Voltage center optimization
857 07:29:47.501121 INFO : Training has run successfully!
858 07:29:47.501580
859 07:29:47.502001 channel==0
860 07:29:47.506679 RxClkDly_Margin_A0==88 ps 9
861 07:29:47.507119 TxDqDly_Margin_A0==98 ps 10
862 07:29:47.512316 RxClkDly_Margin_A1==88 ps 9
863 07:29:47.512759 TxDqDly_Margin_A1==98 ps 10
864 07:29:47.513185 TrainedVREFDQ_A0==74
865 07:29:47.518032 TrainedVREFDQ_A1==74
866 07:29:47.518525 VrefDac_Margin_A0==25
867 07:29:47.518941 DeviceVref_Margin_A0==40
868 07:29:47.523537 VrefDac_Margin_A1==25
869 07:29:47.524026 DeviceVref_Margin_A1==40
870 07:29:47.524423
871 07:29:47.524814
872 07:29:47.529085 channel==1
873 07:29:47.529504 RxClkDly_Margin_A0==98 ps 10
874 07:29:47.529895 TxDqDly_Margin_A0==98 ps 10
875 07:29:47.534718 RxClkDly_Margin_A1==98 ps 10
876 07:29:47.535142 TxDqDly_Margin_A1==88 ps 9
877 07:29:47.540363 TrainedVREFDQ_A0==77
878 07:29:47.540787 TrainedVREFDQ_A1==77
879 07:29:47.541175 VrefDac_Margin_A0==22
880 07:29:47.545998 DeviceVref_Margin_A0==37
881 07:29:47.546408 VrefDac_Margin_A1==22
882 07:29:47.551492 DeviceVref_Margin_A1==37
883 07:29:47.551909
884 07:29:47.552334 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
885 07:29:47.557114
886 07:29:47.585124 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000018 00000019 00000017 00000019 00000018 0000001a 0000001a 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
887 07:29:47.585606 2D training succeed
888 07:29:47.590679 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
889 07:29:47.596322 auto size-- 65535DDR cs0 size: 2048MB
890 07:29:47.596748 DDR cs1 size: 2048MB
891 07:29:47.601908 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
892 07:29:47.602329 cs0 DataBus test pass
893 07:29:47.607515 cs1 DataBus test pass
894 07:29:47.607935 cs0 AddrBus test pass
895 07:29:47.608375 cs1 AddrBus test pass
896 07:29:47.608761
897 07:29:47.613117 100bdlr_step_size ps== 420
898 07:29:47.613549 result report
899 07:29:47.618723 boot times 0Enable ddr reg access
900 07:29:47.624208 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
901 07:29:47.636819 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
902 07:29:48.211304 0.0;M3 CHK:0;cm4_sp_mode 0
903 07:29:48.212071 MVN_1=0x00000000
904 07:29:48.216818 MVN_2=0x00000000
905 07:29:48.222575 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
906 07:29:48.223149 OPS=0x10
907 07:29:48.223594 ring efuse init
908 07:29:48.224095 chipver efuse init
909 07:29:48.228267 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
910 07:29:48.233674 [0.018961 Inits done]
911 07:29:48.234160 secure task start!
912 07:29:48.234586 high task start!
913 07:29:48.238324 low task start!
914 07:29:48.238795 run into bl31
915 07:29:48.244958 NOTICE: BL31: v1.3(release):4fc40b1
916 07:29:48.251884 NOTICE: BL31: Built : 15:58:17, May 22 2019
917 07:29:48.252410 NOTICE: BL31: G12A normal boot!
918 07:29:48.278170 NOTICE: BL31: BL33 decompress pass
919 07:29:48.283737 ERROR: Error initializing runtime service opteed_fast
920 07:29:49.516654
921 07:29:49.517072
922 07:29:49.525050 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
923 07:29:49.525506
924 07:29:49.525854 Model: Libre Computer AML-A311D-CC Alta
925 07:29:49.733558 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
926 07:29:49.756908 DRAM: 2 GiB (effective 3.8 GiB)
927 07:29:49.899908 Core: 408 devices, 31 uclasses, devicetree: separate
928 07:29:49.905758 WDT: Not starting watchdog@f0d0
929 07:29:49.938009 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
930 07:29:49.950474 Loading Environment from FAT... Card did not respond to voltage select! : -110
931 07:29:49.955411 ** Bad device specification mmc 0 **
932 07:29:49.965772 Card did not respond to voltage select! : -110
933 07:29:49.973406 ** Bad device specification mmc 0 **
934 07:29:49.973766 Couldn't find partition mmc 0
935 07:29:49.981767 Card did not respond to voltage select! : -110
936 07:29:49.987272 ** Bad device specification mmc 0 **
937 07:29:49.987751 Couldn't find partition mmc 0
938 07:29:49.992360 Error: could not access storage.
939 07:29:50.494586 Net: eth0: ethernet@ff3f0000
940 07:29:50.495030 starting USB...
941 07:29:50.587676 Bus usb@ff500000: Register 3000140 NbrPorts 3
942 07:29:50.588107 Starting the controller
943 07:29:50.594658 USB XHCI 1.10
944 07:29:52.455551 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
945 07:29:52.456332 bl2_stage_init 0x01
946 07:29:52.456819 bl2_stage_init 0x81
947 07:29:52.461151 hw id: 0x0000 - pwm id 0x01
948 07:29:52.461671 bl2_stage_init 0xc1
949 07:29:52.462135 bl2_stage_init 0x02
950 07:29:52.462592
951 07:29:52.466755 L0:00000000
952 07:29:52.467271 L1:20000703
953 07:29:52.467731 L2:00008067
954 07:29:52.468213 L3:14000000
955 07:29:52.472249 B2:00402000
956 07:29:52.472773 B1:e0f83180
957 07:29:52.473233
958 07:29:52.473685 TE: 58159
959 07:29:52.474133
960 07:29:52.477949 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
961 07:29:52.478466
962 07:29:52.478924 Board ID = 1
963 07:29:52.483526 Set A53 clk to 24M
964 07:29:52.484062 Set A73 clk to 24M
965 07:29:52.484520 Set clk81 to 24M
966 07:29:52.489059 A53 clk: 1200 MHz
967 07:29:52.489578 A73 clk: 1200 MHz
968 07:29:52.490030 CLK81: 166.6M
969 07:29:52.490471 smccc: 00012ab5
970 07:29:52.494752 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
971 07:29:52.500338 board id: 1
972 07:29:52.506233 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
973 07:29:52.516767 fw parse done
974 07:29:52.522968 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
975 07:29:52.565285 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
976 07:29:52.576195 PIEI prepare done
977 07:29:52.576706 fastboot data load
978 07:29:52.577148 fastboot data verify
979 07:29:52.581815 verify result: 266
980 07:29:52.587426 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
981 07:29:52.587917 LPDDR4 probe
982 07:29:52.588404 ddr clk to 1584MHz
983 07:29:52.595423 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
984 07:29:52.632639
985 07:29:52.633141 dmc_version 0001
986 07:29:52.638434 Check phy result
987 07:29:52.645221 INFO : End of CA training
988 07:29:52.645708 INFO : End of initialization
989 07:29:52.650784 INFO : Training has run successfully!
990 07:29:52.651271 Check phy result
991 07:29:52.656413 INFO : End of initialization
992 07:29:52.656904 INFO : End of read enable training
993 07:29:52.662014 INFO : End of fine write leveling
994 07:29:52.667706 INFO : End of Write leveling coarse delay
995 07:29:52.668248 INFO : Training has run successfully!
996 07:29:52.668701 Check phy result
997 07:29:52.673233 INFO : End of initialization
998 07:29:52.673734 INFO : End of read dq deskew training
999 07:29:52.678834 INFO : End of MPR read delay center optimization
1000 07:29:52.684400 INFO : End of write delay center optimization
1001 07:29:52.690045 INFO : End of read delay center optimization
1002 07:29:52.690544 INFO : End of max read latency training
1003 07:29:52.695658 INFO : Training has run successfully!
1004 07:29:52.696198 1D training succeed
1005 07:29:52.704767 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
1006 07:29:52.752394 Check phy result
1007 07:29:52.752895 INFO : End of initialization
1008 07:29:52.774059 INFO : End of 2D read delay Voltage center optimization
1009 07:29:52.794326 INFO : End of 2D read delay Voltage center optimization
1010 07:29:52.846331 INFO : End of 2D write delay Voltage center optimization
1011 07:29:52.895699 INFO : End of 2D write delay Voltage center optimization
1012 07:29:52.901316 INFO : Training has run successfully!
1013 07:29:52.901823
1014 07:29:52.902281 channel==0
1015 07:29:52.906881 RxClkDly_Margin_A0==69 ps 7
1016 07:29:52.907383 TxDqDly_Margin_A0==98 ps 10
1017 07:29:52.912484 RxClkDly_Margin_A1==88 ps 9
1018 07:29:52.912984 TxDqDly_Margin_A1==98 ps 10
1019 07:29:52.913439 TrainedVREFDQ_A0==74
1020 07:29:52.918107 TrainedVREFDQ_A1==74
1021 07:29:52.918614 VrefDac_Margin_A0==25
1022 07:29:52.919069 DeviceVref_Margin_A0==40
1023 07:29:52.923703 VrefDac_Margin_A1==25
1024 07:29:52.924230 DeviceVref_Margin_A1==40
1025 07:29:52.924680
1026 07:29:52.925125
1027 07:29:52.929287 channel==1
1028 07:29:52.929785 RxClkDly_Margin_A0==98 ps 10
1029 07:29:52.930237 TxDqDly_Margin_A0==98 ps 10
1030 07:29:52.934921 RxClkDly_Margin_A1==98 ps 10
1031 07:29:52.935423 TxDqDly_Margin_A1==88 ps 9
1032 07:29:52.940444 TrainedVREFDQ_A0==77
1033 07:29:52.940949 TrainedVREFDQ_A1==77
1034 07:29:52.941401 VrefDac_Margin_A0==22
1035 07:29:52.946085 DeviceVref_Margin_A0==37
1036 07:29:52.946581 VrefDac_Margin_A1==23
1037 07:29:52.951707 DeviceVref_Margin_A1==37
1038 07:29:52.952229
1039 07:29:52.952680 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
1040 07:29:52.957286
1041 07:29:52.985241 soc_vref_reg_value 0x 00000019 0000001a 00000018 00000019 00000018 00000019 00000018 00000018 00000018 00000016 00000017 00000015 00000018 00000019 00000018 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000017 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
1042 07:29:52.985795 2D training succeed
1043 07:29:52.990858 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
1044 07:29:52.996449 auto size-- 65535DDR cs0 size: 2048MB
1045 07:29:52.996956 DDR cs1 size: 2048MB
1046 07:29:53.002082 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
1047 07:29:53.002591 cs0 DataBus test pass
1048 07:29:53.007753 cs1 DataBus test pass
1049 07:29:53.008296 cs0 AddrBus test pass
1050 07:29:53.008746 cs1 AddrBus test pass
1051 07:29:53.009185
1052 07:29:53.013329 100bdlr_step_size ps== 420
1053 07:29:53.013852 result report
1054 07:29:53.018926 boot times 0Enable ddr reg access
1055 07:29:53.024381 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
1056 07:29:53.037807 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
1057 07:29:53.611494 0.0;M3 CHK:0;cm4_sp_mode 0
1058 07:29:53.612201 MVN_1=0x00000000
1059 07:29:53.617076 MVN_2=0x00000000
1060 07:29:53.622816 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
1061 07:29:53.623320 OPS=0x10
1062 07:29:53.623778 ring efuse init
1063 07:29:53.624262 chipver efuse init
1064 07:29:53.628403 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
1065 07:29:53.634009 [0.018961 Inits done]
1066 07:29:53.634510 secure task start!
1067 07:29:53.634956 high task start!
1068 07:29:53.638596 low task start!
1069 07:29:53.639097 run into bl31
1070 07:29:53.645232 NOTICE: BL31: v1.3(release):4fc40b1
1071 07:29:53.653059 NOTICE: BL31: Built : 15:58:17, May 22 2019
1072 07:29:53.653563 NOTICE: BL31: G12A normal boot!
1073 07:29:53.678368 NOTICE: BL31: BL33 decompress pass
1074 07:29:53.684111 ERROR: Error initializing runtime service opteed_fast
1075 07:29:54.916962
1076 07:29:54.917614
1077 07:29:54.925505 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
1078 07:29:54.926032
1079 07:29:54.926494 Model: Libre Computer AML-A311D-CC Alta
1080 07:29:55.133893 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
1081 07:29:55.157244 DRAM: 2 GiB (effective 3.8 GiB)
1082 07:29:55.300218 Core: 408 devices, 31 uclasses, devicetree: separate
1083 07:29:55.306137 WDT: Not starting watchdog@f0d0
1084 07:29:55.338366 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
1085 07:29:55.350819 Loading Environment from FAT... Card did not respond to voltage select! : -110
1086 07:29:55.355837 ** Bad device specification mmc 0 **
1087 07:29:55.366195 Card did not respond to voltage select! : -110
1088 07:29:55.373817 ** Bad device specification mmc 0 **
1089 07:29:55.374363 Couldn't find partition mmc 0
1090 07:29:55.382137 Card did not respond to voltage select! : -110
1091 07:29:55.387646 ** Bad device specification mmc 0 **
1092 07:29:55.388198 Couldn't find partition mmc 0
1093 07:29:55.392721 Error: could not access storage.
1094 07:29:55.735152 Net: eth0: ethernet@ff3f0000
1095 07:29:55.735708 starting USB...
1096 07:29:55.986919 Bus usb@ff500000: Register 3000140 NbrPorts 3
1097 07:29:55.987460 Starting the controller
1098 07:29:55.993951 USB XHCI 1.10
1099 07:29:57.551037 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
1100 07:29:57.559567 scanning usb for storage devices... 0 Storage Device(s) found
1102 07:29:57.611269 Hit any key to stop autoboot: 1
1103 07:29:57.612133 end: 2.4.2 bootloader-interrupt (duration 00:00:37) [common]
1104 07:29:57.612832 start: 2.4.3 bootloader-commands (timeout 00:04:23) [common]
1105 07:29:57.613346 Setting prompt string to ['=>']
1106 07:29:57.613868 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:23)
1107 07:29:57.626975 0
1108 07:29:57.627915 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1109 07:29:57.628483 Sending with 10 millisecond of delay
1111 07:29:58.763163 => setenv autoload no
1112 07:29:58.774032 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:22)
1113 07:29:58.779451 setenv autoload no
1114 07:29:58.780272 Sending with 10 millisecond of delay
1116 07:30:00.577161 => setenv initrd_high 0xffffffff
1117 07:30:00.588037 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:20)
1118 07:30:00.589027 setenv initrd_high 0xffffffff
1119 07:30:00.589801 Sending with 10 millisecond of delay
1121 07:30:02.206129 => setenv fdt_high 0xffffffff
1122 07:30:02.216847 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1123 07:30:02.217341 setenv fdt_high 0xffffffff
1124 07:30:02.217828 Sending with 10 millisecond of delay
1126 07:30:02.509210 => dhcp
1127 07:30:02.519931 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1128 07:30:02.520454 dhcp
1129 07:30:02.520693 Speed: 1000, full duplex
1130 07:30:02.520922 BOOTP broadcast 1
1131 07:30:02.604143 DHCP client bound to address 192.168.6.27 (84 ms)
1132 07:30:02.605190 Sending with 10 millisecond of delay
1134 07:30:04.283001 => setenv serverip 192.168.6.2
1135 07:30:04.294266 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:16)
1136 07:30:04.295640 setenv serverip 192.168.6.2
1137 07:30:04.296845 Sending with 10 millisecond of delay
1139 07:30:08.025294 => tftpboot 0x01080000 978425/tftp-deploy-dz3xfdac/kernel/uImage
1140 07:30:08.036181 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:12)
1141 07:30:08.037180 tftpboot 0x01080000 978425/tftp-deploy-dz3xfdac/kernel/uImage
1142 07:30:08.037668 Speed: 1000, full duplex
1143 07:30:08.038114 Using ethernet@ff3f0000 device
1144 07:30:08.038973 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1145 07:30:08.044397 Filename '978425/tftp-deploy-dz3xfdac/kernel/uImage'.
1146 07:30:08.048377 Load address: 0x1080000
1147 07:30:12.284633 Loading: *#################################################
1148 07:30:12.285259 TFTP error: trying to overwrite reserved memory...
1150 07:30:12.286632 end: 2.4.3 bootloader-commands (duration 00:00:15) [common]
1153 07:30:12.288517 end: 2.4 uboot-commands (duration 00:00:52) [common]
1155 07:30:12.289891 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'TFTP error: trying to overwrite reserved memory' (12)'
1157 07:30:12.290945 end: 2 uboot-action (duration 00:00:52) [common]
1159 07:30:12.292502 Cleaning after the job
1160 07:30:12.293074 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/978425/tftp-deploy-dz3xfdac/ramdisk
1161 07:30:12.309049 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/978425/tftp-deploy-dz3xfdac/kernel
1162 07:30:12.338907 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/978425/tftp-deploy-dz3xfdac/dtb
1163 07:30:12.339714 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/978425/tftp-deploy-dz3xfdac/nfsrootfs
1164 07:30:12.494235 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/978425/tftp-deploy-dz3xfdac/modules
1165 07:30:12.523754 start: 4.1 power-off (timeout 00:00:30) [common]
1166 07:30:12.524443 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1167 07:30:12.557642 >> OK - accepted request
1168 07:30:12.559284 Returned 0 in 0 seconds
1169 07:30:12.660008 end: 4.1 power-off (duration 00:00:00) [common]
1171 07:30:12.660950 start: 4.2 read-feedback (timeout 00:10:00) [common]
1172 07:30:12.661606 Listened to connection for namespace 'common' for up to 1s
1173 07:30:13.662556 Finalising connection for namespace 'common'
1174 07:30:13.663030 Disconnecting from shell: Finalise
1175 07:30:13.663328 =>
1176 07:30:13.764217 end: 4.2 read-feedback (duration 00:00:01) [common]
1177 07:30:13.764895 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/978425
1178 07:30:15.697082 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/978425
1179 07:30:15.697721 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.