Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 07:58:55.354333 lava-dispatcher, installed at version: 2024.01
2 07:58:55.355134 start: 0 validate
3 07:58:55.355643 Start time: 2024-11-12 07:58:55.355613+00:00 (UTC)
4 07:58:55.356225 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 07:58:55.356777 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-igt%2F20240313.0%2Farm64%2Frootfs.cpio.gz exists
6 07:58:55.393886 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 07:58:55.394405 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241112%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 07:58:55.428836 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 07:58:55.429449 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241112%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 07:58:55.460722 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 07:58:55.461242 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241112%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
12 07:58:55.498390 validate duration: 0.14
14 07:58:55.499236 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 07:58:55.499581 start: 1.1 download-retry (timeout 00:10:00) [common]
16 07:58:55.499887 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 07:58:55.500734 Not decompressing ramdisk as can be used compressed.
18 07:58:55.501509 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-igt/20240313.0/arm64/rootfs.cpio.gz
19 07:58:55.501823 saving as /var/lib/lava/dispatcher/tmp/978589/tftp-deploy-cizhol9x/ramdisk/rootfs.cpio.gz
20 07:58:55.502081 total size: 47897469 (45 MB)
21 07:58:55.537435 progress 0 % (0 MB)
22 07:58:55.566552 progress 5 % (2 MB)
23 07:58:55.594177 progress 10 % (4 MB)
24 07:58:55.621798 progress 15 % (6 MB)
25 07:58:55.649506 progress 20 % (9 MB)
26 07:58:55.677089 progress 25 % (11 MB)
27 07:58:55.704742 progress 30 % (13 MB)
28 07:58:55.732648 progress 35 % (16 MB)
29 07:58:55.760210 progress 40 % (18 MB)
30 07:58:55.787737 progress 45 % (20 MB)
31 07:58:55.815260 progress 50 % (22 MB)
32 07:58:55.842855 progress 55 % (25 MB)
33 07:58:55.870674 progress 60 % (27 MB)
34 07:58:55.898108 progress 65 % (29 MB)
35 07:58:55.925701 progress 70 % (32 MB)
36 07:58:55.953173 progress 75 % (34 MB)
37 07:58:55.980624 progress 80 % (36 MB)
38 07:58:56.008467 progress 85 % (38 MB)
39 07:58:56.036341 progress 90 % (41 MB)
40 07:58:56.063829 progress 95 % (43 MB)
41 07:58:56.092437 progress 100 % (45 MB)
42 07:58:56.093186 45 MB downloaded in 0.59 s (77.28 MB/s)
43 07:58:56.093736 end: 1.1.1 http-download (duration 00:00:01) [common]
45 07:58:56.094633 end: 1.1 download-retry (duration 00:00:01) [common]
46 07:58:56.094925 start: 1.2 download-retry (timeout 00:09:59) [common]
47 07:58:56.095193 start: 1.2.1 http-download (timeout 00:09:59) [common]
48 07:58:56.095666 downloading http://storage.kernelci.org/next/master/next-20241112/arm64/defconfig/gcc-12/kernel/Image
49 07:58:56.095916 saving as /var/lib/lava/dispatcher/tmp/978589/tftp-deploy-cizhol9x/kernel/Image
50 07:58:56.096152 total size: 46121472 (43 MB)
51 07:58:56.096364 No compression specified
52 07:58:56.132679 progress 0 % (0 MB)
53 07:58:56.160331 progress 5 % (2 MB)
54 07:58:56.187356 progress 10 % (4 MB)
55 07:58:56.214816 progress 15 % (6 MB)
56 07:58:56.241882 progress 20 % (8 MB)
57 07:58:56.268667 progress 25 % (11 MB)
58 07:58:56.295877 progress 30 % (13 MB)
59 07:58:56.322939 progress 35 % (15 MB)
60 07:58:56.350263 progress 40 % (17 MB)
61 07:58:56.377583 progress 45 % (19 MB)
62 07:58:56.404324 progress 50 % (22 MB)
63 07:58:56.431300 progress 55 % (24 MB)
64 07:58:56.457807 progress 60 % (26 MB)
65 07:58:56.484315 progress 65 % (28 MB)
66 07:58:56.511208 progress 70 % (30 MB)
67 07:58:56.537933 progress 75 % (33 MB)
68 07:58:56.565445 progress 80 % (35 MB)
69 07:58:56.592365 progress 85 % (37 MB)
70 07:58:56.619123 progress 90 % (39 MB)
71 07:58:56.646392 progress 95 % (41 MB)
72 07:58:56.672081 progress 100 % (43 MB)
73 07:58:56.672734 43 MB downloaded in 0.58 s (76.29 MB/s)
74 07:58:56.673227 end: 1.2.1 http-download (duration 00:00:01) [common]
76 07:58:56.674036 end: 1.2 download-retry (duration 00:00:01) [common]
77 07:58:56.674311 start: 1.3 download-retry (timeout 00:09:59) [common]
78 07:58:56.674575 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 07:58:56.675049 downloading http://storage.kernelci.org/next/master/next-20241112/arm64/defconfig/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
80 07:58:56.675300 saving as /var/lib/lava/dispatcher/tmp/978589/tftp-deploy-cizhol9x/dtb/meson-g12b-a311d-libretech-cc.dtb
81 07:58:56.675506 total size: 54703 (0 MB)
82 07:58:56.675716 No compression specified
83 07:58:56.713948 progress 59 % (0 MB)
84 07:58:56.715032 progress 100 % (0 MB)
85 07:58:56.715782 0 MB downloaded in 0.04 s (1.30 MB/s)
86 07:58:56.716489 end: 1.3.1 http-download (duration 00:00:00) [common]
88 07:58:56.717639 end: 1.3 download-retry (duration 00:00:00) [common]
89 07:58:56.718044 start: 1.4 download-retry (timeout 00:09:59) [common]
90 07:58:56.718447 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 07:58:56.719084 downloading http://storage.kernelci.org/next/master/next-20241112/arm64/defconfig/gcc-12/modules.tar.xz
92 07:58:56.719431 saving as /var/lib/lava/dispatcher/tmp/978589/tftp-deploy-cizhol9x/modules/modules.tar
93 07:58:56.719728 total size: 11690048 (11 MB)
94 07:58:56.720059 Using unxz to decompress xz
95 07:58:56.754945 progress 0 % (0 MB)
96 07:58:56.820815 progress 5 % (0 MB)
97 07:58:56.894401 progress 10 % (1 MB)
98 07:58:56.989994 progress 15 % (1 MB)
99 07:58:57.086179 progress 20 % (2 MB)
100 07:58:57.165416 progress 25 % (2 MB)
101 07:58:57.241122 progress 30 % (3 MB)
102 07:58:57.315529 progress 35 % (3 MB)
103 07:58:57.415036 progress 40 % (4 MB)
104 07:58:57.515120 progress 45 % (5 MB)
105 07:58:57.625507 progress 50 % (5 MB)
106 07:58:57.732308 progress 55 % (6 MB)
107 07:58:57.844616 progress 60 % (6 MB)
108 07:58:57.942559 progress 65 % (7 MB)
109 07:58:58.045004 progress 70 % (7 MB)
110 07:58:58.127459 progress 75 % (8 MB)
111 07:58:58.211218 progress 80 % (8 MB)
112 07:58:58.291095 progress 85 % (9 MB)
113 07:58:58.374512 progress 90 % (10 MB)
114 07:58:58.448020 progress 95 % (10 MB)
115 07:58:58.524499 progress 100 % (11 MB)
116 07:58:58.538065 11 MB downloaded in 1.82 s (6.13 MB/s)
117 07:58:58.539025 end: 1.4.1 http-download (duration 00:00:02) [common]
119 07:58:58.540834 end: 1.4 download-retry (duration 00:00:02) [common]
120 07:58:58.541416 start: 1.5 prepare-tftp-overlay (timeout 00:09:57) [common]
121 07:58:58.541988 start: 1.5.1 extract-nfsrootfs (timeout 00:09:57) [common]
122 07:58:58.542534 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 07:58:58.543089 start: 1.5.2 lava-overlay (timeout 00:09:57) [common]
124 07:58:58.544163 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/978589/lava-overlay-h8zp13w4
125 07:58:58.545080 makedir: /var/lib/lava/dispatcher/tmp/978589/lava-overlay-h8zp13w4/lava-978589/bin
126 07:58:58.545770 makedir: /var/lib/lava/dispatcher/tmp/978589/lava-overlay-h8zp13w4/lava-978589/tests
127 07:58:58.546443 makedir: /var/lib/lava/dispatcher/tmp/978589/lava-overlay-h8zp13w4/lava-978589/results
128 07:58:58.547105 Creating /var/lib/lava/dispatcher/tmp/978589/lava-overlay-h8zp13w4/lava-978589/bin/lava-add-keys
129 07:58:58.548196 Creating /var/lib/lava/dispatcher/tmp/978589/lava-overlay-h8zp13w4/lava-978589/bin/lava-add-sources
130 07:58:58.549224 Creating /var/lib/lava/dispatcher/tmp/978589/lava-overlay-h8zp13w4/lava-978589/bin/lava-background-process-start
131 07:58:58.550296 Creating /var/lib/lava/dispatcher/tmp/978589/lava-overlay-h8zp13w4/lava-978589/bin/lava-background-process-stop
132 07:58:58.551444 Creating /var/lib/lava/dispatcher/tmp/978589/lava-overlay-h8zp13w4/lava-978589/bin/lava-common-functions
133 07:58:58.552555 Creating /var/lib/lava/dispatcher/tmp/978589/lava-overlay-h8zp13w4/lava-978589/bin/lava-echo-ipv4
134 07:58:58.553604 Creating /var/lib/lava/dispatcher/tmp/978589/lava-overlay-h8zp13w4/lava-978589/bin/lava-install-packages
135 07:58:58.554689 Creating /var/lib/lava/dispatcher/tmp/978589/lava-overlay-h8zp13w4/lava-978589/bin/lava-installed-packages
136 07:58:58.555678 Creating /var/lib/lava/dispatcher/tmp/978589/lava-overlay-h8zp13w4/lava-978589/bin/lava-os-build
137 07:58:58.556761 Creating /var/lib/lava/dispatcher/tmp/978589/lava-overlay-h8zp13w4/lava-978589/bin/lava-probe-channel
138 07:58:58.557762 Creating /var/lib/lava/dispatcher/tmp/978589/lava-overlay-h8zp13w4/lava-978589/bin/lava-probe-ip
139 07:58:58.558760 Creating /var/lib/lava/dispatcher/tmp/978589/lava-overlay-h8zp13w4/lava-978589/bin/lava-target-ip
140 07:58:58.559780 Creating /var/lib/lava/dispatcher/tmp/978589/lava-overlay-h8zp13w4/lava-978589/bin/lava-target-mac
141 07:58:58.560859 Creating /var/lib/lava/dispatcher/tmp/978589/lava-overlay-h8zp13w4/lava-978589/bin/lava-target-storage
142 07:58:58.561965 Creating /var/lib/lava/dispatcher/tmp/978589/lava-overlay-h8zp13w4/lava-978589/bin/lava-test-case
143 07:58:58.562984 Creating /var/lib/lava/dispatcher/tmp/978589/lava-overlay-h8zp13w4/lava-978589/bin/lava-test-event
144 07:58:58.563969 Creating /var/lib/lava/dispatcher/tmp/978589/lava-overlay-h8zp13w4/lava-978589/bin/lava-test-feedback
145 07:58:58.565019 Creating /var/lib/lava/dispatcher/tmp/978589/lava-overlay-h8zp13w4/lava-978589/bin/lava-test-raise
146 07:58:58.566011 Creating /var/lib/lava/dispatcher/tmp/978589/lava-overlay-h8zp13w4/lava-978589/bin/lava-test-reference
147 07:58:58.567009 Creating /var/lib/lava/dispatcher/tmp/978589/lava-overlay-h8zp13w4/lava-978589/bin/lava-test-runner
148 07:58:58.568019 Creating /var/lib/lava/dispatcher/tmp/978589/lava-overlay-h8zp13w4/lava-978589/bin/lava-test-set
149 07:58:58.569029 Creating /var/lib/lava/dispatcher/tmp/978589/lava-overlay-h8zp13w4/lava-978589/bin/lava-test-shell
150 07:58:58.570009 Updating /var/lib/lava/dispatcher/tmp/978589/lava-overlay-h8zp13w4/lava-978589/bin/lava-install-packages (oe)
151 07:58:58.571101 Updating /var/lib/lava/dispatcher/tmp/978589/lava-overlay-h8zp13w4/lava-978589/bin/lava-installed-packages (oe)
152 07:58:58.572074 Creating /var/lib/lava/dispatcher/tmp/978589/lava-overlay-h8zp13w4/lava-978589/environment
153 07:58:58.572947 LAVA metadata
154 07:58:58.573487 - LAVA_JOB_ID=978589
155 07:58:58.573959 - LAVA_DISPATCHER_IP=192.168.6.2
156 07:58:58.574695 start: 1.5.2.1 ssh-authorize (timeout 00:09:57) [common]
157 07:58:58.576713 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 07:58:58.577369 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:57) [common]
159 07:58:58.577836 skipped lava-vland-overlay
160 07:58:58.578379 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 07:58:58.578938 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:57) [common]
162 07:58:58.579410 skipped lava-multinode-overlay
163 07:58:58.579944 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 07:58:58.580543 start: 1.5.2.4 test-definition (timeout 00:09:57) [common]
165 07:58:58.581075 Loading test definitions
166 07:58:58.581677 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:57) [common]
167 07:58:58.582166 Using /lava-978589 at stage 0
168 07:58:58.584646 uuid=978589_1.5.2.4.1 testdef=None
169 07:58:58.585245 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 07:58:58.585764 start: 1.5.2.4.2 test-overlay (timeout 00:09:57) [common]
171 07:58:58.589102 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 07:58:58.590649 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:57) [common]
174 07:58:58.595358 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 07:58:58.596624 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:57) [common]
177 07:58:58.598830 runner path: /var/lib/lava/dispatcher/tmp/978589/lava-overlay-h8zp13w4/lava-978589/0/tests/0_igt-gpu-panfrost test_uuid 978589_1.5.2.4.1
178 07:58:58.599443 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 07:58:58.600295 Creating lava-test-runner.conf files
181 07:58:58.600507 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/978589/lava-overlay-h8zp13w4/lava-978589/0 for stage 0
182 07:58:58.600882 - 0_igt-gpu-panfrost
183 07:58:58.601245 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 07:58:58.601537 start: 1.5.2.5 compress-overlay (timeout 00:09:57) [common]
185 07:58:58.625380 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 07:58:58.625818 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:57) [common]
187 07:58:58.626095 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 07:58:58.626370 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 07:58:58.626641 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:57) [common]
190 07:59:06.219625 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:08) [common]
191 07:59:06.220193 start: 1.5.4 extract-modules (timeout 00:09:49) [common]
192 07:59:06.220494 extracting modules file /var/lib/lava/dispatcher/tmp/978589/tftp-deploy-cizhol9x/modules/modules.tar to /var/lib/lava/dispatcher/tmp/978589/extract-overlay-ramdisk-plpiyqvt/ramdisk
193 07:59:07.941274 end: 1.5.4 extract-modules (duration 00:00:02) [common]
194 07:59:07.941777 start: 1.5.5 apply-overlay-tftp (timeout 00:09:48) [common]
195 07:59:07.942061 [common] Applying overlay /var/lib/lava/dispatcher/tmp/978589/compress-overlay-7rg9gjlq/overlay-1.5.2.5.tar.gz to ramdisk
196 07:59:07.942275 [common] Applying overlay /var/lib/lava/dispatcher/tmp/978589/compress-overlay-7rg9gjlq/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/978589/extract-overlay-ramdisk-plpiyqvt/ramdisk
197 07:59:07.973128 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 07:59:07.973596 start: 1.5.6 prepare-kernel (timeout 00:09:48) [common]
199 07:59:07.973875 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:48) [common]
200 07:59:07.974107 Converting downloaded kernel to a uImage
201 07:59:07.974434 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/978589/tftp-deploy-cizhol9x/kernel/Image /var/lib/lava/dispatcher/tmp/978589/tftp-deploy-cizhol9x/kernel/uImage
202 07:59:08.441618 output: Image Name:
203 07:59:08.442053 output: Created: Tue Nov 12 07:59:07 2024
204 07:59:08.442266 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 07:59:08.442471 output: Data Size: 46121472 Bytes = 45040.50 KiB = 43.98 MiB
206 07:59:08.442674 output: Load Address: 01080000
207 07:59:08.442876 output: Entry Point: 01080000
208 07:59:08.443077 output:
209 07:59:08.443413 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
210 07:59:08.443683 end: 1.5.6 prepare-kernel (duration 00:00:00) [common]
211 07:59:08.443955 start: 1.5.7 configure-preseed-file (timeout 00:09:47) [common]
212 07:59:08.444268 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 07:59:08.444532 start: 1.5.8 compress-ramdisk (timeout 00:09:47) [common]
214 07:59:08.444787 Building ramdisk /var/lib/lava/dispatcher/tmp/978589/extract-overlay-ramdisk-plpiyqvt/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/978589/extract-overlay-ramdisk-plpiyqvt/ramdisk
215 07:59:14.978914 >> 503722 blocks
216 07:59:35.886455 Adding RAMdisk u-boot header.
217 07:59:35.886892 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/978589/extract-overlay-ramdisk-plpiyqvt/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/978589/extract-overlay-ramdisk-plpiyqvt/ramdisk.cpio.gz.uboot
218 07:59:36.553588 output: Image Name:
219 07:59:36.554264 output: Created: Tue Nov 12 07:59:35 2024
220 07:59:36.554725 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 07:59:36.555173 output: Data Size: 65844169 Bytes = 64300.95 KiB = 62.79 MiB
222 07:59:36.555611 output: Load Address: 00000000
223 07:59:36.556103 output: Entry Point: 00000000
224 07:59:36.556549 output:
225 07:59:36.557559 rename /var/lib/lava/dispatcher/tmp/978589/extract-overlay-ramdisk-plpiyqvt/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/978589/tftp-deploy-cizhol9x/ramdisk/ramdisk.cpio.gz.uboot
226 07:59:36.558529 end: 1.5.8 compress-ramdisk (duration 00:00:28) [common]
227 07:59:36.559210 end: 1.5 prepare-tftp-overlay (duration 00:00:38) [common]
228 07:59:36.559818 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:19) [common]
229 07:59:36.560373 No LXC device requested
230 07:59:36.560941 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 07:59:36.561504 start: 1.7 deploy-device-env (timeout 00:09:19) [common]
232 07:59:36.562044 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 07:59:36.562494 Checking files for TFTP limit of 4294967296 bytes.
234 07:59:36.565454 end: 1 tftp-deploy (duration 00:00:41) [common]
235 07:59:36.566115 start: 2 uboot-action (timeout 00:05:00) [common]
236 07:59:36.566745 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 07:59:36.567380 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 07:59:36.568038 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 07:59:36.568681 Using kernel file from prepare-kernel: 978589/tftp-deploy-cizhol9x/kernel/uImage
240 07:59:36.569366 substitutions:
241 07:59:36.569889 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 07:59:36.570387 - {DTB_ADDR}: 0x01070000
243 07:59:36.570834 - {DTB}: 978589/tftp-deploy-cizhol9x/dtb/meson-g12b-a311d-libretech-cc.dtb
244 07:59:36.571293 - {INITRD}: 978589/tftp-deploy-cizhol9x/ramdisk/ramdisk.cpio.gz.uboot
245 07:59:36.571773 - {KERNEL_ADDR}: 0x01080000
246 07:59:36.572271 - {KERNEL}: 978589/tftp-deploy-cizhol9x/kernel/uImage
247 07:59:36.572717 - {LAVA_MAC}: None
248 07:59:36.573228 - {PRESEED_CONFIG}: None
249 07:59:36.573672 - {PRESEED_LOCAL}: None
250 07:59:36.574108 - {RAMDISK_ADDR}: 0x08000000
251 07:59:36.574541 - {RAMDISK}: 978589/tftp-deploy-cizhol9x/ramdisk/ramdisk.cpio.gz.uboot
252 07:59:36.574994 - {ROOT_PART}: None
253 07:59:36.575429 - {ROOT}: None
254 07:59:36.575862 - {SERVER_IP}: 192.168.6.2
255 07:59:36.576331 - {TEE_ADDR}: 0x83000000
256 07:59:36.576775 - {TEE}: None
257 07:59:36.577211 Parsed boot commands:
258 07:59:36.577635 - setenv autoload no
259 07:59:36.578088 - setenv initrd_high 0xffffffff
260 07:59:36.578534 - setenv fdt_high 0xffffffff
261 07:59:36.579019 - dhcp
262 07:59:36.579481 - setenv serverip 192.168.6.2
263 07:59:36.579960 - tftpboot 0x01080000 978589/tftp-deploy-cizhol9x/kernel/uImage
264 07:59:36.580463 - tftpboot 0x08000000 978589/tftp-deploy-cizhol9x/ramdisk/ramdisk.cpio.gz.uboot
265 07:59:36.580909 - tftpboot 0x01070000 978589/tftp-deploy-cizhol9x/dtb/meson-g12b-a311d-libretech-cc.dtb
266 07:59:36.581354 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 07:59:36.581797 - bootm 0x01080000 0x08000000 0x01070000
268 07:59:36.582396 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 07:59:36.584150 start: 2.3 connect-device (timeout 00:05:00) [common]
271 07:59:36.584683 [common] connect-device Connecting to device using 'telnet conserv1 3007'
272 07:59:36.598995 Setting prompt string to ['lava-test: # ']
273 07:59:36.600643 end: 2.3 connect-device (duration 00:00:00) [common]
274 07:59:36.601307 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 07:59:36.601940 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 07:59:36.602568 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 07:59:36.603859 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
278 07:59:36.642285 >> OK - accepted request
279 07:59:36.644430 Returned 0 in 0 seconds
280 07:59:36.745713 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
282 07:59:36.747592 end: 2.4.1 reset-device (duration 00:00:00) [common]
283 07:59:36.748279 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
284 07:59:36.748851 Setting prompt string to ['Hit any key to stop autoboot']
285 07:59:36.749355 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 07:59:36.751081 Trying 192.168.56.21...
287 07:59:36.751606 Connected to conserv1.
288 07:59:36.752083 Escape character is '^]'.
289 07:59:36.752544
290 07:59:36.753024 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
291 07:59:36.753488
292 07:59:47.674429 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
293 07:59:47.674888 bl2_stage_init 0x01
294 07:59:47.675152 bl2_stage_init 0x81
295 07:59:47.680057 hw id: 0x0000 - pwm id 0x01
296 07:59:47.680645 bl2_stage_init 0xc1
297 07:59:47.681089 bl2_stage_init 0x02
298 07:59:47.681516
299 07:59:47.685526 L0:00000000
300 07:59:47.685854 L1:20000703
301 07:59:47.686068 L2:00008067
302 07:59:47.686267 L3:14000000
303 07:59:47.688404 B2:00402000
304 07:59:47.688721 B1:e0f83180
305 07:59:47.688940
306 07:59:47.689148 TE: 58124
307 07:59:47.689359
308 07:59:47.699582 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
309 07:59:47.699960
310 07:59:47.700252 Board ID = 1
311 07:59:47.700491 Set A53 clk to 24M
312 07:59:47.700698 Set A73 clk to 24M
313 07:59:47.705196 Set clk81 to 24M
314 07:59:47.705558 A53 clk: 1200 MHz
315 07:59:47.705778 A73 clk: 1200 MHz
316 07:59:47.710763 CLK81: 166.6M
317 07:59:47.711117 smccc: 00012a91
318 07:59:47.716372 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
319 07:59:47.716839 board id: 1
320 07:59:47.725217 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
321 07:59:47.735529 fw parse done
322 07:59:47.741773 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
323 07:59:47.784323 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
324 07:59:47.795118 PIEI prepare done
325 07:59:47.795787 fastboot data load
326 07:59:47.796521 fastboot data verify
327 07:59:47.800665 verify result: 266
328 07:59:47.806368 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
329 07:59:47.807065 LPDDR4 probe
330 07:59:47.807818 ddr clk to 1584MHz
331 07:59:47.814343 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
332 07:59:47.851539
333 07:59:47.852036 dmc_version 0001
334 07:59:47.858502 Check phy result
335 07:59:47.864036 INFO : End of CA training
336 07:59:47.864585 INFO : End of initialization
337 07:59:47.869599 INFO : Training has run successfully!
338 07:59:47.870145 Check phy result
339 07:59:47.875208 INFO : End of initialization
340 07:59:47.875722 INFO : End of read enable training
341 07:59:47.880855 INFO : End of fine write leveling
342 07:59:47.886446 INFO : End of Write leveling coarse delay
343 07:59:47.886984 INFO : Training has run successfully!
344 07:59:47.887461 Check phy result
345 07:59:47.892107 INFO : End of initialization
346 07:59:47.892813 INFO : End of read dq deskew training
347 07:59:47.897769 INFO : End of MPR read delay center optimization
348 07:59:47.903230 INFO : End of write delay center optimization
349 07:59:47.908905 INFO : End of read delay center optimization
350 07:59:47.909665 INFO : End of max read latency training
351 07:59:47.914426 INFO : Training has run successfully!
352 07:59:47.914924 1D training succeed
353 07:59:47.923597 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
354 07:59:47.971294 Check phy result
355 07:59:47.971723 INFO : End of initialization
356 07:59:47.997738 INFO : End of 2D read delay Voltage center optimization
357 07:59:48.013082 INFO : End of 2D read delay Voltage center optimization
358 07:59:48.065193 INFO : End of 2D write delay Voltage center optimization
359 07:59:48.114185 INFO : End of 2D write delay Voltage center optimization
360 07:59:48.119647 INFO : Training has run successfully!
361 07:59:48.120061
362 07:59:48.120306 channel==0
363 07:59:48.125215 RxClkDly_Margin_A0==88 ps 9
364 07:59:48.125544 TxDqDly_Margin_A0==98 ps 10
365 07:59:48.130806 RxClkDly_Margin_A1==88 ps 9
366 07:59:48.131161 TxDqDly_Margin_A1==98 ps 10
367 07:59:48.131394 TrainedVREFDQ_A0==74
368 07:59:48.136432 TrainedVREFDQ_A1==74
369 07:59:48.136828 VrefDac_Margin_A0==25
370 07:59:48.137053 DeviceVref_Margin_A0==40
371 07:59:48.142030 VrefDac_Margin_A1==25
372 07:59:48.142385 DeviceVref_Margin_A1==40
373 07:59:48.142625
374 07:59:48.142849
375 07:59:48.147700 channel==1
376 07:59:48.148098 RxClkDly_Margin_A0==98 ps 10
377 07:59:48.148327 TxDqDly_Margin_A0==88 ps 9
378 07:59:48.153224 RxClkDly_Margin_A1==98 ps 10
379 07:59:48.153621 TxDqDly_Margin_A1==88 ps 9
380 07:59:48.158831 TrainedVREFDQ_A0==76
381 07:59:48.159244 TrainedVREFDQ_A1==77
382 07:59:48.159482 VrefDac_Margin_A0==22
383 07:59:48.164412 DeviceVref_Margin_A0==38
384 07:59:48.164789 VrefDac_Margin_A1==23
385 07:59:48.170053 DeviceVref_Margin_A1==37
386 07:59:48.170539
387 07:59:48.171030 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
388 07:59:48.171480
389 07:59:48.203888 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000018 00000019 00000017 00000019 00000018 0000001a 0000001a 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
390 07:59:48.204671 2D training succeed
391 07:59:48.209394 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
392 07:59:48.215069 auto size-- 65535DDR cs0 size: 2048MB
393 07:59:48.215713 DDR cs1 size: 2048MB
394 07:59:48.220646 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
395 07:59:48.221266 cs0 DataBus test pass
396 07:59:48.226176 cs1 DataBus test pass
397 07:59:48.226719 cs0 AddrBus test pass
398 07:59:48.227176 cs1 AddrBus test pass
399 07:59:48.227657
400 07:59:48.231765 100bdlr_step_size ps== 420
401 07:59:48.232427 result report
402 07:59:48.237411 boot times 0Enable ddr reg access
403 07:59:48.242716 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
404 07:59:48.256209 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
405 07:59:48.828104 0.0;M3 CHK:0;cm4_sp_mode 0
406 07:59:48.828526 MVN_1=0x00000000
407 07:59:48.833432 MVN_2=0x00000000
408 07:59:48.839207 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
409 07:59:48.839456 OPS=0x10
410 07:59:48.839662 ring efuse init
411 07:59:48.839863 chipver efuse init
412 07:59:48.844862 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
413 07:59:48.850390 [0.018961 Inits done]
414 07:59:48.850632 secure task start!
415 07:59:48.850833 high task start!
416 07:59:48.855090 low task start!
417 07:59:48.855349 run into bl31
418 07:59:48.861733 NOTICE: BL31: v1.3(release):4fc40b1
419 07:59:48.869568 NOTICE: BL31: Built : 15:58:17, May 22 2019
420 07:59:48.870050 NOTICE: BL31: G12A normal boot!
421 07:59:48.894988 NOTICE: BL31: BL33 decompress pass
422 07:59:48.900599 ERROR: Error initializing runtime service opteed_fast
423 07:59:50.133470
424 07:59:50.134143
425 07:59:50.141832 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
426 07:59:50.142336
427 07:59:50.142783 Model: Libre Computer AML-A311D-CC Alta
428 07:59:50.350252 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
429 07:59:50.373605 DRAM: 2 GiB (effective 3.8 GiB)
430 07:59:50.516705 Core: 408 devices, 31 uclasses, devicetree: separate
431 07:59:50.522569 WDT: Not starting watchdog@f0d0
432 07:59:50.554823 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
433 07:59:50.567372 Loading Environment from FAT... Card did not respond to voltage select! : -110
434 07:59:50.572268 ** Bad device specification mmc 0 **
435 07:59:50.582632 Card did not respond to voltage select! : -110
436 07:59:50.590251 ** Bad device specification mmc 0 **
437 07:59:50.590865 Couldn't find partition mmc 0
438 07:59:50.598624 Card did not respond to voltage select! : -110
439 07:59:50.604289 ** Bad device specification mmc 0 **
440 07:59:50.604905 Couldn't find partition mmc 0
441 07:59:50.609294 Error: could not access storage.
442 07:59:51.874706 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.�!,K��х��}���с0x01
443 07:59:51.875424 bl2_stage_init 0x81
444 07:59:51.880265 hw id: 0x0000 - pwm id 0x01
445 07:59:51.880819 bl2_stage_init 0xc1
446 07:59:51.881284 bl2_stage_init 0x02
447 07:59:51.881738
448 07:59:51.885867 L0:00000000
449 07:59:51.886364 L1:20000703
450 07:59:51.886817 L2:00008067
451 07:59:51.887260 L3:14000000
452 07:59:51.887699 B2:00402000
453 07:59:51.888656 B1:e0f83180
454 07:59:51.889139
455 07:59:51.889588 TE: 58150
456 07:59:51.890037
457 07:59:51.899842 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
458 07:59:51.900366
459 07:59:51.900820 Board ID = 1
460 07:59:51.901264 Set A53 clk to 24M
461 07:59:51.901704 Set A73 clk to 24M
462 07:59:51.905447 Set clk81 to 24M
463 07:59:51.905938 A53 clk: 1200 MHz
464 07:59:51.906384 A73 clk: 1200 MHz
465 07:59:51.911031 CLK81: 166.6M
466 07:59:51.911504 smccc: 00012aac
467 07:59:51.916654 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
468 07:59:51.917135 board id: 1
469 07:59:51.925231 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
470 07:59:51.935878 fw parse done
471 07:59:51.941849 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
472 07:59:51.984571 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
473 07:59:51.995481 PIEI prepare done
474 07:59:51.996047 fastboot data load
475 07:59:51.996513 fastboot data verify
476 07:59:52.001039 verify result: 266
477 07:59:52.006639 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
478 07:59:52.007121 LPDDR4 probe
479 07:59:52.007569 ddr clk to 1584MHz
480 07:59:52.014710 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
481 07:59:52.052015
482 07:59:52.052527 dmc_version 0001
483 07:59:52.058720 Check phy result
484 07:59:52.064596 INFO : End of CA training
485 07:59:52.065103 INFO : End of initialization
486 07:59:52.070090 INFO : Training has run successfully!
487 07:59:52.070612 Check phy result
488 07:59:52.075674 INFO : End of initialization
489 07:59:52.076182 INFO : End of read enable training
490 07:59:52.081265 INFO : End of fine write leveling
491 07:59:52.086851 INFO : End of Write leveling coarse delay
492 07:59:52.087324 INFO : Training has run successfully!
493 07:59:52.087770 Check phy result
494 07:59:52.092568 INFO : End of initialization
495 07:59:52.093038 INFO : End of read dq deskew training
496 07:59:52.098051 INFO : End of MPR read delay center optimization
497 07:59:52.103644 INFO : End of write delay center optimization
498 07:59:52.109263 INFO : End of read delay center optimization
499 07:59:52.109737 INFO : End of max read latency training
500 07:59:52.114859 INFO : Training has run successfully!
501 07:59:52.115326 1D training succeed
502 07:59:52.124057 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
503 07:59:52.171727 Check phy result
504 07:59:52.172327 INFO : End of initialization
505 07:59:52.193405 INFO : End of 2D read delay Voltage center optimization
506 07:59:52.213692 INFO : End of 2D read delay Voltage center optimization
507 07:59:52.265725 INFO : End of 2D write delay Voltage center optimization
508 07:59:52.315060 INFO : End of 2D write delay Voltage center optimization
509 07:59:52.320634 INFO : Training has run successfully!
510 07:59:52.321143
511 07:59:52.321607 channel==0
512 07:59:52.326162 RxClkDly_Margin_A0==88 ps 9
513 07:59:52.326665 TxDqDly_Margin_A0==98 ps 10
514 07:59:52.331772 RxClkDly_Margin_A1==88 ps 9
515 07:59:52.332288 TxDqDly_Margin_A1==98 ps 10
516 07:59:52.332747 TrainedVREFDQ_A0==74
517 07:59:52.337377 TrainedVREFDQ_A1==74
518 07:59:52.337876 VrefDac_Margin_A0==25
519 07:59:52.338325 DeviceVref_Margin_A0==40
520 07:59:52.342984 VrefDac_Margin_A1==25
521 07:59:52.343493 DeviceVref_Margin_A1==40
522 07:59:52.343942
523 07:59:52.344427
524 07:59:52.348606 channel==1
525 07:59:52.349090 RxClkDly_Margin_A0==98 ps 10
526 07:59:52.349535 TxDqDly_Margin_A0==98 ps 10
527 07:59:52.354157 RxClkDly_Margin_A1==98 ps 10
528 07:59:52.354644 TxDqDly_Margin_A1==88 ps 9
529 07:59:52.359753 TrainedVREFDQ_A0==76
530 07:59:52.360320 TrainedVREFDQ_A1==77
531 07:59:52.360818 VrefDac_Margin_A0==22
532 07:59:52.365376 DeviceVref_Margin_A0==38
533 07:59:52.365856 VrefDac_Margin_A1==24
534 07:59:52.371018 DeviceVref_Margin_A1==37
535 07:59:52.371579
536 07:59:52.372084 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
537 07:59:52.376618
538 07:59:52.404688 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000018 00000018 00000019 00000018 00000019 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
539 07:59:52.405319 2D training succeed
540 07:59:52.410198 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
541 07:59:52.415755 auto size-- 65535DDR cs0 size: 2048MB
542 07:59:52.416288 DDR cs1 size: 2048MB
543 07:59:52.421359 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
544 07:59:52.421871 cs0 DataBus test pass
545 07:59:52.426932 cs1 DataBus test pass
546 07:59:52.427406 cs0 AddrBus test pass
547 07:59:52.427838 cs1 AddrBus test pass
548 07:59:52.428311
549 07:59:52.432608 100bdlr_step_size ps== 420
550 07:59:52.433090 result report
551 07:59:52.438163 boot times 0Enable ddr reg access
552 07:59:52.443706 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
553 07:59:52.457068 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
554 07:59:53.030910 0.0;M3 CHK:0;cm4_sp_mode 0
555 07:59:53.031316 MVN_1=0x00000000
556 07:59:53.036424 MVN_2=0x00000000
557 07:59:53.042094 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
558 07:59:53.042359 OPS=0x10
559 07:59:53.042569 ring efuse init
560 07:59:53.042775 chipver efuse init
561 07:59:53.050398 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
562 07:59:53.050687 [0.018961 Inits done]
563 07:59:53.050897 secure task start!
564 07:59:53.057962 high task start!
565 07:59:53.058232 low task start!
566 07:59:53.058442 run into bl31
567 07:59:53.064544 NOTICE: BL31: v1.3(release):4fc40b1
568 07:59:53.072407 NOTICE: BL31: Built : 15:58:17, May 22 2019
569 07:59:53.072678 NOTICE: BL31: G12A normal boot!
570 07:59:53.097727 NOTICE: BL31: BL33 decompress pass
571 07:59:53.103354 ERROR: Error initializing runtime service opteed_fast
572 07:59:54.336420
573 07:59:54.336842
574 07:59:54.344691 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
575 07:59:54.345043
576 07:59:54.345269 Model: Libre Computer AML-A311D-CC Alta
577 07:59:54.553233 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
578 07:59:54.576598 DRAM: 2 GiB (effective 3.8 GiB)
579 07:59:54.719538 Core: 408 devices, 31 uclasses, devicetree: separate
580 07:59:54.725341 WDT: Not starting watchdog@f0d0
581 07:59:54.757589 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
582 07:59:54.770129 Loading Environment from FAT... Card did not respond to voltage select! : -110
583 07:59:54.775131 ** Bad device specification mmc 0 **
584 07:59:54.785549 Card did not respond to voltage select! : -110
585 07:59:54.793168 ** Bad device specification mmc 0 **
586 07:59:54.793459 Couldn't find partition mmc 0
587 07:59:54.801382 Card did not respond to voltage select! : -110
588 07:59:54.807018 ** Bad device specification mmc 0 **
589 07:59:54.807315 Couldn't find partition mmc 0
590 07:59:54.812194 Error: could not access storage.
591 07:59:55.154549 Net: eth0: ethernet@ff3f0000
592 07:59:55.154925 starting USB...
593 07:59:55.406572 Bus usb@ff500000: Register 3000140 NbrPorts 3
594 07:59:55.406972 Starting the controller
595 07:59:55.413325 USB XHCI 1.10
596 07:59:57.125184 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.�!,K��х��}���с0x01
597 07:59:57.125630 bl2_stage_init 0x81
598 07:59:57.130659 hw id: 0x0000 - pwm id 0x01
599 07:59:57.131085 bl2_stage_init 0xc1
600 07:59:57.131451 bl2_stage_init 0x02
601 07:59:57.131712
602 07:59:57.136310 L0:00000000
603 07:59:57.136724 L1:20000703
604 07:59:57.137086 L2:00008067
605 07:59:57.137349 L3:14000000
606 07:59:57.137582 B2:00402000
607 07:59:57.139032 B1:e0f83180
608 07:59:57.139311
609 07:59:57.139544 TE: 58150
610 07:59:57.139772
611 07:59:57.150316 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
612 07:59:57.150657
613 07:59:57.150902 Board ID = 1
614 07:59:57.151126 Set A53 clk to 24M
615 07:59:57.151352 Set A73 clk to 24M
616 07:59:57.155929 Set clk81 to 24M
617 07:59:57.156257 A53 clk: 1200 MHz
618 07:59:57.156493 A73 clk: 1200 MHz
619 07:59:57.161551 CLK81: 166.6M
620 07:59:57.162005 smccc: 00012aab
621 07:59:57.167083 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
622 07:59:57.167516 board id: 1
623 07:59:57.175781 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
624 07:59:57.186257 fw parse done
625 07:59:57.192203 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
626 07:59:57.234840 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
627 07:59:57.245680 PIEI prepare done
628 07:59:57.246175 fastboot data load
629 07:59:57.246450 fastboot data verify
630 07:59:57.251292 verify result: 266
631 07:59:57.256866 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
632 07:59:57.257204 LPDDR4 probe
633 07:59:57.257439 ddr clk to 1584MHz
634 07:59:57.264848 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
635 07:59:57.302204
636 07:59:57.302604 dmc_version 0001
637 07:59:57.308806 Check phy result
638 07:59:57.314705 INFO : End of CA training
639 07:59:57.315205 INFO : End of initialization
640 07:59:57.320292 INFO : Training has run successfully!
641 07:59:57.320618 Check phy result
642 07:59:57.325898 INFO : End of initialization
643 07:59:57.326235 INFO : End of read enable training
644 07:59:57.329300 INFO : End of fine write leveling
645 07:59:57.334810 INFO : End of Write leveling coarse delay
646 07:59:57.340410 INFO : Training has run successfully!
647 07:59:57.340760 Check phy result
648 07:59:57.341003 INFO : End of initialization
649 07:59:57.346025 INFO : End of read dq deskew training
650 07:59:57.351764 INFO : End of MPR read delay center optimization
651 07:59:57.352167 INFO : End of write delay center optimization
652 07:59:57.357296 INFO : End of read delay center optimization
653 07:59:57.362810 INFO : End of max read latency training
654 07:59:57.363281 INFO : Training has run successfully!
655 07:59:57.368407 1D training succeed
656 07:59:57.374392 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
657 07:59:57.421886 Check phy result
658 07:59:57.422260 INFO : End of initialization
659 07:59:57.443596 INFO : End of 2D read delay Voltage center optimization
660 07:59:57.463593 INFO : End of 2D read delay Voltage center optimization
661 07:59:57.516048 INFO : End of 2D write delay Voltage center optimization
662 07:59:57.565596 INFO : End of 2D write delay Voltage center optimization
663 07:59:57.570934 INFO : Training has run successfully!
664 07:59:57.571463
665 07:59:57.571930 channel==0
666 07:59:57.576578 RxClkDly_Margin_A0==88 ps 9
667 07:59:57.577278 TxDqDly_Margin_A0==98 ps 10
668 07:59:57.582178 RxClkDly_Margin_A1==88 ps 9
669 07:59:57.582706 TxDqDly_Margin_A1==98 ps 10
670 07:59:57.583166 TrainedVREFDQ_A0==74
671 07:59:57.587742 TrainedVREFDQ_A1==74
672 07:59:57.588299 VrefDac_Margin_A0==25
673 07:59:57.588749 DeviceVref_Margin_A0==40
674 07:59:57.593448 VrefDac_Margin_A1==25
675 07:59:57.593965 DeviceVref_Margin_A1==40
676 07:59:57.594417
677 07:59:57.594920
678 07:59:57.599011 channel==1
679 07:59:57.599533 RxClkDly_Margin_A0==88 ps 9
680 07:59:57.600040 TxDqDly_Margin_A0==98 ps 10
681 07:59:57.604645 RxClkDly_Margin_A1==88 ps 9
682 07:59:57.605164 TxDqDly_Margin_A1==98 ps 10
683 07:59:57.610268 TrainedVREFDQ_A0==77
684 07:59:57.610785 TrainedVREFDQ_A1==77
685 07:59:57.611240 VrefDac_Margin_A0==22
686 07:59:57.615949 DeviceVref_Margin_A0==37
687 07:59:57.616526 VrefDac_Margin_A1==24
688 07:59:57.621481 DeviceVref_Margin_A1==37
689 07:59:57.622004
690 07:59:57.622460 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
691 07:59:57.622906
692 07:59:57.654911 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000019 00000018 00000019 00000018 0000001a 0000001a 00000018 00000017 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000018 00000018 dram_vref_reg_value 0x 00000060
693 07:59:57.655491 2D training succeed
694 07:59:57.660623 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
695 07:59:57.666155 auto size-- 65535DDR cs0 size: 2048MB
696 07:59:57.666670 DDR cs1 size: 2048MB
697 07:59:57.671755 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
698 07:59:57.672306 cs0 DataBus test pass
699 07:59:57.677488 cs1 DataBus test pass
700 07:59:57.678000 cs0 AddrBus test pass
701 07:59:57.678449 cs1 AddrBus test pass
702 07:59:57.678885
703 07:59:57.682950 100bdlr_step_size ps== 420
704 07:59:57.683474 result report
705 07:59:57.688561 boot times 0Enable ddr reg access
706 07:59:57.693894 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
707 07:59:57.707378 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
708 07:59:58.280806 0.0;M3 CHK:0;cm4_sp_mode 0
709 07:59:58.281227 MVN_1=0x00000000
710 07:59:58.286407 MVN_2=0x00000000
711 07:59:58.292174 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
712 07:59:58.292778 OPS=0x10
713 07:59:58.293263 ring efuse init
714 07:59:58.293720 chipver efuse init
715 07:59:58.297717 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
716 07:59:58.303440 [0.018961 Inits done]
717 07:59:58.304071 secure task start!
718 07:59:58.304775 high task start!
719 07:59:58.307905 low task start!
720 07:59:58.308474 run into bl31
721 07:59:58.314536 NOTICE: BL31: v1.3(release):4fc40b1
722 07:59:58.322485 NOTICE: BL31: Built : 15:58:17, May 22 2019
723 07:59:58.323075 NOTICE: BL31: G12A normal boot!
724 07:59:58.347794 NOTICE: BL31: BL33 decompress pass
725 07:59:58.353889 ERROR: Error initializing runtime service opteed_fast
726 07:59:59.586255
727 07:59:59.586682
728 07:59:59.594645 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
729 07:59:59.594962
730 07:59:59.595199 Model: Libre Computer AML-A311D-CC Alta
731 07:59:59.803133 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
732 07:59:59.826609 DRAM: 2 GiB (effective 3.8 GiB)
733 07:59:59.969578 Core: 408 devices, 31 uclasses, devicetree: separate
734 07:59:59.975332 WDT: Not starting watchdog@f0d0
735 08:00:00.007766 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
736 08:00:00.020089 Loading Environment from FAT... Card did not respond to voltage select! : -110
737 08:00:00.025047 ** Bad device specification mmc 0 **
738 08:00:00.035417 Card did not respond to voltage select! : -110
739 08:00:00.043097 ** Bad device specification mmc 0 **
740 08:00:00.043447 Couldn't find partition mmc 0
741 08:00:00.051399 Card did not respond to voltage select! : -110
742 08:00:00.056873 ** Bad device specification mmc 0 **
743 08:00:00.057390 Couldn't find partition mmc 0
744 08:00:00.061983 Error: could not access storage.
745 08:00:00.404536 Net: eth0: ethernet@ff3f0000
746 08:00:00.405152 starting USB...
747 08:00:00.656282 Bus usb@ff500000: Register 3000140 NbrPorts 3
748 08:00:00.656909 Starting the controller
749 08:00:00.663236 USB XHCI 1.10
750 08:00:02.826636 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.�!,K��х��}���с0x01
751 08:00:02.827457 bl2_stage_init 0x81
752 08:00:02.832103 hw id: 0x0000 - pwm id 0x01
753 08:00:02.832807 bl2_stage_init 0xc1
754 08:00:02.833356 bl2_stage_init 0x02
755 08:00:02.833950
756 08:00:02.837625 L0:00000000
757 08:00:02.838132 L1:20000703
758 08:00:02.838589 L2:00008067
759 08:00:02.839041 L3:14000000
760 08:00:02.839473 B2:00402000
761 08:00:02.843216 B1:e0f83180
762 08:00:02.843722
763 08:00:02.844247 TE: 58150
764 08:00:02.844690
765 08:00:02.848886 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
766 08:00:02.849452
767 08:00:02.849912 Board ID = 1
768 08:00:02.854421 Set A53 clk to 24M
769 08:00:02.854941 Set A73 clk to 24M
770 08:00:02.855386 Set clk81 to 24M
771 08:00:02.860194 A53 clk: 1200 MHz
772 08:00:02.860760 A73 clk: 1200 MHz
773 08:00:02.861226 CLK81: 166.6M
774 08:00:02.861691 smccc: 00012aac
775 08:00:02.865680 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
776 08:00:02.871334 board id: 1
777 08:00:02.876810 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
778 08:00:02.887732 fw parse done
779 08:00:02.892698 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
780 08:00:02.935503 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
781 08:00:02.947231 PIEI prepare done
782 08:00:02.947794 fastboot data load
783 08:00:02.948288 fastboot data verify
784 08:00:02.952974 verify result: 266
785 08:00:02.958520 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
786 08:00:02.959066 LPDDR4 probe
787 08:00:02.959506 ddr clk to 1584MHz
788 08:00:02.966014 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
789 08:00:03.002944
790 08:00:03.003519 dmc_version 0001
791 08:00:03.009924 Check phy result
792 08:00:03.016303 INFO : End of CA training
793 08:00:03.016885 INFO : End of initialization
794 08:00:03.021924 INFO : Training has run successfully!
795 08:00:03.022499 Check phy result
796 08:00:03.027711 INFO : End of initialization
797 08:00:03.028372 INFO : End of read enable training
798 08:00:03.030858 INFO : End of fine write leveling
799 08:00:03.036346 INFO : End of Write leveling coarse delay
800 08:00:03.041989 INFO : Training has run successfully!
801 08:00:03.042580 Check phy result
802 08:00:03.043025 INFO : End of initialization
803 08:00:03.047523 INFO : End of read dq deskew training
804 08:00:03.053223 INFO : End of MPR read delay center optimization
805 08:00:03.053807 INFO : End of write delay center optimization
806 08:00:03.058768 INFO : End of read delay center optimization
807 08:00:03.064290 INFO : End of max read latency training
808 08:00:03.064848 INFO : Training has run successfully!
809 08:00:03.069884 1D training succeed
810 08:00:03.075144 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
811 08:00:03.122911 Check phy result
812 08:00:03.123513 INFO : End of initialization
813 08:00:03.145027 INFO : End of 2D read delay Voltage center optimization
814 08:00:03.164812 INFO : End of 2D read delay Voltage center optimization
815 08:00:03.216844 INFO : End of 2D write delay Voltage center optimization
816 08:00:03.266908 INFO : End of 2D write delay Voltage center optimization
817 08:00:03.272487 INFO : Training has run successfully!
818 08:00:03.273032
819 08:00:03.273479 channel==0
820 08:00:03.278089 RxClkDly_Margin_A0==88 ps 9
821 08:00:03.278630 TxDqDly_Margin_A0==98 ps 10
822 08:00:03.283693 RxClkDly_Margin_A1==88 ps 9
823 08:00:03.284284 TxDqDly_Margin_A1==98 ps 10
824 08:00:03.284738 TrainedVREFDQ_A0==74
825 08:00:03.289270 TrainedVREFDQ_A1==74
826 08:00:03.289815 VrefDac_Margin_A0==25
827 08:00:03.290249 DeviceVref_Margin_A0==40
828 08:00:03.294861 VrefDac_Margin_A1==25
829 08:00:03.295390 DeviceVref_Margin_A1==40
830 08:00:03.295823
831 08:00:03.296298
832 08:00:03.300505 channel==1
833 08:00:03.301053 RxClkDly_Margin_A0==88 ps 9
834 08:00:03.301487 TxDqDly_Margin_A0==98 ps 10
835 08:00:03.306095 RxClkDly_Margin_A1==98 ps 10
836 08:00:03.306639 TxDqDly_Margin_A1==88 ps 9
837 08:00:03.311639 TrainedVREFDQ_A0==77
838 08:00:03.312234 TrainedVREFDQ_A1==77
839 08:00:03.312674 VrefDac_Margin_A0==22
840 08:00:03.317264 DeviceVref_Margin_A0==37
841 08:00:03.317796 VrefDac_Margin_A1==22
842 08:00:03.322835 DeviceVref_Margin_A1==37
843 08:00:03.323364
844 08:00:03.323813 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
845 08:00:03.324287
846 08:00:03.356456 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000018 00000019 00000018 00000019 00000018 00000019 0000001a 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
847 08:00:03.357117 2D training succeed
848 08:00:03.362082 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
849 08:00:03.367692 auto size-- 65535DDR cs0 size: 2048MB
850 08:00:03.368349 DDR cs1 size: 2048MB
851 08:00:03.373243 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
852 08:00:03.373816 cs0 DataBus test pass
853 08:00:03.378932 cs1 DataBus test pass
854 08:00:03.379529 cs0 AddrBus test pass
855 08:00:03.380078 cs1 AddrBus test pass
856 08:00:03.380590
857 08:00:03.384474 100bdlr_step_size ps== 420
858 08:00:03.385050 result report
859 08:00:03.390174 boot times 0Enable ddr reg access
860 08:00:03.395145 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
861 08:00:03.408492 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
862 08:00:03.981938 0.0;M3 CHK:0;cm4_sp_mode 0
863 08:00:03.982866 MVN_1=0x00000000
864 08:00:03.987339 MVN_2=0x00000000
865 08:00:03.993211 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
866 08:00:03.993983 OPS=0x10
867 08:00:03.994595 ring efuse init
868 08:00:03.995300 chipver efuse init
869 08:00:03.998693 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
870 08:00:04.004802 [0.018961 Inits done]
871 08:00:04.005124 secure task start!
872 08:00:04.005337 high task start!
873 08:00:04.008815 low task start!
874 08:00:04.009412 run into bl31
875 08:00:04.015555 NOTICE: BL31: v1.3(release):4fc40b1
876 08:00:04.022651 NOTICE: BL31: Built : 15:58:17, May 22 2019
877 08:00:04.023269 NOTICE: BL31: G12A normal boot!
878 08:00:04.049387 NOTICE: BL31: BL33 decompress pass
879 08:00:04.054410 ERROR: Error initializing runtime service opteed_fast
880 08:00:05.287834
881 08:00:05.288523
882 08:00:05.296233 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
883 08:00:05.296782
884 08:00:05.297246 Model: Libre Computer AML-A311D-CC Alta
885 08:00:05.504797 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
886 08:00:05.528086 DRAM: 2 GiB (effective 3.8 GiB)
887 08:00:05.671048 Core: 408 devices, 31 uclasses, devicetree: separate
888 08:00:05.676902 WDT: Not starting watchdog@f0d0
889 08:00:05.709135 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
890 08:00:05.721578 Loading Environment from FAT... Card did not respond to voltage select! : -110
891 08:00:05.726561 ** Bad device specification mmc 0 **
892 08:00:05.737001 Card did not respond to voltage select! : -110
893 08:00:05.744616 ** Bad device specification mmc 0 **
894 08:00:05.745106 Couldn't find partition mmc 0
895 08:00:05.752963 Card did not respond to voltage select! : -110
896 08:00:05.758448 ** Bad device specification mmc 0 **
897 08:00:05.758935 Couldn't find partition mmc 0
898 08:00:05.763580 Error: could not access storage.
899 08:00:06.105761 Net: eth0: ethernet@ff3f0000
900 08:00:06.106383 starting USB...
901 08:00:06.357928 Bus usb@ff500000: Register 3000140 NbrPorts 3
902 08:00:06.358885 Starting the controller
903 08:00:06.364813 USB XHCI 1.10
904 08:00:07.918891 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
905 08:00:07.927287 scanning usb for storage devices... 0 Storage Device(s) found
907 08:00:07.978364 Hit any key to stop autoboot: 1
908 08:00:07.979318 end: 2.4.2 bootloader-interrupt (duration 00:00:31) [common]
909 08:00:07.979738 start: 2.4.3 bootloader-commands (timeout 00:04:29) [common]
910 08:00:07.980067 Setting prompt string to ['=>']
911 08:00:07.980373 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:29)
912 08:00:07.994245 0
913 08:00:07.994943 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
914 08:00:07.995284 Sending with 10 millisecond of delay
916 08:00:09.131340 => setenv autoload no
917 08:00:09.142289 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:27)
918 08:00:09.147908 setenv autoload no
919 08:00:09.148772 Sending with 10 millisecond of delay
921 08:00:10.946182 => setenv initrd_high 0xffffffff
922 08:00:10.957023 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:26)
923 08:00:10.957959 setenv initrd_high 0xffffffff
924 08:00:10.958728 Sending with 10 millisecond of delay
926 08:00:12.575766 => setenv fdt_high 0xffffffff
927 08:00:12.586667 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:24)
928 08:00:12.587608 setenv fdt_high 0xffffffff
929 08:00:12.588408 Sending with 10 millisecond of delay
931 08:00:12.880375 => dhcp
932 08:00:12.891226 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:24)
933 08:00:12.892161 dhcp
934 08:00:12.892646 Speed: 1000, full duplex
935 08:00:12.893100 BOOTP broadcast 1
936 08:00:12.901389 DHCP client bound to address 192.168.6.27 (9 ms)
937 08:00:12.902138 Sending with 10 millisecond of delay
939 08:00:14.579343 => setenv serverip 192.168.6.2
940 08:00:14.590232 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:22)
941 08:00:14.591233 setenv serverip 192.168.6.2
942 08:00:14.592088 Sending with 10 millisecond of delay
944 08:00:18.318215 => tftpboot 0x01080000 978589/tftp-deploy-cizhol9x/kernel/uImage
945 08:00:18.328920 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
946 08:00:18.329650 tftpboot 0x01080000 978589/tftp-deploy-cizhol9x/kernel/uImage
947 08:00:18.329968 Speed: 1000, full duplex
948 08:00:18.330245 Using ethernet@ff3f0000 device
949 08:00:18.331615 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
950 08:00:18.337122 Filename '978589/tftp-deploy-cizhol9x/kernel/uImage'.
951 08:00:18.340981 Load address: 0x1080000
952 08:00:21.509597 Loading: *################################################## 44 MiB
953 08:00:21.510192 13.9 MiB/s
954 08:00:21.510622 done
955 08:00:21.513735 Bytes transferred = 46121536 (2bfc240 hex)
956 08:00:21.514501 Sending with 10 millisecond of delay
958 08:00:26.205726 => tftpboot 0x08000000 978589/tftp-deploy-cizhol9x/ramdisk/ramdisk.cpio.gz.uboot
959 08:00:26.216565 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:10)
960 08:00:26.217501 tftpboot 0x08000000 978589/tftp-deploy-cizhol9x/ramdisk/ramdisk.cpio.gz.uboot
961 08:00:26.217986 Speed: 1000, full duplex
962 08:00:26.218448 Using ethernet@ff3f0000 device
963 08:00:26.219655 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
964 08:00:26.228250 Filename '978589/tftp-deploy-cizhol9x/ramdisk/ramdisk.cpio.gz.uboot'.
965 08:00:26.228797 Load address: 0x8000000
966 08:00:35.467161 Loading: *###T ############################################## UDP wrong checksum 0000000f 000050af
967 08:00:40.467664 T UDP wrong checksum 0000000f 000050af
968 08:00:45.389491 UDP wrong checksum 000000ff 00008b7f
969 08:00:45.403021 UDP wrong checksum 000000ff 00002072
970 08:00:45.587347 T UDP wrong checksum 000000ff 00000c25
971 08:00:45.600414 UDP wrong checksum 000000ff 0000a217
972 08:00:50.470842 T UDP wrong checksum 0000000f 000050af
973 08:01:07.455551 T T T UDP wrong checksum 000000ff 000084eb
974 08:01:07.514890 UDP wrong checksum 000000ff 000017de
975 08:01:10.471956 UDP wrong checksum 0000000f 000050af
976 08:01:25.478777 T T T
977 08:01:25.479416 Retry count exceeded; starting again
979 08:01:25.480988 end: 2.4.3 bootloader-commands (duration 00:01:18) [common]
982 08:01:25.483025 end: 2.4 uboot-commands (duration 00:01:49) [common]
984 08:01:25.484619 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
986 08:01:25.485699 end: 2 uboot-action (duration 00:01:49) [common]
988 08:01:25.487334 Cleaning after the job
989 08:01:25.487910 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/978589/tftp-deploy-cizhol9x/ramdisk
990 08:01:25.489408 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/978589/tftp-deploy-cizhol9x/kernel
991 08:01:25.538371 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/978589/tftp-deploy-cizhol9x/dtb
992 08:01:25.539177 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/978589/tftp-deploy-cizhol9x/modules
993 08:01:25.557576 start: 4.1 power-off (timeout 00:00:30) [common]
994 08:01:25.558192 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
995 08:01:25.592253 >> OK - accepted request
996 08:01:25.594240 Returned 0 in 0 seconds
997 08:01:25.695056 end: 4.1 power-off (duration 00:00:00) [common]
999 08:01:25.696265 start: 4.2 read-feedback (timeout 00:10:00) [common]
1000 08:01:25.697023 Listened to connection for namespace 'common' for up to 1s
1001 08:01:26.697957 Finalising connection for namespace 'common'
1002 08:01:26.698750 Disconnecting from shell: Finalise
1003 08:01:26.699505 =>
1004 08:01:26.800706 end: 4.2 read-feedback (duration 00:00:01) [common]
1005 08:01:26.801474 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/978589
1006 08:01:27.452405 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/978589
1007 08:01:27.452997 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.