Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 1
- Kernel Warnings: 6
- Errors: 0
- Boot result: PASS
- Kernel Errors: 3
1 08:23:16.069077 lava-dispatcher, installed at version: 2024.01
2 08:23:16.069904 start: 0 validate
3 08:23:16.070446 Start time: 2024-11-12 08:23:16.070415+00:00 (UTC)
4 08:23:16.071006 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 08:23:16.071553 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 08:23:16.116306 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 08:23:16.116844 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241112%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 08:23:16.149934 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 08:23:16.150848 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241112%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 08:23:16.180224 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 08:23:16.180726 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 08:23:16.213502 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 08:23:16.213990 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241112%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
14 08:23:16.255420 validate duration: 0.19
16 08:23:16.256936 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 08:23:16.257548 start: 1.1 download-retry (timeout 00:10:00) [common]
18 08:23:16.258146 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 08:23:16.259119 Not decompressing ramdisk as can be used compressed.
20 08:23:16.259878 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 08:23:16.260433 saving as /var/lib/lava/dispatcher/tmp/978668/tftp-deploy-ojpnit67/ramdisk/initrd.cpio.gz
22 08:23:16.260942 total size: 5628169 (5 MB)
23 08:23:16.302437 progress 0 % (0 MB)
24 08:23:16.309988 progress 5 % (0 MB)
25 08:23:16.317820 progress 10 % (0 MB)
26 08:23:16.324707 progress 15 % (0 MB)
27 08:23:16.330302 progress 20 % (1 MB)
28 08:23:16.333968 progress 25 % (1 MB)
29 08:23:16.337896 progress 30 % (1 MB)
30 08:23:16.341955 progress 35 % (1 MB)
31 08:23:16.345596 progress 40 % (2 MB)
32 08:23:16.349607 progress 45 % (2 MB)
33 08:23:16.353184 progress 50 % (2 MB)
34 08:23:16.357153 progress 55 % (2 MB)
35 08:23:16.361059 progress 60 % (3 MB)
36 08:23:16.364761 progress 65 % (3 MB)
37 08:23:16.368695 progress 70 % (3 MB)
38 08:23:16.372265 progress 75 % (4 MB)
39 08:23:16.376243 progress 80 % (4 MB)
40 08:23:16.379727 progress 85 % (4 MB)
41 08:23:16.383653 progress 90 % (4 MB)
42 08:23:16.387409 progress 95 % (5 MB)
43 08:23:16.390635 progress 100 % (5 MB)
44 08:23:16.391268 5 MB downloaded in 0.13 s (41.19 MB/s)
45 08:23:16.391793 end: 1.1.1 http-download (duration 00:00:00) [common]
47 08:23:16.392705 end: 1.1 download-retry (duration 00:00:00) [common]
48 08:23:16.392997 start: 1.2 download-retry (timeout 00:10:00) [common]
49 08:23:16.393267 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 08:23:16.393728 downloading http://storage.kernelci.org/next/master/next-20241112/arm64/defconfig/gcc-12/kernel/Image
51 08:23:16.393971 saving as /var/lib/lava/dispatcher/tmp/978668/tftp-deploy-ojpnit67/kernel/Image
52 08:23:16.394181 total size: 46121472 (43 MB)
53 08:23:16.394390 No compression specified
54 08:23:16.432480 progress 0 % (0 MB)
55 08:23:16.461139 progress 5 % (2 MB)
56 08:23:16.489153 progress 10 % (4 MB)
57 08:23:16.517474 progress 15 % (6 MB)
58 08:23:16.545449 progress 20 % (8 MB)
59 08:23:16.573610 progress 25 % (11 MB)
60 08:23:16.601813 progress 30 % (13 MB)
61 08:23:16.629792 progress 35 % (15 MB)
62 08:23:16.658308 progress 40 % (17 MB)
63 08:23:16.686168 progress 45 % (19 MB)
64 08:23:16.713850 progress 50 % (22 MB)
65 08:23:16.742290 progress 55 % (24 MB)
66 08:23:16.770326 progress 60 % (26 MB)
67 08:23:16.798000 progress 65 % (28 MB)
68 08:23:16.826085 progress 70 % (30 MB)
69 08:23:16.853846 progress 75 % (33 MB)
70 08:23:16.882531 progress 80 % (35 MB)
71 08:23:16.910333 progress 85 % (37 MB)
72 08:23:16.938087 progress 90 % (39 MB)
73 08:23:16.966905 progress 95 % (41 MB)
74 08:23:16.993934 progress 100 % (43 MB)
75 08:23:16.994582 43 MB downloaded in 0.60 s (73.26 MB/s)
76 08:23:16.995055 end: 1.2.1 http-download (duration 00:00:01) [common]
78 08:23:16.995856 end: 1.2 download-retry (duration 00:00:01) [common]
79 08:23:16.996161 start: 1.3 download-retry (timeout 00:09:59) [common]
80 08:23:16.996428 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 08:23:16.996893 downloading http://storage.kernelci.org/next/master/next-20241112/arm64/defconfig/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
82 08:23:16.997130 saving as /var/lib/lava/dispatcher/tmp/978668/tftp-deploy-ojpnit67/dtb/meson-g12b-a311d-libretech-cc.dtb
83 08:23:16.997335 total size: 54703 (0 MB)
84 08:23:16.997541 No compression specified
85 08:23:17.043268 progress 59 % (0 MB)
86 08:23:17.044170 progress 100 % (0 MB)
87 08:23:17.044718 0 MB downloaded in 0.05 s (1.10 MB/s)
88 08:23:17.045173 end: 1.3.1 http-download (duration 00:00:00) [common]
90 08:23:17.045976 end: 1.3 download-retry (duration 00:00:00) [common]
91 08:23:17.046235 start: 1.4 download-retry (timeout 00:09:59) [common]
92 08:23:17.046496 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 08:23:17.046946 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 08:23:17.047184 saving as /var/lib/lava/dispatcher/tmp/978668/tftp-deploy-ojpnit67/nfsrootfs/full.rootfs.tar
95 08:23:17.047387 total size: 120894716 (115 MB)
96 08:23:17.047597 Using unxz to decompress xz
97 08:23:17.086446 progress 0 % (0 MB)
98 08:23:17.878472 progress 5 % (5 MB)
99 08:23:18.713388 progress 10 % (11 MB)
100 08:23:19.516870 progress 15 % (17 MB)
101 08:23:20.264687 progress 20 % (23 MB)
102 08:23:20.856918 progress 25 % (28 MB)
103 08:23:21.690500 progress 30 % (34 MB)
104 08:23:22.472965 progress 35 % (40 MB)
105 08:23:22.835021 progress 40 % (46 MB)
106 08:23:23.210702 progress 45 % (51 MB)
107 08:23:23.922597 progress 50 % (57 MB)
108 08:23:24.801395 progress 55 % (63 MB)
109 08:23:25.578305 progress 60 % (69 MB)
110 08:23:26.328598 progress 65 % (74 MB)
111 08:23:27.113028 progress 70 % (80 MB)
112 08:23:27.932726 progress 75 % (86 MB)
113 08:23:28.712471 progress 80 % (92 MB)
114 08:23:29.467293 progress 85 % (98 MB)
115 08:23:30.310440 progress 90 % (103 MB)
116 08:23:31.075235 progress 95 % (109 MB)
117 08:23:31.896547 progress 100 % (115 MB)
118 08:23:31.909134 115 MB downloaded in 14.86 s (7.76 MB/s)
119 08:23:31.910053 end: 1.4.1 http-download (duration 00:00:15) [common]
121 08:23:31.912207 end: 1.4 download-retry (duration 00:00:15) [common]
122 08:23:31.912894 start: 1.5 download-retry (timeout 00:09:44) [common]
123 08:23:31.913572 start: 1.5.1 http-download (timeout 00:09:44) [common]
124 08:23:31.914965 downloading http://storage.kernelci.org/next/master/next-20241112/arm64/defconfig/gcc-12/modules.tar.xz
125 08:23:31.915592 saving as /var/lib/lava/dispatcher/tmp/978668/tftp-deploy-ojpnit67/modules/modules.tar
126 08:23:31.916167 total size: 11690048 (11 MB)
127 08:23:31.916729 Using unxz to decompress xz
128 08:23:31.965301 progress 0 % (0 MB)
129 08:23:32.031002 progress 5 % (0 MB)
130 08:23:32.105460 progress 10 % (1 MB)
131 08:23:32.199638 progress 15 % (1 MB)
132 08:23:32.296633 progress 20 % (2 MB)
133 08:23:32.375678 progress 25 % (2 MB)
134 08:23:32.451093 progress 30 % (3 MB)
135 08:23:32.524154 progress 35 % (3 MB)
136 08:23:32.600084 progress 40 % (4 MB)
137 08:23:32.675183 progress 45 % (5 MB)
138 08:23:32.757975 progress 50 % (5 MB)
139 08:23:32.838221 progress 55 % (6 MB)
140 08:23:32.922473 progress 60 % (6 MB)
141 08:23:32.997289 progress 65 % (7 MB)
142 08:23:33.079184 progress 70 % (7 MB)
143 08:23:33.159963 progress 75 % (8 MB)
144 08:23:33.242322 progress 80 % (8 MB)
145 08:23:33.321241 progress 85 % (9 MB)
146 08:23:33.405974 progress 90 % (10 MB)
147 08:23:33.478459 progress 95 % (10 MB)
148 08:23:33.554955 progress 100 % (11 MB)
149 08:23:33.568419 11 MB downloaded in 1.65 s (6.75 MB/s)
150 08:23:33.569019 end: 1.5.1 http-download (duration 00:00:02) [common]
152 08:23:33.569858 end: 1.5 download-retry (duration 00:00:02) [common]
153 08:23:33.570131 start: 1.6 prepare-tftp-overlay (timeout 00:09:43) [common]
154 08:23:33.570401 start: 1.6.1 extract-nfsrootfs (timeout 00:09:43) [common]
155 08:23:49.702057 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/978668/extract-nfsrootfs-iaw2q4k4
156 08:23:49.702642 end: 1.6.1 extract-nfsrootfs (duration 00:00:16) [common]
157 08:23:49.702927 start: 1.6.2 lava-overlay (timeout 00:09:27) [common]
158 08:23:49.703533 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/978668/lava-overlay-7ic01ylp
159 08:23:49.703956 makedir: /var/lib/lava/dispatcher/tmp/978668/lava-overlay-7ic01ylp/lava-978668/bin
160 08:23:49.704340 makedir: /var/lib/lava/dispatcher/tmp/978668/lava-overlay-7ic01ylp/lava-978668/tests
161 08:23:49.704650 makedir: /var/lib/lava/dispatcher/tmp/978668/lava-overlay-7ic01ylp/lava-978668/results
162 08:23:49.704978 Creating /var/lib/lava/dispatcher/tmp/978668/lava-overlay-7ic01ylp/lava-978668/bin/lava-add-keys
163 08:23:49.705503 Creating /var/lib/lava/dispatcher/tmp/978668/lava-overlay-7ic01ylp/lava-978668/bin/lava-add-sources
164 08:23:49.706027 Creating /var/lib/lava/dispatcher/tmp/978668/lava-overlay-7ic01ylp/lava-978668/bin/lava-background-process-start
165 08:23:49.706550 Creating /var/lib/lava/dispatcher/tmp/978668/lava-overlay-7ic01ylp/lava-978668/bin/lava-background-process-stop
166 08:23:49.707074 Creating /var/lib/lava/dispatcher/tmp/978668/lava-overlay-7ic01ylp/lava-978668/bin/lava-common-functions
167 08:23:49.707566 Creating /var/lib/lava/dispatcher/tmp/978668/lava-overlay-7ic01ylp/lava-978668/bin/lava-echo-ipv4
168 08:23:49.708073 Creating /var/lib/lava/dispatcher/tmp/978668/lava-overlay-7ic01ylp/lava-978668/bin/lava-install-packages
169 08:23:49.708565 Creating /var/lib/lava/dispatcher/tmp/978668/lava-overlay-7ic01ylp/lava-978668/bin/lava-installed-packages
170 08:23:49.709033 Creating /var/lib/lava/dispatcher/tmp/978668/lava-overlay-7ic01ylp/lava-978668/bin/lava-os-build
171 08:23:49.709500 Creating /var/lib/lava/dispatcher/tmp/978668/lava-overlay-7ic01ylp/lava-978668/bin/lava-probe-channel
172 08:23:49.709987 Creating /var/lib/lava/dispatcher/tmp/978668/lava-overlay-7ic01ylp/lava-978668/bin/lava-probe-ip
173 08:23:49.710481 Creating /var/lib/lava/dispatcher/tmp/978668/lava-overlay-7ic01ylp/lava-978668/bin/lava-target-ip
174 08:23:49.710950 Creating /var/lib/lava/dispatcher/tmp/978668/lava-overlay-7ic01ylp/lava-978668/bin/lava-target-mac
175 08:23:49.711418 Creating /var/lib/lava/dispatcher/tmp/978668/lava-overlay-7ic01ylp/lava-978668/bin/lava-target-storage
176 08:23:49.711895 Creating /var/lib/lava/dispatcher/tmp/978668/lava-overlay-7ic01ylp/lava-978668/bin/lava-test-case
177 08:23:49.712410 Creating /var/lib/lava/dispatcher/tmp/978668/lava-overlay-7ic01ylp/lava-978668/bin/lava-test-event
178 08:23:49.712955 Creating /var/lib/lava/dispatcher/tmp/978668/lava-overlay-7ic01ylp/lava-978668/bin/lava-test-feedback
179 08:23:49.713436 Creating /var/lib/lava/dispatcher/tmp/978668/lava-overlay-7ic01ylp/lava-978668/bin/lava-test-raise
180 08:23:49.713920 Creating /var/lib/lava/dispatcher/tmp/978668/lava-overlay-7ic01ylp/lava-978668/bin/lava-test-reference
181 08:23:49.714411 Creating /var/lib/lava/dispatcher/tmp/978668/lava-overlay-7ic01ylp/lava-978668/bin/lava-test-runner
182 08:23:49.714887 Creating /var/lib/lava/dispatcher/tmp/978668/lava-overlay-7ic01ylp/lava-978668/bin/lava-test-set
183 08:23:49.715356 Creating /var/lib/lava/dispatcher/tmp/978668/lava-overlay-7ic01ylp/lava-978668/bin/lava-test-shell
184 08:23:49.715841 Updating /var/lib/lava/dispatcher/tmp/978668/lava-overlay-7ic01ylp/lava-978668/bin/lava-add-keys (debian)
185 08:23:49.716399 Updating /var/lib/lava/dispatcher/tmp/978668/lava-overlay-7ic01ylp/lava-978668/bin/lava-add-sources (debian)
186 08:23:49.716897 Updating /var/lib/lava/dispatcher/tmp/978668/lava-overlay-7ic01ylp/lava-978668/bin/lava-install-packages (debian)
187 08:23:49.717384 Updating /var/lib/lava/dispatcher/tmp/978668/lava-overlay-7ic01ylp/lava-978668/bin/lava-installed-packages (debian)
188 08:23:49.717866 Updating /var/lib/lava/dispatcher/tmp/978668/lava-overlay-7ic01ylp/lava-978668/bin/lava-os-build (debian)
189 08:23:49.718288 Creating /var/lib/lava/dispatcher/tmp/978668/lava-overlay-7ic01ylp/lava-978668/environment
190 08:23:49.718647 LAVA metadata
191 08:23:49.718902 - LAVA_JOB_ID=978668
192 08:23:49.719118 - LAVA_DISPATCHER_IP=192.168.6.2
193 08:23:49.719465 start: 1.6.2.1 ssh-authorize (timeout 00:09:27) [common]
194 08:23:49.720439 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
195 08:23:49.720756 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:27) [common]
196 08:23:49.720961 skipped lava-vland-overlay
197 08:23:49.721200 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
198 08:23:49.721450 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:27) [common]
199 08:23:49.721665 skipped lava-multinode-overlay
200 08:23:49.721907 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
201 08:23:49.722154 start: 1.6.2.4 test-definition (timeout 00:09:27) [common]
202 08:23:49.722395 Loading test definitions
203 08:23:49.722666 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:27) [common]
204 08:23:49.722885 Using /lava-978668 at stage 0
205 08:23:49.723944 uuid=978668_1.6.2.4.1 testdef=None
206 08:23:49.724268 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
207 08:23:49.724529 start: 1.6.2.4.2 test-overlay (timeout 00:09:27) [common]
208 08:23:49.726056 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
210 08:23:49.726833 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:27) [common]
211 08:23:49.728751 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
213 08:23:49.729565 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:27) [common]
214 08:23:49.731350 runner path: /var/lib/lava/dispatcher/tmp/978668/lava-overlay-7ic01ylp/lava-978668/0/tests/0_timesync-off test_uuid 978668_1.6.2.4.1
215 08:23:49.731893 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
217 08:23:49.732726 start: 1.6.2.4.5 git-repo-action (timeout 00:09:27) [common]
218 08:23:49.732947 Using /lava-978668 at stage 0
219 08:23:49.733289 Fetching tests from https://github.com/kernelci/test-definitions.git
220 08:23:49.733574 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/978668/lava-overlay-7ic01ylp/lava-978668/0/tests/1_kselftest-alsa'
221 08:23:53.217773 Running '/usr/bin/git checkout kernelci.org
222 08:23:53.453855 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/978668/lava-overlay-7ic01ylp/lava-978668/0/tests/1_kselftest-alsa/automated/linux/kselftest/kselftest.yaml
223 08:23:53.455329 uuid=978668_1.6.2.4.5 testdef=None
224 08:23:53.455676 end: 1.6.2.4.5 git-repo-action (duration 00:00:04) [common]
226 08:23:53.456903 start: 1.6.2.4.6 test-overlay (timeout 00:09:23) [common]
227 08:23:53.462278 end: 1.6.2.4.6 test-overlay (duration 00:00:00) [common]
229 08:23:53.463831 start: 1.6.2.4.7 test-install-overlay (timeout 00:09:23) [common]
230 08:23:53.470923 end: 1.6.2.4.7 test-install-overlay (duration 00:00:00) [common]
232 08:23:53.472585 start: 1.6.2.4.8 test-runscript-overlay (timeout 00:09:23) [common]
233 08:23:53.479430 runner path: /var/lib/lava/dispatcher/tmp/978668/lava-overlay-7ic01ylp/lava-978668/0/tests/1_kselftest-alsa test_uuid 978668_1.6.2.4.5
234 08:23:53.479947 BOARD='meson-g12b-a311d-libretech-cc'
235 08:23:53.480411 BRANCH='next'
236 08:23:53.480801 SKIPFILE='/dev/null'
237 08:23:53.481191 SKIP_INSTALL='True'
238 08:23:53.481574 TESTPROG_URL='http://storage.kernelci.org/next/master/next-20241112/arm64/defconfig/gcc-12/kselftest.tar.xz'
239 08:23:53.481965 TST_CASENAME=''
240 08:23:53.482358 TST_CMDFILES='alsa'
241 08:23:53.483307 end: 1.6.2.4.8 test-runscript-overlay (duration 00:00:00) [common]
243 08:23:53.484864 Creating lava-test-runner.conf files
244 08:23:53.485269 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/978668/lava-overlay-7ic01ylp/lava-978668/0 for stage 0
245 08:23:53.485901 - 0_timesync-off
246 08:23:53.486346 - 1_kselftest-alsa
247 08:23:53.486967 end: 1.6.2.4 test-definition (duration 00:00:04) [common]
248 08:23:53.487496 start: 1.6.2.5 compress-overlay (timeout 00:09:23) [common]
249 08:24:16.771577 end: 1.6.2.5 compress-overlay (duration 00:00:23) [common]
250 08:24:16.772050 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:08:59) [common]
251 08:24:16.772321 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
252 08:24:16.772592 end: 1.6.2 lava-overlay (duration 00:00:27) [common]
253 08:24:16.772855 start: 1.6.3 extract-overlay-ramdisk (timeout 00:08:59) [common]
254 08:24:17.384767 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:01) [common]
255 08:24:17.385251 start: 1.6.4 extract-modules (timeout 00:08:59) [common]
256 08:24:17.385504 extracting modules file /var/lib/lava/dispatcher/tmp/978668/tftp-deploy-ojpnit67/modules/modules.tar to /var/lib/lava/dispatcher/tmp/978668/extract-nfsrootfs-iaw2q4k4
257 08:24:18.782835 extracting modules file /var/lib/lava/dispatcher/tmp/978668/tftp-deploy-ojpnit67/modules/modules.tar to /var/lib/lava/dispatcher/tmp/978668/extract-overlay-ramdisk-gso1ekxp/ramdisk
258 08:24:20.196763 end: 1.6.4 extract-modules (duration 00:00:03) [common]
259 08:24:20.197243 start: 1.6.5 apply-overlay-tftp (timeout 00:08:56) [common]
260 08:24:20.197540 [common] Applying overlay to NFS
261 08:24:20.197768 [common] Applying overlay /var/lib/lava/dispatcher/tmp/978668/compress-overlay-two6epkj/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/978668/extract-nfsrootfs-iaw2q4k4
262 08:24:22.925240 end: 1.6.5 apply-overlay-tftp (duration 00:00:03) [common]
263 08:24:22.925714 start: 1.6.6 prepare-kernel (timeout 00:08:53) [common]
264 08:24:22.926016 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:08:53) [common]
265 08:24:22.926275 Converting downloaded kernel to a uImage
266 08:24:22.926612 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/978668/tftp-deploy-ojpnit67/kernel/Image /var/lib/lava/dispatcher/tmp/978668/tftp-deploy-ojpnit67/kernel/uImage
267 08:24:23.427827 output: Image Name:
268 08:24:23.428286 output: Created: Tue Nov 12 08:24:22 2024
269 08:24:23.428514 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
270 08:24:23.428726 output: Data Size: 46121472 Bytes = 45040.50 KiB = 43.98 MiB
271 08:24:23.428933 output: Load Address: 01080000
272 08:24:23.429142 output: Entry Point: 01080000
273 08:24:23.429349 output:
274 08:24:23.429691 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:01) [common]
275 08:24:23.429970 end: 1.6.6 prepare-kernel (duration 00:00:01) [common]
276 08:24:23.430251 start: 1.6.7 configure-preseed-file (timeout 00:08:53) [common]
277 08:24:23.430514 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
278 08:24:23.430783 start: 1.6.8 compress-ramdisk (timeout 00:08:53) [common]
279 08:24:23.431048 Building ramdisk /var/lib/lava/dispatcher/tmp/978668/extract-overlay-ramdisk-gso1ekxp/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/978668/extract-overlay-ramdisk-gso1ekxp/ramdisk
280 08:24:25.618653 >> 168134 blocks
281 08:24:33.390001 Adding RAMdisk u-boot header.
282 08:24:33.390675 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/978668/extract-overlay-ramdisk-gso1ekxp/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/978668/extract-overlay-ramdisk-gso1ekxp/ramdisk.cpio.gz.uboot
283 08:24:33.659684 output: Image Name:
284 08:24:33.660209 output: Created: Tue Nov 12 08:24:33 2024
285 08:24:33.660703 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
286 08:24:33.661185 output: Data Size: 23562824 Bytes = 23010.57 KiB = 22.47 MiB
287 08:24:33.661653 output: Load Address: 00000000
288 08:24:33.662107 output: Entry Point: 00000000
289 08:24:33.662555 output:
290 08:24:33.663594 rename /var/lib/lava/dispatcher/tmp/978668/extract-overlay-ramdisk-gso1ekxp/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/978668/tftp-deploy-ojpnit67/ramdisk/ramdisk.cpio.gz.uboot
291 08:24:33.664415 end: 1.6.8 compress-ramdisk (duration 00:00:10) [common]
292 08:24:33.665029 end: 1.6 prepare-tftp-overlay (duration 00:01:00) [common]
293 08:24:33.665626 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:43) [common]
294 08:24:33.666133 No LXC device requested
295 08:24:33.666695 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
296 08:24:33.667270 start: 1.8 deploy-device-env (timeout 00:08:43) [common]
297 08:24:33.667829 end: 1.8 deploy-device-env (duration 00:00:00) [common]
298 08:24:33.668338 Checking files for TFTP limit of 4294967296 bytes.
299 08:24:33.671267 end: 1 tftp-deploy (duration 00:01:17) [common]
300 08:24:33.671898 start: 2 uboot-action (timeout 00:05:00) [common]
301 08:24:33.672534 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
302 08:24:33.673098 end: 2.1 uboot-from-media (duration 00:00:00) [common]
303 08:24:33.673664 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
304 08:24:33.674252 Using kernel file from prepare-kernel: 978668/tftp-deploy-ojpnit67/kernel/uImage
305 08:24:33.674952 substitutions:
306 08:24:33.675407 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
307 08:24:33.675857 - {DTB_ADDR}: 0x01070000
308 08:24:33.676345 - {DTB}: 978668/tftp-deploy-ojpnit67/dtb/meson-g12b-a311d-libretech-cc.dtb
309 08:24:33.676797 - {INITRD}: 978668/tftp-deploy-ojpnit67/ramdisk/ramdisk.cpio.gz.uboot
310 08:24:33.677242 - {KERNEL_ADDR}: 0x01080000
311 08:24:33.677681 - {KERNEL}: 978668/tftp-deploy-ojpnit67/kernel/uImage
312 08:24:33.678118 - {LAVA_MAC}: None
313 08:24:33.678599 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/978668/extract-nfsrootfs-iaw2q4k4
314 08:24:33.679043 - {NFS_SERVER_IP}: 192.168.6.2
315 08:24:33.679480 - {PRESEED_CONFIG}: None
316 08:24:33.679914 - {PRESEED_LOCAL}: None
317 08:24:33.680421 - {RAMDISK_ADDR}: 0x08000000
318 08:24:33.680862 - {RAMDISK}: 978668/tftp-deploy-ojpnit67/ramdisk/ramdisk.cpio.gz.uboot
319 08:24:33.681302 - {ROOT_PART}: None
320 08:24:33.681743 - {ROOT}: None
321 08:24:33.682179 - {SERVER_IP}: 192.168.6.2
322 08:24:33.682611 - {TEE_ADDR}: 0x83000000
323 08:24:33.683038 - {TEE}: None
324 08:24:33.683469 Parsed boot commands:
325 08:24:33.683886 - setenv autoload no
326 08:24:33.684366 - setenv initrd_high 0xffffffff
327 08:24:33.684800 - setenv fdt_high 0xffffffff
328 08:24:33.685233 - dhcp
329 08:24:33.685659 - setenv serverip 192.168.6.2
330 08:24:33.686089 - tftpboot 0x01080000 978668/tftp-deploy-ojpnit67/kernel/uImage
331 08:24:33.686522 - tftpboot 0x08000000 978668/tftp-deploy-ojpnit67/ramdisk/ramdisk.cpio.gz.uboot
332 08:24:33.686957 - tftpboot 0x01070000 978668/tftp-deploy-ojpnit67/dtb/meson-g12b-a311d-libretech-cc.dtb
333 08:24:33.687392 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/978668/extract-nfsrootfs-iaw2q4k4,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
334 08:24:33.687840 - bootm 0x01080000 0x08000000 0x01070000
335 08:24:33.688423 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
337 08:24:33.690082 start: 2.3 connect-device (timeout 00:05:00) [common]
338 08:24:33.690555 [common] connect-device Connecting to device using 'telnet conserv1 3007'
339 08:24:33.707545 Setting prompt string to ['lava-test: # ']
340 08:24:33.709215 end: 2.3 connect-device (duration 00:00:00) [common]
341 08:24:33.709908 start: 2.4 uboot-commands (timeout 00:05:00) [common]
342 08:24:33.710795 start: 2.4.1 reset-device (timeout 00:05:00) [common]
343 08:24:33.711546 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
344 08:24:33.712884 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
345 08:24:33.752571 >> OK - accepted request
346 08:24:33.754647 Returned 0 in 0 seconds
347 08:24:33.855837 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
349 08:24:33.857696 end: 2.4.1 reset-device (duration 00:00:00) [common]
350 08:24:33.858320 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
351 08:24:33.858892 Setting prompt string to ['Hit any key to stop autoboot']
352 08:24:33.859402 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
353 08:24:33.861122 Trying 192.168.56.21...
354 08:24:33.861640 Connected to conserv1.
355 08:24:33.862113 Escape character is '^]'.
356 08:24:33.862587
357 08:24:33.863056 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
358 08:24:33.863533
359 08:24:44.714880 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
360 08:24:44.715559 bl2_stage_init 0x01
361 08:24:44.716115 bl2_stage_init 0x81
362 08:24:44.720538 hw id: 0x0000 - pwm id 0x01
363 08:24:44.721088 bl2_stage_init 0xc1
364 08:24:44.721593 bl2_stage_init 0x02
365 08:24:44.722064
366 08:24:44.726118 L0:00000000
367 08:24:44.726640 L1:20000703
368 08:24:44.727102 L2:00008067
369 08:24:44.727543 L3:14000000
370 08:24:44.731701 B2:00402000
371 08:24:44.732224 B1:e0f83180
372 08:24:44.732674
373 08:24:44.733106 TE: 58124
374 08:24:44.733536
375 08:24:44.737201 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
376 08:24:44.737661
377 08:24:44.738095 Board ID = 1
378 08:24:44.742761 Set A53 clk to 24M
379 08:24:44.743213 Set A73 clk to 24M
380 08:24:44.743640 Set clk81 to 24M
381 08:24:44.748466 A53 clk: 1200 MHz
382 08:24:44.748925 A73 clk: 1200 MHz
383 08:24:44.749351 CLK81: 166.6M
384 08:24:44.749773 smccc: 00012a92
385 08:24:44.753880 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
386 08:24:44.759532 board id: 1
387 08:24:44.765809 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
388 08:24:44.776028 fw parse done
389 08:24:44.781970 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
390 08:24:44.824645 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
391 08:24:44.835511 PIEI prepare done
392 08:24:44.835973 fastboot data load
393 08:24:44.836456 fastboot data verify
394 08:24:44.841293 verify result: 266
395 08:24:44.846797 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
396 08:24:44.847309 LPDDR4 probe
397 08:24:44.847760 ddr clk to 1584MHz
398 08:24:44.854759 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
399 08:24:44.892032
400 08:24:44.892516 dmc_version 0001
401 08:24:44.898747 Check phy result
402 08:24:44.904624 INFO : End of CA training
403 08:24:44.905109 INFO : End of initialization
404 08:24:44.910281 INFO : Training has run successfully!
405 08:24:44.910750 Check phy result
406 08:24:44.915735 INFO : End of initialization
407 08:24:44.916250 INFO : End of read enable training
408 08:24:44.919120 INFO : End of fine write leveling
409 08:24:44.924708 INFO : End of Write leveling coarse delay
410 08:24:44.930329 INFO : Training has run successfully!
411 08:24:44.930804 Check phy result
412 08:24:44.931250 INFO : End of initialization
413 08:24:44.935872 INFO : End of read dq deskew training
414 08:24:44.941564 INFO : End of MPR read delay center optimization
415 08:24:44.942037 INFO : End of write delay center optimization
416 08:24:44.947060 INFO : End of read delay center optimization
417 08:24:44.952617 INFO : End of max read latency training
418 08:24:44.953096 INFO : Training has run successfully!
419 08:24:44.958286 1D training succeed
420 08:24:44.964229 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
421 08:24:45.011743 Check phy result
422 08:24:45.012309 INFO : End of initialization
423 08:24:45.033658 INFO : End of 2D read delay Voltage center optimization
424 08:24:45.053745 INFO : End of 2D read delay Voltage center optimization
425 08:24:45.105837 INFO : End of 2D write delay Voltage center optimization
426 08:24:45.155269 INFO : End of 2D write delay Voltage center optimization
427 08:24:45.160779 INFO : Training has run successfully!
428 08:24:45.161254
429 08:24:45.161691 channel==0
430 08:24:45.166356 RxClkDly_Margin_A0==88 ps 9
431 08:24:45.166815 TxDqDly_Margin_A0==98 ps 10
432 08:24:45.171913 RxClkDly_Margin_A1==88 ps 9
433 08:24:45.172402 TxDqDly_Margin_A1==98 ps 10
434 08:24:45.172840 TrainedVREFDQ_A0==74
435 08:24:45.177576 TrainedVREFDQ_A1==74
436 08:24:45.178037 VrefDac_Margin_A0==25
437 08:24:45.178470 DeviceVref_Margin_A0==40
438 08:24:45.183175 VrefDac_Margin_A1==26
439 08:24:45.183629 DeviceVref_Margin_A1==40
440 08:24:45.184091
441 08:24:45.184522
442 08:24:45.188780 channel==1
443 08:24:45.189239 RxClkDly_Margin_A0==98 ps 10
444 08:24:45.189668 TxDqDly_Margin_A0==88 ps 9
445 08:24:45.194353 RxClkDly_Margin_A1==98 ps 10
446 08:24:45.194812 TxDqDly_Margin_A1==98 ps 10
447 08:24:45.200010 TrainedVREFDQ_A0==77
448 08:24:45.200471 TrainedVREFDQ_A1==77
449 08:24:45.200906 VrefDac_Margin_A0==22
450 08:24:45.205685 DeviceVref_Margin_A0==37
451 08:24:45.206142 VrefDac_Margin_A1==22
452 08:24:45.211194 DeviceVref_Margin_A1==37
453 08:24:45.211649
454 08:24:45.212114 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
455 08:24:45.212548
456 08:24:45.244811 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000018 00000019 00000018 00000019 00000018 00000019 0000001a 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
457 08:24:45.245344 2D training succeed
458 08:24:45.250537 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
459 08:24:45.256045 auto size-- 65535DDR cs0 size: 2048MB
460 08:24:45.256512 DDR cs1 size: 2048MB
461 08:24:45.261601 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
462 08:24:45.262060 cs0 DataBus test pass
463 08:24:45.267271 cs1 DataBus test pass
464 08:24:45.267723 cs0 AddrBus test pass
465 08:24:45.268199 cs1 AddrBus test pass
466 08:24:45.268629
467 08:24:45.272800 100bdlr_step_size ps== 420
468 08:24:45.273271 result report
469 08:24:45.278540 boot times 0Enable ddr reg access
470 08:24:45.283797 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
471 08:24:45.297250 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
472 08:24:45.871146 0.0;M3 CHK:0;cm4_sp_mode 0
473 08:24:45.871795 MVN_1=0x00000000
474 08:24:45.876487 MVN_2=0x00000000
475 08:24:45.882250 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
476 08:24:45.882723 OPS=0x10
477 08:24:45.883166 ring efuse init
478 08:24:45.883600 chipver efuse init
479 08:24:45.887640 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
480 08:24:45.893330 [0.018961 Inits done]
481 08:24:45.893799 secure task start!
482 08:24:45.894234 high task start!
483 08:24:45.897921 low task start!
484 08:24:45.898388 run into bl31
485 08:24:45.904675 NOTICE: BL31: v1.3(release):4fc40b1
486 08:24:45.912440 NOTICE: BL31: Built : 15:58:17, May 22 2019
487 08:24:45.912915 NOTICE: BL31: G12A normal boot!
488 08:24:45.937804 NOTICE: BL31: BL33 decompress pass
489 08:24:45.943511 ERROR: Error initializing runtime service opteed_fast
490 08:24:47.176499
491 08:24:47.177169
492 08:24:47.184734 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
493 08:24:47.185227
494 08:24:47.185682 Model: Libre Computer AML-A311D-CC Alta
495 08:24:47.393296 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
496 08:24:47.416574 DRAM: 2 GiB (effective 3.8 GiB)
497 08:24:47.559631 Core: 408 devices, 31 uclasses, devicetree: separate
498 08:24:47.565537 WDT: Not starting watchdog@f0d0
499 08:24:47.597718 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
500 08:24:47.610296 Loading Environment from FAT... Card did not respond to voltage select! : -110
501 08:24:47.615239 ** Bad device specification mmc 0 **
502 08:24:47.625569 Card did not respond to voltage select! : -110
503 08:24:47.633115 ** Bad device specification mmc 0 **
504 08:24:47.633585 Couldn't find partition mmc 0
505 08:24:47.641375 Card did not respond to voltage select! : -110
506 08:24:47.646986 ** Bad device specification mmc 0 **
507 08:24:47.647460 Couldn't find partition mmc 0
508 08:24:47.652097 Error: could not access storage.
509 08:24:48.915543 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
510 08:24:48.916246 bl2_stage_init 0x01
511 08:24:48.916718 bl2_stage_init 0x81
512 08:24:48.921060 hw id: 0x0000 - pwm id 0x01
513 08:24:48.921528 bl2_stage_init 0xc1
514 08:24:48.921978 bl2_stage_init 0x02
515 08:24:48.922423
516 08:24:48.926721 L0:00000000
517 08:24:48.927205 L1:20000703
518 08:24:48.927651 L2:00008067
519 08:24:48.928122 L3:14000000
520 08:24:48.932267 B2:00402000
521 08:24:48.932737 B1:e0f83180
522 08:24:48.933176
523 08:24:48.933617 TE: 58124
524 08:24:48.934057
525 08:24:48.937999 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
526 08:24:48.938475
527 08:24:48.938919 Board ID = 1
528 08:24:48.943477 Set A53 clk to 24M
529 08:24:48.943947 Set A73 clk to 24M
530 08:24:48.944437 Set clk81 to 24M
531 08:24:48.949166 A53 clk: 1200 MHz
532 08:24:48.949639 A73 clk: 1200 MHz
533 08:24:48.950079 CLK81: 166.6M
534 08:24:48.950514 smccc: 00012a92
535 08:24:48.954656 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
536 08:24:48.960256 board id: 1
537 08:24:48.966149 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
538 08:24:48.976787 fw parse done
539 08:24:48.982821 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
540 08:24:49.025421 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
541 08:24:49.036237 PIEI prepare done
542 08:24:49.036722 fastboot data load
543 08:24:49.037179 fastboot data verify
544 08:24:49.042133 verify result: 266
545 08:24:49.047545 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
546 08:24:49.048075 LPDDR4 probe
547 08:24:49.048531 ddr clk to 1584MHz
548 08:24:49.055487 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
549 08:24:49.092809
550 08:24:49.093305 dmc_version 0001
551 08:24:49.099497 Check phy result
552 08:24:49.105351 INFO : End of CA training
553 08:24:49.105826 INFO : End of initialization
554 08:24:49.110926 INFO : Training has run successfully!
555 08:24:49.111418 Check phy result
556 08:24:49.116477 INFO : End of initialization
557 08:24:49.116944 INFO : End of read enable training
558 08:24:49.119862 INFO : End of fine write leveling
559 08:24:49.125481 INFO : End of Write leveling coarse delay
560 08:24:49.131092 INFO : Training has run successfully!
561 08:24:49.131558 Check phy result
562 08:24:49.132037 INFO : End of initialization
563 08:24:49.136703 INFO : End of read dq deskew training
564 08:24:49.142310 INFO : End of MPR read delay center optimization
565 08:24:49.142779 INFO : End of write delay center optimization
566 08:24:49.147928 INFO : End of read delay center optimization
567 08:24:49.153486 INFO : End of max read latency training
568 08:24:49.153959 INFO : Training has run successfully!
569 08:24:49.159100 1D training succeed
570 08:24:49.164939 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
571 08:24:49.212516 Check phy result
572 08:24:49.212982 INFO : End of initialization
573 08:24:49.234293 INFO : End of 2D read delay Voltage center optimization
574 08:24:49.254509 INFO : End of 2D read delay Voltage center optimization
575 08:24:49.306595 INFO : End of 2D write delay Voltage center optimization
576 08:24:49.356040 INFO : End of 2D write delay Voltage center optimization
577 08:24:49.361509 INFO : Training has run successfully!
578 08:24:49.361993
579 08:24:49.362442 channel==0
580 08:24:49.367151 RxClkDly_Margin_A0==78 ps 8
581 08:24:49.367636 TxDqDly_Margin_A0==98 ps 10
582 08:24:49.370459 RxClkDly_Margin_A1==88 ps 9
583 08:24:49.370948 TxDqDly_Margin_A1==88 ps 9
584 08:24:49.375966 TrainedVREFDQ_A0==74
585 08:24:49.376470 TrainedVREFDQ_A1==74
586 08:24:49.376918 VrefDac_Margin_A0==25
587 08:24:49.381526 DeviceVref_Margin_A0==40
588 08:24:49.381994 VrefDac_Margin_A1==25
589 08:24:49.387231 DeviceVref_Margin_A1==40
590 08:24:49.387704
591 08:24:49.388191
592 08:24:49.388636 channel==1
593 08:24:49.389070 RxClkDly_Margin_A0==88 ps 9
594 08:24:49.392781 TxDqDly_Margin_A0==98 ps 10
595 08:24:49.393256 RxClkDly_Margin_A1==88 ps 9
596 08:24:49.398395 TxDqDly_Margin_A1==88 ps 9
597 08:24:49.398869 TrainedVREFDQ_A0==77
598 08:24:49.399311 TrainedVREFDQ_A1==77
599 08:24:49.403967 VrefDac_Margin_A0==22
600 08:24:49.404469 DeviceVref_Margin_A0==37
601 08:24:49.409561 VrefDac_Margin_A1==24
602 08:24:49.410030 DeviceVref_Margin_A1==37
603 08:24:49.410474
604 08:24:49.415158 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
605 08:24:49.415629
606 08:24:49.443162 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000018 00000015 00000018 00000018 00000017 00000019 00000018 0000001a 0000001a 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000019 00000018 dram_vref_reg_value 0x 00000060
607 08:24:49.448736 2D training succeed
608 08:24:49.454377 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
609 08:24:49.454857 auto size-- 65535DDR cs0 size: 2048MB
610 08:24:49.459922 DDR cs1 size: 2048MB
611 08:24:49.460444 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
612 08:24:49.465528 cs0 DataBus test pass
613 08:24:49.466015 cs1 DataBus test pass
614 08:24:49.466462 cs0 AddrBus test pass
615 08:24:49.471164 cs1 AddrBus test pass
616 08:24:49.471634
617 08:24:49.472108 100bdlr_step_size ps== 420
618 08:24:49.472560 result report
619 08:24:49.476727 boot times 0Enable ddr reg access
620 08:24:49.484367 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
621 08:24:49.497789 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
622 08:24:50.070855 0.0;M3 CHK:0;cm4_sp_mode 0
623 08:24:50.071480 MVN_1=0x00000000
624 08:24:50.076220 MVN_2=0x00000000
625 08:24:50.081983 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
626 08:24:50.082496 OPS=0x10
627 08:24:50.082962 ring efuse init
628 08:24:50.083434 chipver efuse init
629 08:24:50.087664 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
630 08:24:50.093249 [0.018960 Inits done]
631 08:24:50.093723 secure task start!
632 08:24:50.094155 high task start!
633 08:24:50.097865 low task start!
634 08:24:50.098322 run into bl31
635 08:24:50.104544 NOTICE: BL31: v1.3(release):4fc40b1
636 08:24:50.113317 NOTICE: BL31: Built : 15:58:17, May 22 2019
637 08:24:50.113823 NOTICE: BL31: G12A normal boot!
638 08:24:50.138400 NOTICE: BL31: BL33 decompress pass
639 08:24:50.144409 ERROR: Error initializing runtime service opteed_fast
640 08:24:51.376973
641 08:24:51.377651
642 08:24:51.385265 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
643 08:24:51.385762
644 08:24:51.386224 Model: Libre Computer AML-A311D-CC Alta
645 08:24:51.593708 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
646 08:24:51.617021 DRAM: 2 GiB (effective 3.8 GiB)
647 08:24:51.759853 Core: 408 devices, 31 uclasses, devicetree: separate
648 08:24:51.765900 WDT: Not starting watchdog@f0d0
649 08:24:51.798212 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
650 08:24:51.810581 Loading Environment from FAT... Card did not respond to voltage select! : -110
651 08:24:51.815599 ** Bad device specification mmc 0 **
652 08:24:51.825881 Card did not respond to voltage select! : -110
653 08:24:51.833622 ** Bad device specification mmc 0 **
654 08:24:51.834100 Couldn't find partition mmc 0
655 08:24:51.841856 Card did not respond to voltage select! : -110
656 08:24:51.847372 ** Bad device specification mmc 0 **
657 08:24:51.847846 Couldn't find partition mmc 0
658 08:24:51.852486 Error: could not access storage.
659 08:24:52.195020 Net: eth0: ethernet@ff3f0000
660 08:24:52.195620 starting USB...
661 08:24:52.446799 Bus usb@ff500000: Register 3000140 NbrPorts 3
662 08:24:52.447382 Starting the controller
663 08:24:52.453687 USB XHCI 1.10
664 08:24:54.164113 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
665 08:24:54.164810 bl2_stage_init 0x01
666 08:24:54.165284 bl2_stage_init 0x81
667 08:24:54.169745 hw id: 0x0000 - pwm id 0x01
668 08:24:54.170236 bl2_stage_init 0xc1
669 08:24:54.170692 bl2_stage_init 0x02
670 08:24:54.171138
671 08:24:54.175355 L0:00000000
672 08:24:54.175835 L1:20000703
673 08:24:54.176354 L2:00008067
674 08:24:54.176801 L3:14000000
675 08:24:54.180942 B2:00402000
676 08:24:54.181425 B1:e0f83180
677 08:24:54.181870
678 08:24:54.182311 TE: 58159
679 08:24:54.182749
680 08:24:54.186455 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
681 08:24:54.186937
682 08:24:54.187383 Board ID = 1
683 08:24:54.192127 Set A53 clk to 24M
684 08:24:54.192606 Set A73 clk to 24M
685 08:24:54.193046 Set clk81 to 24M
686 08:24:54.197833 A53 clk: 1200 MHz
687 08:24:54.198310 A73 clk: 1200 MHz
688 08:24:54.198753 CLK81: 166.6M
689 08:24:54.199194 smccc: 00012ab5
690 08:24:54.203302 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
691 08:24:54.208940 board id: 1
692 08:24:54.214796 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
693 08:24:54.225436 fw parse done
694 08:24:54.231348 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
695 08:24:54.273991 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
696 08:24:54.284894 PIEI prepare done
697 08:24:54.285376 fastboot data load
698 08:24:54.285830 fastboot data verify
699 08:24:54.290656 verify result: 266
700 08:24:54.296217 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
701 08:24:54.296692 LPDDR4 probe
702 08:24:54.297135 ddr clk to 1584MHz
703 08:24:54.304184 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
704 08:24:54.341684
705 08:24:54.342205 dmc_version 0001
706 08:24:54.348305 Check phy result
707 08:24:54.353980 INFO : End of CA training
708 08:24:54.354465 INFO : End of initialization
709 08:24:54.359602 INFO : Training has run successfully!
710 08:24:54.360130 Check phy result
711 08:24:54.365204 INFO : End of initialization
712 08:24:54.365693 INFO : End of read enable training
713 08:24:54.370862 INFO : End of fine write leveling
714 08:24:54.376399 INFO : End of Write leveling coarse delay
715 08:24:54.376874 INFO : Training has run successfully!
716 08:24:54.377320 Check phy result
717 08:24:54.382005 INFO : End of initialization
718 08:24:54.382479 INFO : End of read dq deskew training
719 08:24:54.387575 INFO : End of MPR read delay center optimization
720 08:24:54.393183 INFO : End of write delay center optimization
721 08:24:54.398834 INFO : End of read delay center optimization
722 08:24:54.399311 INFO : End of max read latency training
723 08:24:54.404351 INFO : Training has run successfully!
724 08:24:54.404829 1D training succeed
725 08:24:54.413575 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
726 08:24:54.461153 Check phy result
727 08:24:54.461627 INFO : End of initialization
728 08:24:54.482927 INFO : End of 2D read delay Voltage center optimization
729 08:24:54.503104 INFO : End of 2D read delay Voltage center optimization
730 08:24:54.555156 INFO : End of 2D write delay Voltage center optimization
731 08:24:54.604517 INFO : End of 2D write delay Voltage center optimization
732 08:24:54.610111 INFO : Training has run successfully!
733 08:24:54.610586
734 08:24:54.611037 channel==0
735 08:24:54.615675 RxClkDly_Margin_A0==88 ps 9
736 08:24:54.616191 TxDqDly_Margin_A0==98 ps 10
737 08:24:54.621299 RxClkDly_Margin_A1==88 ps 9
738 08:24:54.621772 TxDqDly_Margin_A1==98 ps 10
739 08:24:54.622223 TrainedVREFDQ_A0==74
740 08:24:54.626923 TrainedVREFDQ_A1==74
741 08:24:54.627400 VrefDac_Margin_A0==25
742 08:24:54.627849 DeviceVref_Margin_A0==40
743 08:24:54.632583 VrefDac_Margin_A1==25
744 08:24:54.633051 DeviceVref_Margin_A1==40
745 08:24:54.633491
746 08:24:54.633928
747 08:24:54.638098 channel==1
748 08:24:54.638584 RxClkDly_Margin_A0==98 ps 10
749 08:24:54.639027 TxDqDly_Margin_A0==98 ps 10
750 08:24:54.643687 RxClkDly_Margin_A1==98 ps 10
751 08:24:54.644190 TxDqDly_Margin_A1==88 ps 9
752 08:24:54.649316 TrainedVREFDQ_A0==77
753 08:24:54.649796 TrainedVREFDQ_A1==77
754 08:24:54.650245 VrefDac_Margin_A0==23
755 08:24:54.654923 DeviceVref_Margin_A0==37
756 08:24:54.655392 VrefDac_Margin_A1==22
757 08:24:54.660431 DeviceVref_Margin_A1==37
758 08:24:54.660904
759 08:24:54.661348 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
760 08:24:54.666079
761 08:24:54.694037 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000018 00000019 00000017 00000019 00000018 00000019 0000001a 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
762 08:24:54.694537 2D training succeed
763 08:24:54.699633 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
764 08:24:54.705218 auto size-- 65535DDR cs0 size: 2048MB
765 08:24:54.705689 DDR cs1 size: 2048MB
766 08:24:54.710844 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
767 08:24:54.711313 cs0 DataBus test pass
768 08:24:54.716441 cs1 DataBus test pass
769 08:24:54.716907 cs0 AddrBus test pass
770 08:24:54.717347 cs1 AddrBus test pass
771 08:24:54.717781
772 08:24:54.722497 100bdlr_step_size ps== 420
773 08:24:54.722980 result report
774 08:24:54.727662 boot times 0Enable ddr reg access
775 08:24:54.733079 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
776 08:24:54.745638 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
777 08:24:55.320283 0.0;M3 CHK:0;cm4_sp_mode 0
778 08:24:55.320938 MVN_1=0x00000000
779 08:24:55.325686 MVN_2=0x00000000
780 08:24:55.331464 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
781 08:24:55.332055 OPS=0x10
782 08:24:55.332505 ring efuse init
783 08:24:55.332934 chipver efuse init
784 08:24:55.337013 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
785 08:24:55.342733 [0.018961 Inits done]
786 08:24:55.343209 secure task start!
787 08:24:55.343644 high task start!
788 08:24:55.347317 low task start!
789 08:24:55.347786 run into bl31
790 08:24:55.353886 NOTICE: BL31: v1.3(release):4fc40b1
791 08:24:55.361679 NOTICE: BL31: Built : 15:58:17, May 22 2019
792 08:24:55.362151 NOTICE: BL31: G12A normal boot!
793 08:24:55.387095 NOTICE: BL31: BL33 decompress pass
794 08:24:55.392742 ERROR: Error initializing runtime service opteed_fast
795 08:24:56.625754
796 08:24:56.626422
797 08:24:56.634084 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
798 08:24:56.634570
799 08:24:56.635047 Model: Libre Computer AML-A311D-CC Alta
800 08:24:56.842373 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
801 08:24:56.865861 DRAM: 2 GiB (effective 3.8 GiB)
802 08:24:57.008806 Core: 408 devices, 31 uclasses, devicetree: separate
803 08:24:57.014769 WDT: Not starting watchdog@f0d0
804 08:24:57.047098 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
805 08:24:57.059446 Loading Environment from FAT... Card did not respond to voltage select! : -110
806 08:24:57.064419 ** Bad device specification mmc 0 **
807 08:24:57.074815 Card did not respond to voltage select! : -110
808 08:24:57.082411 ** Bad device specification mmc 0 **
809 08:24:57.082896 Couldn't find partition mmc 0
810 08:24:57.090817 Card did not respond to voltage select! : -110
811 08:24:57.096282 ** Bad device specification mmc 0 **
812 08:24:57.096756 Couldn't find partition mmc 0
813 08:24:57.101331 Error: could not access storage.
814 08:24:57.443820 Net: eth0: ethernet@ff3f0000
815 08:24:57.444457 starting USB...
816 08:24:57.695620 Bus usb@ff500000: Register 3000140 NbrPorts 3
817 08:24:57.696219 Starting the controller
818 08:24:57.702589 USB XHCI 1.10
819 08:24:59.864342 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
820 08:24:59.864994 bl2_stage_init 0x01
821 08:24:59.865455 bl2_stage_init 0x81
822 08:24:59.869997 hw id: 0x0000 - pwm id 0x01
823 08:24:59.870482 bl2_stage_init 0xc1
824 08:24:59.870930 bl2_stage_init 0x02
825 08:24:59.871370
826 08:24:59.875490 L0:00000000
827 08:24:59.875967 L1:20000703
828 08:24:59.876448 L2:00008067
829 08:24:59.876889 L3:14000000
830 08:24:59.881006 B2:00402000
831 08:24:59.881483 B1:e0f83180
832 08:24:59.881929
833 08:24:59.882367 TE: 58159
834 08:24:59.882812
835 08:24:59.886591 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
836 08:24:59.887063
837 08:24:59.887511 Board ID = 1
838 08:24:59.892291 Set A53 clk to 24M
839 08:24:59.892765 Set A73 clk to 24M
840 08:24:59.893205 Set clk81 to 24M
841 08:24:59.897825 A53 clk: 1200 MHz
842 08:24:59.898294 A73 clk: 1200 MHz
843 08:24:59.898737 CLK81: 166.6M
844 08:24:59.899175 smccc: 00012ab5
845 08:24:59.903493 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
846 08:24:59.908973 board id: 1
847 08:24:59.914928 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
848 08:24:59.925580 fw parse done
849 08:24:59.931693 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
850 08:24:59.974094 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
851 08:24:59.984977 PIEI prepare done
852 08:24:59.985450 fastboot data load
853 08:24:59.985894 fastboot data verify
854 08:24:59.990638 verify result: 266
855 08:24:59.996243 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
856 08:24:59.996718 LPDDR4 probe
857 08:24:59.997161 ddr clk to 1584MHz
858 08:25:00.004227 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
859 08:25:00.041515
860 08:25:00.042107 dmc_version 0001
861 08:25:00.048182 Check phy result
862 08:25:00.054020 INFO : End of CA training
863 08:25:00.054497 INFO : End of initialization
864 08:25:00.059618 INFO : Training has run successfully!
865 08:25:00.060124 Check phy result
866 08:25:00.065181 INFO : End of initialization
867 08:25:00.065645 INFO : End of read enable training
868 08:25:00.070898 INFO : End of fine write leveling
869 08:25:00.076440 INFO : End of Write leveling coarse delay
870 08:25:00.076919 INFO : Training has run successfully!
871 08:25:00.077368 Check phy result
872 08:25:00.082023 INFO : End of initialization
873 08:25:00.082488 INFO : End of read dq deskew training
874 08:25:00.087679 INFO : End of MPR read delay center optimization
875 08:25:00.093235 INFO : End of write delay center optimization
876 08:25:00.098863 INFO : End of read delay center optimization
877 08:25:00.099334 INFO : End of max read latency training
878 08:25:00.104417 INFO : Training has run successfully!
879 08:25:00.104890 1D training succeed
880 08:25:00.113682 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
881 08:25:00.161236 Check phy result
882 08:25:00.161710 INFO : End of initialization
883 08:25:00.183716 INFO : End of 2D read delay Voltage center optimization
884 08:25:00.203799 INFO : End of 2D read delay Voltage center optimization
885 08:25:00.255740 INFO : End of 2D write delay Voltage center optimization
886 08:25:00.304900 INFO : End of 2D write delay Voltage center optimization
887 08:25:00.310551 INFO : Training has run successfully!
888 08:25:00.311031
889 08:25:00.311477 channel==0
890 08:25:00.316089 RxClkDly_Margin_A0==78 ps 8
891 08:25:00.316581 TxDqDly_Margin_A0==98 ps 10
892 08:25:00.319484 RxClkDly_Margin_A1==88 ps 9
893 08:25:00.319951 TxDqDly_Margin_A1==98 ps 10
894 08:25:00.325070 TrainedVREFDQ_A0==74
895 08:25:00.325547 TrainedVREFDQ_A1==74
896 08:25:00.326016 VrefDac_Margin_A0==25
897 08:25:00.330680 DeviceVref_Margin_A0==40
898 08:25:00.331205 VrefDac_Margin_A1==24
899 08:25:00.336248 DeviceVref_Margin_A1==40
900 08:25:00.336797
901 08:25:00.337232
902 08:25:00.337661 channel==1
903 08:25:00.338081 RxClkDly_Margin_A0==98 ps 10
904 08:25:00.339799 TxDqDly_Margin_A0==88 ps 9
905 08:25:00.345440 RxClkDly_Margin_A1==88 ps 9
906 08:25:00.345942 TxDqDly_Margin_A1==88 ps 9
907 08:25:00.346375 TrainedVREFDQ_A0==76
908 08:25:00.350976 TrainedVREFDQ_A1==77
909 08:25:00.351449 VrefDac_Margin_A0==22
910 08:25:00.356416 DeviceVref_Margin_A0==38
911 08:25:00.356872 VrefDac_Margin_A1==24
912 08:25:00.357294 DeviceVref_Margin_A1==37
913 08:25:00.357720
914 08:25:00.362059 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
915 08:25:00.362515
916 08:25:00.395572 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000018 00000018 00000016 00000017 00000015 00000018 00000018 00000017 00000019 00000018 0000001a 0000001a 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
917 08:25:00.396117 2D training succeed
918 08:25:00.401135 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
919 08:25:00.406732 auto size-- 65535DDR cs0 size: 2048MB
920 08:25:00.407194 DDR cs1 size: 2048MB
921 08:25:00.412379 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
922 08:25:00.412843 cs0 DataBus test pass
923 08:25:00.413270 cs1 DataBus test pass
924 08:25:00.417929 cs0 AddrBus test pass
925 08:25:00.418383 cs1 AddrBus test pass
926 08:25:00.418807
927 08:25:00.423557 100bdlr_step_size ps== 432
928 08:25:00.424063 result report
929 08:25:00.424494 boot times 0Enable ddr reg access
930 08:25:00.433336 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
931 08:25:00.446721 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
932 08:25:01.018734 0.0;M3 CHK:0;cm4_sp_mode 0
933 08:25:01.019401 MVN_1=0x00000000
934 08:25:01.024213 MVN_2=0x00000000
935 08:25:01.029964 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
936 08:25:01.030442 OPS=0x10
937 08:25:01.030890 ring efuse init
938 08:25:01.031325 chipver efuse init
939 08:25:01.035596 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
940 08:25:01.041175 [0.018961 Inits done]
941 08:25:01.041655 secure task start!
942 08:25:01.042102 high task start!
943 08:25:01.045741 low task start!
944 08:25:01.046212 run into bl31
945 08:25:01.052399 NOTICE: BL31: v1.3(release):4fc40b1
946 08:25:01.060220 NOTICE: BL31: Built : 15:58:17, May 22 2019
947 08:25:01.060701 NOTICE: BL31: G12A normal boot!
948 08:25:01.085620 NOTICE: BL31: BL33 decompress pass
949 08:25:01.091205 ERROR: Error initializing runtime service opteed_fast
950 08:25:02.324204
951 08:25:02.324889
952 08:25:02.332453 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
953 08:25:02.332948
954 08:25:02.333400 Model: Libre Computer AML-A311D-CC Alta
955 08:25:02.541052 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
956 08:25:02.564296 DRAM: 2 GiB (effective 3.8 GiB)
957 08:25:02.707228 Core: 408 devices, 31 uclasses, devicetree: separate
958 08:25:02.713144 WDT: Not starting watchdog@f0d0
959 08:25:02.745397 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
960 08:25:02.757854 Loading Environment from FAT... Card did not respond to voltage select! : -110
961 08:25:02.762901 ** Bad device specification mmc 0 **
962 08:25:02.773197 Card did not respond to voltage select! : -110
963 08:25:02.780909 ** Bad device specification mmc 0 **
964 08:25:02.781393 Couldn't find partition mmc 0
965 08:25:02.789168 Card did not respond to voltage select! : -110
966 08:25:02.794844 ** Bad device specification mmc 0 **
967 08:25:02.795321 Couldn't find partition mmc 0
968 08:25:02.799743 Error: could not access storage.
969 08:25:03.142222 Net: eth0: ethernet@ff3f0000
970 08:25:03.142794 starting USB...
971 08:25:03.394165 Bus usb@ff500000: Register 3000140 NbrPorts 3
972 08:25:03.394732 Starting the controller
973 08:25:03.401022 USB XHCI 1.10
974 08:25:04.955375 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
975 08:25:04.963509 scanning usb for storage devices... 0 Storage Device(s) found
977 08:25:05.015101 Hit any key to stop autoboot: 1
978 08:25:05.015977 end: 2.4.2 bootloader-interrupt (duration 00:00:31) [common]
979 08:25:05.016642 start: 2.4.3 bootloader-commands (timeout 00:04:29) [common]
980 08:25:05.017169 Setting prompt string to ['=>']
981 08:25:05.017698 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:29)
982 08:25:05.031013 0
983 08:25:05.031937 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
984 08:25:05.032522 Sending with 10 millisecond of delay
986 08:25:06.167260 => setenv autoload no
987 08:25:06.178100 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:27)
988 08:25:06.183482 setenv autoload no
989 08:25:06.184275 Sending with 10 millisecond of delay
991 08:25:07.981009 => setenv initrd_high 0xffffffff
992 08:25:07.991865 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:26)
993 08:25:07.992796 setenv initrd_high 0xffffffff
994 08:25:07.993554 Sending with 10 millisecond of delay
996 08:25:09.609894 => setenv fdt_high 0xffffffff
997 08:25:09.620753 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:24)
998 08:25:09.621617 setenv fdt_high 0xffffffff
999 08:25:09.622371 Sending with 10 millisecond of delay
1001 08:25:09.914222 => dhcp
1002 08:25:09.924895 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:24)
1003 08:25:09.925705 dhcp
1004 08:25:09.926171 Speed: 1000, full duplex
1005 08:25:09.926618 BOOTP broadcast 1
1006 08:25:09.933947 DHCP client bound to address 192.168.6.27 (9 ms)
1007 08:25:09.934699 Sending with 10 millisecond of delay
1009 08:25:11.611211 => setenv serverip 192.168.6.2
1010 08:25:11.622052 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:22)
1011 08:25:11.622986 setenv serverip 192.168.6.2
1012 08:25:11.623722 Sending with 10 millisecond of delay
1014 08:25:15.347271 => tftpboot 0x01080000 978668/tftp-deploy-ojpnit67/kernel/uImage
1015 08:25:15.358163 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1016 08:25:15.359059 tftpboot 0x01080000 978668/tftp-deploy-ojpnit67/kernel/uImage
1017 08:25:15.359543 Speed: 1000, full duplex
1018 08:25:15.360029 Using ethernet@ff3f0000 device
1019 08:25:15.361023 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1020 08:25:15.366565 Filename '978668/tftp-deploy-ojpnit67/kernel/uImage'.
1021 08:25:15.370370 Load address: 0x1080000
1022 08:25:18.202199 Loading: *################################################## 44 MiB
1023 08:25:18.202872 15.5 MiB/s
1024 08:25:18.203346 done
1025 08:25:18.206356 Bytes transferred = 46121536 (2bfc240 hex)
1026 08:25:18.207186 Sending with 10 millisecond of delay
1028 08:25:22.893824 => tftpboot 0x08000000 978668/tftp-deploy-ojpnit67/ramdisk/ramdisk.cpio.gz.uboot
1029 08:25:22.904656 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:11)
1030 08:25:22.905540 tftpboot 0x08000000 978668/tftp-deploy-ojpnit67/ramdisk/ramdisk.cpio.gz.uboot
1031 08:25:22.906026 Speed: 1000, full duplex
1032 08:25:22.906485 Using ethernet@ff3f0000 device
1033 08:25:22.907513 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1034 08:25:22.919274 Filename '978668/tftp-deploy-ojpnit67/ramdisk/ramdisk.cpio.gz.uboot'.
1035 08:25:22.919769 Load address: 0x8000000
1036 08:25:29.863600 Loading: *########################T ########################## 22.5 MiB
1037 08:25:29.864320 3.2 MiB/s
1038 08:25:29.864802 done
1039 08:25:29.868073 Bytes transferred = 23562888 (1678a88 hex)
1040 08:25:29.868854 Sending with 10 millisecond of delay
1042 08:25:35.036926 => tftpboot 0x01070000 978668/tftp-deploy-ojpnit67/dtb/meson-g12b-a311d-libretech-cc.dtb
1043 08:25:35.047763 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:03:59)
1044 08:25:35.048655 tftpboot 0x01070000 978668/tftp-deploy-ojpnit67/dtb/meson-g12b-a311d-libretech-cc.dtb
1045 08:25:35.049163 Speed: 1000, full duplex
1046 08:25:35.049622 Using ethernet@ff3f0000 device
1047 08:25:35.052822 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1048 08:25:35.065538 Filename '978668/tftp-deploy-ojpnit67/dtb/meson-g12b-a311d-libretech-cc.dtb'.
1049 08:25:35.066065 Load address: 0x1070000
1050 08:25:35.081486 Loading: *################################################## 53.4 KiB
1051 08:25:35.082028 2.9 MiB/s
1052 08:25:35.082484 done
1053 08:25:35.087911 Bytes transferred = 54703 (d5af hex)
1054 08:25:35.088697 Sending with 10 millisecond of delay
1056 08:25:48.386998 => setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/978668/extract-nfsrootfs-iaw2q4k4,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
1057 08:25:48.397877 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:03:45)
1058 08:25:48.398829 setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/978668/extract-nfsrootfs-iaw2q4k4,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
1059 08:25:48.399589 Sending with 10 millisecond of delay
1061 08:25:50.738388 => bootm 0x01080000 0x08000000 0x01070000
1062 08:25:50.749260 Setting prompt string to ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1063 08:25:50.749822 bootloader-commands: Wait for prompt ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:03:43)
1064 08:25:50.750906 bootm 0x01080000 0x08000000 0x01070000
1065 08:25:50.751389 ## Booting kernel from Legacy Image at 01080000 ...
1066 08:25:50.754091 Image Name:
1067 08:25:50.759645 Image Type: AArch64 Linux Kernel Image (uncompressed)
1068 08:25:50.760169 Data Size: 46121472 Bytes = 44 MiB
1069 08:25:50.765083 Load Address: 01080000
1070 08:25:50.765560 Entry Point: 01080000
1071 08:25:50.961888 Verifying Checksum ... OK
1072 08:25:50.962396 ## Loading init Ramdisk from Legacy Image at 08000000 ...
1073 08:25:50.967390 Image Name:
1074 08:25:50.972800 Image Type: AArch64 Linux RAMDisk Image (uncompressed)
1075 08:25:50.973277 Data Size: 23562824 Bytes = 22.5 MiB
1076 08:25:50.975199 Load Address: 00000000
1077 08:25:50.982407 Entry Point: 00000000
1078 08:25:51.081128 Verifying Checksum ... OK
1079 08:25:51.081676 ## Flattened Device Tree blob at 01070000
1080 08:25:51.086651 Booting using the fdt blob at 0x1070000
1081 08:25:51.087125 Working FDT set to 1070000
1082 08:25:51.091095 Loading Kernel Image
1083 08:25:51.135929 Loading Ramdisk to 7e987000, end 7ffffa48 ... OK
1084 08:25:51.144332 Loading Device Tree to 000000007e976000, end 000000007e9865ae ... OK
1085 08:25:51.144812 Working FDT set to 7e976000
1086 08:25:51.145269
1087 08:25:51.146206 end: 2.4.3 bootloader-commands (duration 00:00:46) [common]
1088 08:25:51.146834 start: 2.4.4 auto-login-action (timeout 00:03:43) [common]
1089 08:25:51.147345 Setting prompt string to ['Linux version [0-9]']
1090 08:25:51.147846 Setting prompt string to ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1091 08:25:51.148403 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:05:00)
1092 08:25:51.149478 Starting kernel ...
1093 08:25:51.149967
1094 08:25:51.185076 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x410fd034]
1095 08:25:51.186004 start: 2.4.4.1 login-action (timeout 00:03:42) [common]
1096 08:25:51.186571 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
1097 08:25:51.187068 Setting prompt string to []
1098 08:25:51.187590 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
1099 08:25:51.188126 Using line separator: #'\n'#
1100 08:25:51.188582 No login prompt set.
1101 08:25:51.189054 Parsing kernel messages
1102 08:25:51.189490 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
1103 08:25:51.190346 [login-action] Waiting for messages, (timeout 00:03:42)
1104 08:25:51.190839 Waiting using forced prompt support (timeout 00:01:51)
1105 08:25:51.201670 [ 0.000000] Linux version 6.12.0-rc7-next-20241112 (KernelCI@build-j373747-arm64-gcc-12-defconfig-xvdlw) (aarch64-linux-gnu-gcc (Debian 12.2.0-14) 12.2.0, GNU ld (GNU Binutils for Debian) 2.40) #1 SMP PREEMPT Tue Nov 12 07:32:50 UTC 2024
1106 08:25:51.207138 [ 0.000000] KASLR disabled due to lack of seed
1107 08:25:51.212689 [ 0.000000] Machine model: Libre Computer AML-A311D-CC Alta
1108 08:25:51.218221 [ 0.000000] efi: UEFI not found.
1109 08:25:51.223697 [ 0.000000] [Firmware Bug]: Kernel image misaligned at boot, please fix your bootloader!
1110 08:25:51.234774 [ 0.000000] Reserved memory: created CMA memory pool at 0x00000000e4c00000, size 256 MiB
1111 08:25:51.240326 [ 0.000000] OF: reserved mem: initialized node linux,cma, compatible id shared-dma-pool
1112 08:25:51.251366 [ 0.000000] OF: reserved mem: 0x00000000e4c00000..0x00000000f4bfffff (262144 KiB) map reusable linux,cma
1113 08:25:51.256828 [ 0.000000] earlycon: meson0 at MMIO 0x00000000ff803000 (options '115200n8')
1114 08:25:51.262379 [ 0.000000] printk: legacy bootconsole [meson0] enabled
1115 08:25:51.273348 [ 0.000000] OF: reserved mem: 0x0000000005000000..0x00000000052fffff (3072 KiB) nomap non-reusable secmon@5000000
1116 08:25:51.284401 [ 0.000000] OF: reserved mem: 0x0000000005300000..0x00000000072fffff (32768 KiB) nomap non-reusable secmon@5300000
1117 08:25:51.289831 [ 0.000000] NUMA: Faking a node at [mem 0x0000000000000000-0x00000000f4e5afff]
1118 08:25:51.295408 [ 0.000000] NODE_DATA(0) allocated [mem 0xe465d380-0xe465f9bf]
1119 08:25:51.300939 [ 0.000000] Zone ranges:
1120 08:25:51.306429 [ 0.000000] DMA [mem 0x0000000000000000-0x00000000f4e5afff]
1121 08:25:51.306933 [ 0.000000] DMA32 empty
1122 08:25:51.311918 [ 0.000000] Normal empty
1123 08:25:51.312438 [ 0.000000] Movable zone start for each node
1124 08:25:51.317445 [ 0.000000] Early memory node ranges
1125 08:25:51.322948 [ 0.000000] node 0: [mem 0x0000000000000000-0x0000000004ffffff]
1126 08:25:51.328444 [ 0.000000] node 0: [mem 0x0000000005000000-0x00000000072fffff]
1127 08:25:51.334015 [ 0.000000] node 0: [mem 0x0000000007300000-0x00000000f4e5afff]
1128 08:25:51.343864 [ 0.000000] Initmem setup node 0 [mem 0x0000000000000000-0x00000000f4e5afff]
1129 08:25:51.368243 [ 0.000000] On node 0, zone DMA: 12709 pages in unavailable ranges
1130 08:25:51.373611 [ 0.000000] psci: probing for conduit method from DT.
1131 08:25:51.374108 [ 0.000000] psci: PSCIv1.0 detected in firmware.
1132 08:25:51.382588 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
1133 08:25:51.383080 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
1134 08:25:51.388099 [ 0.000000] psci: SMC Calling Convention v1.1
1135 08:25:51.397226 [ 0.000000] RME: RMM doesn't support RSI version 1.0. Supported range: 1.0-0.0
1136 08:25:51.402709 [ 0.000000] percpu: Embedded 25 pages/cpu s61464 r8192 d32744 u102400
1137 08:25:51.408312 [ 0.000000] Detected VIPT I-cache on CPU0
1138 08:25:51.413808 [ 0.000000] CPU features: detected: ARM erratum 845719
1139 08:25:51.419444 [ 0.000000] alternatives: applying boot alternatives
1140 08:25:51.435945 [ 0.000000] Kernel command line: console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/978668/extract-nfsrootfs-iaw2q4k4,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp
1141 08:25:51.446950 <6>[ 0.000000] printk: log buffer data + meta data: 131072 + 458752 = 589824 bytes
1142 08:25:51.452499 <6>[ 0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
1143 08:25:51.463523 <6>[ 0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes, linear)
1144 08:25:51.464053 <6>[ 0.000000] Fallback order for Node 0: 0
1145 08:25:51.474528 <6>[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 1003099
1146 08:25:51.475011 <6>[ 0.000000] Policy zone: DMA
1147 08:25:51.485572 <6>[ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
1148 08:25:51.491140 <6>[ 0.000000] software IO TLB: SWIOTLB bounce buffer size adjusted to 3MB
1149 08:25:51.491680 <6>[ 0.000000] software IO TLB: area num 8.
1150 08:25:51.502207 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000dfc00000-0x00000000e0000000] (4MB)
1151 08:25:51.548869 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=6, Nodes=1
1152 08:25:51.554435 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
1153 08:25:51.559901 <6>[ 0.000000] rcu: RCU event tracing is enabled.
1154 08:25:51.565471 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=512 to nr_cpu_ids=6.
1155 08:25:51.570936 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
1156 08:25:51.576459 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
1157 08:25:51.581978 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
1158 08:25:51.587525 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=6
1159 08:25:51.598545 <6>[ 0.000000] RCU Tasks: Setting shift to 3 and lim to 1 rcu_task_cb_adjust=1 rcu_task_cpu_ids=6.
1160 08:25:51.609597 <6>[ 0.000000] RCU Tasks Trace: Setting shift to 3 and lim to 1 rcu_task_cb_adjust=1 rcu_task_cpu_ids=6.
1161 08:25:51.615084 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
1162 08:25:51.620625 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
1163 08:25:51.621104 <6>[ 0.000000] GIC: Using split EOI/Deactivate mode
1164 08:25:51.630552 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
1165 08:25:51.643346 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 24.00MHz (phys).
1166 08:25:51.652479 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x588fe9dc0, max_idle_ns: 440795202592 ns
1167 08:25:51.657988 <6>[ 0.000000] sched_clock: 56 bits at 24MHz, resolution 41ns, wraps every 4398046511097ns
1168 08:25:51.663503 <6>[ 0.008795] Console: colour dummy device 80x25
1169 08:25:51.678066 <6>[ 0.012943] Calibrating delay loop (skipped), value calculated using timer frequency.. 48.00 BogoMIPS (lpj=96000)
1170 08:25:51.678558 <6>[ 0.023295] pid_max: default: 32768 minimum: 301
1171 08:25:51.683599 <6>[ 0.028190] LSM: initializing lsm=capability
1172 08:25:51.692667 <6>[ 0.032732] Mount-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
1173 08:25:51.698165 <6>[ 0.040211] Mountpoint-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
1174 08:25:51.703682 <6>[ 0.050783] rcu: Hierarchical SRCU implementation.
1175 08:25:51.709206 <6>[ 0.053262] rcu: Max phase no-delay instances is 1000.
1176 08:25:51.720254 <6>[ 0.058869] Timer migration: 1 hierarchy levels; 8 children per group; 1 crossnode level
1177 08:25:51.725776 <6>[ 0.071649] EFI services will not be available.
1178 08:25:51.731291 <6>[ 0.072106] smp: Bringing up secondary CPUs ...
1179 08:25:51.731761 <6>[ 0.077156] Detected VIPT I-cache on CPU1
1180 08:25:51.742365 <6>[ 0.077275] CPU1: Booted secondary processor 0x0000000001 [0x410fd034]
1181 08:25:51.742843 <6>[ 0.078618] CPU features: detected: Spectre-v2
1182 08:25:51.747858 <6>[ 0.078633] CPU features: detected: Spectre-v4
1183 08:25:51.753364 <6>[ 0.078638] CPU features: detected: Spectre-BHB
1184 08:25:51.758884 <6>[ 0.078643] CPU features: detected: ARM erratum 858921
1185 08:25:51.764498 <6>[ 0.078651] Detected VIPT I-cache on CPU2
1186 08:25:51.769902 <6>[ 0.078723] arch_timer: Enabling local workaround for ARM erratum 858921
1187 08:25:51.775469 <6>[ 0.078740] arch_timer: CPU2: Trapping CNTVCT access
1188 08:25:51.780965 <6>[ 0.078750] CPU2: Booted secondary processor 0x0000000100 [0x410fd092]
1189 08:25:51.786496 <6>[ 0.079506] Detected VIPT I-cache on CPU3
1190 08:25:51.792061 <6>[ 0.079551] arch_timer: Enabling local workaround for ARM erratum 858921
1191 08:25:51.797554 <6>[ 0.079561] arch_timer: CPU3: Trapping CNTVCT access
1192 08:25:51.803047 <6>[ 0.079568] CPU3: Booted secondary processor 0x0000000101 [0x410fd092]
1193 08:25:51.808518 <6>[ 0.080280] Detected VIPT I-cache on CPU4
1194 08:25:51.814067 <6>[ 0.080326] arch_timer: Enabling local workaround for ARM erratum 858921
1195 08:25:51.819602 <6>[ 0.080335] arch_timer: CPU4: Trapping CNTVCT access
1196 08:25:51.830655 <6>[ 0.080342] CPU4: Booted secondary processor 0x0000000102 [0x410fd092]
1197 08:25:51.831164 <6>[ 0.081117] Detected VIPT I-cache on CPU5
1198 08:25:51.841696 <6>[ 0.081164] arch_timer: Enabling local workaround for ARM erratum 858921
1199 08:25:51.842176 <6>[ 0.081174] arch_timer: CPU5: Trapping CNTVCT access
1200 08:25:51.852728 <6>[ 0.081181] CPU5: Booted secondary processor 0x0000000103 [0x410fd092]
1201 08:25:51.853208 <6>[ 0.081304] smp: Brought up 1 node, 6 CPUs
1202 08:25:51.858240 <6>[ 0.203227] SMP: Total of 6 processors activated.
1203 08:25:51.863742 <6>[ 0.208131] CPU: All CPU(s) started at EL2
1204 08:25:51.869293 <6>[ 0.212474] CPU features: detected: 32-bit EL0 Support
1205 08:25:51.874800 <6>[ 0.217788] CPU features: detected: 32-bit EL1 Support
1206 08:25:51.880386 <6>[ 0.223149] CPU features: detected: CRC32 instructions
1207 08:25:51.885843 <6>[ 0.228545] alternatives: applying system-wide alternatives
1208 08:25:51.903879 <6>[ 0.235942] Memory: 3556796K/4012396K available (17408K kernel code, 4912K rwdata, 12000K rodata, 10560K init, 744K bss, 188340K reserved, 262144K cma-reserved)
1209 08:25:51.904390 <6>[ 0.250096] devtmpfs: initialized
1210 08:25:51.914945 <6>[ 0.259350] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
1211 08:25:51.920516 <6>[ 0.263711] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
1212 08:25:51.925981 <6>[ 0.274513] 21296 pages in range for non-PLT usage
1213 08:25:51.931527 <6>[ 0.274523] 512816 pages in range for PLT usage
1214 08:25:51.936998 <6>[ 0.276073] pinctrl core: initialized pinctrl subsystem
1215 08:25:51.942565 <6>[ 0.288145] DMI not present or invalid.
1216 08:25:51.948088 <6>[ 0.292386] NET: Registered PF_NETLINK/PF_ROUTE protocol family
1217 08:25:51.953574 <6>[ 0.297228] DMA: preallocated 512 KiB GFP_KERNEL pool for atomic allocations
1218 08:25:51.964614 <6>[ 0.304054] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
1219 08:25:51.970146 <6>[ 0.312185] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
1220 08:25:51.975666 <6>[ 0.319526] audit: initializing netlink subsys (disabled)
1221 08:25:51.986655 <5>[ 0.325321] audit: type=2000 audit(0.244:1): state=initialized audit_enabled=0 res=1
1222 08:25:51.992201 <6>[ 0.326810] thermal_sys: Registered thermal governor 'step_wise'
1223 08:25:51.997725 <6>[ 0.333052] thermal_sys: Registered thermal governor 'power_allocator'
1224 08:25:52.003295 <6>[ 0.339308] cpuidle: using governor menu
1225 08:25:52.008790 <6>[ 0.350286] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
1226 08:25:52.014308 <6>[ 0.357228] ASID allocator initialised with 65536 entries
1227 08:25:52.021280 <6>[ 0.364767] Serial: AMBA PL011 UART driver
1228 08:25:52.026781 <6>[ 0.374046] /soc/bus@ff600000/hdmi-tx@0: Fixed dependency cycle(s) with /soc/vpu@ff900000
1229 08:25:52.037825 <6>[ 0.377226] /soc/vpu@ff900000: Fixed dependency cycle(s) with /soc/bus@ff600000/hdmi-tx@0
1230 08:25:52.048873 <6>[ 0.385212] /soc/interrupt-controller@ffc01000: Fixed dependency cycle(s) with /soc/interrupt-controller@ffc01000
1231 08:25:52.054411 <6>[ 0.396437] /soc/bus@ff600000/hdmi-tx@0: Fixed dependency cycle(s) with /soc/vpu@ff900000
1232 08:25:52.064972 <6>[ 0.404539] /soc/bus@ff600000/hdmi-tx@0: Fixed dependency cycle(s) with /soc/vpu@ff900000
1233 08:25:52.080540 <6>[ 0.425555] /soc/bus@ff600000/hdmi-tx@0: Fixed dependency cycle(s) with /soc/vpu@ff900000
1234 08:25:52.091572 <6>[ 0.428382] /soc/vpu@ff900000: Fixed dependency cycle(s) with /soc/bus@ff600000/hdmi-tx@0
1235 08:25:52.097113 <6>[ 0.441264] /soc/vpu@ff900000: Fixed dependency cycle(s) with /cvbs-connector
1236 08:25:52.102619 <6>[ 0.444080] /cvbs-connector: Fixed dependency cycle(s) with /soc/vpu@ff900000
1237 08:25:52.113682 <6>[ 0.451817] /soc/bus@ff600000/hdmi-tx@0: Fixed dependency cycle(s) with /hdmi-connector
1238 08:25:52.119188 <6>[ 0.459615] /hdmi-connector: Fixed dependency cycle(s) with /soc/bus@ff600000/hdmi-tx@0
1239 08:25:52.124701 <6>[ 0.472590] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
1240 08:25:52.135733 <6>[ 0.474743] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
1241 08:25:52.141264 <6>[ 0.481224] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
1242 08:25:52.146768 <6>[ 0.488201] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
1243 08:25:52.152294 <6>[ 0.494671] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
1244 08:25:52.157823 <6>[ 0.501655] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
1245 08:25:52.168855 <6>[ 0.508125] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
1246 08:25:52.174422 <6>[ 0.515110] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
1247 08:25:52.179886 <6>[ 0.523153] ACPI: Interpreter disabled.
1248 08:25:52.185425 <6>[ 0.528538] iommu: Default domain type: Translated
1249 08:25:52.190941 <6>[ 0.530643] iommu: DMA domain TLB invalidation policy: strict mode
1250 08:25:52.191414 <5>[ 0.537352] SCSI subsystem initialized
1251 08:25:52.196555 <6>[ 0.541209] usbcore: registered new interface driver usbfs
1252 08:25:52.201986 <6>[ 0.546701] usbcore: registered new interface driver hub
1253 08:25:52.207556 <6>[ 0.552221] usbcore: registered new device driver usb
1254 08:25:52.212988 <6>[ 0.558498] pps_core: LinuxPPS API ver. 1 registered
1255 08:25:52.224065 <6>[ 0.562637] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
1256 08:25:52.229618 <6>[ 0.571958] PTP clock support registered
1257 08:25:52.230092 <6>[ 0.576195] EDAC MC: Ver: 3.0.0
1258 08:25:52.235106 <6>[ 0.579836] scmi_core: SCMI protocol bus registered
1259 08:25:52.240610 <6>[ 0.585507] FPGA manager framework
1260 08:25:52.246139 <6>[ 0.588217] Advanced Linux Sound Architecture Driver Initialized.
1261 08:25:52.251655 <6>[ 0.595171] vgaarb: loaded
1262 08:25:52.257181 <6>[ 0.597768] clocksource: Switched to clocksource arch_sys_counter
1263 08:25:52.262698 <5>[ 0.603879] VFS: Disk quotas dquot_6.6.0
1264 08:25:52.268235 <6>[ 0.607851] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
1265 08:25:52.268709 <6>[ 0.615063] pnp: PnP ACPI: disabled
1266 08:25:52.273703 <6>[ 0.623711] NET: Registered PF_INET protocol family
1267 08:25:52.284760 <6>[ 0.623929] IP idents hash table entries: 65536 (order: 7, 524288 bytes, linear)
1268 08:25:52.290271 <6>[ 0.634052] tcp_listen_portaddr_hash hash table entries: 2048 (order: 3, 32768 bytes, linear)
1269 08:25:52.301337 <6>[ 0.640053] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
1270 08:25:52.306886 <6>[ 0.647950] TCP established hash table entries: 32768 (order: 6, 262144 bytes, linear)
1271 08:25:52.317862 <6>[ 0.656187] TCP bind hash table entries: 32768 (order: 8, 1048576 bytes, linear)
1272 08:25:52.323403 <6>[ 0.663979] TCP: Hash tables configured (established 32768 bind 32768)
1273 08:25:52.328888 <6>[ 0.670465] UDP hash table entries: 2048 (order: 4, 65536 bytes, linear)
1274 08:25:52.334543 <6>[ 0.677305] UDP-Lite hash table entries: 2048 (order: 4, 65536 bytes, linear)
1275 08:25:52.340421 <6>[ 0.684731] NET: Registered PF_UNIX/PF_LOCAL protocol family
1276 08:25:52.351021 <6>[ 0.690797] RPC: Registered named UNIX socket transport module.
1277 08:25:52.351543 <6>[ 0.696594] RPC: Registered udp transport module.
1278 08:25:52.356562 <6>[ 0.701500] RPC: Registered tcp transport module.
1279 08:25:52.362054 <6>[ 0.706414] RPC: Registered tcp-with-tls transport module.
1280 08:25:52.373095 <6>[ 0.712108] RPC: Registered tcp NFSv4.1 backchannel transport module.
1281 08:25:52.373603 <6>[ 0.718755] PCI: CLS 0 bytes, default 64
1282 08:25:52.378868 <6>[ 0.723082] Unpacking initramfs...
1283 08:25:52.384454 <6>[ 0.732456] kvm [1]: nv: 557 coarse grained trap handlers
1284 08:25:52.389907 <6>[ 0.732761] kvm [1]: IPA Size Limit: 40 bits
1285 08:25:52.395482 <6>[ 0.738437] kvm [1]: vgic interrupt IRQ9
1286 08:25:52.400984 <6>[ 0.741137] kvm [1]: Hyp nVHE mode initialized successfully
1287 08:25:52.401477 <5>[ 0.748214] Initialise system trusted keyrings
1288 08:25:52.412106 <6>[ 0.751748] workingset: timestamp_bits=42 max_order=20 bucket_order=0
1289 08:25:52.417595 <6>[ 0.758422] squashfs: version 4.0 (2009/01/31) Phillip Lougher
1290 08:25:52.423127 <5>[ 0.764422] NFS: Registering the id_resolver key type
1291 08:25:52.428668 <5>[ 0.769523] Key type id_resolver registered
1292 08:25:52.429148 <5>[ 0.773891] Key type id_legacy registered
1293 08:25:52.439710 <6>[ 0.778128] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
1294 08:25:52.445224 <6>[ 0.785016] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
1295 08:25:52.450900 <6>[ 0.792799] 9p: Installing v9fs 9p2000 file system support
1296 08:25:52.487321 <5>[ 0.837847] Key type asymmetric registered
1297 08:25:52.492856 <5>[ 0.837892] Asymmetric key parser 'x509' registered
1298 08:25:52.503867 <6>[ 0.841744] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 245)
1299 08:25:52.504399 <6>[ 0.849280] io scheduler mq-deadline registered
1300 08:25:52.509387 <6>[ 0.854009] io scheduler kyber registered
1301 08:25:52.514876 <6>[ 0.858276] io scheduler bfq registered
1302 08:25:52.521359 <6>[ 0.867609] irq_meson_gpio: 100 to 8 gpio interrupt mux initialized
1303 08:25:52.537847 <6>[ 0.884636] ledtrig-cpu: registered to indicate activity on CPUs
1304 08:25:52.570454 <6>[ 0.916033] soc soc0: Amlogic Meson G12B (A311D) Revision 29:b (10:2) Detected
1305 08:25:52.589757 <6>[ 0.929118] Serial: 8250/16550 driver, 4 ports,<6>[ 0.933791] ff803000.serial: ttyAML0 at MMIO 0xff803000 (irq = 14, base_baud = 1500000) is a meson_uart
1306 08:25:52.595323 <6>[ 0.943418] printk: legacy console [ttyAML0] enabled
1307 08:25:52.600865 <6>[ 0.943418] printk: legacy console [ttyAML0] enabled
1308 08:25:52.606473 <6>[ 0.948214] printk: legacy bootconsole [meson0] disabled
1309 08:25:52.611969 <6>[ 0.948214] printk: legacy bootconsole [meson0] disabled
1310 08:25:52.617604 <6>[ 0.962527] msm_serial: driver initialized
1311 08:25:52.623060 <6>[ 0.964161] SuperH (H)SCI(F) driver initialized
1312 08:25:52.623542 <6>[ 0.968681] STM32 USART driver initialized
1313 08:25:52.628601 <5>[ 0.975069] random: crng init done
1314 08:25:52.635790 <6>[ 0.980663] loop: module loaded
1315 08:25:52.636300 <6>[ 0.981975] megasas: 07.727.03.00-rc1
1316 08:25:52.641355 <6>[ 0.990904] tun: Universal TUN/TAP device driver, 1.6
1317 08:25:52.646879 <6>[ 0.992099] thunder_xcv, ver 1.0
1318 08:25:52.652481 <6>[ 0.994094] thunder_bgx, ver 1.0
1319 08:25:52.652955 <6>[ 0.997529] nicpf, ver 1.0
1320 08:25:52.657965 <6>[ 1.002147] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
1321 08:25:52.663610 <6>[ 1.007924] hns3: Copyright (c) 2017 Huawei Corporation.
1322 08:25:52.669071 <6>[ 1.013512] hclge is initializing
1323 08:25:52.674596 <6>[ 1.017055] e1000: Intel(R) PRO/1000 Network Driver
1324 08:25:52.680206 <6>[ 1.022132] e1000: Copyright (c) 1999-2006 Intel Corporation.
1325 08:25:52.685705 <6>[ 1.028150] e1000e: Intel(R) PRO/1000 Network Driver
1326 08:25:52.691263 <6>[ 1.033313] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
1327 08:25:52.696804 <6>[ 1.039492] igb: Intel(R) Gigabit Ethernet Network Driver
1328 08:25:52.702338 <6>[ 1.045098] igb: Copyright (c) 2007-2014 Intel Corporation.
1329 08:25:52.707872 <6>[ 1.050944] igbvf: Intel(R) Gigabit Virtual Function Network Driver
1330 08:25:52.713485 <6>[ 1.057406] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
1331 08:25:52.718976 <6>[ 1.064172] sky2: driver version 1.30
1332 08:25:52.724617 <6>[ 1.069256] VFIO - User Level meta-driver version: 0.3
1333 08:25:52.730079 <6>[ 1.076839] usbcore: registered new interface driver usb-storage
1334 08:25:52.736224 <6>[ 1.082831] i2c_dev: i2c /dev entries driver
1335 08:25:52.749107 <6>[ 1.094078] sdhci: Secure Digital Host Controller Interface driver
1336 08:25:52.749580 <6>[ 1.094882] sdhci: Copyright(c) Pierre Ossman
1337 08:25:52.760210 <6>[ 1.100626] Synopsys Designware Multimedia Card Interface Driver
1338 08:25:52.765754 <6>[ 1.107185] sdhci-pltfm: SDHCI platform and OF driver helper
1339 08:25:52.766225 <6>[ 1.114816] meson-sm: secure-monitor enabled
1340 08:25:52.778690 <6>[ 1.117274] usbcore: registered new interface driver usbhid
1341 08:25:52.779159 <6>[ 1.121937] usbhid: USB HID core driver
1342 08:25:52.786289 <6>[ 1.136795] NET: Registered PF_PACKET protocol family
1343 08:25:52.791817 <6>[ 1.136882] 9pnet: Installing 9P2000 support
1344 08:25:52.798786 <5>[ 1.141048] Key type dns_resolver registered
1345 08:25:52.804307 <6>[ 1.152524] registered taskstats version 1
1346 08:25:52.809883 <5>[ 1.152689] Loading compiled-in X.509 certificates
1347 08:25:52.813469 <6>[ 1.161485] Demotion targets for Node 0: null
1348 08:25:52.839956 <6>[ 1.190467] dwc3-meson-g12a ffe09000.usb: USB2 ports: 2
1349 08:25:52.845510 <6>[ 1.190505] dwc3-meson-g12a ffe09000.usb: USB3 ports: 1
1350 08:25:52.854518 <4>[ 1.199710] dwc2 ff400000.usb: supply vusb_d not found, using dummy regulator
1351 08:25:52.860074 <4>[ 1.203261] dwc2 ff400000.usb: supply vusb_a not found, using dummy regulator
1352 08:25:52.871148 <6>[ 1.210772] dwc2 ff400000.usb: EPs: 7, dedicated fifos, 712 entries in SPRAM
1353 08:25:52.876693 <6>[ 1.220145] xhci-hcd xhci-hcd.0.auto: xHCI Host Controller
1354 08:25:52.882209 <6>[ 1.223547] xhci-hcd xhci-hcd.0.auto: new USB bus registered, assigned bus number 1
1355 08:25:52.893335 <6>[ 1.231533] xhci-hcd xhci-hcd.0.auto: hcc params 0x0228fe6c hci version 0x110 quirks 0x0000808000000010
1356 08:25:52.898869 <6>[ 1.241066] xhci-hcd xhci-hcd.0.auto: irq 16, io mem 0xff500000
1357 08:25:52.904429 <6>[ 1.247299] xhci-hcd xhci-hcd.0.auto: xHCI Host Controller
1358 08:25:52.915493 <6>[ 1.252913] xhci-hcd xhci-hcd.0.auto: new USB bus registered, assigned bus number 2
1359 08:25:52.921064 <6>[ 1.260801] xhci-hcd xhci-hcd.0.auto: Host supports USB 3.0 SuperSpeed
1360 08:25:52.921542 <6>[ 1.268050] hub 1-0:1.0: USB hub found
1361 08:25:52.926646 <6>[ 1.271579] hub 1-0:1.0: 2 ports detected
1362 08:25:52.937706 <6>[ 1.277642] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
1363 08:25:52.938189 <6>[ 1.284551] hub 2-0:1.0: USB hub found
1364 08:25:52.944866 <6>[ 1.288112] hub 2-0:1.0: 1 port detected
1365 08:25:52.971318 <6>[ 1.319278] meson-gx-mmc ffe05000.mmc: Got CD GPIO
1366 08:25:52.982370 <6>[ 1.329552] meson-gx-mmc ffe07000.mmc: allocated mmc-pwrseq
1367 08:25:53.017872 <6>[ 1.364687] Trying to probe devices needed for running init ...
1368 08:25:53.183633 <6>[ 1.529805] usb 1-1: new high-speed USB device number 2 using xhci-hcd
1369 08:25:53.332114 <6>[ 1.677088] mmc0: new UHS-I speed SDR104 SDXC card at address e624
1370 08:25:53.332724 <6>[ 1.678452] mmcblk0: mmc0:e624 SD64G 59.5 GiB
1371 08:25:53.337882 <6>[ 1.684259] mmcblk0: p1
1372 08:25:53.348878 <6>[ 1.697466] Freeing initrd memory: 23008K
1373 08:25:53.365392 <6>[ 1.715905] hub 1-1:1.0: USB hub found
1374 08:25:53.371113 <6>[ 1.716210] hub 1-1:1.0: 4 ports detected
1375 08:25:53.439807 <6>[ 1.785907] usb 2-1: new SuperSpeed USB device number 2 using xhci-hcd
1376 08:25:53.478078 <6>[ 1.828555] hub 2-1:1.0: USB hub found
1377 08:25:53.483798 <6>[ 1.829385] hub 2-1:1.0: 4 ports detected
1378 08:26:05.299818 <6>[ 13.649844] clk: Disabling unused clocks
1379 08:26:05.305042 <6>[ 13.650012] PM: genpd: Disabling unused power domains
1380 08:26:05.313243 <6>[ 13.653703] ALSA device list:
1381 08:26:05.313792 <6>[ 13.656907] No soundcards found.
1382 08:26:05.318792 <6>[ 13.668833] Freeing unused kernel memory: 10560K
1383 08:26:05.324730 <6>[ 13.668936] Run /init as init process
1384 08:26:05.331207 Loading, please wait...
1385 08:26:05.369311 Starting systemd-udevd version 252.22-1~deb12u1
1386 08:26:05.790882 <6>[ 14.139881] mc: Linux media interface: v0.10
1387 08:26:05.815127 <6>[ 14.158504] videodev: Linux video capture interface: v2.00
1388 08:26:05.820560 <6>[ 14.165680] meson8b-dwmac ff3f0000.ethernet: IRQ eth_wake_irq not found
1389 08:26:05.826218 <6>[ 14.166981] meson8b-dwmac ff3f0000.ethernet: IRQ eth_lpi not found
1390 08:26:05.831671 <6>[ 14.173380] meson8b-dwmac ff3f0000.ethernet: IRQ sfty not found
1391 08:26:05.837271 <6>[ 14.179617] meson8b-dwmac ff3f0000.ethernet: PTP uses main clock
1392 08:26:05.842841 <6>[ 14.186597] meson8b-dwmac ff3f0000.ethernet: User ID: 0x11, Synopsys ID: 0x37
1393 08:26:05.848365 <6>[ 14.193178] meson8b-dwmac ff3f0000.ethernet: DWMAC1000
1394 08:26:05.859580 <6>[ 14.198571] meson8b-dwmac ff3f0000.ethernet: DMA HW capability register supported
1395 08:26:05.865039 <6>[ 14.206276] meson8b-dwmac ff3f0000.ethernet: RX Checksum Offload Engine supported
1396 08:26:05.870533 <6>[ 14.214018] meson8b-dwmac ff3f0000.ethernet: COE Type 2
1397 08:26:05.881599 <6>[ 14.219455] meson8b-dwmac ff3f0000.ethernet: TX Checksum insertion supported
1398 08:26:05.887136 <6>[ 14.226728] meson8b-dwmac ff3f0000.ethernet: Wake-Up On Lan supported
1399 08:26:05.892755 <6>[ 14.233673] meson8b-dwmac ff3f0000.ethernet: Normal descriptors
1400 08:26:05.898324 <6>[ 14.239603] meson8b-dwmac ff3f0000.ethernet: Ring mode enabled
1401 08:26:05.903841 <6>[ 14.245644] meson8b-dwmac ff3f0000.ethernet: Enable RX Mitigation via HW Watchdog Timer
1402 08:26:05.914811 <4>[ 14.247046] meson-pwm ff802000.pwm: using obsolete compatible, please consider updating dt
1403 08:26:05.920430 <6>[ 14.266125] Registered IR keymap rc-empty
1404 08:26:05.925895 <6>[ 14.268979] meson-vrtc ff8000a8.rtc: registered as rtc0
1405 08:26:05.931458 <6>[ 14.270280] rc rc0: meson-ir as /devices/platform/soc/ff800000.bus/ff808000.ir/rc/rc0
1406 08:26:05.942535 <6>[ 14.272256] meson-vrtc ff8000a8.rtc: setting system clock to 1970-01-01T00:00:14 UTC (14)
1407 08:26:05.948103 <6>[ 14.290731] panfrost ffe40000.gpu: clock rate = 24000000
1408 08:26:05.953629 <3>[ 14.291064] debugfs: Directory 'ff800280.cec' with parent 'regmap' already present!
1409 08:26:05.964724 <3>[ 14.294247] panfrost ffe40000.gpu: error -ENODEV: _opp_set_regulators: no regulator (mali) found
1410 08:26:05.970305 <6>[ 14.311704] meson-drm ff900000.vpu: Queued 2 outputs on vpu
1411 08:26:05.975821 <6>[ 14.312796] input: meson-ir as /devices/platform/soc/ff800000.bus/ff808000.ir/rc/rc0/input0
1412 08:26:05.986899 <6>[ 14.319607] panfrost ffe40000.gpu: mali-g52 id 0x7212 major 0x0 minor 0x0 status 0x0
1413 08:26:05.992482 <6>[ 14.333382] panfrost ffe40000.gpu: features: 00000000,00000cf7, issues: 00000000,00000400
1414 08:26:05.998009 <6>[ 14.333639] rc rc0: sw decoder init
1415 08:26:06.009103 <4>[ 14.333849] meson_vdec: module is from the staging directory, the quality is unknown, you have been warned.
1416 08:26:06.020222 <6>[ 14.341756] panfrost ffe40000.gpu: Features: L2:0x07110206 Shader:0x00000000 Tiler:0x00000809 Mem:0x1 MMU:0x00002830 AS:0xff JS:0x7
1417 08:26:06.025742 <6>[ 14.341779] panfrost ffe40000.gpu: shader_present=0x3 l2_present=0x1
1418 08:26:06.031315 <6>[ 14.374184] meson-ir ff808000.ir: receiver initialized
1419 08:26:06.038806 <6>[ 14.377671] [drm] Initialized panfrost 1.3.0 for ffe40000.gpu on minor 0
1420 08:26:06.050970 <6>[ 14.393923] meson-dw-hdmi ff600000.hdmi-tx: Detected HDMI TX controller v2.01a with HDCP (meson_dw_hdmi_phy)
1421 08:26:06.078946 <6>[ 14.423893] meson-dw-hdmi ff600000.hdmi-tx: registered DesignWare HDMI I2C bus driver
1422 08:26:06.098722 <6>[ 14.443734] meson8b-dwmac ff3f0000.ethernet end0: renamed from eth0
1423 08:26:06.104333 <6>[ 14.445385] meson-drm ff900000.vpu: bound ff600000.hdmi-tx (ops meson_dw_hdmi_ops [meson_dw_hdmi])
1424 08:26:06.115478 <3>[ 14.453933] meson-drm ff900000.vpu: DSI transceiver device is disabled
1425 08:26:06.120945 <6>[ 14.461007] usbcore: registered new device driver onboard-usb-dev
1426 08:26:06.126174 <6>[ 14.461158] [drm] Initialized meson 1.0.0 for ff900000.vpu on minor 1
1427 08:26:06.461778 <6>[ 14.634555] Console: switching to colour frame buffer device 128x48
1428 08:26:06.462396 <6>[ 14.654451] meson-drm ff900000.vpu: [drm] fb0: mesondrmfb frame buffer device
1429 08:26:06.464572 <6>[ 14.679980] cpufreq: cpufreq_online: CPU2: Running at unlisted initial frequency: 999999 kHz, changing to: 1000000 kHz
1430 08:26:06.549629 <6>[ 14.900028] hub 1-1:1.0: USB hub found
1431 08:26:06.555057 <6>[ 14.900369] hub 1-1:1.0: 4 ports detected
1432 08:26:06.561521 <6>[ 14.905838] onboard-usb-dev 1-1: USB disconnect, device number 2
1433 08:26:06.675377 <4>[ 15.025797] rc rc0: two consecutive events of type space
1434 08:26:06.959588 <6>[ 15.305803] usb 1-1: new high-speed USB device number 3 using xhci-hcd
1435 08:26:07.157718 <6>[ 15.508000] hub 1-1:1.0: USB hub found
1436 08:26:07.163219 <6>[ 15.508316] hub 1-1:1.0: 4 ports detected
1437 08:26:07.171867 Begin: Loading essential drivers ... done.
1438 08:26:07.177478 Begin: Running /scripts/init-premount ... done.
1439 08:26:07.182948 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
1440 08:26:07.196695 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
1441 08:26:07.197186 Device /sys/class/net/end0 found
1442 08:26:07.197640 done.
1443 08:26:07.212560 Begin: Waiting up to 180 secs for any network device to become available ... done.
1444 08:26:07.250440 IP-Config: end0 hardware address de:ca:d3:e3:c6:63 mtu 1500 DHCP
<6>[ 15.592324] meson8b-dwmac ff3f0000.ethernet end0: Register MEM_TYPE_PAGE_POOL RxQ-0
1445 08:26:07.250962
1446 08:26:07.332868 <6>[ 15.677874] meson8b-dwmac ff3f0000.ethernet end0: PHY [mdio_mux-0.0:00] driver [RTL8211F Gigabit Ethernet] (irq=32)
1447 08:26:07.344172 <6>[ 15.683859] usb 2-1: reset SuperSpeed USB device number 2 using xhci-hcd
1448 08:26:07.349671 <6>[ 15.695375] meson8b-dwmac ff3f0000.ethernet end0: No Safety Features support found
1449 08:26:07.355072 <6>[ 15.697656] meson8b-dwmac ff3f0000.ethernet end0: PTP not supported by HW
1450 08:26:07.365343 <6>[ 15.705016] meson8b-dwmac ff3f0000.ethernet end0: configuring for phy/rgmii link mode
1451 08:26:07.593725 <6>[ 15.939850] usb 2-1: reset SuperSpeed USB device number 2 using xhci-hcd
1452 08:26:08.423726 IP-Config: no response after 2 secs - giving up
1453 08:26:08.470468 IP-Config: end0 hardware address de:ca:d3:e3:c6:63 mtu 1500 DHCP
1454 08:26:10.309737 <6>[ 18.654111] meson8b-dwmac ff3f0000.ethernet end0: Link is Up - 1Gbps/Full - flow control off
1455 08:26:10.684518 IP-Config: end0 guessed broadcast address 192.168.6.255
1456 08:26:10.689928 IP-Config: end0 complete (dhcp from 192.168.6.1):
1457 08:26:10.695400 address: 192.168.6.27 broadcast: 192.168.6.255 netmask: 255.255.255.0
1458 08:26:10.704422 gateway: 192.168.6.1 dns0 : 10.255.253.1 dns1 : 0.0.0.0
1459 08:26:10.709996 rootserver: 192.168.6.1 rootpath:
1460 08:26:10.710481 filename :
1461 08:26:10.823684 done.
1462 08:26:10.833983 Begin: Running /scripts/nfs-bottom ... done.
1463 08:26:10.843376 Begin: Running /scripts/init-bottom ... done.
1464 08:26:11.158424 <30>[ 19.504314] systemd[1]: System time before build time, advancing clock.
1465 08:26:11.209232 <6>[ 19.559677] NET: Registered PF_INET6 protocol family
1466 08:26:11.214776 <6>[ 19.562511] Segment Routing with IPv6
1467 08:26:11.219961 <6>[ 19.563179] In-situ OAM (IOAM) with IPv6
1468 08:26:11.293495 <30>[ 19.616318] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
1469 08:26:11.299171 <30>[ 19.643692] systemd[1]: Detected architecture arm64.
1470 08:26:11.299650
1471 08:26:11.306544 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
1472 08:26:11.307042
1473 08:26:11.320774 <30>[ 19.667466] systemd[1]: Hostname set to <debian-bookworm-arm64>.
1474 08:26:11.998820 <30>[ 20.344189] systemd[1]: Queued start job for default target graphical.target.
1475 08:26:12.027316 <30>[ 20.372140] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
1476 08:26:12.034803 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
1477 08:26:12.045842 <30>[ 20.390782] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
1478 08:26:12.054283 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
1479 08:26:12.065954 <30>[ 20.410835] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
1480 08:26:12.079400 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
1481 08:26:12.084950 <30>[ 20.430542] systemd[1]: Created slice user.slice - User and Session Slice.
1482 08:26:12.091433 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
1483 08:26:12.102287 <30>[ 20.446047] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
1484 08:26:12.113800 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
1485 08:26:12.124878 <30>[ 20.465978] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
1486 08:26:12.131432 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
1487 08:26:12.153618 <30>[ 20.485956] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
1488 08:26:12.159171 <30>[ 20.500029] systemd[1]: Expecting device dev-ttyAML0.device - /dev/ttyAML0...
1489 08:26:12.166811 Expecting device [0;1;39mdev-ttyAML0.device[0m - /dev/ttyAML0...
1490 08:26:12.177909 <30>[ 20.521869] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
1491 08:26:12.185068 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
1492 08:26:12.200882 <30>[ 20.545888] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
1493 08:26:12.214575 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
1494 08:26:12.220228 <30>[ 20.565915] systemd[1]: Reached target paths.target - Path Units.
1495 08:26:12.228555 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
1496 08:26:12.234063 <30>[ 20.581870] systemd[1]: Reached target remote-fs.target - Remote File Systems.
1497 08:26:12.245825 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
1498 08:26:12.251383 <30>[ 20.597859] systemd[1]: Reached target slices.target - Slice Units.
1499 08:26:12.259527 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
1500 08:26:12.265067 <30>[ 20.613895] systemd[1]: Reached target swap.target - Swaps.
1501 08:26:12.272916 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
1502 08:26:12.284861 <30>[ 20.629890] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
1503 08:26:12.293763 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
1504 08:26:12.309077 <30>[ 20.654069] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
1505 08:26:12.318320 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
1506 08:26:12.330174 <30>[ 20.675161] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
1507 08:26:12.338997 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
1508 08:26:12.353778 <30>[ 20.698767] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
1509 08:26:12.363159 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
1510 08:26:12.377263 <30>[ 20.722219] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
1511 08:26:12.384042 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
1512 08:26:12.391720 <30>[ 20.738808] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
1513 08:26:12.402959 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
1514 08:26:12.414764 <30>[ 20.759772] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
1515 08:26:12.420329 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
1516 08:26:12.434891 <30>[ 20.778124] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
1517 08:26:12.441591 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
1518 08:26:12.480964 <30>[ 20.825967] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
1519 08:26:12.487682 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
1520 08:26:12.499528 <30>[ 20.844520] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
1521 08:26:12.507045 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
1522 08:26:12.519016 <30>[ 20.864013] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
1523 08:26:12.526431 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
1524 08:26:12.543712 <30>[ 20.882621] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
1525 08:26:12.554795 <30>[ 20.898316] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
1526 08:26:12.561892 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
1527 08:26:12.577843 <30>[ 20.922857] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
1528 08:26:12.585811 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
1529 08:26:12.601777 <30>[ 20.946777] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
1530 08:26:12.609402 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
1531 08:26:12.625841 <6>[ 20.970842] device-mapper: ioctl: 4.48.0-ioctl (2023-03-01) initialised: dm-devel@lists.linux.dev
1532 08:26:12.636950 <30>[ 20.972477] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
1533 08:26:12.641835 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
1534 08:26:12.658368 <30>[ 21.003345] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
1535 08:26:12.666640 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
1536 08:26:12.681954 <30>[ 21.026953] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
1537 08:26:12.689213 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
1538 08:26:12.703744 <30>[ 21.048745] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
1539 08:26:12.713240 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel<6>[ 21.057292] fuse: init (API version 7.41)
1540 08:26:12.713731 Module loop...
1541 08:26:12.733616 <30>[ 21.078620] systemd[1]: Starting systemd-journald.service - Journal Service...
1542 08:26:12.740014 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
1543 08:26:12.760396 <30>[ 21.105392] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
1544 08:26:12.767903 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
1545 08:26:12.779235 <30>[ 21.124187] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
1546 08:26:12.788567 Starting [0;1;39msystemd-network-g… units from Kernel command line...
1547 08:26:12.803229 <30>[ 21.148173] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
1548 08:26:12.811969 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
1549 08:26:12.823227 <30>[ 21.168189] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
1550 08:26:12.831172 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
1551 08:26:12.846880 <30>[ 21.191872] systemd[1]: Started systemd-journald.service - Journal Service.
1552 08:26:12.853697 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
1553 08:26:12.869439 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
1554 08:26:12.886045 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
1555 08:26:12.902098 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
1556 08:26:12.918638 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
1557 08:26:12.931724 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
1558 08:26:12.943721 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
1559 08:26:12.955338 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
1560 08:26:12.967710 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
1561 08:26:12.979470 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
1562 08:26:12.994535 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
1563 08:26:13.001870 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
1564 08:26:13.015415 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
1565 08:26:13.026740 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
1566 08:26:13.040003 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
1567 08:26:13.081362 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
1568 08:26:13.101094 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
1569 08:26:13.117246 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
1570 08:26:13.137732 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
1571 08:26:13.154777 <46>[ 21.499790] systemd-journald[235]: Received client request to flush runtime journal.
1572 08:26:13.162165 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
1573 08:26:13.175011 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
1574 08:26:13.193918 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
1575 08:26:13.206194 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
1576 08:26:13.221739 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
1577 08:26:13.234074 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
1578 08:26:13.246068 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
1579 08:26:13.345862 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
1580 08:26:13.393069 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
1581 08:26:13.477112 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
1582 08:26:13.506325 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
1583 08:26:13.517547 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
1584 08:26:13.532574 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
1585 08:26:13.584632 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
1586 08:26:13.595436 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
1587 08:26:13.814423 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
1588 08:26:13.826046 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
1589 08:26:13.876633 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
1590 08:26:13.903942 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
1591 08:26:13.910495 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
1592 08:26:13.954329 [[0;32m OK [0m] Found device [0;1;39mdev-ttyAML0.device[0m - /dev/ttyAML0.
1593 08:26:14.004988 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
1594 08:26:14.069010 <5>[ 22.414103] cfg80211: Loading compiled-in X.509 certificates for regulatory database
1595 08:26:14.093330 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
1596 08:26:14.101691 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
1597 08:26:14.107223 <5>[ 22.457168] Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
1598 08:26:14.118306 <5>[ 22.457958] Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
1599 08:26:14.123863 <4>[ 22.465621] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
1600 08:26:14.131283 <6>[ 22.473811] cfg80211: failed to load regulatory.db
1601 08:26:14.141512 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
1602 08:26:14.156513 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
1603 08:26:14.176974 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
1604 08:26:14.199505 <46>[ 22.533423] systemd-journald[235]: Oldest entry in /var/log/journal/44a983756b26438995e691b947c527e4/system.journal is older than the configured file retention duration (1month), suggesting rotation.
1605 08:26:14.213347 <46>[ 22.546459] systemd-journald[235]: /var/log/journal/44a983756b26438995e691b947c527e4/system.journal: Journal header limits reached or header out-of-date, rotating.
1606 08:26:14.229352 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
1607 08:26:14.245352 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
1608 08:26:14.263340 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
1609 08:26:14.353199 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
1610 08:26:14.360059 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
1611 08:26:14.377005 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
1612 08:26:14.384234 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
1613 08:26:14.395959 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
1614 08:26:14.436033 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
1615 08:26:14.465307 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
1616 08:26:14.488235 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
1617 08:26:14.502092 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
1618 08:26:14.546397 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
1619 08:26:14.557646 [[0;32m OK [0m] Reached target [0;1;39musb-gadget.…m - Hardware activated USB gadget.
1620 08:26:14.573576 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
1621 08:26:14.615567 Starting [0;1;39malsa-restore.serv…- Save/Restore Sound Card State...
1622 08:26:14.622115 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
1623 08:26:14.632846 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
1624 08:26:14.664072 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
1625 08:26:14.679588 [[0;32m OK [0m] Finished [0;1;39malsa-restore.serv…m - Save/Restore Sound Card State.
1626 08:26:14.693930 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
1627 08:26:14.700830 [[0;32m OK [0m] Reached target [0;1;39msound.target[0m - Sound Card.
1628 08:26:14.736792 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
1629 08:26:14.761537 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyAM…ice[0m - Serial Getty on ttyAML0.
1630 08:26:14.767725 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
1631 08:26:14.778497 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
1632 08:26:14.790857 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
1633 08:26:14.801861 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
1634 08:26:14.818711 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
1635 08:26:14.863516 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
1636 08:26:14.955917
1637 08:26:14.956414 Debian GNU/Linux 12 debian-bookworm-arm64 ttyAML0
1638 08:26:14.956816
1639 08:26:14.963142 debian-bookworm-arm64 login: root (automatic login)
1640 08:26:14.963574
1641 08:26:15.099343 Linux debian-bookworm-arm64 6.12.0-rc7-next-20241112 #1 SMP PREEMPT Tue Nov 12 07:32:50 UTC 2024 aarch64
1642 08:26:15.099817
1643 08:26:15.104878 The programs included with the Debian GNU/Linux system are free software;
1644 08:26:15.110446 the exact distribution terms for each program are described in the
1645 08:26:15.115969 individual files in /usr/share/doc/*/copyright.
1646 08:26:15.116424
1647 08:26:15.121602 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
1648 08:26:15.125898 permitted by applicable law.
1649 08:26:15.781381 Matched prompt #10: / #
1651 08:26:15.782963 Setting prompt string to ['/ #']
1652 08:26:15.783544 end: 2.4.4.1 login-action (duration 00:00:25) [common]
1654 08:26:15.784999 end: 2.4.4 auto-login-action (duration 00:00:25) [common]
1655 08:26:15.785534 start: 2.4.5 expect-shell-connection (timeout 00:03:18) [common]
1656 08:26:15.785966 Setting prompt string to ['/ #']
1657 08:26:15.786376 Forcing a shell prompt, looking for ['/ #']
1659 08:26:15.837339 / #
1660 08:26:15.838070 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
1661 08:26:15.838514 Waiting using forced prompt support (timeout 00:02:30)
1662 08:26:15.842876
1663 08:26:15.843687 end: 2.4.5 expect-shell-connection (duration 00:00:00) [common]
1664 08:26:15.844325 start: 2.4.6 export-device-env (timeout 00:03:18) [common]
1665 08:26:15.844798 Sending with 10 millisecond of delay
1667 08:26:20.831711 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/978668/extract-nfsrootfs-iaw2q4k4'
1668 08:26:20.842699 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/978668/extract-nfsrootfs-iaw2q4k4'
1669 08:26:20.843469 Sending with 10 millisecond of delay
1671 08:26:22.941830 / # export NFS_SERVER_IP='192.168.6.2'
1672 08:26:22.952870 export NFS_SERVER_IP='192.168.6.2'
1673 08:26:22.953812 end: 2.4.6 export-device-env (duration 00:00:07) [common]
1674 08:26:22.954457 end: 2.4 uboot-commands (duration 00:01:49) [common]
1675 08:26:22.955084 end: 2 uboot-action (duration 00:01:49) [common]
1676 08:26:22.955708 start: 3 lava-test-retry (timeout 00:06:53) [common]
1677 08:26:22.956404 start: 3.1 lava-test-shell (timeout 00:06:53) [common]
1678 08:26:22.956921 Using namespace: common
1680 08:26:23.058226 / # #
1681 08:26:23.058970 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
1682 08:26:23.064377 #
1683 08:26:23.065173 Using /lava-978668
1685 08:26:23.166371 / # export SHELL=/bin/bash
1686 08:26:23.172392 export SHELL=/bin/bash
1688 08:26:23.273844 / # . /lava-978668/environment
1689 08:26:23.278716 . /lava-978668/environment
1691 08:26:23.384672 / # /lava-978668/bin/lava-test-runner /lava-978668/0
1692 08:26:23.385413 Test shell timeout: 10s (minimum of the action and connection timeout)
1693 08:26:23.389782 /lava-978668/bin/lava-test-runner /lava-978668/0
1694 08:26:23.604703 + export TESTRUN_ID=0_timesync-off
1695 08:26:23.612376 + TESTRUN_ID=0_timesync-off
1696 08:26:23.612886 + cd /lava-978668/0/tests/0_timesync-off
1697 08:26:23.613361 ++ cat uuid
1698 08:26:23.617917 + UUID=978668_1.6.2.4.1
1699 08:26:23.618410 + set +x
1700 08:26:23.625765 <LAVA_SIGNAL_STARTRUN 0_timesync-off 978668_1.6.2.4.1>
1701 08:26:23.626260 + systemctl stop systemd-timesyncd
1702 08:26:23.627020 Received signal: <STARTRUN> 0_timesync-off 978668_1.6.2.4.1
1703 08:26:23.627515 Starting test lava.0_timesync-off (978668_1.6.2.4.1)
1704 08:26:23.628140 Skipping test definition patterns.
1705 08:26:23.679335 + set +x
1706 08:26:23.679901 <LAVA_SIGNAL_ENDRUN 0_timesync-off 978668_1.6.2.4.1>
1707 08:26:23.680668 Received signal: <ENDRUN> 0_timesync-off 978668_1.6.2.4.1
1708 08:26:23.681212 Ending use of test pattern.
1709 08:26:23.681670 Ending test lava.0_timesync-off (978668_1.6.2.4.1), duration 0.05
1711 08:26:23.756233 + export TESTRUN_ID=1_kselftest-alsa
1712 08:26:23.764682 + TESTRUN_ID=1_kselftest-alsa
1713 08:26:23.765182 + cd /lava-978668/0/tests/1_kselftest-alsa
1714 08:26:23.765647 ++ cat uuid
1715 08:26:23.770393 + UUID=978668_1.6.2.4.5
1716 08:26:23.770879 + set +x
1717 08:26:23.775907 <LAVA_SIGNAL_STARTRUN 1_kselftest-alsa 978668_1.6.2.4.5>
1718 08:26:23.776445 + cd ./automated/linux/kselftest/
1719 08:26:23.777181 Received signal: <STARTRUN> 1_kselftest-alsa 978668_1.6.2.4.5
1720 08:26:23.777654 Starting test lava.1_kselftest-alsa (978668_1.6.2.4.5)
1721 08:26:23.778185 Skipping test definition patterns.
1722 08:26:23.801804 + ./kselftest.sh -c alsa -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/next/master/next-20241112/arm64/defconfig/gcc-12/kselftest.tar.xz -L '' -S /dev/null -b meson-g12b-a311d-libretech-cc -g next -e '' -p /opt/kselftests/mainline/ -n 1 -i 1 -E ''
1723 08:26:23.838352 INFO: install_deps skipped
1724 08:26:23.953949 --2024-11-12 08:26:23-- http://storage.kernelci.org/next/master/next-20241112/arm64/defconfig/gcc-12/kselftest.tar.xz
1725 08:26:23.981545 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
1726 08:26:24.120316 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
1727 08:26:24.256712 HTTP request sent, awaiting response... 200 OK
1728 08:26:24.257290 Length: 6756532 (6.4M) [application/octet-stream]
1729 08:26:24.262127 Saving to: 'kselftest_armhf.tar.gz'
1730 08:26:24.262609
1731 08:26:25.515884
kselftest_armhf.tar 0%[ ] 0 --.-KB/s
kselftest_armhf.tar 0%[ ] 49.92K 182KB/s
kselftest_armhf.tar 3%[ ] 218.67K 399KB/s
kselftest_armhf.tar 13%[=> ] 893.67K 1.06MB/s
kselftest_armhf.tar 47%[========> ] 3.06M 2.75MB/s
kselftest_armhf.tar 100%[===================>] 6.44M 5.14MB/s in 1.3s
1732 08:26:25.516643
1733 08:26:25.618034 2024-11-12 08:26:25 (5.14 MB/s) - 'kselftest_armhf.tar.gz' saved [6756532/6756532]
1734 08:26:25.618704
1735 08:26:34.746648 skiplist:
1736 08:26:34.747341 ========================================
1737 08:26:34.752179 ========================================
1738 08:26:34.789507 alsa:mixer-test
1739 08:26:34.790009 alsa:pcm-test
1740 08:26:34.790467 alsa:test-pcmtest-driver
1741 08:26:34.793472 alsa:utimer-test
1742 08:26:34.804939 ============== Tests to run ===============
1743 08:26:34.805422 alsa:mixer-test
1744 08:26:34.810422 alsa:pcm-test
1745 08:26:34.810902 alsa:test-pcmtest-driver
1746 08:26:34.811349 alsa:utimer-test
1747 08:26:34.818758 ===========End Tests to run ===============
1748 08:26:34.819244 shardfile-alsa pass
1749 08:26:34.927751 <12>[ 43.276085] kselftest: Running tests in alsa
1750 08:26:34.933856 TAP version 13
1751 08:26:34.941780 1..4
1752 08:26:34.962231 # timeout set to 45
1753 08:26:34.962703 # selftests: alsa: mixer-test
1754 08:26:35.130705 # TAP version 13
1755 08:26:35.131285 # # Card 0/LCALTA - LC-ALTA (LC-ALTA)
1756 08:26:35.136086 # 1..427
1757 08:26:35.136601 # ok 1 get_value.LCALTA.60
1758 08:26:35.137066 # # LCALTA.60 TDMOUT_A SRC SEL
1759 08:26:35.141707 # ok 2 name.LCALTA.60
1760 08:26:35.142181 # ok 3 write_default.LCALTA.60
1761 08:26:35.145177 # ok 4 write_valid.LCALTA.60
1762 08:26:35.150708 # ok 5 write_invalid.LCALTA.60
1763 08:26:35.151187 # ok 6 event_missing.LCALTA.60
1764 08:26:35.156341 # ok 7 event_spurious.LCALTA.60
1765 08:26:35.156812 # ok 8 get_value.LCALTA.59
1766 08:26:35.161892 # # LCALTA.59 TDMOUT_B SRC SEL
1767 08:26:35.162357 # ok 9 name.LCALTA.59
1768 08:26:35.165565 # ok 10 write_default.LCALTA.59
1769 08:26:35.166036 # ok 11 write_valid.LCALTA.59
1770 08:26:35.171072 # ok 12 write_invalid.LCALTA.59
1771 08:26:35.171537 # ok 13 event_missing.LCALTA.59
1772 08:26:35.176699 # ok 14 event_spurious.LCALTA.59
1773 08:26:35.177180 # ok 15 get_value.LCALTA.58
1774 08:26:35.182034 # # LCALTA.58 TDMOUT_C SRC SEL
1775 08:26:35.182504 # ok 16 name.LCALTA.58
1776 08:26:35.185823 # ok 17 write_default.LCALTA.58
1777 08:26:35.191267 # ok 18 write_valid.LCALTA.58
1778 08:26:35.191732 # ok 19 write_invalid.LCALTA.58
1779 08:26:35.196951 # ok 20 event_missing.LCALTA.58
1780 08:26:35.197422 # ok 21 event_spurious.LCALTA.58
1781 08:26:35.202456 # ok 22 get_value.LCALTA.57
1782 08:26:35.202927 # # LCALTA.57 TDMIN_A SRC SEL
1783 08:26:35.203374 # ok 23 name.LCALTA.57
1784 08:26:35.207871 # ok 24 write_default.LCALTA.57
1785 08:26:35.208380 # ok 25 write_valid.LCALTA.57
1786 08:26:35.213360 # ok 26 write_invalid.LCALTA.57
1787 08:26:35.213831 # ok 27 event_missing.LCALTA.57
1788 08:26:35.218865 # ok 28 event_spurious.LCALTA.57
1789 08:26:35.219330 # ok 29 get_value.LCALTA.56
1790 08:26:35.224425 # # LCALTA.56 TDMIN_B SRC SEL
1791 08:26:35.224898 # ok 30 name.LCALTA.56
1792 08:26:35.229958 # ok 31 write_default.LCALTA.56
1793 08:26:35.230429 # ok 32 write_valid.LCALTA.56
1794 08:26:35.235486 # ok 33 write_invalid.LCALTA.56
1795 08:26:35.246648 #<3>[ 43.582693] fe.dai-link-5: ASoC: no backend DAIs enabled for fe.dai-link-5, possibly missing ALSA mixer-based routing or UCM profile
1796 08:26:35.252207 ok 34 event_missing.LCALTA.56
1797 08:26:35.252672 # ok 35 event_spurious.LCALTA.56
1798 08:26:35.257693 # ok 36 get_value.LCALTA.55
1799 08:26:35.258162 # # LCALTA.55 TDMIN_C SRC SEL
1800 08:26:35.258608 # ok 37 name.LCALTA.55
1801 08:26:35.263301 # ok 38 write_default.LCALTA.55
1802 08:26:35.263771 # ok 39 write_valid.LCALTA.55
1803 08:26:35.268805 # ok 40 write_invalid.LCALTA.55
1804 08:26:35.269276 # ok 41 event_missing.LCALTA.55
1805 08:26:35.274387 # ok 42 event_spurious.LCALTA.55
1806 08:26:35.274854 # ok 43 get_value.LCALTA.54
1807 08:26:35.279921 # # LCALTA.54 ACODEC Left DAC Sel
1808 08:26:35.280424 # ok 44 name.LCALTA.54
1809 08:26:35.285476 # ok 45 write_default.LCALTA.54
1810 08:26:35.285948 # ok 46 write_valid.LCALTA.54
1811 08:26:35.290980 # ok 47 write_invalid.LCALTA.54
1812 08:26:35.291465 # ok 48 event_missing.LCALTA.54
1813 08:26:35.296543 # ok 49 event_spurious.LCALTA.54
1814 08:26:35.297013 # ok 50 get_value.LCALTA.53
1815 08:26:35.302109 # # LCALTA.53 ACODEC Right DAC Sel
1816 08:26:35.302577 # ok 51 name.LCALTA.53
1817 08:26:35.307660 # ok 52 write_default.LCALTA.53
1818 08:26:35.308166 # ok 53 write_valid.LCALTA.53
1819 08:26:35.313198 # ok 54 write_invalid.LCALTA.53
1820 08:26:35.313672 # ok 55 event_missing.LCALTA.53
1821 08:26:35.318733 # ok 56 event_spurious.LCALTA.53
1822 08:26:35.319206 # ok 57 get_value.LCALTA.52
1823 08:26:35.324333 # # LCALTA.52 TOACODEC OUT EN Switch
1824 08:26:35.324806 # ok 58 name.LCALTA.52
1825 08:26:35.329822 # ok 59 write_default.LCALTA.52
1826 08:26:35.330293 # ok 60 write_valid.LCALTA.52
1827 08:26:35.335401 # ok 61 write_invalid.LCALTA.52
1828 08:26:35.335882 # ok 62 event_missing.LCALTA.52
1829 08:26:35.340945 # ok 63 event_spurious.LCALTA.52
1830 08:26:35.341437 # ok 64 get_value.LCALTA.51
1831 08:26:35.346479 # # LCALTA.51 TOACODEC SRC
1832 08:26:35.346972 # ok 65 name.LCALTA.51
1833 08:26:35.352011 # ok 66 write_default.LCALTA.51
1834 08:26:35.352495 # ok 67 write_valid.LCALTA.51
1835 08:26:35.357554 # ok 68 write_invalid.LCALTA.51
1836 08:26:35.358025 # ok 69 event_missing.LCALTA.51
1837 08:26:35.363099 # ok 70 event_spurious.LCALTA.51
1838 08:26:35.363569 # ok 71 get_value.LCALTA.50
1839 08:26:35.368661 # # LCALTA.50 TOHDMITX SPDIF SRC
1840 08:26:35.369152 # ok 72 name.LCALTA.50
1841 08:26:35.374208 # ok 73 write_default.LCALTA.50
1842 08:26:35.374686 # ok 74 write_valid.LCALTA.50
1843 08:26:35.379741 # ok 75 write_invalid.LCALTA.50
1844 08:26:35.380247 # ok 76 event_missing.LCALTA.50
1845 08:26:35.385349 # ok 77 event_spurious.LCALTA.50
1846 08:26:35.385848 # ok 78 get_value.LCALTA.49
1847 08:26:35.390800 # # LCALTA.49 TOHDMITX Switch
1848 08:26:35.391273 # ok 79 name.LCALTA.49
1849 08:26:35.391721 # ok 80 write_default.LCALTA.49
1850 08:26:35.396380 # ok 81 write_valid.LCALTA.49
1851 08:26:35.396902 # ok 82 write_invalid.LCALTA.49
1852 08:26:35.401912 # ok 83 event_missing.LCALTA.49
1853 08:26:35.402431 # ok 84 event_spurious.LCALTA.49
1854 08:26:35.407457 # ok 85 get_value.LCALTA.48
1855 08:26:35.408020 # # LCALTA.48 TOHDMITX I2S SRC
1856 08:26:35.412965 # ok 86 name.LCALTA.48
1857 08:26:35.413432 # ok 87 write_default.LCALTA.48
1858 08:26:35.418512 # ok 88 write_valid.LCALTA.48
1859 08:26:35.418967 # ok 89 write_invalid.LCALTA.48
1860 08:26:35.424087 # ok 90 event_missing.LCALTA.48
1861 08:26:35.424556 # ok 91 event_spurious.LCALTA.48
1862 08:26:35.429606 # ok 92 get_value.LCALTA.47
1863 08:26:35.430060 # # LCALTA.47 TODDR_C SRC SEL
1864 08:26:35.435235 # ok 93 name.LCALTA.47
1865 08:26:35.435688 # ok 94 write_default.LCALTA.47
1866 08:26:35.440734 # ok 95 write_valid.LCALTA.47
1867 08:26:35.441224 # ok 96 write_invalid.LCALTA.47
1868 08:26:35.446310 # ok 97 event_missing.LCALTA.47
1869 08:26:35.446769 # ok 98 event_spurious.LCALTA.47
1870 08:26:35.451809 # ok 99 get_value.LCALTA.46
1871 08:26:35.452305 # # LCALTA.46 TODDR_B SRC SEL
1872 08:26:35.457366 # ok 100 name.LCALTA.46
1873 08:26:35.457831 # ok 101 write_default.LCALTA.46
1874 08:26:35.462905 # ok 102 write_valid.LCALTA.46
1875 08:26:35.463366 # ok 103 write_invalid.LCALTA.46
1876 08:26:35.468479 # ok 104 event_missing.LCALTA.46
1877 08:26:35.468943 # ok 105 event_spurious.LCALTA.46
1878 08:26:35.474029 # ok 106 get_value.LCALTA.45
1879 08:26:35.474488 # # LCALTA.45 TODDR_A SRC SEL
1880 08:26:35.479571 # ok 107 name.LCALTA.45
1881 08:26:35.480059 # ok 108 write_default.LCALTA.45
1882 08:26:35.485141 # ok 109 write_valid.LCALTA.45
1883 08:26:35.485600 # ok 110 write_invalid.LCALTA.45
1884 08:26:35.490684 # ok 111 event_missing.LCALTA.45
1885 08:26:35.491144 # ok 112 event_spurious.LCALTA.45
1886 08:26:35.496253 # ok 113 get_value.LCALTA.44
1887 08:26:35.496712 # # LCALTA.44 FRDDR_C SINK 3 SEL
1888 08:26:35.501779 # ok 114 name.LCALTA.44
1889 08:26:35.502237 # ok 115 write_default.LCALTA.44
1890 08:26:35.507378 # ok 116 write_valid.LCALTA.44
1891 08:26:35.507833 # ok 117 write_invalid.LCALTA.44
1892 08:26:35.512885 # ok 118 event_missing.LCALTA.44
1893 08:26:35.513352 # ok 119 event_spurious.LCALTA.44
1894 08:26:35.518418 # ok 120 get_value.LCALTA.43
1895 08:26:35.518874 # # LCALTA.43 FRDDR_C SINK 2 SEL
1896 08:26:35.523958 # ok 121 name.LCALTA.43
1897 08:26:35.524447 # ok 122 write_default.LCALTA.43
1898 08:26:35.529514 # ok 123 write_valid.LCALTA.43
1899 08:26:35.529971 # ok 124 write_invalid.LCALTA.43
1900 08:26:35.535051 # ok 125 event_missing.LCALTA.43
1901 08:26:35.535506 # ok 126 event_spurious.LCALTA.43
1902 08:26:35.540617 # ok 127 get_value.LCALTA.42
1903 08:26:35.541075 # # LCALTA.42 FRDDR_C SINK 1 SEL
1904 08:26:35.546134 # ok 128 name.LCALTA.42
1905 08:26:35.546590 # ok 129 write_default.LCALTA.42
1906 08:26:35.551704 # ok 130 write_valid.LCALTA.42
1907 08:26:35.552191 # ok 131 write_invalid.LCALTA.42
1908 08:26:35.557261 # ok 132 event_missing.LCALTA.42
1909 08:26:35.557719 # ok 133 event_spurious.LCALTA.42
1910 08:26:35.562773 # ok 134 get_value.LCALTA.41
1911 08:26:35.563230 # # LCALTA.41 FRDDR_C SRC 3 EN Switch
1912 08:26:35.568363 # ok 135 name.LCALTA.41
1913 08:26:35.568822 # ok 136 write_default.LCALTA.41
1914 08:26:35.573867 # ok 137 write_valid.LCALTA.41
1915 08:26:35.574322 # ok 138 write_invalid.LCALTA.41
1916 08:26:35.579444 # ok 139 event_missing.LCALTA.41
1917 08:26:35.579900 # ok 140 event_spurious.LCALTA.41
1918 08:26:35.584950 # ok 141 get_value.LCALTA.40
1919 08:26:35.585406 # # LCALTA.40 FRDDR_C SRC 2 EN Switch
1920 08:26:35.590518 # ok 142 name.LCALTA.40
1921 08:26:35.590972 # ok 143 write_default.LCALTA.40
1922 08:26:35.596074 # ok 144 write_valid.LCALTA.40
1923 08:26:35.596531 # ok 145 write_invalid.LCALTA.40
1924 08:26:35.601627 # ok 146 event_missing.LCALTA.40
1925 08:26:35.602084 # ok 147 event_spurious.LCALTA.40
1926 08:26:35.607163 # ok 148 get_value.LCALTA.39
1927 08:26:35.612719 # # LCALTA.39 FRDDR_C SRC 1 EN Switch
1928 08:26:35.613195 # ok 149 name.LCALTA.39
1929 08:26:35.613628 # ok 150 write_default.LCALTA.39
1930 08:26:35.618282 # ok 151 write_valid.LCALTA.39
1931 08:26:35.623807 # ok 152 write_invalid.LCALTA.39
1932 08:26:35.624299 # ok 153 event_missing.LCALTA.39
1933 08:26:35.629371 # ok 154 event_spurious.LCALTA.39
1934 08:26:35.629826 # ok 155 get_value.LCALTA.38
1935 08:26:35.634906 # # LCALTA.38 FRDDR_B SINK 3 SEL
1936 08:26:35.635357 # ok 156 name.LCALTA.38
1937 08:26:35.640454 # ok 157 write_default.LCALTA.38
1938 08:26:35.640907 # ok 158 write_valid.LCALTA.38
1939 08:26:35.646004 # ok 159 write_invalid.LCALTA.38
1940 08:26:35.646455 # ok 160 event_missing.LCALTA.38
1941 08:26:35.651536 # ok 161 event_spurious.LCALTA.38
1942 08:26:35.652010 # ok 162 get_value.LCALTA.37
1943 08:26:35.657089 # # LCALTA.37 FRDDR_B SINK 2 SEL
1944 08:26:35.657543 # ok 163 name.LCALTA.37
1945 08:26:35.662635 # ok 164 write_default.LCALTA.37
1946 08:26:35.663088 # ok 165 write_valid.LCALTA.37
1947 08:26:35.668250 # ok 166 write_invalid.LCALTA.37
1948 08:26:35.668699 # ok 167 event_missing.LCALTA.37
1949 08:26:35.673702 # ok 168 event_spurious.LCALTA.37
1950 08:26:35.674156 # ok 169 get_value.LCALTA.36
1951 08:26:35.679274 # # LCALTA.36 FRDDR_B SINK 1 SEL
1952 08:26:35.679726 # ok 170 name.LCALTA.36
1953 08:26:35.684815 # ok 171 write_default.LCALTA.36
1954 08:26:35.685274 # ok 172 write_valid.LCALTA.36
1955 08:26:35.690412 # ok 173 write_invalid.LCALTA.36
1956 08:26:35.690866 # ok 174 event_missing.LCALTA.36
1957 08:26:35.695905 # ok 175 event_spurious.LCALTA.36
1958 08:26:35.696392 # ok 176 get_value.LCALTA.35
1959 08:26:35.701457 # # LCALTA.35 FRDDR_B SRC 3 EN Switch
1960 08:26:35.701912 # ok 177 name.LCALTA.35
1961 08:26:35.707013 # ok 178 write_default.LCALTA.35
1962 08:26:35.707466 # ok 179 write_valid.LCALTA.35
1963 08:26:35.712548 # ok 180 write_invalid.LCALTA.35
1964 08:26:35.712999 # ok 181 event_missing.LCALTA.35
1965 08:26:35.718075 # ok 182 event_spurious.LCALTA.35
1966 08:26:35.718526 # ok 183 get_value.LCALTA.34
1967 08:26:35.723638 # # LCALTA.34 FRDDR_B SRC 2 EN Switch
1968 08:26:35.724120 # ok 184 name.LCALTA.34
1969 08:26:35.729196 # ok 185 write_default.LCALTA.34
1970 08:26:35.729648 # ok 186 write_valid.LCALTA.34
1971 08:26:35.734745 # ok 187 write_invalid.LCALTA.34
1972 08:26:35.735198 # ok 188 event_missing.LCALTA.34
1973 08:26:35.740293 # ok 189 event_spurious.LCALTA.34
1974 08:26:35.740766 # ok 190 get_value.LCALTA.33
1975 08:26:35.745829 # # LCALTA.33 FRDDR_B SRC 1 EN Switch
1976 08:26:35.746282 # ok 191 name.LCALTA.33
1977 08:26:35.751411 # ok 192 write_default.LCALTA.33
1978 08:26:35.751861 # ok 193 write_valid.LCALTA.33
1979 08:26:35.756921 # ok 194 write_invalid.LCALTA.33
1980 08:26:35.757373 # ok 195 event_missing.LCALTA.33
1981 08:26:35.762439 # ok 196 event_spurious.LCALTA.33
1982 08:26:35.762892 # ok 197 get_value.LCALTA.32
1983 08:26:35.768050 # # LCALTA.32 FRDDR_A SINK 3 SEL
1984 08:26:35.768518 # ok 198 name.LCALTA.32
1985 08:26:35.773573 # ok 199 write_default.LCALTA.32
1986 08:26:35.774044 # ok 200 write_valid.LCALTA.32
1987 08:26:35.779109 # ok 201 write_invalid.LCALTA.32
1988 08:26:35.784669 # ok 202 event_missing.LCALTA.32
1989 08:26:35.785138 # ok 203 event_spurious.LCALTA.32
1990 08:26:35.790206 # ok 204 get_value.LCALTA.31
1991 08:26:35.790679 # # LCALTA.31 FRDDR_A SINK 2 SEL
1992 08:26:35.791123 # ok 205 name.LCALTA.31
1993 08:26:35.795759 # ok 206 write_default.LCALTA.31
1994 08:26:35.796270 # ok 207 write_valid.LCALTA.31
1995 08:26:35.801293 # ok 208 write_invalid.LCALTA.31
1996 08:26:35.806846 # ok 209 event_missing.LCALTA.31
1997 08:26:35.807315 # ok 210 event_spurious.LCALTA.31
1998 08:26:35.812420 # ok 211 get_value.LCALTA.30
1999 08:26:35.812893 # # LCALTA.30 FRDDR_A SINK 1 SEL
2000 08:26:35.813339 # ok 212 name.LCALTA.30
2001 08:26:35.817937 # ok 213 write_default.LCALTA.30
2002 08:26:35.823466 # ok 214 write_valid.LCALTA.30
2003 08:26:35.823935 # ok 215 write_invalid.LCALTA.30
2004 08:26:35.829062 # ok 216 event_missing.LCALTA.30
2005 08:26:35.829530 # ok 217 event_spurious.LCALTA.30
2006 08:26:35.834595 # ok 218 get_value.LCALTA.29
2007 08:26:35.835069 # # LCALTA.29 FRDDR_A SRC 3 EN Switch
2008 08:26:35.840151 # ok 219 name.LCALTA.29
2009 08:26:35.840622 # ok 220 write_default.LCALTA.29
2010 08:26:35.845681 # ok 221 write_valid.LCALTA.29
2011 08:26:35.846151 # ok 222 write_invalid.LCALTA.29
2012 08:26:35.851215 # ok 223 event_missing.LCALTA.29
2013 08:26:35.851688 # ok 224 event_spurious.LCALTA.29
2014 08:26:35.856766 # ok 225 get_value.LCALTA.28
2015 08:26:35.857236 # # LCALTA.28 FRDDR_A SRC 2 EN Switch
2016 08:26:35.862318 # ok 226 name.LCALTA.28
2017 08:26:35.862791 # ok 227 write_default.LCALTA.28
2018 08:26:35.867855 # ok 228 write_valid.LCALTA.28
2019 08:26:35.868356 # ok 229 write_invalid.LCALTA.28
2020 08:26:35.873427 # ok 230 event_missing.LCALTA.28
2021 08:26:35.873896 # ok 231 event_spurious.LCALTA.28
2022 08:26:35.878933 # ok 232 get_value.LCALTA.27
2023 08:26:35.879403 # # LCALTA.27 FRDDR_A SRC 1 EN Switch
2024 08:26:35.884473 # ok 233 name.LCALTA.27
2025 08:26:35.884945 # ok 234 write_default.LCALTA.27
2026 08:26:35.890050 # ok 235 write_valid.LCALTA.27
2027 08:26:35.890524 # ok 236 write_invalid.LCALTA.27
2028 08:26:35.895600 # ok 237 event_missing.LCALTA.27
2029 08:26:35.896109 # ok 238 event_spurious.LCALTA.27
2030 08:26:35.901140 # ok 239 get_value.LCALTA.26
2031 08:26:35.901615 # # LCALTA.26 ELD
2032 08:26:35.906677 # ok 240 name.LCALTA.26
2033 08:26:35.907145 # # ELD is not writeable
2034 08:26:35.912221 # ok 241 # SKIP write_default.LCALTA.26
2035 08:26:35.912695 # # ELD is not writeable
2036 08:26:35.917778 # ok 242 # SKIP write_valid.LCALTA.26
2037 08:26:35.918255 # # ELD is not writeable
2038 08:26:35.923340 # ok 243 # SKIP write_invalid.LCALTA.26
2039 08:26:35.923825 # ok 244 event_missing.LCALTA.26
2040 08:26:35.928884 # ok 245 event_spurious.LCALTA.26
2041 08:26:35.929358 # ok 246 get_value.LCALTA.25
2042 08:26:35.934416 # # LCALTA.25 IEC958 Playback Default
2043 08:26:35.934891 # ok 247 name.LCALTA.25
2044 08:26:35.939937 # ok 248 write_default.LCALTA.25
2045 08:26:35.940440 # ok 249 # SKIP write_valid.LCALTA.25
2046 08:26:35.945516 # ok 250 # SKIP write_invalid.LCALTA.25
2047 08:26:35.951067 # ok 251 event_missing.LCALTA.25
2048 08:26:35.951534 # ok 252 event_spurious.LCALTA.25
2049 08:26:35.956600 # ok 253 get_value.LCALTA.24
2050 08:26:35.957075 # # LCALTA.24 IEC958 Playback Mask
2051 08:26:35.962146 # ok 254 name.LCALTA.24
2052 08:26:35.962613 # # IEC958 Playback Mask is not writeable
2053 08:26:35.967698 # ok 255 # SKIP write_default.LCALTA.24
2054 08:26:35.973244 # # IEC958 Playback Mask is not writeable
2055 08:26:35.973713 # ok 256 # SKIP write_valid.LCALTA.24
2056 08:26:35.978775 # # IEC958 Playback Mask is not writeable
2057 08:26:35.979249 # ok 257 # SKIP write_invalid.LCALTA.24
2058 08:26:35.984331 # ok 258 event_missing.LCALTA.24
2059 08:26:35.989894 # ok 259 event_spurious.LCALTA.24
2060 08:26:35.990364 # ok 260 get_value.LCALTA.23
2061 08:26:35.995445 # # LCALTA.23 Playback Channel Map
2062 08:26:35.995918 # ok 261 name.LCALTA.23
2063 08:26:36.000988 # # Playback Channel Map is not writeable
2064 08:26:36.001462 # ok 262 # SKIP write_default.LCALTA.23
2065 08:26:36.006530 # # Playback Channel Map is not writeable
2066 08:26:36.012082 # ok 263 # SKIP write_valid.LCALTA.23
2067 08:26:36.012556 # # Playback Channel Map is not writeable
2068 08:26:36.017637 # ok 264 # SKIP write_invalid.LCALTA.23
2069 08:26:36.018119 # ok 265 event_missing.LCALTA.23
2070 08:26:36.023166 # ok 266 event_spurious.LCALTA.23
2071 08:26:36.023646 # ok 267 get_value.LCALTA.22
2072 08:26:36.028724 # # LCALTA.22 TDMOUT_A Gain Enable Switch
2073 08:26:36.029206 # ok 268 name.LCALTA.22
2074 08:26:36.034266 # ok 269 write_default.LCALTA.22
2075 08:26:36.034734 # ok 270 write_valid.LCALTA.22
2076 08:26:36.039813 # ok 271 write_invalid.LCALTA.22
2077 08:26:36.045361 # ok 272 event_missing.LCALTA.22
2078 08:26:36.045863 # ok 273 event_spurious.LCALTA.22
2079 08:26:36.050901 # ok 274 get_value.LCALTA.21
2080 08:26:36.051385 # # LCALTA.21 TDMOUT_A Lane 3 Volume
2081 08:26:36.056453 # ok 275 name.LCALTA.21
2082 08:26:36.056927 # ok 276 write_default.LCALTA.21
2083 08:26:36.061983 # ok 277 write_valid.LCALTA.21
2084 08:26:36.062452 # ok 278 write_invalid.LCALTA.21
2085 08:26:36.067511 # ok 279 event_missing.LCALTA.21
2086 08:26:36.068005 # ok 280 event_spurious.LCALTA.21
2087 08:26:36.073069 # ok 281 get_value.LCALTA.20
2088 08:26:36.073536 # # LCALTA.20 TDMOUT_A Lane 2 Volume
2089 08:26:36.078637 # ok 282 name.LCALTA.20
2090 08:26:36.079106 # ok 283 write_default.LCALTA.20
2091 08:26:36.084214 # ok 284 write_valid.LCALTA.20
2092 08:26:36.084684 # ok 285 write_invalid.LCALTA.20
2093 08:26:36.089702 # ok 286 event_missing.LCALTA.20
2094 08:26:36.090178 # ok 287 event_spurious.LCALTA.20
2095 08:26:36.095278 # ok 288 get_value.LCALTA.19
2096 08:26:36.095750 # # LCALTA.19 TDMOUT_A Lane 1 Volume
2097 08:26:36.100823 # ok 289 name.LCALTA.19
2098 08:26:36.101295 # ok 290 write_default.LCALTA.19
2099 08:26:36.106378 # ok 291 write_valid.LCALTA.19
2100 08:26:36.106847 # ok 292 write_invalid.LCALTA.19
2101 08:26:36.111924 # ok 293 event_missing.LCALTA.19
2102 08:26:36.112420 # ok 294 event_spurious.LCALTA.19
2103 08:26:36.117459 # ok 295 get_value.LCALTA.18
2104 08:26:36.117929 # # LCALTA.18 TDMOUT_A Lane 0 Volume
2105 08:26:36.123000 # ok 296 name.LCALTA.18
2106 08:26:36.123475 # ok 297 write_default.LCALTA.18
2107 08:26:36.128538 # ok 298 write_valid.LCALTA.18
2108 08:26:36.129009 # ok 299 write_invalid.LCALTA.18
2109 08:26:36.134063 # ok 300 event_missing.LCALTA.18
2110 08:26:36.134531 # ok 301 event_spurious.LCALTA.18
2111 08:26:36.139654 # ok 302 get_value.LCALTA.17
2112 08:26:36.145202 # # LCALTA.17 TDMOUT_B Gain Enable Switch
2113 08:26:36.145678 # ok 303 name.LCALTA.17
2114 08:26:36.150740 # ok 304 write_default.LCALTA.17
2115 08:26:36.151211 # ok 305 write_valid.LCALTA.17
2116 08:26:36.156286 # ok 306 write_invalid.LCALTA.17
2117 08:26:36.156761 # ok 307 event_missing.LCALTA.17
2118 08:26:36.161841 # ok 308 event_spurious.LCALTA.17
2119 08:26:36.162308 # ok 309 get_value.LCALTA.16
2120 08:26:36.167376 # # LCALTA.16 TDMOUT_B Lane 3 Volume
2121 08:26:36.167845 # ok 310 name.LCALTA.16
2122 08:26:36.172934 # ok 311 write_default.LCALTA.16
2123 08:26:36.173404 # ok 312 write_valid.LCALTA.16
2124 08:26:36.178469 # ok 313 write_invalid.LCALTA.16
2125 08:26:36.178940 # ok 314 event_missing.LCALTA.16
2126 08:26:36.184051 # ok 315 event_spurious.LCALTA.16
2127 08:26:36.184526 # ok 316 get_value.LCALTA.15
2128 08:26:36.189565 # # LCALTA.15 TDMOUT_B Lane 2 Volume
2129 08:26:36.190035 # ok 317 name.LCALTA.15
2130 08:26:36.195113 # ok 318 write_default.LCALTA.15
2131 08:26:36.195578 # ok 319 write_valid.LCALTA.15
2132 08:26:36.200659 # ok 320 write_invalid.LCALTA.15
2133 08:26:36.201136 # ok 321 event_missing.LCALTA.15
2134 08:26:36.206208 # ok 322 event_spurious.LCALTA.15
2135 08:26:36.206677 # ok 323 get_value.LCALTA.14
2136 08:26:36.211758 # # LCALTA.14 TDMOUT_B Lane 1 Volume
2137 08:26:36.212257 # ok 324 name.LCALTA.14
2138 08:26:36.217301 # ok 325 write_default.LCALTA.14
2139 08:26:36.217769 # ok 326 write_valid.LCALTA.14
2140 08:26:36.222853 # ok 327 write_invalid.LCALTA.14
2141 08:26:36.223318 # ok 328 event_missing.LCALTA.14
2142 08:26:36.228364 # ok 329 event_spurious.LCALTA.14
2143 08:26:36.228839 # ok 330 get_value.LCALTA.13
2144 08:26:36.233942 # # LCALTA.13 TDMOUT_B Lane 0 Volume
2145 08:26:36.234409 # ok 331 name.LCALTA.13
2146 08:26:36.239482 # ok 332 write_default.LCALTA.13
2147 08:26:36.239954 # ok 333 write_valid.LCALTA.13
2148 08:26:36.245035 # ok 334 write_invalid.LCALTA.13
2149 08:26:36.245508 # ok 335 event_missing.LCALTA.13
2150 08:26:36.250588 # ok 336 event_spurious.LCALTA.13
2151 08:26:36.251056 # ok 337 get_value.LCALTA.12
2152 08:26:36.256148 # # LCALTA.12 TDMOUT_C Gain Enable Switch
2153 08:26:36.261654 # ok 338 name.LCALTA.12
2154 08:26:36.262124 # ok 339 write_default.LCALTA.12
2155 08:26:36.267226 # ok 340 write_valid.LCALTA.12
2156 08:26:36.267695 # ok 341 write_invalid.LCALTA.12
2157 08:26:36.272745 # ok 342 event_missing.LCALTA.12
2158 08:26:36.273212 # ok 343 event_spurious.LCALTA.12
2159 08:26:36.278321 # ok 344 get_value.LCALTA.11
2160 08:26:36.278784 # # LCALTA.11 TDMOUT_C Lane 3 Volume
2161 08:26:36.283863 # ok 345 name.LCALTA.11
2162 08:26:36.284363 # ok 346 write_default.LCALTA.11
2163 08:26:36.289405 # ok 347 write_valid.LCALTA.11
2164 08:26:36.289873 # ok 348 write_invalid.LCALTA.11
2165 08:26:36.294946 # ok 349 event_missing.LCALTA.11
2166 08:26:36.295415 # ok 350 event_spurious.LCALTA.11
2167 08:26:36.300546 # ok 351 get_value.LCALTA.10
2168 08:26:36.301021 # # LCALTA.10 TDMOUT_C Lane 2 Volume
2169 08:26:36.306053 # ok 352 name.LCALTA.10
2170 08:26:36.306532 # ok 353 write_default.LCALTA.10
2171 08:26:36.311602 # ok 354 write_valid.LCALTA.10
2172 08:26:36.312113 # ok 355 write_invalid.LCALTA.10
2173 08:26:36.317143 # ok 356 event_missing.LCALTA.10
2174 08:26:36.317625 # ok 357 event_spurious.LCALTA.10
2175 08:26:36.322685 # ok 358 get_value.LCALTA.9
2176 08:26:36.323163 # # LCALTA.9 TDMOUT_C Lane 1 Volume
2177 08:26:36.328248 # ok 359 name.LCALTA.9
2178 08:26:36.328732 # ok 360 write_default.LCALTA.9
2179 08:26:36.333776 # ok 361 write_valid.LCALTA.9
2180 08:26:36.334263 # ok 362 write_invalid.LCALTA.9
2181 08:26:36.339338 # ok 363 event_missing.LCALTA.9
2182 08:26:36.339821 # ok 364 event_spurious.LCALTA.9
2183 08:26:36.344886 # ok 365 get_value.LCALTA.8
2184 08:26:36.345387 # # LCALTA.8 TDMOUT_C Lane 0 Volume
2185 08:26:36.350484 # ok 366 name.LCALTA.8
2186 08:26:36.350969 # ok 367 write_default.LCALTA.8
2187 08:26:36.355958 # ok 368 write_valid.LCALTA.8
2188 08:26:36.356463 # ok 369 write_invalid.LCALTA.8
2189 08:26:36.361549 # ok 370 event_missing.LCALTA.8
2190 08:26:36.362026 # ok 371 event_spurious.LCALTA.8
2191 08:26:36.367076 # ok 372 get_value.LCALTA.7
2192 08:26:36.367569 # # LCALTA.7 ACODEC Unmute Ramp Switch
2193 08:26:36.372615 # ok 373 name.LCALTA.7
2194 08:26:36.373100 # ok 374 write_default.LCALTA.7
2195 08:26:36.378153 # ok 375 write_valid.LCALTA.7
2196 08:26:36.378637 # ok 376 write_invalid.LCALTA.7
2197 08:26:36.383697 # ok 377 event_missing.LCALTA.7
2198 08:26:36.384198 # ok 378 event_spurious.LCALTA.7
2199 08:26:36.389250 # ok 379 get_value.LCALTA.6
2200 08:26:36.389719 # # LCALTA.6 ACODEC Mute Ramp Switch
2201 08:26:36.394801 # ok 380 name.LCALTA.6
2202 08:26:36.395343 # ok 381 write_default.LCALTA.6
2203 08:26:36.400352 # ok 382 write_valid.LCALTA.6
2204 08:26:36.400868 # ok 383 write_invalid.LCALTA.6
2205 08:26:36.405874 # ok 384 event_missing.LCALTA.6
2206 08:26:36.406331 # ok 385 event_spurious.LCALTA.6
2207 08:26:36.411499 # ok 386 get_value.LCALTA.5
2208 08:26:36.411945 # # LCALTA.5 ACODEC Volume Ramp Switch
2209 08:26:36.416981 # ok 387 name.LCALTA.5
2210 08:26:36.417430 # ok 388 write_default.LCALTA.5
2211 08:26:36.422524 # ok 389 write_valid.LCALTA.5
2212 08:26:36.422962 # ok 390 write_invalid.LCALTA.5
2213 08:26:36.428066 # ok 391 event_missing.LCALTA.5
2214 08:26:36.428503 # ok 392 event_spurious.LCALTA.5
2215 08:26:36.433665 # ok 393 get_value.LCALTA.4
2216 08:26:36.434105 # # LCALTA.4 ACODEC Ramp Rate
2217 08:26:36.439170 # ok 394 name.LCALTA.4
2218 08:26:36.439612 # ok 395 write_default.LCALTA.4
2219 08:26:36.444713 # ok 396 write_valid.LCALTA.4
2220 08:26:36.445154 # ok 397 write_invalid.LCALTA.4
2221 08:26:36.450262 # ok 398 event_missing.LCALTA.4
2222 08:26:36.450698 # ok 399 event_spurious.LCALTA.4
2223 08:26:36.455803 # ok 400 get_value.LCALTA.3
2224 08:26:36.456275 # # LCALTA.3 ACODEC Playback Volume
2225 08:26:36.461366 # ok 401 name.LCALTA.3
2226 08:26:36.461803 # ok 402 write_default.LCALTA.3
2227 08:26:36.466890 # ok 403 write_valid.LCALTA.3
2228 08:26:36.467329 # ok 404 write_invalid.LCALTA.3
2229 08:26:36.472502 # ok 405 event_missing.LCALTA.3
2230 08:26:36.472941 # ok 406 event_spurious.LCALTA.3
2231 08:26:36.477985 # ok 407 get_value.LCALTA.2
2232 08:26:36.478429 # # LCALTA.2 ACODEC Playback Switch
2233 08:26:36.483532 # ok 408 name.LCALTA.2
2234 08:26:36.483970 # ok 409 write_default.LCALTA.2
2235 08:26:36.489081 # ok 410 write_valid.LCALTA.2
2236 08:26:36.489530 # ok 411 write_invalid.LCALTA.2
2237 08:26:36.494634 # ok 412 event_missing.LCALTA.2
2238 08:26:36.495073 # ok 413 event_spurious.LCALTA.2
2239 08:26:36.500224 # ok 414 get_value.LCALTA.1
2240 08:26:36.500665 # # LCALTA.1 ACODEC Playback Channel Mode
2241 08:26:36.505722 # ok 415 name.LCALTA.1
2242 08:26:36.506162 # ok 416 write_default.LCALTA.1
2243 08:26:36.511266 # ok 417 write_valid.LCALTA.1
2244 08:26:36.511704 # ok 418 write_invalid.LCALTA.1
2245 08:26:36.516816 # ok 419 event_missing.LCALTA.1
2246 08:26:36.517262 # ok 420 event_spurious.LCALTA.1
2247 08:26:36.522376 # ok 421 get_value.LCALTA.0
2248 08:26:36.522824 # # LCALTA.0 TOACODEC Lane Select
2249 08:26:36.527899 # ok 422 name.LCALTA.0
2250 08:26:36.528371 # ok 423 write_default.LCALTA.0
2251 08:26:36.533508 # ok 424 write_valid.LCALTA.0
2252 08:26:36.533948 # ok 425 write_invalid.LCALTA.0
2253 08:26:36.538990 # ok 426 event_missing.LCALTA.0
2254 08:26:36.539426 # ok 427 event_spurious.LCALTA.0
2255 08:26:36.544560 # # Totals: pass:416 fail:0 xfail:0 xpass:0 skip:11 error:0
2256 08:26:36.550093 ok 1 selftests: alsa: mixer-test
2257 08:26:36.550536 # timeout set to 45
2258 08:26:36.550951 # selftests: alsa: pcm-test
2259 08:26:36.555634 # TAP version 13
2260 08:26:36.556102 # # Card 0/LCALTA - LC-ALTA (LC-ALTA)
2261 08:26:36.561178 # # LCALTA.0 - fe.dai-link-0 (*)
2262 08:26:36.561623 # # LCALTA.0 - fe.dai-link-1 (*)
2263 08:26:36.566711 # # LCALTA.0 - fe.dai-link-2 (*)
2264 08:26:36.567146 # # LCALTA.0 - fe.dai-link-3 (*)
2265 08:26:36.572270 # # LCALTA.0 - fe.dai-link-4 (*)
2266 08:26:36.572710 # # LCALTA.0 - fe.dai-link-5 (*)
2267 08:26:36.577831 # 1..42
2268 08:26:36.583380 # # default.time1.LCALTA.5.0.CAPTURE - 8kHz mono large periods
2269 08:26:36.583819 # ok 1 # SKIP default.time1.LCALTA.5.0.CAPTURE
2270 08:26:36.588921 # # snd_pcm_hw_params: Invalid argument
2271 08:26:36.594495 # # default.time2.LCALTA.5.0.CAPTURE - 8kHz stereo large periods
2272 08:26:36.600017 # ok 2 # SKIP default.time2.LCALTA.5.0.CAPTURE
2273 08:26:36.600458 # # snd_pcm_hw_params: Invalid argument
2274 08:26:36.611107 # # default.time3.LCALTA.5.0.CAPTURE - 44.1kHz stereo large periods
2275 08:26:36.611549 # ok 3 # SKIP default.time3.LCALTA.5.0.CAPTURE
2276 08:26:36.616644 # # snd_pcm_hw_params: Invalid argument
2277 08:26:36.622197 # # default.time4.LCALTA.5.0.CAPTURE - 48kHz stereo small periods
2278 08:26:36.627742 # ok 4 # SKIP default.time4.LCALTA.5.0.CAPTURE
2279 08:26:36.628220 # # snd_pcm_hw_params: Invalid argument
2280 08:26:36.633290 # # default.time5.LCALTA.5.0.CAPTURE - 48kHz stereo large periods
2281 08:26:36.638817 # ok 5 # SKIP default.time5.LCALTA.5.0.CAPTURE
2282 08:26:36.644401 # # snd_pcm_hw_params: Invalid argument
2283 08:26:36.649928 # # default.time6.LCALTA.5.0.CAPTURE - 48kHz 6 channel large periods
2284 08:26:36.655523 # ok 6 # SKIP default.time6.LCALTA.5.0.CAPTURE
2285 08:26:36.655960 # # snd_pcm_hw_params: Invalid argument
2286 08:26:36.661050 # # default.time7.LCALTA.5.0.CAPTURE - 96kHz stereo large periods
2287 08:26:36.666587 # ok 7 # SKIP default.time7.LCALTA.5.0.CAPTURE
2288 08:26:36.672137 # # snd_pcm_hw_params: Invalid argument
2289 08:26:36.677670 # # default.time1.LCALTA.4.0.CAPTURE - 8kHz mono large periods
2290 08:26:36.678169 # ok 8 # SKIP default.time1.LCALTA.4.0.CAPTURE
2291 08:26:36.683219 # # snd_pcm_hw_params: Invalid argument
2292 08:26:36.690274 # # default.time2.LCALTA.4.0.CAPTURE - 8kHz stereo large periods
2293 08:26:36.694534 # ok 9 # SKIP default.time2.LCALTA.4.0.CAPTURE
2294 08:26:36.699969 # # snd_pcm_hw_params: Invalid argument
2295 08:26:36.705499 # # default.time3.LCALTA.4.0.CAPTURE - 44.1kHz stereo large periods
2296 08:26:36.705991 # ok 10 # SKIP default.time3.LCALTA.4.0.CAPTURE
2297 08:26:36.711010 # # snd_pcm_hw_params: Invalid argument
2298 08:26:36.716583 # # default.time4.LCALTA.4.0.CAPTURE - 48kHz stereo small periods
2299 08:26:36.722058 # ok 11 # SKIP default.time4.LCALTA.4.0.CAPTURE
2300 08:26:36.722554 # # snd_pcm_hw_params: Invalid argument
2301 08:26:36.733186 # # default.time5.LCALTA.4.0.CAPTURE - 48kHz stereo large periods
2302 08:26:36.733684 # ok 12 # SKIP default.time5.LCALTA.4.0.CAPTURE
2303 08:26:36.738765 # # snd_pcm_hw_params: Invalid argument
2304 08:26:36.744267 # # default.time6.LCALTA.4.0.CAPTURE - 48kHz 6 channel large periods
2305 08:26:36.749808 # ok 13 # SKIP default.time6.LCALTA.4.0.CAPTURE
2306 08:26:36.750301 # # snd_pcm_hw_params: Invalid argument
2307 08:26:36.755351 # # default.time7.LCALTA.4.0.CAPTURE - 96kHz stereo large periods
2308 08:26:36.760937 # ok 14 # SKIP default.time7.LCALTA.4.0.CAPTURE
2309 08:26:36.766428 # # snd_pcm_hw_params: Invalid argument
2310 08:26:36.771951 # # default.time1.LCALTA.3.0.CAPTURE - 8kHz mono large periods
2311 08:26:36.777603 # ok 15 # SKIP default.time1.LCALTA.3.0.CAPTURE
2312 08:26:36.778090 # # snd_pcm_hw_params: Invalid argument
2313 08:26:36.783064 # # default.time2.LCALTA.3.0.CAPTURE - 8kHz stereo large periods
2314 08:26:36.788655 # ok 16 # SKIP default.time2.LCALTA.3.0.CAPTURE
2315 08:26:36.794203 # # snd_pcm_hw_params: Invalid argument
2316 08:26:36.799713 # # default.time3.LCALTA.3.0.CAPTURE - 44.1kHz stereo large periods
2317 08:26:36.805217 # ok 17 # SKIP default.time3.LCALTA.3.0.CAPTURE
2318 08:26:36.805708 # # snd_pcm_hw_params: Invalid argument
2319 08:26:36.810858 # # default.time4.LCALTA.3.0.CAPTURE - 48kHz stereo small periods
2320 08:26:36.816338 # ok 18 # SKIP default.time4.LCALTA.3.0.CAPTURE
2321 08:26:36.821897 # # snd_pcm_hw_params: Invalid argument
2322 08:26:36.827463 # # default.time5.LCALTA.3.0.CAPTURE - 48kHz stereo large periods
2323 08:26:36.827959 # ok 19 # SKIP default.time5.LCALTA.3.0.CAPTURE
2324 08:26:36.832986 # # snd_pcm_hw_params: Invalid argument
2325 08:26:36.838603 # # default.time6.LCALTA.3.0.CAPTURE - 48kHz 6 channel large periods
2326 08:26:36.844085 # ok 20 # SKIP default.time6.LCALTA.3.0.CAPTURE
2327 08:26:36.849666 # # snd_pcm_hw_params: Invalid argument
2328 08:26:36.855203 # # default.time7.LCALTA.3.0.CAPTURE - 96kHz stereo large periods
2329 08:26:36.855658 # ok 21 # SKIP default.time7.LCALTA.3.0.CAPTURE
2330 08:26:36.860710 # # snd_pcm_hw_params: Invalid argument
2331 08:26:36.866364 # # default.time1.LCALTA.2.0.PLAYBACK - 8kHz mono large periods
2332 08:26:36.871899 # ok 22 # SKIP default.time1.LCALTA.2.0.PLAYBACK
2333 08:26:36.872397 # # snd_pcm_hw_params: Invalid argument
2334 08:26:36.882899 # # default.time2.LCALTA.2.0.PLAYBACK - 8kHz stereo large periods
2335 08:26:36.883360 # ok 23 # SKIP default.time2.LCALTA.2.0.PLAYBACK
2336 08:26:36.888454 # # snd_pcm_hw_params: Invalid argument
2337 08:26:36.894000 # # default.time3.LCALTA.2.0.PLAYBACK - 44.1kHz stereo large periods
2338 08:26:36.899655 # ok 24 # SKIP default.time3.LCALTA.2.0.PLAYBACK
2339 08:26:36.900255 # # snd_pcm_hw_params: Invalid argument
2340 08:26:36.910613 # # default.time4.LCALTA.2.0.PLAYBACK - 48kHz stereo small periods
2341 08:26:36.911140 # ok 25 # SKIP default.time4.LCALTA.2.0.PLAYBACK
2342 08:26:36.916202 # # snd_pcm_hw_params: Invalid argument
2343 08:26:36.921720 # # default.time5.LCALTA.2.0.PLAYBACK - 48kHz stereo large periods
2344 08:26:36.927270 # ok 26 # SKIP default.time5.LCALTA.2.0.PLAYBACK
2345 08:26:36.927733 # # snd_pcm_hw_params: Invalid argument
2346 08:26:36.938349 # # default.time6.LCALTA.2.0.PLAYBACK - 48kHz 6 channel large periods
2347 08:26:36.938804 # ok 27 # SKIP default.time6.LCALTA.2.0.PLAYBACK
2348 08:26:36.943893 # # snd_pcm_hw_params: Invalid argument
2349 08:26:36.949435 # # default.time7.LCALTA.2.0.PLAYBACK - 96kHz stereo large periods
2350 08:26:36.955005 # ok 28 # SKIP default.time7.LCALTA.2.0.PLAYBACK
2351 08:26:36.955460 # # snd_pcm_hw_params: Invalid argument
2352 08:26:36.960603 # # default.time1.LCALTA.1.0.PLAYBACK - 8kHz mono large periods
2353 08:26:36.966090 # ok 29 # SKIP default.time1.LCALTA.1.0.PLAYBACK
2354 08:26:36.971642 # # snd_pcm_hw_params: Invalid argument
2355 08:26:36.977196 # # default.time2.LCALTA.1.0.PLAYBACK - 8kHz stereo large periods
2356 08:26:36.982770 # ok 30 # SKIP default.time2.LCALTA.1.0.PLAYBACK
2357 08:26:36.983213 # # snd_pcm_hw_params: Invalid argument
2358 08:26:36.988286 # # default.time3.LCALTA.1.0.PLAYBACK - 44.1kHz stereo large periods
2359 08:26:36.993835 # ok 31 # SKIP default.time3.LCALTA.1.0.PLAYBACK
2360 08:26:36.999356 # # snd_pcm_hw_params: Invalid argument
2361 08:26:37.004924 # # default.time4.LCALTA.1.0.PLAYBACK - 48kHz stereo small periods
2362 08:26:37.010458 # ok 32 # SKIP default.time4.LCALTA.1.0.PLAYBACK
2363 08:26:37.010911 # # snd_pcm_hw_params: Invalid argument
2364 08:26:37.016046 # # default.time5.LCALTA.1.0.PLAYBACK - 48kHz stereo large periods
2365 08:26:37.021615 # ok 33 # SKIP default.time5.LCALTA.1.0.PLAYBACK
2366 08:26:37.027118 # # snd_pcm_hw_params: Invalid argument
2367 08:26:37.032660 # # default.time6.LCALTA.1.0.PLAYBACK - 48kHz 6 channel large periods
2368 08:26:37.038217 # ok 34 # SKIP default.time6.LCALTA.1.0.PLAYBACK
2369 08:26:37.038676 # # snd_pcm_hw_params: Invalid argument
2370 08:26:37.043753 # # default.time7.LCALTA.1.0.PLAYBACK - 96kHz stereo large periods
2371 08:26:37.049293 # ok 35 # SKIP default.time7.LCALTA.1.0.PLAYBACK
2372 08:26:37.054828 # # snd_pcm_hw_params: Invalid argument
2373 08:26:37.060389 # # default.time1.LCALTA.0.0.PLAYBACK - 8kHz mono large periods
2374 08:26:37.065916 # ok 36 # SKIP default.time1.LCALTA.0.0.PLAYBACK
2375 08:26:37.066365 # # snd_pcm_hw_params: Invalid argument
2376 08:26:37.071464 # # default.time2.LCALTA.0.0.PLAYBACK - 8kHz stereo large periods
2377 08:26:37.077027 # ok 37 # SKIP default.time2.LCALTA.0.0.PLAYBACK
2378 08:26:37.082621 # # snd_pcm_hw_params: Invalid argument
2379 08:26:37.088145 # # default.time3.LCALTA.0.0.PLAYBACK - 44.1kHz stereo large periods
2380 08:26:37.093674 # ok 38 # SKIP default.time3.LCALTA.0.0.PLAYBACK
2381 08:26:37.094125 # # snd_pcm_hw_params: Invalid argument
2382 08:26:37.099214 # # default.time4.LCALTA.0.0.PLAYBACK - 48kHz stereo small periods
2383 08:26:37.104786 # ok 39 # SKIP default.time4.LCALTA.0.0.PLAYBACK
2384 08:26:37.110349 # # snd_pcm_hw_params: Invalid argument
2385 08:26:37.115824 # # default.time5.LCALTA.0.0.PLAYBACK - 48kHz stereo large periods
2386 08:26:37.121398 # ok 40 # SKIP default.time5.LCALTA.0.0.PLAYBACK
2387 08:26:37.121851 # # snd_pcm_hw_params: Invalid argument
2388 08:26:37.126960 # # default.time6.LCALTA.0.0.PLAYBACK - 48kHz 6 channel large periods
2389 08:26:37.132488 # ok 41 # SKIP default.time6.LCALTA.0.0.PLAYBACK
2390 08:26:37.138013 # # snd_pcm_hw_params: Invalid argument
2391 08:26:37.143626 # # default.time7.LCALTA.0.0.PLAYBACK - 96kHz stereo large periods
2392 08:26:37.149141 # ok 42 # SKIP default.time7.LCALTA.0.0.PLAYBACK
2393 08:26:37.149588 # # snd_pcm_hw_params: Invalid argument
2394 08:26:37.154661 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:42 error:0
2395 08:26:37.160225 ok 2 selftests: alsa: pcm-test
2396 08:26:37.160680 # timeout set to 45
2397 08:26:37.165790 # selftests: alsa: test-pcmtest-driver
2398 08:26:37.166237 # TAP version 13
2399 08:26:37.166650 # 1..5
2400 08:26:37.171350 # # Starting 5 tests from 1 test cases.
2401 08:26:37.171809 # # RUN pcmtest.playback ...
2402 08:26:37.176879 # # SKIP Can't read patterns. Probably, module isn't loaded
2403 08:26:37.182398 # # OK pcmtest.playback
2404 08:26:37.187941 # ok 1 pcmtest.playback # SKIP Can't read patterns. Probably, module isn't loaded
2405 08:26:37.193518 # # RUN pcmtest.capture ...
2406 08:26:37.199053 # # SKIP Can't read patterns. Probably, module isn't loaded
2407 08:26:37.204634 # # OK pcmtest.capture
2408 08:26:37.210153 # ok 2 pcmtest.capture # SKIP Can't read patterns. Probably, module isn't loaded
2409 08:26:37.215679 # # RUN pcmtest.ni_capture ...
2410 08:26:37.221240 # # SKIP Can't read patterns. Probably, module isn't loaded
2411 08:26:37.221704 # # OK pcmtest.ni_capture
2412 08:26:37.232357 # ok 3 pcmtest.ni_capture # SKIP Can't read patterns. Probably, module isn't loaded
2413 08:26:37.232825 # # RUN pcmtest.ni_playback ...
2414 08:26:37.237894 # # SKIP Can't read patterns. Probably, module isn't loaded
2415 08:26:37.243420 # # OK pcmtest.ni_playback
2416 08:26:37.248974 # ok 4 pcmtest.ni_playback # SKIP Can't read patterns. Probably, module isn't loaded
2417 08:26:37.254505 # # RUN pcmtest.reset_ioctl ...
2418 08:26:37.260166 # # SKIP Can't read patterns. Probably, module isn't loaded
2419 08:26:37.265683 # # OK pcmtest.reset_ioctl
2420 08:26:37.271150 # ok 5 pcmtest.reset_ioctl # SKIP Can't read patterns. Probably, module isn't loaded
2421 08:26:37.276713 # # PASSED: 5 / 5 tests passed.
2422 08:26:37.282304 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:5 error:0
2423 08:26:37.282770 ok 3 selftests: alsa: test-pcmtest-driver
2424 08:26:37.287792 # timeout set to 45
2425 08:26:37.288278 # selftests: alsa: utimer-test
2426 08:26:37.288697 # TAP version 13
2427 08:26:37.289100 # 1..2
2428 08:26:37.293347 # # Starting 2 tests from 2 test cases.
2429 08:26:37.298913 # # RUN global.wrong_timers_test ...
2430 08:26:37.304503 # # OK global.wrong_timers_test
2431 08:26:37.305036 # ok 1 global.wrong_timers_test
2432 08:26:37.310065 # # RUN timer_f.utimer ...
2433 08:26:37.321119 # # utimer-test.c:55:utimer:Expected ioctl(timer_dev_fd, SNDRV_TIMER_IOCTL_CREATE, self->utimer_info) (-1) == 0 (0)
2434 08:26:37.321598 # # utimer: Test terminated by assertion
2435 08:26:37.326627 # # FAIL timer_f.utimer
2436 08:26:37.327098 # not ok 2 timer_f.utimer
2437 08:26:37.332212 # # FAILED: 1 / 2 tests passed.
2438 08:26:37.339956 # # Totals: pass:1 fail:1 xfail:0 xpass:0 skip:0 error:0
2439 08:26:37.340472 not ok 4 selftests: alsa: utimer-test # exit=1
2440 08:26:37.868327 alsa_mixer-test_get_value_LCALTA_60 pass
2441 08:26:37.873663 alsa_mixer-test_name_LCALTA_60 pass
2442 08:26:37.874142 alsa_mixer-test_write_default_LCALTA_60 pass
2443 08:26:37.879201 alsa_mixer-test_write_valid_LCALTA_60 pass
2444 08:26:37.884749 alsa_mixer-test_write_invalid_LCALTA_60 pass
2445 08:26:37.890284 alsa_mixer-test_event_missing_LCALTA_60 pass
2446 08:26:37.890746 alsa_mixer-test_event_spurious_LCALTA_60 pass
2447 08:26:37.895833 alsa_mixer-test_get_value_LCALTA_59 pass
2448 08:26:37.901402 alsa_mixer-test_name_LCALTA_59 pass
2449 08:26:37.901855 alsa_mixer-test_write_default_LCALTA_59 pass
2450 08:26:37.906979 alsa_mixer-test_write_valid_LCALTA_59 pass
2451 08:26:37.912482 alsa_mixer-test_write_invalid_LCALTA_59 pass
2452 08:26:37.912971 alsa_mixer-test_event_missing_LCALTA_59 pass
2453 08:26:37.918024 alsa_mixer-test_event_spurious_LCALTA_59 pass
2454 08:26:37.923568 alsa_mixer-test_get_value_LCALTA_58 pass
2455 08:26:37.924052 alsa_mixer-test_name_LCALTA_58 pass
2456 08:26:37.929105 alsa_mixer-test_write_default_LCALTA_58 pass
2457 08:26:37.934655 alsa_mixer-test_write_valid_LCALTA_58 pass
2458 08:26:37.935109 alsa_mixer-test_write_invalid_LCALTA_58 pass
2459 08:26:37.940203 alsa_mixer-test_event_missing_LCALTA_58 pass
2460 08:26:37.945735 alsa_mixer-test_event_spurious_LCALTA_58 pass
2461 08:26:37.951310 alsa_mixer-test_get_value_LCALTA_57 pass
2462 08:26:37.951768 alsa_mixer-test_name_LCALTA_57 pass
2463 08:26:37.956905 alsa_mixer-test_write_default_LCALTA_57 pass
2464 08:26:37.962473 alsa_mixer-test_write_valid_LCALTA_57 pass
2465 08:26:37.962922 alsa_mixer-test_write_invalid_LCALTA_57 pass
2466 08:26:37.968021 alsa_mixer-test_event_missing_LCALTA_57 pass
2467 08:26:37.973547 alsa_mixer-test_event_spurious_LCALTA_57 pass
2468 08:26:37.973994 alsa_mixer-test_get_value_LCALTA_56 pass
2469 08:26:37.979088 alsa_mixer-test_name_LCALTA_56 pass
2470 08:26:37.984645 alsa_mixer-test_write_default_LCALTA_56 pass
2471 08:26:37.985095 alsa_mixer-test_write_valid_LCALTA_56 pass
2472 08:26:37.990185 alsa_mixer-test_write_invalid_LCALTA_56 pass
2473 08:26:37.995740 alsa_mixer-test_event_missing_LCALTA_56 pass
2474 08:26:38.001284 alsa_mixer-test_event_spurious_LCALTA_56 pass
2475 08:26:38.001729 alsa_mixer-test_get_value_LCALTA_55 pass
2476 08:26:38.006851 alsa_mixer-test_name_LCALTA_55 pass
2477 08:26:38.012379 alsa_mixer-test_write_default_LCALTA_55 pass
2478 08:26:38.012851 alsa_mixer-test_write_valid_LCALTA_55 pass
2479 08:26:38.017922 alsa_mixer-test_write_invalid_LCALTA_55 pass
2480 08:26:38.023478 alsa_mixer-test_event_missing_LCALTA_55 pass
2481 08:26:38.023928 alsa_mixer-test_event_spurious_LCALTA_55 pass
2482 08:26:38.029011 alsa_mixer-test_get_value_LCALTA_54 pass
2483 08:26:38.034553 alsa_mixer-test_name_LCALTA_54 pass
2484 08:26:38.034997 alsa_mixer-test_write_default_LCALTA_54 pass
2485 08:26:38.040104 alsa_mixer-test_write_valid_LCALTA_54 pass
2486 08:26:38.045754 alsa_mixer-test_write_invalid_LCALTA_54 pass
2487 08:26:38.046202 alsa_mixer-test_event_missing_LCALTA_54 pass
2488 08:26:38.051195 alsa_mixer-test_event_spurious_LCALTA_54 pass
2489 08:26:38.056750 alsa_mixer-test_get_value_LCALTA_53 pass
2490 08:26:38.057203 alsa_mixer-test_name_LCALTA_53 pass
2491 08:26:38.062250 alsa_mixer-test_write_default_LCALTA_53 pass
2492 08:26:38.067818 alsa_mixer-test_write_valid_LCALTA_53 pass
2493 08:26:38.073374 alsa_mixer-test_write_invalid_LCALTA_53 pass
2494 08:26:38.073818 alsa_mixer-test_event_missing_LCALTA_53 pass
2495 08:26:38.078934 alsa_mixer-test_event_spurious_LCALTA_53 pass
2496 08:26:38.084482 alsa_mixer-test_get_value_LCALTA_52 pass
2497 08:26:38.084931 alsa_mixer-test_name_LCALTA_52 pass
2498 08:26:38.090021 alsa_mixer-test_write_default_LCALTA_52 pass
2499 08:26:38.095574 alsa_mixer-test_write_valid_LCALTA_52 pass
2500 08:26:38.096052 alsa_mixer-test_write_invalid_LCALTA_52 pass
2501 08:26:38.101108 alsa_mixer-test_event_missing_LCALTA_52 pass
2502 08:26:38.106787 alsa_mixer-test_event_spurious_LCALTA_52 pass
2503 08:26:38.107295 alsa_mixer-test_get_value_LCALTA_51 pass
2504 08:26:38.112260 alsa_mixer-test_name_LCALTA_51 pass
2505 08:26:38.117764 alsa_mixer-test_write_default_LCALTA_51 pass
2506 08:26:38.118239 alsa_mixer-test_write_valid_LCALTA_51 pass
2507 08:26:38.123309 alsa_mixer-test_write_invalid_LCALTA_51 pass
2508 08:26:38.128862 alsa_mixer-test_event_missing_LCALTA_51 pass
2509 08:26:38.134380 alsa_mixer-test_event_spurious_LCALTA_51 pass
2510 08:26:38.134824 alsa_mixer-test_get_value_LCALTA_50 pass
2511 08:26:38.139948 alsa_mixer-test_name_LCALTA_50 pass
2512 08:26:38.145487 alsa_mixer-test_write_default_LCALTA_50 pass
2513 08:26:38.145936 alsa_mixer-test_write_valid_LCALTA_50 pass
2514 08:26:38.151034 alsa_mixer-test_write_invalid_LCALTA_50 pass
2515 08:26:38.156652 alsa_mixer-test_event_missing_LCALTA_50 pass
2516 08:26:38.157103 alsa_mixer-test_event_spurious_LCALTA_50 pass
2517 08:26:38.162216 alsa_mixer-test_get_value_LCALTA_49 pass
2518 08:26:38.167777 alsa_mixer-test_name_LCALTA_49 pass
2519 08:26:38.168254 alsa_mixer-test_write_default_LCALTA_49 pass
2520 08:26:38.173240 alsa_mixer-test_write_valid_LCALTA_49 pass
2521 08:26:38.178829 alsa_mixer-test_write_invalid_LCALTA_49 pass
2522 08:26:38.184324 alsa_mixer-test_event_missing_LCALTA_49 pass
2523 08:26:38.184776 alsa_mixer-test_event_spurious_LCALTA_49 pass
2524 08:26:38.189870 alsa_mixer-test_get_value_LCALTA_48 pass
2525 08:26:38.190317 alsa_mixer-test_name_LCALTA_48 pass
2526 08:26:38.195414 alsa_mixer-test_write_default_LCALTA_48 pass
2527 08:26:38.200956 alsa_mixer-test_write_valid_LCALTA_48 pass
2528 08:26:38.206531 alsa_mixer-test_write_invalid_LCALTA_48 pass
2529 08:26:38.207034 alsa_mixer-test_event_missing_LCALTA_48 pass
2530 08:26:38.212073 alsa_mixer-test_event_spurious_LCALTA_48 pass
2531 08:26:38.217612 alsa_mixer-test_get_value_LCALTA_47 pass
2532 08:26:38.218069 alsa_mixer-test_name_LCALTA_47 pass
2533 08:26:38.223152 alsa_mixer-test_write_default_LCALTA_47 pass
2534 08:26:38.228776 alsa_mixer-test_write_valid_LCALTA_47 pass
2535 08:26:38.229234 alsa_mixer-test_write_invalid_LCALTA_47 pass
2536 08:26:38.234238 alsa_mixer-test_event_missing_LCALTA_47 pass
2537 08:26:38.239775 alsa_mixer-test_event_spurious_LCALTA_47 pass
2538 08:26:38.245338 alsa_mixer-test_get_value_LCALTA_46 pass
2539 08:26:38.245788 alsa_mixer-test_name_LCALTA_46 pass
2540 08:26:38.250879 alsa_mixer-test_write_default_LCALTA_46 pass
2541 08:26:38.256433 alsa_mixer-test_write_valid_LCALTA_46 pass
2542 08:26:38.256889 alsa_mixer-test_write_invalid_LCALTA_46 pass
2543 08:26:38.261942 alsa_mixer-test_event_missing_LCALTA_46 pass
2544 08:26:38.267493 alsa_mixer-test_event_spurious_LCALTA_46 pass
2545 08:26:38.267934 alsa_mixer-test_get_value_LCALTA_45 pass
2546 08:26:38.273073 alsa_mixer-test_name_LCALTA_45 pass
2547 08:26:38.278634 alsa_mixer-test_write_default_LCALTA_45 pass
2548 08:26:38.279077 alsa_mixer-test_write_valid_LCALTA_45 pass
2549 08:26:38.284209 alsa_mixer-test_write_invalid_LCALTA_45 pass
2550 08:26:38.289757 alsa_mixer-test_event_missing_LCALTA_45 pass
2551 08:26:38.290202 alsa_mixer-test_event_spurious_LCALTA_45 pass
2552 08:26:38.295261 alsa_mixer-test_get_value_LCALTA_44 pass
2553 08:26:38.300813 alsa_mixer-test_name_LCALTA_44 pass
2554 08:26:38.301262 alsa_mixer-test_write_default_LCALTA_44 pass
2555 08:26:38.306379 alsa_mixer-test_write_valid_LCALTA_44 pass
2556 08:26:38.311894 alsa_mixer-test_write_invalid_LCALTA_44 pass
2557 08:26:38.317446 alsa_mixer-test_event_missing_LCALTA_44 pass
2558 08:26:38.317903 alsa_mixer-test_event_spurious_LCALTA_44 pass
2559 08:26:38.323004 alsa_mixer-test_get_value_LCALTA_43 pass
2560 08:26:38.328532 alsa_mixer-test_name_LCALTA_43 pass
2561 08:26:38.328997 alsa_mixer-test_write_default_LCALTA_43 pass
2562 08:26:38.334075 alsa_mixer-test_write_valid_LCALTA_43 pass
2563 08:26:38.339674 alsa_mixer-test_write_invalid_LCALTA_43 pass
2564 08:26:38.340195 alsa_mixer-test_event_missing_LCALTA_43 pass
2565 08:26:38.345166 alsa_mixer-test_event_spurious_LCALTA_43 pass
2566 08:26:38.350797 alsa_mixer-test_get_value_LCALTA_42 pass
2567 08:26:38.351268 alsa_mixer-test_name_LCALTA_42 pass
2568 08:26:38.356287 alsa_mixer-test_write_default_LCALTA_42 pass
2569 08:26:38.361957 alsa_mixer-test_write_valid_LCALTA_42 pass
2570 08:26:38.362448 alsa_mixer-test_write_invalid_LCALTA_42 pass
2571 08:26:38.367436 alsa_mixer-test_event_missing_LCALTA_42 pass
2572 08:26:38.372990 alsa_mixer-test_event_spurious_LCALTA_42 pass
2573 08:26:38.378458 alsa_mixer-test_get_value_LCALTA_41 pass
2574 08:26:38.378907 alsa_mixer-test_name_LCALTA_41 pass
2575 08:26:38.384069 alsa_mixer-test_write_default_LCALTA_41 pass
2576 08:26:38.389561 alsa_mixer-test_write_valid_LCALTA_41 pass
2577 08:26:38.390044 alsa_mixer-test_write_invalid_LCALTA_41 pass
2578 08:26:38.395089 alsa_mixer-test_event_missing_LCALTA_41 pass
2579 08:26:38.400638 alsa_mixer-test_event_spurious_LCALTA_41 pass
2580 08:26:38.401086 alsa_mixer-test_get_value_LCALTA_40 pass
2581 08:26:38.406195 alsa_mixer-test_name_LCALTA_40 pass
2582 08:26:38.411774 alsa_mixer-test_write_default_LCALTA_40 pass
2583 08:26:38.412291 alsa_mixer-test_write_valid_LCALTA_40 pass
2584 08:26:38.417271 alsa_mixer-test_write_invalid_LCALTA_40 pass
2585 08:26:38.422810 alsa_mixer-test_event_missing_LCALTA_40 pass
2586 08:26:38.428354 alsa_mixer-test_event_spurious_LCALTA_40 pass
2587 08:26:38.428800 alsa_mixer-test_get_value_LCALTA_39 pass
2588 08:26:38.433937 alsa_mixer-test_name_LCALTA_39 pass
2589 08:26:38.439448 alsa_mixer-test_write_default_LCALTA_39 pass
2590 08:26:38.439892 alsa_mixer-test_write_valid_LCALTA_39 pass
2591 08:26:38.445014 alsa_mixer-test_write_invalid_LCALTA_39 pass
2592 08:26:38.450558 alsa_mixer-test_event_missing_LCALTA_39 pass
2593 08:26:38.451011 alsa_mixer-test_event_spurious_LCALTA_39 pass
2594 08:26:38.456100 alsa_mixer-test_get_value_LCALTA_38 pass
2595 08:26:38.461659 alsa_mixer-test_name_LCALTA_38 pass
2596 08:26:38.462105 alsa_mixer-test_write_default_LCALTA_38 pass
2597 08:26:38.467196 alsa_mixer-test_write_valid_LCALTA_38 pass
2598 08:26:38.472781 alsa_mixer-test_write_invalid_LCALTA_38 pass
2599 08:26:38.473229 alsa_mixer-test_event_missing_LCALTA_38 pass
2600 08:26:38.478288 alsa_mixer-test_event_spurious_LCALTA_38 pass
2601 08:26:38.483823 alsa_mixer-test_get_value_LCALTA_37 pass
2602 08:26:38.484298 alsa_mixer-test_name_LCALTA_37 pass
2603 08:26:38.489346 alsa_mixer-test_write_default_LCALTA_37 pass
2604 08:26:38.494879 alsa_mixer-test_write_valid_LCALTA_37 pass
2605 08:26:38.500483 alsa_mixer-test_write_invalid_LCALTA_37 pass
2606 08:26:38.500940 alsa_mixer-test_event_missing_LCALTA_37 pass
2607 08:26:38.506045 alsa_mixer-test_event_spurious_LCALTA_37 pass
2608 08:26:38.511562 alsa_mixer-test_get_value_LCALTA_36 pass
2609 08:26:38.512051 alsa_mixer-test_name_LCALTA_36 pass
2610 08:26:38.517112 alsa_mixer-test_write_default_LCALTA_36 pass
2611 08:26:38.522663 alsa_mixer-test_write_valid_LCALTA_36 pass
2612 08:26:38.523105 alsa_mixer-test_write_invalid_LCALTA_36 pass
2613 08:26:38.528213 alsa_mixer-test_event_missing_LCALTA_36 pass
2614 08:26:38.533788 alsa_mixer-test_event_spurious_LCALTA_36 pass
2615 08:26:38.534234 alsa_mixer-test_get_value_LCALTA_35 pass
2616 08:26:38.539304 alsa_mixer-test_name_LCALTA_35 pass
2617 08:26:38.544820 alsa_mixer-test_write_default_LCALTA_35 pass
2618 08:26:38.545266 alsa_mixer-test_write_valid_LCALTA_35 pass
2619 08:26:38.550393 alsa_mixer-test_write_invalid_LCALTA_35 pass
2620 08:26:38.555937 alsa_mixer-test_event_missing_LCALTA_35 pass
2621 08:26:38.561489 alsa_mixer-test_event_spurious_LCALTA_35 pass
2622 08:26:38.561939 alsa_mixer-test_get_value_LCALTA_34 pass
2623 08:26:38.567012 alsa_mixer-test_name_LCALTA_34 pass
2624 08:26:38.572559 alsa_mixer-test_write_default_LCALTA_34 pass
2625 08:26:38.573004 alsa_mixer-test_write_valid_LCALTA_34 pass
2626 08:26:38.578136 alsa_mixer-test_write_invalid_LCALTA_34 pass
2627 08:26:38.583680 alsa_mixer-test_event_missing_LCALTA_34 pass
2628 08:26:38.584153 alsa_mixer-test_event_spurious_LCALTA_34 pass
2629 08:26:38.589221 alsa_mixer-test_get_value_LCALTA_33 pass
2630 08:26:38.594769 alsa_mixer-test_name_LCALTA_33 pass
2631 08:26:38.595214 alsa_mixer-test_write_default_LCALTA_33 pass
2632 08:26:38.600306 alsa_mixer-test_write_valid_LCALTA_33 pass
2633 08:26:38.605853 alsa_mixer-test_write_invalid_LCALTA_33 pass
2634 08:26:38.611430 alsa_mixer-test_event_missing_LCALTA_33 pass
2635 08:26:38.611940 alsa_mixer-test_event_spurious_LCALTA_33 pass
2636 08:26:38.616951 alsa_mixer-test_get_value_LCALTA_32 pass
2637 08:26:38.617416 alsa_mixer-test_name_LCALTA_32 pass
2638 08:26:38.622497 alsa_mixer-test_write_default_LCALTA_32 pass
2639 08:26:38.628071 alsa_mixer-test_write_valid_LCALTA_32 pass
2640 08:26:38.633575 alsa_mixer-test_write_invalid_LCALTA_32 pass
2641 08:26:38.634024 alsa_mixer-test_event_missing_LCALTA_32 pass
2642 08:26:38.639162 alsa_mixer-test_event_spurious_LCALTA_32 pass
2643 08:26:38.644769 alsa_mixer-test_get_value_LCALTA_31 pass
2644 08:26:38.645218 alsa_mixer-test_name_LCALTA_31 pass
2645 08:26:38.650303 alsa_mixer-test_write_default_LCALTA_31 pass
2646 08:26:38.655828 alsa_mixer-test_write_valid_LCALTA_31 pass
2647 08:26:38.656315 alsa_mixer-test_write_invalid_LCALTA_31 pass
2648 08:26:38.661338 alsa_mixer-test_event_missing_LCALTA_31 pass
2649 08:26:38.666876 alsa_mixer-test_event_spurious_LCALTA_31 pass
2650 08:26:38.672427 alsa_mixer-test_get_value_LCALTA_30 pass
2651 08:26:38.672870 alsa_mixer-test_name_LCALTA_30 pass
2652 08:26:38.677976 alsa_mixer-test_write_default_LCALTA_30 pass
2653 08:26:38.683524 alsa_mixer-test_write_valid_LCALTA_30 pass
2654 08:26:38.683973 alsa_mixer-test_write_invalid_LCALTA_30 pass
2655 08:26:38.689071 alsa_mixer-test_event_missing_LCALTA_30 pass
2656 08:26:38.694594 alsa_mixer-test_event_spurious_LCALTA_30 pass
2657 08:26:38.695040 alsa_mixer-test_get_value_LCALTA_29 pass
2658 08:26:38.700184 alsa_mixer-test_name_LCALTA_29 pass
2659 08:26:38.705789 alsa_mixer-test_write_default_LCALTA_29 pass
2660 08:26:38.706229 alsa_mixer-test_write_valid_LCALTA_29 pass
2661 08:26:38.711288 alsa_mixer-test_write_invalid_LCALTA_29 pass
2662 08:26:38.716887 alsa_mixer-test_event_missing_LCALTA_29 pass
2663 08:26:38.717343 alsa_mixer-test_event_spurious_LCALTA_29 pass
2664 08:26:38.722347 alsa_mixer-test_get_value_LCALTA_28 pass
2665 08:26:38.727887 alsa_mixer-test_name_LCALTA_28 pass
2666 08:26:38.728367 alsa_mixer-test_write_default_LCALTA_28 pass
2667 08:26:38.733439 alsa_mixer-test_write_valid_LCALTA_28 pass
2668 08:26:38.738959 alsa_mixer-test_write_invalid_LCALTA_28 pass
2669 08:26:38.744531 alsa_mixer-test_event_missing_LCALTA_28 pass
2670 08:26:38.744976 alsa_mixer-test_event_spurious_LCALTA_28 pass
2671 08:26:38.750077 alsa_mixer-test_get_value_LCALTA_27 pass
2672 08:26:38.755621 alsa_mixer-test_name_LCALTA_27 pass
2673 08:26:38.756096 alsa_mixer-test_write_default_LCALTA_27 pass
2674 08:26:38.761186 alsa_mixer-test_write_valid_LCALTA_27 pass
2675 08:26:38.766699 alsa_mixer-test_write_invalid_LCALTA_27 pass
2676 08:26:38.767157 alsa_mixer-test_event_missing_LCALTA_27 pass
2677 08:26:38.772257 alsa_mixer-test_event_spurious_LCALTA_27 pass
2678 08:26:38.777829 alsa_mixer-test_get_value_LCALTA_26 pass
2679 08:26:38.778271 alsa_mixer-test_name_LCALTA_26 pass
2680 08:26:38.783356 alsa_mixer-test_write_default_LCALTA_26 skip
2681 08:26:38.788906 alsa_mixer-test_write_valid_LCALTA_26 skip
2682 08:26:38.789350 alsa_mixer-test_write_invalid_LCALTA_26 skip
2683 08:26:38.794438 alsa_mixer-test_event_missing_LCALTA_26 pass
2684 08:26:38.799976 alsa_mixer-test_event_spurious_LCALTA_26 pass
2685 08:26:38.805540 alsa_mixer-test_get_value_LCALTA_25 pass
2686 08:26:38.805984 alsa_mixer-test_name_LCALTA_25 pass
2687 08:26:38.811108 alsa_mixer-test_write_default_LCALTA_25 pass
2688 08:26:38.816650 alsa_mixer-test_write_valid_LCALTA_25 skip
2689 08:26:38.817120 alsa_mixer-test_write_invalid_LCALTA_25 skip
2690 08:26:38.822200 alsa_mixer-test_event_missing_LCALTA_25 pass
2691 08:26:38.827750 alsa_mixer-test_event_spurious_LCALTA_25 pass
2692 08:26:38.828229 alsa_mixer-test_get_value_LCALTA_24 pass
2693 08:26:38.833282 alsa_mixer-test_name_LCALTA_24 pass
2694 08:26:38.838834 alsa_mixer-test_write_default_LCALTA_24 skip
2695 08:26:38.839279 alsa_mixer-test_write_valid_LCALTA_24 skip
2696 08:26:38.844372 alsa_mixer-test_write_invalid_LCALTA_24 skip
2697 08:26:38.849916 alsa_mixer-test_event_missing_LCALTA_24 pass
2698 08:26:38.855503 alsa_mixer-test_event_spurious_LCALTA_24 pass
2699 08:26:38.855944 alsa_mixer-test_get_value_LCALTA_23 pass
2700 08:26:38.861017 alsa_mixer-test_name_LCALTA_23 pass
2701 08:26:38.866571 alsa_mixer-test_write_default_LCALTA_23 skip
2702 08:26:38.867022 alsa_mixer-test_write_valid_LCALTA_23 skip
2703 08:26:38.872104 alsa_mixer-test_write_invalid_LCALTA_23 skip
2704 08:26:38.877646 alsa_mixer-test_event_missing_LCALTA_23 pass
2705 08:26:38.878084 alsa_mixer-test_event_spurious_LCALTA_23 pass
2706 08:26:38.883174 alsa_mixer-test_get_value_LCALTA_22 pass
2707 08:26:38.888739 alsa_mixer-test_name_LCALTA_22 pass
2708 08:26:38.889190 alsa_mixer-test_write_default_LCALTA_22 pass
2709 08:26:38.894278 alsa_mixer-test_write_valid_LCALTA_22 pass
2710 08:26:38.899828 alsa_mixer-test_write_invalid_LCALTA_22 pass
2711 08:26:38.900292 alsa_mixer-test_event_missing_LCALTA_22 pass
2712 08:26:38.905370 alsa_mixer-test_event_spurious_LCALTA_22 pass
2713 08:26:38.910979 alsa_mixer-test_get_value_LCALTA_21 pass
2714 08:26:38.911507 alsa_mixer-test_name_LCALTA_21 pass
2715 08:26:38.916486 alsa_mixer-test_write_default_LCALTA_21 pass
2716 08:26:38.922022 alsa_mixer-test_write_valid_LCALTA_21 pass
2717 08:26:38.927581 alsa_mixer-test_write_invalid_LCALTA_21 pass
2718 08:26:38.928065 alsa_mixer-test_event_missing_LCALTA_21 pass
2719 08:26:38.933115 alsa_mixer-test_event_spurious_LCALTA_21 pass
2720 08:26:38.938638 alsa_mixer-test_get_value_LCALTA_20 pass
2721 08:26:38.939081 alsa_mixer-test_name_LCALTA_20 pass
2722 08:26:38.944197 alsa_mixer-test_write_default_LCALTA_20 pass
2723 08:26:38.949748 alsa_mixer-test_write_valid_LCALTA_20 pass
2724 08:26:38.950214 alsa_mixer-test_write_invalid_LCALTA_20 pass
2725 08:26:38.955308 alsa_mixer-test_event_missing_LCALTA_20 pass
2726 08:26:38.960852 alsa_mixer-test_event_spurious_LCALTA_20 pass
2727 08:26:38.961304 alsa_mixer-test_get_value_LCALTA_19 pass
2728 08:26:38.966398 alsa_mixer-test_name_LCALTA_19 pass
2729 08:26:38.971935 alsa_mixer-test_write_default_LCALTA_19 pass
2730 08:26:38.972411 alsa_mixer-test_write_valid_LCALTA_19 pass
2731 08:26:38.977463 alsa_mixer-test_write_invalid_LCALTA_19 pass
2732 08:26:38.983041 alsa_mixer-test_event_missing_LCALTA_19 pass
2733 08:26:38.988590 alsa_mixer-test_event_spurious_LCALTA_19 pass
2734 08:26:38.989053 alsa_mixer-test_get_value_LCALTA_18 pass
2735 08:26:38.994117 alsa_mixer-test_name_LCALTA_18 pass
2736 08:26:38.999660 alsa_mixer-test_write_default_LCALTA_18 pass
2737 08:26:39.000153 alsa_mixer-test_write_valid_LCALTA_18 pass
2738 08:26:39.005212 alsa_mixer-test_write_invalid_LCALTA_18 pass
2739 08:26:39.010807 alsa_mixer-test_event_missing_LCALTA_18 pass
2740 08:26:39.011316 alsa_mixer-test_event_spurious_LCALTA_18 pass
2741 08:26:39.016307 alsa_mixer-test_get_value_LCALTA_17 pass
2742 08:26:39.021862 alsa_mixer-test_name_LCALTA_17 pass
2743 08:26:39.022325 alsa_mixer-test_write_default_LCALTA_17 pass
2744 08:26:39.027388 alsa_mixer-test_write_valid_LCALTA_17 pass
2745 08:26:39.032951 alsa_mixer-test_write_invalid_LCALTA_17 pass
2746 08:26:39.038496 alsa_mixer-test_event_missing_LCALTA_17 pass
2747 08:26:39.038943 alsa_mixer-test_event_spurious_LCALTA_17 pass
2748 08:26:39.044072 alsa_mixer-test_get_value_LCALTA_16 pass
2749 08:26:39.044523 alsa_mixer-test_name_LCALTA_16 pass
2750 08:26:39.049609 alsa_mixer-test_write_default_LCALTA_16 pass
2751 08:26:39.055139 alsa_mixer-test_write_valid_LCALTA_16 pass
2752 08:26:39.060688 alsa_mixer-test_write_invalid_LCALTA_16 pass
2753 08:26:39.061132 alsa_mixer-test_event_missing_LCALTA_16 pass
2754 08:26:39.066242 alsa_mixer-test_event_spurious_LCALTA_16 pass
2755 08:26:39.071769 alsa_mixer-test_get_value_LCALTA_15 pass
2756 08:26:39.072245 alsa_mixer-test_name_LCALTA_15 pass
2757 08:26:39.077312 alsa_mixer-test_write_default_LCALTA_15 pass
2758 08:26:39.082867 alsa_mixer-test_write_valid_LCALTA_15 pass
2759 08:26:39.083310 alsa_mixer-test_write_invalid_LCALTA_15 pass
2760 08:26:39.088412 alsa_mixer-test_event_missing_LCALTA_15 pass
2761 08:26:39.093965 alsa_mixer-test_event_spurious_LCALTA_15 pass
2762 08:26:39.099509 alsa_mixer-test_get_value_LCALTA_14 pass
2763 08:26:39.099942 alsa_mixer-test_name_LCALTA_14 pass
2764 08:26:39.105077 alsa_mixer-test_write_default_LCALTA_14 pass
2765 08:26:39.110630 alsa_mixer-test_write_valid_LCALTA_14 pass
2766 08:26:39.111099 alsa_mixer-test_write_invalid_LCALTA_14 pass
2767 08:26:39.116197 alsa_mixer-test_event_missing_LCALTA_14 pass
2768 08:26:39.121708 alsa_mixer-test_event_spurious_LCALTA_14 pass
2769 08:26:39.122162 alsa_mixer-test_get_value_LCALTA_13 pass
2770 08:26:39.127255 alsa_mixer-test_name_LCALTA_13 pass
2771 08:26:39.132799 alsa_mixer-test_write_default_LCALTA_13 pass
2772 08:26:39.133266 alsa_mixer-test_write_valid_LCALTA_13 pass
2773 08:26:39.138324 alsa_mixer-test_write_invalid_LCALTA_13 pass
2774 08:26:39.143919 alsa_mixer-test_event_missing_LCALTA_13 pass
2775 08:26:39.144459 alsa_mixer-test_event_spurious_LCALTA_13 pass
2776 08:26:39.149440 alsa_mixer-test_get_value_LCALTA_12 pass
2777 08:26:39.154984 alsa_mixer-test_name_LCALTA_12 pass
2778 08:26:39.155444 alsa_mixer-test_write_default_LCALTA_12 pass
2779 08:26:39.160532 alsa_mixer-test_write_valid_LCALTA_12 pass
2780 08:26:39.166075 alsa_mixer-test_write_invalid_LCALTA_12 pass
2781 08:26:39.171630 alsa_mixer-test_event_missing_LCALTA_12 pass
2782 08:26:39.172114 alsa_mixer-test_event_spurious_LCALTA_12 pass
2783 08:26:39.177141 alsa_mixer-test_get_value_LCALTA_11 pass
2784 08:26:39.182722 alsa_mixer-test_name_LCALTA_11 pass
2785 08:26:39.183185 alsa_mixer-test_write_default_LCALTA_11 pass
2786 08:26:39.188259 alsa_mixer-test_write_valid_LCALTA_11 pass
2787 08:26:39.193906 alsa_mixer-test_write_invalid_LCALTA_11 pass
2788 08:26:39.194357 alsa_mixer-test_event_missing_LCALTA_11 pass
2789 08:26:39.199367 alsa_mixer-test_event_spurious_LCALTA_11 pass
2790 08:26:39.204942 alsa_mixer-test_get_value_LCALTA_10 pass
2791 08:26:39.205392 alsa_mixer-test_name_LCALTA_10 pass
2792 08:26:39.210452 alsa_mixer-test_write_default_LCALTA_10 pass
2793 08:26:39.216019 alsa_mixer-test_write_valid_LCALTA_10 pass
2794 08:26:39.216470 alsa_mixer-test_write_invalid_LCALTA_10 pass
2795 08:26:39.221533 alsa_mixer-test_event_missing_LCALTA_10 pass
2796 08:26:39.227087 alsa_mixer-test_event_spurious_LCALTA_10 pass
2797 08:26:39.232637 alsa_mixer-test_get_value_LCALTA_9 pass
2798 08:26:39.233079 alsa_mixer-test_name_LCALTA_9 pass
2799 08:26:39.238153 alsa_mixer-test_write_default_LCALTA_9 pass
2800 08:26:39.243720 alsa_mixer-test_write_valid_LCALTA_9 pass
2801 08:26:39.244212 alsa_mixer-test_write_invalid_LCALTA_9 pass
2802 08:26:39.249272 alsa_mixer-test_event_missing_LCALTA_9 pass
2803 08:26:39.254908 alsa_mixer-test_event_spurious_LCALTA_9 pass
2804 08:26:39.255349 alsa_mixer-test_get_value_LCALTA_8 pass
2805 08:26:39.260370 alsa_mixer-test_name_LCALTA_8 pass
2806 08:26:39.265922 alsa_mixer-test_write_default_LCALTA_8 pass
2807 08:26:39.266366 alsa_mixer-test_write_valid_LCALTA_8 pass
2808 08:26:39.271463 alsa_mixer-test_write_invalid_LCALTA_8 pass
2809 08:26:39.277053 alsa_mixer-test_event_missing_LCALTA_8 pass
2810 08:26:39.277505 alsa_mixer-test_event_spurious_LCALTA_8 pass
2811 08:26:39.282549 alsa_mixer-test_get_value_LCALTA_7 pass
2812 08:26:39.288103 alsa_mixer-test_name_LCALTA_7 pass
2813 08:26:39.288548 alsa_mixer-test_write_default_LCALTA_7 pass
2814 08:26:39.293633 alsa_mixer-test_write_valid_LCALTA_7 pass
2815 08:26:39.299196 alsa_mixer-test_write_invalid_LCALTA_7 pass
2816 08:26:39.299638 alsa_mixer-test_event_missing_LCALTA_7 pass
2817 08:26:39.304737 alsa_mixer-test_event_spurious_LCALTA_7 pass
2818 08:26:39.310275 alsa_mixer-test_get_value_LCALTA_6 pass
2819 08:26:39.310725 alsa_mixer-test_name_LCALTA_6 pass
2820 08:26:39.315912 alsa_mixer-test_write_default_LCALTA_6 pass
2821 08:26:39.321376 alsa_mixer-test_write_valid_LCALTA_6 pass
2822 08:26:39.321828 alsa_mixer-test_write_invalid_LCALTA_6 pass
2823 08:26:39.326950 alsa_mixer-test_event_missing_LCALTA_6 pass
2824 08:26:39.332471 alsa_mixer-test_event_spurious_LCALTA_6 pass
2825 08:26:39.332927 alsa_mixer-test_get_value_LCALTA_5 pass
2826 08:26:39.338021 alsa_mixer-test_name_LCALTA_5 pass
2827 08:26:39.343572 alsa_mixer-test_write_default_LCALTA_5 pass
2828 08:26:39.344078 alsa_mixer-test_write_valid_LCALTA_5 pass
2829 08:26:39.349126 alsa_mixer-test_write_invalid_LCALTA_5 pass
2830 08:26:39.354661 alsa_mixer-test_event_missing_LCALTA_5 pass
2831 08:26:39.355120 alsa_mixer-test_event_spurious_LCALTA_5 pass
2832 08:26:39.360213 alsa_mixer-test_get_value_LCALTA_4 pass
2833 08:26:39.365762 alsa_mixer-test_name_LCALTA_4 pass
2834 08:26:39.366222 alsa_mixer-test_write_default_LCALTA_4 pass
2835 08:26:39.371299 alsa_mixer-test_write_valid_LCALTA_4 pass
2836 08:26:39.376925 alsa_mixer-test_write_invalid_LCALTA_4 pass
2837 08:26:39.377383 alsa_mixer-test_event_missing_LCALTA_4 pass
2838 08:26:39.382398 alsa_mixer-test_event_spurious_LCALTA_4 pass
2839 08:26:39.387930 alsa_mixer-test_get_value_LCALTA_3 pass
2840 08:26:39.388414 alsa_mixer-test_name_LCALTA_3 pass
2841 08:26:39.393477 alsa_mixer-test_write_default_LCALTA_3 pass
2842 08:26:39.399031 alsa_mixer-test_write_valid_LCALTA_3 pass
2843 08:26:39.399490 alsa_mixer-test_write_invalid_LCALTA_3 pass
2844 08:26:39.404558 alsa_mixer-test_event_missing_LCALTA_3 pass
2845 08:26:39.410102 alsa_mixer-test_event_spurious_LCALTA_3 pass
2846 08:26:39.410567 alsa_mixer-test_get_value_LCALTA_2 pass
2847 08:26:39.415675 alsa_mixer-test_name_LCALTA_2 pass
2848 08:26:39.421205 alsa_mixer-test_write_default_LCALTA_2 pass
2849 08:26:39.421684 alsa_mixer-test_write_valid_LCALTA_2 pass
2850 08:26:39.426740 alsa_mixer-test_write_invalid_LCALTA_2 pass
2851 08:26:39.432306 alsa_mixer-test_event_missing_LCALTA_2 pass
2852 08:26:39.437931 alsa_mixer-test_event_spurious_LCALTA_2 pass
2853 08:26:39.438380 alsa_mixer-test_get_value_LCALTA_1 pass
2854 08:26:39.443395 alsa_mixer-test_name_LCALTA_1 pass
2855 08:26:39.443843 alsa_mixer-test_write_default_LCALTA_1 pass
2856 08:26:39.448947 alsa_mixer-test_write_valid_LCALTA_1 pass
2857 08:26:39.454484 alsa_mixer-test_write_invalid_LCALTA_1 pass
2858 08:26:39.460023 alsa_mixer-test_event_missing_LCALTA_1 pass
2859 08:26:39.460469 alsa_mixer-test_event_spurious_LCALTA_1 pass
2860 08:26:39.465598 alsa_mixer-test_get_value_LCALTA_0 pass
2861 08:26:39.466061 alsa_mixer-test_name_LCALTA_0 pass
2862 08:26:39.471135 alsa_mixer-test_write_default_LCALTA_0 pass
2863 08:26:39.476674 alsa_mixer-test_write_valid_LCALTA_0 pass
2864 08:26:39.482226 alsa_mixer-test_write_invalid_LCALTA_0 pass
2865 08:26:39.482677 alsa_mixer-test_event_missing_LCALTA_0 pass
2866 08:26:39.487783 alsa_mixer-test_event_spurious_LCALTA_0 pass
2867 08:26:39.488280 alsa_mixer-test pass
2868 08:26:39.493310 alsa_pcm-test_default_time1_LCALTA_5_0_CAPTURE skip
2869 08:26:39.498930 alsa_pcm-test_default_time2_LCALTA_5_0_CAPTURE skip
2870 08:26:39.504410 alsa_pcm-test_default_time3_LCALTA_5_0_CAPTURE skip
2871 08:26:39.509970 alsa_pcm-test_default_time4_LCALTA_5_0_CAPTURE skip
2872 08:26:39.510427 alsa_pcm-test_default_time5_LCALTA_5_0_CAPTURE skip
2873 08:26:39.515480 alsa_pcm-test_default_time6_LCALTA_5_0_CAPTURE skip
2874 08:26:39.521051 alsa_pcm-test_default_time7_LCALTA_5_0_CAPTURE skip
2875 08:26:39.526595 alsa_pcm-test_default_time1_LCALTA_4_0_CAPTURE skip
2876 08:26:39.532185 alsa_pcm-test_default_time2_LCALTA_4_0_CAPTURE skip
2877 08:26:39.537684 alsa_pcm-test_default_time3_LCALTA_4_0_CAPTURE skip
2878 08:26:39.538134 alsa_pcm-test_default_time4_LCALTA_4_0_CAPTURE skip
2879 08:26:39.543309 alsa_pcm-test_default_time5_LCALTA_4_0_CAPTURE skip
2880 08:26:39.548808 alsa_pcm-test_default_time6_LCALTA_4_0_CAPTURE skip
2881 08:26:39.554336 alsa_pcm-test_default_time7_LCALTA_4_0_CAPTURE skip
2882 08:26:39.559917 alsa_pcm-test_default_time1_LCALTA_3_0_CAPTURE skip
2883 08:26:39.565431 alsa_pcm-test_default_time2_LCALTA_3_0_CAPTURE skip
2884 08:26:39.565922 alsa_pcm-test_default_time3_LCALTA_3_0_CAPTURE skip
2885 08:26:39.570960 alsa_pcm-test_default_time4_LCALTA_3_0_CAPTURE skip
2886 08:26:39.576499 alsa_pcm-test_default_time5_LCALTA_3_0_CAPTURE skip
2887 08:26:39.582096 alsa_pcm-test_default_time6_LCALTA_3_0_CAPTURE skip
2888 08:26:39.587612 alsa_pcm-test_default_time7_LCALTA_3_0_CAPTURE skip
2889 08:26:39.593172 alsa_pcm-test_default_time1_LCALTA_2_0_PLAYBACK skip
2890 08:26:39.593647 alsa_pcm-test_default_time2_LCALTA_2_0_PLAYBACK skip
2891 08:26:39.598693 alsa_pcm-test_default_time3_LCALTA_2_0_PLAYBACK skip
2892 08:26:39.604264 alsa_pcm-test_default_time4_LCALTA_2_0_PLAYBACK skip
2893 08:26:39.609822 alsa_pcm-test_default_time5_LCALTA_2_0_PLAYBACK skip
2894 08:26:39.615346 alsa_pcm-test_default_time6_LCALTA_2_0_PLAYBACK skip
2895 08:26:39.620914 alsa_pcm-test_default_time7_LCALTA_2_0_PLAYBACK skip
2896 08:26:39.621379 alsa_pcm-test_default_time1_LCALTA_1_0_PLAYBACK skip
2897 08:26:39.626443 alsa_pcm-test_default_time2_LCALTA_1_0_PLAYBACK skip
2898 08:26:39.632008 alsa_pcm-test_default_time3_LCALTA_1_0_PLAYBACK skip
2899 08:26:39.637545 alsa_pcm-test_default_time4_LCALTA_1_0_PLAYBACK skip
2900 08:26:39.643071 alsa_pcm-test_default_time5_LCALTA_1_0_PLAYBACK skip
2901 08:26:39.648633 alsa_pcm-test_default_time6_LCALTA_1_0_PLAYBACK skip
2902 08:26:39.654168 alsa_pcm-test_default_time7_LCALTA_1_0_PLAYBACK skip
2903 08:26:39.654640 alsa_pcm-test_default_time1_LCALTA_0_0_PLAYBACK skip
2904 08:26:39.659712 alsa_pcm-test_default_time2_LCALTA_0_0_PLAYBACK skip
2905 08:26:39.665240 alsa_pcm-test_default_time3_LCALTA_0_0_PLAYBACK skip
2906 08:26:39.670789 alsa_pcm-test_default_time4_LCALTA_0_0_PLAYBACK skip
2907 08:26:39.676340 alsa_pcm-test_default_time5_LCALTA_0_0_PLAYBACK skip
2908 08:26:39.681947 alsa_pcm-test_default_time6_LCALTA_0_0_PLAYBACK skip
2909 08:26:39.682410 alsa_pcm-test_default_time7_LCALTA_0_0_PLAYBACK skip
2910 08:26:39.687453 alsa_pcm-test pass
2911 08:26:39.693003 alsa_test-pcmtest-driver_pcmtest_playback_Can_t_read_patterns_Probably_module_isn_t_loaded skip
2912 08:26:39.704099 alsa_test-pcmtest-driver_pcmtest_capture_Can_t_read_patterns_Probably_module_isn_t_loaded skip
2913 08:26:39.709642 alsa_test-pcmtest-driver_pcmtest_ni_capture_Can_t_read_patterns_Probably_module_isn_t_loaded skip
2914 08:26:39.720725 alsa_test-pcmtest-driver_pcmtest_ni_playback_Can_t_read_patterns_Probably_module_isn_t_loaded skip
2915 08:26:39.726264 alsa_test-pcmtest-driver_pcmtest_reset_ioctl_Can_t_read_patterns_Probably_module_isn_t_loaded skip
2916 08:26:39.731898 alsa_test-pcmtest-driver pass
2917 08:26:39.737387 alsa_utimer-test_global_wrong_timers_test pass
2918 08:26:39.737851 alsa_utimer-test_timer_f_utimer fail
2919 08:26:39.742947 alsa_utimer-test fail
2920 08:26:39.743402 + ../../utils/send-to-lava.sh ./output/result.txt
2921 08:26:39.748449 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-alsa RESULT=pass>
2922 08:26:39.749348 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-alsa RESULT=pass
2924 08:26:39.759569 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_60 RESULT=pass>
2925 08:26:39.760337 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_60 RESULT=pass
2927 08:26:39.765324 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_60 RESULT=pass>
2928 08:26:39.766034 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_60 RESULT=pass
2930 08:26:39.787531 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_60 RESULT=pass>
2931 08:26:39.788286 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_60 RESULT=pass
2933 08:26:39.838295 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_60 RESULT=pass>
2934 08:26:39.839103 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_60 RESULT=pass
2936 08:26:39.889091 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_60 RESULT=pass>
2937 08:26:39.889793 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_60 RESULT=pass
2939 08:26:39.933377 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_60 RESULT=pass>
2940 08:26:39.934070 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_60 RESULT=pass
2942 08:26:39.987337 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_60 RESULT=pass>
2943 08:26:39.988068 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_60 RESULT=pass
2945 08:26:40.037060 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_59 RESULT=pass>
2946 08:26:40.037762 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_59 RESULT=pass
2948 08:26:40.088383 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_59 RESULT=pass>
2949 08:26:40.089187 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_59 RESULT=pass
2951 08:26:40.139072 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_59 RESULT=pass>
2952 08:26:40.139790 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_59 RESULT=pass
2954 08:26:40.189575 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_59 RESULT=pass>
2955 08:26:40.190299 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_59 RESULT=pass
2957 08:26:40.242893 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_59 RESULT=pass>
2958 08:26:40.243604 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_59 RESULT=pass
2960 08:26:40.296752 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_59 RESULT=pass>
2961 08:26:40.297474 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_59 RESULT=pass
2963 08:26:40.351575 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_59 RESULT=pass>
2964 08:26:40.352372 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_59 RESULT=pass
2966 08:26:40.405458 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_58 RESULT=pass>
2967 08:26:40.406193 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_58 RESULT=pass
2969 08:26:40.449307 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_58 RESULT=pass>
2970 08:26:40.450028 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_58 RESULT=pass
2972 08:26:40.495152 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_58 RESULT=pass>
2973 08:26:40.495887 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_58 RESULT=pass
2975 08:26:40.540971 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_58 RESULT=pass>
2976 08:26:40.541698 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_58 RESULT=pass
2978 08:26:40.597881 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_58 RESULT=pass>
2979 08:26:40.598588 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_58 RESULT=pass
2981 08:26:40.642800 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_58 RESULT=pass>
2982 08:26:40.643503 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_58 RESULT=pass
2984 08:26:40.692960 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_58 RESULT=pass>
2985 08:26:40.693689 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_58 RESULT=pass
2987 08:26:40.745095 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_57 RESULT=pass>
2988 08:26:40.745797 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_57 RESULT=pass
2990 08:26:40.796842 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_57 RESULT=pass>
2991 08:26:40.797541 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_57 RESULT=pass
2993 08:26:40.848687 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_57 RESULT=pass>
2994 08:26:40.849408 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_57 RESULT=pass
2996 08:26:40.899946 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_57 RESULT=pass>
2997 08:26:40.900747 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_57 RESULT=pass
2999 08:26:40.947628 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_57 RESULT=pass>
3000 08:26:40.948412 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_57 RESULT=pass
3002 08:26:41.002523 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_57 RESULT=pass>
3003 08:26:41.003245 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_57 RESULT=pass
3005 08:26:41.049820 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_57 RESULT=pass>
3006 08:26:41.050569 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_57 RESULT=pass
3008 08:26:41.104732 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_56 RESULT=pass>
3009 08:26:41.105436 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_56 RESULT=pass
3011 08:26:41.149162 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_56 RESULT=pass>
3012 08:26:41.149913 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_56 RESULT=pass
3014 08:26:41.206384 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_56 RESULT=pass>
3015 08:26:41.207096 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_56 RESULT=pass
3017 08:26:41.255570 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_56 RESULT=pass>
3018 08:26:41.256305 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_56 RESULT=pass
3020 08:26:41.309183 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_56 RESULT=pass>
3021 08:26:41.309903 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_56 RESULT=pass
3023 08:26:41.360569 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_56 RESULT=pass>
3024 08:26:41.361308 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_56 RESULT=pass
3026 08:26:41.412840 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_56 RESULT=pass>
3027 08:26:41.413562 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_56 RESULT=pass
3029 08:26:41.465542 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_55 RESULT=pass>
3030 08:26:41.466282 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_55 RESULT=pass
3032 08:26:41.510026 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_55 RESULT=pass>
3033 08:26:41.510786 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_55 RESULT=pass
3035 08:26:41.557448 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_55 RESULT=pass>
3036 08:26:41.558178 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_55 RESULT=pass
3038 08:26:41.605092 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_55 RESULT=pass>
3039 08:26:41.605798 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_55 RESULT=pass
3041 08:26:41.650552 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_55 RESULT=pass>
3042 08:26:41.651251 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_55 RESULT=pass
3044 08:26:41.696175 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_55 RESULT=pass>
3045 08:26:41.696876 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_55 RESULT=pass
3047 08:26:41.748062 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_55 RESULT=pass>
3048 08:26:41.748759 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_55 RESULT=pass
3050 08:26:41.805268 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_54 RESULT=pass>
3051 08:26:41.805964 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_54 RESULT=pass
3053 08:26:41.856035 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_54 RESULT=pass>
3054 08:26:41.856771 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_54 RESULT=pass
3056 08:26:41.905772 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_54 RESULT=pass>
3057 08:26:41.906462 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_54 RESULT=pass
3059 08:26:41.960494 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_54 RESULT=pass>
3060 08:26:41.961200 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_54 RESULT=pass
3062 08:26:42.006662 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_54 RESULT=pass>
3063 08:26:42.007360 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_54 RESULT=pass
3065 08:26:42.059620 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_54 RESULT=pass>
3066 08:26:42.060379 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_54 RESULT=pass
3068 08:26:42.109575 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_54 RESULT=pass>
3069 08:26:42.110272 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_54 RESULT=pass
3071 08:26:42.160282 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_53 RESULT=pass>
3072 08:26:42.161021 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_53 RESULT=pass
3074 08:26:42.204635 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_53 RESULT=pass>
3075 08:26:42.205340 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_53 RESULT=pass
3077 08:26:42.253214 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_53 RESULT=pass>
3078 08:26:42.253991 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_53 RESULT=pass
3080 08:26:42.299730 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_53 RESULT=pass>
3081 08:26:42.300526 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_53 RESULT=pass
3083 08:26:42.356711 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_53 RESULT=pass>
3084 08:26:42.357560 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_53 RESULT=pass
3086 08:26:42.404067 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_53 RESULT=pass>
3087 08:26:42.404810 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_53 RESULT=pass
3089 08:26:42.457336 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_53 RESULT=pass>
3090 08:26:42.458069 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_53 RESULT=pass
3092 08:26:42.511616 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_52 RESULT=pass>
3093 08:26:42.512377 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_52 RESULT=pass
3095 08:26:42.557420 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_52 RESULT=pass>
3096 08:26:42.558124 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_52 RESULT=pass
3098 08:26:42.604145 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_52 RESULT=pass>
3099 08:26:42.604846 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_52 RESULT=pass
3101 08:26:42.651084 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_52 RESULT=pass>
3102 08:26:42.651803 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_52 RESULT=pass
3104 08:26:42.699425 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_52 RESULT=pass>
3105 08:26:42.700124 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_52 RESULT=pass
3107 08:26:42.752516 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_52 RESULT=pass>
3108 08:26:42.753209 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_52 RESULT=pass
3110 08:26:42.805692 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_52 RESULT=pass>
3111 08:26:42.806385 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_52 RESULT=pass
3113 08:26:42.858005 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_51 RESULT=pass>
3114 08:26:42.858747 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_51 RESULT=pass
3116 08:26:42.910609 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_51 RESULT=pass>
3117 08:26:42.911315 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_51 RESULT=pass
3119 08:26:42.956065 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_51 RESULT=pass>
3120 08:26:42.956772 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_51 RESULT=pass
3122 08:26:43.012585 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_51 RESULT=pass>
3123 08:26:43.013291 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_51 RESULT=pass
3125 08:26:43.061294 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_51 RESULT=pass>
3126 08:26:43.062011 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_51 RESULT=pass
3128 08:26:43.119253 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_51 RESULT=pass>
3129 08:26:43.119950 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_51 RESULT=pass
3131 08:26:43.173591 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_51 RESULT=pass>
3132 08:26:43.174334 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_51 RESULT=pass
3134 08:26:43.224480 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_50 RESULT=pass>
3135 08:26:43.225182 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_50 RESULT=pass
3137 08:26:43.272656 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_50 RESULT=pass>
3138 08:26:43.273354 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_50 RESULT=pass
3140 08:26:43.329078 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_50 RESULT=pass>
3141 08:26:43.329809 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_50 RESULT=pass
3143 08:26:43.375043 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_50 RESULT=pass>
3144 08:26:43.375773 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_50 RESULT=pass
3146 08:26:43.432380 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_50 RESULT=pass>
3147 08:26:43.433105 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_50 RESULT=pass
3149 08:26:43.477419 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_50 RESULT=pass>
3150 08:26:43.478139 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_50 RESULT=pass
3152 08:26:43.539391 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_50 RESULT=pass>
3153 08:26:43.540091 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_50 RESULT=pass
3155 08:26:43.594562 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_49 RESULT=pass>
3156 08:26:43.595275 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_49 RESULT=pass
3158 08:26:43.646779 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_49 RESULT=pass>
3159 08:26:43.647483 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_49 RESULT=pass
3161 08:26:43.702917 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_49 RESULT=pass>
3162 08:26:43.703615 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_49 RESULT=pass
3164 08:26:43.748342 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_49 RESULT=pass>
3165 08:26:43.749027 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_49 RESULT=pass
3167 08:26:43.795930 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_49 RESULT=pass>
3168 08:26:43.796710 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_49 RESULT=pass
3170 08:26:43.840332 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_49 RESULT=pass>
3171 08:26:43.841022 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_49 RESULT=pass
3173 08:26:43.892929 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_49 RESULT=pass>
3174 08:26:43.893615 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_49 RESULT=pass
3176 08:26:43.943977 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_48 RESULT=pass>
3177 08:26:43.944722 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_48 RESULT=pass
3179 08:26:43.994732 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_48 RESULT=pass>
3180 08:26:43.995434 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_48 RESULT=pass
3182 08:26:44.039165 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_48 RESULT=pass>
3183 08:26:44.039882 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_48 RESULT=pass
3185 08:26:44.092202 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_48 RESULT=pass>
3186 08:26:44.092901 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_48 RESULT=pass
3188 08:26:44.142794 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_48 RESULT=pass>
3189 08:26:44.143492 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_48 RESULT=pass
3191 08:26:44.192758 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_48 RESULT=pass>
3192 08:26:44.193458 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_48 RESULT=pass
3194 08:26:44.237548 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_48 RESULT=pass>
3195 08:26:44.238234 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_48 RESULT=pass
3197 08:26:44.297660 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_47 RESULT=pass>
3198 08:26:44.298343 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_47 RESULT=pass
3200 08:26:44.349551 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_47 RESULT=pass>
3201 08:26:44.350290 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_47 RESULT=pass
3203 08:26:44.394794 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_47 RESULT=pass>
3204 08:26:44.395510 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_47 RESULT=pass
3206 08:26:44.440810 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_47 RESULT=pass>
3207 08:26:44.441539 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_47 RESULT=pass
3209 08:26:44.487824 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_47 RESULT=pass>
3210 08:26:44.488577 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_47 RESULT=pass
3212 08:26:44.532398 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_47 RESULT=pass>
3213 08:26:44.533100 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_47 RESULT=pass
3215 08:26:44.588547 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_47 RESULT=pass>
3216 08:26:44.589246 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_47 RESULT=pass
3218 08:26:44.633816 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_46 RESULT=pass>
3219 08:26:44.634507 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_46 RESULT=pass
3221 08:26:44.684874 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_46 RESULT=pass>
3222 08:26:44.685570 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_46 RESULT=pass
3224 08:26:44.732168 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_46 RESULT=pass>
3225 08:26:44.732875 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_46 RESULT=pass
3227 08:26:44.778360 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_46 RESULT=pass>
3228 08:26:44.779056 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_46 RESULT=pass
3230 08:26:44.832275 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_46 RESULT=pass>
3231 08:26:44.832977 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_46 RESULT=pass
3233 08:26:44.876862 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_46 RESULT=pass>
3234 08:26:44.877615 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_46 RESULT=pass
3236 08:26:44.928171 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_46 RESULT=pass>
3237 08:26:44.928915 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_46 RESULT=pass
3239 08:26:44.971617 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_45 RESULT=pass>
3240 08:26:44.972333 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_45 RESULT=pass
3242 08:26:45.026497 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_45 RESULT=pass>
3243 08:26:45.027324 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_45 RESULT=pass
3245 08:26:45.072265 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_45 RESULT=pass>
3246 08:26:45.073074 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_45 RESULT=pass
3248 08:26:45.129715 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_45 RESULT=pass>
3249 08:26:45.130510 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_45 RESULT=pass
3251 08:26:45.173969 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_45 RESULT=pass>
3252 08:26:45.174733 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_45 RESULT=pass
3254 08:26:45.241058 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_45 RESULT=pass>
3255 08:26:45.241784 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_45 RESULT=pass
3257 08:26:45.289628 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_45 RESULT=pass>
3258 08:26:45.290316 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_45 RESULT=pass
3260 08:26:45.342716 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_44 RESULT=pass>
3261 08:26:45.343665 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_44 RESULT=pass
3263 08:26:45.387800 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_44 RESULT=pass>
3264 08:26:45.388700 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_44 RESULT=pass
3266 08:26:45.442389 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_44 RESULT=pass>
3267 08:26:45.443262 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_44 RESULT=pass
3269 08:26:45.493335 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_44 RESULT=pass>
3270 08:26:45.494231 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_44 RESULT=pass
3272 08:26:45.538769 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_44 RESULT=pass>
3273 08:26:45.539652 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_44 RESULT=pass
3275 08:26:45.594034 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_44 RESULT=pass>
3276 08:26:45.594925 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_44 RESULT=pass
3278 08:26:45.651077 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_44 RESULT=pass>
3279 08:26:45.651964 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_44 RESULT=pass
3281 08:26:45.701784 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_43 RESULT=pass>
3282 08:26:45.702781 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_43 RESULT=pass
3284 08:26:45.751160 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_43 RESULT=pass>
3285 08:26:45.752082 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_43 RESULT=pass
3287 08:26:45.800478 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_43 RESULT=pass>
3288 08:26:45.801385 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_43 RESULT=pass
3290 08:26:45.852372 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_43 RESULT=pass>
3291 08:26:45.853257 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_43 RESULT=pass
3293 08:26:45.897875 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_43 RESULT=pass>
3294 08:26:45.898744 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_43 RESULT=pass
3296 08:26:45.954688 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_43 RESULT=pass>
3297 08:26:45.955551 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_43 RESULT=pass
3299 08:26:45.998185 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_43 RESULT=pass>
3300 08:26:45.999045 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_43 RESULT=pass
3302 08:26:46.051181 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_42 RESULT=pass>
3303 08:26:46.052084 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_42 RESULT=pass
3305 08:26:46.107204 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_42 RESULT=pass>
3306 08:26:46.108130 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_42 RESULT=pass
3308 08:26:46.153952 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_42 RESULT=pass>
3309 08:26:46.154868 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_42 RESULT=pass
3311 08:26:46.198987 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_42 RESULT=pass>
3312 08:26:46.199864 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_42 RESULT=pass
3314 08:26:46.244126 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_42 RESULT=pass>
3315 08:26:46.244981 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_42 RESULT=pass
3317 08:26:46.291464 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_42 RESULT=pass>
3318 08:26:46.292353 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_42 RESULT=pass
3320 08:26:46.338907 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_42 RESULT=pass>
3321 08:26:46.339837 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_42 RESULT=pass
3323 08:26:46.384456 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_41 RESULT=pass>
3324 08:26:46.385418 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_41 RESULT=pass
3326 08:26:46.430414 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_41 RESULT=pass>
3327 08:26:46.431286 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_41 RESULT=pass
3329 08:26:46.478072 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_41 RESULT=pass>
3330 08:26:46.479089 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_41 RESULT=pass
3332 08:26:46.530545 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_41 RESULT=pass>
3333 08:26:46.531408 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_41 RESULT=pass
3335 08:26:46.583262 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_41 RESULT=pass>
3336 08:26:46.584099 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_41 RESULT=pass
3338 08:26:46.636259 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_41 RESULT=pass>
3339 08:26:46.637278 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_41 RESULT=pass
3341 08:26:46.690937 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_41 RESULT=pass>
3342 08:26:46.691762 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_41 RESULT=pass
3344 08:26:46.744639 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_40 RESULT=pass>
3345 08:26:46.745481 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_40 RESULT=pass
3347 08:26:46.797895 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_40 RESULT=pass>
3348 08:26:46.798734 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_40 RESULT=pass
3350 08:26:46.851623 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_40 RESULT=pass>
3351 08:26:46.852492 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_40 RESULT=pass
3353 08:26:46.910261 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_40 RESULT=pass>
3354 08:26:46.911097 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_40 RESULT=pass
3356 08:26:46.960136 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_40 RESULT=pass>
3357 08:26:46.961007 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_40 RESULT=pass
3359 08:26:47.018003 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_40 RESULT=pass>
3360 08:26:47.018884 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_40 RESULT=pass
3362 08:26:47.067447 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_40 RESULT=pass>
3363 08:26:47.068337 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_40 RESULT=pass
3365 08:26:47.117386 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_39 RESULT=pass>
3366 08:26:47.118223 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_39 RESULT=pass
3368 08:26:47.163120 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_39 RESULT=pass>
3369 08:26:47.164096 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_39 RESULT=pass
3371 08:26:47.219910 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_39 RESULT=pass>
3372 08:26:47.220898 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_39 RESULT=pass
3374 08:26:47.272770 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_39 RESULT=pass>
3375 08:26:47.273648 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_39 RESULT=pass
3377 08:26:47.333906 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_39 RESULT=pass>
3378 08:26:47.334814 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_39 RESULT=pass
3380 08:26:47.391861 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_39 RESULT=pass>
3381 08:26:47.392781 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_39 RESULT=pass
3383 08:26:47.449862 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_39 RESULT=pass>
3384 08:26:47.450789 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_39 RESULT=pass
3386 08:26:47.502007 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_38 RESULT=pass>
3387 08:26:47.502932 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_38 RESULT=pass
3389 08:26:47.557038 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_38 RESULT=pass>
3390 08:26:47.557907 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_38 RESULT=pass
3392 08:26:47.619169 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_38 RESULT=pass>
3393 08:26:47.620102 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_38 RESULT=pass
3395 08:26:47.664250 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_38 RESULT=pass>
3396 08:26:47.665141 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_38 RESULT=pass
3398 08:26:47.716891 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_38 RESULT=pass>
3399 08:26:47.717712 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_38 RESULT=pass
3401 08:26:47.764617 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_38 RESULT=pass>
3402 08:26:47.765465 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_38 RESULT=pass
3404 08:26:47.812110 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_38 RESULT=pass>
3405 08:26:47.812939 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_38 RESULT=pass
3407 08:26:47.868712 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_37 RESULT=pass>
3408 08:26:47.869533 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_37 RESULT=pass
3410 08:26:47.914413 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_37 RESULT=pass>
3411 08:26:47.915230 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_37 RESULT=pass
3413 08:26:47.972486 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_37 RESULT=pass>
3414 08:26:47.973305 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_37 RESULT=pass
3416 08:26:48.024402 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_37 RESULT=pass>
3417 08:26:48.025318 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_37 RESULT=pass
3419 08:26:48.081637 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_37 RESULT=pass>
3420 08:26:48.082519 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_37 RESULT=pass
3422 08:26:48.140190 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_37 RESULT=pass>
3423 08:26:48.140990 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_37 RESULT=pass
3425 08:26:48.194114 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_37 RESULT=pass>
3426 08:26:48.194868 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_37 RESULT=pass
3428 08:26:48.249096 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_36 RESULT=pass>
3429 08:26:48.250095 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_36 RESULT=pass
3431 08:26:48.301706 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_36 RESULT=pass>
3432 08:26:48.302557 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_36 RESULT=pass
3434 08:26:48.351833 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_36 RESULT=pass>
3435 08:26:48.352674 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_36 RESULT=pass
3437 08:26:48.404930 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_36 RESULT=pass>
3438 08:26:48.405721 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_36 RESULT=pass
3440 08:26:48.460925 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_36 RESULT=pass>
3441 08:26:48.461713 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_36 RESULT=pass
3443 08:26:48.515814 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_36 RESULT=pass>
3444 08:26:48.516578 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_36 RESULT=pass
3446 08:26:48.568313 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_36 RESULT=pass>
3447 08:26:48.569047 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_36 RESULT=pass
3449 08:26:48.631518 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_35 RESULT=pass>
3450 08:26:48.632318 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_35 RESULT=pass
3452 08:26:48.678907 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_35 RESULT=pass>
3453 08:26:48.679618 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_35 RESULT=pass
3455 08:26:48.733078 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_35 RESULT=pass>
3456 08:26:48.733799 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_35 RESULT=pass
3458 08:26:48.777647 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_35 RESULT=pass>
3459 08:26:48.778355 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_35 RESULT=pass
3461 08:26:48.830084 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_35 RESULT=pass>
3462 08:26:48.830787 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_35 RESULT=pass
3464 08:26:48.885706 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_35 RESULT=pass>
3465 08:26:48.886431 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_35 RESULT=pass
3467 08:26:48.939771 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_35 RESULT=pass>
3468 08:26:48.940530 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_35 RESULT=pass
3470 08:26:48.985976 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_34 RESULT=pass>
3471 08:26:48.986686 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_34 RESULT=pass
3473 08:26:49.036418 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_34 RESULT=pass>
3474 08:26:49.037150 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_34 RESULT=pass
3476 08:26:49.086665 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_34 RESULT=pass>
3477 08:26:49.087380 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_34 RESULT=pass
3479 08:26:49.138105 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_34 RESULT=pass>
3480 08:26:49.138819 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_34 RESULT=pass
3482 08:26:49.193109 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_34 RESULT=pass>
3483 08:26:49.193809 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_34 RESULT=pass
3485 08:26:49.255507 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_34 RESULT=pass>
3486 08:26:49.256209 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_34 RESULT=pass
3488 08:26:49.300079 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_34 RESULT=pass>
3489 08:26:49.300972 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_34 RESULT=pass
3491 08:26:49.350752 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_33 RESULT=pass>
3492 08:26:49.352433 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_33 RESULT=pass
3494 08:26:49.402038 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_33 RESULT=pass>
3495 08:26:49.414718 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_33 RESULT=pass
3497 08:26:49.446916 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_33 RESULT=pass>
3498 08:26:49.447696 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_33 RESULT=pass
3500 08:26:49.502376 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_33 RESULT=pass>
3501 08:26:49.503342 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_33 RESULT=pass
3503 08:26:49.557002 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_33 RESULT=pass>
3504 08:26:49.565308 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_33 RESULT=pass
3506 08:26:49.610643 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_33 RESULT=pass>
3507 08:26:49.611443 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_33 RESULT=pass
3509 08:26:49.662326 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_33 RESULT=pass>
3510 08:26:49.663141 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_33 RESULT=pass
3512 08:26:49.706551 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_32 RESULT=pass>
3513 08:26:49.707728 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_32 RESULT=pass
3515 08:26:49.751340 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_32 RESULT=pass>
3516 08:26:49.752543 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_32 RESULT=pass
3518 08:26:49.797197 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_32 RESULT=pass>
3519 08:26:49.798037 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_32 RESULT=pass
3521 08:26:49.857300 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_32 RESULT=pass>
3522 08:26:49.858084 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_32 RESULT=pass
3524 08:26:49.902911 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_32 RESULT=pass>
3525 08:26:49.903706 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_32 RESULT=pass
3527 08:26:49.949437 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_32 RESULT=pass>
3528 08:26:49.950212 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_32 RESULT=pass
3530 08:26:50.003425 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_32 RESULT=pass>
3531 08:26:50.004331 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_32 RESULT=pass
3533 08:26:50.064787 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_31 RESULT=pass>
3534 08:26:50.065629 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_31 RESULT=pass
3536 08:26:50.108894 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_31 RESULT=pass>
3537 08:26:50.109665 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_31 RESULT=pass
3539 08:26:50.164081 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_31 RESULT=pass>
3540 08:26:50.164920 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_31 RESULT=pass
3542 08:26:50.229809 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_31 RESULT=pass>
3543 08:26:50.230632 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_31 RESULT=pass
3545 08:26:50.275899 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_31 RESULT=pass>
3546 08:26:50.276732 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_31 RESULT=pass
3548 08:26:50.322832 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_31 RESULT=pass>
3549 08:26:50.323682 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_31 RESULT=pass
3551 08:26:50.373785 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_31 RESULT=pass>
3552 08:26:50.374644 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_31 RESULT=pass
3554 08:26:50.424484 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_30 RESULT=pass>
3555 08:26:50.425363 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_30 RESULT=pass
3557 08:26:50.469314 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_30 RESULT=pass>
3558 08:26:50.470220 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_30 RESULT=pass
3560 08:26:50.519203 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_30 RESULT=pass>
3561 08:26:50.520082 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_30 RESULT=pass
3563 08:26:50.577436 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_30 RESULT=pass>
3564 08:26:50.578242 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_30 RESULT=pass
3566 08:26:50.624330 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_30 RESULT=pass>
3567 08:26:50.625119 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_30 RESULT=pass
3569 08:26:50.676798 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_30 RESULT=pass>
3570 08:26:50.677619 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_30 RESULT=pass
3572 08:26:50.722671 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_30 RESULT=pass>
3573 08:26:50.723475 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_30 RESULT=pass
3575 08:26:50.777885 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_29 RESULT=pass>
3576 08:26:50.778674 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_29 RESULT=pass
3578 08:26:50.825719 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_29 RESULT=pass>
3579 08:26:50.826489 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_29 RESULT=pass
3581 08:26:50.882620 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_29 RESULT=pass>
3582 08:26:50.883416 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_29 RESULT=pass
3584 08:26:50.929529 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_29 RESULT=pass>
3585 08:26:50.930322 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_29 RESULT=pass
3587 08:26:50.977630 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_29 RESULT=pass>
3588 08:26:50.978405 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_29 RESULT=pass
3590 08:26:51.039398 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_29 RESULT=pass>
3591 08:26:51.040299 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_29 RESULT=pass
3593 08:26:51.084033 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_29 RESULT=pass>
3594 08:26:51.084865 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_29 RESULT=pass
3596 08:26:51.130149 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_28 RESULT=pass>
3597 08:26:51.130938 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_28 RESULT=pass
3599 08:26:51.176956 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_28 RESULT=pass>
3600 08:26:51.177724 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_28 RESULT=pass
3602 08:26:51.226751 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_28 RESULT=pass>
3603 08:26:51.227542 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_28 RESULT=pass
3605 08:26:51.274941 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_28 RESULT=pass>
3606 08:26:51.275716 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_28 RESULT=pass
3608 08:26:51.320965 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_28 RESULT=pass>
3609 08:26:51.321796 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_28 RESULT=pass
3611 08:26:51.368939 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_28 RESULT=pass>
3612 08:26:51.369741 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_28 RESULT=pass
3614 08:26:51.426219 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_28 RESULT=pass>
3615 08:26:51.427106 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_28 RESULT=pass
3617 08:26:51.472123 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_27 RESULT=pass>
3618 08:26:51.473083 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_27 RESULT=pass
3620 08:26:51.519337 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_27 RESULT=pass>
3621 08:26:51.520230 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_27 RESULT=pass
3623 08:26:51.571449 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_27 RESULT=pass>
3624 08:26:51.572290 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_27 RESULT=pass
3626 08:26:51.620307 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_27 RESULT=pass>
3627 08:26:51.621067 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_27 RESULT=pass
3629 08:26:51.686394 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_27 RESULT=pass>
3630 08:26:51.687203 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_27 RESULT=pass
3632 08:26:51.730860 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_27 RESULT=pass>
3633 08:26:51.731621 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_27 RESULT=pass
3635 08:26:51.779314 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_27 RESULT=pass>
3636 08:26:51.780099 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_27 RESULT=pass
3638 08:26:51.830339 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_26 RESULT=pass>
3639 08:26:51.831133 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_26 RESULT=pass
3641 08:26:51.875476 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_26 RESULT=pass>
3642 08:26:51.876278 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_26 RESULT=pass
3644 08:26:51.929786 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_26 RESULT=skip>
3645 08:26:51.930571 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_26 RESULT=skip
3647 08:26:51.980891 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_26 RESULT=skip>
3648 08:26:51.981666 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_26 RESULT=skip
3650 08:26:52.032465 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_26 RESULT=skip>
3651 08:26:52.033315 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_26 RESULT=skip
3653 08:26:52.084281 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_26 RESULT=pass>
3654 08:26:52.085120 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_26 RESULT=pass
3656 08:26:52.135507 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_26 RESULT=pass>
3657 08:26:52.136332 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_26 RESULT=pass
3659 08:26:52.179145 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_25 RESULT=pass>
3660 08:26:52.179938 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_25 RESULT=pass
3662 08:26:52.228046 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_25 RESULT=pass>
3663 08:26:52.228839 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_25 RESULT=pass
3665 08:26:52.273258 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_25 RESULT=pass>
3666 08:26:52.274050 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_25 RESULT=pass
3668 08:26:52.339328 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_25 RESULT=skip>
3669 08:26:52.340203 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_25 RESULT=skip
3671 08:26:52.384322 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_25 RESULT=skip>
3672 08:26:52.385185 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_25 RESULT=skip
3674 08:26:52.438663 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_25 RESULT=pass>
3675 08:26:52.439611 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_25 RESULT=pass
3677 08:26:52.483066 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_25 RESULT=pass>
3678 08:26:52.483933 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_25 RESULT=pass
3680 08:26:52.533173 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_24 RESULT=pass>
3681 08:26:52.533964 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_24 RESULT=pass
3683 08:26:52.590396 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_24 RESULT=pass>
3684 08:26:52.591182 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_24 RESULT=pass
3686 08:26:52.638097 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_24 RESULT=skip>
3687 08:26:52.638924 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_24 RESULT=skip
3689 08:26:52.690506 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_24 RESULT=skip>
3690 08:26:52.691299 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_24 RESULT=skip
3692 08:26:52.738855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_24 RESULT=skip>
3693 08:26:52.739636 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_24 RESULT=skip
3695 08:26:52.786267 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_24 RESULT=pass>
3696 08:26:52.787051 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_24 RESULT=pass
3698 08:26:52.834444 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_24 RESULT=pass>
3699 08:26:52.835249 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_24 RESULT=pass
3701 08:26:52.890434 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_23 RESULT=pass>
3702 08:26:52.891215 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_23 RESULT=pass
3704 08:26:52.934885 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_23 RESULT=pass>
3705 08:26:52.935669 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_23 RESULT=pass
3707 08:26:52.983300 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_23 RESULT=skip>
3708 08:26:52.984082 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_23 RESULT=skip
3710 08:26:53.028495 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_23 RESULT=skip>
3711 08:26:53.029336 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_23 RESULT=skip
3713 08:26:53.074794 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_23 RESULT=skip>
3714 08:26:53.075592 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_23 RESULT=skip
3716 08:26:53.122846 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_23 RESULT=pass>
3717 08:26:53.123636 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_23 RESULT=pass
3719 08:26:53.168083 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_23 RESULT=pass>
3720 08:26:53.168860 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_23 RESULT=pass
3722 08:26:53.215589 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_22 RESULT=pass>
3723 08:26:53.216389 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_22 RESULT=pass
3725 08:26:53.260509 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_22 RESULT=pass>
3726 08:26:53.261290 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_22 RESULT=pass
3728 08:26:53.322631 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_22 RESULT=pass>
3729 08:26:53.323439 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_22 RESULT=pass
3731 08:26:53.374240 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_22 RESULT=pass>
3732 08:26:53.375044 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_22 RESULT=pass
3734 08:26:53.418988 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_22 RESULT=pass>
3735 08:26:53.419839 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_22 RESULT=pass
3737 08:26:53.462073 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_22 RESULT=pass>
3738 08:26:53.462884 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_22 RESULT=pass
3740 08:26:53.519879 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_22 RESULT=pass>
3741 08:26:53.520773 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_22 RESULT=pass
3743 08:26:53.572481 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_21 RESULT=pass>
3744 08:26:53.573250 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_21 RESULT=pass
3746 08:26:53.618215 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_21 RESULT=pass>
3747 08:26:53.618995 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_21 RESULT=pass
3749 08:26:53.669722 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_21 RESULT=pass>
3750 08:26:53.670484 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_21 RESULT=pass
3752 08:26:53.713659 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_21 RESULT=pass>
3753 08:26:53.714429 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_21 RESULT=pass
3755 08:26:53.764216 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_21 RESULT=pass>
3756 08:26:53.764997 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_21 RESULT=pass
3758 08:26:53.828629 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_21 RESULT=pass>
3759 08:26:53.829380 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_21 RESULT=pass
3761 08:26:53.876853 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_21 RESULT=pass>
3762 08:26:53.877631 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_21 RESULT=pass
3764 08:26:53.922176 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_20 RESULT=pass>
3765 08:26:53.922923 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_20 RESULT=pass
3767 08:26:53.967804 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_20 RESULT=pass>
3768 08:26:53.968619 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_20 RESULT=pass
3770 08:26:54.014353 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_20 RESULT=pass>
3771 08:26:54.015167 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_20 RESULT=pass
3773 08:26:54.060403 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_20 RESULT=pass>
3774 08:26:54.061201 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_20 RESULT=pass
3776 08:26:54.107728 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_20 RESULT=pass>
3777 08:26:54.108568 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_20 RESULT=pass
3779 08:26:54.152933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_20 RESULT=pass>
3780 08:26:54.153708 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_20 RESULT=pass
3782 08:26:54.199410 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_20 RESULT=pass>
3783 08:26:54.200167 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_20 RESULT=pass
3785 08:26:54.247498 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_19 RESULT=pass>
3786 08:26:54.248332 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_19 RESULT=pass
3788 08:26:54.292097 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_19 RESULT=pass>
3789 08:26:54.292881 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_19 RESULT=pass
3791 08:26:54.337347 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_19 RESULT=pass>
3792 08:26:54.338148 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_19 RESULT=pass
3794 08:26:54.387219 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_19 RESULT=pass>
3795 08:26:54.388073 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_19 RESULT=pass
3797 08:26:54.439407 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_19 RESULT=pass>
3798 08:26:54.440296 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_19 RESULT=pass
3800 08:26:54.486631 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_19 RESULT=pass>
3801 08:26:54.487427 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_19 RESULT=pass
3803 08:26:54.532422 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_19 RESULT=pass>
3804 08:26:54.533187 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_19 RESULT=pass
3806 08:26:54.581802 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_18 RESULT=pass>
3807 08:26:54.582583 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_18 RESULT=pass
3809 08:26:54.627231 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_18 RESULT=pass>
3810 08:26:54.628030 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_18 RESULT=pass
3812 08:26:54.678530 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_18 RESULT=pass>
3813 08:26:54.679309 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_18 RESULT=pass
3815 08:26:54.722587 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_18 RESULT=pass>
3816 08:26:54.723335 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_18 RESULT=pass
3818 08:26:54.772275 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_18 RESULT=pass>
3819 08:26:54.773045 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_18 RESULT=pass
3821 08:26:54.828365 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_18 RESULT=pass>
3822 08:26:54.829137 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_18 RESULT=pass
3824 08:26:54.875434 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_18 RESULT=pass>
3825 08:26:54.876193 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_18 RESULT=pass
3827 08:26:54.920549 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_17 RESULT=pass>
3828 08:26:54.921360 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_17 RESULT=pass
3830 08:26:54.967458 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_17 RESULT=pass>
3831 08:26:54.968194 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_17 RESULT=pass
3833 08:26:55.014000 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_17 RESULT=pass>
3834 08:26:55.014808 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_17 RESULT=pass
3836 08:26:55.065309 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_17 RESULT=pass>
3837 08:26:55.066118 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_17 RESULT=pass
3839 08:26:55.114395 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_17 RESULT=pass>
3840 08:26:55.115128 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_17 RESULT=pass
3842 08:26:55.179018 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_17 RESULT=pass>
3843 08:26:55.179840 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_17 RESULT=pass
3845 08:26:55.224251 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_17 RESULT=pass>
3846 08:26:55.225002 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_17 RESULT=pass
3848 08:26:55.275782 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_16 RESULT=pass>
3849 08:26:55.276618 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_16 RESULT=pass
3851 08:26:55.322239 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_16 RESULT=pass>
3852 08:26:55.323023 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_16 RESULT=pass
3854 08:26:55.374731 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_16 RESULT=pass>
3855 08:26:55.375564 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_16 RESULT=pass
3857 08:26:55.426907 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_16 RESULT=pass>
3858 08:26:55.427764 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_16 RESULT=pass
3860 08:26:55.471903 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_16 RESULT=pass>
3861 08:26:55.472744 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_16 RESULT=pass
3863 08:26:55.518351 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_16 RESULT=pass>
3864 08:26:55.519141 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_16 RESULT=pass
3866 08:26:55.565000 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_16 RESULT=pass>
3867 08:26:55.565756 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_16 RESULT=pass
3869 08:26:55.612965 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_15 RESULT=pass>
3870 08:26:55.613754 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_15 RESULT=pass
3872 08:26:55.659723 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_15 RESULT=pass>
3873 08:26:55.660640 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_15 RESULT=pass
3875 08:26:55.707286 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_15 RESULT=pass>
3876 08:26:55.708079 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_15 RESULT=pass
3878 08:26:55.752532 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_15 RESULT=pass>
3879 08:26:55.753276 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_15 RESULT=pass
3881 08:26:55.801970 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_15 RESULT=pass>
3882 08:26:55.802738 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_15 RESULT=pass
3884 08:26:55.856397 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_15 RESULT=pass>
3885 08:26:55.857151 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_15 RESULT=pass
3887 08:26:55.915689 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_15 RESULT=pass>
3888 08:26:55.916495 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_15 RESULT=pass
3890 08:26:55.961678 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_14 RESULT=pass>
3891 08:26:55.962454 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_14 RESULT=pass
3893 08:26:56.010137 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_14 RESULT=pass>
3894 08:26:56.010937 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_14 RESULT=pass
3896 08:26:56.055444 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_14 RESULT=pass>
3897 08:26:56.056290 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_14 RESULT=pass
3899 08:26:56.108464 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_14 RESULT=pass>
3900 08:26:56.109255 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_14 RESULT=pass
3902 08:26:56.160242 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_14 RESULT=pass>
3903 08:26:56.161021 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_14 RESULT=pass
3905 08:26:56.215603 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_14 RESULT=pass>
3906 08:26:56.216416 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_14 RESULT=pass
3908 08:26:56.261218 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_14 RESULT=pass>
3909 08:26:56.261972 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_14 RESULT=pass
3911 08:26:56.306174 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_13 RESULT=pass>
3912 08:26:56.307025 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_13 RESULT=pass
3914 08:26:56.351163 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_13 RESULT=pass>
3915 08:26:56.351957 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_13 RESULT=pass
3917 08:26:56.397425 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_13 RESULT=pass>
3918 08:26:56.398401 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_13 RESULT=pass
3920 08:26:56.442522 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_13 RESULT=pass>
3921 08:26:56.443383 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_13 RESULT=pass
3923 08:26:56.491219 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_13 RESULT=pass>
3924 08:26:56.492095 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_13 RESULT=pass
3926 08:26:56.537448 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_13 RESULT=pass>
3927 08:26:56.538208 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_13 RESULT=pass
3929 08:26:56.583468 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_13 RESULT=pass>
3930 08:26:56.584305 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_13 RESULT=pass
3932 08:26:56.635504 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_12 RESULT=pass>
3933 08:26:56.636312 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_12 RESULT=pass
3935 08:26:56.689245 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_12 RESULT=pass>
3936 08:26:56.689992 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_12 RESULT=pass
3938 08:26:56.740221 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_12 RESULT=pass>
3939 08:26:56.740988 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_12 RESULT=pass
3941 08:26:56.797174 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_12 RESULT=pass>
3942 08:26:56.797925 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_12 RESULT=pass
3944 08:26:56.844401 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_12 RESULT=pass>
3945 08:26:56.845166 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_12 RESULT=pass
3947 08:26:56.903724 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_12 RESULT=pass>
3948 08:26:56.904549 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_12 RESULT=pass
3950 08:26:56.950191 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_12 RESULT=pass>
3951 08:26:56.950962 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_12 RESULT=pass
3953 08:26:56.998996 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_11 RESULT=pass>
3954 08:26:56.999764 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_11 RESULT=pass
3956 08:26:57.045119 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_11 RESULT=pass>
3957 08:26:57.045943 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_11 RESULT=pass
3959 08:26:57.097947 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_11 RESULT=pass>
3960 08:26:57.098744 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_11 RESULT=pass
3962 08:26:57.144367 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_11 RESULT=pass>
3963 08:26:57.145116 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_11 RESULT=pass
3965 08:26:57.197779 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_11 RESULT=pass>
3966 08:26:57.198556 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_11 RESULT=pass
3968 08:26:57.245521 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_11 RESULT=pass>
3969 08:26:57.246284 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_11 RESULT=pass
3971 08:26:57.299820 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_11 RESULT=pass>
3972 08:26:57.300641 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_11 RESULT=pass
3974 08:26:57.356156 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_10 RESULT=pass>
3975 08:26:57.357010 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_10 RESULT=pass
3977 08:26:57.407552 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_10 RESULT=pass>
3978 08:26:57.408444 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_10 RESULT=pass
3980 08:26:57.463290 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_10 RESULT=pass>
3981 08:26:57.464113 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_10 RESULT=pass
3983 08:26:57.519212 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_10 RESULT=pass>
3984 08:26:57.520043 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_10 RESULT=pass
3986 08:26:57.566911 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_10 RESULT=pass>
3987 08:26:57.567667 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_10 RESULT=pass
3989 08:26:57.614926 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_10 RESULT=pass>
3990 08:26:57.615703 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_10 RESULT=pass
3992 08:26:57.673636 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_10 RESULT=pass>
3993 08:26:57.674408 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_10 RESULT=pass
3995 08:26:57.727803 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_9 RESULT=pass>
3996 08:26:57.728624 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_9 RESULT=pass
3998 08:26:57.776935 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_9 RESULT=pass>
3999 08:26:57.777680 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_9 RESULT=pass
4001 08:26:57.837236 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_9 RESULT=pass>
4002 08:26:57.838022 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_9 RESULT=pass
4004 08:26:57.896290 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_9 RESULT=pass>
4005 08:26:57.897103 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_9 RESULT=pass
4007 08:26:57.947791 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_9 RESULT=pass>
4008 08:26:57.948584 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_9 RESULT=pass
4010 08:26:58.012390 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_9 RESULT=pass>
4011 08:26:58.013214 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_9 RESULT=pass
4013 08:26:58.070877 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_9 RESULT=pass>
4014 08:26:58.071710 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_9 RESULT=pass
4016 08:26:58.128977 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_8 RESULT=pass>
4017 08:26:58.129732 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_8 RESULT=pass
4019 08:26:58.190196 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_8 RESULT=pass>
4020 08:26:58.190994 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_8 RESULT=pass
4022 08:26:58.246101 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_8 RESULT=pass>
4023 08:26:58.246894 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_8 RESULT=pass
4025 08:26:58.301388 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_8 RESULT=pass>
4026 08:26:58.302143 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_8 RESULT=pass
4028 08:26:58.354051 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_8 RESULT=pass>
4029 08:26:58.354881 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_8 RESULT=pass
4031 08:26:58.420864 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_8 RESULT=pass>
4032 08:26:58.421734 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_8 RESULT=pass
4034 08:26:58.477990 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_8 RESULT=pass>
4035 08:26:58.478804 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_8 RESULT=pass
4037 08:26:58.531237 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_7 RESULT=pass>
4038 08:26:58.532076 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_7 RESULT=pass
4040 08:26:58.587321 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_7 RESULT=pass>
4041 08:26:58.588107 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_7 RESULT=pass
4043 08:26:58.637875 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_7 RESULT=pass>
4044 08:26:58.638635 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_7 RESULT=pass
4046 08:26:58.691247 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_7 RESULT=pass>
4047 08:26:58.692033 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_7 RESULT=pass
4049 08:26:58.744932 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_7 RESULT=pass>
4050 08:26:58.745708 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_7 RESULT=pass
4052 08:26:58.798937 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_7 RESULT=pass>
4053 08:26:58.799708 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_7 RESULT=pass
4055 08:26:58.857446 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_7 RESULT=pass>
4056 08:26:58.858193 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_7 RESULT=pass
4058 08:26:58.920516 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_6 RESULT=pass>
4059 08:26:58.921303 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_6 RESULT=pass
4061 08:26:58.968235 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_6 RESULT=pass>
4062 08:26:58.969018 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_6 RESULT=pass
4064 08:26:59.029962 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_6 RESULT=pass>
4065 08:26:59.030791 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_6 RESULT=pass
4067 08:26:59.082158 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_6 RESULT=pass>
4068 08:26:59.082941 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_6 RESULT=pass
4070 08:26:59.128589 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_6 RESULT=pass>
4071 08:26:59.129363 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_6 RESULT=pass
4073 08:26:59.188014 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_6 RESULT=pass>
4074 08:26:59.188793 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_6 RESULT=pass
4076 08:26:59.234390 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_6 RESULT=pass>
4077 08:26:59.235137 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_6 RESULT=pass
4079 08:26:59.284533 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_5 RESULT=pass>
4080 08:26:59.285301 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_5 RESULT=pass
4082 08:26:59.346771 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_5 RESULT=pass>
4083 08:26:59.347580 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_5 RESULT=pass
4085 08:26:59.402240 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_5 RESULT=pass>
4086 08:26:59.403234 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_5 RESULT=pass
4088 08:26:59.450297 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_5 RESULT=pass>
4089 08:26:59.451145 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_5 RESULT=pass
4091 08:26:59.499073 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_5 RESULT=pass>
4092 08:26:59.499851 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_5 RESULT=pass
4094 08:26:59.546490 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_5 RESULT=pass>
4095 08:26:59.547257 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_5 RESULT=pass
4097 08:26:59.598159 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_5 RESULT=pass>
4098 08:26:59.598918 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_5 RESULT=pass
4100 08:26:59.643386 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_4 RESULT=pass>
4101 08:26:59.644168 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_4 RESULT=pass
4103 08:26:59.690858 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_4 RESULT=pass>
4104 08:26:59.691610 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_4 RESULT=pass
4106 08:26:59.739800 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_4 RESULT=pass>
4107 08:26:59.740587 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_4 RESULT=pass
4109 08:26:59.785284 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_4 RESULT=pass>
4110 08:26:59.786047 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_4 RESULT=pass
4112 08:26:59.830592 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_4 RESULT=pass>
4113 08:26:59.831329 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_4 RESULT=pass
4115 08:26:59.876955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_4 RESULT=pass>
4116 08:26:59.877842 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_4 RESULT=pass
4118 08:26:59.921906 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_4 RESULT=pass>
4119 08:26:59.922769 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_4 RESULT=pass
4121 08:26:59.980901 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_3 RESULT=pass>
4122 08:26:59.981665 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_3 RESULT=pass
4124 08:27:00.028919 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_3 RESULT=pass>
4125 08:27:00.029664 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_3 RESULT=pass
4127 08:27:00.089270 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_3 RESULT=pass>
4128 08:27:00.089998 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_3 RESULT=pass
4130 08:27:00.141083 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_3 RESULT=pass>
4131 08:27:00.141800 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_3 RESULT=pass
4133 08:27:00.199327 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_3 RESULT=pass>
4134 08:27:00.200072 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_3 RESULT=pass
4136 08:27:00.246470 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_3 RESULT=pass>
4137 08:27:00.247214 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_3 RESULT=pass
4139 08:27:00.295215 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_3 RESULT=pass>
4140 08:27:00.295966 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_3 RESULT=pass
4142 08:27:00.350708 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_2 RESULT=pass>
4143 08:27:00.351520 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_2 RESULT=pass
4145 08:27:00.397306 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_2 RESULT=pass>
4146 08:27:00.398256 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_2 RESULT=pass
4148 08:27:00.450290 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_2 RESULT=pass>
4149 08:27:00.451161 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_2 RESULT=pass
4151 08:27:00.502744 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_2 RESULT=pass>
4152 08:27:00.503527 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_2 RESULT=pass
4154 08:27:00.556532 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_2 RESULT=pass>
4155 08:27:00.557287 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_2 RESULT=pass
4157 08:27:00.603151 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_2 RESULT=pass>
4158 08:27:00.603899 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_2 RESULT=pass
4160 08:27:00.659027 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_2 RESULT=pass>
4161 08:27:00.659787 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_2 RESULT=pass
4163 08:27:00.705646 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_1 RESULT=pass>
4164 08:27:00.706394 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_1 RESULT=pass
4166 08:27:00.758035 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_1 RESULT=pass>
4167 08:27:00.758786 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_1 RESULT=pass
4169 08:27:00.815239 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_1 RESULT=pass>
4170 08:27:00.816019 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_1 RESULT=pass
4172 08:27:00.874745 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_1 RESULT=pass>
4173 08:27:00.875532 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_1 RESULT=pass
4175 08:27:00.937088 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_1 RESULT=pass>
4176 08:27:00.937837 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_1 RESULT=pass
4178 08:27:00.993339 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_1 RESULT=pass>
4179 08:27:00.994096 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_1 RESULT=pass
4181 08:27:01.051819 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_1 RESULT=pass>
4182 08:27:01.052642 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_1 RESULT=pass
4184 08:27:01.104240 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_0 RESULT=pass>
4185 08:27:01.105001 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_0 RESULT=pass
4187 08:27:01.157677 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_0 RESULT=pass>
4188 08:27:01.158427 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_0 RESULT=pass
4190 08:27:01.212062 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_0 RESULT=pass>
4191 08:27:01.212815 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_0 RESULT=pass
4193 08:27:01.263353 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_0 RESULT=pass>
4194 08:27:01.264110 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_0 RESULT=pass
4196 08:27:01.309019 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_0 RESULT=pass>
4197 08:27:01.309785 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_0 RESULT=pass
4199 08:27:01.357627 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_0 RESULT=pass>
4200 08:27:01.358422 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_0 RESULT=pass
4202 08:27:01.406365 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_0 RESULT=pass>
4203 08:27:01.407270 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_0 RESULT=pass
4205 08:27:01.450886 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test RESULT=pass
4207 08:27:01.452795 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test RESULT=pass>
4208 08:27:01.503164 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_5_0_CAPTURE RESULT=skip>
4209 08:27:01.503928 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_5_0_CAPTURE RESULT=skip
4211 08:27:01.549289 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_5_0_CAPTURE RESULT=skip>
4212 08:27:01.550040 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_5_0_CAPTURE RESULT=skip
4214 08:27:01.598979 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_5_0_CAPTURE RESULT=skip>
4215 08:27:01.599726 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_5_0_CAPTURE RESULT=skip
4217 08:27:01.647792 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_5_0_CAPTURE RESULT=skip>
4218 08:27:01.648571 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_5_0_CAPTURE RESULT=skip
4220 08:27:01.699102 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_5_0_CAPTURE RESULT=skip>
4221 08:27:01.699845 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_5_0_CAPTURE RESULT=skip
4223 08:27:01.746554 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_5_0_CAPTURE RESULT=skip>
4224 08:27:01.747293 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_5_0_CAPTURE RESULT=skip
4226 08:27:01.795624 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_5_0_CAPTURE RESULT=skip>
4227 08:27:01.796404 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_5_0_CAPTURE RESULT=skip
4229 08:27:01.845619 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_4_0_CAPTURE RESULT=skip>
4230 08:27:01.846414 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_4_0_CAPTURE RESULT=skip
4232 08:27:01.893681 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_4_0_CAPTURE RESULT=skip>
4233 08:27:01.894502 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_4_0_CAPTURE RESULT=skip
4235 08:27:01.940763 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_4_0_CAPTURE RESULT=skip>
4236 08:27:01.941715 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_4_0_CAPTURE RESULT=skip
4238 08:27:01.998541 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_4_0_CAPTURE RESULT=skip>
4239 08:27:01.999394 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_4_0_CAPTURE RESULT=skip
4241 08:27:02.044356 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_4_0_CAPTURE RESULT=skip>
4242 08:27:02.045193 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_4_0_CAPTURE RESULT=skip
4244 08:27:02.090673 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_4_0_CAPTURE RESULT=skip>
4245 08:27:02.091446 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_4_0_CAPTURE RESULT=skip
4247 08:27:02.139446 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_4_0_CAPTURE RESULT=skip>
4248 08:27:02.140205 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_4_0_CAPTURE RESULT=skip
4250 08:27:02.186929 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_3_0_CAPTURE RESULT=skip>
4251 08:27:02.187673 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_3_0_CAPTURE RESULT=skip
4253 08:27:02.231966 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_3_0_CAPTURE RESULT=skip>
4254 08:27:02.232857 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_3_0_CAPTURE RESULT=skip
4256 08:27:02.277499 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_3_0_CAPTURE RESULT=skip>
4257 08:27:02.278393 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_3_0_CAPTURE RESULT=skip
4259 08:27:02.325418 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_3_0_CAPTURE RESULT=skip>
4260 08:27:02.326333 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_3_0_CAPTURE RESULT=skip
4262 08:27:02.375704 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_3_0_CAPTURE RESULT=skip>
4263 08:27:02.376724 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_3_0_CAPTURE RESULT=skip
4265 08:27:02.421636 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_3_0_CAPTURE RESULT=skip>
4266 08:27:02.422546 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_3_0_CAPTURE RESULT=skip
4268 08:27:02.469283 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_3_0_CAPTURE RESULT=skip>
4269 08:27:02.470185 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_3_0_CAPTURE RESULT=skip
4271 08:27:02.514882 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_2_0_PLAYBACK RESULT=skip>
4272 08:27:02.515756 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_2_0_PLAYBACK RESULT=skip
4274 08:27:02.560476 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_2_0_PLAYBACK RESULT=skip>
4275 08:27:02.561312 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_2_0_PLAYBACK RESULT=skip
4277 08:27:02.607518 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_2_0_PLAYBACK RESULT=skip>
4278 08:27:02.608377 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_2_0_PLAYBACK RESULT=skip
4280 08:27:02.654797 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_2_0_PLAYBACK RESULT=skip>
4281 08:27:02.655668 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_2_0_PLAYBACK RESULT=skip
4283 08:27:02.715883 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_2_0_PLAYBACK RESULT=skip>
4284 08:27:02.716740 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_2_0_PLAYBACK RESULT=skip
4286 08:27:02.761887 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_2_0_PLAYBACK RESULT=skip>
4287 08:27:02.762702 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_2_0_PLAYBACK RESULT=skip
4289 08:27:02.807360 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_2_0_PLAYBACK RESULT=skip>
4290 08:27:02.808184 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_2_0_PLAYBACK RESULT=skip
4292 08:27:02.854013 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_1_0_PLAYBACK RESULT=skip>
4293 08:27:02.854824 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_1_0_PLAYBACK RESULT=skip
4295 08:27:02.898862 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_1_0_PLAYBACK RESULT=skip>
4296 08:27:02.899687 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_1_0_PLAYBACK RESULT=skip
4298 08:27:02.944091 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_1_0_PLAYBACK RESULT=skip>
4299 08:27:02.944904 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_1_0_PLAYBACK RESULT=skip
4301 08:27:02.990899 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_1_0_PLAYBACK RESULT=skip>
4302 08:27:02.991747 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_1_0_PLAYBACK RESULT=skip
4304 08:27:03.046924 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_1_0_PLAYBACK RESULT=skip>
4305 08:27:03.047811 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_1_0_PLAYBACK RESULT=skip
4307 08:27:03.095931 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_1_0_PLAYBACK RESULT=skip>
4308 08:27:03.096841 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_1_0_PLAYBACK RESULT=skip
4310 08:27:03.148908 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_1_0_PLAYBACK RESULT=skip>
4311 08:27:03.149729 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_1_0_PLAYBACK RESULT=skip
4313 08:27:03.198888 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_0_0_PLAYBACK RESULT=skip>
4314 08:27:03.199707 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_0_0_PLAYBACK RESULT=skip
4316 08:27:03.249180 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_0_0_PLAYBACK RESULT=skip>
4317 08:27:03.250106 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_0_0_PLAYBACK RESULT=skip
4319 08:27:03.306645 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_0_0_PLAYBACK RESULT=skip>
4320 08:27:03.307479 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_0_0_PLAYBACK RESULT=skip
4322 08:27:03.352816 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_0_0_PLAYBACK RESULT=skip>
4323 08:27:03.353680 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_0_0_PLAYBACK RESULT=skip
4325 08:27:03.400433 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_0_0_PLAYBACK RESULT=skip>
4326 08:27:03.401392 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_0_0_PLAYBACK RESULT=skip
4328 08:27:03.462718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_0_0_PLAYBACK RESULT=skip>
4329 08:27:03.463564 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_0_0_PLAYBACK RESULT=skip
4331 08:27:03.513514 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_0_0_PLAYBACK RESULT=skip>
4332 08:27:03.514385 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_0_0_PLAYBACK RESULT=skip
4334 08:27:03.571412 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test RESULT=pass>
4335 08:27:03.572351 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test RESULT=pass
4337 08:27:03.625759 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_playback_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip>
4338 08:27:03.626667 Received signal: <TESTCASE> TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_playback_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip
4340 08:27:03.687025 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_capture_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip>
4341 08:27:03.687846 Received signal: <TESTCASE> TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_capture_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip
4343 08:27:03.737871 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_ni_capture_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip>
4344 08:27:03.738763 Received signal: <TESTCASE> TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_ni_capture_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip
4346 08:27:03.787911 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_ni_playback_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip>
4347 08:27:03.788867 Received signal: <TESTCASE> TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_ni_playback_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip
4349 08:27:03.841649 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_reset_ioctl_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip>
4350 08:27:03.842562 Received signal: <TESTCASE> TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_reset_ioctl_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip
4352 08:27:03.883639 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_test-pcmtest-driver RESULT=pass>
4353 08:27:03.884536 Received signal: <TESTCASE> TEST_CASE_ID=alsa_test-pcmtest-driver RESULT=pass
4355 08:27:03.940772 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_utimer-test_global_wrong_timers_test RESULT=pass>
4356 08:27:03.941589 Received signal: <TESTCASE> TEST_CASE_ID=alsa_utimer-test_global_wrong_timers_test RESULT=pass
4358 08:27:03.987885 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_utimer-test_timer_f_utimer RESULT=fail>
4359 08:27:03.988847 Received signal: <TESTCASE> TEST_CASE_ID=alsa_utimer-test_timer_f_utimer RESULT=fail
4361 08:27:04.043319 Received signal: <TESTCASE> TEST_CASE_ID=alsa_utimer-test RESULT=fail
4363 08:27:04.048438 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_utimer-test RESULT=fail>
4364 08:27:04.048981 + set +x
4365 08:27:04.054373 <LAVA_SIGNAL_ENDRUN 1_kselftest-alsa 978668_1.6.2.4.5>
4366 08:27:04.054877 <LAVA_TEST_RUNNER EXIT>
4367 08:27:04.055593 Received signal: <ENDRUN> 1_kselftest-alsa 978668_1.6.2.4.5
4368 08:27:04.056129 Ending use of test pattern.
4369 08:27:04.056591 Ending test lava.1_kselftest-alsa (978668_1.6.2.4.5), duration 40.28
4371 08:27:04.058266 ok: lava_test_shell seems to have completed
4372 08:27:04.082956 alsa_mixer-test: pass
alsa_mixer-test_event_missing_LCALTA_0: pass
alsa_mixer-test_event_missing_LCALTA_1: pass
alsa_mixer-test_event_missing_LCALTA_10: pass
alsa_mixer-test_event_missing_LCALTA_11: pass
alsa_mixer-test_event_missing_LCALTA_12: pass
alsa_mixer-test_event_missing_LCALTA_13: pass
alsa_mixer-test_event_missing_LCALTA_14: pass
alsa_mixer-test_event_missing_LCALTA_15: pass
alsa_mixer-test_event_missing_LCALTA_16: pass
alsa_mixer-test_event_missing_LCALTA_17: pass
alsa_mixer-test_event_missing_LCALTA_18: pass
alsa_mixer-test_event_missing_LCALTA_19: pass
alsa_mixer-test_event_missing_LCALTA_2: pass
alsa_mixer-test_event_missing_LCALTA_20: pass
alsa_mixer-test_event_missing_LCALTA_21: pass
alsa_mixer-test_event_missing_LCALTA_22: pass
alsa_mixer-test_event_missing_LCALTA_23: pass
alsa_mixer-test_event_missing_LCALTA_24: pass
alsa_mixer-test_event_missing_LCALTA_25: pass
alsa_mixer-test_event_missing_LCALTA_26: pass
alsa_mixer-test_event_missing_LCALTA_27: pass
alsa_mixer-test_event_missing_LCALTA_28: pass
alsa_mixer-test_event_missing_LCALTA_29: pass
alsa_mixer-test_event_missing_LCALTA_3: pass
alsa_mixer-test_event_missing_LCALTA_30: pass
alsa_mixer-test_event_missing_LCALTA_31: pass
alsa_mixer-test_event_missing_LCALTA_32: pass
alsa_mixer-test_event_missing_LCALTA_33: pass
alsa_mixer-test_event_missing_LCALTA_34: pass
alsa_mixer-test_event_missing_LCALTA_35: pass
alsa_mixer-test_event_missing_LCALTA_36: pass
alsa_mixer-test_event_missing_LCALTA_37: pass
alsa_mixer-test_event_missing_LCALTA_38: pass
alsa_mixer-test_event_missing_LCALTA_39: pass
alsa_mixer-test_event_missing_LCALTA_4: pass
alsa_mixer-test_event_missing_LCALTA_40: pass
alsa_mixer-test_event_missing_LCALTA_41: pass
alsa_mixer-test_event_missing_LCALTA_42: pass
alsa_mixer-test_event_missing_LCALTA_43: pass
alsa_mixer-test_event_missing_LCALTA_44: pass
alsa_mixer-test_event_missing_LCALTA_45: pass
alsa_mixer-test_event_missing_LCALTA_46: pass
alsa_mixer-test_event_missing_LCALTA_47: pass
alsa_mixer-test_event_missing_LCALTA_48: pass
alsa_mixer-test_event_missing_LCALTA_49: pass
alsa_mixer-test_event_missing_LCALTA_5: pass
alsa_mixer-test_event_missing_LCALTA_50: pass
alsa_mixer-test_event_missing_LCALTA_51: pass
alsa_mixer-test_event_missing_LCALTA_52: pass
alsa_mixer-test_event_missing_LCALTA_53: pass
alsa_mixer-test_event_missing_LCALTA_54: pass
alsa_mixer-test_event_missing_LCALTA_55: pass
alsa_mixer-test_event_missing_LCALTA_56: pass
alsa_mixer-test_event_missing_LCALTA_57: pass
alsa_mixer-test_event_missing_LCALTA_58: pass
alsa_mixer-test_event_missing_LCALTA_59: pass
alsa_mixer-test_event_missing_LCALTA_6: pass
alsa_mixer-test_event_missing_LCALTA_60: pass
alsa_mixer-test_event_missing_LCALTA_7: pass
alsa_mixer-test_event_missing_LCALTA_8: pass
alsa_mixer-test_event_missing_LCALTA_9: pass
alsa_mixer-test_event_spurious_LCALTA_0: pass
alsa_mixer-test_event_spurious_LCALTA_1: pass
alsa_mixer-test_event_spurious_LCALTA_10: pass
alsa_mixer-test_event_spurious_LCALTA_11: pass
alsa_mixer-test_event_spurious_LCALTA_12: pass
alsa_mixer-test_event_spurious_LCALTA_13: pass
alsa_mixer-test_event_spurious_LCALTA_14: pass
alsa_mixer-test_event_spurious_LCALTA_15: pass
alsa_mixer-test_event_spurious_LCALTA_16: pass
alsa_mixer-test_event_spurious_LCALTA_17: pass
alsa_mixer-test_event_spurious_LCALTA_18: pass
alsa_mixer-test_event_spurious_LCALTA_19: pass
alsa_mixer-test_event_spurious_LCALTA_2: pass
alsa_mixer-test_event_spurious_LCALTA_20: pass
alsa_mixer-test_event_spurious_LCALTA_21: pass
alsa_mixer-test_event_spurious_LCALTA_22: pass
alsa_mixer-test_event_spurious_LCALTA_23: pass
alsa_mixer-test_event_spurious_LCALTA_24: pass
alsa_mixer-test_event_spurious_LCALTA_25: pass
alsa_mixer-test_event_spurious_LCALTA_26: pass
alsa_mixer-test_event_spurious_LCALTA_27: pass
alsa_mixer-test_event_spurious_LCALTA_28: pass
alsa_mixer-test_event_spurious_LCALTA_29: pass
alsa_mixer-test_event_spurious_LCALTA_3: pass
alsa_mixer-test_event_spurious_LCALTA_30: pass
alsa_mixer-test_event_spurious_LCALTA_31: pass
alsa_mixer-test_event_spurious_LCALTA_32: pass
alsa_mixer-test_event_spurious_LCALTA_33: pass
alsa_mixer-test_event_spurious_LCALTA_34: pass
alsa_mixer-test_event_spurious_LCALTA_35: pass
alsa_mixer-test_event_spurious_LCALTA_36: pass
alsa_mixer-test_event_spurious_LCALTA_37: pass
alsa_mixer-test_event_spurious_LCALTA_38: pass
alsa_mixer-test_event_spurious_LCALTA_39: pass
alsa_mixer-test_event_spurious_LCALTA_4: pass
alsa_mixer-test_event_spurious_LCALTA_40: pass
alsa_mixer-test_event_spurious_LCALTA_41: pass
alsa_mixer-test_event_spurious_LCALTA_42: pass
alsa_mixer-test_event_spurious_LCALTA_43: pass
alsa_mixer-test_event_spurious_LCALTA_44: pass
alsa_mixer-test_event_spurious_LCALTA_45: pass
alsa_mixer-test_event_spurious_LCALTA_46: pass
alsa_mixer-test_event_spurious_LCALTA_47: pass
alsa_mixer-test_event_spurious_LCALTA_48: pass
alsa_mixer-test_event_spurious_LCALTA_49: pass
alsa_mixer-test_event_spurious_LCALTA_5: pass
alsa_mixer-test_event_spurious_LCALTA_50: pass
alsa_mixer-test_event_spurious_LCALTA_51: pass
alsa_mixer-test_event_spurious_LCALTA_52: pass
alsa_mixer-test_event_spurious_LCALTA_53: pass
alsa_mixer-test_event_spurious_LCALTA_54: pass
alsa_mixer-test_event_spurious_LCALTA_55: pass
alsa_mixer-test_event_spurious_LCALTA_56: pass
alsa_mixer-test_event_spurious_LCALTA_57: pass
alsa_mixer-test_event_spurious_LCALTA_58: pass
alsa_mixer-test_event_spurious_LCALTA_59: pass
alsa_mixer-test_event_spurious_LCALTA_6: pass
alsa_mixer-test_event_spurious_LCALTA_60: pass
alsa_mixer-test_event_spurious_LCALTA_7: pass
alsa_mixer-test_event_spurious_LCALTA_8: pass
alsa_mixer-test_event_spurious_LCALTA_9: pass
alsa_mixer-test_get_value_LCALTA_0: pass
alsa_mixer-test_get_value_LCALTA_1: pass
alsa_mixer-test_get_value_LCALTA_10: pass
alsa_mixer-test_get_value_LCALTA_11: pass
alsa_mixer-test_get_value_LCALTA_12: pass
alsa_mixer-test_get_value_LCALTA_13: pass
alsa_mixer-test_get_value_LCALTA_14: pass
alsa_mixer-test_get_value_LCALTA_15: pass
alsa_mixer-test_get_value_LCALTA_16: pass
alsa_mixer-test_get_value_LCALTA_17: pass
alsa_mixer-test_get_value_LCALTA_18: pass
alsa_mixer-test_get_value_LCALTA_19: pass
alsa_mixer-test_get_value_LCALTA_2: pass
alsa_mixer-test_get_value_LCALTA_20: pass
alsa_mixer-test_get_value_LCALTA_21: pass
alsa_mixer-test_get_value_LCALTA_22: pass
alsa_mixer-test_get_value_LCALTA_23: pass
alsa_mixer-test_get_value_LCALTA_24: pass
alsa_mixer-test_get_value_LCALTA_25: pass
alsa_mixer-test_get_value_LCALTA_26: pass
alsa_mixer-test_get_value_LCALTA_27: pass
alsa_mixer-test_get_value_LCALTA_28: pass
alsa_mixer-test_get_value_LCALTA_29: pass
alsa_mixer-test_get_value_LCALTA_3: pass
alsa_mixer-test_get_value_LCALTA_30: pass
alsa_mixer-test_get_value_LCALTA_31: pass
alsa_mixer-test_get_value_LCALTA_32: pass
alsa_mixer-test_get_value_LCALTA_33: pass
alsa_mixer-test_get_value_LCALTA_34: pass
alsa_mixer-test_get_value_LCALTA_35: pass
alsa_mixer-test_get_value_LCALTA_36: pass
alsa_mixer-test_get_value_LCALTA_37: pass
alsa_mixer-test_get_value_LCALTA_38: pass
alsa_mixer-test_get_value_LCALTA_39: pass
alsa_mixer-test_get_value_LCALTA_4: pass
alsa_mixer-test_get_value_LCALTA_40: pass
alsa_mixer-test_get_value_LCALTA_41: pass
alsa_mixer-test_get_value_LCALTA_42: pass
alsa_mixer-test_get_value_LCALTA_43: pass
alsa_mixer-test_get_value_LCALTA_44: pass
alsa_mixer-test_get_value_LCALTA_45: pass
alsa_mixer-test_get_value_LCALTA_46: pass
alsa_mixer-test_get_value_LCALTA_47: pass
alsa_mixer-test_get_value_LCALTA_48: pass
alsa_mixer-test_get_value_LCALTA_49: pass
alsa_mixer-test_get_value_LCALTA_5: pass
alsa_mixer-test_get_value_LCALTA_50: pass
alsa_mixer-test_get_value_LCALTA_51: pass
alsa_mixer-test_get_value_LCALTA_52: pass
alsa_mixer-test_get_value_LCALTA_53: pass
alsa_mixer-test_get_value_LCALTA_54: pass
alsa_mixer-test_get_value_LCALTA_55: pass
alsa_mixer-test_get_value_LCALTA_56: pass
alsa_mixer-test_get_value_LCALTA_57: pass
alsa_mixer-test_get_value_LCALTA_58: pass
alsa_mixer-test_get_value_LCALTA_59: pass
alsa_mixer-test_get_value_LCALTA_6: pass
alsa_mixer-test_get_value_LCALTA_60: pass
alsa_mixer-test_get_value_LCALTA_7: pass
alsa_mixer-test_get_value_LCALTA_8: pass
alsa_mixer-test_get_value_LCALTA_9: pass
alsa_mixer-test_name_LCALTA_0: pass
alsa_mixer-test_name_LCALTA_1: pass
alsa_mixer-test_name_LCALTA_10: pass
alsa_mixer-test_name_LCALTA_11: pass
alsa_mixer-test_name_LCALTA_12: pass
alsa_mixer-test_name_LCALTA_13: pass
alsa_mixer-test_name_LCALTA_14: pass
alsa_mixer-test_name_LCALTA_15: pass
alsa_mixer-test_name_LCALTA_16: pass
alsa_mixer-test_name_LCALTA_17: pass
alsa_mixer-test_name_LCALTA_18: pass
alsa_mixer-test_name_LCALTA_19: pass
alsa_mixer-test_name_LCALTA_2: pass
alsa_mixer-test_name_LCALTA_20: pass
alsa_mixer-test_name_LCALTA_21: pass
alsa_mixer-test_name_LCALTA_22: pass
alsa_mixer-test_name_LCALTA_23: pass
alsa_mixer-test_name_LCALTA_24: pass
alsa_mixer-test_name_LCALTA_25: pass
alsa_mixer-test_name_LCALTA_26: pass
alsa_mixer-test_name_LCALTA_27: pass
alsa_mixer-test_name_LCALTA_28: pass
alsa_mixer-test_name_LCALTA_29: pass
alsa_mixer-test_name_LCALTA_3: pass
alsa_mixer-test_name_LCALTA_30: pass
alsa_mixer-test_name_LCALTA_31: pass
alsa_mixer-test_name_LCALTA_32: pass
alsa_mixer-test_name_LCALTA_33: pass
alsa_mixer-test_name_LCALTA_34: pass
alsa_mixer-test_name_LCALTA_35: pass
alsa_mixer-test_name_LCALTA_36: pass
alsa_mixer-test_name_LCALTA_37: pass
alsa_mixer-test_name_LCALTA_38: pass
alsa_mixer-test_name_LCALTA_39: pass
alsa_mixer-test_name_LCALTA_4: pass
alsa_mixer-test_name_LCALTA_40: pass
alsa_mixer-test_name_LCALTA_41: pass
alsa_mixer-test_name_LCALTA_42: pass
alsa_mixer-test_name_LCALTA_43: pass
alsa_mixer-test_name_LCALTA_44: pass
alsa_mixer-test_name_LCALTA_45: pass
alsa_mixer-test_name_LCALTA_46: pass
alsa_mixer-test_name_LCALTA_47: pass
alsa_mixer-test_name_LCALTA_48: pass
alsa_mixer-test_name_LCALTA_49: pass
alsa_mixer-test_name_LCALTA_5: pass
alsa_mixer-test_name_LCALTA_50: pass
alsa_mixer-test_name_LCALTA_51: pass
alsa_mixer-test_name_LCALTA_52: pass
alsa_mixer-test_name_LCALTA_53: pass
alsa_mixer-test_name_LCALTA_54: pass
alsa_mixer-test_name_LCALTA_55: pass
alsa_mixer-test_name_LCALTA_56: pass
alsa_mixer-test_name_LCALTA_57: pass
alsa_mixer-test_name_LCALTA_58: pass
alsa_mixer-test_name_LCALTA_59: pass
alsa_mixer-test_name_LCALTA_6: pass
alsa_mixer-test_name_LCALTA_60: pass
alsa_mixer-test_name_LCALTA_7: pass
alsa_mixer-test_name_LCALTA_8: pass
alsa_mixer-test_name_LCALTA_9: pass
alsa_mixer-test_write_default_LCALTA_0: pass
alsa_mixer-test_write_default_LCALTA_1: pass
alsa_mixer-test_write_default_LCALTA_10: pass
alsa_mixer-test_write_default_LCALTA_11: pass
alsa_mixer-test_write_default_LCALTA_12: pass
alsa_mixer-test_write_default_LCALTA_13: pass
alsa_mixer-test_write_default_LCALTA_14: pass
alsa_mixer-test_write_default_LCALTA_15: pass
alsa_mixer-test_write_default_LCALTA_16: pass
alsa_mixer-test_write_default_LCALTA_17: pass
alsa_mixer-test_write_default_LCALTA_18: pass
alsa_mixer-test_write_default_LCALTA_19: pass
alsa_mixer-test_write_default_LCALTA_2: pass
alsa_mixer-test_write_default_LCALTA_20: pass
alsa_mixer-test_write_default_LCALTA_21: pass
alsa_mixer-test_write_default_LCALTA_22: pass
alsa_mixer-test_write_default_LCALTA_23: skip
alsa_mixer-test_write_default_LCALTA_24: skip
alsa_mixer-test_write_default_LCALTA_25: pass
alsa_mixer-test_write_default_LCALTA_26: skip
alsa_mixer-test_write_default_LCALTA_27: pass
alsa_mixer-test_write_default_LCALTA_28: pass
alsa_mixer-test_write_default_LCALTA_29: pass
alsa_mixer-test_write_default_LCALTA_3: pass
alsa_mixer-test_write_default_LCALTA_30: pass
alsa_mixer-test_write_default_LCALTA_31: pass
alsa_mixer-test_write_default_LCALTA_32: pass
alsa_mixer-test_write_default_LCALTA_33: pass
alsa_mixer-test_write_default_LCALTA_34: pass
alsa_mixer-test_write_default_LCALTA_35: pass
alsa_mixer-test_write_default_LCALTA_36: pass
alsa_mixer-test_write_default_LCALTA_37: pass
alsa_mixer-test_write_default_LCALTA_38: pass
alsa_mixer-test_write_default_LCALTA_39: pass
alsa_mixer-test_write_default_LCALTA_4: pass
alsa_mixer-test_write_default_LCALTA_40: pass
alsa_mixer-test_write_default_LCALTA_41: pass
alsa_mixer-test_write_default_LCALTA_42: pass
alsa_mixer-test_write_default_LCALTA_43: pass
alsa_mixer-test_write_default_LCALTA_44: pass
alsa_mixer-test_write_default_LCALTA_45: pass
alsa_mixer-test_write_default_LCALTA_46: pass
alsa_mixer-test_write_default_LCALTA_47: pass
alsa_mixer-test_write_default_LCALTA_48: pass
alsa_mixer-test_write_default_LCALTA_49: pass
alsa_mixer-test_write_default_LCALTA_5: pass
alsa_mixer-test_write_default_LCALTA_50: pass
alsa_mixer-test_write_default_LCALTA_51: pass
alsa_mixer-test_write_default_LCALTA_52: pass
alsa_mixer-test_write_default_LCALTA_53: pass
alsa_mixer-test_write_default_LCALTA_54: pass
alsa_mixer-test_write_default_LCALTA_55: pass
alsa_mixer-test_write_default_LCALTA_56: pass
alsa_mixer-test_write_default_LCALTA_57: pass
alsa_mixer-test_write_default_LCALTA_58: pass
alsa_mixer-test_write_default_LCALTA_59: pass
alsa_mixer-test_write_default_LCALTA_6: pass
alsa_mixer-test_write_default_LCALTA_60: pass
alsa_mixer-test_write_default_LCALTA_7: pass
alsa_mixer-test_write_default_LCALTA_8: pass
alsa_mixer-test_write_default_LCALTA_9: pass
alsa_mixer-test_write_invalid_LCALTA_0: pass
alsa_mixer-test_write_invalid_LCALTA_1: pass
alsa_mixer-test_write_invalid_LCALTA_10: pass
alsa_mixer-test_write_invalid_LCALTA_11: pass
alsa_mixer-test_write_invalid_LCALTA_12: pass
alsa_mixer-test_write_invalid_LCALTA_13: pass
alsa_mixer-test_write_invalid_LCALTA_14: pass
alsa_mixer-test_write_invalid_LCALTA_15: pass
alsa_mixer-test_write_invalid_LCALTA_16: pass
alsa_mixer-test_write_invalid_LCALTA_17: pass
alsa_mixer-test_write_invalid_LCALTA_18: pass
alsa_mixer-test_write_invalid_LCALTA_19: pass
alsa_mixer-test_write_invalid_LCALTA_2: pass
alsa_mixer-test_write_invalid_LCALTA_20: pass
alsa_mixer-test_write_invalid_LCALTA_21: pass
alsa_mixer-test_write_invalid_LCALTA_22: pass
alsa_mixer-test_write_invalid_LCALTA_23: skip
alsa_mixer-test_write_invalid_LCALTA_24: skip
alsa_mixer-test_write_invalid_LCALTA_25: skip
alsa_mixer-test_write_invalid_LCALTA_26: skip
alsa_mixer-test_write_invalid_LCALTA_27: pass
alsa_mixer-test_write_invalid_LCALTA_28: pass
alsa_mixer-test_write_invalid_LCALTA_29: pass
alsa_mixer-test_write_invalid_LCALTA_3: pass
alsa_mixer-test_write_invalid_LCALTA_30: pass
alsa_mixer-test_write_invalid_LCALTA_31: pass
alsa_mixer-test_write_invalid_LCALTA_32: pass
alsa_mixer-test_write_invalid_LCALTA_33: pass
alsa_mixer-test_write_invalid_LCALTA_34: pass
alsa_mixer-test_write_invalid_LCALTA_35: pass
alsa_mixer-test_write_invalid_LCALTA_36: pass
alsa_mixer-test_write_invalid_LCALTA_37: pass
alsa_mixer-test_write_invalid_LCALTA_38: pass
alsa_mixer-test_write_invalid_LCALTA_39: pass
alsa_mixer-test_write_invalid_LCALTA_4: pass
alsa_mixer-test_write_invalid_LCALTA_40: pass
alsa_mixer-test_write_invalid_LCALTA_41: pass
alsa_mixer-test_write_invalid_LCALTA_42: pass
alsa_mixer-test_write_invalid_LCALTA_43: pass
alsa_mixer-test_write_invalid_LCALTA_44: pass
alsa_mixer-test_write_invalid_LCALTA_45: pass
alsa_mixer-test_write_invalid_LCALTA_46: pass
alsa_mixer-test_write_invalid_LCALTA_47: pass
alsa_mixer-test_write_invalid_LCALTA_48: pass
alsa_mixer-test_write_invalid_LCALTA_49: pass
alsa_mixer-test_write_invalid_LCALTA_5: pass
alsa_mixer-test_write_invalid_LCALTA_50: pass
alsa_mixer-test_write_invalid_LCALTA_51: pass
alsa_mixer-test_write_invalid_LCALTA_52: pass
alsa_mixer-test_write_invalid_LCALTA_53: pass
alsa_mixer-test_write_invalid_LCALTA_54: pass
alsa_mixer-test_write_invalid_LCALTA_55: pass
alsa_mixer-test_write_invalid_LCALTA_56: pass
alsa_mixer-test_write_invalid_LCALTA_57: pass
alsa_mixer-test_write_invalid_LCALTA_58: pass
alsa_mixer-test_write_invalid_LCALTA_59: pass
alsa_mixer-test_write_invalid_LCALTA_6: pass
alsa_mixer-test_write_invalid_LCALTA_60: pass
alsa_mixer-test_write_invalid_LCALTA_7: pass
alsa_mixer-test_write_invalid_LCALTA_8: pass
alsa_mixer-test_write_invalid_LCALTA_9: pass
alsa_mixer-test_write_valid_LCALTA_0: pass
alsa_mixer-test_write_valid_LCALTA_1: pass
alsa_mixer-test_write_valid_LCALTA_10: pass
alsa_mixer-test_write_valid_LCALTA_11: pass
alsa_mixer-test_write_valid_LCALTA_12: pass
alsa_mixer-test_write_valid_LCALTA_13: pass
alsa_mixer-test_write_valid_LCALTA_14: pass
alsa_mixer-test_write_valid_LCALTA_15: pass
alsa_mixer-test_write_valid_LCALTA_16: pass
alsa_mixer-test_write_valid_LCALTA_17: pass
alsa_mixer-test_write_valid_LCALTA_18: pass
alsa_mixer-test_write_valid_LCALTA_19: pass
alsa_mixer-test_write_valid_LCALTA_2: pass
alsa_mixer-test_write_valid_LCALTA_20: pass
alsa_mixer-test_write_valid_LCALTA_21: pass
alsa_mixer-test_write_valid_LCALTA_22: pass
alsa_mixer-test_write_valid_LCALTA_23: skip
alsa_mixer-test_write_valid_LCALTA_24: skip
alsa_mixer-test_write_valid_LCALTA_25: skip
alsa_mixer-test_write_valid_LCALTA_26: skip
alsa_mixer-test_write_valid_LCALTA_27: pass
alsa_mixer-test_write_valid_LCALTA_28: pass
alsa_mixer-test_write_valid_LCALTA_29: pass
alsa_mixer-test_write_valid_LCALTA_3: pass
alsa_mixer-test_write_valid_LCALTA_30: pass
alsa_mixer-test_write_valid_LCALTA_31: pass
alsa_mixer-test_write_valid_LCALTA_32: pass
alsa_mixer-test_write_valid_LCALTA_33: pass
alsa_mixer-test_write_valid_LCALTA_34: pass
alsa_mixer-test_write_valid_LCALTA_35: pass
alsa_mixer-test_write_valid_LCALTA_36: pass
alsa_mixer-test_write_valid_LCALTA_37: pass
alsa_mixer-test_write_valid_LCALTA_38: pass
alsa_mixer-test_write_valid_LCALTA_39: pass
alsa_mixer-test_write_valid_LCALTA_4: pass
alsa_mixer-test_write_valid_LCALTA_40: pass
alsa_mixer-test_write_valid_LCALTA_41: pass
alsa_mixer-test_write_valid_LCALTA_42: pass
alsa_mixer-test_write_valid_LCALTA_43: pass
alsa_mixer-test_write_valid_LCALTA_44: pass
alsa_mixer-test_write_valid_LCALTA_45: pass
alsa_mixer-test_write_valid_LCALTA_46: pass
alsa_mixer-test_write_valid_LCALTA_47: pass
alsa_mixer-test_write_valid_LCALTA_48: pass
alsa_mixer-test_write_valid_LCALTA_49: pass
alsa_mixer-test_write_valid_LCALTA_5: pass
alsa_mixer-test_write_valid_LCALTA_50: pass
alsa_mixer-test_write_valid_LCALTA_51: pass
alsa_mixer-test_write_valid_LCALTA_52: pass
alsa_mixer-test_write_valid_LCALTA_53: pass
alsa_mixer-test_write_valid_LCALTA_54: pass
alsa_mixer-test_write_valid_LCALTA_55: pass
alsa_mixer-test_write_valid_LCALTA_56: pass
alsa_mixer-test_write_valid_LCALTA_57: pass
alsa_mixer-test_write_valid_LCALTA_58: pass
alsa_mixer-test_write_valid_LCALTA_59: pass
alsa_mixer-test_write_valid_LCALTA_6: pass
alsa_mixer-test_write_valid_LCALTA_60: pass
alsa_mixer-test_write_valid_LCALTA_7: pass
alsa_mixer-test_write_valid_LCALTA_8: pass
alsa_mixer-test_write_valid_LCALTA_9: pass
alsa_pcm-test: pass
alsa_pcm-test_default_time1_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time1_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time1_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time1_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time1_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time1_LCALTA_5_0_CAPTURE: skip
alsa_pcm-test_default_time2_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time2_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time2_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time2_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time2_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time2_LCALTA_5_0_CAPTURE: skip
alsa_pcm-test_default_time3_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time3_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time3_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time3_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time3_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time3_LCALTA_5_0_CAPTURE: skip
alsa_pcm-test_default_time4_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time4_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time4_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time4_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time4_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time4_LCALTA_5_0_CAPTURE: skip
alsa_pcm-test_default_time5_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time5_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time5_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time5_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time5_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time5_LCALTA_5_0_CAPTURE: skip
alsa_pcm-test_default_time6_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time6_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time6_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time6_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time6_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time6_LCALTA_5_0_CAPTURE: skip
alsa_pcm-test_default_time7_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time7_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time7_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time7_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time7_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time7_LCALTA_5_0_CAPTURE: skip
alsa_test-pcmtest-driver: pass
alsa_test-pcmtest-driver_pcmtest_capture_Can_t_read_patterns_Probably_module_isn_t_loaded: skip
alsa_test-pcmtest-driver_pcmtest_ni_capture_Can_t_read_patterns_Probably_module_isn_t_loaded: skip
alsa_test-pcmtest-driver_pcmtest_ni_playback_Can_t_read_patterns_Probably_module_isn_t_loaded: skip
alsa_test-pcmtest-driver_pcmtest_playback_Can_t_read_patterns_Probably_module_isn_t_loaded: skip
alsa_test-pcmtest-driver_pcmtest_reset_ioctl_Can_t_read_patterns_Probably_module_isn_t_loaded: skip
alsa_utimer-test: fail
alsa_utimer-test_global_wrong_timers_test: pass
alsa_utimer-test_timer_f_utimer: fail
shardfile-alsa: pass
4373 08:27:04.084894 end: 3.1 lava-test-shell (duration 00:00:41) [common]
4374 08:27:04.085560 end: 3 lava-test-retry (duration 00:00:41) [common]
4375 08:27:04.086197 start: 4 finalize (timeout 00:06:12) [common]
4376 08:27:04.086835 start: 4.1 power-off (timeout 00:00:30) [common]
4377 08:27:04.087893 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
4378 08:27:04.124666 >> OK - accepted request
4379 08:27:04.126825 Returned 0 in 0 seconds
4380 08:27:04.228111 end: 4.1 power-off (duration 00:00:00) [common]
4382 08:27:04.229947 start: 4.2 read-feedback (timeout 00:06:12) [common]
4383 08:27:04.231148 Listened to connection for namespace 'common' for up to 1s
4384 08:27:05.231955 Finalising connection for namespace 'common'
4385 08:27:05.232792 Disconnecting from shell: Finalise
4386 08:27:05.233426 / #
4387 08:27:05.334572 end: 4.2 read-feedback (duration 00:00:01) [common]
4388 08:27:05.335376 end: 4 finalize (duration 00:00:01) [common]
4389 08:27:05.336132 Cleaning after the job
4390 08:27:05.336782 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/978668/tftp-deploy-ojpnit67/ramdisk
4391 08:27:05.352714 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/978668/tftp-deploy-ojpnit67/kernel
4392 08:27:05.401621 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/978668/tftp-deploy-ojpnit67/dtb
4393 08:27:05.402486 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/978668/tftp-deploy-ojpnit67/nfsrootfs
4394 08:27:05.592222 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/978668/tftp-deploy-ojpnit67/modules
4395 08:27:05.615161 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/978668
4396 08:27:08.914854 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/978668
4397 08:27:08.915619 Job finished correctly