Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 08:19:35.887558 lava-dispatcher, installed at version: 2024.01
2 08:19:35.888378 start: 0 validate
3 08:19:35.888859 Start time: 2024-11-12 08:19:35.888828+00:00 (UTC)
4 08:19:35.889395 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 08:19:35.889952 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-gst-fluster%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 08:19:35.933508 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 08:19:35.934043 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241112%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 08:19:35.963187 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 08:19:35.963801 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241112%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 08:19:35.994523 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 08:19:35.995017 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-gst-fluster%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 08:19:36.025737 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 08:19:36.026234 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241112%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
14 08:19:36.064114 validate duration: 0.18
16 08:19:36.064964 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 08:19:36.065292 start: 1.1 download-retry (timeout 00:10:00) [common]
18 08:19:36.065612 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 08:19:36.066188 Not decompressing ramdisk as can be used compressed.
20 08:19:36.066637 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-gst-fluster/20240313.0/arm64/initrd.cpio.gz
21 08:19:36.066922 saving as /var/lib/lava/dispatcher/tmp/978663/tftp-deploy-pf_42i5m/ramdisk/initrd.cpio.gz
22 08:19:36.067199 total size: 5628140 (5 MB)
23 08:19:36.101060 progress 0 % (0 MB)
24 08:19:36.106121 progress 5 % (0 MB)
25 08:19:36.113824 progress 10 % (0 MB)
26 08:19:36.120656 progress 15 % (0 MB)
27 08:19:36.126242 progress 20 % (1 MB)
28 08:19:36.129863 progress 25 % (1 MB)
29 08:19:36.133936 progress 30 % (1 MB)
30 08:19:36.137878 progress 35 % (1 MB)
31 08:19:36.141429 progress 40 % (2 MB)
32 08:19:36.145352 progress 45 % (2 MB)
33 08:19:36.148887 progress 50 % (2 MB)
34 08:19:36.152849 progress 55 % (2 MB)
35 08:19:36.156800 progress 60 % (3 MB)
36 08:19:36.160335 progress 65 % (3 MB)
37 08:19:36.164252 progress 70 % (3 MB)
38 08:19:36.167747 progress 75 % (4 MB)
39 08:19:36.171693 progress 80 % (4 MB)
40 08:19:36.175209 progress 85 % (4 MB)
41 08:19:36.179171 progress 90 % (4 MB)
42 08:19:36.182968 progress 95 % (5 MB)
43 08:19:36.186190 progress 100 % (5 MB)
44 08:19:36.186830 5 MB downloaded in 0.12 s (44.87 MB/s)
45 08:19:36.187383 end: 1.1.1 http-download (duration 00:00:00) [common]
47 08:19:36.188304 end: 1.1 download-retry (duration 00:00:00) [common]
48 08:19:36.188601 start: 1.2 download-retry (timeout 00:10:00) [common]
49 08:19:36.188873 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 08:19:36.189346 downloading http://storage.kernelci.org/next/master/next-20241112/arm64/defconfig/gcc-12/kernel/Image
51 08:19:36.189593 saving as /var/lib/lava/dispatcher/tmp/978663/tftp-deploy-pf_42i5m/kernel/Image
52 08:19:36.189803 total size: 46121472 (43 MB)
53 08:19:36.190014 No compression specified
54 08:19:36.227565 progress 0 % (0 MB)
55 08:19:36.255908 progress 5 % (2 MB)
56 08:19:36.283956 progress 10 % (4 MB)
57 08:19:36.313554 progress 15 % (6 MB)
58 08:19:36.344671 progress 20 % (8 MB)
59 08:19:36.373622 progress 25 % (11 MB)
60 08:19:36.401803 progress 30 % (13 MB)
61 08:19:36.429569 progress 35 % (15 MB)
62 08:19:36.457720 progress 40 % (17 MB)
63 08:19:36.485648 progress 45 % (19 MB)
64 08:19:36.513104 progress 50 % (22 MB)
65 08:19:36.541322 progress 55 % (24 MB)
66 08:19:36.568852 progress 60 % (26 MB)
67 08:19:36.596519 progress 65 % (28 MB)
68 08:19:36.624318 progress 70 % (30 MB)
69 08:19:36.651809 progress 75 % (33 MB)
70 08:19:36.680175 progress 80 % (35 MB)
71 08:19:36.707788 progress 85 % (37 MB)
72 08:19:36.735467 progress 90 % (39 MB)
73 08:19:36.763686 progress 95 % (41 MB)
74 08:19:36.790819 progress 100 % (43 MB)
75 08:19:36.791458 43 MB downloaded in 0.60 s (73.11 MB/s)
76 08:19:36.791936 end: 1.2.1 http-download (duration 00:00:01) [common]
78 08:19:36.792780 end: 1.2 download-retry (duration 00:00:01) [common]
79 08:19:36.793060 start: 1.3 download-retry (timeout 00:09:59) [common]
80 08:19:36.793326 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 08:19:36.793793 downloading http://storage.kernelci.org/next/master/next-20241112/arm64/defconfig/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
82 08:19:36.794037 saving as /var/lib/lava/dispatcher/tmp/978663/tftp-deploy-pf_42i5m/dtb/meson-g12b-a311d-libretech-cc.dtb
83 08:19:36.794245 total size: 54703 (0 MB)
84 08:19:36.794455 No compression specified
85 08:19:36.833764 progress 59 % (0 MB)
86 08:19:36.835192 progress 100 % (0 MB)
87 08:19:36.836171 0 MB downloaded in 0.04 s (1.24 MB/s)
88 08:19:36.836657 end: 1.3.1 http-download (duration 00:00:00) [common]
90 08:19:36.837469 end: 1.3 download-retry (duration 00:00:00) [common]
91 08:19:36.837735 start: 1.4 download-retry (timeout 00:09:59) [common]
92 08:19:36.837999 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 08:19:36.838453 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-gst-fluster/20240313.0/arm64/full.rootfs.tar.xz
94 08:19:36.838698 saving as /var/lib/lava/dispatcher/tmp/978663/tftp-deploy-pf_42i5m/nfsrootfs/full.rootfs.tar
95 08:19:36.838905 total size: 474398908 (452 MB)
96 08:19:36.839114 Using unxz to decompress xz
97 08:19:36.874801 progress 0 % (0 MB)
98 08:19:37.963537 progress 5 % (22 MB)
99 08:19:39.398649 progress 10 % (45 MB)
100 08:19:39.827041 progress 15 % (67 MB)
101 08:19:40.652575 progress 20 % (90 MB)
102 08:19:41.183119 progress 25 % (113 MB)
103 08:19:41.537743 progress 30 % (135 MB)
104 08:19:42.138444 progress 35 % (158 MB)
105 08:19:43.050562 progress 40 % (181 MB)
106 08:19:43.798238 progress 45 % (203 MB)
107 08:19:44.341606 progress 50 % (226 MB)
108 08:19:44.986677 progress 55 % (248 MB)
109 08:19:46.208483 progress 60 % (271 MB)
110 08:19:47.698129 progress 65 % (294 MB)
111 08:19:49.343254 progress 70 % (316 MB)
112 08:19:52.421220 progress 75 % (339 MB)
113 08:19:54.899340 progress 80 % (361 MB)
114 08:19:57.803613 progress 85 % (384 MB)
115 08:20:00.973125 progress 90 % (407 MB)
116 08:20:04.138697 progress 95 % (429 MB)
117 08:20:07.267950 progress 100 % (452 MB)
118 08:20:07.280775 452 MB downloaded in 30.44 s (14.86 MB/s)
119 08:20:07.281712 end: 1.4.1 http-download (duration 00:00:30) [common]
121 08:20:07.283464 end: 1.4 download-retry (duration 00:00:30) [common]
122 08:20:07.284071 start: 1.5 download-retry (timeout 00:09:29) [common]
123 08:20:07.284656 start: 1.5.1 http-download (timeout 00:09:29) [common]
124 08:20:07.285637 downloading http://storage.kernelci.org/next/master/next-20241112/arm64/defconfig/gcc-12/modules.tar.xz
125 08:20:07.286149 saving as /var/lib/lava/dispatcher/tmp/978663/tftp-deploy-pf_42i5m/modules/modules.tar
126 08:20:07.286601 total size: 11690048 (11 MB)
127 08:20:07.287060 Using unxz to decompress xz
128 08:20:07.329220 progress 0 % (0 MB)
129 08:20:07.396464 progress 5 % (0 MB)
130 08:20:07.470294 progress 10 % (1 MB)
131 08:20:07.565201 progress 15 % (1 MB)
132 08:20:07.660346 progress 20 % (2 MB)
133 08:20:07.738973 progress 25 % (2 MB)
134 08:20:07.813986 progress 30 % (3 MB)
135 08:20:07.887171 progress 35 % (3 MB)
136 08:20:07.963385 progress 40 % (4 MB)
137 08:20:08.040949 progress 45 % (5 MB)
138 08:20:08.124970 progress 50 % (5 MB)
139 08:20:08.206384 progress 55 % (6 MB)
140 08:20:08.291465 progress 60 % (6 MB)
141 08:20:08.367157 progress 65 % (7 MB)
142 08:20:08.447856 progress 70 % (7 MB)
143 08:20:08.528973 progress 75 % (8 MB)
144 08:20:08.611533 progress 80 % (8 MB)
145 08:20:08.690717 progress 85 % (9 MB)
146 08:20:08.772833 progress 90 % (10 MB)
147 08:20:08.845339 progress 95 % (10 MB)
148 08:20:08.920913 progress 100 % (11 MB)
149 08:20:08.934323 11 MB downloaded in 1.65 s (6.77 MB/s)
150 08:20:08.934901 end: 1.5.1 http-download (duration 00:00:02) [common]
152 08:20:08.935754 end: 1.5 download-retry (duration 00:00:02) [common]
153 08:20:08.936143 start: 1.6 prepare-tftp-overlay (timeout 00:09:27) [common]
154 08:20:08.936677 start: 1.6.1 extract-nfsrootfs (timeout 00:09:27) [common]
155 08:20:24.085911 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/978663/extract-nfsrootfs-nkbtnt06
156 08:20:24.086507 end: 1.6.1 extract-nfsrootfs (duration 00:00:15) [common]
157 08:20:24.086797 start: 1.6.2 lava-overlay (timeout 00:09:12) [common]
158 08:20:24.087449 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/978663/lava-overlay-ye9y5xhd
159 08:20:24.087899 makedir: /var/lib/lava/dispatcher/tmp/978663/lava-overlay-ye9y5xhd/lava-978663/bin
160 08:20:24.088283 makedir: /var/lib/lava/dispatcher/tmp/978663/lava-overlay-ye9y5xhd/lava-978663/tests
161 08:20:24.088603 makedir: /var/lib/lava/dispatcher/tmp/978663/lava-overlay-ye9y5xhd/lava-978663/results
162 08:20:24.088931 Creating /var/lib/lava/dispatcher/tmp/978663/lava-overlay-ye9y5xhd/lava-978663/bin/lava-add-keys
163 08:20:24.089452 Creating /var/lib/lava/dispatcher/tmp/978663/lava-overlay-ye9y5xhd/lava-978663/bin/lava-add-sources
164 08:20:24.089963 Creating /var/lib/lava/dispatcher/tmp/978663/lava-overlay-ye9y5xhd/lava-978663/bin/lava-background-process-start
165 08:20:24.090467 Creating /var/lib/lava/dispatcher/tmp/978663/lava-overlay-ye9y5xhd/lava-978663/bin/lava-background-process-stop
166 08:20:24.091010 Creating /var/lib/lava/dispatcher/tmp/978663/lava-overlay-ye9y5xhd/lava-978663/bin/lava-common-functions
167 08:20:24.091556 Creating /var/lib/lava/dispatcher/tmp/978663/lava-overlay-ye9y5xhd/lava-978663/bin/lava-echo-ipv4
168 08:20:24.092088 Creating /var/lib/lava/dispatcher/tmp/978663/lava-overlay-ye9y5xhd/lava-978663/bin/lava-install-packages
169 08:20:24.092606 Creating /var/lib/lava/dispatcher/tmp/978663/lava-overlay-ye9y5xhd/lava-978663/bin/lava-installed-packages
170 08:20:24.093114 Creating /var/lib/lava/dispatcher/tmp/978663/lava-overlay-ye9y5xhd/lava-978663/bin/lava-os-build
171 08:20:24.093618 Creating /var/lib/lava/dispatcher/tmp/978663/lava-overlay-ye9y5xhd/lava-978663/bin/lava-probe-channel
172 08:20:24.094113 Creating /var/lib/lava/dispatcher/tmp/978663/lava-overlay-ye9y5xhd/lava-978663/bin/lava-probe-ip
173 08:20:24.094624 Creating /var/lib/lava/dispatcher/tmp/978663/lava-overlay-ye9y5xhd/lava-978663/bin/lava-target-ip
174 08:20:24.095102 Creating /var/lib/lava/dispatcher/tmp/978663/lava-overlay-ye9y5xhd/lava-978663/bin/lava-target-mac
175 08:20:24.095581 Creating /var/lib/lava/dispatcher/tmp/978663/lava-overlay-ye9y5xhd/lava-978663/bin/lava-target-storage
176 08:20:24.096106 Creating /var/lib/lava/dispatcher/tmp/978663/lava-overlay-ye9y5xhd/lava-978663/bin/lava-test-case
177 08:20:24.096620 Creating /var/lib/lava/dispatcher/tmp/978663/lava-overlay-ye9y5xhd/lava-978663/bin/lava-test-event
178 08:20:24.097104 Creating /var/lib/lava/dispatcher/tmp/978663/lava-overlay-ye9y5xhd/lava-978663/bin/lava-test-feedback
179 08:20:24.097583 Creating /var/lib/lava/dispatcher/tmp/978663/lava-overlay-ye9y5xhd/lava-978663/bin/lava-test-raise
180 08:20:24.098057 Creating /var/lib/lava/dispatcher/tmp/978663/lava-overlay-ye9y5xhd/lava-978663/bin/lava-test-reference
181 08:20:24.098599 Creating /var/lib/lava/dispatcher/tmp/978663/lava-overlay-ye9y5xhd/lava-978663/bin/lava-test-runner
182 08:20:24.099098 Creating /var/lib/lava/dispatcher/tmp/978663/lava-overlay-ye9y5xhd/lava-978663/bin/lava-test-set
183 08:20:24.099599 Creating /var/lib/lava/dispatcher/tmp/978663/lava-overlay-ye9y5xhd/lava-978663/bin/lava-test-shell
184 08:20:24.100128 Updating /var/lib/lava/dispatcher/tmp/978663/lava-overlay-ye9y5xhd/lava-978663/bin/lava-install-packages (oe)
185 08:20:24.100675 Updating /var/lib/lava/dispatcher/tmp/978663/lava-overlay-ye9y5xhd/lava-978663/bin/lava-installed-packages (oe)
186 08:20:24.101113 Creating /var/lib/lava/dispatcher/tmp/978663/lava-overlay-ye9y5xhd/lava-978663/environment
187 08:20:24.101486 LAVA metadata
188 08:20:24.101743 - LAVA_JOB_ID=978663
189 08:20:24.101958 - LAVA_DISPATCHER_IP=192.168.6.2
190 08:20:24.102316 start: 1.6.2.1 ssh-authorize (timeout 00:09:12) [common]
191 08:20:24.103265 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
192 08:20:24.103571 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:12) [common]
193 08:20:24.103781 skipped lava-vland-overlay
194 08:20:24.104049 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
195 08:20:24.104309 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:12) [common]
196 08:20:24.104529 skipped lava-multinode-overlay
197 08:20:24.104774 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
198 08:20:24.105027 start: 1.6.2.4 test-definition (timeout 00:09:12) [common]
199 08:20:24.105276 Loading test definitions
200 08:20:24.105552 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:12) [common]
201 08:20:24.105775 Using /lava-978663 at stage 0
202 08:20:24.106913 uuid=978663_1.6.2.4.1 testdef=None
203 08:20:24.107218 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
204 08:20:24.107480 start: 1.6.2.4.2 test-overlay (timeout 00:09:12) [common]
205 08:20:24.109260 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
207 08:20:24.110055 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:12) [common]
208 08:20:24.112240 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
210 08:20:24.113064 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:12) [common]
211 08:20:24.115128 runner path: /var/lib/lava/dispatcher/tmp/978663/lava-overlay-ye9y5xhd/lava-978663/0/tests/0_v4l2-decoder-conformance-h264 test_uuid 978663_1.6.2.4.1
212 08:20:24.115697 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
214 08:20:24.116480 Creating lava-test-runner.conf files
215 08:20:24.116682 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/978663/lava-overlay-ye9y5xhd/lava-978663/0 for stage 0
216 08:20:24.117016 - 0_v4l2-decoder-conformance-h264
217 08:20:24.117357 end: 1.6.2.4 test-definition (duration 00:00:00) [common]
218 08:20:24.117627 start: 1.6.2.5 compress-overlay (timeout 00:09:12) [common]
219 08:20:24.140426 end: 1.6.2.5 compress-overlay (duration 00:00:00) [common]
220 08:20:24.140836 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:09:12) [common]
221 08:20:24.141095 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
222 08:20:24.141359 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
223 08:20:24.141619 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:12) [common]
224 08:20:24.762133 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:01) [common]
225 08:20:24.762614 start: 1.6.4 extract-modules (timeout 00:09:11) [common]
226 08:20:24.762867 extracting modules file /var/lib/lava/dispatcher/tmp/978663/tftp-deploy-pf_42i5m/modules/modules.tar to /var/lib/lava/dispatcher/tmp/978663/extract-nfsrootfs-nkbtnt06
227 08:20:26.105186 extracting modules file /var/lib/lava/dispatcher/tmp/978663/tftp-deploy-pf_42i5m/modules/modules.tar to /var/lib/lava/dispatcher/tmp/978663/extract-overlay-ramdisk-ka3js6zq/ramdisk
228 08:20:27.502668 end: 1.6.4 extract-modules (duration 00:00:03) [common]
229 08:20:27.503146 start: 1.6.5 apply-overlay-tftp (timeout 00:09:09) [common]
230 08:20:27.503420 [common] Applying overlay to NFS
231 08:20:27.503636 [common] Applying overlay /var/lib/lava/dispatcher/tmp/978663/compress-overlay-y3e8cwgn/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/978663/extract-nfsrootfs-nkbtnt06
232 08:20:27.532507 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
233 08:20:27.532874 start: 1.6.6 prepare-kernel (timeout 00:09:09) [common]
234 08:20:27.533142 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:09:09) [common]
235 08:20:27.533367 Converting downloaded kernel to a uImage
236 08:20:27.533670 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/978663/tftp-deploy-pf_42i5m/kernel/Image /var/lib/lava/dispatcher/tmp/978663/tftp-deploy-pf_42i5m/kernel/uImage
237 08:20:27.996007 output: Image Name:
238 08:20:27.996423 output: Created: Tue Nov 12 08:20:27 2024
239 08:20:27.996632 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
240 08:20:27.996836 output: Data Size: 46121472 Bytes = 45040.50 KiB = 43.98 MiB
241 08:20:27.997038 output: Load Address: 01080000
242 08:20:27.997238 output: Entry Point: 01080000
243 08:20:27.997438 output:
244 08:20:27.997773 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
245 08:20:27.998041 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
246 08:20:27.998309 start: 1.6.7 configure-preseed-file (timeout 00:09:08) [common]
247 08:20:27.998565 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
248 08:20:27.998820 start: 1.6.8 compress-ramdisk (timeout 00:09:08) [common]
249 08:20:27.999073 Building ramdisk /var/lib/lava/dispatcher/tmp/978663/extract-overlay-ramdisk-ka3js6zq/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/978663/extract-overlay-ramdisk-ka3js6zq/ramdisk
250 08:20:30.315730 >> 168134 blocks
251 08:20:38.091932 Adding RAMdisk u-boot header.
252 08:20:38.092700 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/978663/extract-overlay-ramdisk-ka3js6zq/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/978663/extract-overlay-ramdisk-ka3js6zq/ramdisk.cpio.gz.uboot
253 08:20:38.341153 output: Image Name:
254 08:20:38.341621 output: Created: Tue Nov 12 08:20:38 2024
255 08:20:38.342076 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
256 08:20:38.342498 output: Data Size: 23563149 Bytes = 23010.89 KiB = 22.47 MiB
257 08:20:38.342932 output: Load Address: 00000000
258 08:20:38.343332 output: Entry Point: 00000000
259 08:20:38.343728 output:
260 08:20:38.344949 rename /var/lib/lava/dispatcher/tmp/978663/extract-overlay-ramdisk-ka3js6zq/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/978663/tftp-deploy-pf_42i5m/ramdisk/ramdisk.cpio.gz.uboot
261 08:20:38.345704 end: 1.6.8 compress-ramdisk (duration 00:00:10) [common]
262 08:20:38.346270 end: 1.6 prepare-tftp-overlay (duration 00:00:29) [common]
263 08:20:38.346813 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:58) [common]
264 08:20:38.347299 No LXC device requested
265 08:20:38.347825 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
266 08:20:38.348433 start: 1.8 deploy-device-env (timeout 00:08:58) [common]
267 08:20:38.348951 end: 1.8 deploy-device-env (duration 00:00:00) [common]
268 08:20:38.349373 Checking files for TFTP limit of 4294967296 bytes.
269 08:20:38.352067 end: 1 tftp-deploy (duration 00:01:02) [common]
270 08:20:38.352667 start: 2 uboot-action (timeout 00:05:00) [common]
271 08:20:38.353211 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
272 08:20:38.353716 end: 2.1 uboot-from-media (duration 00:00:00) [common]
273 08:20:38.354226 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
274 08:20:38.354760 Using kernel file from prepare-kernel: 978663/tftp-deploy-pf_42i5m/kernel/uImage
275 08:20:38.355398 substitutions:
276 08:20:38.355813 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
277 08:20:38.356271 - {DTB_ADDR}: 0x01070000
278 08:20:38.356681 - {DTB}: 978663/tftp-deploy-pf_42i5m/dtb/meson-g12b-a311d-libretech-cc.dtb
279 08:20:38.357084 - {INITRD}: 978663/tftp-deploy-pf_42i5m/ramdisk/ramdisk.cpio.gz.uboot
280 08:20:38.357482 - {KERNEL_ADDR}: 0x01080000
281 08:20:38.357878 - {KERNEL}: 978663/tftp-deploy-pf_42i5m/kernel/uImage
282 08:20:38.358273 - {LAVA_MAC}: None
283 08:20:38.358712 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/978663/extract-nfsrootfs-nkbtnt06
284 08:20:38.359115 - {NFS_SERVER_IP}: 192.168.6.2
285 08:20:38.359532 - {PRESEED_CONFIG}: None
286 08:20:38.359934 - {PRESEED_LOCAL}: None
287 08:20:38.360381 - {RAMDISK_ADDR}: 0x08000000
288 08:20:38.360786 - {RAMDISK}: 978663/tftp-deploy-pf_42i5m/ramdisk/ramdisk.cpio.gz.uboot
289 08:20:38.361190 - {ROOT_PART}: None
290 08:20:38.361584 - {ROOT}: None
291 08:20:38.361973 - {SERVER_IP}: 192.168.6.2
292 08:20:38.362366 - {TEE_ADDR}: 0x83000000
293 08:20:38.362759 - {TEE}: None
294 08:20:38.363152 Parsed boot commands:
295 08:20:38.363534 - setenv autoload no
296 08:20:38.363924 - setenv initrd_high 0xffffffff
297 08:20:38.364378 - setenv fdt_high 0xffffffff
298 08:20:38.364776 - dhcp
299 08:20:38.365169 - setenv serverip 192.168.6.2
300 08:20:38.365560 - tftpboot 0x01080000 978663/tftp-deploy-pf_42i5m/kernel/uImage
301 08:20:38.365951 - tftpboot 0x08000000 978663/tftp-deploy-pf_42i5m/ramdisk/ramdisk.cpio.gz.uboot
302 08:20:38.366342 - tftpboot 0x01070000 978663/tftp-deploy-pf_42i5m/dtb/meson-g12b-a311d-libretech-cc.dtb
303 08:20:38.366731 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/978663/extract-nfsrootfs-nkbtnt06,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
304 08:20:38.367135 - bootm 0x01080000 0x08000000 0x01070000
305 08:20:38.367643 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
307 08:20:38.369185 start: 2.3 connect-device (timeout 00:05:00) [common]
308 08:20:38.369616 [common] connect-device Connecting to device using 'telnet conserv1 3007'
309 08:20:38.383341 Setting prompt string to ['lava-test: # ']
310 08:20:38.384838 end: 2.3 connect-device (duration 00:00:00) [common]
311 08:20:38.385446 start: 2.4 uboot-commands (timeout 00:05:00) [common]
312 08:20:38.385998 start: 2.4.1 reset-device (timeout 00:05:00) [common]
313 08:20:38.386540 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
314 08:20:38.387657 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
315 08:20:38.428460 >> OK - accepted request
316 08:20:38.430870 Returned 0 in 0 seconds
317 08:20:38.532060 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
319 08:20:38.533714 end: 2.4.1 reset-device (duration 00:00:00) [common]
320 08:20:38.534315 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
321 08:20:38.534842 Setting prompt string to ['Hit any key to stop autoboot']
322 08:20:38.535315 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
323 08:20:38.536987 Trying 192.168.56.21...
324 08:20:38.537478 Connected to conserv1.
325 08:20:38.537917 Escape character is '^]'.
326 08:20:38.538346
327 08:20:38.538782 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
328 08:20:38.539204
329 08:20:49.662474 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
330 08:20:49.663070 bl2_stage_init 0x01
331 08:20:49.663520 bl2_stage_init 0x81
332 08:20:49.668090 hw id: 0x0000 - pwm id 0x01
333 08:20:49.668616 bl2_stage_init 0xc1
334 08:20:49.669017 bl2_stage_init 0x02
335 08:20:49.669405
336 08:20:49.673566 L0:00000000
337 08:20:49.673994 L1:20000703
338 08:20:49.674383 L2:00008067
339 08:20:49.674768 L3:14000000
340 08:20:49.679219 B2:00402000
341 08:20:49.679636 B1:e0f83180
342 08:20:49.680076
343 08:20:49.680468 TE: 58159
344 08:20:49.680858
345 08:20:49.684753 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
346 08:20:49.685174
347 08:20:49.685565 Board ID = 1
348 08:20:49.690574 Set A53 clk to 24M
349 08:20:49.690991 Set A73 clk to 24M
350 08:20:49.691378 Set clk81 to 24M
351 08:20:49.696010 A53 clk: 1200 MHz
352 08:20:49.696426 A73 clk: 1200 MHz
353 08:20:49.696812 CLK81: 166.6M
354 08:20:49.697194 smccc: 00012ab5
355 08:20:49.701560 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
356 08:20:49.707229 board id: 1
357 08:20:49.713019 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
358 08:20:49.723700 fw parse done
359 08:20:49.729654 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
360 08:20:49.772328 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
361 08:20:49.783246 PIEI prepare done
362 08:20:49.783677 fastboot data load
363 08:20:49.784118 fastboot data verify
364 08:20:49.788978 verify result: 266
365 08:20:49.794471 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
366 08:20:49.794903 LPDDR4 probe
367 08:20:49.795312 ddr clk to 1584MHz
368 08:20:49.802445 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
369 08:20:49.838836
370 08:20:49.839285 dmc_version 0001
371 08:20:49.845523 Check phy result
372 08:20:49.852384 INFO : End of CA training
373 08:20:49.852823 INFO : End of initialization
374 08:20:49.857964 INFO : Training has run successfully!
375 08:20:49.858393 Check phy result
376 08:20:49.863555 INFO : End of initialization
377 08:20:49.864021 INFO : End of read enable training
378 08:20:49.866873 INFO : End of fine write leveling
379 08:20:49.872498 INFO : End of Write leveling coarse delay
380 08:20:49.878152 INFO : Training has run successfully!
381 08:20:49.878577 Check phy result
382 08:20:49.878979 INFO : End of initialization
383 08:20:49.883551 INFO : End of read dq deskew training
384 08:20:49.886871 INFO : End of MPR read delay center optimization
385 08:20:49.892481 INFO : End of write delay center optimization
386 08:20:49.898064 INFO : End of read delay center optimization
387 08:20:49.898487 INFO : End of max read latency training
388 08:20:49.903593 INFO : Training has run successfully!
389 08:20:49.904057 1D training succeed
390 08:20:49.910970 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
391 08:20:49.958604 Check phy result
392 08:20:49.959063 INFO : End of initialization
393 08:20:49.980180 INFO : End of 2D read delay Voltage center optimization
394 08:20:50.000386 INFO : End of 2D read delay Voltage center optimization
395 08:20:50.052227 INFO : End of 2D write delay Voltage center optimization
396 08:20:50.102435 INFO : End of 2D write delay Voltage center optimization
397 08:20:50.107940 INFO : Training has run successfully!
398 08:20:50.108410
399 08:20:50.108819 channel==0
400 08:20:50.113479 RxClkDly_Margin_A0==88 ps 9
401 08:20:50.113917 TxDqDly_Margin_A0==98 ps 10
402 08:20:50.116745 RxClkDly_Margin_A1==88 ps 9
403 08:20:50.117167 TxDqDly_Margin_A1==98 ps 10
404 08:20:50.122484 TrainedVREFDQ_A0==74
405 08:20:50.122906 TrainedVREFDQ_A1==74
406 08:20:50.127976 VrefDac_Margin_A0==25
407 08:20:50.128429 DeviceVref_Margin_A0==40
408 08:20:50.128833 VrefDac_Margin_A1==25
409 08:20:50.133494 DeviceVref_Margin_A1==40
410 08:20:50.133918
411 08:20:50.134319
412 08:20:50.134713 channel==1
413 08:20:50.135104 RxClkDly_Margin_A0==98 ps 10
414 08:20:50.139096 TxDqDly_Margin_A0==98 ps 10
415 08:20:50.139525 RxClkDly_Margin_A1==88 ps 9
416 08:20:50.144669 TxDqDly_Margin_A1==98 ps 10
417 08:20:50.145098 TrainedVREFDQ_A0==77
418 08:20:50.145500 TrainedVREFDQ_A1==77
419 08:20:50.150344 VrefDac_Margin_A0==22
420 08:20:50.150769 DeviceVref_Margin_A0==37
421 08:20:50.155868 VrefDac_Margin_A1==24
422 08:20:50.156316 DeviceVref_Margin_A1==37
423 08:20:50.156715
424 08:20:50.161473 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
425 08:20:50.161895
426 08:20:50.189543 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000018 00000018 00000016 00000017 00000015 00000018 00000019 00000017 00000019 00000018 0000001a 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
427 08:20:50.195062 2D training succeed
428 08:20:50.200673 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
429 08:20:50.201098 auto size-- 65535DDR cs0 size: 2048MB
430 08:20:50.206346 DDR cs1 size: 2048MB
431 08:20:50.206764 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
432 08:20:50.211882 cs0 DataBus test pass
433 08:20:50.212343 cs1 DataBus test pass
434 08:20:50.212746 cs0 AddrBus test pass
435 08:20:50.217485 cs1 AddrBus test pass
436 08:20:50.217906
437 08:20:50.218304 100bdlr_step_size ps== 420
438 08:20:50.218711 result report
439 08:20:50.223088 boot times 0Enable ddr reg access
440 08:20:50.230866 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
441 08:20:50.244426 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
442 08:20:50.816410 0.0;M3 CHK:0;cm4_sp_mode 0
443 08:20:50.817052 MVN_1=0x00000000
444 08:20:50.821824 MVN_2=0x00000000
445 08:20:50.827568 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
446 08:20:50.828056 OPS=0x10
447 08:20:50.828479 ring efuse init
448 08:20:50.828884 chipver efuse init
449 08:20:50.833158 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
450 08:20:50.838761 [0.018961 Inits done]
451 08:20:50.839185 secure task start!
452 08:20:50.839588 high task start!
453 08:20:50.843498 low task start!
454 08:20:50.843940 run into bl31
455 08:20:50.850015 NOTICE: BL31: v1.3(release):4fc40b1
456 08:20:50.857850 NOTICE: BL31: Built : 15:58:17, May 22 2019
457 08:20:50.858301 NOTICE: BL31: G12A normal boot!
458 08:20:50.883215 NOTICE: BL31: BL33 decompress pass
459 08:20:50.888918 ERROR: Error initializing runtime service opteed_fast
460 08:20:52.121920
461 08:20:52.122526
462 08:20:52.130291 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
463 08:20:52.130736
464 08:20:52.131151 Model: Libre Computer AML-A311D-CC Alta
465 08:20:52.338880 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
466 08:20:52.362108 DRAM: 2 GiB (effective 3.8 GiB)
467 08:20:52.505070 Core: 408 devices, 31 uclasses, devicetree: separate
468 08:20:52.510884 WDT: Not starting watchdog@f0d0
469 08:20:52.543135 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
470 08:20:52.555606 Loading Environment from FAT... Card did not respond to voltage select! : -110
471 08:20:52.560678 ** Bad device specification mmc 0 **
472 08:20:52.570907 Card did not respond to voltage select! : -110
473 08:20:52.578543 ** Bad device specification mmc 0 **
474 08:20:52.578974 Couldn't find partition mmc 0
475 08:20:52.586878 Card did not respond to voltage select! : -110
476 08:20:52.592385 ** Bad device specification mmc 0 **
477 08:20:52.592814 Couldn't find partition mmc 0
478 08:20:52.597454 Error: could not access storage.
479 08:20:53.863709 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
480 08:20:53.864367 bl2_stage_init 0x01
481 08:20:53.864799 bl2_stage_init 0x81
482 08:20:53.869165 hw id: 0x0000 - pwm id 0x01
483 08:20:53.869607 bl2_stage_init 0xc1
484 08:20:53.870021 bl2_stage_init 0x02
485 08:20:53.870426
486 08:20:53.874739 L0:00000000
487 08:20:53.875170 L1:20000703
488 08:20:53.875575 L2:00008067
489 08:20:53.875975 L3:14000000
490 08:20:53.877686 B2:00402000
491 08:20:53.878120 B1:e0f83180
492 08:20:53.878524
493 08:20:53.878925 TE: 58159
494 08:20:53.879324
495 08:20:53.888839 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
496 08:20:53.889289
497 08:20:53.889699 Board ID = 1
498 08:20:53.890097 Set A53 clk to 24M
499 08:20:53.890493 Set A73 clk to 24M
500 08:20:53.894461 Set clk81 to 24M
501 08:20:53.894885 A53 clk: 1200 MHz
502 08:20:53.895287 A73 clk: 1200 MHz
503 08:20:53.897750 CLK81: 166.6M
504 08:20:53.898186 smccc: 00012ab5
505 08:20:53.903405 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
506 08:20:53.908952 board id: 1
507 08:20:53.914237 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
508 08:20:53.924884 fw parse done
509 08:20:53.930867 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
510 08:20:53.973487 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
511 08:20:53.984519 PIEI prepare done
512 08:20:53.984960 fastboot data load
513 08:20:53.985366 fastboot data verify
514 08:20:53.990056 verify result: 266
515 08:20:53.995726 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
516 08:20:53.996214 LPDDR4 probe
517 08:20:53.996627 ddr clk to 1584MHz
518 08:20:54.003725 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
519 08:20:54.041016
520 08:20:54.041499 dmc_version 0001
521 08:20:54.047552 Check phy result
522 08:20:54.053379 INFO : End of CA training
523 08:20:54.053818 INFO : End of initialization
524 08:20:54.059162 INFO : Training has run successfully!
525 08:20:54.059592 Check phy result
526 08:20:54.064840 INFO : End of initialization
527 08:20:54.065288 INFO : End of read enable training
528 08:20:54.070416 INFO : End of fine write leveling
529 08:20:54.075957 INFO : End of Write leveling coarse delay
530 08:20:54.076413 INFO : Training has run successfully!
531 08:20:54.076821 Check phy result
532 08:20:54.081605 INFO : End of initialization
533 08:20:54.082036 INFO : End of read dq deskew training
534 08:20:54.087078 INFO : End of MPR read delay center optimization
535 08:20:54.092876 INFO : End of write delay center optimization
536 08:20:54.098298 INFO : End of read delay center optimization
537 08:20:54.098723 INFO : End of max read latency training
538 08:20:54.103954 INFO : Training has run successfully!
539 08:20:54.104421 1D training succeed
540 08:20:54.113170 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
541 08:20:54.160794 Check phy result
542 08:20:54.161239 INFO : End of initialization
543 08:20:54.182390 INFO : End of 2D read delay Voltage center optimization
544 08:20:54.202654 INFO : End of 2D read delay Voltage center optimization
545 08:20:54.254655 INFO : End of 2D write delay Voltage center optimization
546 08:20:54.304211 INFO : End of 2D write delay Voltage center optimization
547 08:20:54.309821 INFO : Training has run successfully!
548 08:20:54.310335
549 08:20:54.310758 channel==0
550 08:20:54.315423 RxClkDly_Margin_A0==88 ps 9
551 08:20:54.315921 TxDqDly_Margin_A0==98 ps 10
552 08:20:54.321067 RxClkDly_Margin_A1==88 ps 9
553 08:20:54.321582 TxDqDly_Margin_A1==98 ps 10
554 08:20:54.322003 TrainedVREFDQ_A0==74
555 08:20:54.326641 TrainedVREFDQ_A1==74
556 08:20:54.327158 VrefDac_Margin_A0==25
557 08:20:54.327578 DeviceVref_Margin_A0==40
558 08:20:54.332227 VrefDac_Margin_A1==25
559 08:20:54.332730 DeviceVref_Margin_A1==40
560 08:20:54.333146
561 08:20:54.333555
562 08:20:54.337819 channel==1
563 08:20:54.338331 RxClkDly_Margin_A0==98 ps 10
564 08:20:54.338756 TxDqDly_Margin_A0==98 ps 10
565 08:20:54.343417 RxClkDly_Margin_A1==98 ps 10
566 08:20:54.343944 TxDqDly_Margin_A1==88 ps 9
567 08:20:54.349027 TrainedVREFDQ_A0==77
568 08:20:54.349572 TrainedVREFDQ_A1==77
569 08:20:54.349992 VrefDac_Margin_A0==22
570 08:20:54.354591 DeviceVref_Margin_A0==37
571 08:20:54.355099 VrefDac_Margin_A1==22
572 08:20:54.360253 DeviceVref_Margin_A1==37
573 08:20:54.360761
574 08:20:54.361177 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
575 08:20:54.365792
576 08:20:54.393674 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000017 00000019 00000017 00000019 00000018 0000001a 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
577 08:20:54.394251 2D training succeed
578 08:20:54.399333 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
579 08:20:54.404965 auto size-- 65535DDR cs0 size: 2048MB
580 08:20:54.405484 DDR cs1 size: 2048MB
581 08:20:54.410519 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
582 08:20:54.411020 cs0 DataBus test pass
583 08:20:54.416138 cs1 DataBus test pass
584 08:20:54.416647 cs0 AddrBus test pass
585 08:20:54.417061 cs1 AddrBus test pass
586 08:20:54.417467
587 08:20:54.421687 100bdlr_step_size ps== 420
588 08:20:54.422205 result report
589 08:20:54.427268 boot times 0Enable ddr reg access
590 08:20:54.432804 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
591 08:20:54.446243 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
592 08:20:55.019880 0.0;M3 CHK:0;cm4_sp_mode 0
593 08:20:55.020522 MVN_1=0x00000000
594 08:20:55.025658 MVN_2=0x00000000
595 08:20:55.031308 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
596 08:20:55.031872 OPS=0x10
597 08:20:55.032376 ring efuse init
598 08:20:55.032771 chipver efuse init
599 08:20:55.036878 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
600 08:20:55.042570 [0.018960 Inits done]
601 08:20:55.043074 secure task start!
602 08:20:55.043471 high task start!
603 08:20:55.047113 low task start!
604 08:20:55.047598 run into bl31
605 08:20:55.053658 NOTICE: BL31: v1.3(release):4fc40b1
606 08:20:55.061508 NOTICE: BL31: Built : 15:58:17, May 22 2019
607 08:20:55.061998 NOTICE: BL31: G12A normal boot!
608 08:20:55.086898 NOTICE: BL31: BL33 decompress pass
609 08:20:55.091896 ERROR: Error initializing runtime service opteed_fast
610 08:20:56.325297
611 08:20:56.325922
612 08:20:56.333819 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
613 08:20:56.334314
614 08:20:56.334737 Model: Libre Computer AML-A311D-CC Alta
615 08:20:56.542219 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
616 08:20:56.565570 DRAM: 2 GiB (effective 3.8 GiB)
617 08:20:56.708540 Core: 408 devices, 31 uclasses, devicetree: separate
618 08:20:56.714432 WDT: Not starting watchdog@f0d0
619 08:20:56.746654 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
620 08:20:56.759119 Loading Environment from FAT... Card did not respond to voltage select! : -110
621 08:20:56.764263 ** Bad device specification mmc 0 **
622 08:20:56.774451 Card did not respond to voltage select! : -110
623 08:20:56.782110 ** Bad device specification mmc 0 **
624 08:20:56.782592 Couldn't find partition mmc 0
625 08:20:56.790471 Card did not respond to voltage select! : -110
626 08:20:56.796034 ** Bad device specification mmc 0 **
627 08:20:56.796519 Couldn't find partition mmc 0
628 08:20:56.801085 Error: could not access storage.
629 08:20:57.144142 Net: eth0: ethernet@ff3f0000
630 08:20:57.145727 starting USB...
631 08:20:57.395174 Bus usb@ff500000: Register 3000140 NbrPorts 3
632 08:20:57.395553 Starting the controller
633 08:20:57.402244 USB XHCI 1.10
634 08:20:59.114597 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
635 08:20:59.115234 bl2_stage_init 0x01
636 08:20:59.115660 bl2_stage_init 0x81
637 08:20:59.120211 hw id: 0x0000 - pwm id 0x01
638 08:20:59.120688 bl2_stage_init 0xc1
639 08:20:59.121100 bl2_stage_init 0x02
640 08:20:59.121505
641 08:20:59.125793 L0:00000000
642 08:20:59.126262 L1:20000703
643 08:20:59.126673 L2:00008067
644 08:20:59.127075 L3:14000000
645 08:20:59.131554 B2:00402000
646 08:20:59.132048 B1:e0f83180
647 08:20:59.132463
648 08:20:59.132864 TE: 58159
649 08:20:59.133266
650 08:20:59.136991 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
651 08:20:59.137460
652 08:20:59.137871 Board ID = 1
653 08:20:59.142599 Set A53 clk to 24M
654 08:20:59.143067 Set A73 clk to 24M
655 08:20:59.143474 Set clk81 to 24M
656 08:20:59.148282 A53 clk: 1200 MHz
657 08:20:59.148748 A73 clk: 1200 MHz
658 08:20:59.149154 CLK81: 166.6M
659 08:20:59.149555 smccc: 00012ab5
660 08:20:59.153785 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
661 08:20:59.159531 board id: 1
662 08:20:59.165339 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
663 08:20:59.175921 fw parse done
664 08:20:59.181889 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
665 08:20:59.224571 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
666 08:20:59.235533 PIEI prepare done
667 08:20:59.236028 fastboot data load
668 08:20:59.236448 fastboot data verify
669 08:20:59.241043 verify result: 266
670 08:20:59.246632 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
671 08:20:59.247093 LPDDR4 probe
672 08:20:59.247504 ddr clk to 1584MHz
673 08:20:59.254635 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
674 08:20:59.291882
675 08:20:59.292383 dmc_version 0001
676 08:20:59.298651 Check phy result
677 08:20:59.304594 INFO : End of CA training
678 08:20:59.305083 INFO : End of initialization
679 08:20:59.310053 INFO : Training has run successfully!
680 08:20:59.310536 Check phy result
681 08:20:59.315630 INFO : End of initialization
682 08:20:59.316140 INFO : End of read enable training
683 08:20:59.321249 INFO : End of fine write leveling
684 08:20:59.326826 INFO : End of Write leveling coarse delay
685 08:20:59.327298 INFO : Training has run successfully!
686 08:20:59.327710 Check phy result
687 08:20:59.332592 INFO : End of initialization
688 08:20:59.333068 INFO : End of read dq deskew training
689 08:20:59.338027 INFO : End of MPR read delay center optimization
690 08:20:59.343651 INFO : End of write delay center optimization
691 08:20:59.349267 INFO : End of read delay center optimization
692 08:20:59.349773 INFO : End of max read latency training
693 08:20:59.354860 INFO : Training has run successfully!
694 08:20:59.355348 1D training succeed
695 08:20:59.363964 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
696 08:20:59.411714 Check phy result
697 08:20:59.412281 INFO : End of initialization
698 08:20:59.433233 INFO : End of 2D read delay Voltage center optimization
699 08:20:59.453322 INFO : End of 2D read delay Voltage center optimization
700 08:20:59.505242 INFO : End of 2D write delay Voltage center optimization
701 08:20:59.554469 INFO : End of 2D write delay Voltage center optimization
702 08:20:59.560071 INFO : Training has run successfully!
703 08:20:59.560539
704 08:20:59.560954 channel==0
705 08:20:59.565653 RxClkDly_Margin_A0==88 ps 9
706 08:20:59.566123 TxDqDly_Margin_A0==98 ps 10
707 08:20:59.571244 RxClkDly_Margin_A1==88 ps 9
708 08:20:59.571710 TxDqDly_Margin_A1==98 ps 10
709 08:20:59.572158 TrainedVREFDQ_A0==74
710 08:20:59.576834 TrainedVREFDQ_A1==74
711 08:20:59.577299 VrefDac_Margin_A0==25
712 08:20:59.577707 DeviceVref_Margin_A0==40
713 08:20:59.582457 VrefDac_Margin_A1==26
714 08:20:59.582926 DeviceVref_Margin_A1==40
715 08:20:59.583333
716 08:20:59.583734
717 08:20:59.588057 channel==1
718 08:20:59.588519 RxClkDly_Margin_A0==98 ps 10
719 08:20:59.588925 TxDqDly_Margin_A0==88 ps 9
720 08:20:59.593661 RxClkDly_Margin_A1==88 ps 9
721 08:20:59.594128 TxDqDly_Margin_A1==88 ps 9
722 08:20:59.599277 TrainedVREFDQ_A0==76
723 08:20:59.599741 TrainedVREFDQ_A1==77
724 08:20:59.600192 VrefDac_Margin_A0==23
725 08:20:59.604785 DeviceVref_Margin_A0==38
726 08:20:59.605251 VrefDac_Margin_A1==24
727 08:20:59.610456 DeviceVref_Margin_A1==37
728 08:20:59.610923
729 08:20:59.611332 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
730 08:20:59.611733
731 08:20:59.644082 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000018 00000019 00000017 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
732 08:20:59.644752 2D training succeed
733 08:20:59.649605 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
734 08:20:59.655237 auto size-- 65535DDR cs0 size: 2048MB
735 08:20:59.655702 DDR cs1 size: 2048MB
736 08:20:59.660823 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
737 08:20:59.661292 cs0 DataBus test pass
738 08:20:59.666440 cs1 DataBus test pass
739 08:20:59.666901 cs0 AddrBus test pass
740 08:20:59.667309 cs1 AddrBus test pass
741 08:20:59.667705
742 08:20:59.672027 100bdlr_step_size ps== 420
743 08:20:59.672504 result report
744 08:20:59.677662 boot times 0Enable ddr reg access
745 08:20:59.682904 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
746 08:20:59.696392 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
747 08:21:00.268307 0.0;M3 CHK:0;cm4_sp_mode 0
748 08:21:00.268844 MVN_1=0x00000000
749 08:21:00.274025 MVN_2=0x00000000
750 08:21:00.279827 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
751 08:21:00.280362 OPS=0x10
752 08:21:00.280761 ring efuse init
753 08:21:00.281144 chipver efuse init
754 08:21:00.285332 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
755 08:21:00.290965 [0.018961 Inits done]
756 08:21:00.291425 secure task start!
757 08:21:00.291818 high task start!
758 08:21:00.295603 low task start!
759 08:21:00.296080 run into bl31
760 08:21:00.302167 NOTICE: BL31: v1.3(release):4fc40b1
761 08:21:00.310067 NOTICE: BL31: Built : 15:58:17, May 22 2019
762 08:21:00.310537 NOTICE: BL31: G12A normal boot!
763 08:21:00.335906 NOTICE: BL31: BL33 decompress pass
764 08:21:00.341646 ERROR: Error initializing runtime service opteed_fast
765 08:21:01.574289
766 08:21:01.574905
767 08:21:01.582823 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
768 08:21:01.583301
769 08:21:01.583733 Model: Libre Computer AML-A311D-CC Alta
770 08:21:01.791190 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
771 08:21:01.814666 DRAM: 2 GiB (effective 3.8 GiB)
772 08:21:01.957654 Core: 408 devices, 31 uclasses, devicetree: separate
773 08:21:01.963556 WDT: Not starting watchdog@f0d0
774 08:21:01.995835 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
775 08:21:02.008170 Loading Environment from FAT... Card did not respond to voltage select! : -110
776 08:21:02.013234 ** Bad device specification mmc 0 **
777 08:21:02.023632 Card did not respond to voltage select! : -110
778 08:21:02.031240 ** Bad device specification mmc 0 **
779 08:21:02.031714 Couldn't find partition mmc 0
780 08:21:02.039619 Card did not respond to voltage select! : -110
781 08:21:02.045090 ** Bad device specification mmc 0 **
782 08:21:02.045556 Couldn't find partition mmc 0
783 08:21:02.050196 Error: could not access storage.
784 08:21:02.392753 Net: eth0: ethernet@ff3f0000
785 08:21:02.393330 starting USB...
786 08:21:02.645241 Bus usb@ff500000: Register 3000140 NbrPorts 3
787 08:21:02.645838 Starting the controller
788 08:21:02.651324 USB XHCI 1.10
789 08:21:04.813188 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
790 08:21:04.813871 bl2_stage_init 0x01
791 08:21:04.814349 bl2_stage_init 0x81
792 08:21:04.818776 hw id: 0x0000 - pwm id 0x01
793 08:21:04.819562 bl2_stage_init 0xc1
794 08:21:04.820194 bl2_stage_init 0x02
795 08:21:04.820817
796 08:21:04.824410 L0:00000000
797 08:21:04.825168 L1:20000703
798 08:21:04.825756 L2:00008067
799 08:21:04.826379 L3:14000000
800 08:21:04.827405 B2:00402000
801 08:21:04.828067 B1:e0f83180
802 08:21:04.828688
803 08:21:04.829218 TE: 58159
804 08:21:04.829818
805 08:21:04.838468 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
806 08:21:04.839268
807 08:21:04.839817 Board ID = 1
808 08:21:04.840457 Set A53 clk to 24M
809 08:21:04.841070 Set A73 clk to 24M
810 08:21:04.844252 Set clk81 to 24M
811 08:21:04.844837 A53 clk: 1200 MHz
812 08:21:04.845251 A73 clk: 1200 MHz
813 08:21:04.849665 CLK81: 166.6M
814 08:21:04.850149 smccc: 00012ab5
815 08:21:04.855223 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
816 08:21:04.855692 board id: 1
817 08:21:04.863332 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
818 08:21:04.874342 fw parse done
819 08:21:04.880323 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
820 08:21:04.922925 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
821 08:21:04.933847 PIEI prepare done
822 08:21:04.934313 fastboot data load
823 08:21:04.934719 fastboot data verify
824 08:21:04.939583 verify result: 266
825 08:21:04.945175 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
826 08:21:04.945660 LPDDR4 probe
827 08:21:04.946058 ddr clk to 1584MHz
828 08:21:04.953150 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
829 08:21:04.989431
830 08:21:04.989924 dmc_version 0001
831 08:21:04.996100 Check phy result
832 08:21:05.003004 INFO : End of CA training
833 08:21:05.003510 INFO : End of initialization
834 08:21:05.008538 INFO : Training has run successfully!
835 08:21:05.009009 Check phy result
836 08:21:05.014150 INFO : End of initialization
837 08:21:05.014609 INFO : End of read enable training
838 08:21:05.019736 INFO : End of fine write leveling
839 08:21:05.025341 INFO : End of Write leveling coarse delay
840 08:21:05.025812 INFO : Training has run successfully!
841 08:21:05.026215 Check phy result
842 08:21:05.030921 INFO : End of initialization
843 08:21:05.031382 INFO : End of read dq deskew training
844 08:21:05.036557 INFO : End of MPR read delay center optimization
845 08:21:05.042176 INFO : End of write delay center optimization
846 08:21:05.047723 INFO : End of read delay center optimization
847 08:21:05.048226 INFO : End of max read latency training
848 08:21:05.053339 INFO : Training has run successfully!
849 08:21:05.053793 1D training succeed
850 08:21:05.062440 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
851 08:21:05.110130 Check phy result
852 08:21:05.110702 INFO : End of initialization
853 08:21:05.130830 INFO : End of 2D read delay Voltage center optimization
854 08:21:05.150913 INFO : End of 2D read delay Voltage center optimization
855 08:21:05.203719 INFO : End of 2D write delay Voltage center optimization
856 08:21:05.252892 INFO : End of 2D write delay Voltage center optimization
857 08:21:05.258565 INFO : Training has run successfully!
858 08:21:05.259026
859 08:21:05.259447 channel==0
860 08:21:05.264126 RxClkDly_Margin_A0==88 ps 9
861 08:21:05.264581 TxDqDly_Margin_A0==98 ps 10
862 08:21:05.269703 RxClkDly_Margin_A1==88 ps 9
863 08:21:05.270148 TxDqDly_Margin_A1==98 ps 10
864 08:21:05.270541 TrainedVREFDQ_A0==74
865 08:21:05.275420 TrainedVREFDQ_A1==74
866 08:21:05.275869 VrefDac_Margin_A0==25
867 08:21:05.276328 DeviceVref_Margin_A0==40
868 08:21:05.280912 VrefDac_Margin_A1==25
869 08:21:05.281370 DeviceVref_Margin_A1==40
870 08:21:05.281758
871 08:21:05.282142
872 08:21:05.286474 channel==1
873 08:21:05.286913 RxClkDly_Margin_A0==98 ps 10
874 08:21:05.287301 TxDqDly_Margin_A0==98 ps 10
875 08:21:05.292057 RxClkDly_Margin_A1==88 ps 9
876 08:21:05.292512 TxDqDly_Margin_A1==88 ps 9
877 08:21:05.297713 TrainedVREFDQ_A0==77
878 08:21:05.298158 TrainedVREFDQ_A1==77
879 08:21:05.298552 VrefDac_Margin_A0==22
880 08:21:05.303387 DeviceVref_Margin_A0==37
881 08:21:05.303772 VrefDac_Margin_A1==24
882 08:21:05.308962 DeviceVref_Margin_A1==37
883 08:21:05.309365
884 08:21:05.309604 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
885 08:21:05.309823
886 08:21:05.342491 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000017 00000018 00000017 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
887 08:21:05.342963 2D training succeed
888 08:21:05.348164 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
889 08:21:05.353661 auto size-- 65535DDR cs0 size: 2048MB
890 08:21:05.354056 DDR cs1 size: 2048MB
891 08:21:05.359346 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
892 08:21:05.359776 cs0 DataBus test pass
893 08:21:05.364887 cs1 DataBus test pass
894 08:21:05.365271 cs0 AddrBus test pass
895 08:21:05.365492 cs1 AddrBus test pass
896 08:21:05.365705
897 08:21:05.370459 100bdlr_step_size ps== 420
898 08:21:05.370828 result report
899 08:21:05.376074 boot times 0Enable ddr reg access
900 08:21:05.381496 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
901 08:21:05.394854 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
902 08:21:05.966788 0.0;M3 CHK:0;cm4_sp_mode 0
903 08:21:05.967306 MVN_1=0x00000000
904 08:21:05.972372 MVN_2=0x00000000
905 08:21:05.978130 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
906 08:21:05.978564 OPS=0x10
907 08:21:05.978969 ring efuse init
908 08:21:05.979363 chipver efuse init
909 08:21:05.983702 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
910 08:21:05.989352 [0.018961 Inits done]
911 08:21:05.989781 secure task start!
912 08:21:05.990176 high task start!
913 08:21:05.993910 low task start!
914 08:21:05.994332 run into bl31
915 08:21:06.000521 NOTICE: BL31: v1.3(release):4fc40b1
916 08:21:06.007488 NOTICE: BL31: Built : 15:58:17, May 22 2019
917 08:21:06.007965 NOTICE: BL31: G12A normal boot!
918 08:21:06.033712 NOTICE: BL31: BL33 decompress pass
919 08:21:06.038942 ERROR: Error initializing runtime service opteed_fast
920 08:21:07.272261
921 08:21:07.272864
922 08:21:07.280661 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
923 08:21:07.281123
924 08:21:07.281550 Model: Libre Computer AML-A311D-CC Alta
925 08:21:07.488217 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
926 08:21:07.512464 DRAM: 2 GiB (effective 3.8 GiB)
927 08:21:07.655727 Core: 408 devices, 31 uclasses, devicetree: separate
928 08:21:07.661566 WDT: Not starting watchdog@f0d0
929 08:21:07.693734 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
930 08:21:07.706223 Loading Environment from FAT... Card did not respond to voltage select! : -110
931 08:21:07.711239 ** Bad device specification mmc 0 **
932 08:21:07.721451 Card did not respond to voltage select! : -110
933 08:21:07.729182 ** Bad device specification mmc 0 **
934 08:21:07.729628 Couldn't find partition mmc 0
935 08:21:07.737441 Card did not respond to voltage select! : -110
936 08:21:07.742975 ** Bad device specification mmc 0 **
937 08:21:07.743412 Couldn't find partition mmc 0
938 08:21:07.748060 Error: could not access storage.
939 08:21:08.090543 Net: eth0: ethernet@ff3f0000
940 08:21:08.091060 starting USB...
941 08:21:08.342458 Bus usb@ff500000: Register 3000140 NbrPorts 3
942 08:21:08.342946 Starting the controller
943 08:21:08.349331 USB XHCI 1.10
944 08:21:10.213020 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
945 08:21:10.213623 bl2_stage_init 0x01
946 08:21:10.214044 bl2_stage_init 0x81
947 08:21:10.218488 hw id: 0x0000 - pwm id 0x01
948 08:21:10.218927 bl2_stage_init 0xc1
949 08:21:10.219337 bl2_stage_init 0x02
950 08:21:10.219739
951 08:21:10.224074 L0:00000000
952 08:21:10.224535 L1:20000703
953 08:21:10.224945 L2:00008067
954 08:21:10.225344 L3:14000000
955 08:21:10.227138 B2:00402000
956 08:21:10.227568 B1:e0f83180
957 08:21:10.227968
958 08:21:10.228409 TE: 58124
959 08:21:10.228814
960 08:21:10.238193 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
961 08:21:10.238637
962 08:21:10.239048 Board ID = 1
963 08:21:10.239448 Set A53 clk to 24M
964 08:21:10.239844 Set A73 clk to 24M
965 08:21:10.243833 Set clk81 to 24M
966 08:21:10.244292 A53 clk: 1200 MHz
967 08:21:10.244699 A73 clk: 1200 MHz
968 08:21:10.247424 CLK81: 166.6M
969 08:21:10.247849 smccc: 00012a92
970 08:21:10.253040 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
971 08:21:10.258572 board id: 1
972 08:21:10.263633 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
973 08:21:10.274155 fw parse done
974 08:21:10.280176 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
975 08:21:10.322798 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
976 08:21:10.333759 PIEI prepare done
977 08:21:10.334198 fastboot data load
978 08:21:10.334596 fastboot data verify
979 08:21:10.339290 verify result: 266
980 08:21:10.345058 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
981 08:21:10.345507 LPDDR4 probe
982 08:21:10.345894 ddr clk to 1584MHz
983 08:21:10.352843 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
984 08:21:10.390237
985 08:21:10.390677 dmc_version 0001
986 08:21:10.396911 Check phy result
987 08:21:10.402683 INFO : End of CA training
988 08:21:10.403127 INFO : End of initialization
989 08:21:10.408363 INFO : Training has run successfully!
990 08:21:10.408855 Check phy result
991 08:21:10.413909 INFO : End of initialization
992 08:21:10.414342 INFO : End of read enable training
993 08:21:10.417196 INFO : End of fine write leveling
994 08:21:10.422830 INFO : End of Write leveling coarse delay
995 08:21:10.428343 INFO : Training has run successfully!
996 08:21:10.428766 Check phy result
997 08:21:10.429167 INFO : End of initialization
998 08:21:10.434089 INFO : End of read dq deskew training
999 08:21:10.439575 INFO : End of MPR read delay center optimization
1000 08:21:10.440055 INFO : End of write delay center optimization
1001 08:21:10.445171 INFO : End of read delay center optimization
1002 08:21:10.450847 INFO : End of max read latency training
1003 08:21:10.451276 INFO : Training has run successfully!
1004 08:21:10.456277 1D training succeed
1005 08:21:10.462286 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
1006 08:21:10.509951 Check phy result
1007 08:21:10.510411 INFO : End of initialization
1008 08:21:10.531618 INFO : End of 2D read delay Voltage center optimization
1009 08:21:10.551920 INFO : End of 2D read delay Voltage center optimization
1010 08:21:10.603926 INFO : End of 2D write delay Voltage center optimization
1011 08:21:10.653299 INFO : End of 2D write delay Voltage center optimization
1012 08:21:10.658891 INFO : Training has run successfully!
1013 08:21:10.659331
1014 08:21:10.659742 channel==0
1015 08:21:10.664456 RxClkDly_Margin_A0==88 ps 9
1016 08:21:10.664909 TxDqDly_Margin_A0==98 ps 10
1017 08:21:10.667771 RxClkDly_Margin_A1==88 ps 9
1018 08:21:10.668233 TxDqDly_Margin_A1==98 ps 10
1019 08:21:10.673258 TrainedVREFDQ_A0==74
1020 08:21:10.673689 TrainedVREFDQ_A1==74
1021 08:21:10.678893 VrefDac_Margin_A0==25
1022 08:21:10.679316 DeviceVref_Margin_A0==40
1023 08:21:10.679720 VrefDac_Margin_A1==25
1024 08:21:10.684476 DeviceVref_Margin_A1==40
1025 08:21:10.684906
1026 08:21:10.685311
1027 08:21:10.685708 channel==1
1028 08:21:10.686099 RxClkDly_Margin_A0==98 ps 10
1029 08:21:10.690144 TxDqDly_Margin_A0==98 ps 10
1030 08:21:10.690580 RxClkDly_Margin_A1==98 ps 10
1031 08:21:10.695686 TxDqDly_Margin_A1==88 ps 9
1032 08:21:10.696155 TrainedVREFDQ_A0==77
1033 08:21:10.696565 TrainedVREFDQ_A1==77
1034 08:21:10.701261 VrefDac_Margin_A0==22
1035 08:21:10.701690 DeviceVref_Margin_A0==37
1036 08:21:10.706883 VrefDac_Margin_A1==24
1037 08:21:10.707308 DeviceVref_Margin_A1==37
1038 08:21:10.707706
1039 08:21:10.712354 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
1040 08:21:10.712784
1041 08:21:10.740333 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000018 00000019 00000018 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
1042 08:21:10.746016 2D training succeed
1043 08:21:10.751530 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
1044 08:21:10.751959 auto size-- 65535DDR cs0 size: 2048MB
1045 08:21:10.757158 DDR cs1 size: 2048MB
1046 08:21:10.757588 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
1047 08:21:10.762781 cs0 DataBus test pass
1048 08:21:10.763217 cs1 DataBus test pass
1049 08:21:10.763621 cs0 AddrBus test pass
1050 08:21:10.768401 cs1 AddrBus test pass
1051 08:21:10.768837
1052 08:21:10.769242 100bdlr_step_size ps== 420
1053 08:21:10.769648 result report
1054 08:21:10.774043 boot times 0Enable ddr reg access
1055 08:21:10.781746 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
1056 08:21:10.795211 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
1057 08:21:11.369081 0.0;M3 CHK:0;cm4_sp_mode 0
1058 08:21:11.369710 MVN_1=0x00000000
1059 08:21:11.374457 MVN_2=0x00000000
1060 08:21:11.380197 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
1061 08:21:11.380634 OPS=0x10
1062 08:21:11.381044 ring efuse init
1063 08:21:11.381442 chipver efuse init
1064 08:21:11.385802 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
1065 08:21:11.391374 [0.018960 Inits done]
1066 08:21:11.391800 secure task start!
1067 08:21:11.392368 high task start!
1068 08:21:11.395976 low task start!
1069 08:21:11.396438 run into bl31
1070 08:21:11.402579 NOTICE: BL31: v1.3(release):4fc40b1
1071 08:21:11.410406 NOTICE: BL31: Built : 15:58:17, May 22 2019
1072 08:21:11.410856 NOTICE: BL31: G12A normal boot!
1073 08:21:11.435825 NOTICE: BL31: BL33 decompress pass
1074 08:21:11.441479 ERROR: Error initializing runtime service opteed_fast
1075 08:21:12.674488
1076 08:21:12.675095
1077 08:21:12.682830 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
1078 08:21:12.683276
1079 08:21:12.683683 Model: Libre Computer AML-A311D-CC Alta
1080 08:21:12.891341 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
1081 08:21:12.914619 DRAM: 2 GiB (effective 3.8 GiB)
1082 08:21:13.057740 Core: 408 devices, 31 uclasses, devicetree: separate
1083 08:21:13.063470 WDT: Not starting watchdog@f0d0
1084 08:21:13.095779 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
1085 08:21:13.108285 Loading Environment from FAT... Card did not respond to voltage select! : -110
1086 08:21:13.113200 ** Bad device specification mmc 0 **
1087 08:21:13.123484 Card did not respond to voltage select! : -110
1088 08:21:13.131147 ** Bad device specification mmc 0 **
1089 08:21:13.131644 Couldn't find partition mmc 0
1090 08:21:13.139469 Card did not respond to voltage select! : -110
1091 08:21:13.145081 ** Bad device specification mmc 0 **
1092 08:21:13.145583 Couldn't find partition mmc 0
1093 08:21:13.150114 Error: could not access storage.
1094 08:21:13.492627 Net: eth0: ethernet@ff3f0000
1095 08:21:13.493210 starting USB...
1096 08:21:13.744323 Bus usb@ff500000: Register 3000140 NbrPorts 3
1097 08:21:13.744845 Starting the controller
1098 08:21:13.751253 USB XHCI 1.10
1099 08:21:15.308603 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
1100 08:21:15.316801 scanning usb for storage devices... 0 Storage Device(s) found
1102 08:21:15.368333 Hit any key to stop autoboot: 1
1103 08:21:15.369114 end: 2.4.2 bootloader-interrupt (duration 00:00:37) [common]
1104 08:21:15.369698 start: 2.4.3 bootloader-commands (timeout 00:04:23) [common]
1105 08:21:15.370148 Setting prompt string to ['=>']
1106 08:21:15.370617 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:23)
1107 08:21:15.384226 0
1108 08:21:15.385083 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1109 08:21:15.385562 Sending with 10 millisecond of delay
1111 08:21:16.520123 => setenv autoload no
1112 08:21:16.530929 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:22)
1113 08:21:16.535783 setenv autoload no
1114 08:21:16.536539 Sending with 10 millisecond of delay
1116 08:21:18.333182 => setenv initrd_high 0xffffffff
1117 08:21:18.343969 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:20)
1118 08:21:18.344862 setenv initrd_high 0xffffffff
1119 08:21:18.345579 Sending with 10 millisecond of delay
1121 08:21:19.961532 => setenv fdt_high 0xffffffff
1122 08:21:19.972277 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1123 08:21:19.973076 setenv fdt_high 0xffffffff
1124 08:21:19.973776 Sending with 10 millisecond of delay
1126 08:21:20.265525 => dhcp
1127 08:21:20.276255 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1128 08:21:20.277031 dhcp
1129 08:21:20.277462 Speed: 1000, full duplex
1130 08:21:20.277870 BOOTP broadcast 1
1131 08:21:20.283607 DHCP client bound to address 192.168.6.27 (8 ms)
1132 08:21:20.284346 Sending with 10 millisecond of delay
1134 08:21:21.960583 => setenv serverip 192.168.6.2
1135 08:21:21.971354 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:16)
1136 08:21:21.972262 setenv serverip 192.168.6.2
1137 08:21:21.972963 Sending with 10 millisecond of delay
1139 08:21:25.695544 => tftpboot 0x01080000 978663/tftp-deploy-pf_42i5m/kernel/uImage
1140 08:21:25.706372 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:13)
1141 08:21:25.707160 tftpboot 0x01080000 978663/tftp-deploy-pf_42i5m/kernel/uImage
1142 08:21:25.707619 Speed: 1000, full duplex
1143 08:21:25.708066 Using ethernet@ff3f0000 device
1144 08:21:25.708984 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1145 08:21:25.714544 Filename '978663/tftp-deploy-pf_42i5m/kernel/uImage'.
1146 08:21:25.718492 Load address: 0x1080000
1147 08:21:28.760255 Loading: *################################################## 44 MiB
1148 08:21:28.760872 14.4 MiB/s
1149 08:21:28.761303 done
1150 08:21:28.764575 Bytes transferred = 46121536 (2bfc240 hex)
1151 08:21:28.765356 Sending with 10 millisecond of delay
1153 08:21:33.450810 => tftpboot 0x08000000 978663/tftp-deploy-pf_42i5m/ramdisk/ramdisk.cpio.gz.uboot
1154 08:21:33.461590 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:05)
1155 08:21:33.462372 tftpboot 0x08000000 978663/tftp-deploy-pf_42i5m/ramdisk/ramdisk.cpio.gz.uboot
1156 08:21:33.462814 Speed: 1000, full duplex
1157 08:21:33.463227 Using ethernet@ff3f0000 device
1158 08:21:33.464291 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1159 08:21:33.472885 Filename '978663/tftp-deploy-pf_42i5m/ramdisk/ramdisk.cpio.gz.uboot'.
1160 08:21:33.473331 Load address: 0x8000000
1161 08:21:40.549000 Loading: *#################T ################################ UDP wrong checksum 00000005 00009293
1162 08:21:45.549491 T UDP wrong checksum 00000005 00009293
1163 08:21:55.552677 T T UDP wrong checksum 00000005 00009293
1164 08:22:15.556488 T T T T UDP wrong checksum 00000005 00009293
1165 08:22:25.690875 T T UDP wrong checksum 000000ff 00000a13
1166 08:22:25.719810 UDP wrong checksum 000000ff 00009d05
1167 08:22:30.560359
1168 08:22:30.560961 Retry count exceeded; starting again
1170 08:22:30.562342 end: 2.4.3 bootloader-commands (duration 00:01:15) [common]
1173 08:22:30.564232 end: 2.4 uboot-commands (duration 00:01:52) [common]
1175 08:22:30.565606 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
1177 08:22:30.566646 end: 2 uboot-action (duration 00:01:52) [common]
1179 08:22:30.568236 Cleaning after the job
1180 08:22:30.568812 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/978663/tftp-deploy-pf_42i5m/ramdisk
1181 08:22:30.570098 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/978663/tftp-deploy-pf_42i5m/kernel
1182 08:22:30.613516 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/978663/tftp-deploy-pf_42i5m/dtb
1183 08:22:30.614270 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/978663/tftp-deploy-pf_42i5m/nfsrootfs
1184 08:22:30.901555 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/978663/tftp-deploy-pf_42i5m/modules
1185 08:22:30.921665 start: 4.1 power-off (timeout 00:00:30) [common]
1186 08:22:30.922283 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1187 08:22:30.957310 >> OK - accepted request
1188 08:22:30.959516 Returned 0 in 0 seconds
1189 08:22:31.060238 end: 4.1 power-off (duration 00:00:00) [common]
1191 08:22:31.061127 start: 4.2 read-feedback (timeout 00:10:00) [common]
1192 08:22:31.061756 Listened to connection for namespace 'common' for up to 1s
1193 08:22:32.061780 Finalising connection for namespace 'common'
1194 08:22:32.062215 Disconnecting from shell: Finalise
1195 08:22:32.062496 =>
1196 08:22:32.163265 end: 4.2 read-feedback (duration 00:00:01) [common]
1197 08:22:32.163896 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/978663
1198 08:22:35.097818 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/978663
1199 08:22:35.098417 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.