Trying 192.168.56.21... Connected to conserv1. Escape character is '^]'. ser2net port telnet,3008 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.3.3:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux) SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0; bl2_stage_init 0x01 bl2_stage_init 0x81 hw id: 0x0000 - pwm id 0x01 bl2_stage_init 0xc1 bl2_stage_init 0x02 L0:00000000 L1:00000703 L2:00008067 L3:15000000 S1:00000000 B2:20282000 B1:a0f83180 TE: 68299 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz Board ID = 1 Set cpu clk to 24M Set clk81 to 24M Use GP1_pll as DSU clk. DSU clk: 1200 Mhz CPU clk: 1200 MHz Set clk81 to 166.6M DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45 board id: 1 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0 fw parse done Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0 PIEI prepare done fastboot data load fastboot data verify verify result: 266 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg LPDDR4 probe ddr clk to 1584MHz Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0 dmc_version 0001 Check phy result INFO : End of CA training INFO : End of initialization INFO : Training has run successfully! Check phy result INFO : End of initialization INFO : End of read enable training INFO : End of fine write leveling INFO : End of Write leveling coarse delay INFO : Training has run successfully! Check phy result INFO : End of initialization INFO : End of read dq deskew training INFO : End of MPR read delay center optimization INFO : End of write delay center optimization INFO : End of read delay center optimization INFO : End of max read latency training INFO : Training has run successfully! 1D training succeed Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0 Check phy result INFO : End of initialization INFO : End of 2D read delay Voltage center optimization INFO : End of 2D read delay Voltage center optimization INFO : End of 2D write delay Voltage center optimization INFO : End of 2D write delay Voltage center optimization INFO : Training has run successfully! channel==0 RxClkDly_Margin_A0==78 ps 8 TxDqDly_Margin_A0==98 ps 10 RxClkDly_Margin_A1==69 ps 7 TxDqDly_Margin_A1==98 ps 10 TrainedVREFDQ_A0==74 TrainedVREFDQ_A1==75 VrefDac_Margin_A0==25 DeviceVref_Margin_A0==40 VrefDac_Margin_A1==23 DeviceVref_Margin_A1==39 channel==1 RxClkDly_Margin_A0==88 ps 9 TxDqDly_Margin_A0==98 ps 10 RxClkDly_Margin_A1==88 ps 9 TxDqDly_Margin_A1==88 ps 9 TrainedVREFDQ_A0==78 TrainedVREFDQ_A1==77 VrefDac_Margin_A0==22 DeviceVref_Margin_A0==36 VrefDac_Margin_A1==22 DeviceVref_Margin_A1==37 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000017 00000018 00000018 00000018 00000017 00000018 00000015 00000017 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001c 00000017 00000016 00000016 dram_vref_reg_value 0x 00000061 2D training succeed aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19 auto size-- 65535DDR cs0 size: 2048MB DDR cs1 size: 2048MB DMC_DDR_CTRL: 00e00024DDR size: 3928MB cs0 DataBus test pass cs1 DataBus test pass cs0 AddrBus test pass cs1 AddrBus test pass 100bdlr_step_size ps== 471 result report boot times 0Enable ddr reg access Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0 bl2z: ptr: 05129330, size: 00001e40 0.0;M3 CHK:0;cm4_sp_mode 0 MVN_1=0x00000000 MVN_2=0x00000000 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz] OPS=0x04 ring efuse init 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50 [0.017354 Inits done] secure task start! high task start! low task start! run into bl31 NOTICE: BL31: v1.3(release):4fc40b1 NOTICE: BL31: Built : 15:57:33, May 22 2019 NOTICE: BL31: G12A normal boot! NOTICE: BL31: BL33 decompress pass ERROR: Error initializing runtime service opteed_fast SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0; bl2_stage_init 0x01 bl2_stage_init 0x81 hw id: 0x0000 - pwm id 0x01 bl2_stage_init 0xc1 bl2_stage_init 0x02 L0:00000000 L1:00000703 L2:00008067 L3:15000000 S1:00000000 B2:20282000 B1:a0f83180 TE: 67642 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz Board ID = 1 Set cpu clk to 24M Set clk81 to 24M Use GP1_pll as DSU clk. DSU clk: 1200 Mhz CPU clk: 1200 MHz Set clk81 to 166.6M DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45 board id: 1 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0 fw parse done Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0 PIEI prepare done fastboot data load fastboot data verify verify result: 266 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg LPDDR4 probe ddr clk to 1584MHz Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0 dmc_version 0001 Check phy result INFO : End of CA training INFO : End of initialization INFO : Training has run successfully! Check phy result INFO : End of initialization INFO : End of read enable training INFO : End of fine write leveling INFO : End of Write leveling coarse delay INFO : Training has run successfully! Check phy result INFO : End of initialization INFO : End of read dq deskew training INFO : End of MPR read delay center optimization INFO : End of write delay center optimization INFO : End of read delay center optimization INFO : End of max read latency training INFO : Training has run successfully! 1D training succeed Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0 Check phy result INFO : End of initialization INFO : End of 2D read delay Voltage center optimization INFO : End of 2D read delay Voltage center optimization INFO : End of 2D write delay Voltage center optimization INFO : End of 2D write delay Voltage center optimization INFO : Training has run successfully! channel==0 RxClkDly_Margin_A0==78 ps 8 TxDqDly_Margin_A0==88 ps 9 RxClkDly_Margin_A1==88 ps 9 TxDqDly_Margin_A1==98 ps 10 TrainedVREFDQ_A0==74 TrainedVREFDQ_A1==75 VrefDac_Margin_A0==24 DeviceVref_Margin_A0==40 VrefDac_Margin_A1==23 DeviceVref_Margin_A1==39 channel==1 RxClkDly_Margin_A0==78 ps 8 TxDqDly_Margin_A0==98 ps 10 RxClkDly_Margin_A1==78 ps 8 TxDqDly_Margin_A1==78 ps 8 TrainedVREFDQ_A0==78 TrainedVREFDQ_A1==75 VrefDac_Margin_A0==22 DeviceVref_Margin_A0==36 VrefDac_Margin_A1==22 DeviceVref_Margin_A1==39 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000016 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000018 00000018 00000019 00000018 00000017 00000019 00000015 00000018 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001c 00000017 00000016 00000016 dram_vref_reg_value 0x 00000061 2D training succeed aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19 auto size-- 65535DDR cs0 size: 2048MB DDR cs1 size: 2048MB DMC_DDR_CTRL: 00e00024DDR size: 3928MB cs0 DataBus test pass cs1 DataBus test pass cs0 AddrBus test pass cs1 AddrBus test pass 100bdlr_step_size ps== 478 result report boot times 0Enable ddr reg access Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0 bl2z: ptr: 05129330, size: 00001e40 0.0;M3 CHK:0;cm4_sp_mode 0 MVN_1=0x00000000 MVN_2=0x00000000 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz] OPS=0x04 ring efuse init 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50 [0.017320 Inits done] secure task start! high task start! low task start! run into bl31 NOTICE: BL31: v1.3(release):4fc40b1 NOTICE: BL31: Built : 15:57:33, May 22 2019 NOTICE: BL31: G12A normal boot! NOTICE: BL31: BL33 decompress pass ERROR: Error initializing runtime service opteed_fast SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0; bl2_stage_init 0x01 bl2_stage_init 0x81 hw id: 0x0000 - pwm id 0x01 bl2_stage_init 0xc1 bl2_stage_init 0x02 L0:00000000 L1:00000703 L2:00008067 L3:15000000 S1:00000000 B2:20282000 B1:a0f83180 TE: 71336 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz Board ID = 1 Set cpu clk to 24M Set clk81 to 24M Use GP1_pll as DSU clk. DSU clk: 1200 Mhz CPU clk: 1200 MHz Set clk81 to 166.6M DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45 board id: 1 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0 fw parse done Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0 PIEI prepare done fastboot data load fastboot data verify verify result: 266 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg LPDDR4 probe ddr clk to 1584MHz Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0 dmc_version 0001 Check phy result INFO : End of CA training INFO : End of initialization INFO : Training has run successfully! Check phy result INFO : End of initialization INFO : End of read enable training INFO : End of fine write leveling INFO : End of Write leveling coarse delay INFO : Training has run successfully! Check phy result INFO : End of initialization INFO : End of read dq deskew training INFO : End of MPR read delay center optimization INFO : End of write delay center optimization INFO : End of read delay center optimization INFO : End of max read latency training INFO : Training has run successfully! 1D training succeed Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0 Check phy result INFO : End of initialization INFO : End of 2D read delay Voltage center optimization INFO : End of 2D read delay Voltage center optimization INFO : End of 2D write delay Voltage center optimization INFO : End of 2D write delay Voltage center optimization INFO : Training has run successfully! channel==0 RxClkDly_Margin_A0==78 ps 8 TxDqDly_Margin_A0==88 ps 9 RxClkDly_Margin_A1==88 ps 9 TxDqDly_Margin_A1==88 ps 9 TrainedVREFDQ_A0==74 TrainedVREFDQ_A1==74 VrefDac_Margin_A0==25 DeviceVref_Margin_A0==40 VrefDac_Margin_A1==23 DeviceVref_Margin_A1==40 channel==1 RxClkDly_Margin_A0==78 ps 8 TxDqDly_Margin_A0==88 ps 9 RxClkDly_Margin_A1==88 ps 9 TxDqDly_Margin_A1==98 ps 10 TrainedVREFDQ_A0==75 TrainedVREFDQ_A1==78 VrefDac_Margin_A0==22 DeviceVref_Margin_A0==39 VrefDac_Margin_A1==22 DeviceVref_Margin_A1==36 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000016 00000017 00000017 00000017 00000017 00000017 00000018 00000018 00000019 00000018 00000017 00000019 00000015 00000018 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001c 00000017 00000016 00000017 dram_vref_reg_value 0x 00000061 2D training succeed aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19 auto size-- 65535DDR cs0 size: 2048MB DDR cs1 size: 2048MB DMC_DDR_CTRL: 00e00024DDR size: 3928MB cs0 DataBus test pass cs1 DataBus test pass cs0 AddrBus test pass cs1 AddrBus test pass 100bdlr_step_size ps== 478 result report boot times 0Enable ddr reg access Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0 bl2z: ptr: 05129330, size: 00001e40 0.0;M3 CHK:0;cm4_sp_mode 0 MVN_1=0x00000000 MVN_2=0x00000000 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz] OPS=0x04 ring efuse init 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50 [0.017319 Inits done] secure task start! high task start! low task start! run into bl31 NOTICE: BL31: v1.3(release):4fc40b1 NOTICE: BL31: Built : 15:57:33, May 22 2019 NOTICE: BL31: G12A normal boot! NOTICE: BL31: BL33 decompress pass ERROR: Error initializing runtime service opteed_fast U-Boot 2024.01-rc4+ (Dec 14 2023 - 02:26:00 -0500) Libre Computer AML-S905D3-CC Model: Libre Computer AML-S905D3-CC Solitude SoC: Amlogic Meson SM1 (S905D3) Revision 2b:c (4:2) DRAM: 2 GiB (effective 3.8 GiB) Core: 406 devices, 33 uclasses, devicetree: separate WDT: Not starting watchdog@f0d0 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0 Loading Environment from FAT... Card did not respond to voltage select! : -110 ** Bad device specification mmc 0 ** Card did not respond to voltage select! : -110 ** Bad device specification mmc 0 ** Couldn't find partition mmc 0 Card did not respond to voltage select! : -110 ** Bad device specification mmc 0 ** Couldn't find partition mmc 0 Error: could not access storage. Net: eth0: ethernet@ff3f0000 starting USB... Bus usb@ff500000: Register 3000140 NbrPorts 3 Starting the controller USB XHCI 1.10 scanning bus usb@ff500000 for devices... 3 USB Device(s) found scanning usb for storage devices... 0 Storage Device(s) found Hit any key to stop autoboot: 1  0 => setenv autoload no setenv autoload no => setenv initrd_high 0xffffffff setenv initrd_high 0xffffffff => setenv fdt_high 0xffffffff setenv fdt_high 0xffffffff => dhcp dhcp ethernet@ff3f0000 Waiting for PHY auto negotiation to complete.. done Speed: 1000, full duplex BOOTP broadcast 1 DHCP client bound to address 192.168.6.21 (8 ms) => setenv serverip 192.168.6.2 setenv serverip 192.168.6.2 => tftpboot 0x01080000 978661/tftp-deploy-qwxh7ob8/kernel/uImage tftpboot 0x01080000 978661/tftp-deploy-qwxh7ob8/kernel/uImage Speed: 1000, full duplex Using ethernet@ff3f0000 device TFTP from server 192.168.6.2; our IP address is 192.168.6.21 Filename '978661/tftp-deploy-qwxh7ob8/kernel/uImage'. Load address: 0x1080000 Loading: *################################################## 44 MiB 14.6 MiB/s done Bytes transferred = 46121536 (2bfc240 hex) => tftpboot 0x08000000 978661/tftp-deploy-qwxh7ob8/ramdisk/ramdisk.cpio.gz.uboot tftpboot 0x08000000 978661/tftp-deploy-qwxh7ob8/ramdisk/ramdisk.cpio.gz.uboot Speed: 1000, full duplex Using ethernet@ff3f0000 device TFTP from server 192.168.6.2; our IP address is 192.168.6.21 Filename '978661/tftp-deploy-qwxh7ob8/ramdisk/ramdisk.cpio.gz.uboot'. Load address: 0x8000000 Loading: *################################################# UDP wrong checksum 00000005 00000659 T UDP wrong checksum 00000005 00000659 T UDP wrong checksum 000000ff 00003f93 UDP wrong checksum 000000ff 0000cb85 T UDP wrong checksum 00000005 00000659 T T T T UDP wrong checksum 00000005 00000659 T T T UDP wrong checksum 000000ff 00004542 UDP wrong checksum 000000ff 0000ce34 Retry count exceeded; starting again =>