Boot log: meson-g12b-a311d-libretech-cc

    1 04:39:04.063122  lava-dispatcher, installed at version: 2024.01
    2 04:39:04.064451  start: 0 validate
    3 04:39:04.064975  Start time: 2024-10-29 04:39:04.064946+00:00 (UTC)
    4 04:39:04.065490  Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
    5 04:39:04.066016  Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
    6 04:39:04.109563  Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
    7 04:39:04.110131  Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fpending-fixes%2Fv6.12-rc5-243-g2f5e60c44402%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
    8 04:39:04.142597  Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
    9 04:39:04.143233  Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fpending-fixes%2Fv6.12-rc5-243-g2f5e60c44402%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
   10 04:39:04.172174  Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
   11 04:39:04.172666  Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
   12 04:39:04.204336  Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
   13 04:39:04.204816  Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fpending-fixes%2Fv6.12-rc5-243-g2f5e60c44402%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
   14 04:39:04.244344  validate duration: 0.18
   16 04:39:04.245206  start: 1 tftp-deploy (timeout 00:10:00) [common]
   17 04:39:04.245549  start: 1.1 download-retry (timeout 00:10:00) [common]
   18 04:39:04.245879  start: 1.1.1 http-download (timeout 00:10:00) [common]
   19 04:39:04.246479  Not decompressing ramdisk as can be used compressed.
   20 04:39:04.246937  downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
   21 04:39:04.247232  saving as /var/lib/lava/dispatcher/tmp/906892/tftp-deploy-hewr7mbe/ramdisk/initrd.cpio.gz
   22 04:39:04.247510  total size: 5628169 (5 MB)
   23 04:39:04.287581  progress   0 % (0 MB)
   24 04:39:04.295716  progress   5 % (0 MB)
   25 04:39:04.303404  progress  10 % (0 MB)
   26 04:39:04.310235  progress  15 % (0 MB)
   27 04:39:04.315040  progress  20 % (1 MB)
   28 04:39:04.318606  progress  25 % (1 MB)
   29 04:39:04.322520  progress  30 % (1 MB)
   30 04:39:04.326454  progress  35 % (1 MB)
   31 04:39:04.330015  progress  40 % (2 MB)
   32 04:39:04.333911  progress  45 % (2 MB)
   33 04:39:04.337450  progress  50 % (2 MB)
   34 04:39:04.341369  progress  55 % (2 MB)
   35 04:39:04.345263  progress  60 % (3 MB)
   36 04:39:04.348752  progress  65 % (3 MB)
   37 04:39:04.352690  progress  70 % (3 MB)
   38 04:39:04.356176  progress  75 % (4 MB)
   39 04:39:04.360054  progress  80 % (4 MB)
   40 04:39:04.363402  progress  85 % (4 MB)
   41 04:39:04.367023  progress  90 % (4 MB)
   42 04:39:04.370547  progress  95 % (5 MB)
   43 04:39:04.373749  progress 100 % (5 MB)
   44 04:39:04.374383  5 MB downloaded in 0.13 s (42.31 MB/s)
   45 04:39:04.374903  end: 1.1.1 http-download (duration 00:00:00) [common]
   47 04:39:04.375812  end: 1.1 download-retry (duration 00:00:00) [common]
   48 04:39:04.376131  start: 1.2 download-retry (timeout 00:10:00) [common]
   49 04:39:04.376406  start: 1.2.1 http-download (timeout 00:10:00) [common]
   50 04:39:04.376880  downloading http://storage.kernelci.org/next/pending-fixes/v6.12-rc5-243-g2f5e60c44402/arm64/defconfig/gcc-12/kernel/Image
   51 04:39:04.377127  saving as /var/lib/lava/dispatcher/tmp/906892/tftp-deploy-hewr7mbe/kernel/Image
   52 04:39:04.377337  total size: 45713920 (43 MB)
   53 04:39:04.377547  No compression specified
   54 04:39:04.418330  progress   0 % (0 MB)
   55 04:39:04.452631  progress   5 % (2 MB)
   56 04:39:04.487777  progress  10 % (4 MB)
   57 04:39:04.522907  progress  15 % (6 MB)
   58 04:39:04.557750  progress  20 % (8 MB)
   59 04:39:04.592492  progress  25 % (10 MB)
   60 04:39:04.627819  progress  30 % (13 MB)
   61 04:39:04.662030  progress  35 % (15 MB)
   62 04:39:04.695117  progress  40 % (17 MB)
   63 04:39:04.727721  progress  45 % (19 MB)
   64 04:39:04.760644  progress  50 % (21 MB)
   65 04:39:04.793600  progress  55 % (24 MB)
   66 04:39:04.826534  progress  60 % (26 MB)
   67 04:39:04.858855  progress  65 % (28 MB)
   68 04:39:04.891433  progress  70 % (30 MB)
   69 04:39:04.924228  progress  75 % (32 MB)
   70 04:39:04.956778  progress  80 % (34 MB)
   71 04:39:04.989117  progress  85 % (37 MB)
   72 04:39:05.021642  progress  90 % (39 MB)
   73 04:39:05.054157  progress  95 % (41 MB)
   74 04:39:05.085698  progress 100 % (43 MB)
   75 04:39:05.086330  43 MB downloaded in 0.71 s (61.49 MB/s)
   76 04:39:05.086905  end: 1.2.1 http-download (duration 00:00:01) [common]
   78 04:39:05.087863  end: 1.2 download-retry (duration 00:00:01) [common]
   79 04:39:05.088260  start: 1.3 download-retry (timeout 00:09:59) [common]
   80 04:39:05.088587  start: 1.3.1 http-download (timeout 00:09:59) [common]
   81 04:39:05.089153  downloading http://storage.kernelci.org/next/pending-fixes/v6.12-rc5-243-g2f5e60c44402/arm64/defconfig/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
   82 04:39:05.089489  saving as /var/lib/lava/dispatcher/tmp/906892/tftp-deploy-hewr7mbe/dtb/meson-g12b-a311d-libretech-cc.dtb
   83 04:39:05.089749  total size: 54703 (0 MB)
   84 04:39:05.090001  No compression specified
   85 04:39:05.126630  progress  59 % (0 MB)
   86 04:39:05.127591  progress 100 % (0 MB)
   87 04:39:05.128287  0 MB downloaded in 0.04 s (1.35 MB/s)
   88 04:39:05.128910  end: 1.3.1 http-download (duration 00:00:00) [common]
   90 04:39:05.129868  end: 1.3 download-retry (duration 00:00:00) [common]
   91 04:39:05.130192  start: 1.4 download-retry (timeout 00:09:59) [common]
   92 04:39:05.130513  start: 1.4.1 http-download (timeout 00:09:59) [common]
   93 04:39:05.131096  downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
   94 04:39:05.131410  saving as /var/lib/lava/dispatcher/tmp/906892/tftp-deploy-hewr7mbe/nfsrootfs/full.rootfs.tar
   95 04:39:05.131660  total size: 120894716 (115 MB)
   96 04:39:05.131916  Using unxz to decompress xz
   97 04:39:05.171810  progress   0 % (0 MB)
   98 04:39:05.959744  progress   5 % (5 MB)
   99 04:39:06.826509  progress  10 % (11 MB)
  100 04:39:07.615629  progress  15 % (17 MB)
  101 04:39:08.352402  progress  20 % (23 MB)
  102 04:39:08.945595  progress  25 % (28 MB)
  103 04:39:09.774221  progress  30 % (34 MB)
  104 04:39:10.568130  progress  35 % (40 MB)
  105 04:39:10.915875  progress  40 % (46 MB)
  106 04:39:11.298803  progress  45 % (51 MB)
  107 04:39:12.056893  progress  50 % (57 MB)
  108 04:39:12.950140  progress  55 % (63 MB)
  109 04:39:13.733404  progress  60 % (69 MB)
  110 04:39:14.495563  progress  65 % (74 MB)
  111 04:39:15.277402  progress  70 % (80 MB)
  112 04:39:16.104251  progress  75 % (86 MB)
  113 04:39:16.898180  progress  80 % (92 MB)
  114 04:39:17.676989  progress  85 % (98 MB)
  115 04:39:18.536588  progress  90 % (103 MB)
  116 04:39:19.315549  progress  95 % (109 MB)
  117 04:39:20.164037  progress 100 % (115 MB)
  118 04:39:20.177218  115 MB downloaded in 15.05 s (7.66 MB/s)
  119 04:39:20.177934  end: 1.4.1 http-download (duration 00:00:15) [common]
  121 04:39:20.179718  end: 1.4 download-retry (duration 00:00:15) [common]
  122 04:39:20.180354  start: 1.5 download-retry (timeout 00:09:44) [common]
  123 04:39:20.180934  start: 1.5.1 http-download (timeout 00:09:44) [common]
  124 04:39:20.181785  downloading http://storage.kernelci.org/next/pending-fixes/v6.12-rc5-243-g2f5e60c44402/arm64/defconfig/gcc-12/modules.tar.xz
  125 04:39:20.182290  saving as /var/lib/lava/dispatcher/tmp/906892/tftp-deploy-hewr7mbe/modules/modules.tar
  126 04:39:20.182745  total size: 11599752 (11 MB)
  127 04:39:20.183212  Using unxz to decompress xz
  128 04:39:20.232652  progress   0 % (0 MB)
  129 04:39:20.301386  progress   5 % (0 MB)
  130 04:39:20.380403  progress  10 % (1 MB)
  131 04:39:20.464876  progress  15 % (1 MB)
  132 04:39:20.540677  progress  20 % (2 MB)
  133 04:39:20.616226  progress  25 % (2 MB)
  134 04:39:20.694788  progress  30 % (3 MB)
  135 04:39:20.767054  progress  35 % (3 MB)
  136 04:39:20.846824  progress  40 % (4 MB)
  137 04:39:20.932711  progress  45 % (5 MB)
  138 04:39:21.008742  progress  50 % (5 MB)
  139 04:39:21.091107  progress  55 % (6 MB)
  140 04:39:21.171097  progress  60 % (6 MB)
  141 04:39:21.254683  progress  65 % (7 MB)
  142 04:39:21.329776  progress  70 % (7 MB)
  143 04:39:21.410916  progress  75 % (8 MB)
  144 04:39:21.492670  progress  80 % (8 MB)
  145 04:39:21.567880  progress  85 % (9 MB)
  146 04:39:21.640019  progress  90 % (9 MB)
  147 04:39:21.738736  progress  95 % (10 MB)
  148 04:39:21.831892  progress 100 % (11 MB)
  149 04:39:21.848346  11 MB downloaded in 1.67 s (6.64 MB/s)
  150 04:39:21.848949  end: 1.5.1 http-download (duration 00:00:02) [common]
  152 04:39:21.849788  end: 1.5 download-retry (duration 00:00:02) [common]
  153 04:39:21.850058  start: 1.6 prepare-tftp-overlay (timeout 00:09:42) [common]
  154 04:39:21.850327  start: 1.6.1 extract-nfsrootfs (timeout 00:09:42) [common]
  155 04:39:38.084817  Extracted nfsroot to /var/lib/lava/dispatcher/tmp/906892/extract-nfsrootfs-2tz2ri7s
  156 04:39:38.085417  end: 1.6.1 extract-nfsrootfs (duration 00:00:16) [common]
  157 04:39:38.085734  start: 1.6.2 lava-overlay (timeout 00:09:26) [common]
  158 04:39:38.086380  [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/906892/lava-overlay-3g6s5_sk
  159 04:39:38.086850  makedir: /var/lib/lava/dispatcher/tmp/906892/lava-overlay-3g6s5_sk/lava-906892/bin
  160 04:39:38.087238  makedir: /var/lib/lava/dispatcher/tmp/906892/lava-overlay-3g6s5_sk/lava-906892/tests
  161 04:39:38.087610  makedir: /var/lib/lava/dispatcher/tmp/906892/lava-overlay-3g6s5_sk/lava-906892/results
  162 04:39:38.088006  Creating /var/lib/lava/dispatcher/tmp/906892/lava-overlay-3g6s5_sk/lava-906892/bin/lava-add-keys
  163 04:39:38.088589  Creating /var/lib/lava/dispatcher/tmp/906892/lava-overlay-3g6s5_sk/lava-906892/bin/lava-add-sources
  164 04:39:38.089150  Creating /var/lib/lava/dispatcher/tmp/906892/lava-overlay-3g6s5_sk/lava-906892/bin/lava-background-process-start
  165 04:39:38.089674  Creating /var/lib/lava/dispatcher/tmp/906892/lava-overlay-3g6s5_sk/lava-906892/bin/lava-background-process-stop
  166 04:39:38.090187  Creating /var/lib/lava/dispatcher/tmp/906892/lava-overlay-3g6s5_sk/lava-906892/bin/lava-common-functions
  167 04:39:38.090665  Creating /var/lib/lava/dispatcher/tmp/906892/lava-overlay-3g6s5_sk/lava-906892/bin/lava-echo-ipv4
  168 04:39:38.091130  Creating /var/lib/lava/dispatcher/tmp/906892/lava-overlay-3g6s5_sk/lava-906892/bin/lava-install-packages
  169 04:39:38.091593  Creating /var/lib/lava/dispatcher/tmp/906892/lava-overlay-3g6s5_sk/lava-906892/bin/lava-installed-packages
  170 04:39:38.092186  Creating /var/lib/lava/dispatcher/tmp/906892/lava-overlay-3g6s5_sk/lava-906892/bin/lava-os-build
  171 04:39:38.092689  Creating /var/lib/lava/dispatcher/tmp/906892/lava-overlay-3g6s5_sk/lava-906892/bin/lava-probe-channel
  172 04:39:38.093161  Creating /var/lib/lava/dispatcher/tmp/906892/lava-overlay-3g6s5_sk/lava-906892/bin/lava-probe-ip
  173 04:39:38.093626  Creating /var/lib/lava/dispatcher/tmp/906892/lava-overlay-3g6s5_sk/lava-906892/bin/lava-target-ip
  174 04:39:38.094083  Creating /var/lib/lava/dispatcher/tmp/906892/lava-overlay-3g6s5_sk/lava-906892/bin/lava-target-mac
  175 04:39:38.094543  Creating /var/lib/lava/dispatcher/tmp/906892/lava-overlay-3g6s5_sk/lava-906892/bin/lava-target-storage
  176 04:39:38.095016  Creating /var/lib/lava/dispatcher/tmp/906892/lava-overlay-3g6s5_sk/lava-906892/bin/lava-test-case
  177 04:39:38.095487  Creating /var/lib/lava/dispatcher/tmp/906892/lava-overlay-3g6s5_sk/lava-906892/bin/lava-test-event
  178 04:39:38.095961  Creating /var/lib/lava/dispatcher/tmp/906892/lava-overlay-3g6s5_sk/lava-906892/bin/lava-test-feedback
  179 04:39:38.096471  Creating /var/lib/lava/dispatcher/tmp/906892/lava-overlay-3g6s5_sk/lava-906892/bin/lava-test-raise
  180 04:39:38.096937  Creating /var/lib/lava/dispatcher/tmp/906892/lava-overlay-3g6s5_sk/lava-906892/bin/lava-test-reference
  181 04:39:38.097403  Creating /var/lib/lava/dispatcher/tmp/906892/lava-overlay-3g6s5_sk/lava-906892/bin/lava-test-runner
  182 04:39:38.097867  Creating /var/lib/lava/dispatcher/tmp/906892/lava-overlay-3g6s5_sk/lava-906892/bin/lava-test-set
  183 04:39:38.098328  Creating /var/lib/lava/dispatcher/tmp/906892/lava-overlay-3g6s5_sk/lava-906892/bin/lava-test-shell
  184 04:39:38.098799  Updating /var/lib/lava/dispatcher/tmp/906892/lava-overlay-3g6s5_sk/lava-906892/bin/lava-add-keys (debian)
  185 04:39:38.099315  Updating /var/lib/lava/dispatcher/tmp/906892/lava-overlay-3g6s5_sk/lava-906892/bin/lava-add-sources (debian)
  186 04:39:38.099825  Updating /var/lib/lava/dispatcher/tmp/906892/lava-overlay-3g6s5_sk/lava-906892/bin/lava-install-packages (debian)
  187 04:39:38.100360  Updating /var/lib/lava/dispatcher/tmp/906892/lava-overlay-3g6s5_sk/lava-906892/bin/lava-installed-packages (debian)
  188 04:39:38.100845  Updating /var/lib/lava/dispatcher/tmp/906892/lava-overlay-3g6s5_sk/lava-906892/bin/lava-os-build (debian)
  189 04:39:38.101266  Creating /var/lib/lava/dispatcher/tmp/906892/lava-overlay-3g6s5_sk/lava-906892/environment
  190 04:39:38.101624  LAVA metadata
  191 04:39:38.101875  - LAVA_JOB_ID=906892
  192 04:39:38.102091  - LAVA_DISPATCHER_IP=192.168.6.2
  193 04:39:38.102447  start: 1.6.2.1 ssh-authorize (timeout 00:09:26) [common]
  194 04:39:38.103380  end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
  195 04:39:38.103685  start: 1.6.2.2 lava-vland-overlay (timeout 00:09:26) [common]
  196 04:39:38.103890  skipped lava-vland-overlay
  197 04:39:38.104192  end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
  198 04:39:38.104447  start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:26) [common]
  199 04:39:38.104663  skipped lava-multinode-overlay
  200 04:39:38.104902  end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
  201 04:39:38.105151  start: 1.6.2.4 test-definition (timeout 00:09:26) [common]
  202 04:39:38.105393  Loading test definitions
  203 04:39:38.105664  start: 1.6.2.4.1 inline-repo-action (timeout 00:09:26) [common]
  204 04:39:38.105881  Using /lava-906892 at stage 0
  205 04:39:38.106963  uuid=906892_1.6.2.4.1 testdef=None
  206 04:39:38.107260  end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
  207 04:39:38.107519  start: 1.6.2.4.2 test-overlay (timeout 00:09:26) [common]
  208 04:39:38.109080  end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
  210 04:39:38.109856  start: 1.6.2.4.3 test-install-overlay (timeout 00:09:26) [common]
  211 04:39:38.111717  end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
  213 04:39:38.112552  start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:26) [common]
  214 04:39:38.114348  runner path: /var/lib/lava/dispatcher/tmp/906892/lava-overlay-3g6s5_sk/lava-906892/0/tests/0_timesync-off test_uuid 906892_1.6.2.4.1
  215 04:39:38.114895  end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
  217 04:39:38.115700  start: 1.6.2.4.5 git-repo-action (timeout 00:09:26) [common]
  218 04:39:38.115927  Using /lava-906892 at stage 0
  219 04:39:38.116310  Fetching tests from https://github.com/kernelci/test-definitions.git
  220 04:39:38.116596  Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/906892/lava-overlay-3g6s5_sk/lava-906892/0/tests/1_kselftest-alsa'
  221 04:39:41.560829  Running '/usr/bin/git checkout kernelci.org
  222 04:39:42.001842  Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/906892/lava-overlay-3g6s5_sk/lava-906892/0/tests/1_kselftest-alsa/automated/linux/kselftest/kselftest.yaml
  223 04:39:42.003283  uuid=906892_1.6.2.4.5 testdef=None
  224 04:39:42.003626  end: 1.6.2.4.5 git-repo-action (duration 00:00:04) [common]
  226 04:39:42.004422  start: 1.6.2.4.6 test-overlay (timeout 00:09:22) [common]
  227 04:39:42.007228  end: 1.6.2.4.6 test-overlay (duration 00:00:00) [common]
  229 04:39:42.008108  start: 1.6.2.4.7 test-install-overlay (timeout 00:09:22) [common]
  230 04:39:42.011857  end: 1.6.2.4.7 test-install-overlay (duration 00:00:00) [common]
  232 04:39:42.012739  start: 1.6.2.4.8 test-runscript-overlay (timeout 00:09:22) [common]
  233 04:39:42.016330  runner path: /var/lib/lava/dispatcher/tmp/906892/lava-overlay-3g6s5_sk/lava-906892/0/tests/1_kselftest-alsa test_uuid 906892_1.6.2.4.5
  234 04:39:42.016622  BOARD='meson-g12b-a311d-libretech-cc'
  235 04:39:42.016828  BRANCH='next'
  236 04:39:42.017026  SKIPFILE='/dev/null'
  237 04:39:42.017222  SKIP_INSTALL='True'
  238 04:39:42.017417  TESTPROG_URL='http://storage.kernelci.org/next/pending-fixes/v6.12-rc5-243-g2f5e60c44402/arm64/defconfig/gcc-12/kselftest.tar.xz'
  239 04:39:42.017617  TST_CASENAME=''
  240 04:39:42.017814  TST_CMDFILES='alsa'
  241 04:39:42.018350  end: 1.6.2.4.8 test-runscript-overlay (duration 00:00:00) [common]
  243 04:39:42.019138  Creating lava-test-runner.conf files
  244 04:39:42.019340  Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/906892/lava-overlay-3g6s5_sk/lava-906892/0 for stage 0
  245 04:39:42.019684  - 0_timesync-off
  246 04:39:42.019922  - 1_kselftest-alsa
  247 04:39:42.020283  end: 1.6.2.4 test-definition (duration 00:00:04) [common]
  248 04:39:42.020566  start: 1.6.2.5 compress-overlay (timeout 00:09:22) [common]
  249 04:40:05.348875  end: 1.6.2.5 compress-overlay (duration 00:00:23) [common]
  250 04:40:05.349315  start: 1.6.2.6 persistent-nfs-overlay (timeout 00:08:59) [common]
  251 04:40:05.349606  end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
  252 04:40:05.349915  end: 1.6.2 lava-overlay (duration 00:00:27) [common]
  253 04:40:05.350208  start: 1.6.3 extract-overlay-ramdisk (timeout 00:08:59) [common]
  254 04:40:05.998676  end: 1.6.3 extract-overlay-ramdisk (duration 00:00:01) [common]
  255 04:40:05.999175  start: 1.6.4 extract-modules (timeout 00:08:58) [common]
  256 04:40:05.999453  extracting modules file /var/lib/lava/dispatcher/tmp/906892/tftp-deploy-hewr7mbe/modules/modules.tar to /var/lib/lava/dispatcher/tmp/906892/extract-nfsrootfs-2tz2ri7s
  257 04:40:07.381742  extracting modules file /var/lib/lava/dispatcher/tmp/906892/tftp-deploy-hewr7mbe/modules/modules.tar to /var/lib/lava/dispatcher/tmp/906892/extract-overlay-ramdisk-fsx1reen/ramdisk
  258 04:40:08.817532  end: 1.6.4 extract-modules (duration 00:00:03) [common]
  259 04:40:08.818000  start: 1.6.5 apply-overlay-tftp (timeout 00:08:55) [common]
  260 04:40:08.818299  [common] Applying overlay to NFS
  261 04:40:08.818531  [common] Applying overlay /var/lib/lava/dispatcher/tmp/906892/compress-overlay-gzj1f5w0/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/906892/extract-nfsrootfs-2tz2ri7s
  262 04:40:11.580927  end: 1.6.5 apply-overlay-tftp (duration 00:00:03) [common]
  263 04:40:11.581385  start: 1.6.6 prepare-kernel (timeout 00:08:53) [common]
  264 04:40:11.581690  start: 1.6.6.1 uboot-prepare-kernel (timeout 00:08:53) [common]
  265 04:40:11.581953  Converting downloaded kernel to a uImage
  266 04:40:11.582281  mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/906892/tftp-deploy-hewr7mbe/kernel/Image /var/lib/lava/dispatcher/tmp/906892/tftp-deploy-hewr7mbe/kernel/uImage
  267 04:40:12.036272  output: Image Name:   
  268 04:40:12.036699  output: Created:      Tue Oct 29 04:40:11 2024
  269 04:40:12.036929  output: Image Type:   AArch64 Linux Kernel Image (uncompressed)
  270 04:40:12.037147  output: Data Size:    45713920 Bytes = 44642.50 KiB = 43.60 MiB
  271 04:40:12.037356  output: Load Address: 01080000
  272 04:40:12.037563  output: Entry Point:  01080000
  273 04:40:12.037768  output: 
  274 04:40:12.038108  end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
  275 04:40:12.038389  end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
  276 04:40:12.038672  start: 1.6.7 configure-preseed-file (timeout 00:08:52) [common]
  277 04:40:12.038941  end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
  278 04:40:12.039210  start: 1.6.8 compress-ramdisk (timeout 00:08:52) [common]
  279 04:40:12.039480  Building ramdisk /var/lib/lava/dispatcher/tmp/906892/extract-overlay-ramdisk-fsx1reen/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/906892/extract-overlay-ramdisk-fsx1reen/ramdisk
  280 04:40:14.235525  >> 166814 blocks

  281 04:40:21.951867  Adding RAMdisk u-boot header.
  282 04:40:21.952556  mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/906892/extract-overlay-ramdisk-fsx1reen/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/906892/extract-overlay-ramdisk-fsx1reen/ramdisk.cpio.gz.uboot
  283 04:40:22.190765  output: Image Name:   
  284 04:40:22.191398  output: Created:      Tue Oct 29 04:40:21 2024
  285 04:40:22.191836  output: Image Type:   AArch64 Linux RAMDisk Image (uncompressed)
  286 04:40:22.192314  output: Data Size:    23433518 Bytes = 22884.29 KiB = 22.35 MiB
  287 04:40:22.192732  output: Load Address: 00000000
  288 04:40:22.193136  output: Entry Point:  00000000
  289 04:40:22.193555  output: 
  290 04:40:22.194623  rename /var/lib/lava/dispatcher/tmp/906892/extract-overlay-ramdisk-fsx1reen/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/906892/tftp-deploy-hewr7mbe/ramdisk/ramdisk.cpio.gz.uboot
  291 04:40:22.195391  end: 1.6.8 compress-ramdisk (duration 00:00:10) [common]
  292 04:40:22.195966  end: 1.6 prepare-tftp-overlay (duration 00:01:00) [common]
  293 04:40:22.196588  start: 1.7 lxc-create-udev-rule-action (timeout 00:08:42) [common]
  294 04:40:22.197096  No LXC device requested
  295 04:40:22.197620  end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
  296 04:40:22.198202  start: 1.8 deploy-device-env (timeout 00:08:42) [common]
  297 04:40:22.198902  end: 1.8 deploy-device-env (duration 00:00:00) [common]
  298 04:40:22.199382  Checking files for TFTP limit of 4294967296 bytes.
  299 04:40:22.202124  end: 1 tftp-deploy (duration 00:01:18) [common]
  300 04:40:22.202702  start: 2 uboot-action (timeout 00:05:00) [common]
  301 04:40:22.203239  start: 2.1 uboot-from-media (timeout 00:05:00) [common]
  302 04:40:22.203745  end: 2.1 uboot-from-media (duration 00:00:00) [common]
  303 04:40:22.204349  start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
  304 04:40:22.204928  Using kernel file from prepare-kernel: 906892/tftp-deploy-hewr7mbe/kernel/uImage
  305 04:40:22.205565  substitutions:
  306 04:40:22.205968  - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
  307 04:40:22.206364  - {DTB_ADDR}: 0x01070000
  308 04:40:22.206755  - {DTB}: 906892/tftp-deploy-hewr7mbe/dtb/meson-g12b-a311d-libretech-cc.dtb
  309 04:40:22.207169  - {INITRD}: 906892/tftp-deploy-hewr7mbe/ramdisk/ramdisk.cpio.gz.uboot
  310 04:40:22.207579  - {KERNEL_ADDR}: 0x01080000
  311 04:40:22.208047  - {KERNEL}: 906892/tftp-deploy-hewr7mbe/kernel/uImage
  312 04:40:22.208472  - {LAVA_MAC}: None
  313 04:40:22.208936  - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/906892/extract-nfsrootfs-2tz2ri7s
  314 04:40:22.209357  - {NFS_SERVER_IP}: 192.168.6.2
  315 04:40:22.209772  - {PRESEED_CONFIG}: None
  316 04:40:22.210177  - {PRESEED_LOCAL}: None
  317 04:40:22.210590  - {RAMDISK_ADDR}: 0x08000000
  318 04:40:22.211000  - {RAMDISK}: 906892/tftp-deploy-hewr7mbe/ramdisk/ramdisk.cpio.gz.uboot
  319 04:40:22.211396  - {ROOT_PART}: None
  320 04:40:22.211787  - {ROOT}: None
  321 04:40:22.212216  - {SERVER_IP}: 192.168.6.2
  322 04:40:22.212610  - {TEE_ADDR}: 0x83000000
  323 04:40:22.213000  - {TEE}: None
  324 04:40:22.213391  Parsed boot commands:
  325 04:40:22.213772  - setenv autoload no
  326 04:40:22.214160  - setenv initrd_high 0xffffffff
  327 04:40:22.214547  - setenv fdt_high 0xffffffff
  328 04:40:22.214952  - dhcp
  329 04:40:22.215532  - setenv serverip 192.168.6.2
  330 04:40:22.216002  - tftpboot 0x01080000 906892/tftp-deploy-hewr7mbe/kernel/uImage
  331 04:40:22.216421  - tftpboot 0x08000000 906892/tftp-deploy-hewr7mbe/ramdisk/ramdisk.cpio.gz.uboot
  332 04:40:22.216824  - tftpboot 0x01070000 906892/tftp-deploy-hewr7mbe/dtb/meson-g12b-a311d-libretech-cc.dtb
  333 04:40:22.217223  - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/906892/extract-nfsrootfs-2tz2ri7s,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
  334 04:40:22.217664  - bootm 0x01080000 0x08000000 0x01070000
  335 04:40:22.218197  end: 2.2 bootloader-overlay (duration 00:00:00) [common]
  337 04:40:22.219724  start: 2.3 connect-device (timeout 00:05:00) [common]
  338 04:40:22.220246  [common] connect-device Connecting to device using 'telnet conserv1 3007'
  339 04:40:22.236382  Setting prompt string to ['lava-test: # ']
  340 04:40:22.237884  end: 2.3 connect-device (duration 00:00:00) [common]
  341 04:40:22.238513  start: 2.4 uboot-commands (timeout 00:05:00) [common]
  342 04:40:22.239091  start: 2.4.1 reset-device (timeout 00:05:00) [common]
  343 04:40:22.239645  start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
  344 04:40:22.240820  Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
  345 04:40:22.278024  >> OK - accepted request

  346 04:40:22.280232  Returned 0 in 0 seconds
  347 04:40:22.381444  end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
  349 04:40:22.383127  end: 2.4.1 reset-device (duration 00:00:00) [common]
  350 04:40:22.383687  start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
  351 04:40:22.384240  Setting prompt string to ['Hit any key to stop autoboot']
  352 04:40:22.384710  bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
  353 04:40:22.386295  Trying 192.168.56.21...
  354 04:40:22.386782  Connected to conserv1.
  355 04:40:22.387201  Escape character is '^]'.
  356 04:40:22.387628  
  357 04:40:22.388119  ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
  358 04:40:22.388571  
  359 04:40:33.845908  G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
  360 04:40:33.846537  bl2_stage_init 0x01
  361 04:40:33.846958  bl2_stage_init 0x81
  362 04:40:33.851741  hw id: 0x0000 - pwm id 0x01
  363 04:40:33.852319  bl2_stage_init 0xc1
  364 04:40:33.852735  bl2_stage_init 0x02
  365 04:40:33.853127  
  366 04:40:33.857090  L0:00000000
  367 04:40:33.857584  L1:20000703
  368 04:40:33.857999  L2:00008067
  369 04:40:33.858406  L3:14000000
  370 04:40:33.862803  B2:00402000
  371 04:40:33.863290  B1:e0f83180
  372 04:40:33.863704  
  373 04:40:33.864128  TE: 58124
  374 04:40:33.864521  
  375 04:40:33.868297  BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
  376 04:40:33.868792  
  377 04:40:33.869195  Board ID = 1
  378 04:40:33.873898  Set A53 clk to 24M
  379 04:40:33.874386  Set A73 clk to 24M
  380 04:40:33.874773  Set clk81 to 24M
  381 04:40:33.879383  A53 clk: 1200 MHz
  382 04:40:33.879839  A73 clk: 1200 MHz
  383 04:40:33.880267  CLK81: 166.6M
  384 04:40:33.880653  smccc: 00012a92
  385 04:40:33.885060  DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
  386 04:40:33.890671  board id: 1
  387 04:40:33.896540  Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
  388 04:40:33.907108  fw parse done
  389 04:40:33.913074  Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
  390 04:40:33.955708  Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
  391 04:40:33.966606  PIEI prepare done
  392 04:40:33.967065  fastboot data load
  393 04:40:33.967458  fastboot data verify
  394 04:40:33.972284  verify result: 266
  395 04:40:33.977871  Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
  396 04:40:33.978332  LPDDR4 probe
  397 04:40:33.978728  ddr clk to 1584MHz
  398 04:40:33.985883  Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
  399 04:40:34.023187  
  400 04:40:34.023688  dmc_version 0001
  401 04:40:34.029817  Check phy result
  402 04:40:34.035730  INFO : End of CA training
  403 04:40:34.036236  INFO : End of initialization
  404 04:40:34.041280  INFO : Training has run successfully!
  405 04:40:34.041738  Check phy result
  406 04:40:34.046900  INFO : End of initialization
  407 04:40:34.047376  INFO : End of read enable training
  408 04:40:34.052538  INFO : End of fine write leveling
  409 04:40:34.058118  INFO : End of Write leveling coarse delay
  410 04:40:34.058577  INFO : Training has run successfully!
  411 04:40:34.058975  Check phy result
  412 04:40:34.063731  INFO : End of initialization
  413 04:40:34.064235  INFO : End of read dq deskew training
  414 04:40:34.069326  INFO : End of MPR read delay center optimization
  415 04:40:34.074967  INFO : End of write delay center optimization
  416 04:40:34.080530  INFO : End of read delay center optimization
  417 04:40:34.081013  INFO : End of max read latency training
  418 04:40:34.086123  INFO : Training has run successfully!
  419 04:40:34.086633  1D training succeed
  420 04:40:34.095292  Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
  421 04:40:34.142842  Check phy result
  422 04:40:34.143343  INFO : End of initialization
  423 04:40:34.165378  INFO : End of 2D read delay Voltage center optimization
  424 04:40:34.185693  INFO : End of 2D read delay Voltage center optimization
  425 04:40:34.237697  INFO : End of 2D write delay Voltage center optimization
  426 04:40:34.287015  INFO : End of 2D write delay Voltage center optimization
  427 04:40:34.292593  INFO : Training has run successfully!
  428 04:40:34.293065  
  429 04:40:34.293463  channel==0
  430 04:40:34.297707  RxClkDly_Margin_A0==88 ps 9
  431 04:40:34.300261  TxDqDly_Margin_A0==98 ps 10
  432 04:40:34.300719  RxClkDly_Margin_A1==88 ps 9
  433 04:40:34.305858  TxDqDly_Margin_A1==98 ps 10
  434 04:40:34.306308  TrainedVREFDQ_A0==74
  435 04:40:34.306708  TrainedVREFDQ_A1==74
  436 04:40:34.311443  VrefDac_Margin_A0==24
  437 04:40:34.311891  DeviceVref_Margin_A0==40
  438 04:40:34.312328  VrefDac_Margin_A1==24
  439 04:40:34.317058  DeviceVref_Margin_A1==40
  440 04:40:34.317516  
  441 04:40:34.317909  
  442 04:40:34.318300  channel==1
  443 04:40:34.322669  RxClkDly_Margin_A0==98 ps 10
  444 04:40:34.323122  TxDqDly_Margin_A0==98 ps 10
  445 04:40:34.328255  RxClkDly_Margin_A1==98 ps 10
  446 04:40:34.328724  TxDqDly_Margin_A1==88 ps 9
  447 04:40:34.329122  TrainedVREFDQ_A0==77
  448 04:40:34.333860  TrainedVREFDQ_A1==77
  449 04:40:34.334311  VrefDac_Margin_A0==22
  450 04:40:34.334707  DeviceVref_Margin_A0==37
  451 04:40:34.339430  VrefDac_Margin_A1==24
  452 04:40:34.339877  DeviceVref_Margin_A1==37
  453 04:40:34.340306  
  454 04:40:34.345143   dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004 
  455 04:40:34.345671  
  456 04:40:34.373028  soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000017 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000017 00000018 00000017 00000019 00000018 0000001a 0000001a 00000018 00000017 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
  457 04:40:34.378707  2D training succeed
  458 04:40:34.384322  aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
  459 04:40:34.389925  auto size-- 65535DDR cs0 size: 2048MB
  460 04:40:34.390434  DDR cs1 size: 2048MB
  461 04:40:34.395504  DMC_DDR_CTRL: 00e00024DDR size: 3928MB
  462 04:40:34.396011  cs0 DataBus test pass
  463 04:40:34.396418  cs1 DataBus test pass
  464 04:40:34.401093  cs0 AddrBus test pass
  465 04:40:34.401576  cs1 AddrBus test pass
  466 04:40:34.401972  
  467 04:40:34.402367  100bdlr_step_size ps== 420
  468 04:40:34.406708  result report
  469 04:40:34.407197  boot times 0Enable ddr reg access
  470 04:40:34.415624  Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
  471 04:40:34.429034  Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
  472 04:40:35.002683  0.0;M3 CHK:0;cm4_sp_mode 0
  473 04:40:35.003241  MVN_1=0x00000000
  474 04:40:35.008184  MVN_2=0x00000000
  475 04:40:35.013913  [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
  476 04:40:35.014368  OPS=0x10
  477 04:40:35.014779  ring efuse init
  478 04:40:35.015180  chipver efuse init
  479 04:40:35.022091  29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50 
  480 04:40:35.022573  [0.018961 Inits done]
  481 04:40:35.029718  secure task start!
  482 04:40:35.030204  high task start!
  483 04:40:35.030614  low task start!
  484 04:40:35.031016  run into bl31
  485 04:40:35.036396  NOTICE:  BL31: v1.3(release):4fc40b1
  486 04:40:35.044171  NOTICE:  BL31: Built : 15:58:17, May 22 2019
  487 04:40:35.044646  NOTICE:  BL31: G12A normal boot!
  488 04:40:35.069511  NOTICE:  BL31: BL33 decompress pass
  489 04:40:35.075163  ERROR:   Error initializing runtime service opteed_fast
  490 04:40:36.308078  
  491 04:40:36.308701  
  492 04:40:36.316408  U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
  493 04:40:36.316891  
  494 04:40:36.317315  Model: Libre Computer AML-A311D-CC Alta
  495 04:40:36.524863  SoC:   Amlogic Meson G12B (A311D) Revision 29:b (10:2)
  496 04:40:36.548234  DRAM:  2 GiB (effective 3.8 GiB)
  497 04:40:36.691268  Core:  408 devices, 31 uclasses, devicetree: separate
  498 04:40:36.697093  WDT:   Not starting watchdog@f0d0
  499 04:40:36.729350  MMC:   mmc@ffe05000: 1, mmc@ffe07000: 0
  500 04:40:36.741783  Loading Environment from FAT... Card did not respond to voltage select! : -110
  501 04:40:36.746924  ** Bad device specification mmc 0 **
  502 04:40:36.757133  Card did not respond to voltage select! : -110
  503 04:40:36.764814  ** Bad device specification mmc 0 **
  504 04:40:36.765303  Couldn't find partition mmc 0
  505 04:40:36.773149  Card did not respond to voltage select! : -110
  506 04:40:36.778720  ** Bad device specification mmc 0 **
  507 04:40:36.779199  Couldn't find partition mmc 0
  508 04:40:36.783699  Error: could not access storage.
  509 04:40:38.046421  G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
  510 04:40:38.047067  bl2_stage_init 0x01
  511 04:40:38.047506  bl2_stage_init 0x81
  512 04:40:38.052052  hw id: 0x0000 - pwm id 0x01
  513 04:40:38.052570  bl2_stage_init 0xc1
  514 04:40:38.052993  bl2_stage_init 0x02
  515 04:40:38.053403  
  516 04:40:38.057489  L0:00000000
  517 04:40:38.057949  L1:20000703
  518 04:40:38.058364  L2:00008067
  519 04:40:38.058775  L3:14000000
  520 04:40:38.063089  B2:00402000
  521 04:40:38.063553  B1:e0f83180
  522 04:40:38.063968  
  523 04:40:38.064415  TE: 58159
  524 04:40:38.064824  
  525 04:40:38.068682  BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
  526 04:40:38.069150  
  527 04:40:38.069566  Board ID = 1
  528 04:40:38.074272  Set A53 clk to 24M
  529 04:40:38.074755  Set A73 clk to 24M
  530 04:40:38.075170  Set clk81 to 24M
  531 04:40:38.079860  A53 clk: 1200 MHz
  532 04:40:38.080356  A73 clk: 1200 MHz
  533 04:40:38.080771  CLK81: 166.6M
  534 04:40:38.081173  smccc: 00012ab5
  535 04:40:38.085490  DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
  536 04:40:38.091094  board id: 1
  537 04:40:38.097041  Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
  538 04:40:38.107628  fw parse done
  539 04:40:38.113606  Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
  540 04:40:38.156197  Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
  541 04:40:38.167146  PIEI prepare done
  542 04:40:38.167603  fastboot data load
  543 04:40:38.168068  fastboot data verify
  544 04:40:38.172719  verify result: 266
  545 04:40:38.178321  Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
  546 04:40:38.178779  LPDDR4 probe
  547 04:40:38.179193  ddr clk to 1584MHz
  548 04:40:38.186300  Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
  549 04:40:38.223572  
  550 04:40:38.224126  dmc_version 0001
  551 04:40:38.230242  Check phy result
  552 04:40:38.236133  INFO : End of CA training
  553 04:40:38.236592  INFO : End of initialization
  554 04:40:38.241696  INFO : Training has run successfully!
  555 04:40:38.242153  Check phy result
  556 04:40:38.247305  INFO : End of initialization
  557 04:40:38.247759  INFO : End of read enable training
  558 04:40:38.252902  INFO : End of fine write leveling
  559 04:40:38.258567  INFO : End of Write leveling coarse delay
  560 04:40:38.259056  INFO : Training has run successfully!
  561 04:40:38.259468  Check phy result
  562 04:40:38.264222  INFO : End of initialization
  563 04:40:38.264720  INFO : End of read dq deskew training
  564 04:40:38.269731  INFO : End of MPR read delay center optimization
  565 04:40:38.275307  INFO : End of write delay center optimization
  566 04:40:38.280903  INFO : End of read delay center optimization
  567 04:40:38.281360  INFO : End of max read latency training
  568 04:40:38.286507  INFO : Training has run successfully!
  569 04:40:38.286960  1D training succeed
  570 04:40:38.295664  Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
  571 04:40:38.343297  Check phy result
  572 04:40:38.343771  INFO : End of initialization
  573 04:40:38.364909  INFO : End of 2D read delay Voltage center optimization
  574 04:40:38.384978  INFO : End of 2D read delay Voltage center optimization
  575 04:40:38.436667  INFO : End of 2D write delay Voltage center optimization
  576 04:40:38.486206  INFO : End of 2D write delay Voltage center optimization
  577 04:40:38.491688  INFO : Training has run successfully!
  578 04:40:38.492202  
  579 04:40:38.492623  channel==0
  580 04:40:38.497306  RxClkDly_Margin_A0==88 ps 9
  581 04:40:38.497764  TxDqDly_Margin_A0==98 ps 10
  582 04:40:38.502914  RxClkDly_Margin_A1==88 ps 9
  583 04:40:38.503371  TxDqDly_Margin_A1==88 ps 9
  584 04:40:38.503787  TrainedVREFDQ_A0==74
  585 04:40:38.508495  TrainedVREFDQ_A1==74
  586 04:40:38.508953  VrefDac_Margin_A0==25
  587 04:40:38.509361  DeviceVref_Margin_A0==40
  588 04:40:38.514207  VrefDac_Margin_A1==25
  589 04:40:38.514686  DeviceVref_Margin_A1==40
  590 04:40:38.515098  
  591 04:40:38.515507  
  592 04:40:38.515907  channel==1
  593 04:40:38.519727  RxClkDly_Margin_A0==98 ps 10
  594 04:40:38.520246  TxDqDly_Margin_A0==88 ps 9
  595 04:40:38.525296  RxClkDly_Margin_A1==98 ps 10
  596 04:40:38.525756  TxDqDly_Margin_A1==88 ps 9
  597 04:40:38.530895  TrainedVREFDQ_A0==76
  598 04:40:38.531356  TrainedVREFDQ_A1==77
  599 04:40:38.531773  VrefDac_Margin_A0==22
  600 04:40:38.536480  DeviceVref_Margin_A0==38
  601 04:40:38.536933  VrefDac_Margin_A1==22
  602 04:40:38.542133  DeviceVref_Margin_A1==37
  603 04:40:38.542604  
  604 04:40:38.543015   dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004 
  605 04:40:38.543423  
  606 04:40:38.575675  soc_vref_reg_value 0x 00000019 00000019 00000018 00000019 00000018 00000019 00000018 00000017 00000017 00000016 00000017 00000015 00000018 00000018 00000017 00000019 00000018 0000001a 0000001a 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
  607 04:40:38.576262  2D training succeed
  608 04:40:38.581319  aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
  609 04:40:38.586921  auto size-- 65535DDR cs0 size: 2048MB
  610 04:40:38.587384  DDR cs1 size: 2048MB
  611 04:40:38.592516  DMC_DDR_CTRL: 00e00024DDR size: 3928MB
  612 04:40:38.592977  cs0 DataBus test pass
  613 04:40:38.598173  cs1 DataBus test pass
  614 04:40:38.598630  cs0 AddrBus test pass
  615 04:40:38.599040  cs1 AddrBus test pass
  616 04:40:38.599441  
  617 04:40:38.603709  100bdlr_step_size ps== 420
  618 04:40:38.604217  result report
  619 04:40:38.609418  boot times 0Enable ddr reg access
  620 04:40:38.614566  Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
  621 04:40:38.627962  Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
  622 04:40:39.200199  0.0;M3 CHK:0;cm4_sp_mode 0
  623 04:40:39.200824  MVN_1=0x00000000
  624 04:40:39.205709  MVN_2=0x00000000
  625 04:40:39.211375  [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
  626 04:40:39.211861  OPS=0x10
  627 04:40:39.212363  ring efuse init
  628 04:40:39.212765  chipver efuse init
  629 04:40:39.217024  29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50 
  630 04:40:39.222618  [0.018961 Inits done]
  631 04:40:39.223079  secure task start!
  632 04:40:39.223469  high task start!
  633 04:40:39.227197  low task start!
  634 04:40:39.227671  run into bl31
  635 04:40:39.233861  NOTICE:  BL31: v1.3(release):4fc40b1
  636 04:40:39.241697  NOTICE:  BL31: Built : 15:58:17, May 22 2019
  637 04:40:39.242154  NOTICE:  BL31: G12A normal boot!
  638 04:40:39.267042  NOTICE:  BL31: BL33 decompress pass
  639 04:40:39.272805  ERROR:   Error initializing runtime service opteed_fast
  640 04:40:40.505789  
  641 04:40:40.506396  
  642 04:40:40.514172  U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
  643 04:40:40.514641  
  644 04:40:40.515052  Model: Libre Computer AML-A311D-CC Alta
  645 04:40:40.722457  SoC:   Amlogic Meson G12B (A311D) Revision 29:b (10:2)
  646 04:40:40.745961  DRAM:  2 GiB (effective 3.8 GiB)
  647 04:40:40.888841  Core:  408 devices, 31 uclasses, devicetree: separate
  648 04:40:40.894759  WDT:   Not starting watchdog@f0d0
  649 04:40:40.926978  MMC:   mmc@ffe05000: 1, mmc@ffe07000: 0
  650 04:40:40.939423  Loading Environment from FAT... Card did not respond to voltage select! : -110
  651 04:40:40.944489  ** Bad device specification mmc 0 **
  652 04:40:40.954694  Card did not respond to voltage select! : -110
  653 04:40:40.962388  ** Bad device specification mmc 0 **
  654 04:40:40.962851  Couldn't find partition mmc 0
  655 04:40:40.970738  Card did not respond to voltage select! : -110
  656 04:40:40.976295  ** Bad device specification mmc 0 **
  657 04:40:40.976754  Couldn't find partition mmc 0
  658 04:40:40.981381  Error: could not access storage.
  659 04:40:41.323869  Net:   eth0: ethernet@ff3f0000
  660 04:40:41.324508  starting USB...
  661 04:40:41.575701  Bus usb@ff500000: Register 3000140 NbrPorts 3
  662 04:40:41.576283  Starting the controller
  663 04:40:41.582782  USB XHCI 1.10
  664 04:40:43.298304  scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
  665 04:40:43.298940  bl2_stage_init 0x01
  666 04:40:43.299373  bl2_stage_init 0x81
  667 04:40:43.303709  hw id: 0x0000 - pwm id 0x01
  668 04:40:43.304212  bl2_stage_init 0xc1
  669 04:40:43.304636  bl2_stage_init 0x02
  670 04:40:43.305044  
  671 04:40:43.309363  L0:00000000
  672 04:40:43.309824  L1:20000703
  673 04:40:43.310240  L2:00008067
  674 04:40:43.310642  L3:14000000
  675 04:40:43.312328  B2:00402000
  676 04:40:43.312786  B1:e0f83180
  677 04:40:43.313199  
  678 04:40:43.313607  TE: 58124
  679 04:40:43.314011  
  680 04:40:43.323210  BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
  681 04:40:43.323490  
  682 04:40:43.323792  Board ID = 1
  683 04:40:43.324239  Set A53 clk to 24M
  684 04:40:43.324644  Set A73 clk to 24M
  685 04:40:43.328995  Set clk81 to 24M
  686 04:40:43.329451  A53 clk: 1200 MHz
  687 04:40:43.329858  A73 clk: 1200 MHz
  688 04:40:43.332550  CLK81: 166.6M
  689 04:40:43.333009  smccc: 00012a92
  690 04:40:43.338110  DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
  691 04:40:43.343649  board id: 1
  692 04:40:43.348811  Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
  693 04:40:43.359470  fw parse done
  694 04:40:43.365417  Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
  695 04:40:43.408068  Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
  696 04:40:43.418941  PIEI prepare done
  697 04:40:43.419443  fastboot data load
  698 04:40:43.419867  fastboot data verify
  699 04:40:43.424565  verify result: 266
  700 04:40:43.430106  Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
  701 04:40:43.430578  LPDDR4 probe
  702 04:40:43.430989  ddr clk to 1584MHz
  703 04:40:43.437968  Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
  704 04:40:43.475373  
  705 04:40:43.475950  dmc_version 0001
  706 04:40:43.482057  Check phy result
  707 04:40:43.487886  INFO : End of CA training
  708 04:40:43.488377  INFO : End of initialization
  709 04:40:43.493487  INFO : Training has run successfully!
  710 04:40:43.493944  Check phy result
  711 04:40:43.499093  INFO : End of initialization
  712 04:40:43.499562  INFO : End of read enable training
  713 04:40:43.504683  INFO : End of fine write leveling
  714 04:40:43.510281  INFO : End of Write leveling coarse delay
  715 04:40:43.510757  INFO : Training has run successfully!
  716 04:40:43.511173  Check phy result
  717 04:40:43.515952  INFO : End of initialization
  718 04:40:43.516468  INFO : End of read dq deskew training
  719 04:40:43.521503  INFO : End of MPR read delay center optimization
  720 04:40:43.527073  INFO : End of write delay center optimization
  721 04:40:43.532685  INFO : End of read delay center optimization
  722 04:40:43.533154  INFO : End of max read latency training
  723 04:40:43.538274  INFO : Training has run successfully!
  724 04:40:43.538736  1D training succeed
  725 04:40:43.547465  Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
  726 04:40:43.595105  Check phy result
  727 04:40:43.595629  INFO : End of initialization
  728 04:40:43.616762  INFO : End of 2D read delay Voltage center optimization
  729 04:40:43.637155  INFO : End of 2D read delay Voltage center optimization
  730 04:40:43.689160  INFO : End of 2D write delay Voltage center optimization
  731 04:40:43.738541  INFO : End of 2D write delay Voltage center optimization
  732 04:40:43.744069  INFO : Training has run successfully!
  733 04:40:43.744563  
  734 04:40:43.744980  channel==0
  735 04:40:43.749715  RxClkDly_Margin_A0==88 ps 9
  736 04:40:43.750199  TxDqDly_Margin_A0==98 ps 10
  737 04:40:43.755232  RxClkDly_Margin_A1==88 ps 9
  738 04:40:43.755722  TxDqDly_Margin_A1==98 ps 10
  739 04:40:43.756175  TrainedVREFDQ_A0==74
  740 04:40:43.760993  TrainedVREFDQ_A1==74
  741 04:40:43.761498  VrefDac_Margin_A0==25
  742 04:40:43.761914  DeviceVref_Margin_A0==40
  743 04:40:43.766512  VrefDac_Margin_A1==25
  744 04:40:43.766989  DeviceVref_Margin_A1==40
  745 04:40:43.767396  
  746 04:40:43.767798  
  747 04:40:43.772054  channel==1
  748 04:40:43.772538  RxClkDly_Margin_A0==98 ps 10
  749 04:40:43.772952  TxDqDly_Margin_A0==98 ps 10
  750 04:40:43.777697  RxClkDly_Margin_A1==88 ps 9
  751 04:40:43.778193  TxDqDly_Margin_A1==88 ps 9
  752 04:40:43.783300  TrainedVREFDQ_A0==77
  753 04:40:43.783775  TrainedVREFDQ_A1==77
  754 04:40:43.784231  VrefDac_Margin_A0==22
  755 04:40:43.788913  DeviceVref_Margin_A0==37
  756 04:40:43.789385  VrefDac_Margin_A1==24
  757 04:40:43.794398  DeviceVref_Margin_A1==37
  758 04:40:43.794870  
  759 04:40:43.795284   dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004 
  760 04:40:43.795690  
  761 04:40:43.827952  soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000017 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000017 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
  762 04:40:43.828543  2D training succeed
  763 04:40:43.833619  aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
  764 04:40:43.839171  auto size-- 65535DDR cs0 size: 2048MB
  765 04:40:43.839653  DDR cs1 size: 2048MB
  766 04:40:43.844801  DMC_DDR_CTRL: 00e00024DDR size: 3928MB
  767 04:40:43.845280  cs0 DataBus test pass
  768 04:40:43.850366  cs1 DataBus test pass
  769 04:40:43.850838  cs0 AddrBus test pass
  770 04:40:43.851247  cs1 AddrBus test pass
  771 04:40:43.851648  
  772 04:40:43.856011  100bdlr_step_size ps== 420
  773 04:40:43.856519  result report
  774 04:40:43.861543  boot times 0Enable ddr reg access
  775 04:40:43.866989  Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
  776 04:40:43.880344  Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
  777 04:40:44.453951  0.0;M3 CHK:0;cm4_sp_mode 0
  778 04:40:44.454359  MVN_1=0x00000000
  779 04:40:44.459480  MVN_2=0x00000000
  780 04:40:44.465241  [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
  781 04:40:44.465575  OPS=0x10
  782 04:40:44.465807  ring efuse init
  783 04:40:44.466017  chipver efuse init
  784 04:40:44.470873  29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50 
  785 04:40:44.476421  [0.018961 Inits done]
  786 04:40:44.476739  secure task start!
  787 04:40:44.476968  high task start!
  788 04:40:44.481026  low task start!
  789 04:40:44.481346  run into bl31
  790 04:40:44.487762  NOTICE:  BL31: v1.3(release):4fc40b1
  791 04:40:44.495446  NOTICE:  BL31: Built : 15:58:17, May 22 2019
  792 04:40:44.495758  NOTICE:  BL31: G12A normal boot!
  793 04:40:44.520971  NOTICE:  BL31: BL33 decompress pass
  794 04:40:44.526553  ERROR:   Error initializing runtime service opteed_fast
  795 04:40:45.759432  
  796 04:40:45.759894  
  797 04:40:45.767861  U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
  798 04:40:45.768327  
  799 04:40:45.768571  Model: Libre Computer AML-A311D-CC Alta
  800 04:40:45.976240  SoC:   Amlogic Meson G12B (A311D) Revision 29:b (10:2)
  801 04:40:45.999647  DRAM:  2 GiB (effective 3.8 GiB)
  802 04:40:46.142633  Core:  408 devices, 31 uclasses, devicetree: separate
  803 04:40:46.148478  WDT:   Not starting watchdog@f0d0
  804 04:40:46.180780  MMC:   mmc@ffe05000: 1, mmc@ffe07000: 0
  805 04:40:46.193270  Loading Environment from FAT... Card did not respond to voltage select! : -110
  806 04:40:46.198192  ** Bad device specification mmc 0 **
  807 04:40:46.208544  Card did not respond to voltage select! : -110
  808 04:40:46.216214  ** Bad device specification mmc 0 **
  809 04:40:46.216572  Couldn't find partition mmc 0
  810 04:40:46.224534  Card did not respond to voltage select! : -110
  811 04:40:46.230017  ** Bad device specification mmc 0 **
  812 04:40:46.230354  Couldn't find partition mmc 0
  813 04:40:46.235089  Error: could not access storage.
  814 04:40:46.577589  Net:   eth0: ethernet@ff3f0000
  815 04:40:46.578015  starting USB...
  816 04:40:46.829420  Bus usb@ff500000: Register 3000140 NbrPorts 3
  817 04:40:46.829846  Starting the controller
  818 04:40:46.836256  USB XHCI 1.10
  819 04:40:48.996654  scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
  820 04:40:48.997289  bl2_stage_init 0x01
  821 04:40:48.997726  bl2_stage_init 0x81
  822 04:40:49.002189  hw id: 0x0000 - pwm id 0x01
  823 04:40:49.002710  bl2_stage_init 0xc1
  824 04:40:49.003151  bl2_stage_init 0x02
  825 04:40:49.003551  
  826 04:40:49.007795  L0:00000000
  827 04:40:49.008331  L1:20000703
  828 04:40:49.008755  L2:00008067
  829 04:40:49.009168  L3:14000000
  830 04:40:49.010737  B2:00402000
  831 04:40:49.011227  B1:e0f83180
  832 04:40:49.011657  
  833 04:40:49.012107  TE: 58124
  834 04:40:49.012529  
  835 04:40:49.021855  BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
  836 04:40:49.022393  
  837 04:40:49.022803  Board ID = 1
  838 04:40:49.023211  Set A53 clk to 24M
  839 04:40:49.023619  Set A73 clk to 24M
  840 04:40:49.027603  Set clk81 to 24M
  841 04:40:49.028119  A53 clk: 1200 MHz
  842 04:40:49.028547  A73 clk: 1200 MHz
  843 04:40:49.033162  CLK81: 166.6M
  844 04:40:49.033655  smccc: 00012a92
  845 04:40:49.038735  DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
  846 04:40:49.039236  board id: 1
  847 04:40:49.047490  Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
  848 04:40:49.057839  fw parse done
  849 04:40:49.063792  Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
  850 04:40:49.106383  Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
  851 04:40:49.117293  PIEI prepare done
  852 04:40:49.117825  fastboot data load
  853 04:40:49.118262  fastboot data verify
  854 04:40:49.122998  verify result: 266
  855 04:40:49.128604  Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
  856 04:40:49.129103  LPDDR4 probe
  857 04:40:49.129518  ddr clk to 1584MHz
  858 04:40:49.136614  Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
  859 04:40:49.173894  
  860 04:40:49.174510  dmc_version 0001
  861 04:40:49.180743  Check phy result
  862 04:40:49.186449  INFO : End of CA training
  863 04:40:49.187195  INFO : End of initialization
  864 04:40:49.192064  INFO : Training has run successfully!
  865 04:40:49.192823  Check phy result
  866 04:40:49.197588  INFO : End of initialization
  867 04:40:49.198298  INFO : End of read enable training
  868 04:40:49.203193  INFO : End of fine write leveling
  869 04:40:49.208737  INFO : End of Write leveling coarse delay
  870 04:40:49.209256  INFO : Training has run successfully!
  871 04:40:49.209683  Check phy result
  872 04:40:49.214365  INFO : End of initialization
  873 04:40:49.214854  INFO : End of read dq deskew training
  874 04:40:49.219966  INFO : End of MPR read delay center optimization
  875 04:40:49.225577  INFO : End of write delay center optimization
  876 04:40:49.231166  INFO : End of read delay center optimization
  877 04:40:49.231668  INFO : End of max read latency training
  878 04:40:49.236739  INFO : Training has run successfully!
  879 04:40:49.237214  1D training succeed
  880 04:40:49.245932  Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
  881 04:40:49.293526  Check phy result
  882 04:40:49.294039  INFO : End of initialization
  883 04:40:49.315314  INFO : End of 2D read delay Voltage center optimization
  884 04:40:49.335420  INFO : End of 2D read delay Voltage center optimization
  885 04:40:49.387628  INFO : End of 2D write delay Voltage center optimization
  886 04:40:49.436823  INFO : End of 2D write delay Voltage center optimization
  887 04:40:49.442366  INFO : Training has run successfully!
  888 04:40:49.442873  
  889 04:40:49.443294  channel==0
  890 04:40:49.447946  RxClkDly_Margin_A0==88 ps 9
  891 04:40:49.448459  TxDqDly_Margin_A0==98 ps 10
  892 04:40:49.453565  RxClkDly_Margin_A1==88 ps 9
  893 04:40:49.454054  TxDqDly_Margin_A1==88 ps 9
  894 04:40:49.454476  TrainedVREFDQ_A0==74
  895 04:40:49.459196  TrainedVREFDQ_A1==74
  896 04:40:49.459778  VrefDac_Margin_A0==25
  897 04:40:49.460219  DeviceVref_Margin_A0==40
  898 04:40:49.464809  VrefDac_Margin_A1==25
  899 04:40:49.465386  DeviceVref_Margin_A1==40
  900 04:40:49.465782  
  901 04:40:49.466172  
  902 04:40:49.466561  channel==1
  903 04:40:49.470355  RxClkDly_Margin_A0==98 ps 10
  904 04:40:49.470833  TxDqDly_Margin_A0==98 ps 10
  905 04:40:49.475945  RxClkDly_Margin_A1==88 ps 9
  906 04:40:49.476454  TxDqDly_Margin_A1==98 ps 10
  907 04:40:49.481572  TrainedVREFDQ_A0==77
  908 04:40:49.482034  TrainedVREFDQ_A1==78
  909 04:40:49.482426  VrefDac_Margin_A0==22
  910 04:40:49.487141  DeviceVref_Margin_A0==37
  911 04:40:49.487595  VrefDac_Margin_A1==24
  912 04:40:49.492747  DeviceVref_Margin_A1==36
  913 04:40:49.493210  
  914 04:40:49.493606   dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004 
  915 04:40:49.493999  
  916 04:40:49.526376  soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000018 00000018 00000016 00000017 00000015 00000017 00000018 00000017 00000019 00000018 00000019 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
  917 04:40:49.526870  2D training succeed
  918 04:40:49.531961  aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
  919 04:40:49.537561  auto size-- 65535DDR cs0 size: 2048MB
  920 04:40:49.537986  DDR cs1 size: 2048MB
  921 04:40:49.543138  DMC_DDR_CTRL: 00e00024DDR size: 3928MB
  922 04:40:49.543564  cs0 DataBus test pass
  923 04:40:49.548749  cs1 DataBus test pass
  924 04:40:49.549175  cs0 AddrBus test pass
  925 04:40:49.549565  cs1 AddrBus test pass
  926 04:40:49.549949  
  927 04:40:49.554445  100bdlr_step_size ps== 420
  928 04:40:49.555125  result report
  929 04:40:49.559976  boot times 0Enable ddr reg access
  930 04:40:49.565281  Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
  931 04:40:49.578875  Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
  932 04:40:50.152719  0.0;M3 CHK:0;cm4_sp_mode 0
  933 04:40:50.153546  MVN_1=0x00000000
  934 04:40:50.158036  MVN_2=0x00000000
  935 04:40:50.163781  [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
  936 04:40:50.164433  OPS=0x10
  937 04:40:50.164985  ring efuse init
  938 04:40:50.165517  chipver efuse init
  939 04:40:50.169391  29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50 
  940 04:40:50.174976  [0.018961 Inits done]
  941 04:40:50.175563  secure task start!
  942 04:40:50.176137  high task start!
  943 04:40:50.179632  low task start!
  944 04:40:50.180236  run into bl31
  945 04:40:50.186230  NOTICE:  BL31: v1.3(release):4fc40b1
  946 04:40:50.194036  NOTICE:  BL31: Built : 15:58:17, May 22 2019
  947 04:40:50.194631  NOTICE:  BL31: G12A normal boot!
  948 04:40:50.219395  NOTICE:  BL31: BL33 decompress pass
  949 04:40:50.225092  ERROR:   Error initializing runtime service opteed_fast
  950 04:40:51.458113  
  951 04:40:51.458966  
  952 04:40:51.466412  U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
  953 04:40:51.467079  
  954 04:40:51.467631  Model: Libre Computer AML-A311D-CC Alta
  955 04:40:51.674983  SoC:   Amlogic Meson G12B (A311D) Revision 29:b (10:2)
  956 04:40:51.698311  DRAM:  2 GiB (effective 3.8 GiB)
  957 04:40:51.841268  Core:  408 devices, 31 uclasses, devicetree: separate
  958 04:40:51.848644  WDT:   Not starting watchdog@f0d0
  959 04:40:51.879346  MMC:   mmc@ffe05000: 1, mmc@ffe07000: 0
  960 04:40:51.891757  Loading Environment from FAT... Card did not respond to voltage select! : -110
  961 04:40:51.896741  ** Bad device specification mmc 0 **
  962 04:40:51.907124  Card did not respond to voltage select! : -110
  963 04:40:51.914767  ** Bad device specification mmc 0 **
  964 04:40:51.915396  Couldn't find partition mmc 0
  965 04:40:51.923087  Card did not respond to voltage select! : -110
  966 04:40:51.928592  ** Bad device specification mmc 0 **
  967 04:40:51.929226  Couldn't find partition mmc 0
  968 04:40:51.933644  Error: could not access storage.
  969 04:40:52.277276  Net:   eth0: ethernet@ff3f0000
  970 04:40:52.278067  starting USB...
  971 04:40:52.529042  Bus usb@ff500000: Register 3000140 NbrPorts 3
  972 04:40:52.529810  Starting the controller
  973 04:40:52.535975  USB XHCI 1.10
  974 04:40:54.396539  scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
  975 04:40:54.397336  bl2_stage_init 0x01
  976 04:40:54.397890  bl2_stage_init 0x81
  977 04:40:54.402147  hw id: 0x0000 - pwm id 0x01
  978 04:40:54.402729  bl2_stage_init 0xc1
  979 04:40:54.403255  bl2_stage_init 0x02
  980 04:40:54.403790  
  981 04:40:54.407639  L0:00000000
  982 04:40:54.408240  L1:20000703
  983 04:40:54.408788  L2:00008067
  984 04:40:54.409311  L3:14000000
  985 04:40:54.410592  B2:00402000
  986 04:40:54.411139  B1:e0f83180
  987 04:40:54.411671  
  988 04:40:54.412240  TE: 58124
  989 04:40:54.412775  
  990 04:40:54.421621  BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
  991 04:40:54.422209  
  992 04:40:54.422736  Board ID = 1
  993 04:40:54.423261  Set A53 clk to 24M
  994 04:40:54.423776  Set A73 clk to 24M
  995 04:40:54.427329  Set clk81 to 24M
  996 04:40:54.427886  A53 clk: 1200 MHz
  997 04:40:54.428452  A73 clk: 1200 MHz
  998 04:40:54.432912  CLK81: 166.6M
  999 04:40:54.433475  smccc: 00012a92
 1000 04:40:54.438449  DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
 1001 04:40:54.439008  board id: 1
 1002 04:40:54.447028  Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
 1003 04:40:54.457639  fw parse done
 1004 04:40:54.463676  Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
 1005 04:40:54.506300  Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
 1006 04:40:54.517214  PIEI prepare done
 1007 04:40:54.517770  fastboot data load
 1008 04:40:54.518285  fastboot data verify
 1009 04:40:54.522755  verify result: 266
 1010 04:40:54.528365  Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
 1011 04:40:54.528916  LPDDR4 probe
 1012 04:40:54.529424  ddr clk to 1584MHz
 1013 04:40:54.536430  Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
 1014 04:40:54.573831  
 1015 04:40:54.574373  dmc_version 0001
 1016 04:40:54.580478  Check phy result
 1017 04:40:54.586381  INFO : End of CA training
 1018 04:40:54.586928  INFO : End of initialization
 1019 04:40:54.591903  INFO : Training has run successfully!
 1020 04:40:54.592480  Check phy result
 1021 04:40:54.597483  INFO : End of initialization
 1022 04:40:54.598013  INFO : End of read enable training
 1023 04:40:54.600809  INFO : End of fine write leveling
 1024 04:40:54.606354  INFO : End of Write leveling coarse delay
 1025 04:40:54.611897  INFO : Training has run successfully!
 1026 04:40:54.612425  Check phy result
 1027 04:40:54.612821  INFO : End of initialization
 1028 04:40:54.617523  INFO : End of read dq deskew training
 1029 04:40:54.623101  INFO : End of MPR read delay center optimization
 1030 04:40:54.623604  INFO : End of write delay center optimization
 1031 04:40:54.628700  INFO : End of read delay center optimization
 1032 04:40:54.634358  INFO : End of max read latency training
 1033 04:40:54.634865  INFO : Training has run successfully!
 1034 04:40:54.639919  1D training succeed
 1035 04:40:54.645917  Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
 1036 04:40:54.693483  Check phy result
 1037 04:40:54.694035  INFO : End of initialization
 1038 04:40:54.715174  INFO : End of 2D read delay Voltage center optimization
 1039 04:40:54.735534  INFO : End of 2D read delay Voltage center optimization
 1040 04:40:54.787517  INFO : End of 2D write delay Voltage center optimization
 1041 04:40:54.836906  INFO : End of 2D write delay Voltage center optimization
 1042 04:40:54.842519  INFO : Training has run successfully!
 1043 04:40:54.843057  
 1044 04:40:54.843499  channel==0
 1045 04:40:54.848181  RxClkDly_Margin_A0==88 ps 9
 1046 04:40:54.848748  TxDqDly_Margin_A0==98 ps 10
 1047 04:40:54.851455  RxClkDly_Margin_A1==88 ps 9
 1048 04:40:54.852018  TxDqDly_Margin_A1==88 ps 9
 1049 04:40:54.856965  TrainedVREFDQ_A0==74
 1050 04:40:54.857508  TrainedVREFDQ_A1==74
 1051 04:40:54.857949  VrefDac_Margin_A0==25
 1052 04:40:54.862539  DeviceVref_Margin_A0==40
 1053 04:40:54.863079  VrefDac_Margin_A1==25
 1054 04:40:54.868120  DeviceVref_Margin_A1==40
 1055 04:40:54.868660  
 1056 04:40:54.869091  
 1057 04:40:54.869512  channel==1
 1058 04:40:54.869922  RxClkDly_Margin_A0==98 ps 10
 1059 04:40:54.873762  TxDqDly_Margin_A0==98 ps 10
 1060 04:40:54.874290  RxClkDly_Margin_A1==98 ps 10
 1061 04:40:54.879371  TxDqDly_Margin_A1==108 ps 11
 1062 04:40:54.879894  TrainedVREFDQ_A0==77
 1063 04:40:54.880366  TrainedVREFDQ_A1==78
 1064 04:40:54.884890  VrefDac_Margin_A0==22
 1065 04:40:54.885419  DeviceVref_Margin_A0==37
 1066 04:40:54.890483  VrefDac_Margin_A1==24
 1067 04:40:54.891010  DeviceVref_Margin_A1==36
 1068 04:40:54.891432  
 1069 04:40:54.896044   dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004 
 1070 04:40:54.896571  
 1071 04:40:54.923965  soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000017 00000019 00000018 00000019 0000001a 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
 1072 04:40:54.929657  2D training succeed
 1073 04:40:54.935273  aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
 1074 04:40:54.935807  auto size-- 65535DDR cs0 size: 2048MB
 1075 04:40:54.940915  DDR cs1 size: 2048MB
 1076 04:40:54.941458  DMC_DDR_CTRL: 00e00024DDR size: 3928MB
 1077 04:40:54.946512  cs0 DataBus test pass
 1078 04:40:54.947040  cs1 DataBus test pass
 1079 04:40:54.947469  cs0 AddrBus test pass
 1080 04:40:54.952084  cs1 AddrBus test pass
 1081 04:40:54.952616  
 1082 04:40:54.953049  100bdlr_step_size ps== 420
 1083 04:40:54.953475  result report
 1084 04:40:54.957677  boot times 0Enable ddr reg access
 1085 04:40:54.965595  Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
 1086 04:40:54.978992  Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
 1087 04:40:55.552055  0.0;M3 CHK:0;cm4_sp_mode 0
 1088 04:40:55.552515  MVN_1=0x00000000
 1089 04:40:55.557495  MVN_2=0x00000000
 1090 04:40:55.563297  [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
 1091 04:40:55.563717  OPS=0x10
 1092 04:40:55.563936  ring efuse init
 1093 04:40:55.564191  chipver efuse init
 1094 04:40:55.568907  29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50 
 1095 04:40:55.574513  [0.018961 Inits done]
 1096 04:40:55.575070  secure task start!
 1097 04:40:55.575326  high task start!
 1098 04:40:55.579038  low task start!
 1099 04:40:55.579440  run into bl31
 1100 04:40:55.585739  NOTICE:  BL31: v1.3(release):4fc40b1
 1101 04:40:55.593548  NOTICE:  BL31: Built : 15:58:17, May 22 2019
 1102 04:40:55.594123  NOTICE:  BL31: G12A normal boot!
 1103 04:40:55.618963  NOTICE:  BL31: BL33 decompress pass
 1104 04:40:55.624612  ERROR:   Error initializing runtime service opteed_fast
 1105 04:40:56.857498  
 1106 04:40:56.858124  
 1107 04:40:56.865872  U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
 1108 04:40:56.866376  
 1109 04:40:56.866818  Model: Libre Computer AML-A311D-CC Alta
 1110 04:40:57.074259  SoC:   Amlogic Meson G12B (A311D) Revision 29:b (10:2)
 1111 04:40:57.097715  DRAM:  2 GiB (effective 3.8 GiB)
 1112 04:40:57.240576  Core:  408 devices, 31 uclasses, devicetree: separate
 1113 04:40:57.246401  WDT:   Not starting watchdog@f0d0
 1114 04:40:57.278730  MMC:   mmc@ffe05000: 1, mmc@ffe07000: 0
 1115 04:40:57.291079  Loading Environment from FAT... Card did not respond to voltage select! : -110
 1116 04:40:57.296131  ** Bad device specification mmc 0 **
 1117 04:40:57.306415  Card did not respond to voltage select! : -110
 1118 04:40:57.314066  ** Bad device specification mmc 0 **
 1119 04:40:57.314562  Couldn't find partition mmc 0
 1120 04:40:57.322426  Card did not respond to voltage select! : -110
 1121 04:40:57.327935  ** Bad device specification mmc 0 **
 1122 04:40:57.328457  Couldn't find partition mmc 0
 1123 04:40:57.332997  Error: could not access storage.
 1124 04:40:57.676499  Net:   eth0: ethernet@ff3f0000
 1125 04:40:57.677055  starting USB...
 1126 04:40:57.928366  Bus usb@ff500000: Register 3000140 NbrPorts 3
 1127 04:40:57.928907  Starting the controller
 1128 04:40:57.935325  USB XHCI 1.10
 1129 04:40:59.489431  scanning bus usb@ff500000 for devices... 3 USB Device(s) found
 1130 04:40:59.497730         scanning usb for storage devices... 0 Storage Device(s) found
 1132 04:40:59.549302  Hit any key to stop autoboot:  1 
 1133 04:40:59.550330  end: 2.4.2 bootloader-interrupt (duration 00:00:37) [common]
 1134 04:40:59.551095  start: 2.4.3 bootloader-commands (timeout 00:04:23) [common]
 1135 04:40:59.551567  Setting prompt string to ['=>']
 1136 04:40:59.552086  bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:23)
 1137 04:40:59.565153   0 
 1138 04:40:59.566036  Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
 1139 04:40:59.566515  Sending with 10 millisecond of delay
 1141 04:41:00.701165  => setenv autoload no
 1142 04:41:00.711968  bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:21)
 1143 04:41:00.716852  setenv autoload no
 1144 04:41:00.717588  Sending with 10 millisecond of delay
 1146 04:41:02.515288  => setenv initrd_high 0xffffffff
 1147 04:41:02.526037  bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:20)
 1148 04:41:02.526877  setenv initrd_high 0xffffffff
 1149 04:41:02.527631  Sending with 10 millisecond of delay
 1151 04:41:04.143953  => setenv fdt_high 0xffffffff
 1152 04:41:04.154765  bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
 1153 04:41:04.155608  setenv fdt_high 0xffffffff
 1154 04:41:04.156354  Sending with 10 millisecond of delay
 1156 04:41:04.448142  => dhcp
 1157 04:41:04.458891  bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
 1158 04:41:04.459745  dhcp
 1159 04:41:04.460239  Speed: 1000, full duplex
 1160 04:41:04.460658  BOOTP broadcast 1
 1161 04:41:04.467224  DHCP client bound to address 192.168.6.27 (8 ms)
 1162 04:41:04.467963  Sending with 10 millisecond of delay
 1164 04:41:06.144289  => setenv serverip 192.168.6.2
 1165 04:41:06.155124  bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:16)
 1166 04:41:06.156160  setenv serverip 192.168.6.2
 1167 04:41:06.156878  Sending with 10 millisecond of delay
 1169 04:41:09.881968  => tftpboot 0x01080000 906892/tftp-deploy-hewr7mbe/kernel/uImage
 1170 04:41:09.892725  bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:12)
 1171 04:41:09.893567  tftpboot 0x01080000 906892/tftp-deploy-hewr7mbe/kernel/uImage
 1172 04:41:09.894012  Speed: 1000, full duplex
 1173 04:41:09.894425  Using ethernet@ff3f0000 device
 1174 04:41:09.895669  TFTP from server 192.168.6.2; our IP address is 192.168.6.27
 1175 04:41:09.901116  Filename '906892/tftp-deploy-hewr7mbe/kernel/uImage'.
 1176 04:41:09.904886  Load address: 0x1080000
 1177 04:41:11.851912  Loading: *############################# UDP wrong checksum 000000ff 0000be33
 1178 04:41:11.863869   UDP wrong checksum 000000ff 00005426
 1179 04:41:12.126158  #### UDP wrong checksum 000000ff 0000d810
 1180 04:41:12.173332  # UDP wrong checksum 000000ff 00007303
 1181 04:41:13.182847  ################  43.6 MiB
 1182 04:41:13.183514  	 13.3 MiB/s
 1183 04:41:13.184092  done
 1184 04:41:13.186978  Bytes transferred = 45713984 (2b98a40 hex)
 1185 04:41:13.187785  Sending with 10 millisecond of delay
 1187 04:41:17.879221  => tftpboot 0x08000000 906892/tftp-deploy-hewr7mbe/ramdisk/ramdisk.cpio.gz.uboot
 1188 04:41:17.889856  bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:04)
 1189 04:41:17.890409  tftpboot 0x08000000 906892/tftp-deploy-hewr7mbe/ramdisk/ramdisk.cpio.gz.uboot
 1190 04:41:17.890659  Speed: 1000, full duplex
 1191 04:41:17.890877  Using ethernet@ff3f0000 device
 1192 04:41:17.892476  TFTP from server 192.168.6.2; our IP address is 192.168.6.27
 1193 04:41:17.901157  Filename '906892/tftp-deploy-hewr7mbe/ramdisk/ramdisk.cpio.gz.uboot'.
 1194 04:41:17.901537  Load address: 0x8000000
 1195 04:41:24.783739  Loading: *###T ###############################################  22.3 MiB
 1196 04:41:24.784167  	 3.2 MiB/s
 1197 04:41:24.784384  done
 1198 04:41:24.788042  Bytes transferred = 23433582 (165916e hex)
 1199 04:41:24.788639  Sending with 10 millisecond of delay
 1201 04:41:29.962173  => tftpboot 0x01070000 906892/tftp-deploy-hewr7mbe/dtb/meson-g12b-a311d-libretech-cc.dtb
 1202 04:41:29.973044  bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:03:52)
 1203 04:41:29.973584  tftpboot 0x01070000 906892/tftp-deploy-hewr7mbe/dtb/meson-g12b-a311d-libretech-cc.dtb
 1204 04:41:29.973838  Speed: 1000, full duplex
 1205 04:41:29.974049  Using ethernet@ff3f0000 device
 1206 04:41:29.977864  TFTP from server 192.168.6.2; our IP address is 192.168.6.27
 1207 04:41:29.985306  Filename '906892/tftp-deploy-hewr7mbe/dtb/meson-g12b-a311d-libretech-cc.dtb'.
 1208 04:41:29.996257  Load address: 0x1070000
 1209 04:41:30.007929  Loading: *##################################################  53.4 KiB
 1210 04:41:30.008420  	 3.1 MiB/s
 1211 04:41:30.008759  done
 1212 04:41:30.012628  Bytes transferred = 54703 (d5af hex)
 1213 04:41:30.013298  Sending with 10 millisecond of delay
 1215 04:41:43.317735  => setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/906892/extract-nfsrootfs-2tz2ri7s,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
 1216 04:41:43.328548  bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:03:39)
 1217 04:41:43.329420  setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/906892/extract-nfsrootfs-2tz2ri7s,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
 1218 04:41:43.330129  Sending with 10 millisecond of delay
 1220 04:41:45.669136  => bootm 0x01080000 0x08000000 0x01070000
 1221 04:41:45.679958  Setting prompt string to ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
 1222 04:41:45.680596  bootloader-commands: Wait for prompt ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:03:37)
 1223 04:41:45.681591  bootm 0x01080000 0x08000000 0x01070000
 1224 04:41:45.682037  ## Booting kernel from Legacy Image at 01080000 ...
 1225 04:41:45.684976     Image Name:   
 1226 04:41:45.690467     Image Type:   AArch64 Linux Kernel Image (uncompressed)
 1227 04:41:45.690955     Data Size:    45713920 Bytes = 43.6 MiB
 1228 04:41:45.696022     Load Address: 01080000
 1229 04:41:45.696513     Entry Point:  01080000
 1230 04:41:45.891328     Verifying Checksum ... OK
 1231 04:41:45.891937  ## Loading init Ramdisk from Legacy Image at 08000000 ...
 1232 04:41:45.896723     Image Name:   
 1233 04:41:45.902165     Image Type:   AArch64 Linux RAMDisk Image (uncompressed)
 1234 04:41:45.902641     Data Size:    23433518 Bytes = 22.3 MiB
 1235 04:41:45.904519     Load Address: 00000000
 1236 04:41:45.911788     Entry Point:  00000000
 1237 04:41:46.009983     Verifying Checksum ... OK
 1238 04:41:46.010594  ## Flattened Device Tree blob at 01070000
 1239 04:41:46.015435     Booting using the fdt blob at 0x1070000
 1240 04:41:46.015911  Working FDT set to 1070000
 1241 04:41:46.019919     Loading Kernel Image
 1242 04:41:46.171143     Loading Ramdisk to 7e9a6000, end 7ffff12e ... OK
 1243 04:41:46.179531     Loading Device Tree to 000000007e995000, end 000000007e9a55ae ... OK
 1244 04:41:46.180064  Working FDT set to 7e995000
 1245 04:41:46.180493  
 1246 04:41:46.181385  end: 2.4.3 bootloader-commands (duration 00:00:47) [common]
 1247 04:41:46.181978  start: 2.4.4 auto-login-action (timeout 00:03:36) [common]
 1248 04:41:46.182441  Setting prompt string to ['Linux version [0-9]']
 1249 04:41:46.182932  Setting prompt string to ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
 1250 04:41:46.183422  auto-login-action: Wait for prompt ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:05:00)
 1251 04:41:46.184492  Starting kernel ...
 1252 04:41:46.184947  
 1253 04:41:46.219737  [    0.000000] Booting Linux on physical CPU 0x0000000000 [0x410fd034]
 1254 04:41:46.221035  start: 2.4.4.1 login-action (timeout 00:03:36) [common]
 1255 04:41:46.221713  The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
 1256 04:41:46.222320  Setting prompt string to []
 1257 04:41:46.222950  Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
 1258 04:41:46.223541  Using line separator: #'\n'#
 1259 04:41:46.224114  No login prompt set.
 1260 04:41:46.224704  Parsing kernel messages
 1261 04:41:46.225275  ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
 1262 04:41:46.226384  [login-action] Waiting for messages, (timeout 00:03:36)
 1263 04:41:46.226982  Waiting using forced prompt support (timeout 00:01:48)
 1264 04:41:46.236246  [    0.000000] Linux version 6.12.0-rc5 (KernelCI@build-j355503-arm64-gcc-12-defconfig-xflrr) (aarch64-linux-gnu-gcc (Debian 12.2.0-14) 12.2.0, GNU ld (GNU Binutils for Debian) 2.40) #1 SMP PREEMPT Tue Oct 29 02:02:39 UTC 2024
 1265 04:41:46.241795  [    0.000000] KASLR disabled due to lack of seed
 1266 04:41:46.247273  [    0.000000] Machine model: Libre Computer AML-A311D-CC Alta
 1267 04:41:46.252859  [    0.000000] efi: UEFI not found.
 1268 04:41:46.258435  [    0.000000] [Firmware Bug]: Kernel image misaligned at boot, please fix your bootloader!
 1269 04:41:46.263895  [    0.000000] Reserved memory: created CMA memory pool at 0x00000000e4c00000, size 256 MiB
 1270 04:41:46.274891  [    0.000000] OF: reserved mem: initialized node linux,cma, compatible id shared-dma-pool
 1271 04:41:46.285774  [    0.000000] OF: reserved mem: 0x00000000e4c00000..0x00000000f4bfffff (262144 KiB) map reusable linux,cma
 1272 04:41:46.291375  [    0.000000] OF: reserved mem: 0x0000000005000000..0x00000000052fffff (3072 KiB) nomap non-reusable secmon@5000000
 1273 04:41:46.302386  [    0.000000] OF: reserved mem: 0x0000000005300000..0x00000000072fffff (32768 KiB) nomap non-reusable secmon@5300000
 1274 04:41:46.313404  [    0.000000] earlycon: meson0 at MMIO 0x00000000ff803000 (options '115200n8')
 1275 04:41:46.318963  [    0.000000] printk: legacy bootconsole [meson0] enabled
 1276 04:41:46.324494  [    0.000000] NUMA: Faking a node at [mem 0x0000000000000000-0x00000000f4e5afff]
 1277 04:41:46.330012  [    0.000000] NODE_DATA(0) allocated [mem 0xe4666a80-0xe46690bf]
 1278 04:41:46.330488  [    0.000000] Zone ranges:
 1279 04:41:46.335508  [    0.000000]   DMA      [mem 0x0000000000000000-0x00000000f4e5afff]
 1280 04:41:46.341014  [    0.000000]   DMA32    empty
 1281 04:41:46.341484  [    0.000000]   Normal   empty
 1282 04:41:46.346576  [    0.000000] Movable zone start for each node
 1283 04:41:46.352087  [    0.000000] Early memory node ranges
 1284 04:41:46.357621  [    0.000000]   node   0: [mem 0x0000000000000000-0x0000000004ffffff]
 1285 04:41:46.363124  [    0.000000]   node   0: [mem 0x0000000005000000-0x00000000072fffff]
 1286 04:41:46.368632  [    0.000000]   node   0: [mem 0x0000000007300000-0x00000000f4e5afff]
 1287 04:41:46.374135  [    0.000000] Initmem setup node 0 [mem 0x0000000000000000-0x00000000f4e5afff]
 1288 04:41:46.401474  [    0.000000] On node 0, zone DMA: 12709 pages in unavailable ranges
 1289 04:41:46.407038  [    0.000000] psci: probing for conduit method from DT.
 1290 04:41:46.407512  [    0.000000] psci: PSCIv1.0 detected in firmware.
 1291 04:41:46.412538  [    0.000000] psci: Using standard PSCI v0.2 function IDs
 1292 04:41:46.418049  [    0.000000] psci: MIGRATE_INFO_TYPE not supported.
 1293 04:41:46.423578  [    0.000000] psci: SMC Calling Convention v1.1
 1294 04:41:46.429091  [    0.000000] percpu: Embedded 25 pages/cpu s61656 r8192 d32552 u102400
 1295 04:41:46.434647  [    0.000000] Detected VIPT I-cache on CPU0
 1296 04:41:46.440153  [    0.000000] CPU features: detected: ARM erratum 845719
 1297 04:41:46.445672  [    0.000000] alternatives: applying boot alternatives
 1298 04:41:46.462174  [    0.000000] Kernel command line: console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/906892/extract-nfsrootfs-2tz2ri7s,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp
 1299 04:41:46.473229  <6>[    0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
 1300 04:41:46.478782  <6>[    0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes, linear)
 1301 04:41:46.484380  <6>[    0.000000] Fallback order for Node 0: 0 
 1302 04:41:46.489808  <6>[    0.000000] Built 1 zonelists, mobility grouping on.  Total pages: 1003099
 1303 04:41:46.495408  <6>[    0.000000] Policy zone: DMA
 1304 04:41:46.500854  <6>[    0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
 1305 04:41:46.506370  <6>[    0.000000] software IO TLB: SWIOTLB bounce buffer size adjusted to 3MB
 1306 04:41:46.511910  <6>[    0.000000] software IO TLB: area num 8.
 1307 04:41:46.520868  <6>[    0.000000] software IO TLB: mapped [mem 0x00000000dfc00000-0x00000000e0000000] (4MB)
 1308 04:41:46.567508  <6>[    0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=6, Nodes=1
 1309 04:41:46.572978  <6>[    0.000000] rcu: Preemptible hierarchical RCU implementation.
 1310 04:41:46.576528  <6>[    0.000000] rcu: 	RCU event tracing is enabled.
 1311 04:41:46.582027  <6>[    0.000000] rcu: 	RCU restricting CPUs from NR_CPUS=512 to nr_cpu_ids=6.
 1312 04:41:46.587526  <6>[    0.000000] 	Trampoline variant of Tasks RCU enabled.
 1313 04:41:46.593047  <6>[    0.000000] 	Tracing variant of Tasks RCU enabled.
 1314 04:41:46.604101  <6>[    0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
 1315 04:41:46.609631  <6>[    0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=6
 1316 04:41:46.615131  <6>[    0.000000] RCU Tasks: Setting shift to 3 and lim to 1 rcu_task_cb_adjust=1 rcu_task_cpu_ids=6.
 1317 04:41:46.626144  <6>[    0.000000] RCU Tasks Trace: Setting shift to 3 and lim to 1 rcu_task_cb_adjust=1 rcu_task_cpu_ids=6.
 1318 04:41:46.631694  <6>[    0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
 1319 04:41:46.637203  <6>[    0.000000] Root IRQ handler: gic_handle_irq
 1320 04:41:46.642708  <6>[    0.000000] GIC: Using split EOI/Deactivate mode
 1321 04:41:46.649066  <6>[    0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
 1322 04:41:46.661751  <6>[    0.000000] arch_timer: cp15 timer(s) running at 24.00MHz (phys).
 1323 04:41:46.672776  <6>[    0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x588fe9dc0, max_idle_ns: 440795202592 ns
 1324 04:41:46.678378  <6>[    0.000001] sched_clock: 56 bits at 24MHz, resolution 41ns, wraps every 4398046511097ns
 1325 04:41:46.683805  <6>[    0.008799] Console: colour dummy device 80x25
 1326 04:41:46.694843  <6>[    0.012942] Calibrating delay loop (skipped), value calculated using timer frequency.. 48.00 BogoMIPS (lpj=96000)
 1327 04:41:46.700386  <6>[    0.023294] pid_max: default: 32768 minimum: 301
 1328 04:41:46.705860  <6>[    0.028190] LSM: initializing lsm=capability
 1329 04:41:46.711375  <6>[    0.032731] Mount-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
 1330 04:41:46.716929  <6>[    0.040211] Mountpoint-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
 1331 04:41:46.722445  <6>[    0.050774] rcu: Hierarchical SRCU implementation.
 1332 04:41:46.727958  <6>[    0.053267] rcu: 	Max phase no-delay instances is 1000.
 1333 04:41:46.739037  <6>[    0.058871] Timer migration: 1 hierarchy levels; 8 children per group; 1 crossnode level
 1334 04:41:46.747485  <6>[    0.071617] EFI services will not be available.
 1335 04:41:46.748170  <6>[    0.075265] smp: Bringing up secondary CPUs ...
 1336 04:41:46.767763  <6>[    0.077132] Detected VIPT I-cache on CPU1
 1337 04:41:46.773241  <6>[    0.077252] CPU1: Booted secondary processor 0x0000000001 [0x410fd034]
 1338 04:41:46.778729  <6>[    0.078594] CPU features: detected: Spectre-v2
 1339 04:41:46.787806  <6>[    0.078608] CPU features: detected: Spectre-v4
 1340 04:41:46.788382  <6>[    0.078613] CPU features: detected: Spectre-BHB
 1341 04:41:46.793342  <6>[    0.078619] CPU features: detected: ARM erratum 858921
 1342 04:41:46.798844  <6>[    0.078626] Detected VIPT I-cache on CPU2
 1343 04:41:46.804419  <6>[    0.078697] arch_timer: Enabling local workaround for ARM erratum 858921
 1344 04:41:46.809931  <6>[    0.078714] arch_timer: CPU2: Trapping CNTVCT access
 1345 04:41:46.820988  <6>[    0.078724] CPU2: Booted secondary processor 0x0000000100 [0x410fd092]
 1346 04:41:46.821611  <6>[    0.083691] Detected VIPT I-cache on CPU3
 1347 04:41:46.831951  <6>[    0.083736] arch_timer: Enabling local workaround for ARM erratum 858921
 1348 04:41:46.832535  <6>[    0.083746] arch_timer: CPU3: Trapping CNTVCT access
 1349 04:41:46.842997  <6>[    0.083753] CPU3: Booted secondary processor 0x0000000101 [0x410fd092]
 1350 04:41:46.843519  <6>[    0.095587] Detected VIPT I-cache on CPU4
 1351 04:41:46.854041  <6>[    0.095634] arch_timer: Enabling local workaround for ARM erratum 858921
 1352 04:41:46.859562  <6>[    0.095643] arch_timer: CPU4: Trapping CNTVCT access
 1353 04:41:46.865098  <6>[    0.095650] CPU4: Booted secondary processor 0x0000000102 [0x410fd092]
 1354 04:41:46.870581  <6>[    0.099670] Detected VIPT I-cache on CPU5
 1355 04:41:46.876123  <6>[    0.099718] arch_timer: Enabling local workaround for ARM erratum 858921
 1356 04:41:46.881687  <6>[    0.099728] arch_timer: CPU5: Trapping CNTVCT access
 1357 04:41:46.887164  <6>[    0.099735] CPU5: Booted secondary processor 0x0000000103 [0x410fd092]
 1358 04:41:46.892699  <6>[    0.099848] smp: Brought up 1 node, 6 CPUs
 1359 04:41:46.898289  <6>[    0.221083] SMP: Total of 6 processors activated.
 1360 04:41:46.898887  <6>[    0.225984] CPU: All CPU(s) started at EL2
 1361 04:41:46.903761  <6>[    0.230329] CPU features: detected: 32-bit EL0 Support
 1362 04:41:46.909295  <6>[    0.235643] CPU features: detected: 32-bit EL1 Support
 1363 04:41:46.914810  <6>[    0.241004] CPU features: detected: CRC32 instructions
 1364 04:41:46.920364  <6>[    0.246395] alternatives: applying system-wide alternatives
 1365 04:41:46.936837  <6>[    0.253692] Memory: 3557432K/4012396K available (17280K kernel code, 4898K rwdata, 11876K rodata, 10432K init, 742K bss, 187800K reserved, 262144K cma-reserved)
 1366 04:41:46.943727  <6>[    0.267928] devtmpfs: initialized
 1367 04:41:46.954779  <6>[    0.277062] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
 1368 04:41:46.960330  <6>[    0.281416] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
 1369 04:41:46.965791  <6>[    0.292204] 21392 pages in range for non-PLT usage
 1370 04:41:46.971412  <6>[    0.292216] 512912 pages in range for PLT usage
 1371 04:41:46.976852  <6>[    0.293774] pinctrl core: initialized pinctrl subsystem
 1372 04:41:46.977473  <6>[    0.305852] DMI not present or invalid.
 1373 04:41:46.982410  <6>[    0.310152] NET: Registered PF_NETLINK/PF_ROUTE protocol family
 1374 04:41:46.993449  <6>[    0.314890] DMA: preallocated 512 KiB GFP_KERNEL pool for atomic allocations
 1375 04:41:46.998938  <6>[    0.321670] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
 1376 04:41:47.009950  <6>[    0.329768] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
 1377 04:41:47.015494  <6>[    0.337247] audit: initializing netlink subsys (disabled)
 1378 04:41:47.020986  <5>[    0.342984] audit: type=2000 audit(0.264:1): state=initialized audit_enabled=0 res=1
 1379 04:41:47.026510  <6>[    0.344397] thermal_sys: Registered thermal governor 'step_wise'
 1380 04:41:47.032066  <6>[    0.350754] thermal_sys: Registered thermal governor 'power_allocator'
 1381 04:41:47.038035  <6>[    0.357014] cpuidle: using governor menu
 1382 04:41:47.043183  <6>[    0.368058] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
 1383 04:41:47.048785  <6>[    0.374934] ASID allocator initialised with 65536 entries
 1384 04:41:47.056985  <6>[    0.382435] Serial: AMBA PL011 UART driver
 1385 04:41:47.066667  <6>[    0.392998] platform ff600000.hdmi-tx: Fixed dependency cycle(s) with /soc/vpu@ff900000
 1386 04:41:47.081936  <6>[    0.408365] platform ff600000.hdmi-tx: Fixed dependency cycle(s) with /soc/vpu@ff900000
 1387 04:41:47.090909  <6>[    0.411028] platform ff900000.vpu: Fixed dependency cycle(s) with /soc/bus@ff600000/hdmi-tx@0
 1388 04:41:47.096554  <6>[    0.424143] platform ff900000.vpu: Fixed dependency cycle(s) with /cvbs-connector
 1389 04:41:47.107548  <6>[    0.427412] platform cvbs-connector: Fixed dependency cycle(s) with /soc/vpu@ff900000
 1390 04:41:47.113039  <6>[    0.435828] platform ff600000.hdmi-tx: Fixed dependency cycle(s) with /hdmi-connector
 1391 04:41:47.124094  <6>[    0.443456] platform hdmi-connector: Fixed dependency cycle(s) with /soc/bus@ff600000/hdmi-tx@0
 1392 04:41:47.129584  <6>[    0.457037] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
 1393 04:41:47.135146  <6>[    0.459279] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
 1394 04:41:47.146206  <6>[    0.465759] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
 1395 04:41:47.151654  <6>[    0.472738] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
 1396 04:41:47.157380  <6>[    0.479206] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
 1397 04:41:47.162756  <6>[    0.486190] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
 1398 04:41:47.168264  <6>[    0.492661] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
 1399 04:41:47.179318  <6>[    0.499646] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
 1400 04:41:47.180079  <6>[    0.507660] ACPI: Interpreter disabled.
 1401 04:41:47.184782  <6>[    0.513168] iommu: Default domain type: Translated
 1402 04:41:47.190277  <6>[    0.515179] iommu: DMA domain TLB invalidation policy: strict mode
 1403 04:41:47.195808  <5>[    0.521867] SCSI subsystem initialized
 1404 04:41:47.201460  <6>[    0.529729] usbcore: registered new interface driver usbfs
 1405 04:41:47.206791  <6>[    0.531230] usbcore: registered new interface driver hub
 1406 04:41:47.212358  <6>[    0.536764] usbcore: registered new device driver usb
 1407 04:41:47.217916  <6>[    0.543026] pps_core: LinuxPPS API ver. 1 registered
 1408 04:41:47.229010  <6>[    0.547173] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
 1409 04:41:47.229585  <6>[    0.556492] PTP clock support registered
 1410 04:41:47.234542  <6>[    0.560732] EDAC MC: Ver: 3.0.0
 1411 04:41:47.239917  <6>[    0.564382] scmi_core: SCMI protocol bus registered
 1412 04:41:47.245435  <6>[    0.569999] FPGA manager framework
 1413 04:41:47.250899  <6>[    0.572757] Advanced Linux Sound Architecture Driver Initialized.
 1414 04:41:47.251438  <6>[    0.579732] vgaarb: loaded
 1415 04:41:47.256491  <6>[    0.582237] clocksource: Switched to clocksource arch_sys_counter
 1416 04:41:47.262034  <5>[    0.588400] VFS: Disk quotas dquot_6.6.0
 1417 04:41:47.267567  <6>[    0.592386] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
 1418 04:41:47.273067  <6>[    0.599770] pnp: PnP ACPI: disabled
 1419 04:41:47.278549  <6>[    0.608074] NET: Registered PF_INET protocol family
 1420 04:41:47.284157  <6>[    0.608420] IP idents hash table entries: 65536 (order: 7, 524288 bytes, linear)
 1421 04:41:47.295184  <6>[    0.618579] tcp_listen_portaddr_hash hash table entries: 2048 (order: 3, 32768 bytes, linear)
 1422 04:41:47.300664  <6>[    0.624593] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
 1423 04:41:47.311751  <6>[    0.632485] TCP established hash table entries: 32768 (order: 6, 262144 bytes, linear)
 1424 04:41:47.317252  <6>[    0.640724] TCP bind hash table entries: 32768 (order: 8, 1048576 bytes, linear)
 1425 04:41:47.328465  <6>[    0.648513] TCP: Hash tables configured (established 32768 bind 32768)
 1426 04:41:47.333775  <6>[    0.654994] UDP hash table entries: 2048 (order: 4, 65536 bytes, linear)
 1427 04:41:47.339385  <6>[    0.661842] UDP-Lite hash table entries: 2048 (order: 4, 65536 bytes, linear)
 1428 04:41:47.344756  <6>[    0.669269] NET: Registered PF_UNIX/PF_LOCAL protocol family
 1429 04:41:47.350336  <6>[    0.675364] RPC: Registered named UNIX socket transport module.
 1430 04:41:47.355924  <6>[    0.681128] RPC: Registered udp transport module.
 1431 04:41:47.361432  <6>[    0.686036] RPC: Registered tcp transport module.
 1432 04:41:47.366871  <6>[    0.690950] RPC: Registered tcp-with-tls transport module.
 1433 04:41:47.372399  <6>[    0.696643] RPC: Registered tcp NFSv4.1 backchannel transport module.
 1434 04:41:47.377933  <6>[    0.703291] PCI: CLS 0 bytes, default 64
 1435 04:41:47.383676  <6>[    0.707611] Unpacking initramfs...
 1436 04:41:47.389267  <6>[    0.716891] kvm [1]: nv: 554 coarse grained trap handlers
 1437 04:41:47.394778  <6>[    0.717191] kvm [1]: IPA Size Limit: 40 bits
 1438 04:41:47.395372  <6>[    0.722866] kvm [1]: vgic interrupt IRQ9
 1439 04:41:47.400287  <6>[    0.725566] kvm [1]: Hyp nVHE mode initialized successfully
 1440 04:41:47.405771  <5>[    0.732746] Initialise system trusted keyrings
 1441 04:41:47.411460  <6>[    0.736195] workingset: timestamp_bits=42 max_order=20 bucket_order=0
 1442 04:41:47.416917  <6>[    0.742932] squashfs: version 4.0 (2009/01/31) Phillip Lougher
 1443 04:41:47.422462  <5>[    0.748940] NFS: Registering the id_resolver key type
 1444 04:41:47.428179  <5>[    0.753964] Key type id_resolver registered
 1445 04:41:47.433477  <5>[    0.758323] Key type id_legacy registered
 1446 04:41:47.438971  <6>[    0.762582] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
 1447 04:41:47.450014  <6>[    0.769449] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
 1448 04:41:47.453826  <6>[    0.777204] 9p: Installing v9fs 9p2000 file system support
 1449 04:41:47.500151  <5>[    0.823349] Key type asymmetric registered
 1450 04:41:47.500818  <5>[    0.823392] Asymmetric key parser 'x509' registered
 1451 04:41:47.507299  <6>[    0.827249] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 245)
 1452 04:41:47.512964  <6>[    0.834774] io scheduler mq-deadline registered
 1453 04:41:47.513593  <6>[    0.839511] io scheduler kyber registered
 1454 04:41:47.518454  <6>[    0.843779] io scheduler bfq registered
 1455 04:41:47.525474  <6>[    0.849669] irq_meson_gpio: 100 to 8 gpio interrupt mux initialized
 1456 04:41:47.541704  <6>[    0.869951] ledtrig-cpu: registered to indicate activity on CPUs
 1457 04:41:47.574504  <6>[    0.901443] soc soc0: Amlogic Meson G12B (A311D) Revision 29:b (10:2) Detected
 1458 04:41:47.594183  <6>[    0.914961] Serial: 8250/16550 driver, 4 port�<6>[    0.919519] ff803000.serial: ttyAML0 at MMIO 0xff803000 (irq = 14, base_baud = 1500000) is a meson_uart
 1459 04:41:47.597586  <6>[    0.929149] printk: legacy console [ttyAML0] enabled
 1460 04:41:47.603037  <6>[    0.929149] printk: legacy console [ttyAML0] enabled
 1461 04:41:47.608606  <6>[    0.933948] printk: legacy bootconsole [meson0] disabled
 1462 04:41:47.614143  <6>[    0.933948] printk: legacy bootconsole [meson0] disabled
 1463 04:41:47.619675  <6>[    0.947035] msm_serial: driver initialized
 1464 04:41:47.625253  <6>[    0.949879] SuperH (H)SCI(F) driver initialized
 1465 04:41:47.630818  <6>[    0.954443] STM32 USART driver initialized
 1466 04:41:47.631345  <5>[    0.960588] random: crng init done
 1467 04:41:47.636359  <6>[    0.966188] loop: module loaded
 1468 04:41:47.643422  <6>[    0.967487] megasas: 07.727.03.00-rc1
 1469 04:41:47.648942  <6>[    0.976508] tun: Universal TUN/TAP device driver, 1.6
 1470 04:41:47.649504  <6>[    0.977714] thunder_xcv, ver 1.0
 1471 04:41:47.654481  <6>[    0.979687] thunder_bgx, ver 1.0
 1472 04:41:47.655018  <6>[    0.983140] nicpf, ver 1.0
 1473 04:41:47.665634  <6>[    0.987735] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
 1474 04:41:47.671144  <6>[    0.993530] hns3: Copyright (c) 2017 Huawei Corporation.
 1475 04:41:47.671723  <6>[    0.999113] hclge is initializing
 1476 04:41:47.676666  <6>[    1.002654] e1000: Intel(R) PRO/1000 Network Driver
 1477 04:41:47.682334  <6>[    1.007736] e1000: Copyright (c) 1999-2006 Intel Corporation.
 1478 04:41:47.687951  <6>[    1.013763] e1000e: Intel(R) PRO/1000 Network Driver
 1479 04:41:47.693350  <6>[    1.018915] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
 1480 04:41:47.698839  <6>[    1.025102] igb: Intel(R) Gigabit Ethernet Network Driver
 1481 04:41:47.709953  <6>[    1.030702] igb: Copyright (c) 2007-2014 Intel Corporation.
 1482 04:41:47.715523  <6>[    1.036535] igbvf: Intel(R) Gigabit Virtual Function Network Driver
 1483 04:41:47.721052  <6>[    1.043009] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
 1484 04:41:47.726697  <6>[    1.049774] sky2: driver version 1.30
 1485 04:41:47.727298  <6>[    1.054930] VFIO - User Level meta-driver version: 0.3
 1486 04:41:47.740307  <6>[    1.062374] usbcore: registered new interface driver usb-storage
 1487 04:41:47.740901  <6>[    1.068642] i2c_dev: i2c /dev entries driver
 1488 04:41:47.753158  <6>[    1.079581] sdhci: Secure Digital Host Controller Interface driver
 1489 04:41:47.753793  <6>[    1.080382] sdhci: Copyright(c) Pierre Ossman
 1490 04:41:47.764302  <6>[    1.086096] Synopsys Designware Multimedia Card Interface Driver
 1491 04:41:47.769878  <6>[    1.092644] sdhci-pltfm: SDHCI platform and OF driver helper
 1492 04:41:47.770469  <6>[    1.100299] meson-sm: secure-monitor enabled
 1493 04:41:47.782725  <6>[    1.102872] usbcore: registered new interface driver usbhid
 1494 04:41:47.783343  <6>[    1.107444] usbhid: USB HID core driver
 1495 04:41:47.790213  <6>[    1.122174] NET: Registered PF_PACKET protocol family
 1496 04:41:47.795758  <6>[    1.122299] 9pnet: Installing 9P2000 support
 1497 04:41:47.802789  <5>[    1.126431] Key type dns_resolver registered
 1498 04:41:47.808316  <6>[    1.137957] registered taskstats version 1
 1499 04:41:47.813854  <5>[    1.138111] Loading compiled-in X.509 certificates
 1500 04:41:47.817505  <6>[    1.146760] Demotion targets for Node 0: null
 1501 04:41:47.857974  <6>[    1.189859] dwc3-meson-g12a ffe09000.usb: USB2 ports: 2
 1502 04:41:47.863424  <6>[    1.189904] dwc3-meson-g12a ffe09000.usb: USB3 ports: 1
 1503 04:41:47.874531  <4>[    1.200101] dwc2 ff400000.usb: supply vusb_d not found, using dummy regulator
 1504 04:41:47.880068  <4>[    1.202673] dwc2 ff400000.usb: supply vusb_a not found, using dummy regulator
 1505 04:41:47.885608  <6>[    1.210201] dwc2 ff400000.usb: EPs: 7, dedicated fifos, 712 entries in SPRAM
 1506 04:41:47.891192  <6>[    1.219536] xhci-hcd xhci-hcd.0.auto: xHCI Host Controller
 1507 04:41:47.902161  <6>[    1.222945] xhci-hcd xhci-hcd.0.auto: new USB bus registered, assigned bus number 1
 1508 04:41:47.913353  <6>[    1.230924] xhci-hcd xhci-hcd.0.auto: hcc params 0x0228fe6c hci version 0x110 quirks 0x0000808000000010
 1509 04:41:47.918945  <6>[    1.240465] xhci-hcd xhci-hcd.0.auto: irq 16, io mem 0xff500000
 1510 04:41:47.924431  <6>[    1.246688] xhci-hcd xhci-hcd.0.auto: xHCI Host Controller
 1511 04:41:47.929995  <6>[    1.252305] xhci-hcd xhci-hcd.0.auto: new USB bus registered, assigned bus number 2
 1512 04:41:47.935557  <6>[    1.260194] xhci-hcd xhci-hcd.0.auto: Host supports USB 3.0 SuperSpeed
 1513 04:41:47.941057  <6>[    1.267452] hub 1-0:1.0: USB hub found
 1514 04:41:47.946630  <6>[    1.270959] hub 1-0:1.0: 2 ports detected
 1515 04:41:47.952235  <6>[    1.277065] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
 1516 04:41:47.957746  <6>[    1.283935] hub 2-0:1.0: USB hub found
 1517 04:41:47.962798  <6>[    1.287514] hub 2-0:1.0: 1 port detected
 1518 04:41:47.990487  <6>[    1.318365] meson-gx-mmc ffe05000.mmc: Got CD GPIO
 1519 04:41:47.999786  <6>[    1.328543] meson-gx-mmc ffe07000.mmc: allocated mmc-pwrseq
 1520 04:41:48.033422  <6>[    1.361732] Trying to probe devices needed for running init ...
 1521 04:41:48.194595  <6>[    1.522274] usb 1-1: new high-speed USB device number 2 using xhci-hcd
 1522 04:41:48.343192  <6>[    1.669593] mmc0: new ultra high speed SDR104 SDXC card at address e624
 1523 04:41:48.348660  <6>[    1.671847] mmcblk0: mmc0:e624 SD64G 59.5 GiB
 1524 04:41:48.349207  <6>[    1.676753] Freeing initrd memory: 22884K
 1525 04:41:48.352626  <6>[    1.678109]  mmcblk0: p1
 1526 04:41:48.383351  <6>[    1.715289] hub 1-1:1.0: USB hub found
 1527 04:41:48.389067  <6>[    1.715609] hub 1-1:1.0: 4 ports detected
 1528 04:41:48.450593  <6>[    1.778381] usb 2-1: new SuperSpeed USB device number 2 using xhci-hcd
 1529 04:41:48.496062  <6>[    1.827955] hub 2-1:1.0: USB hub found
 1530 04:41:48.501740  <6>[    1.828775] hub 2-1:1.0: 4 ports detected
 1531 04:42:00.314455  <6>[   13.646298] clk: Disabling unused clocks
 1532 04:42:00.319853  <6>[   13.646469] PM: genpd: Disabling unused power domains
 1533 04:42:00.327151  <6>[   13.650157] ALSA device list:
 1534 04:42:00.327604  <6>[   13.653362]   No soundcards found.
 1535 04:42:00.333305  <6>[   13.665238] Freeing unused kernel memory: 10432K
 1536 04:42:00.338738  <6>[   13.665339] Run /init as init process
 1537 04:42:00.345288  Loading, please wait...
 1538 04:42:00.382771  Starting systemd-udevd version 252.22-1~deb12u1
 1539 04:42:00.830196  <4>[   14.156498] meson-pwm ff802000.pwm: using obsolete compatible, please consider updating dt
 1540 04:42:00.839221  <6>[   14.162704] mc: Linux media interface: v0.10
 1541 04:42:00.843794  <6>[   14.172168] videodev: Linux video capture interface: v2.00
 1542 04:42:00.849389  <6>[   14.172573] meson8b-dwmac ff3f0000.ethernet: IRQ eth_wake_irq not found
 1543 04:42:00.854886  <6>[   14.179208] meson8b-dwmac ff3f0000.ethernet: IRQ eth_lpi not found
 1544 04:42:00.860502  <6>[   14.184089] meson-vrtc ff8000a8.rtc: registered as rtc0
 1545 04:42:00.866021  <6>[   14.185571] meson8b-dwmac ff3f0000.ethernet: IRQ sfty not found
 1546 04:42:00.877148  <6>[   14.191068] meson-vrtc ff8000a8.rtc: setting system clock to 1970-01-01T00:00:14 UTC (14)
 1547 04:42:00.882630  <6>[   14.197262] meson8b-dwmac ff3f0000.ethernet: PTP uses main clock
 1548 04:42:00.888150  <6>[   14.212479] meson8b-dwmac ff3f0000.ethernet: User ID: 0x11, Synopsys ID: 0x37
 1549 04:42:00.893675  <6>[   14.213339] panfrost ffe40000.gpu: clock rate = 24000000
 1550 04:42:00.899346  <6>[   14.219204] meson8b-dwmac ff3f0000.ethernet: 	DWMAC1000
 1551 04:42:00.910531  <6>[   14.219216] meson8b-dwmac ff3f0000.ethernet: DMA HW capability register supported
 1552 04:42:00.916050  <6>[   14.219221] meson8b-dwmac ff3f0000.ethernet: RX Checksum Offload Engine supported
 1553 04:42:00.926936  <3>[   14.224853] panfrost ffe40000.gpu: error -ENODEV: _opp_set_regulators: no regulator (mali) found
 1554 04:42:00.932454  <6>[   14.230189] meson8b-dwmac ff3f0000.ethernet: COE Type 2
 1555 04:42:00.938080  <6>[   14.230198] meson8b-dwmac ff3f0000.ethernet: TX Checksum insertion supported
 1556 04:42:00.943648  <6>[   14.230202] meson8b-dwmac ff3f0000.ethernet: Wake-Up On Lan supported
 1557 04:42:00.949137  <6>[   14.230296] meson8b-dwmac ff3f0000.ethernet: Normal descriptors
 1558 04:42:00.960263  <6>[   14.231398] cpufreq: cpufreq_online: CPU2: Running at unlisted initial frequency: 999999 KHz, changing to: 1000000 KHz
 1559 04:42:00.971385  <6>[   14.240491] panfrost ffe40000.gpu: mali-g52 id 0x7212 major 0x0 minor 0x0 status 0x0
 1560 04:42:00.976899  <6>[   14.245615] meson8b-dwmac ff3f0000.ethernet: Ring mode enabled
 1561 04:42:00.982344  <6>[   14.245628] meson8b-dwmac ff3f0000.ethernet: Enable RX Mitigation via HW Watchdog Timer
 1562 04:42:00.987885  <6>[   14.264654] meson-drm ff900000.vpu: Queued 2 outputs on vpu
 1563 04:42:00.999055  <6>[   14.267386] panfrost ffe40000.gpu: features: 00000000,00000cf7, issues: 00000000,00000400
 1564 04:42:01.010186  <4>[   14.267548] meson_vdec: module is from the staging directory, the quality is unknown, you have been warned.
 1565 04:42:01.015677  <3>[   14.274194] debugfs: Directory 'ff800280.cec' with parent 'regmap' already present!
 1566 04:42:01.026691  <6>[   14.280210] panfrost ffe40000.gpu: Features: L2:0x07110206 Shader:0x00000000 Tiler:0x00000809 Mem:0x1 MMU:0x00002830 AS:0xff JS:0x7
 1567 04:42:01.032343  <6>[   14.357538] panfrost ffe40000.gpu: shader_present=0x3 l2_present=0x1
 1568 04:42:01.037919  <6>[   14.364858] Registered IR keymap rc-empty
 1569 04:42:01.048975  <6>[   14.370810] rc rc0: meson-ir as /devices/platform/soc/ff800000.bus/ff808000.ir/rc/rc0
 1570 04:42:01.054543  <6>[   14.378529] input: meson-ir as /devices/platform/soc/ff800000.bus/ff808000.ir/rc/rc0/input0
 1571 04:42:01.060138  <6>[   14.378561] [drm] Initialized panfrost 1.2.0 for ffe40000.gpu on minor 0
 1572 04:42:01.071123  <6>[   14.392062] meson-dw-hdmi ff600000.hdmi-tx: Detected HDMI TX controller v2.01a with HDCP (meson_dw_hdmi_phy)
 1573 04:42:01.076671  <6>[   14.402099] rc rc0: sw decoder init
 1574 04:42:01.082251  <6>[   14.405751] meson-ir ff808000.ir: receiver initialized
 1575 04:42:01.090123  <6>[   14.408017] meson-dw-hdmi ff600000.hdmi-tx: registered DesignWare HDMI I2C bus driver
 1576 04:42:01.101356  <6>[   14.427027] meson-drm ff900000.vpu: bound ff600000.hdmi-tx (ops meson_dw_hdmi_ops [meson_dw_hdmi])
 1577 04:42:01.106753  <6>[   14.428773] usbcore: registered new device driver onboard-usb-dev
 1578 04:42:01.112254  <3>[   14.430788] meson-drm ff900000.vpu: DSI transceiver device is disabled
 1579 04:42:01.123368  <6>[   14.444300] [drm] Initialized meson 1.0.0 for ff900000.vpu on minor 1
 1580 04:42:01.128074  <6>[   14.450577] meson8b-dwmac ff3f0000.ethernet end0: renamed from eth0
 1581 04:42:01.310435  <6>[   14.619023] Console: switching to colour frame buffer device 128x48
 1582 04:42:01.316320  <6>[   14.637912] meson-drm ff900000.vpu: [drm] fb0: mesondrmfb frame buffer device
 1583 04:42:01.535188  <6>[   14.867268] hub 1-1:1.0: USB hub found
 1584 04:42:01.540620  <6>[   14.867566] hub 1-1:1.0: 4 ports detected
 1585 04:42:01.547074  <6>[   14.872274] onboard-usb-dev 1-1: USB disconnect, device number 2
 1586 04:42:01.678890  Begin: Loading essential drivers ... done.
 1587 04:42:01.684393  Begin: Running /scripts/init-premount ... done.
 1588 04:42:01.689932  Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
 1589 04:42:01.703697  Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
 1590 04:42:01.704191  Device /sys/class/net/end0 found
 1591 04:42:01.704505  done.
 1592 04:42:01.719313  Begin: Waiting up to 180 secs for any network device to become available ... done.
 1593 04:42:01.787676  IP-Config: end0 hardware address de:ca:d3:e3:c6:63 mtu 1500 DHCP
 1594 04:42:01.793321  <6>[   15.117710] meson8b-dwmac ff3f0000.ethernet end0: Register MEM_TYPE_PAGE_POOL RxQ-0
 1595 04:42:01.843538  <6>[   15.171272] usb 2-1: reset SuperSpeed USB device number 2 using xhci-hcd
 1596 04:42:01.866597  <6>[   15.190415] meson8b-dwmac ff3f0000.ethernet end0: PHY [mdio_mux-0.0:00] driver [RTL8211F Gigabit Ethernet] (irq=32)
 1597 04:42:01.879751  <6>[   15.206302] meson8b-dwmac ff3f0000.ethernet end0: No Safety Features support found
 1598 04:42:01.885321  <6>[   15.208514] meson8b-dwmac ff3f0000.ethernet end0: PTP not supported by HW
 1599 04:42:01.894588  <6>[   15.216059] meson8b-dwmac ff3f0000.ethernet end0: configuring for phy/rgmii link mode
 1600 04:42:01.983511  <6>[   15.311335] usb 1-1: new high-speed USB device number 3 using xhci-hcd
 1601 04:42:02.175413  <6>[   15.507421] hub 1-1:1.0: USB hub found
 1602 04:42:02.181078  <6>[   15.507776] hub 1-1:1.0: 4 ports detected
 1603 04:42:02.450191  <4>[   15.782244] rc rc0: two consecutive events of type space
 1604 04:42:03.360891  IP-Config: no response after 2 secs - giving up
 1605 04:42:03.421999  IP-Config: end0 hardware address de:ca:d3:e3:c6:63 mtu 1500 DHCP
 1606 04:42:04.853010  <6>[   18.178987] meson8b-dwmac ff3f0000.ethernet end0: Link is Up - 1Gbps/Full - flow control off
 1607 04:42:05.639100  IP-Config: end0 guessed broadcast address 192.168.6.255
 1608 04:42:05.644541  IP-Config: end0 complete (dhcp from 192.168.6.1):
 1609 04:42:05.650079   address: 192.168.6.27     broadcast: 192.168.6.255    netmask: 255.255.255.0   
 1610 04:42:05.661134   gateway: 192.168.6.1      dns0     : 10.255.253.1     dns1   : 0.0.0.0         
 1611 04:42:05.661627   rootserver: 192.168.6.1 rootpath: 
 1612 04:42:05.664549   filename  : 
 1613 04:42:05.773172  done.
 1614 04:42:05.783564  Begin: Running /scripts/nfs-bottom ... done.
 1615 04:42:05.801613  Begin: Running /scripts/init-bottom ... done.
 1616 04:42:06.144654  <30>[   19.472244] systemd[1]: System time before build time, advancing clock.
 1617 04:42:06.210648  <6>[   19.542596] NET: Registered PF_INET6 protocol family
 1618 04:42:06.216077  <6>[   19.544433] Segment Routing with IPv6
 1619 04:42:06.221380  <6>[   19.546121] In-situ OAM (IOAM) with IPv6
 1620 04:42:06.311031  <30>[   19.615471] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
 1621 04:42:06.316603  <30>[   19.642978] systemd[1]: Detected architecture arm64.
 1622 04:42:06.317099  
 1623 04:42:06.324160  Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
 1624 04:42:06.324641  
 1625 04:42:06.339761  <30>[   19.668012] systemd[1]: Hostname set to <debian-bookworm-arm64>.
 1626 04:42:07.025286  <30>[   20.352252] systemd[1]: Queued start job for default target graphical.target.
 1627 04:42:07.065984  <30>[   20.392611] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
 1628 04:42:07.074695  [[0;32m  OK  [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
 1629 04:42:07.086291  <30>[   20.411231] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
 1630 04:42:07.093188  [[0;32m  OK  [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
 1631 04:42:07.104756  <30>[   20.431313] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
 1632 04:42:07.118175  [[0;32m  OK  [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
 1633 04:42:07.123630  <30>[   20.450993] systemd[1]: Created slice user.slice - User and Session Slice.
 1634 04:42:07.130062  [[0;32m  OK  [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
 1635 04:42:07.141181  <30>[   20.466507] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
 1636 04:42:07.152616  [[0;32m  OK  [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
 1637 04:42:07.163706  <30>[   20.486440] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
 1638 04:42:07.170241  [[0;32m  OK  [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
 1639 04:42:07.192460  <30>[   20.506418] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
 1640 04:42:07.198000  <30>[   20.520482] systemd[1]: Expecting device dev-ttyAML0.device - /dev/ttyAML0...
 1641 04:42:07.205660           Expecting device [0;1;39mdev-ttyAML0.device[0m - /dev/ttyAML0...
 1642 04:42:07.216730  <30>[   20.542339] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
 1643 04:42:07.222955  [[0;32m  OK  [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
 1644 04:42:07.239711  <30>[   20.566348] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
 1645 04:42:07.253445  [[0;32m  OK  [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
 1646 04:42:07.259066  <30>[   20.586392] systemd[1]: Reached target paths.target - Path Units.
 1647 04:42:07.267468  [[0;32m  OK  [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
 1648 04:42:07.272980  <30>[   20.602338] systemd[1]: Reached target remote-fs.target - Remote File Systems.
 1649 04:42:07.284754  [[0;32m  OK  [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
 1650 04:42:07.290330  <30>[   20.618332] systemd[1]: Reached target slices.target - Slice Units.
 1651 04:42:07.298440  [[0;32m  OK  [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
 1652 04:42:07.303943  <30>[   20.634348] systemd[1]: Reached target swap.target - Swaps.
 1653 04:42:07.311841  [[0;32m  OK  [0m] Reached target [0;1;39mswap.target[0m - Swaps.
 1654 04:42:07.323838  <30>[   20.650367] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
 1655 04:42:07.332689  [[0;32m  OK  [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
 1656 04:42:07.348011  <30>[   20.674530] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
 1657 04:42:07.357181  [[0;32m  OK  [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
 1658 04:42:07.369653  <30>[   20.696240] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
 1659 04:42:07.378460  [[0;32m  OK  [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
 1660 04:42:07.392610  <30>[   20.719191] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
 1661 04:42:07.401611  [[0;32m  OK  [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
 1662 04:42:07.412720  <30>[   20.738675] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
 1663 04:42:07.419440  [[0;32m  OK  [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
 1664 04:42:07.432679  <30>[   20.759253] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
 1665 04:42:07.441814  [[0;32m  OK  [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
 1666 04:42:07.453680  <30>[   20.780225] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
 1667 04:42:07.459228  [[0;32m  OK  [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
 1668 04:42:07.473751  <30>[   20.798573] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
 1669 04:42:07.480474  [[0;32m  OK  [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
 1670 04:42:07.519894  <30>[   20.846435] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
 1671 04:42:07.525711           Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
 1672 04:42:07.542134  <30>[   20.868676] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
 1673 04:42:07.549652           Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
 1674 04:42:07.568858  <30>[   20.895401] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
 1675 04:42:07.576326           Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
 1676 04:42:07.595511  <30>[   20.914972] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
 1677 04:42:07.608504  <30>[   20.931666] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
 1678 04:42:07.613679           Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
 1679 04:42:07.629299  <30>[   20.955870] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
 1680 04:42:07.637348           Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
 1681 04:42:07.658237  <30>[   20.984763] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
 1682 04:42:07.665803           Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
 1683 04:42:07.681416  <30>[   21.007961] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
 1684 04:42:07.686990           Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
 1685 04:42:07.697397  <6>[   21.021481] device-mapper: ioctl: 4.48.0-ioctl (2023-03-01) initialised: dm-devel@lists.linux.dev
 1686 04:42:07.717535  <30>[   21.044075] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
 1687 04:42:07.725830           Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
 1688 04:42:07.741290  <30>[   21.067857] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
 1689 04:42:07.748569           Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
 1690 04:42:07.759133  <6>[   21.091254] fuse: init (API version 7.41)
 1691 04:42:07.770244  <30>[   21.092041] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
 1692 04:42:07.774161           Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
 1693 04:42:07.796271  <30>[   21.122742] systemd[1]: Starting systemd-journald.service - Journal Service...
 1694 04:42:07.802605           Starting [0;1;39msystemd-journald.service[0m - Journal Service...
 1695 04:42:07.822684  <30>[   21.149159] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
 1696 04:42:07.830149           Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
 1697 04:42:07.848642  <30>[   21.175175] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
 1698 04:42:07.857983           Starting [0;1;39msystemd-network-g… units from Kernel command line...
 1699 04:42:07.871344  <30>[   21.197886] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
 1700 04:42:07.880145           Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
 1701 04:42:07.895908  <30>[   21.222433] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
 1702 04:42:07.903973           Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
 1703 04:42:07.927161  <30>[   21.253600] systemd[1]: Started systemd-journald.service - Journal Service.
 1704 04:42:07.933909  [[0;32m  OK  [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
 1705 04:42:07.951691  [[0;32m  OK  [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
 1706 04:42:07.964985  [[0;32m  OK  [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
 1707 04:42:07.977023  [[0;32m  OK  [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
 1708 04:42:07.993573  [[0;32m  OK  [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
 1709 04:42:08.006711  [[0;32m  OK  [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
 1710 04:42:08.020613  [[0;32m  OK  [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
 1711 04:42:08.027724  [[0;32m  OK  [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
 1712 04:42:08.041248  [[0;32m  OK  [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
 1713 04:42:08.052811  [[0;32m  OK  [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
 1714 04:42:08.072979  [[0;32m  OK  [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
 1715 04:42:08.084805  [[0;32m  OK  [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
 1716 04:42:08.100800  [[0;32m  OK  [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
 1717 04:42:08.116809  [[0;32m  OK  [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
 1718 04:42:08.133203  [[0;32m  OK  [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
 1719 04:42:08.168096           Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
 1720 04:42:08.181057           Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
 1721 04:42:08.198052           Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
 1722 04:42:08.209622           Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
 1723 04:42:08.224309           Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
 1724 04:42:08.237327  <46>[   21.563865] systemd-journald[231]: Received client request to flush runtime journal.
 1725 04:42:08.244194           Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
 1726 04:42:08.264423  [[0;32m  OK  [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
 1727 04:42:08.271798  [[0;32m  OK  [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
 1728 04:42:08.292501  [[0;32m  OK  [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
 1729 04:42:08.304635  [[0;32m  OK  [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
 1730 04:42:08.354858  [[0;32m  OK  [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
 1731 04:42:08.368657  [[0;32m  OK  [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
 1732 04:42:08.419641           Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
 1733 04:42:08.513755  [[0;32m  OK  [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
 1734 04:42:08.529359  [[0;32m  OK  [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
 1735 04:42:08.544519  [[0;32m  OK  [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
 1736 04:42:08.559486  [[0;32m  OK  [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
 1737 04:42:08.607560           Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
 1738 04:42:08.618078           Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
 1739 04:42:08.804332  [[0;32m  OK  [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
 1740 04:42:08.857259           Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
 1741 04:42:08.882385  [[0;32m  OK  [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
 1742 04:42:08.906327  [[0;32m  OK  [0m] Found device [0;1;39mdev-ttyAML0.device[0m - /dev/ttyAML0.
 1743 04:42:08.980366           Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
 1744 04:42:08.998454           Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
 1745 04:42:09.015548  <5>[   22.342099] cfg80211: Loading compiled-in X.509 certificates for regulatory database
 1746 04:42:09.059746  <5>[   22.386294] Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
 1747 04:42:09.065310  <5>[   22.387174] Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
 1748 04:42:09.076459  [[0;32m  <4>[   22.396266] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
 1749 04:42:09.081975  <6>[   22.404857] cfg80211: failed to load regulatory.db
 1750 04:42:09.087208  OK  [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
 1751 04:42:09.141288  [[0;32m  OK  [0m] Reached target [0;1;39musb-gadget.…m - Hardware activated USB gadget.
 1752 04:42:09.156223  [[0;32m  OK  [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
 1753 04:42:09.162847  [[0;32m  OK  [0m] Reached target [0;1;39mnetwork.target[0m - Network.
 1754 04:42:09.199876  [[0;32m  OK  [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
 1755 04:42:09.231685  [[0;32m  OK  [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
 1756 04:42:09.248166  [[0;32m  OK  [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
 1757 04:42:09.264683  <46>[   22.580638] systemd-journald[231]: Oldest entry in /var/log/journal/44a983756b26438995e691b947c527e4/system.journal is older than the configured file retention duration (1month), suggesting rotation.
 1758 04:42:09.281260  <46>[   22.595276] systemd-journald[231]: /var/log/journal/44a983756b26438995e691b947c527e4/system.journal: Journal header limits reached or header out-of-date, rotating.
 1759 04:42:09.331326           Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
 1760 04:42:09.337842           Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
 1761 04:42:09.349313           Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
 1762 04:42:09.414249  [[0;32m  OK  [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
 1763 04:42:09.425533  [[0;32m  OK  [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
 1764 04:42:09.437181  [[0;32m  OK  [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
 1765 04:42:09.448483  [[0;32m  OK  [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
 1766 04:42:09.477617  [[0;32m  OK  [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
 1767 04:42:09.492252  [[0;32m  OK  [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
 1768 04:42:09.499700  [[0;32m  OK  [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
 1769 04:42:09.540980  [[0;32m  OK  [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
 1770 04:42:09.556227  [[0;32m  OK  [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
 1771 04:42:09.564536  [[0;32m  OK  [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
 1772 04:42:09.579057  [[0;32m  OK  [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
 1773 04:42:09.592172  [[0;32m  OK  [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
 1774 04:42:09.598834  [[0;32m  OK  [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
 1775 04:42:09.606445  [[0;32m  OK  [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
 1776 04:42:09.659937           Starting [0;1;39malsa-restore.serv…- Save/Restore Sound Card State...
 1777 04:42:09.672105           Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
 1778 04:42:09.689712           Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
 1779 04:42:09.716361           Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
 1780 04:42:09.739230           Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
 1781 04:42:09.746733  [[0;32m  OK  [0m] Finished [0;1;39malsa-restore.serv…m - Save/Restore Sound Card State.
 1782 04:42:09.752163  [[0;32m  OK  [0m] Reached target [0;1;39msound.target[0m - Sound Card.
 1783 04:42:09.773883  [[0;32m  OK  [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
 1784 04:42:09.784484  [[0;32m  OK  [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
 1785 04:42:09.801180  [[0;32m  OK  [0m] Started [0;1;39mserial-getty@ttyAM…ice[0m - Serial Getty on ttyAML0.
 1786 04:42:09.818162  [[0;32m  OK  [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
 1787 04:42:09.824207  [[0;32m  OK  [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
 1788 04:42:09.845167  [[0;32m  OK  [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
 1789 04:42:09.861400  [[0;32m  OK  [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
 1790 04:42:09.872538  [[0;32m  OK  [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
 1791 04:42:09.887852  [[0;32m  OK  [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
 1792 04:42:09.931797           Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
 1793 04:42:09.990284  [[0;32m  OK  [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
 1794 04:42:10.081281  
 1795 04:42:10.081685  Debian GNU/Linux 12 debian-bookworm-arm64 ttyAML0
 1796 04:42:10.081911  
 1797 04:42:10.087936  debian-bookworm-arm64 login: root (automatic login)
 1798 04:42:10.088253  
 1799 04:42:10.259865  Linux debian-bookworm-arm64 6.12.0-rc5 #1 SMP PREEMPT Tue Oct 29 02:02:39 UTC 2024 aarch64
 1800 04:42:10.260578  
 1801 04:42:10.265406  The programs included with the Debian GNU/Linux system are free software;
 1802 04:42:10.270911  the exact distribution terms for each program are described in the
 1803 04:42:10.276373  individual files in /usr/share/doc/*/copyright.
 1804 04:42:10.276904  
 1805 04:42:10.281903  Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
 1806 04:42:10.285082  permitted by applicable law.
 1807 04:42:11.020662  Matched prompt #10: / #
 1809 04:42:11.022523  Setting prompt string to ['/ #']
 1810 04:42:11.023306  end: 2.4.4.1 login-action (duration 00:00:25) [common]
 1812 04:42:11.024970  end: 2.4.4 auto-login-action (duration 00:00:25) [common]
 1813 04:42:11.026098  start: 2.4.5 expect-shell-connection (timeout 00:03:11) [common]
 1814 04:42:11.026933  Setting prompt string to ['/ #']
 1815 04:42:11.027738  Forcing a shell prompt, looking for ['/ #']
 1817 04:42:11.079594  / # 
 1818 04:42:11.080463  expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
 1819 04:42:11.081029  Waiting using forced prompt support (timeout 00:02:30)
 1820 04:42:11.086335  
 1821 04:42:11.087226  end: 2.4.5 expect-shell-connection (duration 00:00:00) [common]
 1822 04:42:11.087791  start: 2.4.6 export-device-env (timeout 00:03:11) [common]
 1823 04:42:11.088302  Sending with 10 millisecond of delay
 1825 04:42:16.077700  / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/906892/extract-nfsrootfs-2tz2ri7s'
 1826 04:42:16.088395  export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/906892/extract-nfsrootfs-2tz2ri7s'
 1827 04:42:16.088906  Sending with 10 millisecond of delay
 1829 04:42:18.186192  / # export NFS_SERVER_IP='192.168.6.2'
 1830 04:42:18.197173  export NFS_SERVER_IP='192.168.6.2'
 1831 04:42:18.197834  end: 2.4.6 export-device-env (duration 00:00:07) [common]
 1832 04:42:18.198176  end: 2.4 uboot-commands (duration 00:01:56) [common]
 1833 04:42:18.198482  end: 2 uboot-action (duration 00:01:56) [common]
 1834 04:42:18.198786  start: 3 lava-test-retry (timeout 00:06:46) [common]
 1835 04:42:18.199083  start: 3.1 lava-test-shell (timeout 00:06:46) [common]
 1836 04:42:18.199338  Using namespace: common
 1838 04:42:18.300075  / # #
 1839 04:42:18.300718  lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
 1840 04:42:18.306258  #
 1841 04:42:18.306784  Using /lava-906892
 1843 04:42:18.407542  / # export SHELL=/bin/bash
 1844 04:42:18.413933  export SHELL=/bin/bash
 1846 04:42:18.514895  / # . /lava-906892/environment
 1847 04:42:18.519518  . /lava-906892/environment
 1849 04:42:18.624979  / # /lava-906892/bin/lava-test-runner /lava-906892/0
 1850 04:42:18.625483  Test shell timeout: 10s (minimum of the action and connection timeout)
 1851 04:42:18.629717  /lava-906892/bin/lava-test-runner /lava-906892/0
 1852 04:42:18.820877  + export TESTRUN_ID=0_timesync-off
 1853 04:42:18.828772  + TESTRUN_ID=0_timesync-off
 1854 04:42:18.829028  + cd /lava-906892/0/tests/0_timesync-off
 1855 04:42:18.829241  ++ cat uuid
 1856 04:42:18.837997  + UUID=906892_1.6.2.4.1
 1857 04:42:18.838262  + set +x
 1858 04:42:18.846581  <LAVA_SIGNAL_STARTRUN 0_timesync-off 906892_1.6.2.4.1>
 1859 04:42:18.846825  + systemctl stop systemd-timesyncd
 1860 04:42:18.847268  Received signal: <STARTRUN> 0_timesync-off 906892_1.6.2.4.1
 1861 04:42:18.847497  Starting test lava.0_timesync-off (906892_1.6.2.4.1)
 1862 04:42:18.847779  Skipping test definition patterns.
 1863 04:42:18.889542  + set +x
 1864 04:42:18.889884  <LAVA_SIGNAL_ENDRUN 0_timesync-off 906892_1.6.2.4.1>
 1865 04:42:18.890348  Received signal: <ENDRUN> 0_timesync-off 906892_1.6.2.4.1
 1866 04:42:18.890660  Ending use of test pattern.
 1867 04:42:18.890886  Ending test lava.0_timesync-off (906892_1.6.2.4.1), duration 0.04
 1869 04:42:18.973804  + export TESTRUN_ID=1_kselftest-alsa
 1870 04:42:18.982200  + TESTRUN_ID=1_kselftest-alsa
 1871 04:42:18.982464  + cd /lava-906892/0/tests/1_kselftest-alsa
 1872 04:42:18.982678  ++ cat uuid
 1873 04:42:18.990399  + UUID=906892_1.6.2.4.5
 1874 04:42:18.990662  + set +x
 1875 04:42:18.996109  <LAVA_SIGNAL_STARTRUN 1_kselftest-alsa 906892_1.6.2.4.5>
 1876 04:42:18.996382  + cd ./automated/linux/kselftest/
 1877 04:42:18.996827  Received signal: <STARTRUN> 1_kselftest-alsa 906892_1.6.2.4.5
 1878 04:42:18.997056  Starting test lava.1_kselftest-alsa (906892_1.6.2.4.5)
 1879 04:42:18.997315  Skipping test definition patterns.
 1880 04:42:19.024789  + ./kselftest.sh -c alsa -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/next/pending-fixes/v6.12-rc5-243-g2f5e60c44402/arm64/defconfig/gcc-12/kselftest.tar.xz -L '' -S /dev/null -b meson-g12b-a311d-libretech-cc -g next -e '' -p /opt/kselftests/mainline/ -n 1 -i 1 -E ''
 1881 04:42:19.060291  INFO: install_deps skipped
 1882 04:42:19.195134  --2024-10-29 04:42:19--  http://storage.kernelci.org/next/pending-fixes/v6.12-rc5-243-g2f5e60c44402/arm64/defconfig/gcc-12/kselftest.tar.xz
 1883 04:42:19.219751  Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
 1884 04:42:19.364936  Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
 1885 04:42:19.511204  HTTP request sent, awaiting response... 200 OK
 1886 04:42:19.511629  Length: 7114456 (6.8M) [application/octet-stream]
 1887 04:42:19.516590  Saving to: 'kselftest_armhf.tar.gz'
 1888 04:42:19.516915  
 1889 04:42:20.951167  
kselftest_armhf.tar   0%[                    ]       0  --.-KB/s               
kselftest_armhf.tar   0%[                    ]  49.92K   175KB/s               
kselftest_armhf.tar   3%[                    ] 218.67K   383KB/s               
kselftest_armhf.tar  11%[=>                  ] 826.17K   965KB/s               
kselftest_armhf.tar  47%[========>           ]   3.25M  2.84MB/s               
kselftest_armhf.tar  92%[=================>  ]   6.30M  4.41MB/s               
kselftest_armhf.tar 100%[===================>]   6.78M  4.74MB/s    in 1.4s    
 1890 04:42:20.951641  
 1891 04:42:21.038096  2024-10-29 04:42:20 (4.74 MB/s) - 'kselftest_armhf.tar.gz' saved [7114456/7114456]
 1892 04:42:21.038520  
 1893 04:42:29.837861  skiplist:
 1894 04:42:29.838309  ========================================
 1895 04:42:29.843672  ========================================
 1896 04:42:29.895618  alsa:mixer-test
 1897 04:42:29.896341  alsa:pcm-test
 1898 04:42:29.896728  alsa:test-pcmtest-driver
 1899 04:42:29.899771  alsa:utimer-test
 1900 04:42:29.927604  ============== Tests to run ===============
 1901 04:42:29.928315  alsa:mixer-test
 1902 04:42:29.933037  alsa:pcm-test
 1903 04:42:29.933584  alsa:test-pcmtest-driver
 1904 04:42:29.934016  alsa:utimer-test
 1905 04:42:29.939270  ===========End Tests to run ===============
 1906 04:42:29.939808  shardfile-alsa pass
 1907 04:42:30.056415  <12>[   43.386116] kselftest: Running tests in alsa
 1908 04:42:30.063662  TAP version 13
 1909 04:42:30.072087  1..4
 1910 04:42:30.093792  # timeout set to 45
 1911 04:42:30.094343  # selftests: alsa: mixer-test
 1912 04:42:30.246857  # TAP version 13
 1913 04:42:30.247475  # # Card 0/LCALTA - LC-ALTA (LC-ALTA)
 1914 04:42:30.252264  # 1..427
 1915 04:42:30.252785  # ok 1 get_value.LCALTA.60
 1916 04:42:30.253213  # # LCALTA.60 TDMOUT_A SRC SEL
 1917 04:42:30.257859  # ok 2 name.LCALTA.60
 1918 04:42:30.258375  # ok 3 write_default.LCALTA.60
 1919 04:42:30.263470  # ok 4 write_valid.LCALTA.60
 1920 04:42:30.264021  # ok 5 write_invalid.LCALTA.60
 1921 04:42:30.268911  # ok 6 event_missing.LCALTA.60
 1922 04:42:30.269420  # ok 7 event_spurious.LCALTA.60
 1923 04:42:30.274581  # ok 8 get_value.LCALTA.59
 1924 04:42:30.275090  # # LCALTA.59 TDMOUT_B SRC SEL
 1925 04:42:30.280309  # ok 9 name.LCALTA.59
 1926 04:42:30.280849  # ok 10 write_default.LCALTA.59
 1927 04:42:30.285676  # ok 11 write_valid.LCALTA.59
 1928 04:42:30.286187  # ok 12 write_invalid.LCALTA.59
 1929 04:42:30.291313  # ok 13 event_missing.LCALTA.59
 1930 04:42:30.291829  # ok 14 event_spurious.LCALTA.59
 1931 04:42:30.296626  # ok 15 get_value.LCALTA.58
 1932 04:42:30.297159  # # LCALTA.58 TDMOUT_C SRC SEL
 1933 04:42:30.302383  # ok 16 name.LCALTA.58
 1934 04:42:30.302946  # ok 17 write_default.LCALTA.58
 1935 04:42:30.307880  # ok 18 write_valid.LCALTA.58
 1936 04:42:30.308429  # ok 19 write_invalid.LCALTA.58
 1937 04:42:30.313347  # ok 20 event_missing.LCALTA.58
 1938 04:42:30.313867  # ok 21 event_spurious.LCALTA.58
 1939 04:42:30.318826  # ok 22 get_value.LCALTA.57
 1940 04:42:30.319349  # # LCALTA.57 TDMIN_A SRC SEL
 1941 04:42:30.319769  # ok 23 name.LCALTA.57
 1942 04:42:30.324336  # ok 24 write_default.LCALTA.57
 1943 04:42:30.324852  # ok 25 write_valid.LCALTA.57
 1944 04:42:30.329891  # ok 26 write_invalid.LCALTA.57
 1945 04:42:30.330403  # ok 27 event_missing.LCALTA.57
 1946 04:42:30.335544  # ok 28 event_spurious.LCALTA.57
 1947 04:42:30.336110  # ok 29 get_value.LCALTA.56
 1948 04:42:30.340986  # # LCALTA.56 TDMIN_B SRC SEL
 1949 04:42:30.341511  # ok 30 name.LCALTA.56
 1950 04:42:30.346572  # ok 31 write_default.LCALTA.56
 1951 04:42:30.347086  # ok 32 write_valid.LCALTA.56
 1952 04:42:30.352102  # ok 33 write_invalid.LCALTA.56
 1953 04:42:30.363187  # ok 34 event_missi<3>[   43.682517]  fe.dai-link-5: ASoC: no backend DAIs enabled for fe.dai-link-5, possibly missing ALSA mixer-based routing or UCM profile
 1954 04:42:30.363617  ng.LCALTA.56
 1955 04:42:30.368716  # ok 35 event_spurious.LCALTA.56
 1956 04:42:30.369294  # ok 36 get_value.LCALTA.55
 1957 04:42:30.374255  # # LCALTA.55 TDMIN_C SRC SEL
 1958 04:42:30.374803  # ok 37 name.LCALTA.55
 1959 04:42:30.379848  # ok 38 write_default.LCALTA.55
 1960 04:42:30.380449  # ok 39 write_valid.LCALTA.55
 1961 04:42:30.385327  # ok 40 write_invalid.LCALTA.55
 1962 04:42:30.385885  # ok 41 event_missing.LCALTA.55
 1963 04:42:30.390888  # ok 42 event_spurious.LCALTA.55
 1964 04:42:30.391438  # ok 43 get_value.LCALTA.54
 1965 04:42:30.396428  # # LCALTA.54 ACODEC Left DAC Sel
 1966 04:42:30.397008  # ok 44 name.LCALTA.54
 1967 04:42:30.402006  # ok 45 write_default.LCALTA.54
 1968 04:42:30.402581  # ok 46 write_valid.LCALTA.54
 1969 04:42:30.407558  # ok 47 write_invalid.LCALTA.54
 1970 04:42:30.408128  # ok 48 event_missing.LCALTA.54
 1971 04:42:30.413065  # ok 49 event_spurious.LCALTA.54
 1972 04:42:30.413627  # ok 50 get_value.LCALTA.53
 1973 04:42:30.418592  # # LCALTA.53 ACODEC Right DAC Sel
 1974 04:42:30.419182  # ok 51 name.LCALTA.53
 1975 04:42:30.424245  # ok 52 write_default.LCALTA.53
 1976 04:42:30.424811  # ok 53 write_valid.LCALTA.53
 1977 04:42:30.429724  # ok 54 write_invalid.LCALTA.53
 1978 04:42:30.430252  # ok 55 event_missing.LCALTA.53
 1979 04:42:30.435252  # ok 56 event_spurious.LCALTA.53
 1980 04:42:30.435757  # ok 57 get_value.LCALTA.52
 1981 04:42:30.440808  # # LCALTA.52 TOACODEC OUT EN Switch
 1982 04:42:30.441320  # ok 58 name.LCALTA.52
 1983 04:42:30.446401  # ok 59 write_default.LCALTA.52
 1984 04:42:30.446912  # ok 60 write_valid.LCALTA.52
 1985 04:42:30.451882  # ok 61 write_invalid.LCALTA.52
 1986 04:42:30.452418  # ok 62 event_missing.LCALTA.52
 1987 04:42:30.457515  # ok 63 event_spurious.LCALTA.52
 1988 04:42:30.458016  # ok 64 get_value.LCALTA.51
 1989 04:42:30.462972  # # LCALTA.51 TOACODEC SRC
 1990 04:42:30.463482  # ok 65 name.LCALTA.51
 1991 04:42:30.468487  # ok 66 write_default.LCALTA.51
 1992 04:42:30.469005  # ok 67 write_valid.LCALTA.51
 1993 04:42:30.474064  # ok 68 write_invalid.LCALTA.51
 1994 04:42:30.474571  # ok 69 event_missing.LCALTA.51
 1995 04:42:30.479558  # ok 70 event_spurious.LCALTA.51
 1996 04:42:30.480142  # ok 71 get_value.LCALTA.50
 1997 04:42:30.485167  # # LCALTA.50 TOHDMITX SPDIF SRC
 1998 04:42:30.485676  # ok 72 name.LCALTA.50
 1999 04:42:30.486095  # ok 73 write_default.LCALTA.50
 2000 04:42:30.490755  # ok 74 write_valid.LCALTA.50
 2001 04:42:30.491293  # ok 75 write_invalid.LCALTA.50
 2002 04:42:30.496354  # ok 76 event_missing.LCALTA.50
 2003 04:42:30.501867  # ok 77 event_spurious.LCALTA.50
 2004 04:42:30.502465  # ok 78 get_value.LCALTA.49
 2005 04:42:30.502915  # # LCALTA.49 TOHDMITX Switch
 2006 04:42:30.507445  # ok 79 name.LCALTA.49
 2007 04:42:30.508028  # ok 80 write_default.LCALTA.49
 2008 04:42:30.512997  # ok 81 write_valid.LCALTA.49
 2009 04:42:30.513564  # ok 82 write_invalid.LCALTA.49
 2010 04:42:30.518561  # ok 83 event_missing.LCALTA.49
 2011 04:42:30.519111  # ok 84 event_spurious.LCALTA.49
 2012 04:42:30.524082  # ok 85 get_value.LCALTA.48
 2013 04:42:30.524628  # # LCALTA.48 TOHDMITX I2S SRC
 2014 04:42:30.529603  # ok 86 name.LCALTA.48
 2015 04:42:30.530135  # ok 87 write_default.LCALTA.48
 2016 04:42:30.535154  # ok 88 write_valid.LCALTA.48
 2017 04:42:30.535722  # ok 89 write_invalid.LCALTA.48
 2018 04:42:30.540614  # ok 90 event_missing.LCALTA.48
 2019 04:42:30.541202  # ok 91 event_spurious.LCALTA.48
 2020 04:42:30.546219  # ok 92 get_value.LCALTA.47
 2021 04:42:30.546778  # # LCALTA.47 TODDR_C SRC SEL
 2022 04:42:30.551728  # ok 93 name.LCALTA.47
 2023 04:42:30.552287  # ok 94 write_default.LCALTA.47
 2024 04:42:30.557266  # ok 95 write_valid.LCALTA.47
 2025 04:42:30.557794  # ok 96 write_invalid.LCALTA.47
 2026 04:42:30.562815  # ok 97 event_missing.LCALTA.47
 2027 04:42:30.563372  # ok 98 event_spurious.LCALTA.47
 2028 04:42:30.568404  # ok 99 get_value.LCALTA.46
 2029 04:42:30.568946  # # LCALTA.46 TODDR_B SRC SEL
 2030 04:42:30.569376  # ok 100 name.LCALTA.46
 2031 04:42:30.573875  # ok 101 write_default.LCALTA.46
 2032 04:42:30.579513  # ok 102 write_valid.LCALTA.46
 2033 04:42:30.580066  # ok 103 write_invalid.LCALTA.46
 2034 04:42:30.584980  # ok 104 event_missing.LCALTA.46
 2035 04:42:30.585486  # ok 105 event_spurious.LCALTA.46
 2036 04:42:30.590755  # ok 106 get_value.LCALTA.45
 2037 04:42:30.591351  # # LCALTA.45 TODDR_A SRC SEL
 2038 04:42:30.591839  # ok 107 name.LCALTA.45
 2039 04:42:30.596087  # ok 108 write_default.LCALTA.45
 2040 04:42:30.601651  # ok 109 write_valid.LCALTA.45
 2041 04:42:30.602176  # ok 110 write_invalid.LCALTA.45
 2042 04:42:30.607174  # ok 111 event_missing.LCALTA.45
 2043 04:42:30.607744  # ok 112 event_spurious.LCALTA.45
 2044 04:42:30.612704  # ok 113 get_value.LCALTA.44
 2045 04:42:30.613221  # # LCALTA.44 FRDDR_C SINK 3 SEL
 2046 04:42:30.618401  # ok 114 name.LCALTA.44
 2047 04:42:30.618967  # ok 115 write_default.LCALTA.44
 2048 04:42:30.623962  # ok 116 write_valid.LCALTA.44
 2049 04:42:30.624361  # ok 117 write_invalid.LCALTA.44
 2050 04:42:30.629567  # ok 118 event_missing.LCALTA.44
 2051 04:42:30.630131  # ok 119 event_spurious.LCALTA.44
 2052 04:42:30.634954  # ok 120 get_value.LCALTA.43
 2053 04:42:30.635449  # # LCALTA.43 FRDDR_C SINK 2 SEL
 2054 04:42:30.640691  # ok 121 name.LCALTA.43
 2055 04:42:30.641333  # ok 122 write_default.LCALTA.43
 2056 04:42:30.646237  # ok 123 write_valid.LCALTA.43
 2057 04:42:30.646841  # ok 124 write_invalid.LCALTA.43
 2058 04:42:30.651574  # ok 125 event_missing.LCALTA.43
 2059 04:42:30.652019  # ok 126 event_spurious.LCALTA.43
 2060 04:42:30.657090  # ok 127 get_value.LCALTA.42
 2061 04:42:30.657681  # # LCALTA.42 FRDDR_C SINK 1 SEL
 2062 04:42:30.662860  # ok 128 name.LCALTA.42
 2063 04:42:30.663299  # ok 129 write_default.LCALTA.42
 2064 04:42:30.668168  # ok 130 write_valid.LCALTA.42
 2065 04:42:30.668555  # ok 131 write_invalid.LCALTA.42
 2066 04:42:30.674492  # ok 132 event_missing.LCALTA.42
 2067 04:42:30.674820  # ok 133 event_spurious.LCALTA.42
 2068 04:42:30.679191  # ok 134 get_value.LCALTA.41
 2069 04:42:30.679627  # # LCALTA.41 FRDDR_C SRC 3 EN Switch
 2070 04:42:30.685988  # ok 135 name.LCALTA.41
 2071 04:42:30.686423  # ok 136 write_default.LCALTA.41
 2072 04:42:30.690370  # ok 137 write_valid.LCALTA.41
 2073 04:42:30.690760  # ok 138 write_invalid.LCALTA.41
 2074 04:42:30.696003  # ok 139 event_missing.LCALTA.41
 2075 04:42:30.696433  # ok 140 event_spurious.LCALTA.41
 2076 04:42:30.701393  # ok 141 get_value.LCALTA.40
 2077 04:42:30.701800  # # LCALTA.40 FRDDR_C SRC 2 EN Switch
 2078 04:42:30.706986  # ok 142 name.LCALTA.40
 2079 04:42:30.707390  # ok 143 write_default.LCALTA.40
 2080 04:42:30.712444  # ok 144 write_valid.LCALTA.40
 2081 04:42:30.712835  # ok 145 write_invalid.LCALTA.40
 2082 04:42:30.718154  # ok 146 event_missing.LCALTA.40
 2083 04:42:30.718535  # ok 147 event_spurious.LCALTA.40
 2084 04:42:30.723566  # ok 148 get_value.LCALTA.39
 2085 04:42:30.729124  # # LCALTA.39 FRDDR_C SRC 1 EN Switch
 2086 04:42:30.729488  # ok 149 name.LCALTA.39
 2087 04:42:30.729732  # ok 150 write_default.LCALTA.39
 2088 04:42:30.734657  # ok 151 write_valid.LCALTA.39
 2089 04:42:30.735009  # ok 152 write_invalid.LCALTA.39
 2090 04:42:30.740381  # ok 153 event_missing.LCALTA.39
 2091 04:42:30.745765  # ok 154 event_spurious.LCALTA.39
 2092 04:42:30.746148  # ok 155 get_value.LCALTA.38
 2093 04:42:30.751309  # # LCALTA.38 FRDDR_B SINK 3 SEL
 2094 04:42:30.751671  # ok 156 name.LCALTA.38
 2095 04:42:30.751917  # ok 157 write_default.LCALTA.38
 2096 04:42:30.756857  # ok 158 write_valid.LCALTA.38
 2097 04:42:30.757222  # ok 159 write_invalid.LCALTA.38
 2098 04:42:30.762640  # ok 160 event_missing.LCALTA.38
 2099 04:42:30.768082  # ok 161 event_spurious.LCALTA.38
 2100 04:42:30.768659  # ok 162 get_value.LCALTA.37
 2101 04:42:30.773602  # # LCALTA.37 FRDDR_B SINK 2 SEL
 2102 04:42:30.774153  # ok 163 name.LCALTA.37
 2103 04:42:30.774593  # ok 164 write_default.LCALTA.37
 2104 04:42:30.779128  # ok 165 write_valid.LCALTA.37
 2105 04:42:30.784670  # ok 166 write_invalid.LCALTA.37
 2106 04:42:30.785228  # ok 167 event_missing.LCALTA.37
 2107 04:42:30.790248  # ok 168 event_spurious.LCALTA.37
 2108 04:42:30.790694  # ok 169 get_value.LCALTA.36
 2109 04:42:30.795891  # # LCALTA.36 FRDDR_B SINK 1 SEL
 2110 04:42:30.796827  # ok 170 name.LCALTA.36
 2111 04:42:30.801380  # ok 171 write_default.LCALTA.36
 2112 04:42:30.802013  # ok 172 write_valid.LCALTA.36
 2113 04:42:30.807189  # ok 173 write_invalid.LCALTA.36
 2114 04:42:30.807850  # ok 174 event_missing.LCALTA.36
 2115 04:42:30.812412  # ok 175 event_spurious.LCALTA.36
 2116 04:42:30.812978  # ok 176 get_value.LCALTA.35
 2117 04:42:30.817982  # # LCALTA.35 FRDDR_B SRC 3 EN Switch
 2118 04:42:30.818538  # ok 177 name.LCALTA.35
 2119 04:42:30.823564  # ok 178 write_default.LCALTA.35
 2120 04:42:30.824142  # ok 179 write_valid.LCALTA.35
 2121 04:42:30.829056  # ok 180 write_invalid.LCALTA.35
 2122 04:42:30.829601  # ok 181 event_missing.LCALTA.35
 2123 04:42:30.834600  # ok 182 event_spurious.LCALTA.35
 2124 04:42:30.835132  # ok 183 get_value.LCALTA.34
 2125 04:42:30.840173  # # LCALTA.34 FRDDR_B SRC 2 EN Switch
 2126 04:42:30.840664  # ok 184 name.LCALTA.34
 2127 04:42:30.845610  # ok 185 write_default.LCALTA.34
 2128 04:42:30.845979  # ok 186 write_valid.LCALTA.34
 2129 04:42:30.851314  # ok 187 write_invalid.LCALTA.34
 2130 04:42:30.852137  # ok 188 event_missing.LCALTA.34
 2131 04:42:30.856859  # ok 189 event_spurious.LCALTA.34
 2132 04:42:30.857226  # ok 190 get_value.LCALTA.33
 2133 04:42:30.862455  # # LCALTA.33 FRDDR_B SRC 1 EN Switch
 2134 04:42:30.862838  # ok 191 name.LCALTA.33
 2135 04:42:30.867865  # ok 192 write_default.LCALTA.33
 2136 04:42:30.868454  # ok 193 write_valid.LCALTA.33
 2137 04:42:30.873456  # ok 194 write_invalid.LCALTA.33
 2138 04:42:30.873935  # ok 195 event_missing.LCALTA.33
 2139 04:42:30.879007  # ok 196 event_spurious.LCALTA.33
 2140 04:42:30.879609  # ok 197 get_value.LCALTA.32
 2141 04:42:30.884609  # # LCALTA.32 FRDDR_A SINK 3 SEL
 2142 04:42:30.884990  # ok 198 name.LCALTA.32
 2143 04:42:30.890098  # ok 199 write_default.LCALTA.32
 2144 04:42:30.890668  # ok 200 write_valid.LCALTA.32
 2145 04:42:30.896199  # ok 201 write_invalid.LCALTA.32
 2146 04:42:30.897886  # ok 202 event_missing.LCALTA.32
 2147 04:42:30.901195  # ok 203 event_spurious.LCALTA.32
 2148 04:42:30.901758  # ok 204 get_value.LCALTA.31
 2149 04:42:30.906687  # # LCALTA.31 FRDDR_A SINK 2 SEL
 2150 04:42:30.907282  # ok 205 name.LCALTA.31
 2151 04:42:30.912262  # ok 206 write_default.LCALTA.31
 2152 04:42:30.912846  # ok 207 write_valid.LCALTA.31
 2153 04:42:30.917808  # ok 208 write_invalid.LCALTA.31
 2154 04:42:30.918162  # ok 209 event_missing.LCALTA.31
 2155 04:42:30.923272  # ok 210 event_spurious.LCALTA.31
 2156 04:42:30.923669  # ok 211 get_value.LCALTA.30
 2157 04:42:30.929244  # # LCALTA.30 FRDDR_A SINK 1 SEL
 2158 04:42:30.929638  # ok 212 name.LCALTA.30
 2159 04:42:30.934581  # ok 213 write_default.LCALTA.30
 2160 04:42:30.935119  # ok 214 write_valid.LCALTA.30
 2161 04:42:30.940011  # ok 215 write_invalid.LCALTA.30
 2162 04:42:30.945643  # ok 216 event_missing.LCALTA.30
 2163 04:42:30.946205  # ok 217 event_spurious.LCALTA.30
 2164 04:42:30.951037  # ok 218 get_value.LCALTA.29
 2165 04:42:30.951542  # # LCALTA.29 FRDDR_A SRC 3 EN Switch
 2166 04:42:30.957148  # ok 219 name.LCALTA.29
 2167 04:42:30.957647  # ok 220 write_default.LCALTA.29
 2168 04:42:30.962194  # ok 221 write_valid.LCALTA.29
 2169 04:42:30.962670  # ok 222 write_invalid.LCALTA.29
 2170 04:42:30.967796  # ok 223 event_missing.LCALTA.29
 2171 04:42:30.968215  # ok 224 event_spurious.LCALTA.29
 2172 04:42:30.973443  # ok 225 get_value.LCALTA.28
 2173 04:42:30.974060  # # LCALTA.28 FRDDR_A SRC 2 EN Switch
 2174 04:42:30.979330  # ok 226 name.LCALTA.28
 2175 04:42:30.980004  # ok 227 write_default.LCALTA.28
 2176 04:42:30.984384  # ok 228 write_valid.LCALTA.28
 2177 04:42:30.984752  # ok 229 write_invalid.LCALTA.28
 2178 04:42:30.989908  # ok 230 event_missing.LCALTA.28
 2179 04:42:30.990517  # ok 231 event_spurious.LCALTA.28
 2180 04:42:30.995314  # ok 232 get_value.LCALTA.27
 2181 04:42:30.995616  # # LCALTA.27 FRDDR_A SRC 1 EN Switch
 2182 04:42:31.000942  # ok 233 name.LCALTA.27
 2183 04:42:31.001546  # ok 234 write_default.LCALTA.27
 2184 04:42:31.006445  # ok 235 write_valid.LCALTA.27
 2185 04:42:31.006781  # ok 236 write_invalid.LCALTA.27
 2186 04:42:31.012151  # ok 237 event_missing.LCALTA.27
 2187 04:42:31.012723  # ok 238 event_spurious.LCALTA.27
 2188 04:42:31.017732  # ok 239 get_value.LCALTA.26
 2189 04:42:31.018460  # # LCALTA.26 ELD
 2190 04:42:31.023291  # ok 240 name.LCALTA.26
 2191 04:42:31.023884  # # ELD is not writeable
 2192 04:42:31.028843  # ok 241 # SKIP write_default.LCALTA.26
 2193 04:42:31.029495  # # ELD is not writeable
 2194 04:42:31.035023  # ok 242 # SKIP write_valid.LCALTA.26
 2195 04:42:31.035425  # # ELD is not writeable
 2196 04:42:31.039886  # ok 243 # SKIP write_invalid.LCALTA.26
 2197 04:42:31.040606  # ok 244 event_missing.LCALTA.26
 2198 04:42:31.045395  # ok 245 event_spurious.LCALTA.26
 2199 04:42:31.045775  # ok 246 get_value.LCALTA.25
 2200 04:42:31.050958  # # LCALTA.25 IEC958 Playback Default
 2201 04:42:31.051534  # ok 247 name.LCALTA.25
 2202 04:42:31.056493  # ok 248 write_default.LCALTA.25
 2203 04:42:31.057092  # ok 249 # SKIP write_valid.LCALTA.25
 2204 04:42:31.062056  # ok 250 # SKIP write_invalid.LCALTA.25
 2205 04:42:31.067640  # ok 251 event_missing.LCALTA.25
 2206 04:42:31.068297  # ok 252 event_spurious.LCALTA.25
 2207 04:42:31.073151  # ok 253 get_value.LCALTA.24
 2208 04:42:31.073537  # # LCALTA.24 IEC958 Playback Mask
 2209 04:42:31.073788  # ok 254 name.LCALTA.24
 2210 04:42:31.078709  # # IEC958 Playback Mask is not writeable
 2211 04:42:31.084342  # ok 255 # SKIP write_default.LCALTA.24
 2212 04:42:31.084989  # # IEC958 Playback Mask is not writeable
 2213 04:42:31.089789  # ok 256 # SKIP write_valid.LCALTA.24
 2214 04:42:31.095358  # # IEC958 Playback Mask is not writeable
 2215 04:42:31.096077  # ok 257 # SKIP write_invalid.LCALTA.24
 2216 04:42:31.101120  # ok 258 event_missing.LCALTA.24
 2217 04:42:31.101820  # ok 259 event_spurious.LCALTA.24
 2218 04:42:31.106502  # ok 260 get_value.LCALTA.23
 2219 04:42:31.107093  # # LCALTA.23 Playback Channel Map
 2220 04:42:31.112092  # ok 261 name.LCALTA.23
 2221 04:42:31.117607  # # Playback Channel Map is not writeable
 2222 04:42:31.118254  # ok 262 # SKIP write_default.LCALTA.23
 2223 04:42:31.123100  # # Playback Channel Map is not writeable
 2224 04:42:31.123791  # ok 263 # SKIP write_valid.LCALTA.23
 2225 04:42:31.128630  # # Playback Channel Map is not writeable
 2226 04:42:31.134222  # ok 264 # SKIP write_invalid.LCALTA.23
 2227 04:42:31.134969  # ok 265 event_missing.LCALTA.23
 2228 04:42:31.139731  # ok 266 event_spurious.LCALTA.23
 2229 04:42:31.140439  # ok 267 get_value.LCALTA.22
 2230 04:42:31.145282  # # LCALTA.22 TDMOUT_A Gain Enable Switch
 2231 04:42:31.146000  # ok 268 name.LCALTA.22
 2232 04:42:31.150823  # ok 269 write_default.LCALTA.22
 2233 04:42:31.151472  # ok 270 write_valid.LCALTA.22
 2234 04:42:31.156356  # ok 271 write_invalid.LCALTA.22
 2235 04:42:31.156998  # ok 272 event_missing.LCALTA.22
 2236 04:42:31.161925  # ok 273 event_spurious.LCALTA.22
 2237 04:42:31.167613  # ok 274 get_value.LCALTA.21
 2238 04:42:31.168379  # # LCALTA.21 TDMOUT_A Lane 3 Volume
 2239 04:42:31.168911  # ok 275 name.LCALTA.21
 2240 04:42:31.173029  # ok 276 write_default.LCALTA.21
 2241 04:42:31.178418  # ok 277 write_valid.LCALTA.21
 2242 04:42:31.179013  # ok 278 write_invalid.LCALTA.21
 2243 04:42:31.184039  # ok 279 event_missing.LCALTA.21
 2244 04:42:31.184576  # ok 280 event_spurious.LCALTA.21
 2245 04:42:31.189533  # ok 281 get_value.LCALTA.20
 2246 04:42:31.190153  # # LCALTA.20 TDMOUT_A Lane 2 Volume
 2247 04:42:31.195208  # ok 282 name.LCALTA.20
 2248 04:42:31.196215  # ok 283 write_default.LCALTA.20
 2249 04:42:31.200872  # ok 284 write_valid.LCALTA.20
 2250 04:42:31.201737  # ok 285 write_invalid.LCALTA.20
 2251 04:42:31.206369  # ok 286 event_missing.LCALTA.20
 2252 04:42:31.207409  # ok 287 event_spurious.LCALTA.20
 2253 04:42:31.211931  # ok 288 get_value.LCALTA.19
 2254 04:42:31.212945  # # LCALTA.19 TDMOUT_A Lane 1 Volume
 2255 04:42:31.217417  # ok 289 name.LCALTA.19
 2256 04:42:31.217980  # ok 290 write_default.LCALTA.19
 2257 04:42:31.222812  # ok 291 write_valid.LCALTA.19
 2258 04:42:31.223357  # ok 292 write_invalid.LCALTA.19
 2259 04:42:31.228368  # ok 293 event_missing.LCALTA.19
 2260 04:42:31.228973  # ok 294 event_spurious.LCALTA.19
 2261 04:42:31.233972  # ok 295 get_value.LCALTA.18
 2262 04:42:31.234575  # # LCALTA.18 TDMOUT_A Lane 0 Volume
 2263 04:42:31.239486  # ok 296 name.LCALTA.18
 2264 04:42:31.240060  # ok 297 write_default.LCALTA.18
 2265 04:42:31.245028  # ok 298 write_valid.LCALTA.18
 2266 04:42:31.245639  # ok 299 write_invalid.LCALTA.18
 2267 04:42:31.250605  # ok 300 event_missing.LCALTA.18
 2268 04:42:31.251200  # ok 301 event_spurious.LCALTA.18
 2269 04:42:31.256186  # ok 302 get_value.LCALTA.17
 2270 04:42:31.261687  # # LCALTA.17 TDMOUT_B Gain Enable Switch
 2271 04:42:31.262229  # ok 303 name.LCALTA.17
 2272 04:42:31.262764  # ok 304 write_default.LCALTA.17
 2273 04:42:31.267267  # ok 305 write_valid.LCALTA.17
 2274 04:42:31.272742  # ok 306 write_invalid.LCALTA.17
 2275 04:42:31.273332  # ok 307 event_missing.LCALTA.17
 2276 04:42:31.278291  # ok 308 event_spurious.LCALTA.17
 2277 04:42:31.278905  # ok 309 get_value.LCALTA.16
 2278 04:42:31.283857  # # LCALTA.16 TDMOUT_B Lane 3 Volume
 2279 04:42:31.284501  # ok 310 name.LCALTA.16
 2280 04:42:31.289437  # ok 311 write_default.LCALTA.16
 2281 04:42:31.290024  # ok 312 write_valid.LCALTA.16
 2282 04:42:31.295002  # ok 313 write_invalid.LCALTA.16
 2283 04:42:31.295612  # ok 314 event_missing.LCALTA.16
 2284 04:42:31.300544  # ok 315 event_spurious.LCALTA.16
 2285 04:42:31.301086  # ok 316 get_value.LCALTA.15
 2286 04:42:31.306032  # # LCALTA.15 TDMOUT_B Lane 2 Volume
 2287 04:42:31.306633  # ok 317 name.LCALTA.15
 2288 04:42:31.311614  # ok 318 write_default.LCALTA.15
 2289 04:42:31.312280  # ok 319 write_valid.LCALTA.15
 2290 04:42:31.317201  # ok 320 write_invalid.LCALTA.15
 2291 04:42:31.317802  # ok 321 event_missing.LCALTA.15
 2292 04:42:31.322858  # ok 322 event_spurious.LCALTA.15
 2293 04:42:31.323836  # ok 323 get_value.LCALTA.14
 2294 04:42:31.328482  # # LCALTA.14 TDMOUT_B Lane 1 Volume
 2295 04:42:31.329385  # ok 324 name.LCALTA.14
 2296 04:42:31.333880  # ok 325 write_default.LCALTA.14
 2297 04:42:31.334447  # ok 326 write_valid.LCALTA.14
 2298 04:42:31.339462  # ok 327 write_invalid.LCALTA.14
 2299 04:42:31.340470  # ok 328 event_missing.LCALTA.14
 2300 04:42:31.344881  # ok 329 event_spurious.LCALTA.14
 2301 04:42:31.345438  # ok 330 get_value.LCALTA.13
 2302 04:42:31.350429  # # LCALTA.13 TDMOUT_B Lane 0 Volume
 2303 04:42:31.351045  # ok 331 name.LCALTA.13
 2304 04:42:31.356016  # ok 332 write_default.LCALTA.13
 2305 04:42:31.356617  # ok 333 write_valid.LCALTA.13
 2306 04:42:31.361500  # ok 334 write_invalid.LCALTA.13
 2307 04:42:31.362115  # ok 335 event_missing.LCALTA.13
 2308 04:42:31.367079  # ok 336 event_spurious.LCALTA.13
 2309 04:42:31.367622  # ok 337 get_value.LCALTA.12
 2310 04:42:31.372583  # # LCALTA.12 TDMOUT_C Gain Enable Switch
 2311 04:42:31.373123  # ok 338 name.LCALTA.12
 2312 04:42:31.378171  # ok 339 write_default.LCALTA.12
 2313 04:42:31.383723  # ok 340 write_valid.LCALTA.12
 2314 04:42:31.384307  # ok 341 write_invalid.LCALTA.12
 2315 04:42:31.389295  # ok 342 event_missing.LCALTA.12
 2316 04:42:31.389852  # ok 343 event_spurious.LCALTA.12
 2317 04:42:31.395020  # ok 344 get_value.LCALTA.11
 2318 04:42:31.396119  # # LCALTA.11 TDMOUT_C Lane 3 Volume
 2319 04:42:31.400418  # ok 345 name.LCALTA.11
 2320 04:42:31.401044  # ok 346 write_default.LCALTA.11
 2321 04:42:31.405952  # ok 347 write_valid.LCALTA.11
 2322 04:42:31.406573  # ok 348 write_invalid.LCALTA.11
 2323 04:42:31.411549  # ok 349 event_missing.LCALTA.11
 2324 04:42:31.412224  # ok 350 event_spurious.LCALTA.11
 2325 04:42:31.417023  # ok 351 get_value.LCALTA.10
 2326 04:42:31.417639  # # LCALTA.10 TDMOUT_C Lane 2 Volume
 2327 04:42:31.422700  # ok 352 name.LCALTA.10
 2328 04:42:31.423283  # ok 353 write_default.LCALTA.10
 2329 04:42:31.428135  # ok 354 write_valid.LCALTA.10
 2330 04:42:31.428713  # ok 355 write_invalid.LCALTA.10
 2331 04:42:31.433671  # ok 356 event_missing.LCALTA.10
 2332 04:42:31.434240  # ok 357 event_spurious.LCALTA.10
 2333 04:42:31.439255  # ok 358 get_value.LCALTA.9
 2334 04:42:31.439812  # # LCALTA.9 TDMOUT_C Lane 1 Volume
 2335 04:42:31.444770  # ok 359 name.LCALTA.9
 2336 04:42:31.445338  # ok 360 write_default.LCALTA.9
 2337 04:42:31.450253  # ok 361 write_valid.LCALTA.9
 2338 04:42:31.450778  # ok 362 write_invalid.LCALTA.9
 2339 04:42:31.455734  # ok 363 event_missing.LCALTA.9
 2340 04:42:31.456352  # ok 364 event_spurious.LCALTA.9
 2341 04:42:31.461349  # ok 365 get_value.LCALTA.8
 2342 04:42:31.461925  # # LCALTA.8 TDMOUT_C Lane 0 Volume
 2343 04:42:31.466825  # ok 366 name.LCALTA.8
 2344 04:42:31.467398  # ok 367 write_default.LCALTA.8
 2345 04:42:31.472357  # ok 368 write_valid.LCALTA.8
 2346 04:42:31.472940  # ok 369 write_invalid.LCALTA.8
 2347 04:42:31.477913  # ok 370 event_missing.LCALTA.8
 2348 04:42:31.478469  # ok 371 event_spurious.LCALTA.8
 2349 04:42:31.483366  # ok 372 get_value.LCALTA.7
 2350 04:42:31.483869  # # LCALTA.7 ACODEC Unmute Ramp Switch
 2351 04:42:31.488934  # ok 373 name.LCALTA.7
 2352 04:42:31.489469  # ok 374 write_default.LCALTA.7
 2353 04:42:31.494506  # ok 375 write_valid.LCALTA.7
 2354 04:42:31.495036  # ok 376 write_invalid.LCALTA.7
 2355 04:42:31.500092  # ok 377 event_missing.LCALTA.7
 2356 04:42:31.500634  # ok 378 event_spurious.LCALTA.7
 2357 04:42:31.505585  # ok 379 get_value.LCALTA.6
 2358 04:42:31.506100  # # LCALTA.6 ACODEC Mute Ramp Switch
 2359 04:42:31.511177  # ok 380 name.LCALTA.6
 2360 04:42:31.511890  # ok 381 write_default.LCALTA.6
 2361 04:42:31.516696  # ok 382 write_valid.LCALTA.6
 2362 04:42:31.517221  # ok 383 write_invalid.LCALTA.6
 2363 04:42:31.522194  # ok 384 event_missing.LCALTA.6
 2364 04:42:31.522706  # ok 385 event_spurious.LCALTA.6
 2365 04:42:31.527752  # ok 386 get_value.LCALTA.5
 2366 04:42:31.528363  # # LCALTA.5 ACODEC Volume Ramp Switch
 2367 04:42:31.533365  # ok 387 name.LCALTA.5
 2368 04:42:31.533975  # ok 388 write_default.LCALTA.5
 2369 04:42:31.538842  # ok 389 write_valid.LCALTA.5
 2370 04:42:31.539404  # ok 390 write_invalid.LCALTA.5
 2371 04:42:31.544474  # ok 391 event_missing.LCALTA.5
 2372 04:42:31.545235  # ok 392 event_spurious.LCALTA.5
 2373 04:42:31.549999  # ok 393 get_value.LCALTA.4
 2374 04:42:31.550868  # # LCALTA.4 ACODEC Ramp Rate
 2375 04:42:31.555636  # ok 394 name.LCALTA.4
 2376 04:42:31.556337  # ok 395 write_default.LCALTA.4
 2377 04:42:31.561039  # ok 396 write_valid.LCALTA.4
 2378 04:42:31.561577  # ok 397 write_invalid.LCALTA.4
 2379 04:42:31.566593  # ok 398 event_missing.LCALTA.4
 2380 04:42:31.567115  # ok 399 event_spurious.LCALTA.4
 2381 04:42:31.572184  # ok 400 get_value.LCALTA.3
 2382 04:42:31.572690  # # LCALTA.3 ACODEC Playback Volume
 2383 04:42:31.577657  # ok 401 name.LCALTA.3
 2384 04:42:31.578161  # ok 402 write_default.LCALTA.3
 2385 04:42:31.583212  # ok 403 write_valid.LCALTA.3
 2386 04:42:31.583715  # ok 404 write_invalid.LCALTA.3
 2387 04:42:31.588762  # ok 405 event_missing.LCALTA.3
 2388 04:42:31.589268  # ok 406 event_spurious.LCALTA.3
 2389 04:42:31.594328  # ok 407 get_value.LCALTA.2
 2390 04:42:31.594826  # # LCALTA.2 ACODEC Playback Switch
 2391 04:42:31.599850  # ok 408 name.LCALTA.2
 2392 04:42:31.600387  # ok 409 write_default.LCALTA.2
 2393 04:42:31.605490  # ok 410 write_valid.LCALTA.2
 2394 04:42:31.606017  # ok 411 write_invalid.LCALTA.2
 2395 04:42:31.611157  # ok 412 event_missing.LCALTA.2
 2396 04:42:31.611770  # ok 413 event_spurious.LCALTA.2
 2397 04:42:31.616579  # ok 414 get_value.LCALTA.1
 2398 04:42:31.617138  # # LCALTA.1 ACODEC Playback Channel Mode
 2399 04:42:31.622127  # ok 415 name.LCALTA.1
 2400 04:42:31.622713  # ok 416 write_default.LCALTA.1
 2401 04:42:31.627652  # ok 417 write_valid.LCALTA.1
 2402 04:42:31.628260  # ok 418 write_invalid.LCALTA.1
 2403 04:42:31.633210  # ok 419 event_missing.LCALTA.1
 2404 04:42:31.633769  # ok 420 event_spurious.LCALTA.1
 2405 04:42:31.638781  # ok 421 get_value.LCALTA.0
 2406 04:42:31.639336  # # LCALTA.0 TOACODEC Lane Select
 2407 04:42:31.644280  # ok 422 name.LCALTA.0
 2408 04:42:31.644832  # ok 423 write_default.LCALTA.0
 2409 04:42:31.649873  # ok 424 write_valid.LCALTA.0
 2410 04:42:31.650436  # ok 425 write_invalid.LCALTA.0
 2411 04:42:31.655350  # ok 426 event_missing.LCALTA.0
 2412 04:42:31.655897  # ok 427 event_spurious.LCALTA.0
 2413 04:42:31.660883  # # Totals: pass:416 fail:0 xfail:0 xpass:0 skip:11 error:0
 2414 04:42:31.666592  ok 1 selftests: alsa: mixer-test
 2415 04:42:31.667163  # timeout set to 45
 2416 04:42:31.667630  # selftests: alsa: pcm-test
 2417 04:42:31.672038  # TAP version 13
 2418 04:42:31.672442  # # Card 0/LCALTA - LC-ALTA (LC-ALTA)
 2419 04:42:31.677652  # # LCALTA.0 - fe.dai-link-0 (*)
 2420 04:42:31.678021  # # LCALTA.0 - fe.dai-link-1 (*)
 2421 04:42:31.683149  # # LCALTA.0 - fe.dai-link-2 (*)
 2422 04:42:31.683640  # # LCALTA.0 - fe.dai-link-3 (*)
 2423 04:42:31.688743  # # LCALTA.0 - fe.dai-link-4 (*)
 2424 04:42:31.689113  # # LCALTA.0 - fe.dai-link-5 (*)
 2425 04:42:31.694249  # 1..42
 2426 04:42:31.699775  # # default.time1.LCALTA.5.0.CAPTURE - 8kHz mono large periods
 2427 04:42:31.700125  # ok 1 # SKIP default.time1.LCALTA.5.0.CAPTURE
 2428 04:42:31.705365  # # snd_pcm_hw_params: Invalid argument
 2429 04:42:31.710890  # # default.time2.LCALTA.5.0.CAPTURE - 8kHz stereo large periods
 2430 04:42:31.716451  # ok 2 # SKIP default.time2.LCALTA.5.0.CAPTURE
 2431 04:42:31.716793  # # snd_pcm_hw_params: Invalid argument
 2432 04:42:31.721986  # # default.time3.LCALTA.5.0.CAPTURE - 44.1kHz stereo large periods
 2433 04:42:31.727611  # ok 3 # SKIP default.time3.LCALTA.5.0.CAPTURE
 2434 04:42:31.733080  # # snd_pcm_hw_params: Invalid argument
 2435 04:42:31.738783  # # default.time4.LCALTA.5.0.CAPTURE - 48kHz stereo small periods
 2436 04:42:31.744183  # ok 4 # SKIP default.time4.LCALTA.5.0.CAPTURE
 2437 04:42:31.744752  # # snd_pcm_hw_params: Invalid argument
 2438 04:42:31.749737  # # default.time5.LCALTA.5.0.CAPTURE - 48kHz stereo large periods
 2439 04:42:31.755209  # ok 5 # SKIP default.time5.LCALTA.5.0.CAPTURE
 2440 04:42:31.760727  # # snd_pcm_hw_params: Invalid argument
 2441 04:42:31.766264  # # default.time6.LCALTA.5.0.CAPTURE - 48kHz 6 channel large periods
 2442 04:42:31.771814  # ok 6 # SKIP default.time6.LCALTA.5.0.CAPTURE
 2443 04:42:31.772364  # # snd_pcm_hw_params: Invalid argument
 2444 04:42:31.777395  # # default.time7.LCALTA.5.0.CAPTURE - 96kHz stereo large periods
 2445 04:42:31.782911  # ok 7 # SKIP default.time7.LCALTA.5.0.CAPTURE
 2446 04:42:31.788522  # # snd_pcm_hw_params: Invalid argument
 2447 04:42:31.793979  # # default.time1.LCALTA.4.0.CAPTURE - 8kHz mono large periods
 2448 04:42:31.794442  # ok 8 # SKIP default.time1.LCALTA.4.0.CAPTURE
 2449 04:42:31.799581  # # snd_pcm_hw_params: Invalid argument
 2450 04:42:31.805056  # # default.time2.LCALTA.4.0.CAPTURE - 8kHz stereo large periods
 2451 04:42:31.810678  # ok 9 # SKIP default.time2.LCALTA.4.0.CAPTURE
 2452 04:42:31.811280  # # snd_pcm_hw_params: Invalid argument
 2453 04:42:31.821713  # # default.time3.LCALTA.4.0.CAPTURE - 44.1kHz stereo large periods
 2454 04:42:31.822264  # ok 10 # SKIP default.time3.LCALTA.4.0.CAPTURE
 2455 04:42:31.827243  # # snd_pcm_hw_params: Invalid argument
 2456 04:42:31.832814  # # default.time4.LCALTA.4.0.CAPTURE - 48kHz stereo small periods
 2457 04:42:31.838375  # ok 11 # SKIP default.time4.LCALTA.4.0.CAPTURE
 2458 04:42:31.838878  # # snd_pcm_hw_params: Invalid argument
 2459 04:42:31.843913  # # default.time5.LCALTA.4.0.CAPTURE - 48kHz stereo large periods
 2460 04:42:31.849495  # ok 12 # SKIP default.time5.LCALTA.4.0.CAPTURE
 2461 04:42:31.854999  # # snd_pcm_hw_params: Invalid argument
 2462 04:42:31.860582  # # default.time6.LCALTA.4.0.CAPTURE - 48kHz 6 channel large periods
 2463 04:42:31.866083  # ok 13 # SKIP default.time6.LCALTA.4.0.CAPTURE
 2464 04:42:31.866586  # # snd_pcm_hw_params: Invalid argument
 2465 04:42:31.871645  # # default.time7.LCALTA.4.0.CAPTURE - 96kHz stereo large periods
 2466 04:42:31.877173  # ok 14 # SKIP default.time7.LCALTA.4.0.CAPTURE
 2467 04:42:31.882744  # # snd_pcm_hw_params: Invalid argument
 2468 04:42:31.888279  # # default.time1.LCALTA.3.0.CAPTURE - 8kHz mono large periods
 2469 04:42:31.893819  # ok 15 # SKIP default.time1.LCALTA.3.0.CAPTURE
 2470 04:42:31.894333  # # snd_pcm_hw_params: Invalid argument
 2471 04:42:31.899394  # # default.time2.LCALTA.3.0.CAPTURE - 8kHz stereo large periods
 2472 04:42:31.904909  # ok 16 # SKIP default.time2.LCALTA.3.0.CAPTURE
 2473 04:42:31.910505  # # snd_pcm_hw_params: Invalid argument
 2474 04:42:31.916030  # # default.time3.LCALTA.3.0.CAPTURE - 44.1kHz stereo large periods
 2475 04:42:31.916493  # ok 17 # SKIP default.time3.LCALTA.3.0.CAPTURE
 2476 04:42:31.921584  # # snd_pcm_hw_params: Invalid argument
 2477 04:42:31.927104  # # default.time4.LCALTA.3.0.CAPTURE - 48kHz stereo small periods
 2478 04:42:31.932743  # ok 18 # SKIP default.time4.LCALTA.3.0.CAPTURE
 2479 04:42:31.938252  # # snd_pcm_hw_params: Invalid argument
 2480 04:42:31.943763  # # default.time5.LCALTA.3.0.CAPTURE - 48kHz stereo large periods
 2481 04:42:31.944296  # ok 19 # SKIP default.time5.LCALTA.3.0.CAPTURE
 2482 04:42:31.949284  # # snd_pcm_hw_params: Invalid argument
 2483 04:42:31.954828  # # default.time6.LCALTA.3.0.CAPTURE - 48kHz 6 channel large periods
 2484 04:42:31.960423  # ok 20 # SKIP default.time6.LCALTA.3.0.CAPTURE
 2485 04:42:31.966019  # # snd_pcm_hw_params: Invalid argument
 2486 04:42:31.971598  # # default.time7.LCALTA.3.0.CAPTURE - 96kHz stereo large periods
 2487 04:42:31.972149  # ok 21 # SKIP default.time7.LCALTA.3.0.CAPTURE
 2488 04:42:31.977102  # # snd_pcm_hw_params: Invalid argument
 2489 04:42:31.982586  # # default.time1.LCALTA.2.0.PLAYBACK - 8kHz mono large periods
 2490 04:42:31.988207  # ok 22 # SKIP default.time1.LCALTA.2.0.PLAYBACK
 2491 04:42:31.988740  # # snd_pcm_hw_params: Invalid argument
 2492 04:42:31.993728  # # default.time2.LCALTA.2.0.PLAYBACK - 8kHz stereo large periods
 2493 04:42:31.999244  # ok 23 # SKIP default.time2.LCALTA.2.0.PLAYBACK
 2494 04:42:32.004766  # # snd_pcm_hw_params: Invalid argument
 2495 04:42:32.010323  # # default.time3.LCALTA.2.0.PLAYBACK - 44.1kHz stereo large periods
 2496 04:42:32.015872  # ok 24 # SKIP default.time3.LCALTA.2.0.PLAYBACK
 2497 04:42:32.016345  # # snd_pcm_hw_params: Invalid argument
 2498 04:42:32.021429  # # default.time4.LCALTA.2.0.PLAYBACK - 48kHz stereo small periods
 2499 04:42:32.026947  # ok 25 # SKIP default.time4.LCALTA.2.0.PLAYBACK
 2500 04:42:32.032522  # # snd_pcm_hw_params: Invalid argument
 2501 04:42:32.038064  # # default.time5.LCALTA.2.0.PLAYBACK - 48kHz stereo large periods
 2502 04:42:32.043601  # ok 26 # SKIP default.time5.LCALTA.2.0.PLAYBACK
 2503 04:42:32.044072  # # snd_pcm_hw_params: Invalid argument
 2504 04:42:32.049164  # # default.time6.LCALTA.2.0.PLAYBACK - 48kHz 6 channel large periods
 2505 04:42:32.054690  # ok 27 # SKIP default.time6.LCALTA.2.0.PLAYBACK
 2506 04:42:32.060241  # # snd_pcm_hw_params: Invalid argument
 2507 04:42:32.065774  # # default.time7.LCALTA.2.0.PLAYBACK - 96kHz stereo large periods
 2508 04:42:32.071304  # ok 28 # SKIP default.time7.LCALTA.2.0.PLAYBACK
 2509 04:42:32.071737  # # snd_pcm_hw_params: Invalid argument
 2510 04:42:32.076884  # # default.time1.LCALTA.1.0.PLAYBACK - 8kHz mono large periods
 2511 04:42:32.082423  # ok 29 # SKIP default.time1.LCALTA.1.0.PLAYBACK
 2512 04:42:32.087962  # # snd_pcm_hw_params: Invalid argument
 2513 04:42:32.093504  # # default.time2.LCALTA.1.0.PLAYBACK - 8kHz stereo large periods
 2514 04:42:32.099068  # ok 30 # SKIP default.time2.LCALTA.1.0.PLAYBACK
 2515 04:42:32.099522  # # snd_pcm_hw_params: Invalid argument
 2516 04:42:32.104584  # # default.time3.LCALTA.1.0.PLAYBACK - 44.1kHz stereo large periods
 2517 04:42:32.110123  # ok 31 # SKIP default.time3.LCALTA.1.0.PLAYBACK
 2518 04:42:32.115732  # # snd_pcm_hw_params: Invalid argument
 2519 04:42:32.121262  # # default.time4.LCALTA.1.0.PLAYBACK - 48kHz stereo small periods
 2520 04:42:32.126803  # ok 32 # SKIP default.time4.LCALTA.1.0.PLAYBACK
 2521 04:42:32.127383  # # snd_pcm_hw_params: Invalid argument
 2522 04:42:32.132363  # # default.time5.LCALTA.1.0.PLAYBACK - 48kHz stereo large periods
 2523 04:42:32.137887  # ok 33 # SKIP default.time5.LCALTA.1.0.PLAYBACK
 2524 04:42:32.143413  # # snd_pcm_hw_params: Invalid argument
 2525 04:42:32.148962  # # default.time6.LCALTA.1.0.PLAYBACK - 48kHz 6 channel large periods
 2526 04:42:32.154610  # ok 34 # SKIP default.time6.LCALTA.1.0.PLAYBACK
 2527 04:42:32.155180  # # snd_pcm_hw_params: Invalid argument
 2528 04:42:32.160069  # # default.time7.LCALTA.1.0.PLAYBACK - 96kHz stereo large periods
 2529 04:42:32.165619  # ok 35 # SKIP default.time7.LCALTA.1.0.PLAYBACK
 2530 04:42:32.171150  # # snd_pcm_hw_params: Invalid argument
 2531 04:42:32.176733  # # default.time1.LCALTA.0.0.PLAYBACK - 8kHz mono large periods
 2532 04:42:32.182297  # ok 36 # SKIP default.time1.LCALTA.0.0.PLAYBACK
 2533 04:42:32.182895  # # snd_pcm_hw_params: Invalid argument
 2534 04:42:32.187828  # # default.time2.LCALTA.0.0.PLAYBACK - 8kHz stereo large periods
 2535 04:42:32.193395  # ok 37 # SKIP default.time2.LCALTA.0.0.PLAYBACK
 2536 04:42:32.198919  # # snd_pcm_hw_params: Invalid argument
 2537 04:42:32.204482  # # default.time3.LCALTA.0.0.PLAYBACK - 44.1kHz stereo large periods
 2538 04:42:32.210010  # ok 38 # SKIP default.time3.LCALTA.0.0.PLAYBACK
 2539 04:42:32.210615  # # snd_pcm_hw_params: Invalid argument
 2540 04:42:32.215594  # # default.time4.LCALTA.0.0.PLAYBACK - 48kHz stereo small periods
 2541 04:42:32.221076  # ok 39 # SKIP default.time4.LCALTA.0.0.PLAYBACK
 2542 04:42:32.226703  # # snd_pcm_hw_params: Invalid argument
 2543 04:42:32.232242  # # default.time5.LCALTA.0.0.PLAYBACK - 48kHz stereo large periods
 2544 04:42:32.237782  # ok 40 # SKIP default.time5.LCALTA.0.0.PLAYBACK
 2545 04:42:32.238351  # # snd_pcm_hw_params: Invalid argument
 2546 04:42:32.243344  # # default.time6.LCALTA.0.0.PLAYBACK - 48kHz 6 channel large periods
 2547 04:42:32.248888  # ok 41 # SKIP default.time6.LCALTA.0.0.PLAYBACK
 2548 04:42:32.254407  # # snd_pcm_hw_params: Invalid argument
 2549 04:42:32.259929  # # default.time7.LCALTA.0.0.PLAYBACK - 96kHz stereo large periods
 2550 04:42:32.265529  # ok 42 # SKIP default.time7.LCALTA.0.0.PLAYBACK
 2551 04:42:32.266085  # # snd_pcm_hw_params: Invalid argument
 2552 04:42:32.271058  # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:42 error:0
 2553 04:42:32.276614  ok 2 selftests: alsa: pcm-test
 2554 04:42:32.277193  # timeout set to 45
 2555 04:42:32.282165  # selftests: alsa: test-pcmtest-driver
 2556 04:42:32.282726  # TAP version 13
 2557 04:42:32.283239  # 1..5
 2558 04:42:32.287707  # # Starting 5 tests from 1 test cases.
 2559 04:42:32.288332  # #  RUN           pcmtest.playback ...
 2560 04:42:32.293260  # #      SKIP      Can't read patterns. Probably, module isn't loaded
 2561 04:42:32.298796  # #            OK  pcmtest.playback
 2562 04:42:32.304350  # ok 1 pcmtest.playback # SKIP Can't read patterns. Probably, module isn't loaded
 2563 04:42:32.309910  # #  RUN           pcmtest.capture ...
 2564 04:42:32.315461  # #      SKIP      Can't read patterns. Probably, module isn't loaded
 2565 04:42:32.320980  # #            OK  pcmtest.capture
 2566 04:42:32.326528  # ok 2 pcmtest.capture # SKIP Can't read patterns. Probably, module isn't loaded
 2567 04:42:32.332277  # #  RUN           pcmtest.ni_capture ...
 2568 04:42:32.337724  # #      SKIP      Can't read patterns. Probably, module isn't loaded
 2569 04:42:32.338342  # #            OK  pcmtest.ni_capture
 2570 04:42:32.348840  # ok 3 pcmtest.ni_capture # SKIP Can't read patterns. Probably, module isn't loaded
 2571 04:42:32.349466  # #  RUN           pcmtest.ni_playback ...
 2572 04:42:32.354393  # #      SKIP      Can't read patterns. Probably, module isn't loaded
 2573 04:42:32.359910  # #            OK  pcmtest.ni_playback
 2574 04:42:32.365385  # ok 4 pcmtest.ni_playback # SKIP Can't read patterns. Probably, module isn't loaded
 2575 04:42:32.370921  # #  RUN           pcmtest.reset_ioctl ...
 2576 04:42:32.376465  # #      SKIP      Can't read patterns. Probably, module isn't loaded
 2577 04:42:32.382067  # #            OK  pcmtest.reset_ioctl
 2578 04:42:32.387548  # ok 5 pcmtest.reset_ioctl # SKIP Can't read patterns. Probably, module isn't loaded
 2579 04:42:32.393070  # # PASSED: 5 / 5 tests passed.
 2580 04:42:32.398609  # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:5 error:0
 2581 04:42:32.399179  ok 3 selftests: alsa: test-pcmtest-driver
 2582 04:42:32.404209  # timeout set to 45
 2583 04:42:32.404805  # selftests: alsa: utimer-test
 2584 04:42:32.405341  # TAP version 13
 2585 04:42:32.405862  # 1..2
 2586 04:42:32.409803  # # Starting 2 tests from 2 test cases.
 2587 04:42:32.415301  # #  RUN           global.wrong_timers_test ...
 2588 04:42:32.420816  # #            OK  global.wrong_timers_test
 2589 04:42:32.421392  # ok 1 global.wrong_timers_test
 2590 04:42:32.426324  # #  RUN           timer_f.utimer ...
 2591 04:42:32.431885  # # utimer-test.c:55:utimer:Expected ioctl(timer_dev_fd, SNDRV_TIMER_IOCTL_CREATE, self->utimer_info) (-1) == 0 (0)
 2592 04:42:32.437435  # # utimer: Test terminated by assertion
 2593 04:42:32.442980  # #          FAIL  timer_f.utimer
 2594 04:42:32.443546  # not ok 2 timer_f.utimer
 2595 04:42:32.448515  # # FAILED: 1 / 2 tests passed.
 2596 04:42:32.455938  # # Totals: pass:1 fail:1 xfail:0 xpass:0 skip:0 error:0
 2597 04:42:32.456541  not ok 4 selftests: alsa: utimer-test # exit=1
 2598 04:42:33.306000  alsa_mixer-test_get_value_LCALTA_60 pass
 2599 04:42:33.311389  alsa_mixer-test_name_LCALTA_60 pass
 2600 04:42:33.311976  alsa_mixer-test_write_default_LCALTA_60 pass
 2601 04:42:33.316930  alsa_mixer-test_write_valid_LCALTA_60 pass
 2602 04:42:33.320406  alsa_mixer-test_write_invalid_LCALTA_60 pass
 2603 04:42:33.325940  alsa_mixer-test_event_missing_LCALTA_60 pass
 2604 04:42:33.331487  alsa_mixer-test_event_spurious_LCALTA_60 pass
 2605 04:42:33.332106  alsa_mixer-test_get_value_LCALTA_59 pass
 2606 04:42:33.337057  alsa_mixer-test_name_LCALTA_59 pass
 2607 04:42:33.340504  alsa_mixer-test_write_default_LCALTA_59 pass
 2608 04:42:33.346045  alsa_mixer-test_write_valid_LCALTA_59 pass
 2609 04:42:33.346597  alsa_mixer-test_write_invalid_LCALTA_59 pass
 2610 04:42:33.351599  alsa_mixer-test_event_missing_LCALTA_59 pass
 2611 04:42:33.357156  alsa_mixer-test_event_spurious_LCALTA_59 pass
 2612 04:42:33.362722  alsa_mixer-test_get_value_LCALTA_58 pass
 2613 04:42:33.363284  alsa_mixer-test_name_LCALTA_58 pass
 2614 04:42:33.368260  alsa_mixer-test_write_default_LCALTA_58 pass
 2615 04:42:33.373792  alsa_mixer-test_write_valid_LCALTA_58 pass
 2616 04:42:33.374348  alsa_mixer-test_write_invalid_LCALTA_58 pass
 2617 04:42:33.379357  alsa_mixer-test_event_missing_LCALTA_58 pass
 2618 04:42:33.384892  alsa_mixer-test_event_spurious_LCALTA_58 pass
 2619 04:42:33.385480  alsa_mixer-test_get_value_LCALTA_57 pass
 2620 04:42:33.390494  alsa_mixer-test_name_LCALTA_57 pass
 2621 04:42:33.396068  alsa_mixer-test_write_default_LCALTA_57 pass
 2622 04:42:33.396625  alsa_mixer-test_write_valid_LCALTA_57 pass
 2623 04:42:33.401592  alsa_mixer-test_write_invalid_LCALTA_57 pass
 2624 04:42:33.407136  alsa_mixer-test_event_missing_LCALTA_57 pass
 2625 04:42:33.407681  alsa_mixer-test_event_spurious_LCALTA_57 pass
 2626 04:42:33.412692  alsa_mixer-test_get_value_LCALTA_56 pass
 2627 04:42:33.418217  alsa_mixer-test_name_LCALTA_56 pass
 2628 04:42:33.418771  alsa_mixer-test_write_default_LCALTA_56 pass
 2629 04:42:33.423783  alsa_mixer-test_write_valid_LCALTA_56 pass
 2630 04:42:33.429313  alsa_mixer-test_write_invalid_LCALTA_56 pass
 2631 04:42:33.434848  alsa_mixer-test_event_missing_LCALTA_56 pass
 2632 04:42:33.435398  alsa_mixer-test_event_spurious_LCALTA_56 pass
 2633 04:42:33.440422  alsa_mixer-test_get_value_LCALTA_55 pass
 2634 04:42:33.445958  alsa_mixer-test_name_LCALTA_55 pass
 2635 04:42:33.446510  alsa_mixer-test_write_default_LCALTA_55 pass
 2636 04:42:33.451481  alsa_mixer-test_write_valid_LCALTA_55 pass
 2637 04:42:33.457042  alsa_mixer-test_write_invalid_LCALTA_55 pass
 2638 04:42:33.457604  alsa_mixer-test_event_missing_LCALTA_55 pass
 2639 04:42:33.462603  alsa_mixer-test_event_spurious_LCALTA_55 pass
 2640 04:42:33.468206  alsa_mixer-test_get_value_LCALTA_54 pass
 2641 04:42:33.468756  alsa_mixer-test_name_LCALTA_54 pass
 2642 04:42:33.473667  alsa_mixer-test_write_default_LCALTA_54 pass
 2643 04:42:33.479246  alsa_mixer-test_write_valid_LCALTA_54 pass
 2644 04:42:33.479797  alsa_mixer-test_write_invalid_LCALTA_54 pass
 2645 04:42:33.484801  alsa_mixer-test_event_missing_LCALTA_54 pass
 2646 04:42:33.490330  alsa_mixer-test_event_spurious_LCALTA_54 pass
 2647 04:42:33.495882  alsa_mixer-test_get_value_LCALTA_53 pass
 2648 04:42:33.496442  alsa_mixer-test_name_LCALTA_53 pass
 2649 04:42:33.501425  alsa_mixer-test_write_default_LCALTA_53 pass
 2650 04:42:33.506959  alsa_mixer-test_write_valid_LCALTA_53 pass
 2651 04:42:33.507509  alsa_mixer-test_write_invalid_LCALTA_53 pass
 2652 04:42:33.512501  alsa_mixer-test_event_missing_LCALTA_53 pass
 2653 04:42:33.518069  alsa_mixer-test_event_spurious_LCALTA_53 pass
 2654 04:42:33.518629  alsa_mixer-test_get_value_LCALTA_52 pass
 2655 04:42:33.523609  alsa_mixer-test_name_LCALTA_52 pass
 2656 04:42:33.529141  alsa_mixer-test_write_default_LCALTA_52 pass
 2657 04:42:33.529713  alsa_mixer-test_write_valid_LCALTA_52 pass
 2658 04:42:33.534707  alsa_mixer-test_write_invalid_LCALTA_52 pass
 2659 04:42:33.540240  alsa_mixer-test_event_missing_LCALTA_52 pass
 2660 04:42:33.545805  alsa_mixer-test_event_spurious_LCALTA_52 pass
 2661 04:42:33.546364  alsa_mixer-test_get_value_LCALTA_51 pass
 2662 04:42:33.551332  alsa_mixer-test_name_LCALTA_51 pass
 2663 04:42:33.556900  alsa_mixer-test_write_default_LCALTA_51 pass
 2664 04:42:33.557490  alsa_mixer-test_write_valid_LCALTA_51 pass
 2665 04:42:33.562441  alsa_mixer-test_write_invalid_LCALTA_51 pass
 2666 04:42:33.567965  alsa_mixer-test_event_missing_LCALTA_51 pass
 2667 04:42:33.568549  alsa_mixer-test_event_spurious_LCALTA_51 pass
 2668 04:42:33.573548  alsa_mixer-test_get_value_LCALTA_50 pass
 2669 04:42:33.579084  alsa_mixer-test_name_LCALTA_50 pass
 2670 04:42:33.579636  alsa_mixer-test_write_default_LCALTA_50 pass
 2671 04:42:33.584612  alsa_mixer-test_write_valid_LCALTA_50 pass
 2672 04:42:33.590188  alsa_mixer-test_write_invalid_LCALTA_50 pass
 2673 04:42:33.590748  alsa_mixer-test_event_missing_LCALTA_50 pass
 2674 04:42:33.595711  alsa_mixer-test_event_spurious_LCALTA_50 pass
 2675 04:42:33.601237  alsa_mixer-test_get_value_LCALTA_49 pass
 2676 04:42:33.601796  alsa_mixer-test_name_LCALTA_49 pass
 2677 04:42:33.606820  alsa_mixer-test_write_default_LCALTA_49 pass
 2678 04:42:33.612365  alsa_mixer-test_write_valid_LCALTA_49 pass
 2679 04:42:33.617901  alsa_mixer-test_write_invalid_LCALTA_49 pass
 2680 04:42:33.618450  alsa_mixer-test_event_missing_LCALTA_49 pass
 2681 04:42:33.623442  alsa_mixer-test_event_spurious_LCALTA_49 pass
 2682 04:42:33.629004  alsa_mixer-test_get_value_LCALTA_48 pass
 2683 04:42:33.629566  alsa_mixer-test_name_LCALTA_48 pass
 2684 04:42:33.634532  alsa_mixer-test_write_default_LCALTA_48 pass
 2685 04:42:33.640099  alsa_mixer-test_write_valid_LCALTA_48 pass
 2686 04:42:33.640660  alsa_mixer-test_write_invalid_LCALTA_48 pass
 2687 04:42:33.645640  alsa_mixer-test_event_missing_LCALTA_48 pass
 2688 04:42:33.651177  alsa_mixer-test_event_spurious_LCALTA_48 pass
 2689 04:42:33.651736  alsa_mixer-test_get_value_LCALTA_47 pass
 2690 04:42:33.656719  alsa_mixer-test_name_LCALTA_47 pass
 2691 04:42:33.662272  alsa_mixer-test_write_default_LCALTA_47 pass
 2692 04:42:33.662844  alsa_mixer-test_write_valid_LCALTA_47 pass
 2693 04:42:33.667829  alsa_mixer-test_write_invalid_LCALTA_47 pass
 2694 04:42:33.673373  alsa_mixer-test_event_missing_LCALTA_47 pass
 2695 04:42:33.679194  alsa_mixer-test_event_spurious_LCALTA_47 pass
 2696 04:42:33.679754  alsa_mixer-test_get_value_LCALTA_46 pass
 2697 04:42:33.684466  alsa_mixer-test_name_LCALTA_46 pass
 2698 04:42:33.690021  alsa_mixer-test_write_default_LCALTA_46 pass
 2699 04:42:33.690569  alsa_mixer-test_write_valid_LCALTA_46 pass
 2700 04:42:33.695564  alsa_mixer-test_write_invalid_LCALTA_46 pass
 2701 04:42:33.701113  alsa_mixer-test_event_missing_LCALTA_46 pass
 2702 04:42:33.701681  alsa_mixer-test_event_spurious_LCALTA_46 pass
 2703 04:42:33.706625  alsa_mixer-test_get_value_LCALTA_45 pass
 2704 04:42:33.712230  alsa_mixer-test_name_LCALTA_45 pass
 2705 04:42:33.712789  alsa_mixer-test_write_default_LCALTA_45 pass
 2706 04:42:33.717833  alsa_mixer-test_write_valid_LCALTA_45 pass
 2707 04:42:33.723284  alsa_mixer-test_write_invalid_LCALTA_45 pass
 2708 04:42:33.728860  alsa_mixer-test_event_missing_LCALTA_45 pass
 2709 04:42:33.729405  alsa_mixer-test_event_spurious_LCALTA_45 pass
 2710 04:42:33.734388  alsa_mixer-test_get_value_LCALTA_44 pass
 2711 04:42:33.734934  alsa_mixer-test_name_LCALTA_44 pass
 2712 04:42:33.739945  alsa_mixer-test_write_default_LCALTA_44 pass
 2713 04:42:33.745481  alsa_mixer-test_write_valid_LCALTA_44 pass
 2714 04:42:33.751023  alsa_mixer-test_write_invalid_LCALTA_44 pass
 2715 04:42:33.751573  alsa_mixer-test_event_missing_LCALTA_44 pass
 2716 04:42:33.756580  alsa_mixer-test_event_spurious_LCALTA_44 pass
 2717 04:42:33.762105  alsa_mixer-test_get_value_LCALTA_43 pass
 2718 04:42:33.762668  alsa_mixer-test_name_LCALTA_43 pass
 2719 04:42:33.767652  alsa_mixer-test_write_default_LCALTA_43 pass
 2720 04:42:33.773228  alsa_mixer-test_write_valid_LCALTA_43 pass
 2721 04:42:33.773775  alsa_mixer-test_write_invalid_LCALTA_43 pass
 2722 04:42:33.778829  alsa_mixer-test_event_missing_LCALTA_43 pass
 2723 04:42:33.784314  alsa_mixer-test_event_spurious_LCALTA_43 pass
 2724 04:42:33.789864  alsa_mixer-test_get_value_LCALTA_42 pass
 2725 04:42:33.790415  alsa_mixer-test_name_LCALTA_42 pass
 2726 04:42:33.795391  alsa_mixer-test_write_default_LCALTA_42 pass
 2727 04:42:33.800930  alsa_mixer-test_write_valid_LCALTA_42 pass
 2728 04:42:33.801480  alsa_mixer-test_write_invalid_LCALTA_42 pass
 2729 04:42:33.806493  alsa_mixer-test_event_missing_LCALTA_42 pass
 2730 04:42:33.812065  alsa_mixer-test_event_spurious_LCALTA_42 pass
 2731 04:42:33.812617  alsa_mixer-test_get_value_LCALTA_41 pass
 2732 04:42:33.817584  alsa_mixer-test_name_LCALTA_41 pass
 2733 04:42:33.823111  alsa_mixer-test_write_default_LCALTA_41 pass
 2734 04:42:33.823656  alsa_mixer-test_write_valid_LCALTA_41 pass
 2735 04:42:33.828679  alsa_mixer-test_write_invalid_LCALTA_41 pass
 2736 04:42:33.834212  alsa_mixer-test_event_missing_LCALTA_41 pass
 2737 04:42:33.834776  alsa_mixer-test_event_spurious_LCALTA_41 pass
 2738 04:42:33.839758  alsa_mixer-test_get_value_LCALTA_40 pass
 2739 04:42:33.845319  alsa_mixer-test_name_LCALTA_40 pass
 2740 04:42:33.845872  alsa_mixer-test_write_default_LCALTA_40 pass
 2741 04:42:33.850892  alsa_mixer-test_write_valid_LCALTA_40 pass
 2742 04:42:33.856398  alsa_mixer-test_write_invalid_LCALTA_40 pass
 2743 04:42:33.861975  alsa_mixer-test_event_missing_LCALTA_40 pass
 2744 04:42:33.862543  alsa_mixer-test_event_spurious_LCALTA_40 pass
 2745 04:42:33.867492  alsa_mixer-test_get_value_LCALTA_39 pass
 2746 04:42:33.873041  alsa_mixer-test_name_LCALTA_39 pass
 2747 04:42:33.873607  alsa_mixer-test_write_default_LCALTA_39 pass
 2748 04:42:33.878602  alsa_mixer-test_write_valid_LCALTA_39 pass
 2749 04:42:33.884207  alsa_mixer-test_write_invalid_LCALTA_39 pass
 2750 04:42:33.884791  alsa_mixer-test_event_missing_LCALTA_39 pass
 2751 04:42:33.889718  alsa_mixer-test_event_spurious_LCALTA_39 pass
 2752 04:42:33.895241  alsa_mixer-test_get_value_LCALTA_38 pass
 2753 04:42:33.895784  alsa_mixer-test_name_LCALTA_38 pass
 2754 04:42:33.900869  alsa_mixer-test_write_default_LCALTA_38 pass
 2755 04:42:33.906342  alsa_mixer-test_write_valid_LCALTA_38 pass
 2756 04:42:33.906891  alsa_mixer-test_write_invalid_LCALTA_38 pass
 2757 04:42:33.911910  alsa_mixer-test_event_missing_LCALTA_38 pass
 2758 04:42:33.917423  alsa_mixer-test_event_spurious_LCALTA_38 pass
 2759 04:42:33.922965  alsa_mixer-test_get_value_LCALTA_37 pass
 2760 04:42:33.923511  alsa_mixer-test_name_LCALTA_37 pass
 2761 04:42:33.928489  alsa_mixer-test_write_default_LCALTA_37 pass
 2762 04:42:33.934084  alsa_mixer-test_write_valid_LCALTA_37 pass
 2763 04:42:33.934627  alsa_mixer-test_write_invalid_LCALTA_37 pass
 2764 04:42:33.939608  alsa_mixer-test_event_missing_LCALTA_37 pass
 2765 04:42:33.945141  alsa_mixer-test_event_spurious_LCALTA_37 pass
 2766 04:42:33.945695  alsa_mixer-test_get_value_LCALTA_36 pass
 2767 04:42:33.950726  alsa_mixer-test_name_LCALTA_36 pass
 2768 04:42:33.956225  alsa_mixer-test_write_default_LCALTA_36 pass
 2769 04:42:33.956770  alsa_mixer-test_write_valid_LCALTA_36 pass
 2770 04:42:33.961874  alsa_mixer-test_write_invalid_LCALTA_36 pass
 2771 04:42:33.967350  alsa_mixer-test_event_missing_LCALTA_36 pass
 2772 04:42:33.972917  alsa_mixer-test_event_spurious_LCALTA_36 pass
 2773 04:42:33.973461  alsa_mixer-test_get_value_LCALTA_35 pass
 2774 04:42:33.978420  alsa_mixer-test_name_LCALTA_35 pass
 2775 04:42:33.984019  alsa_mixer-test_write_default_LCALTA_35 pass
 2776 04:42:33.984568  alsa_mixer-test_write_valid_LCALTA_35 pass
 2777 04:42:33.989534  alsa_mixer-test_write_invalid_LCALTA_35 pass
 2778 04:42:33.995100  alsa_mixer-test_event_missing_LCALTA_35 pass
 2779 04:42:33.995649  alsa_mixer-test_event_spurious_LCALTA_35 pass
 2780 04:42:34.000604  alsa_mixer-test_get_value_LCALTA_34 pass
 2781 04:42:34.006179  alsa_mixer-test_name_LCALTA_34 pass
 2782 04:42:34.006752  alsa_mixer-test_write_default_LCALTA_34 pass
 2783 04:42:34.011717  alsa_mixer-test_write_valid_LCALTA_34 pass
 2784 04:42:34.017237  alsa_mixer-test_write_invalid_LCALTA_34 pass
 2785 04:42:34.017788  alsa_mixer-test_event_missing_LCALTA_34 pass
 2786 04:42:34.022843  alsa_mixer-test_event_spurious_LCALTA_34 pass
 2787 04:42:34.028361  alsa_mixer-test_get_value_LCALTA_33 pass
 2788 04:42:34.028907  alsa_mixer-test_name_LCALTA_33 pass
 2789 04:42:34.033906  alsa_mixer-test_write_default_LCALTA_33 pass
 2790 04:42:34.039427  alsa_mixer-test_write_valid_LCALTA_33 pass
 2791 04:42:34.044988  alsa_mixer-test_write_invalid_LCALTA_33 pass
 2792 04:42:34.045554  alsa_mixer-test_event_missing_LCALTA_33 pass
 2793 04:42:34.050504  alsa_mixer-test_event_spurious_LCALTA_33 pass
 2794 04:42:34.056093  alsa_mixer-test_get_value_LCALTA_32 pass
 2795 04:42:34.056643  alsa_mixer-test_name_LCALTA_32 pass
 2796 04:42:34.061608  alsa_mixer-test_write_default_LCALTA_32 pass
 2797 04:42:34.067148  alsa_mixer-test_write_valid_LCALTA_32 pass
 2798 04:42:34.067695  alsa_mixer-test_write_invalid_LCALTA_32 pass
 2799 04:42:34.072720  alsa_mixer-test_event_missing_LCALTA_32 pass
 2800 04:42:34.078249  alsa_mixer-test_event_spurious_LCALTA_32 pass
 2801 04:42:34.078795  alsa_mixer-test_get_value_LCALTA_31 pass
 2802 04:42:34.083877  alsa_mixer-test_name_LCALTA_31 pass
 2803 04:42:34.089367  alsa_mixer-test_write_default_LCALTA_31 pass
 2804 04:42:34.089927  alsa_mixer-test_write_valid_LCALTA_31 pass
 2805 04:42:34.094917  alsa_mixer-test_write_invalid_LCALTA_31 pass
 2806 04:42:34.100419  alsa_mixer-test_event_missing_LCALTA_31 pass
 2807 04:42:34.105978  alsa_mixer-test_event_spurious_LCALTA_31 pass
 2808 04:42:34.106529  alsa_mixer-test_get_value_LCALTA_30 pass
 2809 04:42:34.111545  alsa_mixer-test_name_LCALTA_30 pass
 2810 04:42:34.117069  alsa_mixer-test_write_default_LCALTA_30 pass
 2811 04:42:34.117615  alsa_mixer-test_write_valid_LCALTA_30 pass
 2812 04:42:34.122625  alsa_mixer-test_write_invalid_LCALTA_30 pass
 2813 04:42:34.128196  alsa_mixer-test_event_missing_LCALTA_30 pass
 2814 04:42:34.128748  alsa_mixer-test_event_spurious_LCALTA_30 pass
 2815 04:42:34.133725  alsa_mixer-test_get_value_LCALTA_29 pass
 2816 04:42:34.139286  alsa_mixer-test_name_LCALTA_29 pass
 2817 04:42:34.139835  alsa_mixer-test_write_default_LCALTA_29 pass
 2818 04:42:34.144857  alsa_mixer-test_write_valid_LCALTA_29 pass
 2819 04:42:34.150389  alsa_mixer-test_write_invalid_LCALTA_29 pass
 2820 04:42:34.155906  alsa_mixer-test_event_missing_LCALTA_29 pass
 2821 04:42:34.156469  alsa_mixer-test_event_spurious_LCALTA_29 pass
 2822 04:42:34.161465  alsa_mixer-test_get_value_LCALTA_28 pass
 2823 04:42:34.162013  alsa_mixer-test_name_LCALTA_28 pass
 2824 04:42:34.167011  alsa_mixer-test_write_default_LCALTA_28 pass
 2825 04:42:34.172533  alsa_mixer-test_write_valid_LCALTA_28 pass
 2826 04:42:34.178105  alsa_mixer-test_write_invalid_LCALTA_28 pass
 2827 04:42:34.178648  alsa_mixer-test_event_missing_LCALTA_28 pass
 2828 04:42:34.183641  alsa_mixer-test_event_spurious_LCALTA_28 pass
 2829 04:42:34.189206  alsa_mixer-test_get_value_LCALTA_27 pass
 2830 04:42:34.189752  alsa_mixer-test_name_LCALTA_27 pass
 2831 04:42:34.194754  alsa_mixer-test_write_default_LCALTA_27 pass
 2832 04:42:34.200295  alsa_mixer-test_write_valid_LCALTA_27 pass
 2833 04:42:34.200860  alsa_mixer-test_write_invalid_LCALTA_27 pass
 2834 04:42:34.205884  alsa_mixer-test_event_missing_LCALTA_27 pass
 2835 04:42:34.211384  alsa_mixer-test_event_spurious_LCALTA_27 pass
 2836 04:42:34.216922  alsa_mixer-test_get_value_LCALTA_26 pass
 2837 04:42:34.217469  alsa_mixer-test_name_LCALTA_26 pass
 2838 04:42:34.222498  alsa_mixer-test_write_default_LCALTA_26 skip
 2839 04:42:34.228258  alsa_mixer-test_write_valid_LCALTA_26 skip
 2840 04:42:34.228850  alsa_mixer-test_write_invalid_LCALTA_26 skip
 2841 04:42:34.233654  alsa_mixer-test_event_missing_LCALTA_26 pass
 2842 04:42:34.239313  alsa_mixer-test_event_spurious_LCALTA_26 pass
 2843 04:42:34.239868  alsa_mixer-test_get_value_LCALTA_25 pass
 2844 04:42:34.244828  alsa_mixer-test_name_LCALTA_25 pass
 2845 04:42:34.250342  alsa_mixer-test_write_default_LCALTA_25 pass
 2846 04:42:34.250885  alsa_mixer-test_write_valid_LCALTA_25 skip
 2847 04:42:34.255949  alsa_mixer-test_write_invalid_LCALTA_25 skip
 2848 04:42:34.261475  alsa_mixer-test_event_missing_LCALTA_25 pass
 2849 04:42:34.262015  alsa_mixer-test_event_spurious_LCALTA_25 pass
 2850 04:42:34.267056  alsa_mixer-test_get_value_LCALTA_24 pass
 2851 04:42:34.272548  alsa_mixer-test_name_LCALTA_24 pass
 2852 04:42:34.273113  alsa_mixer-test_write_default_LCALTA_24 skip
 2853 04:42:34.278080  alsa_mixer-test_write_valid_LCALTA_24 skip
 2854 04:42:34.283644  alsa_mixer-test_write_invalid_LCALTA_24 skip
 2855 04:42:34.289211  alsa_mixer-test_event_missing_LCALTA_24 pass
 2856 04:42:34.289740  alsa_mixer-test_event_spurious_LCALTA_24 pass
 2857 04:42:34.294687  alsa_mixer-test_get_value_LCALTA_23 pass
 2858 04:42:34.300277  alsa_mixer-test_name_LCALTA_23 pass
 2859 04:42:34.300753  alsa_mixer-test_write_default_LCALTA_23 skip
 2860 04:42:34.305773  alsa_mixer-test_write_valid_LCALTA_23 skip
 2861 04:42:34.311311  alsa_mixer-test_write_invalid_LCALTA_23 skip
 2862 04:42:34.311792  alsa_mixer-test_event_missing_LCALTA_23 pass
 2863 04:42:34.316894  alsa_mixer-test_event_spurious_LCALTA_23 pass
 2864 04:42:34.322425  alsa_mixer-test_get_value_LCALTA_22 pass
 2865 04:42:34.322921  alsa_mixer-test_name_LCALTA_22 pass
 2866 04:42:34.328029  alsa_mixer-test_write_default_LCALTA_22 pass
 2867 04:42:34.333484  alsa_mixer-test_write_valid_LCALTA_22 pass
 2868 04:42:34.333986  alsa_mixer-test_write_invalid_LCALTA_22 pass
 2869 04:42:34.339029  alsa_mixer-test_event_missing_LCALTA_22 pass
 2870 04:42:34.344587  alsa_mixer-test_event_spurious_LCALTA_22 pass
 2871 04:42:34.350120  alsa_mixer-test_get_value_LCALTA_21 pass
 2872 04:42:34.350603  alsa_mixer-test_name_LCALTA_21 pass
 2873 04:42:34.355660  alsa_mixer-test_write_default_LCALTA_21 pass
 2874 04:42:34.361322  alsa_mixer-test_write_valid_LCALTA_21 pass
 2875 04:42:34.361856  alsa_mixer-test_write_invalid_LCALTA_21 pass
 2876 04:42:34.366794  alsa_mixer-test_event_missing_LCALTA_21 pass
 2877 04:42:34.372441  alsa_mixer-test_event_spurious_LCALTA_21 pass
 2878 04:42:34.373087  alsa_mixer-test_get_value_LCALTA_20 pass
 2879 04:42:34.377808  alsa_mixer-test_name_LCALTA_20 pass
 2880 04:42:34.383333  alsa_mixer-test_write_default_LCALTA_20 pass
 2881 04:42:34.383861  alsa_mixer-test_write_valid_LCALTA_20 pass
 2882 04:42:34.388926  alsa_mixer-test_write_invalid_LCALTA_20 pass
 2883 04:42:34.394419  alsa_mixer-test_event_missing_LCALTA_20 pass
 2884 04:42:34.399962  alsa_mixer-test_event_spurious_LCALTA_20 pass
 2885 04:42:34.400554  alsa_mixer-test_get_value_LCALTA_19 pass
 2886 04:42:34.405546  alsa_mixer-test_name_LCALTA_19 pass
 2887 04:42:34.411086  alsa_mixer-test_write_default_LCALTA_19 pass
 2888 04:42:34.411629  alsa_mixer-test_write_valid_LCALTA_19 pass
 2889 04:42:34.416620  alsa_mixer-test_write_invalid_LCALTA_19 pass
 2890 04:42:34.422186  alsa_mixer-test_event_missing_LCALTA_19 pass
 2891 04:42:34.422737  alsa_mixer-test_event_spurious_LCALTA_19 pass
 2892 04:42:34.427741  alsa_mixer-test_get_value_LCALTA_18 pass
 2893 04:42:34.433279  alsa_mixer-test_name_LCALTA_18 pass
 2894 04:42:34.433842  alsa_mixer-test_write_default_LCALTA_18 pass
 2895 04:42:34.438834  alsa_mixer-test_write_valid_LCALTA_18 pass
 2896 04:42:34.444368  alsa_mixer-test_write_invalid_LCALTA_18 pass
 2897 04:42:34.444923  alsa_mixer-test_event_missing_LCALTA_18 pass
 2898 04:42:34.449955  alsa_mixer-test_event_spurious_LCALTA_18 pass
 2899 04:42:34.455442  alsa_mixer-test_get_value_LCALTA_17 pass
 2900 04:42:34.456000  alsa_mixer-test_name_LCALTA_17 pass
 2901 04:42:34.460994  alsa_mixer-test_write_default_LCALTA_17 pass
 2902 04:42:34.466558  alsa_mixer-test_write_valid_LCALTA_17 pass
 2903 04:42:34.472093  alsa_mixer-test_write_invalid_LCALTA_17 pass
 2904 04:42:34.472637  alsa_mixer-test_event_missing_LCALTA_17 pass
 2905 04:42:34.477662  alsa_mixer-test_event_spurious_LCALTA_17 pass
 2906 04:42:34.483231  alsa_mixer-test_get_value_LCALTA_16 pass
 2907 04:42:34.483845  alsa_mixer-test_name_LCALTA_16 pass
 2908 04:42:34.488698  alsa_mixer-test_write_default_LCALTA_16 pass
 2909 04:42:34.494239  alsa_mixer-test_write_valid_LCALTA_16 pass
 2910 04:42:34.494785  alsa_mixer-test_write_invalid_LCALTA_16 pass
 2911 04:42:34.499866  alsa_mixer-test_event_missing_LCALTA_16 pass
 2912 04:42:34.505384  alsa_mixer-test_event_spurious_LCALTA_16 pass
 2913 04:42:34.505935  alsa_mixer-test_get_value_LCALTA_15 pass
 2914 04:42:34.510963  alsa_mixer-test_name_LCALTA_15 pass
 2915 04:42:34.516483  alsa_mixer-test_write_default_LCALTA_15 pass
 2916 04:42:34.517050  alsa_mixer-test_write_valid_LCALTA_15 pass
 2917 04:42:34.522007  alsa_mixer-test_write_invalid_LCALTA_15 pass
 2918 04:42:34.527597  alsa_mixer-test_event_missing_LCALTA_15 pass
 2919 04:42:34.533092  alsa_mixer-test_event_spurious_LCALTA_15 pass
 2920 04:42:34.533646  alsa_mixer-test_get_value_LCALTA_14 pass
 2921 04:42:34.538639  alsa_mixer-test_name_LCALTA_14 pass
 2922 04:42:34.544199  alsa_mixer-test_write_default_LCALTA_14 pass
 2923 04:42:34.544743  alsa_mixer-test_write_valid_LCALTA_14 pass
 2924 04:42:34.549723  alsa_mixer-test_write_invalid_LCALTA_14 pass
 2925 04:42:34.555295  alsa_mixer-test_event_missing_LCALTA_14 pass
 2926 04:42:34.555842  alsa_mixer-test_event_spurious_LCALTA_14 pass
 2927 04:42:34.560804  alsa_mixer-test_get_value_LCALTA_13 pass
 2928 04:42:34.566379  alsa_mixer-test_name_LCALTA_13 pass
 2929 04:42:34.566923  alsa_mixer-test_write_default_LCALTA_13 pass
 2930 04:42:34.572005  alsa_mixer-test_write_valid_LCALTA_13 pass
 2931 04:42:34.577497  alsa_mixer-test_write_invalid_LCALTA_13 pass
 2932 04:42:34.583061  alsa_mixer-test_event_missing_LCALTA_13 pass
 2933 04:42:34.583617  alsa_mixer-test_event_spurious_LCALTA_13 pass
 2934 04:42:34.588591  alsa_mixer-test_get_value_LCALTA_12 pass
 2935 04:42:34.589133  alsa_mixer-test_name_LCALTA_12 pass
 2936 04:42:34.594131  alsa_mixer-test_write_default_LCALTA_12 pass
 2937 04:42:34.599692  alsa_mixer-test_write_valid_LCALTA_12 pass
 2938 04:42:34.605404  alsa_mixer-test_write_invalid_LCALTA_12 pass
 2939 04:42:34.606019  alsa_mixer-test_event_missing_LCALTA_12 pass
 2940 04:42:34.610803  alsa_mixer-test_event_spurious_LCALTA_12 pass
 2941 04:42:34.616350  alsa_mixer-test_get_value_LCALTA_11 pass
 2942 04:42:34.616918  alsa_mixer-test_name_LCALTA_11 pass
 2943 04:42:34.621868  alsa_mixer-test_write_default_LCALTA_11 pass
 2944 04:42:34.627436  alsa_mixer-test_write_valid_LCALTA_11 pass
 2945 04:42:34.628045  alsa_mixer-test_write_invalid_LCALTA_11 pass
 2946 04:42:34.632956  alsa_mixer-test_event_missing_LCALTA_11 pass
 2947 04:42:34.638510  alsa_mixer-test_event_spurious_LCALTA_11 pass
 2948 04:42:34.644068  alsa_mixer-test_get_value_LCALTA_10 pass
 2949 04:42:34.644630  alsa_mixer-test_name_LCALTA_10 pass
 2950 04:42:34.649567  alsa_mixer-test_write_default_LCALTA_10 pass
 2951 04:42:34.655145  alsa_mixer-test_write_valid_LCALTA_10 pass
 2952 04:42:34.655704  alsa_mixer-test_write_invalid_LCALTA_10 pass
 2953 04:42:34.660681  alsa_mixer-test_event_missing_LCALTA_10 pass
 2954 04:42:34.666212  alsa_mixer-test_event_spurious_LCALTA_10 pass
 2955 04:42:34.666752  alsa_mixer-test_get_value_LCALTA_9 pass
 2956 04:42:34.671769  alsa_mixer-test_name_LCALTA_9 pass
 2957 04:42:34.677349  alsa_mixer-test_write_default_LCALTA_9 pass
 2958 04:42:34.677919  alsa_mixer-test_write_valid_LCALTA_9 pass
 2959 04:42:34.682887  alsa_mixer-test_write_invalid_LCALTA_9 pass
 2960 04:42:34.688417  alsa_mixer-test_event_missing_LCALTA_9 pass
 2961 04:42:34.688978  alsa_mixer-test_event_spurious_LCALTA_9 pass
 2962 04:42:34.693973  alsa_mixer-test_get_value_LCALTA_8 pass
 2963 04:42:34.699526  alsa_mixer-test_name_LCALTA_8 pass
 2964 04:42:34.700108  alsa_mixer-test_write_default_LCALTA_8 pass
 2965 04:42:34.705084  alsa_mixer-test_write_valid_LCALTA_8 pass
 2966 04:42:34.710599  alsa_mixer-test_write_invalid_LCALTA_8 pass
 2967 04:42:34.711137  alsa_mixer-test_event_missing_LCALTA_8 pass
 2968 04:42:34.716152  alsa_mixer-test_event_spurious_LCALTA_8 pass
 2969 04:42:34.721743  alsa_mixer-test_get_value_LCALTA_7 pass
 2970 04:42:34.722279  alsa_mixer-test_name_LCALTA_7 pass
 2971 04:42:34.727261  alsa_mixer-test_write_default_LCALTA_7 pass
 2972 04:42:34.732777  alsa_mixer-test_write_valid_LCALTA_7 pass
 2973 04:42:34.733283  alsa_mixer-test_write_invalid_LCALTA_7 pass
 2974 04:42:34.738306  alsa_mixer-test_event_missing_LCALTA_7 pass
 2975 04:42:34.743878  alsa_mixer-test_event_spurious_LCALTA_7 pass
 2976 04:42:34.744391  alsa_mixer-test_get_value_LCALTA_6 pass
 2977 04:42:34.749472  alsa_mixer-test_name_LCALTA_6 pass
 2978 04:42:34.754989  alsa_mixer-test_write_default_LCALTA_6 pass
 2979 04:42:34.755526  alsa_mixer-test_write_valid_LCALTA_6 pass
 2980 04:42:34.760531  alsa_mixer-test_write_invalid_LCALTA_6 pass
 2981 04:42:34.766065  alsa_mixer-test_event_missing_LCALTA_6 pass
 2982 04:42:34.766590  alsa_mixer-test_event_spurious_LCALTA_6 pass
 2983 04:42:34.771606  alsa_mixer-test_get_value_LCALTA_5 pass
 2984 04:42:34.777165  alsa_mixer-test_name_LCALTA_5 pass
 2985 04:42:34.777688  alsa_mixer-test_write_default_LCALTA_5 pass
 2986 04:42:34.782727  alsa_mixer-test_write_valid_LCALTA_5 pass
 2987 04:42:34.788271  alsa_mixer-test_write_invalid_LCALTA_5 pass
 2988 04:42:34.788811  alsa_mixer-test_event_missing_LCALTA_5 pass
 2989 04:42:34.793788  alsa_mixer-test_event_spurious_LCALTA_5 pass
 2990 04:42:34.799367  alsa_mixer-test_get_value_LCALTA_4 pass
 2991 04:42:34.799899  alsa_mixer-test_name_LCALTA_4 pass
 2992 04:42:34.804978  alsa_mixer-test_write_default_LCALTA_4 pass
 2993 04:42:34.810423  alsa_mixer-test_write_valid_LCALTA_4 pass
 2994 04:42:34.810945  alsa_mixer-test_write_invalid_LCALTA_4 pass
 2995 04:42:34.815970  alsa_mixer-test_event_missing_LCALTA_4 pass
 2996 04:42:34.821532  alsa_mixer-test_event_spurious_LCALTA_4 pass
 2997 04:42:34.827099  alsa_mixer-test_get_value_LCALTA_3 pass
 2998 04:42:34.827690  alsa_mixer-test_name_LCALTA_3 pass
 2999 04:42:34.832629  alsa_mixer-test_write_default_LCALTA_3 pass
 3000 04:42:34.833165  alsa_mixer-test_write_valid_LCALTA_3 pass
 3001 04:42:34.838157  alsa_mixer-test_write_invalid_LCALTA_3 pass
 3002 04:42:34.843693  alsa_mixer-test_event_missing_LCALTA_3 pass
 3003 04:42:34.849251  alsa_mixer-test_event_spurious_LCALTA_3 pass
 3004 04:42:34.849787  alsa_mixer-test_get_value_LCALTA_2 pass
 3005 04:42:34.854810  alsa_mixer-test_name_LCALTA_2 pass
 3006 04:42:34.860381  alsa_mixer-test_write_default_LCALTA_2 pass
 3007 04:42:34.860937  alsa_mixer-test_write_valid_LCALTA_2 pass
 3008 04:42:34.865911  alsa_mixer-test_write_invalid_LCALTA_2 pass
 3009 04:42:34.871472  alsa_mixer-test_event_missing_LCALTA_2 pass
 3010 04:42:34.872029  alsa_mixer-test_event_spurious_LCALTA_2 pass
 3011 04:42:34.877020  alsa_mixer-test_get_value_LCALTA_1 pass
 3012 04:42:34.882563  alsa_mixer-test_name_LCALTA_1 pass
 3013 04:42:34.883087  alsa_mixer-test_write_default_LCALTA_1 pass
 3014 04:42:34.888086  alsa_mixer-test_write_valid_LCALTA_1 pass
 3015 04:42:34.893637  alsa_mixer-test_write_invalid_LCALTA_1 pass
 3016 04:42:34.894162  alsa_mixer-test_event_missing_LCALTA_1 pass
 3017 04:42:34.899186  alsa_mixer-test_event_spurious_LCALTA_1 pass
 3018 04:42:34.904759  alsa_mixer-test_get_value_LCALTA_0 pass
 3019 04:42:34.905287  alsa_mixer-test_name_LCALTA_0 pass
 3020 04:42:34.910264  alsa_mixer-test_write_default_LCALTA_0 pass
 3021 04:42:34.915813  alsa_mixer-test_write_valid_LCALTA_0 pass
 3022 04:42:34.916361  alsa_mixer-test_write_invalid_LCALTA_0 pass
 3023 04:42:34.921386  alsa_mixer-test_event_missing_LCALTA_0 pass
 3024 04:42:34.927000  alsa_mixer-test_event_spurious_LCALTA_0 pass
 3025 04:42:34.927519  alsa_mixer-test pass
 3026 04:42:34.932477  alsa_pcm-test_default_time1_LCALTA_5_0_CAPTURE skip
 3027 04:42:34.938061  alsa_pcm-test_default_time2_LCALTA_5_0_CAPTURE skip
 3028 04:42:34.943578  alsa_pcm-test_default_time3_LCALTA_5_0_CAPTURE skip
 3029 04:42:34.944134  alsa_pcm-test_default_time4_LCALTA_5_0_CAPTURE skip
 3030 04:42:34.949130  alsa_pcm-test_default_time5_LCALTA_5_0_CAPTURE skip
 3031 04:42:34.954634  alsa_pcm-test_default_time6_LCALTA_5_0_CAPTURE skip
 3032 04:42:34.960225  alsa_pcm-test_default_time7_LCALTA_5_0_CAPTURE skip
 3033 04:42:34.965761  alsa_pcm-test_default_time1_LCALTA_4_0_CAPTURE skip
 3034 04:42:34.971311  alsa_pcm-test_default_time2_LCALTA_4_0_CAPTURE skip
 3035 04:42:34.971845  alsa_pcm-test_default_time3_LCALTA_4_0_CAPTURE skip
 3036 04:42:34.976945  alsa_pcm-test_default_time4_LCALTA_4_0_CAPTURE skip
 3037 04:42:34.982398  alsa_pcm-test_default_time5_LCALTA_4_0_CAPTURE skip
 3038 04:42:34.988064  alsa_pcm-test_default_time6_LCALTA_4_0_CAPTURE skip
 3039 04:42:34.993557  alsa_pcm-test_default_time7_LCALTA_4_0_CAPTURE skip
 3040 04:42:34.994130  alsa_pcm-test_default_time1_LCALTA_3_0_CAPTURE skip
 3041 04:42:34.999062  alsa_pcm-test_default_time2_LCALTA_3_0_CAPTURE skip
 3042 04:42:35.004574  alsa_pcm-test_default_time3_LCALTA_3_0_CAPTURE skip
 3043 04:42:35.010165  alsa_pcm-test_default_time4_LCALTA_3_0_CAPTURE skip
 3044 04:42:35.015683  alsa_pcm-test_default_time5_LCALTA_3_0_CAPTURE skip
 3045 04:42:35.021243  alsa_pcm-test_default_time6_LCALTA_3_0_CAPTURE skip
 3046 04:42:35.021792  alsa_pcm-test_default_time7_LCALTA_3_0_CAPTURE skip
 3047 04:42:35.026762  alsa_pcm-test_default_time1_LCALTA_2_0_PLAYBACK skip
 3048 04:42:35.032334  alsa_pcm-test_default_time2_LCALTA_2_0_PLAYBACK skip
 3049 04:42:35.037897  alsa_pcm-test_default_time3_LCALTA_2_0_PLAYBACK skip
 3050 04:42:35.043412  alsa_pcm-test_default_time4_LCALTA_2_0_PLAYBACK skip
 3051 04:42:35.049075  alsa_pcm-test_default_time5_LCALTA_2_0_PLAYBACK skip
 3052 04:42:35.054549  alsa_pcm-test_default_time6_LCALTA_2_0_PLAYBACK skip
 3053 04:42:35.055084  alsa_pcm-test_default_time7_LCALTA_2_0_PLAYBACK skip
 3054 04:42:35.060095  alsa_pcm-test_default_time1_LCALTA_1_0_PLAYBACK skip
 3055 04:42:35.065587  alsa_pcm-test_default_time2_LCALTA_1_0_PLAYBACK skip
 3056 04:42:35.071123  alsa_pcm-test_default_time3_LCALTA_1_0_PLAYBACK skip
 3057 04:42:35.076672  alsa_pcm-test_default_time4_LCALTA_1_0_PLAYBACK skip
 3058 04:42:35.082211  alsa_pcm-test_default_time5_LCALTA_1_0_PLAYBACK skip
 3059 04:42:35.082752  alsa_pcm-test_default_time6_LCALTA_1_0_PLAYBACK skip
 3060 04:42:35.087762  alsa_pcm-test_default_time7_LCALTA_1_0_PLAYBACK skip
 3061 04:42:35.093311  alsa_pcm-test_default_time1_LCALTA_0_0_PLAYBACK skip
 3062 04:42:35.098983  alsa_pcm-test_default_time2_LCALTA_0_0_PLAYBACK skip
 3063 04:42:35.104480  alsa_pcm-test_default_time3_LCALTA_0_0_PLAYBACK skip
 3064 04:42:35.110127  alsa_pcm-test_default_time4_LCALTA_0_0_PLAYBACK skip
 3065 04:42:35.110686  alsa_pcm-test_default_time5_LCALTA_0_0_PLAYBACK skip
 3066 04:42:35.115526  alsa_pcm-test_default_time6_LCALTA_0_0_PLAYBACK skip
 3067 04:42:35.121111  alsa_pcm-test_default_time7_LCALTA_0_0_PLAYBACK skip
 3068 04:42:35.121640  alsa_pcm-test pass
 3069 04:42:35.132255  alsa_test-pcmtest-driver_pcmtest_playback_Can_t_read_patterns_Probably_module_isn_t_loaded skip
 3070 04:42:35.137677  alsa_test-pcmtest-driver_pcmtest_capture_Can_t_read_patterns_Probably_module_isn_t_loaded skip
 3071 04:42:35.148813  alsa_test-pcmtest-driver_pcmtest_ni_capture_Can_t_read_patterns_Probably_module_isn_t_loaded skip
 3072 04:42:35.159912  alsa_test-pcmtest-driver_pcmtest_ni_playback_Can_t_read_patterns_Probably_module_isn_t_loaded skip
 3073 04:42:35.165445  alsa_test-pcmtest-driver_pcmtest_reset_ioctl_Can_t_read_patterns_Probably_module_isn_t_loaded skip
 3074 04:42:35.171070  alsa_test-pcmtest-driver pass
 3075 04:42:35.171701  alsa_utimer-test_global_wrong_timers_test pass
 3076 04:42:35.176565  alsa_utimer-test_timer_f_utimer fail
 3077 04:42:35.177162  alsa_utimer-test fail
 3078 04:42:35.182172  + ../../utils/send-to-lava.sh ./output/result.txt
 3079 04:42:35.187647  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-alsa RESULT=pass>
 3080 04:42:35.189343  Received signal: <TESTCASE> TEST_CASE_ID=shardfile-alsa RESULT=pass
 3082 04:42:35.193194  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_60 RESULT=pass>
 3083 04:42:35.194528  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_60 RESULT=pass
 3085 04:42:35.205080  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_60 RESULT=pass>
 3086 04:42:35.205948  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_60 RESULT=pass
 3088 04:42:35.211539  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_60 RESULT=pass>
 3089 04:42:35.212347  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_60 RESULT=pass
 3091 04:42:35.260247  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_60 RESULT=pass>
 3092 04:42:35.261132  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_60 RESULT=pass
 3094 04:42:35.310088  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_60 RESULT=pass>
 3095 04:42:35.311556  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_60 RESULT=pass
 3097 04:42:35.363045  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_60 RESULT=pass>
 3098 04:42:35.363925  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_60 RESULT=pass
 3100 04:42:35.408452  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_60 RESULT=pass>
 3101 04:42:35.409334  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_60 RESULT=pass
 3103 04:42:35.451867  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_59 RESULT=pass>
 3104 04:42:35.452800  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_59 RESULT=pass
 3106 04:42:35.495166  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_59 RESULT=pass>
 3107 04:42:35.496063  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_59 RESULT=pass
 3109 04:42:35.538909  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_59 RESULT=pass>
 3110 04:42:35.539808  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_59 RESULT=pass
 3112 04:42:35.590966  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_59 RESULT=pass>
 3113 04:42:35.591876  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_59 RESULT=pass
 3115 04:42:35.634679  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_59 RESULT=pass>
 3116 04:42:35.635566  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_59 RESULT=pass
 3118 04:42:35.697988  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_59 RESULT=pass>
 3119 04:42:35.698876  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_59 RESULT=pass
 3121 04:42:35.747301  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_59 RESULT=pass>
 3122 04:42:35.748189  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_59 RESULT=pass
 3124 04:42:35.804976  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_58 RESULT=pass>
 3125 04:42:35.805879  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_58 RESULT=pass
 3127 04:42:35.850712  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_58 RESULT=pass>
 3128 04:42:35.851591  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_58 RESULT=pass
 3130 04:42:35.903238  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_58 RESULT=pass>
 3131 04:42:35.904110  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_58 RESULT=pass
 3133 04:42:35.954972  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_58 RESULT=pass>
 3134 04:42:35.955861  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_58 RESULT=pass
 3136 04:42:35.997433  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_58 RESULT=pass>
 3137 04:42:35.998282  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_58 RESULT=pass
 3139 04:42:36.046039  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_58 RESULT=pass>
 3140 04:42:36.046923  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_58 RESULT=pass
 3142 04:42:36.089964  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_58 RESULT=pass>
 3143 04:42:36.090834  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_58 RESULT=pass
 3145 04:42:36.133950  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_57 RESULT=pass>
 3146 04:42:36.134934  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_57 RESULT=pass
 3148 04:42:36.184173  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_57 RESULT=pass>
 3149 04:42:36.185145  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_57 RESULT=pass
 3151 04:42:36.233107  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_57 RESULT=pass>
 3152 04:42:36.233964  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_57 RESULT=pass
 3154 04:42:36.289336  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_57 RESULT=pass>
 3155 04:42:36.290213  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_57 RESULT=pass
 3157 04:42:36.337822  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_57 RESULT=pass>
 3158 04:42:36.338681  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_57 RESULT=pass
 3160 04:42:36.385194  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_57 RESULT=pass>
 3161 04:42:36.386114  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_57 RESULT=pass
 3163 04:42:36.435526  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_57 RESULT=pass>
 3164 04:42:36.436427  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_57 RESULT=pass
 3166 04:42:36.486377  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_56 RESULT=pass>
 3167 04:42:36.487186  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_56 RESULT=pass
 3169 04:42:36.530930  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_56 RESULT=pass>
 3170 04:42:36.531757  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_56 RESULT=pass
 3172 04:42:36.582268  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_56 RESULT=pass>
 3173 04:42:36.583098  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_56 RESULT=pass
 3175 04:42:36.625181  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_56 RESULT=pass>
 3176 04:42:36.626017  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_56 RESULT=pass
 3178 04:42:36.670127  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_56 RESULT=pass>
 3179 04:42:36.670972  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_56 RESULT=pass
 3181 04:42:36.716228  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_56 RESULT=pass>
 3182 04:42:36.717060  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_56 RESULT=pass
 3184 04:42:36.759269  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_56 RESULT=pass>
 3185 04:42:36.760094  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_56 RESULT=pass
 3187 04:42:36.804501  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_55 RESULT=pass>
 3188 04:42:36.805340  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_55 RESULT=pass
 3190 04:42:36.849825  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_55 RESULT=pass>
 3191 04:42:36.850669  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_55 RESULT=pass
 3193 04:42:36.894400  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_55 RESULT=pass>
 3194 04:42:36.895227  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_55 RESULT=pass
 3196 04:42:36.940204  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_55 RESULT=pass>
 3197 04:42:36.941040  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_55 RESULT=pass
 3199 04:42:36.983583  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_55 RESULT=pass>
 3200 04:42:36.984416  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_55 RESULT=pass
 3202 04:42:37.028991  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_55 RESULT=pass>
 3203 04:42:37.029827  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_55 RESULT=pass
 3205 04:42:37.074589  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_55 RESULT=pass>
 3206 04:42:37.075444  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_55 RESULT=pass
 3208 04:42:37.121513  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_54 RESULT=pass>
 3209 04:42:37.122344  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_54 RESULT=pass
 3211 04:42:37.171616  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_54 RESULT=pass>
 3212 04:42:37.172473  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_54 RESULT=pass
 3214 04:42:37.224575  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_54 RESULT=pass>
 3215 04:42:37.225366  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_54 RESULT=pass
 3217 04:42:37.269658  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_54 RESULT=pass>
 3218 04:42:37.270452  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_54 RESULT=pass
 3220 04:42:37.314395  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_54 RESULT=pass>
 3221 04:42:37.315197  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_54 RESULT=pass
 3223 04:42:37.359344  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_54 RESULT=pass>
 3224 04:42:37.360150  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_54 RESULT=pass
 3226 04:42:37.401561  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_54 RESULT=pass>
 3227 04:42:37.402370  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_54 RESULT=pass
 3229 04:42:37.446890  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_53 RESULT=pass>
 3230 04:42:37.447695  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_53 RESULT=pass
 3232 04:42:37.491713  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_53 RESULT=pass>
 3233 04:42:37.492562  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_53 RESULT=pass
 3235 04:42:37.540117  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_53 RESULT=pass>
 3236 04:42:37.540940  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_53 RESULT=pass
 3238 04:42:37.589769  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_53 RESULT=pass>
 3239 04:42:37.590570  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_53 RESULT=pass
 3241 04:42:37.641674  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_53 RESULT=pass>
 3242 04:42:37.642479  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_53 RESULT=pass
 3244 04:42:37.692220  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_53 RESULT=pass>
 3245 04:42:37.693035  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_53 RESULT=pass
 3247 04:42:37.735166  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_53 RESULT=pass>
 3248 04:42:37.735974  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_53 RESULT=pass
 3250 04:42:37.778351  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_52 RESULT=pass>
 3251 04:42:37.779171  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_52 RESULT=pass
 3253 04:42:37.823554  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_52 RESULT=pass>
 3254 04:42:37.824392  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_52 RESULT=pass
 3256 04:42:37.874973  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_52 RESULT=pass>
 3257 04:42:37.875787  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_52 RESULT=pass
 3259 04:42:37.924760  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_52 RESULT=pass>
 3260 04:42:37.925662  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_52 RESULT=pass
 3262 04:42:37.976954  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_52 RESULT=pass>
 3263 04:42:37.977769  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_52 RESULT=pass
 3265 04:42:38.028256  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_52 RESULT=pass>
 3266 04:42:38.029053  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_52 RESULT=pass
 3268 04:42:38.088353  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_52 RESULT=pass>
 3269 04:42:38.089159  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_52 RESULT=pass
 3271 04:42:38.131136  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_51 RESULT=pass>
 3272 04:42:38.131948  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_51 RESULT=pass
 3274 04:42:38.180911  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_51 RESULT=pass>
 3275 04:42:38.181690  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_51 RESULT=pass
 3277 04:42:38.234083  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_51 RESULT=pass>
 3278 04:42:38.234870  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_51 RESULT=pass
 3280 04:42:38.278914  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_51 RESULT=pass>
 3281 04:42:38.279686  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_51 RESULT=pass
 3283 04:42:38.323467  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_51 RESULT=pass>
 3284 04:42:38.324267  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_51 RESULT=pass
 3286 04:42:38.370406  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_51 RESULT=pass>
 3287 04:42:38.371181  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_51 RESULT=pass
 3289 04:42:38.422027  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_51 RESULT=pass>
 3290 04:42:38.422804  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_51 RESULT=pass
 3292 04:42:38.470738  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_50 RESULT=pass>
 3293 04:42:38.471509  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_50 RESULT=pass
 3295 04:42:38.525985  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_50 RESULT=pass>
 3296 04:42:38.526755  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_50 RESULT=pass
 3298 04:42:38.578566  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_50 RESULT=pass>
 3299 04:42:38.579340  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_50 RESULT=pass
 3301 04:42:38.622114  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_50 RESULT=pass>
 3302 04:42:38.622876  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_50 RESULT=pass
 3304 04:42:38.675874  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_50 RESULT=pass>
 3305 04:42:38.676669  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_50 RESULT=pass
 3307 04:42:38.738055  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_50 RESULT=pass>
 3308 04:42:38.738836  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_50 RESULT=pass
 3310 04:42:38.785319  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_50 RESULT=pass>
 3311 04:42:38.786077  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_50 RESULT=pass
 3313 04:42:38.837791  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_49 RESULT=pass>
 3314 04:42:38.838553  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_49 RESULT=pass
 3316 04:42:38.898320  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_49 RESULT=pass>
 3317 04:42:38.899081  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_49 RESULT=pass
 3319 04:42:38.948719  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_49 RESULT=pass>
 3320 04:42:38.949508  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_49 RESULT=pass
 3322 04:42:38.993378  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_49 RESULT=pass>
 3323 04:42:38.994150  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_49 RESULT=pass
 3325 04:42:39.039518  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_49 RESULT=pass>
 3326 04:42:39.040327  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_49 RESULT=pass
 3328 04:42:39.083648  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_49 RESULT=pass>
 3329 04:42:39.084435  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_49 RESULT=pass
 3331 04:42:39.134583  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_49 RESULT=pass>
 3332 04:42:39.135351  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_49 RESULT=pass
 3334 04:42:39.185037  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_48 RESULT=pass>
 3335 04:42:39.185810  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_48 RESULT=pass
 3337 04:42:39.228665  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_48 RESULT=pass>
 3338 04:42:39.229434  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_48 RESULT=pass
 3340 04:42:39.277736  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_48 RESULT=pass>
 3341 04:42:39.278501  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_48 RESULT=pass
 3343 04:42:39.326164  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_48 RESULT=pass>
 3344 04:42:39.326953  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_48 RESULT=pass
 3346 04:42:39.372187  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_48 RESULT=pass>
 3347 04:42:39.372954  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_48 RESULT=pass
 3349 04:42:39.425019  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_48 RESULT=pass>
 3350 04:42:39.425787  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_48 RESULT=pass
 3352 04:42:39.478224  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_48 RESULT=pass>
 3353 04:42:39.478980  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_48 RESULT=pass
 3355 04:42:39.528780  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_47 RESULT=pass>
 3356 04:42:39.529535  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_47 RESULT=pass
 3358 04:42:39.580961  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_47 RESULT=pass>
 3359 04:42:39.581736  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_47 RESULT=pass
 3361 04:42:39.639965  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_47 RESULT=pass>
 3362 04:42:39.640760  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_47 RESULT=pass
 3364 04:42:39.689293  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_47 RESULT=pass>
 3365 04:42:39.690063  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_47 RESULT=pass
 3367 04:42:39.738193  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_47 RESULT=pass>
 3368 04:42:39.738955  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_47 RESULT=pass
 3370 04:42:39.791770  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_47 RESULT=pass>
 3371 04:42:39.792561  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_47 RESULT=pass
 3373 04:42:39.840217  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_47 RESULT=pass>
 3374 04:42:39.840965  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_47 RESULT=pass
 3376 04:42:39.885812  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_46 RESULT=pass>
 3377 04:42:39.886569  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_46 RESULT=pass
 3379 04:42:39.934018  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_46 RESULT=pass>
 3380 04:42:39.934782  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_46 RESULT=pass
 3382 04:42:39.986659  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_46 RESULT=pass>
 3383 04:42:39.987437  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_46 RESULT=pass
 3385 04:42:40.037760  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_46 RESULT=pass>
 3386 04:42:40.038518  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_46 RESULT=pass
 3388 04:42:40.090120  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_46 RESULT=pass>
 3389 04:42:40.090866  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_46 RESULT=pass
 3391 04:42:40.140885  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_46 RESULT=pass>
 3392 04:42:40.141649  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_46 RESULT=pass
 3394 04:42:40.192402  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_46 RESULT=pass>
 3395 04:42:40.193160  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_46 RESULT=pass
 3397 04:42:40.242587  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_45 RESULT=pass>
 3398 04:42:40.243344  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_45 RESULT=pass
 3400 04:42:40.291838  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_45 RESULT=pass>
 3401 04:42:40.292642  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_45 RESULT=pass
 3403 04:42:40.343904  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_45 RESULT=pass>
 3404 04:42:40.344698  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_45 RESULT=pass
 3406 04:42:40.394607  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_45 RESULT=pass>
 3407 04:42:40.395375  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_45 RESULT=pass
 3409 04:42:40.448381  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_45 RESULT=pass>
 3410 04:42:40.449168  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_45 RESULT=pass
 3412 04:42:40.500440  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_45 RESULT=pass>
 3413 04:42:40.501234  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_45 RESULT=pass
 3415 04:42:40.555755  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_45 RESULT=pass>
 3416 04:42:40.556612  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_45 RESULT=pass
 3418 04:42:40.604464  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_44 RESULT=pass>
 3419 04:42:40.605267  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_44 RESULT=pass
 3421 04:42:40.660179  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_44 RESULT=pass>
 3422 04:42:40.660971  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_44 RESULT=pass
 3424 04:42:40.714461  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_44 RESULT=pass>
 3425 04:42:40.715249  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_44 RESULT=pass
 3427 04:42:40.768050  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_44 RESULT=pass>
 3428 04:42:40.768829  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_44 RESULT=pass
 3430 04:42:40.950142  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_44 RESULT=pass>
 3431 04:42:40.950999  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_44 RESULT=pass
 3433 04:42:41.004621  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_44 RESULT=pass>
 3434 04:42:41.005375  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_44 RESULT=pass
 3436 04:42:41.055354  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_44 RESULT=pass>
 3437 04:42:41.056109  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_44 RESULT=pass
 3439 04:42:41.113563  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_43 RESULT=pass>
 3440 04:42:41.114352  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_43 RESULT=pass
 3442 04:42:41.162549  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_43 RESULT=pass>
 3443 04:42:41.163279  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_43 RESULT=pass
 3445 04:42:41.206401  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_43 RESULT=pass>
 3446 04:42:41.207135  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_43 RESULT=pass
 3448 04:42:41.253918  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_43 RESULT=pass>
 3449 04:42:41.254653  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_43 RESULT=pass
 3451 04:42:41.305294  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_43 RESULT=pass>
 3452 04:42:41.306048  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_43 RESULT=pass
 3454 04:42:41.351447  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_43 RESULT=pass>
 3455 04:42:41.352178  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_43 RESULT=pass
 3457 04:42:41.409123  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_43 RESULT=pass>
 3458 04:42:41.409925  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_43 RESULT=pass
 3460 04:42:41.466373  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_42 RESULT=pass>
 3461 04:42:41.467148  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_42 RESULT=pass
 3463 04:42:41.518756  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_42 RESULT=pass>
 3464 04:42:41.519514  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_42 RESULT=pass
 3466 04:42:41.571461  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_42 RESULT=pass>
 3467 04:42:41.572281  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_42 RESULT=pass
 3469 04:42:41.621298  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_42 RESULT=pass>
 3470 04:42:41.622092  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_42 RESULT=pass
 3472 04:42:41.670477  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_42 RESULT=pass>
 3473 04:42:41.671251  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_42 RESULT=pass
 3475 04:42:41.716407  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_42 RESULT=pass>
 3476 04:42:41.717183  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_42 RESULT=pass
 3478 04:42:41.770683  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_42 RESULT=pass>
 3479 04:42:41.771477  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_42 RESULT=pass
 3481 04:42:41.821403  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_41 RESULT=pass>
 3482 04:42:41.822180  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_41 RESULT=pass
 3484 04:42:41.865112  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_41 RESULT=pass>
 3485 04:42:41.865917  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_41 RESULT=pass
 3487 04:42:41.917736  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_41 RESULT=pass>
 3488 04:42:41.918553  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_41 RESULT=pass
 3490 04:42:41.976356  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_41 RESULT=pass>
 3491 04:42:41.977146  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_41 RESULT=pass
 3493 04:42:42.032545  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_41 RESULT=pass>
 3494 04:42:42.033356  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_41 RESULT=pass
 3496 04:42:42.092325  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_41 RESULT=pass>
 3497 04:42:42.093107  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_41 RESULT=pass
 3499 04:42:42.136243  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_41 RESULT=pass>
 3500 04:42:42.137062  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_41 RESULT=pass
 3502 04:42:42.189064  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_40 RESULT=pass>
 3503 04:42:42.189905  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_40 RESULT=pass
 3505 04:42:42.240458  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_40 RESULT=pass>
 3506 04:42:42.241299  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_40 RESULT=pass
 3508 04:42:42.289908  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_40 RESULT=pass>
 3509 04:42:42.290778  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_40 RESULT=pass
 3511 04:42:42.347591  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_40 RESULT=pass>
 3512 04:42:42.348497  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_40 RESULT=pass
 3514 04:42:42.404983  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_40 RESULT=pass>
 3515 04:42:42.405796  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_40 RESULT=pass
 3517 04:42:42.461385  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_40 RESULT=pass>
 3518 04:42:42.462260  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_40 RESULT=pass
 3520 04:42:42.507188  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_40 RESULT=pass>
 3521 04:42:42.508061  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_40 RESULT=pass
 3523 04:42:42.551359  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_39 RESULT=pass>
 3524 04:42:42.552169  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_39 RESULT=pass
 3526 04:42:42.602879  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_39 RESULT=pass>
 3527 04:42:42.603691  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_39 RESULT=pass
 3529 04:42:42.655686  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_39 RESULT=pass>
 3530 04:42:42.656587  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_39 RESULT=pass
 3532 04:42:42.710282  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_39 RESULT=pass>
 3533 04:42:42.711103  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_39 RESULT=pass
 3535 04:42:42.766941  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_39 RESULT=pass>
 3536 04:42:42.767763  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_39 RESULT=pass
 3538 04:42:42.820131  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_39 RESULT=pass>
 3539 04:42:42.820953  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_39 RESULT=pass
 3541 04:42:42.866428  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_39 RESULT=pass>
 3542 04:42:42.867247  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_39 RESULT=pass
 3544 04:42:42.911156  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_38 RESULT=pass>
 3545 04:42:42.911928  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_38 RESULT=pass
 3547 04:42:42.960368  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_38 RESULT=pass>
 3548 04:42:42.961126  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_38 RESULT=pass
 3550 04:42:43.008242  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_38 RESULT=pass>
 3551 04:42:43.008982  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_38 RESULT=pass
 3553 04:42:43.058015  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_38 RESULT=pass>
 3554 04:42:43.058740  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_38 RESULT=pass
 3556 04:42:43.107499  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_38 RESULT=pass>
 3557 04:42:43.108265  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_38 RESULT=pass
 3559 04:42:43.159129  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_38 RESULT=pass>
 3560 04:42:43.159868  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_38 RESULT=pass
 3562 04:42:43.211616  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_38 RESULT=pass>
 3563 04:42:43.212427  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_38 RESULT=pass
 3565 04:42:43.256291  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_37 RESULT=pass>
 3566 04:42:43.257039  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_37 RESULT=pass
 3568 04:42:43.301562  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_37 RESULT=pass>
 3569 04:42:43.302300  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_37 RESULT=pass
 3571 04:42:43.359936  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_37 RESULT=pass>
 3572 04:42:43.360734  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_37 RESULT=pass
 3574 04:42:43.413160  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_37 RESULT=pass>
 3575 04:42:43.413961  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_37 RESULT=pass
 3577 04:42:43.459032  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_37 RESULT=pass>
 3578 04:42:43.459843  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_37 RESULT=pass
 3580 04:42:43.511579  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_37 RESULT=pass>
 3581 04:42:43.512443  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_37 RESULT=pass
 3583 04:42:43.556790  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_37 RESULT=pass>
 3584 04:42:43.557589  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_37 RESULT=pass
 3586 04:42:43.615560  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_36 RESULT=pass>
 3587 04:42:43.616395  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_36 RESULT=pass
 3589 04:42:43.664345  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_36 RESULT=pass>
 3590 04:42:43.665133  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_36 RESULT=pass
 3592 04:42:43.712366  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_36 RESULT=pass>
 3593 04:42:43.713164  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_36 RESULT=pass
 3595 04:42:43.758092  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_36 RESULT=pass>
 3596 04:42:43.759022  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_36 RESULT=pass
 3598 04:42:43.806440  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_36 RESULT=pass>
 3599 04:42:43.807299  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_36 RESULT=pass
 3601 04:42:43.862303  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_36 RESULT=pass>
 3602 04:42:43.863146  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_36 RESULT=pass
 3604 04:42:43.907664  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_36 RESULT=pass>
 3605 04:42:43.908518  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_36 RESULT=pass
 3607 04:42:43.960430  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_35 RESULT=pass>
 3608 04:42:43.961228  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_35 RESULT=pass
 3610 04:42:44.004772  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_35 RESULT=pass>
 3611 04:42:44.005558  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_35 RESULT=pass
 3613 04:42:44.065334  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_35 RESULT=pass>
 3614 04:42:44.066295  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_35 RESULT=pass
 3616 04:42:44.122187  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_35 RESULT=pass>
 3617 04:42:44.122855  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_35 RESULT=pass
 3619 04:42:44.172068  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_35 RESULT=pass>
 3620 04:42:44.172942  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_35 RESULT=pass
 3622 04:42:44.217708  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_35 RESULT=pass>
 3623 04:42:44.218912  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_35 RESULT=pass
 3625 04:42:44.274026  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_35 RESULT=pass>
 3626 04:42:44.274912  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_35 RESULT=pass
 3628 04:42:44.324872  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_34 RESULT=pass>
 3629 04:42:44.325477  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_34 RESULT=pass
 3631 04:42:44.376634  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_34 RESULT=pass>
 3632 04:42:44.377498  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_34 RESULT=pass
 3634 04:42:44.424995  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_34 RESULT=pass>
 3635 04:42:44.425862  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_34 RESULT=pass
 3637 04:42:44.476594  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_34 RESULT=pass>
 3638 04:42:44.477416  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_34 RESULT=pass
 3640 04:42:44.531501  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_34 RESULT=pass>
 3641 04:42:44.532334  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_34 RESULT=pass
 3643 04:42:44.589315  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_34 RESULT=pass>
 3644 04:42:44.590168  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_34 RESULT=pass
 3646 04:42:44.644096  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_34 RESULT=pass>
 3647 04:42:44.644915  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_34 RESULT=pass
 3649 04:42:44.701168  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_33 RESULT=pass>
 3650 04:42:44.702057  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_33 RESULT=pass
 3652 04:42:44.744283  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_33 RESULT=pass>
 3653 04:42:44.745268  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_33 RESULT=pass
 3655 04:42:44.795598  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_33 RESULT=pass>
 3656 04:42:44.796521  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_33 RESULT=pass
 3658 04:42:44.855083  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_33 RESULT=pass>
 3659 04:42:44.855974  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_33 RESULT=pass
 3661 04:42:44.906789  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_33 RESULT=pass>
 3662 04:42:44.907607  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_33 RESULT=pass
 3664 04:42:44.958852  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_33 RESULT=pass>
 3665 04:42:44.959650  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_33 RESULT=pass
 3667 04:42:45.009343  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_33 RESULT=pass>
 3668 04:42:45.010147  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_33 RESULT=pass
 3670 04:42:45.059011  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_32 RESULT=pass>
 3671 04:42:45.059834  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_32 RESULT=pass
 3673 04:42:45.113396  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_32 RESULT=pass>
 3674 04:42:45.114184  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_32 RESULT=pass
 3676 04:42:45.165586  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_32 RESULT=pass>
 3677 04:42:45.166452  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_32 RESULT=pass
 3679 04:42:45.210708  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_32 RESULT=pass>
 3680 04:42:45.211550  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_32 RESULT=pass
 3682 04:42:45.256666  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_32 RESULT=pass>
 3683 04:42:45.257533  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_32 RESULT=pass
 3685 04:42:45.302915  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_32 RESULT=pass>
 3686 04:42:45.303750  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_32 RESULT=pass
 3688 04:42:45.358256  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_32 RESULT=pass>
 3689 04:42:45.359107  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_32 RESULT=pass
 3691 04:42:45.404265  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_31 RESULT=pass>
 3692 04:42:45.405107  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_31 RESULT=pass
 3694 04:42:45.452167  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_31 RESULT=pass>
 3695 04:42:45.452981  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_31 RESULT=pass
 3697 04:42:45.502298  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_31 RESULT=pass>
 3698 04:42:45.503089  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_31 RESULT=pass
 3700 04:42:45.554036  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_31 RESULT=pass>
 3701 04:42:45.554847  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_31 RESULT=pass
 3703 04:42:45.607715  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_31 RESULT=pass>
 3704 04:42:45.608600  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_31 RESULT=pass
 3706 04:42:45.667004  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_31 RESULT=pass>
 3707 04:42:45.667788  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_31 RESULT=pass
 3709 04:42:45.723239  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_31 RESULT=pass>
 3710 04:42:45.724065  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_31 RESULT=pass
 3712 04:42:45.770574  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_30 RESULT=pass>
 3713 04:42:45.771373  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_30 RESULT=pass
 3715 04:42:45.818295  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_30 RESULT=pass>
 3716 04:42:45.819113  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_30 RESULT=pass
 3718 04:42:45.869880  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_30 RESULT=pass>
 3719 04:42:45.870696  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_30 RESULT=pass
 3721 04:42:45.913591  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_30 RESULT=pass>
 3722 04:42:45.914357  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_30 RESULT=pass
 3724 04:42:45.961984  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_30 RESULT=pass>
 3725 04:42:45.962765  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_30 RESULT=pass
 3727 04:42:46.008238  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_30 RESULT=pass>
 3728 04:42:46.009011  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_30 RESULT=pass
 3730 04:42:46.060822  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_30 RESULT=pass>
 3731 04:42:46.061584  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_30 RESULT=pass
 3733 04:42:46.111430  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_29 RESULT=pass>
 3734 04:42:46.112297  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_29 RESULT=pass
 3736 04:42:46.164489  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_29 RESULT=pass>
 3737 04:42:46.165269  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_29 RESULT=pass
 3739 04:42:46.218117  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_29 RESULT=pass>
 3740 04:42:46.218898  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_29 RESULT=pass
 3742 04:42:46.263815  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_29 RESULT=pass>
 3743 04:42:46.264641  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_29 RESULT=pass
 3745 04:42:46.315537  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_29 RESULT=pass>
 3746 04:42:46.316336  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_29 RESULT=pass
 3748 04:42:46.370274  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_29 RESULT=pass>
 3749 04:42:46.371099  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_29 RESULT=pass
 3751 04:42:46.414806  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_29 RESULT=pass>
 3752 04:42:46.415630  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_29 RESULT=pass
 3754 04:42:46.463667  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_28 RESULT=pass>
 3755 04:42:46.464532  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_28 RESULT=pass
 3757 04:42:46.522445  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_28 RESULT=pass>
 3758 04:42:46.523502  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_28 RESULT=pass
 3760 04:42:46.572892  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_28 RESULT=pass>
 3761 04:42:46.573982  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_28 RESULT=pass
 3763 04:42:46.627082  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_28 RESULT=pass>
 3764 04:42:46.628051  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_28 RESULT=pass
 3766 04:42:46.673420  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_28 RESULT=pass>
 3767 04:42:46.674294  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_28 RESULT=pass
 3769 04:42:46.725606  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_28 RESULT=pass>
 3770 04:42:46.726448  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_28 RESULT=pass
 3772 04:42:46.779006  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_28 RESULT=pass>
 3773 04:42:46.779846  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_28 RESULT=pass
 3775 04:42:46.827658  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_27 RESULT=pass>
 3776 04:42:46.828592  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_27 RESULT=pass
 3778 04:42:46.880775  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_27 RESULT=pass>
 3779 04:42:46.881640  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_27 RESULT=pass
 3781 04:42:46.930322  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_27 RESULT=pass>
 3782 04:42:46.931185  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_27 RESULT=pass
 3784 04:42:46.984981  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_27 RESULT=pass>
 3785 04:42:46.985819  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_27 RESULT=pass
 3787 04:42:47.036492  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_27 RESULT=pass>
 3788 04:42:47.037355  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_27 RESULT=pass
 3790 04:42:47.082504  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_27 RESULT=pass>
 3791 04:42:47.083310  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_27 RESULT=pass
 3793 04:42:47.128199  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_27 RESULT=pass>
 3794 04:42:47.129137  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_27 RESULT=pass
 3796 04:42:47.180289  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_26 RESULT=pass>
 3797 04:42:47.181180  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_26 RESULT=pass
 3799 04:42:47.232208  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_26 RESULT=pass>
 3800 04:42:47.233117  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_26 RESULT=pass
 3802 04:42:47.284768  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_26 RESULT=skip>
 3803 04:42:47.285611  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_26 RESULT=skip
 3805 04:42:47.331437  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_26 RESULT=skip>
 3806 04:42:47.332403  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_26 RESULT=skip
 3808 04:42:47.384050  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_26 RESULT=skip>
 3809 04:42:47.384965  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_26 RESULT=skip
 3811 04:42:47.438156  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_26 RESULT=pass>
 3812 04:42:47.439061  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_26 RESULT=pass
 3814 04:42:47.483185  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_26 RESULT=pass>
 3815 04:42:47.484085  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_26 RESULT=pass
 3817 04:42:47.540147  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_25 RESULT=pass>
 3818 04:42:47.541067  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_25 RESULT=pass
 3820 04:42:47.585216  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_25 RESULT=pass>
 3821 04:42:47.586142  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_25 RESULT=pass
 3823 04:42:47.646823  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_25 RESULT=pass>
 3824 04:42:47.647707  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_25 RESULT=pass
 3826 04:42:47.703051  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_25 RESULT=skip>
 3827 04:42:47.704000  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_25 RESULT=skip
 3829 04:42:47.753492  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_25 RESULT=skip>
 3830 04:42:47.754407  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_25 RESULT=skip
 3832 04:42:47.809608  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_25 RESULT=pass>
 3833 04:42:47.810534  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_25 RESULT=pass
 3835 04:42:47.862777  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_25 RESULT=pass>
 3836 04:42:47.863627  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_25 RESULT=pass
 3838 04:42:47.915347  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_24 RESULT=pass>
 3839 04:42:47.916207  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_24 RESULT=pass
 3841 04:42:47.965444  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_24 RESULT=pass>
 3842 04:42:47.966295  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_24 RESULT=pass
 3844 04:42:48.023559  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_24 RESULT=skip>
 3845 04:42:48.024507  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_24 RESULT=skip
 3847 04:42:48.069302  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_24 RESULT=skip>
 3848 04:42:48.070098  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_24 RESULT=skip
 3850 04:42:48.113493  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_24 RESULT=skip>
 3851 04:42:48.114336  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_24 RESULT=skip
 3853 04:42:48.171569  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_24 RESULT=pass>
 3854 04:42:48.172415  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_24 RESULT=pass
 3856 04:42:48.220087  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_24 RESULT=pass>
 3857 04:42:48.220946  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_24 RESULT=pass
 3859 04:42:48.277045  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_23 RESULT=pass>
 3860 04:42:48.277947  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_23 RESULT=pass
 3862 04:42:48.321670  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_23 RESULT=pass>
 3863 04:42:48.322589  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_23 RESULT=pass
 3865 04:42:48.367230  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_23 RESULT=skip>
 3866 04:42:48.368119  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_23 RESULT=skip
 3868 04:42:48.422423  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_23 RESULT=skip>
 3869 04:42:48.423282  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_23 RESULT=skip
 3871 04:42:48.467017  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_23 RESULT=skip>
 3872 04:42:48.467879  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_23 RESULT=skip
 3874 04:42:48.514797  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_23 RESULT=pass>
 3875 04:42:48.515635  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_23 RESULT=pass
 3877 04:42:48.568680  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_23 RESULT=pass>
 3878 04:42:48.569602  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_23 RESULT=pass
 3880 04:42:48.612277  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_22 RESULT=pass>
 3881 04:42:48.613105  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_22 RESULT=pass
 3883 04:42:48.659556  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_22 RESULT=pass>
 3884 04:42:48.660428  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_22 RESULT=pass
 3886 04:42:48.711713  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_22 RESULT=pass>
 3887 04:42:48.712568  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_22 RESULT=pass
 3889 04:42:48.761012  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_22 RESULT=pass>
 3890 04:42:48.761827  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_22 RESULT=pass
 3892 04:42:48.809714  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_22 RESULT=pass>
 3893 04:42:48.810504  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_22 RESULT=pass
 3895 04:42:48.866759  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_22 RESULT=pass>
 3896 04:42:48.867553  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_22 RESULT=pass
 3898 04:42:48.921085  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_22 RESULT=pass>
 3899 04:42:48.921914  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_22 RESULT=pass
 3901 04:42:48.973157  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_21 RESULT=pass>
 3902 04:42:48.973990  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_21 RESULT=pass
 3904 04:42:49.026265  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_21 RESULT=pass>
 3905 04:42:49.027102  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_21 RESULT=pass
 3907 04:42:49.079836  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_21 RESULT=pass>
 3908 04:42:49.080674  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_21 RESULT=pass
 3910 04:42:49.137923  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_21 RESULT=pass>
 3911 04:42:49.138736  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_21 RESULT=pass
 3913 04:42:49.186814  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_21 RESULT=pass>
 3914 04:42:49.187632  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_21 RESULT=pass
 3916 04:42:49.234637  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_21 RESULT=pass>
 3917 04:42:49.235450  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_21 RESULT=pass
 3919 04:42:49.287152  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_21 RESULT=pass>
 3920 04:42:49.287953  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_21 RESULT=pass
 3922 04:42:49.344445  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_20 RESULT=pass>
 3923 04:42:49.345260  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_20 RESULT=pass
 3925 04:42:49.392078  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_20 RESULT=pass>
 3926 04:42:49.392876  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_20 RESULT=pass
 3928 04:42:49.445100  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_20 RESULT=pass>
 3929 04:42:49.445905  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_20 RESULT=pass
 3931 04:42:49.497576  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_20 RESULT=pass>
 3932 04:42:49.498377  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_20 RESULT=pass
 3934 04:42:49.546944  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_20 RESULT=pass>
 3935 04:42:49.547621  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_20 RESULT=pass
 3937 04:42:49.603779  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_20 RESULT=pass>
 3938 04:42:49.604510  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_20 RESULT=pass
 3940 04:42:49.657627  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_20 RESULT=pass>
 3941 04:42:49.658356  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_20 RESULT=pass
 3943 04:42:49.704803  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_19 RESULT=pass>
 3944 04:42:49.705478  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_19 RESULT=pass
 3946 04:42:49.748646  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_19 RESULT=pass>
 3947 04:42:49.749332  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_19 RESULT=pass
 3949 04:42:49.794593  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_19 RESULT=pass>
 3950 04:42:49.795276  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_19 RESULT=pass
 3952 04:42:49.851322  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_19 RESULT=pass>
 3953 04:42:49.851957  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_19 RESULT=pass
 3955 04:42:49.896778  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_19 RESULT=pass>
 3956 04:42:49.897429  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_19 RESULT=pass
 3958 04:42:49.949955  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_19 RESULT=pass>
 3959 04:42:49.950576  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_19 RESULT=pass
 3961 04:42:50.003605  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_19 RESULT=pass>
 3962 04:42:50.004267  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_19 RESULT=pass
 3964 04:42:50.049090  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_18 RESULT=pass>
 3965 04:42:50.050032  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_18 RESULT=pass
 3967 04:42:50.099004  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_18 RESULT=pass>
 3968 04:42:50.100163  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_18 RESULT=pass
 3970 04:42:50.154122  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_18 RESULT=pass>
 3971 04:42:50.154955  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_18 RESULT=pass
 3973 04:42:50.207793  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_18 RESULT=pass>
 3974 04:42:50.208669  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_18 RESULT=pass
 3976 04:42:50.255078  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_18 RESULT=pass>
 3977 04:42:50.255906  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_18 RESULT=pass
 3979 04:42:50.300778  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_18 RESULT=pass>
 3980 04:42:50.301819  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_18 RESULT=pass
 3982 04:42:50.379817  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_18 RESULT=pass>
 3983 04:42:50.380829  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_18 RESULT=pass
 3985 04:42:50.427558  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_17 RESULT=pass>
 3986 04:42:50.428493  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_17 RESULT=pass
 3988 04:42:50.476076  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_17 RESULT=pass>
 3989 04:42:50.476974  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_17 RESULT=pass
 3991 04:42:50.525065  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_17 RESULT=pass>
 3992 04:42:50.525985  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_17 RESULT=pass
 3994 04:42:50.577005  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_17 RESULT=pass>
 3995 04:42:50.577919  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_17 RESULT=pass
 3997 04:42:50.620635  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_17 RESULT=pass>
 3998 04:42:50.621511  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_17 RESULT=pass
 4000 04:42:50.678198  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_17 RESULT=pass>
 4001 04:42:50.679069  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_17 RESULT=pass
 4003 04:42:50.730784  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_17 RESULT=pass>
 4004 04:42:50.731599  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_17 RESULT=pass
 4006 04:42:50.780599  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_16 RESULT=pass>
 4007 04:42:50.781506  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_16 RESULT=pass
 4009 04:42:50.834945  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_16 RESULT=pass>
 4010 04:42:50.835851  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_16 RESULT=pass
 4012 04:42:50.881696  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_16 RESULT=pass>
 4013 04:42:50.882584  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_16 RESULT=pass
 4015 04:42:50.926067  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_16 RESULT=pass>
 4016 04:42:50.927183  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_16 RESULT=pass
 4018 04:42:50.986051  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_16 RESULT=pass>
 4019 04:42:50.986750  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_16 RESULT=pass
 4021 04:42:51.030657  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_16 RESULT=pass>
 4022 04:42:51.031551  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_16 RESULT=pass
 4024 04:42:51.083556  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_16 RESULT=pass>
 4025 04:42:51.084380  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_16 RESULT=pass
 4027 04:42:51.127504  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_15 RESULT=pass>
 4028 04:42:51.128297  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_15 RESULT=pass
 4030 04:42:51.171958  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_15 RESULT=pass>
 4031 04:42:51.172850  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_15 RESULT=pass
 4033 04:42:51.217276  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_15 RESULT=pass>
 4034 04:42:51.218098  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_15 RESULT=pass
 4036 04:42:51.268692  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_15 RESULT=pass>
 4037 04:42:51.269501  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_15 RESULT=pass
 4039 04:42:51.322524  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_15 RESULT=pass>
 4040 04:42:51.323318  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_15 RESULT=pass
 4042 04:42:51.372847  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_15 RESULT=pass>
 4043 04:42:51.373605  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_15 RESULT=pass
 4045 04:42:51.416671  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_15 RESULT=pass>
 4046 04:42:51.417483  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_15 RESULT=pass
 4048 04:42:51.466733  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_14 RESULT=pass>
 4049 04:42:51.467490  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_14 RESULT=pass
 4051 04:42:51.511612  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_14 RESULT=pass>
 4052 04:42:51.512390  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_14 RESULT=pass
 4054 04:42:51.573695  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_14 RESULT=pass>
 4055 04:42:51.574455  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_14 RESULT=pass
 4057 04:42:51.622174  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_14 RESULT=pass>
 4058 04:42:51.622925  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_14 RESULT=pass
 4060 04:42:51.667670  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_14 RESULT=pass>
 4061 04:42:51.668468  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_14 RESULT=pass
 4063 04:42:51.720981  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_14 RESULT=pass>
 4064 04:42:51.721738  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_14 RESULT=pass
 4066 04:42:51.769218  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_14 RESULT=pass>
 4067 04:42:51.769967  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_14 RESULT=pass
 4069 04:42:51.826034  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_13 RESULT=pass>
 4070 04:42:51.826790  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_13 RESULT=pass
 4072 04:42:51.874798  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_13 RESULT=pass>
 4073 04:42:51.875575  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_13 RESULT=pass
 4075 04:42:51.918518  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_13 RESULT=pass>
 4076 04:42:51.919326  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_13 RESULT=pass
 4078 04:42:51.971205  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_13 RESULT=pass>
 4079 04:42:51.972025  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_13 RESULT=pass
 4081 04:42:52.020066  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_13 RESULT=pass>
 4082 04:42:52.020856  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_13 RESULT=pass
 4084 04:42:52.070564  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_13 RESULT=pass>
 4085 04:42:52.071339  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_13 RESULT=pass
 4087 04:42:52.129926  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_13 RESULT=pass>
 4088 04:42:52.130706  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_13 RESULT=pass
 4090 04:42:52.176391  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_12 RESULT=pass>
 4091 04:42:52.177173  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_12 RESULT=pass
 4093 04:42:52.231948  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_12 RESULT=pass>
 4094 04:42:52.232806  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_12 RESULT=pass
 4096 04:42:52.290357  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_12 RESULT=pass>
 4097 04:42:52.291137  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_12 RESULT=pass
 4099 04:42:52.336097  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_12 RESULT=pass>
 4100 04:42:52.336901  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_12 RESULT=pass
 4102 04:42:52.391025  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_12 RESULT=pass>
 4103 04:42:52.391860  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_12 RESULT=pass
 4105 04:42:52.445966  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_12 RESULT=pass>
 4106 04:42:52.446746  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_12 RESULT=pass
 4108 04:42:52.499560  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_12 RESULT=pass>
 4109 04:42:52.500386  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_12 RESULT=pass
 4111 04:42:52.556087  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_11 RESULT=pass>
 4112 04:42:52.556878  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_11 RESULT=pass
 4114 04:42:52.606281  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_11 RESULT=pass>
 4115 04:42:52.607057  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_11 RESULT=pass
 4117 04:42:52.665824  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_11 RESULT=pass>
 4118 04:42:52.666604  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_11 RESULT=pass
 4120 04:42:52.716425  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_11 RESULT=pass>
 4121 04:42:52.717225  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_11 RESULT=pass
 4123 04:42:52.771659  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_11 RESULT=pass>
 4124 04:42:52.772497  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_11 RESULT=pass
 4126 04:42:52.830546  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_11 RESULT=pass>
 4127 04:42:52.831359  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_11 RESULT=pass
 4129 04:42:52.891902  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_11 RESULT=pass>
 4130 04:42:52.892729  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_11 RESULT=pass
 4132 04:42:52.936258  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_10 RESULT=pass>
 4133 04:42:52.937026  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_10 RESULT=pass
 4135 04:42:52.993171  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_10 RESULT=pass>
 4136 04:42:52.993953  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_10 RESULT=pass
 4138 04:42:53.042983  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_10 RESULT=pass>
 4139 04:42:53.043766  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_10 RESULT=pass
 4141 04:42:53.093085  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_10 RESULT=pass>
 4142 04:42:53.093866  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_10 RESULT=pass
 4144 04:42:53.137842  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_10 RESULT=pass>
 4145 04:42:53.138617  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_10 RESULT=pass
 4147 04:42:53.193259  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_10 RESULT=pass>
 4148 04:42:53.194065  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_10 RESULT=pass
 4150 04:42:53.238431  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_10 RESULT=pass>
 4151 04:42:53.239219  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_10 RESULT=pass
 4153 04:42:53.296407  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_9 RESULT=pass>
 4154 04:42:53.297168  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_9 RESULT=pass
 4156 04:42:53.345877  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_9 RESULT=pass>
 4157 04:42:53.346615  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_9 RESULT=pass
 4159 04:42:53.396685  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_9 RESULT=pass>
 4160 04:42:53.397594  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_9 RESULT=pass
 4162 04:42:53.458022  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_9 RESULT=pass>
 4163 04:42:53.458777  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_9 RESULT=pass
 4165 04:42:53.510284  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_9 RESULT=pass>
 4166 04:42:53.511035  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_9 RESULT=pass
 4168 04:42:53.559540  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_9 RESULT=pass>
 4169 04:42:53.560314  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_9 RESULT=pass
 4171 04:42:53.612934  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_9 RESULT=pass>
 4172 04:42:53.613675  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_9 RESULT=pass
 4174 04:42:53.666859  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_8 RESULT=pass>
 4175 04:42:53.667603  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_8 RESULT=pass
 4177 04:42:53.715011  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_8 RESULT=pass>
 4178 04:42:53.715772  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_8 RESULT=pass
 4180 04:42:53.765277  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_8 RESULT=pass>
 4181 04:42:53.766037  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_8 RESULT=pass
 4183 04:42:53.815065  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_8 RESULT=pass>
 4184 04:42:53.815813  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_8 RESULT=pass
 4186 04:42:53.867684  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_8 RESULT=pass>
 4187 04:42:53.868496  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_8 RESULT=pass
 4189 04:42:53.914105  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_8 RESULT=pass>
 4190 04:42:53.914882  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_8 RESULT=pass
 4192 04:42:53.964348  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_8 RESULT=pass>
 4193 04:42:53.965217  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_8 RESULT=pass
 4195 04:42:54.016363  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_7 RESULT=pass>
 4196 04:42:54.017166  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_7 RESULT=pass
 4198 04:42:54.094603  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_7 RESULT=pass>
 4199 04:42:54.095517  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_7 RESULT=pass
 4201 04:42:54.145745  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_7 RESULT=pass>
 4202 04:42:54.146656  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_7 RESULT=pass
 4204 04:42:54.194958  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_7 RESULT=pass>
 4205 04:42:54.195849  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_7 RESULT=pass
 4207 04:42:54.246069  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_7 RESULT=pass>
 4208 04:42:54.247040  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_7 RESULT=pass
 4210 04:42:54.290738  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_7 RESULT=pass>
 4211 04:42:54.291632  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_7 RESULT=pass
 4213 04:42:54.341027  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_7 RESULT=pass>
 4214 04:42:54.342036  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_7 RESULT=pass
 4216 04:42:54.396859  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_6 RESULT=pass>
 4217 04:42:54.397750  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_6 RESULT=pass
 4219 04:42:54.439513  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_6 RESULT=pass>
 4220 04:42:54.440412  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_6 RESULT=pass
 4222 04:42:54.488905  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_6 RESULT=pass>
 4223 04:42:54.489782  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_6 RESULT=pass
 4225 04:42:54.541273  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_6 RESULT=pass>
 4226 04:42:54.542133  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_6 RESULT=pass
 4228 04:42:54.585911  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_6 RESULT=pass>
 4229 04:42:54.586772  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_6 RESULT=pass
 4231 04:42:54.641962  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_6 RESULT=pass>
 4232 04:42:54.642965  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_6 RESULT=pass
 4234 04:42:54.695662  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_6 RESULT=pass>
 4235 04:42:54.696418  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_6 RESULT=pass
 4237 04:42:54.749583  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_5 RESULT=pass>
 4238 04:42:54.750222  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_5 RESULT=pass
 4240 04:42:54.799879  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_5 RESULT=pass>
 4241 04:42:54.800710  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_5 RESULT=pass
 4243 04:42:54.854654  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_5 RESULT=pass>
 4244 04:42:54.855443  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_5 RESULT=pass
 4246 04:42:54.900530  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_5 RESULT=pass>
 4247 04:42:54.901325  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_5 RESULT=pass
 4249 04:42:54.965000  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_5 RESULT=pass>
 4250 04:42:54.965795  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_5 RESULT=pass
 4252 04:42:55.017599  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_5 RESULT=pass>
 4253 04:42:55.018365  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_5 RESULT=pass
 4255 04:42:55.072614  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_5 RESULT=pass>
 4256 04:42:55.073401  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_5 RESULT=pass
 4258 04:42:55.121625  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_4 RESULT=pass>
 4259 04:42:55.122405  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_4 RESULT=pass
 4261 04:42:55.178050  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_4 RESULT=pass>
 4262 04:42:55.178865  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_4 RESULT=pass
 4264 04:42:55.239101  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_4 RESULT=pass>
 4265 04:42:55.239901  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_4 RESULT=pass
 4267 04:42:55.282653  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_4 RESULT=pass>
 4268 04:42:55.283424  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_4 RESULT=pass
 4270 04:42:55.341598  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_4 RESULT=pass>
 4271 04:42:55.342380  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_4 RESULT=pass
 4273 04:42:55.390979  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_4 RESULT=pass>
 4274 04:42:55.391763  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_4 RESULT=pass
 4276 04:42:55.436301  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_4 RESULT=pass>
 4277 04:42:55.437093  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_4 RESULT=pass
 4279 04:42:55.491807  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_3 RESULT=pass>
 4280 04:42:55.492629  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_3 RESULT=pass
 4282 04:42:55.540027  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_3 RESULT=pass>
 4283 04:42:55.540810  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_3 RESULT=pass
 4285 04:42:55.594145  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_3 RESULT=pass>
 4286 04:42:55.594940  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_3 RESULT=pass
 4288 04:42:55.643786  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_3 RESULT=pass>
 4289 04:42:55.644642  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_3 RESULT=pass
 4291 04:42:55.707803  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_3 RESULT=pass>
 4292 04:42:55.708759  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_3 RESULT=pass
 4294 04:42:55.750046  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_3 RESULT=pass>
 4295 04:42:55.750861  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_3 RESULT=pass
 4297 04:42:55.807193  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_3 RESULT=pass>
 4298 04:42:55.808009  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_3 RESULT=pass
 4300 04:42:55.864367  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_2 RESULT=pass>
 4301 04:42:55.865165  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_2 RESULT=pass
 4303 04:42:55.921331  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_2 RESULT=pass>
 4304 04:42:55.922130  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_2 RESULT=pass
 4306 04:42:55.978417  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_2 RESULT=pass>
 4307 04:42:55.979210  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_2 RESULT=pass
 4309 04:42:56.029804  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_2 RESULT=pass>
 4310 04:42:56.030602  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_2 RESULT=pass
 4312 04:42:56.085052  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_2 RESULT=pass>
 4313 04:42:56.085851  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_2 RESULT=pass
 4315 04:42:56.135716  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_2 RESULT=pass>
 4316 04:42:56.136635  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_2 RESULT=pass
 4318 04:42:56.185803  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_2 RESULT=pass>
 4319 04:42:56.186625  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_2 RESULT=pass
 4321 04:42:56.237322  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_1 RESULT=pass>
 4322 04:42:56.238144  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_1 RESULT=pass
 4324 04:42:56.283801  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_1 RESULT=pass>
 4325 04:42:56.284623  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_1 RESULT=pass
 4327 04:42:56.340230  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_1 RESULT=pass>
 4328 04:42:56.341023  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_1 RESULT=pass
 4330 04:42:56.385527  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_1 RESULT=pass>
 4331 04:42:56.386291  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_1 RESULT=pass
 4333 04:42:56.446074  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_1 RESULT=pass>
 4334 04:42:56.446825  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_1 RESULT=pass
 4336 04:42:56.491398  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_1 RESULT=pass>
 4337 04:42:56.492166  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_1 RESULT=pass
 4339 04:42:56.552415  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_1 RESULT=pass>
 4340 04:42:56.553206  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_1 RESULT=pass
 4342 04:42:56.604021  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_0 RESULT=pass>
 4343 04:42:56.604907  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_0 RESULT=pass
 4345 04:42:56.655616  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_0 RESULT=pass>
 4346 04:42:56.656467  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_0 RESULT=pass
 4348 04:42:56.708949  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_0 RESULT=pass>
 4349 04:42:56.709778  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_0 RESULT=pass
 4351 04:42:56.753424  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_0 RESULT=pass>
 4352 04:42:56.754246  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_0 RESULT=pass
 4354 04:42:56.806941  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_0 RESULT=pass>
 4355 04:42:56.807767  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_0 RESULT=pass
 4357 04:42:56.859252  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_0 RESULT=pass>
 4358 04:42:56.860243  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_0 RESULT=pass
 4360 04:42:56.915926  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_0 RESULT=pass>
 4361 04:42:56.916848  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_0 RESULT=pass
 4363 04:42:56.964008  Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test RESULT=pass
 4365 04:42:56.966845  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test RESULT=pass>
 4366 04:42:57.021971  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_5_0_CAPTURE RESULT=skip>
 4367 04:42:57.023042  Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_5_0_CAPTURE RESULT=skip
 4369 04:42:57.069703  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_5_0_CAPTURE RESULT=skip>
 4370 04:42:57.070567  Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_5_0_CAPTURE RESULT=skip
 4372 04:42:57.127915  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_5_0_CAPTURE RESULT=skip>
 4373 04:42:57.128851  Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_5_0_CAPTURE RESULT=skip
 4375 04:42:57.177285  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_5_0_CAPTURE RESULT=skip>
 4376 04:42:57.178235  Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_5_0_CAPTURE RESULT=skip
 4378 04:42:57.236103  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_5_0_CAPTURE RESULT=skip>
 4379 04:42:57.237013  Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_5_0_CAPTURE RESULT=skip
 4381 04:42:57.285867  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_5_0_CAPTURE RESULT=skip>
 4382 04:42:57.286745  Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_5_0_CAPTURE RESULT=skip
 4384 04:42:57.336866  �<LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_5_0_CAPTURE RESULT=skip>
 4385 04:42:57.337723  Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_5_0_CAPTURE RESULT=skip
 4387 04:42:57.388596  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_4_0_CAPTURE RESULT=skip>
 4388 04:42:57.389474  Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_4_0_CAPTURE RESULT=skip
 4390 04:42:57.439712  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_4_0_CAPTURE RESULT=skip>
 4391 04:42:57.440413  Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_4_0_CAPTURE RESULT=skip
 4393 04:42:57.494367  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_4_0_CAPTURE RESULT=skip>
 4394 04:42:57.494971  Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_4_0_CAPTURE RESULT=skip
 4396 04:42:57.544487  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_4_0_CAPTURE RESULT=skip>
 4397 04:42:57.545071  Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_4_0_CAPTURE RESULT=skip
 4399 04:42:57.589608  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_4_0_CAPTURE RESULT=skip>
 4400 04:42:57.590199  Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_4_0_CAPTURE RESULT=skip
 4402 04:42:57.635254  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_4_0_CAPTURE RESULT=skip>
 4403 04:42:57.635815  Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_4_0_CAPTURE RESULT=skip
 4405 04:42:57.688888  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_4_0_CAPTURE RESULT=skip>
 4406 04:42:57.689475  Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_4_0_CAPTURE RESULT=skip
 4408 04:42:57.745518  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_3_0_CAPTURE RESULT=skip>
 4409 04:42:57.746126  Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_3_0_CAPTURE RESULT=skip
 4411 04:42:57.796513  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_3_0_CAPTURE RESULT=skip>
 4412 04:42:57.797090  Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_3_0_CAPTURE RESULT=skip
 4414 04:42:57.849946  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_3_0_CAPTURE RESULT=skip>
 4415 04:42:57.850529  Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_3_0_CAPTURE RESULT=skip
 4417 04:42:57.901535  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_3_0_CAPTURE RESULT=skip>
 4418 04:42:57.902140  Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_3_0_CAPTURE RESULT=skip
 4420 04:42:57.948284  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_3_0_CAPTURE RESULT=skip>
 4421 04:42:57.948920  Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_3_0_CAPTURE RESULT=skip
 4423 04:42:58.005761  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_3_0_CAPTURE RESULT=skip>
 4424 04:42:58.006360  Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_3_0_CAPTURE RESULT=skip
 4426 04:42:58.058035  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_3_0_CAPTURE RESULT=skip>
 4427 04:42:58.058657  Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_3_0_CAPTURE RESULT=skip
 4429 04:42:58.109271  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_2_0_PLAYBACK RESULT=skip>
 4430 04:42:58.109885  Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_2_0_PLAYBACK RESULT=skip
 4432 04:42:58.165685  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_2_0_PLAYBACK RESULT=skip>
 4433 04:42:58.166318  Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_2_0_PLAYBACK RESULT=skip
 4435 04:42:58.218415  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_2_0_PLAYBACK RESULT=skip>
 4436 04:42:58.219025  Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_2_0_PLAYBACK RESULT=skip
 4438 04:42:58.271738  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_2_0_PLAYBACK RESULT=skip>
 4439 04:42:58.272391  Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_2_0_PLAYBACK RESULT=skip
 4441 04:42:58.323900  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_2_0_PLAYBACK RESULT=skip>
 4442 04:42:58.324529  Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_2_0_PLAYBACK RESULT=skip
 4444 04:42:58.368379  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_2_0_PLAYBACK RESULT=skip>
 4445 04:42:58.368978  Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_2_0_PLAYBACK RESULT=skip
 4447 04:42:58.418088  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_2_0_PLAYBACK RESULT=skip>
 4448 04:42:58.418682  Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_2_0_PLAYBACK RESULT=skip
 4450 04:42:58.469877  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_1_0_PLAYBACK RESULT=skip>
 4451 04:42:58.470552  Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_1_0_PLAYBACK RESULT=skip
 4453 04:42:58.513730  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_1_0_PLAYBACK RESULT=skip>
 4454 04:42:58.514345  Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_1_0_PLAYBACK RESULT=skip
 4456 04:42:58.562265  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_1_0_PLAYBACK RESULT=skip>
 4457 04:42:58.562893  Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_1_0_PLAYBACK RESULT=skip
 4459 04:42:58.620919  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_1_0_PLAYBACK RESULT=skip>
 4460 04:42:58.621540  Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_1_0_PLAYBACK RESULT=skip
 4462 04:42:58.665758  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_1_0_PLAYBACK RESULT=skip>
 4463 04:42:58.666356  Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_1_0_PLAYBACK RESULT=skip
 4465 04:42:58.710829  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_1_0_PLAYBACK RESULT=skip>
 4466 04:42:58.711485  Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_1_0_PLAYBACK RESULT=skip
 4468 04:42:58.757519  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_1_0_PLAYBACK RESULT=skip>
 4469 04:42:58.758112  Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_1_0_PLAYBACK RESULT=skip
 4471 04:42:58.811503  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_0_0_PLAYBACK RESULT=skip>
 4472 04:42:58.812510  Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_0_0_PLAYBACK RESULT=skip
 4474 04:42:58.863692  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_0_0_PLAYBACK RESULT=skip>
 4475 04:42:58.864685  Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_0_0_PLAYBACK RESULT=skip
 4477 04:42:58.916947  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_0_0_PLAYBACK RESULT=skip>
 4478 04:42:58.917916  Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_0_0_PLAYBACK RESULT=skip
 4480 04:42:58.965403  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_0_0_PLAYBACK RESULT=skip>
 4481 04:42:58.966292  Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_0_0_PLAYBACK RESULT=skip
 4483 04:42:59.016094  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_0_0_PLAYBACK RESULT=skip>
 4484 04:42:59.016990  Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_0_0_PLAYBACK RESULT=skip
 4486 04:42:59.063069  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_0_0_PLAYBACK RESULT=skip>
 4487 04:42:59.064084  Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_0_0_PLAYBACK RESULT=skip
 4489 04:42:59.112653  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_0_0_PLAYBACK RESULT=skip>
 4490 04:42:59.113577  Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_0_0_PLAYBACK RESULT=skip
 4492 04:42:59.166544  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test RESULT=pass>
 4493 04:42:59.167526  Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test RESULT=pass
 4495 04:42:59.218320  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_playback_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip>
 4496 04:42:59.219244  Received signal: <TESTCASE> TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_playback_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip
 4498 04:42:59.263569  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_capture_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip>
 4499 04:42:59.264488  Received signal: <TESTCASE> TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_capture_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip
 4501 04:42:59.310696  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_ni_capture_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip>
 4502 04:42:59.311576  Received signal: <TESTCASE> TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_ni_capture_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip
 4504 04:42:59.365964  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_ni_playback_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip>
 4505 04:42:59.366900  Received signal: <TESTCASE> TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_ni_playback_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip
 4507 04:42:59.419015  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_reset_ioctl_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip>
 4508 04:42:59.419931  Received signal: <TESTCASE> TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_reset_ioctl_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip
 4510 04:42:59.468942  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_test-pcmtest-driver RESULT=pass>
 4511 04:42:59.470021  Received signal: <TESTCASE> TEST_CASE_ID=alsa_test-pcmtest-driver RESULT=pass
 4513 04:42:59.517857  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_utimer-test_global_wrong_timers_test RESULT=pass>
 4514 04:42:59.518779  Received signal: <TESTCASE> TEST_CASE_ID=alsa_utimer-test_global_wrong_timers_test RESULT=pass
 4516 04:42:59.565130  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_utimer-test_timer_f_utimer RESULT=fail>
 4517 04:42:59.566031  Received signal: <TESTCASE> TEST_CASE_ID=alsa_utimer-test_timer_f_utimer RESULT=fail
 4519 04:42:59.620312  Received signal: <TESTCASE> TEST_CASE_ID=alsa_utimer-test RESULT=fail
 4521 04:42:59.625514  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_utimer-test RESULT=fail>
 4522 04:42:59.626033  + set +x
 4523 04:42:59.631493  <LAVA_SIGNAL_ENDRUN 1_kselftest-alsa 906892_1.6.2.4.5>
 4524 04:42:59.632024  <LAVA_TEST_RUNNER EXIT>
 4525 04:42:59.632744  Received signal: <ENDRUN> 1_kselftest-alsa 906892_1.6.2.4.5
 4526 04:42:59.633237  Ending use of test pattern.
 4527 04:42:59.633683  Ending test lava.1_kselftest-alsa (906892_1.6.2.4.5), duration 40.64
 4529 04:42:59.635320  ok: lava_test_shell seems to have completed
 4530 04:42:59.660236  alsa_mixer-test: pass
alsa_mixer-test_event_missing_LCALTA_0: pass
alsa_mixer-test_event_missing_LCALTA_1: pass
alsa_mixer-test_event_missing_LCALTA_10: pass
alsa_mixer-test_event_missing_LCALTA_11: pass
alsa_mixer-test_event_missing_LCALTA_12: pass
alsa_mixer-test_event_missing_LCALTA_13: pass
alsa_mixer-test_event_missing_LCALTA_14: pass
alsa_mixer-test_event_missing_LCALTA_15: pass
alsa_mixer-test_event_missing_LCALTA_16: pass
alsa_mixer-test_event_missing_LCALTA_17: pass
alsa_mixer-test_event_missing_LCALTA_18: pass
alsa_mixer-test_event_missing_LCALTA_19: pass
alsa_mixer-test_event_missing_LCALTA_2: pass
alsa_mixer-test_event_missing_LCALTA_20: pass
alsa_mixer-test_event_missing_LCALTA_21: pass
alsa_mixer-test_event_missing_LCALTA_22: pass
alsa_mixer-test_event_missing_LCALTA_23: pass
alsa_mixer-test_event_missing_LCALTA_24: pass
alsa_mixer-test_event_missing_LCALTA_25: pass
alsa_mixer-test_event_missing_LCALTA_26: pass
alsa_mixer-test_event_missing_LCALTA_27: pass
alsa_mixer-test_event_missing_LCALTA_28: pass
alsa_mixer-test_event_missing_LCALTA_29: pass
alsa_mixer-test_event_missing_LCALTA_3: pass
alsa_mixer-test_event_missing_LCALTA_30: pass
alsa_mixer-test_event_missing_LCALTA_31: pass
alsa_mixer-test_event_missing_LCALTA_32: pass
alsa_mixer-test_event_missing_LCALTA_33: pass
alsa_mixer-test_event_missing_LCALTA_34: pass
alsa_mixer-test_event_missing_LCALTA_35: pass
alsa_mixer-test_event_missing_LCALTA_36: pass
alsa_mixer-test_event_missing_LCALTA_37: pass
alsa_mixer-test_event_missing_LCALTA_38: pass
alsa_mixer-test_event_missing_LCALTA_39: pass
alsa_mixer-test_event_missing_LCALTA_4: pass
alsa_mixer-test_event_missing_LCALTA_40: pass
alsa_mixer-test_event_missing_LCALTA_41: pass
alsa_mixer-test_event_missing_LCALTA_42: pass
alsa_mixer-test_event_missing_LCALTA_43: pass
alsa_mixer-test_event_missing_LCALTA_44: pass
alsa_mixer-test_event_missing_LCALTA_45: pass
alsa_mixer-test_event_missing_LCALTA_46: pass
alsa_mixer-test_event_missing_LCALTA_47: pass
alsa_mixer-test_event_missing_LCALTA_48: pass
alsa_mixer-test_event_missing_LCALTA_49: pass
alsa_mixer-test_event_missing_LCALTA_5: pass
alsa_mixer-test_event_missing_LCALTA_50: pass
alsa_mixer-test_event_missing_LCALTA_51: pass
alsa_mixer-test_event_missing_LCALTA_52: pass
alsa_mixer-test_event_missing_LCALTA_53: pass
alsa_mixer-test_event_missing_LCALTA_54: pass
alsa_mixer-test_event_missing_LCALTA_55: pass
alsa_mixer-test_event_missing_LCALTA_56: pass
alsa_mixer-test_event_missing_LCALTA_57: pass
alsa_mixer-test_event_missing_LCALTA_58: pass
alsa_mixer-test_event_missing_LCALTA_59: pass
alsa_mixer-test_event_missing_LCALTA_6: pass
alsa_mixer-test_event_missing_LCALTA_60: pass
alsa_mixer-test_event_missing_LCALTA_7: pass
alsa_mixer-test_event_missing_LCALTA_8: pass
alsa_mixer-test_event_missing_LCALTA_9: pass
alsa_mixer-test_event_spurious_LCALTA_0: pass
alsa_mixer-test_event_spurious_LCALTA_1: pass
alsa_mixer-test_event_spurious_LCALTA_10: pass
alsa_mixer-test_event_spurious_LCALTA_11: pass
alsa_mixer-test_event_spurious_LCALTA_12: pass
alsa_mixer-test_event_spurious_LCALTA_13: pass
alsa_mixer-test_event_spurious_LCALTA_14: pass
alsa_mixer-test_event_spurious_LCALTA_15: pass
alsa_mixer-test_event_spurious_LCALTA_16: pass
alsa_mixer-test_event_spurious_LCALTA_17: pass
alsa_mixer-test_event_spurious_LCALTA_18: pass
alsa_mixer-test_event_spurious_LCALTA_19: pass
alsa_mixer-test_event_spurious_LCALTA_2: pass
alsa_mixer-test_event_spurious_LCALTA_20: pass
alsa_mixer-test_event_spurious_LCALTA_21: pass
alsa_mixer-test_event_spurious_LCALTA_22: pass
alsa_mixer-test_event_spurious_LCALTA_23: pass
alsa_mixer-test_event_spurious_LCALTA_24: pass
alsa_mixer-test_event_spurious_LCALTA_25: pass
alsa_mixer-test_event_spurious_LCALTA_26: pass
alsa_mixer-test_event_spurious_LCALTA_27: pass
alsa_mixer-test_event_spurious_LCALTA_28: pass
alsa_mixer-test_event_spurious_LCALTA_29: pass
alsa_mixer-test_event_spurious_LCALTA_3: pass
alsa_mixer-test_event_spurious_LCALTA_30: pass
alsa_mixer-test_event_spurious_LCALTA_31: pass
alsa_mixer-test_event_spurious_LCALTA_32: pass
alsa_mixer-test_event_spurious_LCALTA_33: pass
alsa_mixer-test_event_spurious_LCALTA_34: pass
alsa_mixer-test_event_spurious_LCALTA_35: pass
alsa_mixer-test_event_spurious_LCALTA_36: pass
alsa_mixer-test_event_spurious_LCALTA_37: pass
alsa_mixer-test_event_spurious_LCALTA_38: pass
alsa_mixer-test_event_spurious_LCALTA_39: pass
alsa_mixer-test_event_spurious_LCALTA_4: pass
alsa_mixer-test_event_spurious_LCALTA_40: pass
alsa_mixer-test_event_spurious_LCALTA_41: pass
alsa_mixer-test_event_spurious_LCALTA_42: pass
alsa_mixer-test_event_spurious_LCALTA_43: pass
alsa_mixer-test_event_spurious_LCALTA_44: pass
alsa_mixer-test_event_spurious_LCALTA_45: pass
alsa_mixer-test_event_spurious_LCALTA_46: pass
alsa_mixer-test_event_spurious_LCALTA_47: pass
alsa_mixer-test_event_spurious_LCALTA_48: pass
alsa_mixer-test_event_spurious_LCALTA_49: pass
alsa_mixer-test_event_spurious_LCALTA_5: pass
alsa_mixer-test_event_spurious_LCALTA_50: pass
alsa_mixer-test_event_spurious_LCALTA_51: pass
alsa_mixer-test_event_spurious_LCALTA_52: pass
alsa_mixer-test_event_spurious_LCALTA_53: pass
alsa_mixer-test_event_spurious_LCALTA_54: pass
alsa_mixer-test_event_spurious_LCALTA_55: pass
alsa_mixer-test_event_spurious_LCALTA_56: pass
alsa_mixer-test_event_spurious_LCALTA_57: pass
alsa_mixer-test_event_spurious_LCALTA_58: pass
alsa_mixer-test_event_spurious_LCALTA_59: pass
alsa_mixer-test_event_spurious_LCALTA_6: pass
alsa_mixer-test_event_spurious_LCALTA_60: pass
alsa_mixer-test_event_spurious_LCALTA_7: pass
alsa_mixer-test_event_spurious_LCALTA_8: pass
alsa_mixer-test_event_spurious_LCALTA_9: pass
alsa_mixer-test_get_value_LCALTA_0: pass
alsa_mixer-test_get_value_LCALTA_1: pass
alsa_mixer-test_get_value_LCALTA_10: pass
alsa_mixer-test_get_value_LCALTA_11: pass
alsa_mixer-test_get_value_LCALTA_12: pass
alsa_mixer-test_get_value_LCALTA_13: pass
alsa_mixer-test_get_value_LCALTA_14: pass
alsa_mixer-test_get_value_LCALTA_15: pass
alsa_mixer-test_get_value_LCALTA_16: pass
alsa_mixer-test_get_value_LCALTA_17: pass
alsa_mixer-test_get_value_LCALTA_18: pass
alsa_mixer-test_get_value_LCALTA_19: pass
alsa_mixer-test_get_value_LCALTA_2: pass
alsa_mixer-test_get_value_LCALTA_20: pass
alsa_mixer-test_get_value_LCALTA_21: pass
alsa_mixer-test_get_value_LCALTA_22: pass
alsa_mixer-test_get_value_LCALTA_23: pass
alsa_mixer-test_get_value_LCALTA_24: pass
alsa_mixer-test_get_value_LCALTA_25: pass
alsa_mixer-test_get_value_LCALTA_26: pass
alsa_mixer-test_get_value_LCALTA_27: pass
alsa_mixer-test_get_value_LCALTA_28: pass
alsa_mixer-test_get_value_LCALTA_29: pass
alsa_mixer-test_get_value_LCALTA_3: pass
alsa_mixer-test_get_value_LCALTA_30: pass
alsa_mixer-test_get_value_LCALTA_31: pass
alsa_mixer-test_get_value_LCALTA_32: pass
alsa_mixer-test_get_value_LCALTA_33: pass
alsa_mixer-test_get_value_LCALTA_34: pass
alsa_mixer-test_get_value_LCALTA_35: pass
alsa_mixer-test_get_value_LCALTA_36: pass
alsa_mixer-test_get_value_LCALTA_37: pass
alsa_mixer-test_get_value_LCALTA_38: pass
alsa_mixer-test_get_value_LCALTA_39: pass
alsa_mixer-test_get_value_LCALTA_4: pass
alsa_mixer-test_get_value_LCALTA_40: pass
alsa_mixer-test_get_value_LCALTA_41: pass
alsa_mixer-test_get_value_LCALTA_42: pass
alsa_mixer-test_get_value_LCALTA_43: pass
alsa_mixer-test_get_value_LCALTA_44: pass
alsa_mixer-test_get_value_LCALTA_45: pass
alsa_mixer-test_get_value_LCALTA_46: pass
alsa_mixer-test_get_value_LCALTA_47: pass
alsa_mixer-test_get_value_LCALTA_48: pass
alsa_mixer-test_get_value_LCALTA_49: pass
alsa_mixer-test_get_value_LCALTA_5: pass
alsa_mixer-test_get_value_LCALTA_50: pass
alsa_mixer-test_get_value_LCALTA_51: pass
alsa_mixer-test_get_value_LCALTA_52: pass
alsa_mixer-test_get_value_LCALTA_53: pass
alsa_mixer-test_get_value_LCALTA_54: pass
alsa_mixer-test_get_value_LCALTA_55: pass
alsa_mixer-test_get_value_LCALTA_56: pass
alsa_mixer-test_get_value_LCALTA_57: pass
alsa_mixer-test_get_value_LCALTA_58: pass
alsa_mixer-test_get_value_LCALTA_59: pass
alsa_mixer-test_get_value_LCALTA_6: pass
alsa_mixer-test_get_value_LCALTA_60: pass
alsa_mixer-test_get_value_LCALTA_7: pass
alsa_mixer-test_get_value_LCALTA_8: pass
alsa_mixer-test_get_value_LCALTA_9: pass
alsa_mixer-test_name_LCALTA_0: pass
alsa_mixer-test_name_LCALTA_1: pass
alsa_mixer-test_name_LCALTA_10: pass
alsa_mixer-test_name_LCALTA_11: pass
alsa_mixer-test_name_LCALTA_12: pass
alsa_mixer-test_name_LCALTA_13: pass
alsa_mixer-test_name_LCALTA_14: pass
alsa_mixer-test_name_LCALTA_15: pass
alsa_mixer-test_name_LCALTA_16: pass
alsa_mixer-test_name_LCALTA_17: pass
alsa_mixer-test_name_LCALTA_18: pass
alsa_mixer-test_name_LCALTA_19: pass
alsa_mixer-test_name_LCALTA_2: pass
alsa_mixer-test_name_LCALTA_20: pass
alsa_mixer-test_name_LCALTA_21: pass
alsa_mixer-test_name_LCALTA_22: pass
alsa_mixer-test_name_LCALTA_23: pass
alsa_mixer-test_name_LCALTA_24: pass
alsa_mixer-test_name_LCALTA_25: pass
alsa_mixer-test_name_LCALTA_26: pass
alsa_mixer-test_name_LCALTA_27: pass
alsa_mixer-test_name_LCALTA_28: pass
alsa_mixer-test_name_LCALTA_29: pass
alsa_mixer-test_name_LCALTA_3: pass
alsa_mixer-test_name_LCALTA_30: pass
alsa_mixer-test_name_LCALTA_31: pass
alsa_mixer-test_name_LCALTA_32: pass
alsa_mixer-test_name_LCALTA_33: pass
alsa_mixer-test_name_LCALTA_34: pass
alsa_mixer-test_name_LCALTA_35: pass
alsa_mixer-test_name_LCALTA_36: pass
alsa_mixer-test_name_LCALTA_37: pass
alsa_mixer-test_name_LCALTA_38: pass
alsa_mixer-test_name_LCALTA_39: pass
alsa_mixer-test_name_LCALTA_4: pass
alsa_mixer-test_name_LCALTA_40: pass
alsa_mixer-test_name_LCALTA_41: pass
alsa_mixer-test_name_LCALTA_42: pass
alsa_mixer-test_name_LCALTA_43: pass
alsa_mixer-test_name_LCALTA_44: pass
alsa_mixer-test_name_LCALTA_45: pass
alsa_mixer-test_name_LCALTA_46: pass
alsa_mixer-test_name_LCALTA_47: pass
alsa_mixer-test_name_LCALTA_48: pass
alsa_mixer-test_name_LCALTA_49: pass
alsa_mixer-test_name_LCALTA_5: pass
alsa_mixer-test_name_LCALTA_50: pass
alsa_mixer-test_name_LCALTA_51: pass
alsa_mixer-test_name_LCALTA_52: pass
alsa_mixer-test_name_LCALTA_53: pass
alsa_mixer-test_name_LCALTA_54: pass
alsa_mixer-test_name_LCALTA_55: pass
alsa_mixer-test_name_LCALTA_56: pass
alsa_mixer-test_name_LCALTA_57: pass
alsa_mixer-test_name_LCALTA_58: pass
alsa_mixer-test_name_LCALTA_59: pass
alsa_mixer-test_name_LCALTA_6: pass
alsa_mixer-test_name_LCALTA_60: pass
alsa_mixer-test_name_LCALTA_7: pass
alsa_mixer-test_name_LCALTA_8: pass
alsa_mixer-test_name_LCALTA_9: pass
alsa_mixer-test_write_default_LCALTA_0: pass
alsa_mixer-test_write_default_LCALTA_1: pass
alsa_mixer-test_write_default_LCALTA_10: pass
alsa_mixer-test_write_default_LCALTA_11: pass
alsa_mixer-test_write_default_LCALTA_12: pass
alsa_mixer-test_write_default_LCALTA_13: pass
alsa_mixer-test_write_default_LCALTA_14: pass
alsa_mixer-test_write_default_LCALTA_15: pass
alsa_mixer-test_write_default_LCALTA_16: pass
alsa_mixer-test_write_default_LCALTA_17: pass
alsa_mixer-test_write_default_LCALTA_18: pass
alsa_mixer-test_write_default_LCALTA_19: pass
alsa_mixer-test_write_default_LCALTA_2: pass
alsa_mixer-test_write_default_LCALTA_20: pass
alsa_mixer-test_write_default_LCALTA_21: pass
alsa_mixer-test_write_default_LCALTA_22: pass
alsa_mixer-test_write_default_LCALTA_23: skip
alsa_mixer-test_write_default_LCALTA_24: skip
alsa_mixer-test_write_default_LCALTA_25: pass
alsa_mixer-test_write_default_LCALTA_26: skip
alsa_mixer-test_write_default_LCALTA_27: pass
alsa_mixer-test_write_default_LCALTA_28: pass
alsa_mixer-test_write_default_LCALTA_29: pass
alsa_mixer-test_write_default_LCALTA_3: pass
alsa_mixer-test_write_default_LCALTA_30: pass
alsa_mixer-test_write_default_LCALTA_31: pass
alsa_mixer-test_write_default_LCALTA_32: pass
alsa_mixer-test_write_default_LCALTA_33: pass
alsa_mixer-test_write_default_LCALTA_34: pass
alsa_mixer-test_write_default_LCALTA_35: pass
alsa_mixer-test_write_default_LCALTA_36: pass
alsa_mixer-test_write_default_LCALTA_37: pass
alsa_mixer-test_write_default_LCALTA_38: pass
alsa_mixer-test_write_default_LCALTA_39: pass
alsa_mixer-test_write_default_LCALTA_4: pass
alsa_mixer-test_write_default_LCALTA_40: pass
alsa_mixer-test_write_default_LCALTA_41: pass
alsa_mixer-test_write_default_LCALTA_42: pass
alsa_mixer-test_write_default_LCALTA_43: pass
alsa_mixer-test_write_default_LCALTA_44: pass
alsa_mixer-test_write_default_LCALTA_45: pass
alsa_mixer-test_write_default_LCALTA_46: pass
alsa_mixer-test_write_default_LCALTA_47: pass
alsa_mixer-test_write_default_LCALTA_48: pass
alsa_mixer-test_write_default_LCALTA_49: pass
alsa_mixer-test_write_default_LCALTA_5: pass
alsa_mixer-test_write_default_LCALTA_50: pass
alsa_mixer-test_write_default_LCALTA_51: pass
alsa_mixer-test_write_default_LCALTA_52: pass
alsa_mixer-test_write_default_LCALTA_53: pass
alsa_mixer-test_write_default_LCALTA_54: pass
alsa_mixer-test_write_default_LCALTA_55: pass
alsa_mixer-test_write_default_LCALTA_56: pass
alsa_mixer-test_write_default_LCALTA_57: pass
alsa_mixer-test_write_default_LCALTA_58: pass
alsa_mixer-test_write_default_LCALTA_59: pass
alsa_mixer-test_write_default_LCALTA_6: pass
alsa_mixer-test_write_default_LCALTA_60: pass
alsa_mixer-test_write_default_LCALTA_7: pass
alsa_mixer-test_write_default_LCALTA_8: pass
alsa_mixer-test_write_default_LCALTA_9: pass
alsa_mixer-test_write_invalid_LCALTA_0: pass
alsa_mixer-test_write_invalid_LCALTA_1: pass
alsa_mixer-test_write_invalid_LCALTA_10: pass
alsa_mixer-test_write_invalid_LCALTA_11: pass
alsa_mixer-test_write_invalid_LCALTA_12: pass
alsa_mixer-test_write_invalid_LCALTA_13: pass
alsa_mixer-test_write_invalid_LCALTA_14: pass
alsa_mixer-test_write_invalid_LCALTA_15: pass
alsa_mixer-test_write_invalid_LCALTA_16: pass
alsa_mixer-test_write_invalid_LCALTA_17: pass
alsa_mixer-test_write_invalid_LCALTA_18: pass
alsa_mixer-test_write_invalid_LCALTA_19: pass
alsa_mixer-test_write_invalid_LCALTA_2: pass
alsa_mixer-test_write_invalid_LCALTA_20: pass
alsa_mixer-test_write_invalid_LCALTA_21: pass
alsa_mixer-test_write_invalid_LCALTA_22: pass
alsa_mixer-test_write_invalid_LCALTA_23: skip
alsa_mixer-test_write_invalid_LCALTA_24: skip
alsa_mixer-test_write_invalid_LCALTA_25: skip
alsa_mixer-test_write_invalid_LCALTA_26: skip
alsa_mixer-test_write_invalid_LCALTA_27: pass
alsa_mixer-test_write_invalid_LCALTA_28: pass
alsa_mixer-test_write_invalid_LCALTA_29: pass
alsa_mixer-test_write_invalid_LCALTA_3: pass
alsa_mixer-test_write_invalid_LCALTA_30: pass
alsa_mixer-test_write_invalid_LCALTA_31: pass
alsa_mixer-test_write_invalid_LCALTA_32: pass
alsa_mixer-test_write_invalid_LCALTA_33: pass
alsa_mixer-test_write_invalid_LCALTA_34: pass
alsa_mixer-test_write_invalid_LCALTA_35: pass
alsa_mixer-test_write_invalid_LCALTA_36: pass
alsa_mixer-test_write_invalid_LCALTA_37: pass
alsa_mixer-test_write_invalid_LCALTA_38: pass
alsa_mixer-test_write_invalid_LCALTA_39: pass
alsa_mixer-test_write_invalid_LCALTA_4: pass
alsa_mixer-test_write_invalid_LCALTA_40: pass
alsa_mixer-test_write_invalid_LCALTA_41: pass
alsa_mixer-test_write_invalid_LCALTA_42: pass
alsa_mixer-test_write_invalid_LCALTA_43: pass
alsa_mixer-test_write_invalid_LCALTA_44: pass
alsa_mixer-test_write_invalid_LCALTA_45: pass
alsa_mixer-test_write_invalid_LCALTA_46: pass
alsa_mixer-test_write_invalid_LCALTA_47: pass
alsa_mixer-test_write_invalid_LCALTA_48: pass
alsa_mixer-test_write_invalid_LCALTA_49: pass
alsa_mixer-test_write_invalid_LCALTA_5: pass
alsa_mixer-test_write_invalid_LCALTA_50: pass
alsa_mixer-test_write_invalid_LCALTA_51: pass
alsa_mixer-test_write_invalid_LCALTA_52: pass
alsa_mixer-test_write_invalid_LCALTA_53: pass
alsa_mixer-test_write_invalid_LCALTA_54: pass
alsa_mixer-test_write_invalid_LCALTA_55: pass
alsa_mixer-test_write_invalid_LCALTA_56: pass
alsa_mixer-test_write_invalid_LCALTA_57: pass
alsa_mixer-test_write_invalid_LCALTA_58: pass
alsa_mixer-test_write_invalid_LCALTA_59: pass
alsa_mixer-test_write_invalid_LCALTA_6: pass
alsa_mixer-test_write_invalid_LCALTA_60: pass
alsa_mixer-test_write_invalid_LCALTA_7: pass
alsa_mixer-test_write_invalid_LCALTA_8: pass
alsa_mixer-test_write_invalid_LCALTA_9: pass
alsa_mixer-test_write_valid_LCALTA_0: pass
alsa_mixer-test_write_valid_LCALTA_1: pass
alsa_mixer-test_write_valid_LCALTA_10: pass
alsa_mixer-test_write_valid_LCALTA_11: pass
alsa_mixer-test_write_valid_LCALTA_12: pass
alsa_mixer-test_write_valid_LCALTA_13: pass
alsa_mixer-test_write_valid_LCALTA_14: pass
alsa_mixer-test_write_valid_LCALTA_15: pass
alsa_mixer-test_write_valid_LCALTA_16: pass
alsa_mixer-test_write_valid_LCALTA_17: pass
alsa_mixer-test_write_valid_LCALTA_18: pass
alsa_mixer-test_write_valid_LCALTA_19: pass
alsa_mixer-test_write_valid_LCALTA_2: pass
alsa_mixer-test_write_valid_LCALTA_20: pass
alsa_mixer-test_write_valid_LCALTA_21: pass
alsa_mixer-test_write_valid_LCALTA_22: pass
alsa_mixer-test_write_valid_LCALTA_23: skip
alsa_mixer-test_write_valid_LCALTA_24: skip
alsa_mixer-test_write_valid_LCALTA_25: skip
alsa_mixer-test_write_valid_LCALTA_26: skip
alsa_mixer-test_write_valid_LCALTA_27: pass
alsa_mixer-test_write_valid_LCALTA_28: pass
alsa_mixer-test_write_valid_LCALTA_29: pass
alsa_mixer-test_write_valid_LCALTA_3: pass
alsa_mixer-test_write_valid_LCALTA_30: pass
alsa_mixer-test_write_valid_LCALTA_31: pass
alsa_mixer-test_write_valid_LCALTA_32: pass
alsa_mixer-test_write_valid_LCALTA_33: pass
alsa_mixer-test_write_valid_LCALTA_34: pass
alsa_mixer-test_write_valid_LCALTA_35: pass
alsa_mixer-test_write_valid_LCALTA_36: pass
alsa_mixer-test_write_valid_LCALTA_37: pass
alsa_mixer-test_write_valid_LCALTA_38: pass
alsa_mixer-test_write_valid_LCALTA_39: pass
alsa_mixer-test_write_valid_LCALTA_4: pass
alsa_mixer-test_write_valid_LCALTA_40: pass
alsa_mixer-test_write_valid_LCALTA_41: pass
alsa_mixer-test_write_valid_LCALTA_42: pass
alsa_mixer-test_write_valid_LCALTA_43: pass
alsa_mixer-test_write_valid_LCALTA_44: pass
alsa_mixer-test_write_valid_LCALTA_45: pass
alsa_mixer-test_write_valid_LCALTA_46: pass
alsa_mixer-test_write_valid_LCALTA_47: pass
alsa_mixer-test_write_valid_LCALTA_48: pass
alsa_mixer-test_write_valid_LCALTA_49: pass
alsa_mixer-test_write_valid_LCALTA_5: pass
alsa_mixer-test_write_valid_LCALTA_50: pass
alsa_mixer-test_write_valid_LCALTA_51: pass
alsa_mixer-test_write_valid_LCALTA_52: pass
alsa_mixer-test_write_valid_LCALTA_53: pass
alsa_mixer-test_write_valid_LCALTA_54: pass
alsa_mixer-test_write_valid_LCALTA_55: pass
alsa_mixer-test_write_valid_LCALTA_56: pass
alsa_mixer-test_write_valid_LCALTA_57: pass
alsa_mixer-test_write_valid_LCALTA_58: pass
alsa_mixer-test_write_valid_LCALTA_59: pass
alsa_mixer-test_write_valid_LCALTA_6: pass
alsa_mixer-test_write_valid_LCALTA_60: pass
alsa_mixer-test_write_valid_LCALTA_7: pass
alsa_mixer-test_write_valid_LCALTA_8: pass
alsa_mixer-test_write_valid_LCALTA_9: pass
alsa_pcm-test: pass
alsa_pcm-test_default_time1_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time1_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time1_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time1_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time1_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time1_LCALTA_5_0_CAPTURE: skip
alsa_pcm-test_default_time2_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time2_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time2_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time2_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time2_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time2_LCALTA_5_0_CAPTURE: skip
alsa_pcm-test_default_time3_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time3_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time3_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time3_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time3_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time3_LCALTA_5_0_CAPTURE: skip
alsa_pcm-test_default_time4_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time4_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time4_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time4_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time4_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time4_LCALTA_5_0_CAPTURE: skip
alsa_pcm-test_default_time5_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time5_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time5_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time5_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time5_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time5_LCALTA_5_0_CAPTURE: skip
alsa_pcm-test_default_time6_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time6_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time6_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time6_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time6_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time6_LCALTA_5_0_CAPTURE: skip
alsa_pcm-test_default_time7_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time7_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time7_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time7_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time7_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time7_LCALTA_5_0_CAPTURE: skip
alsa_test-pcmtest-driver: pass
alsa_test-pcmtest-driver_pcmtest_capture_Can_t_read_patterns_Probably_module_isn_t_loaded: skip
alsa_test-pcmtest-driver_pcmtest_ni_capture_Can_t_read_patterns_Probably_module_isn_t_loaded: skip
alsa_test-pcmtest-driver_pcmtest_ni_playback_Can_t_read_patterns_Probably_module_isn_t_loaded: skip
alsa_test-pcmtest-driver_pcmtest_playback_Can_t_read_patterns_Probably_module_isn_t_loaded: skip
alsa_test-pcmtest-driver_pcmtest_reset_ioctl_Can_t_read_patterns_Probably_module_isn_t_loaded: skip
alsa_utimer-test: fail
alsa_utimer-test_global_wrong_timers_test: pass
alsa_utimer-test_timer_f_utimer: fail
shardfile-alsa: pass

 4531 04:42:59.662167  end: 3.1 lava-test-shell (duration 00:00:41) [common]
 4532 04:42:59.662782  end: 3 lava-test-retry (duration 00:00:41) [common]
 4533 04:42:59.663399  start: 4 finalize (timeout 00:06:05) [common]
 4534 04:42:59.664041  start: 4.1 power-off (timeout 00:00:30) [common]
 4535 04:42:59.665065  Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
 4536 04:42:59.699410  >> OK - accepted request

 4537 04:42:59.701545  Returned 0 in 0 seconds
 4538 04:42:59.802809  end: 4.1 power-off (duration 00:00:00) [common]
 4540 04:42:59.804858  start: 4.2 read-feedback (timeout 00:06:04) [common]
 4541 04:42:59.806192  Listened to connection for namespace 'common' for up to 1s
 4542 04:43:00.806975  Finalising connection for namespace 'common'
 4543 04:43:00.807827  Disconnecting from shell: Finalise
 4544 04:43:00.808467  / # 
 4545 04:43:00.909492  end: 4.2 read-feedback (duration 00:00:01) [common]
 4546 04:43:00.910262  end: 4 finalize (duration 00:00:01) [common]
 4547 04:43:00.911009  Cleaning after the job
 4548 04:43:00.911707  Cleaning up download directory: /var/lib/lava/dispatcher/tmp/906892/tftp-deploy-hewr7mbe/ramdisk
 4549 04:43:00.915045  Cleaning up download directory: /var/lib/lava/dispatcher/tmp/906892/tftp-deploy-hewr7mbe/kernel
 4550 04:43:00.926901  Cleaning up download directory: /var/lib/lava/dispatcher/tmp/906892/tftp-deploy-hewr7mbe/dtb
 4551 04:43:00.928283  Cleaning up download directory: /var/lib/lava/dispatcher/tmp/906892/tftp-deploy-hewr7mbe/nfsrootfs
 4552 04:43:00.980652  Cleaning up download directory: /var/lib/lava/dispatcher/tmp/906892/tftp-deploy-hewr7mbe/modules
 4553 04:43:00.987126  Override tmp directory removed at /var/lib/lava/dispatcher/tmp/906892
 4554 04:43:04.309758  Root tmp directory removed at /var/lib/lava/dispatcher/tmp/906892
 4555 04:43:04.310306  Job finished correctly