Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 05:01:45.186769 lava-dispatcher, installed at version: 2024.01
2 05:01:45.187535 start: 0 validate
3 05:01:45.188041 Start time: 2024-10-29 05:01:45.188009+00:00 (UTC)
4 05:01:45.188600 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 05:01:45.189146 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 05:01:45.231384 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 05:01:45.231958 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fpending-fixes%2Fv6.12-rc5-243-g2f5e60c44402%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 05:01:45.258521 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 05:01:45.259171 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fpending-fixes%2Fv6.12-rc5-243-g2f5e60c44402%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 05:01:45.293167 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 05:01:45.293662 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 05:01:45.327693 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 05:01:45.328221 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fpending-fixes%2Fv6.12-rc5-243-g2f5e60c44402%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
14 05:01:45.368598 validate duration: 0.18
16 05:01:45.369423 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 05:01:45.369732 start: 1.1 download-retry (timeout 00:10:00) [common]
18 05:01:45.370028 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 05:01:45.370594 Not decompressing ramdisk as can be used compressed.
20 05:01:45.371023 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 05:01:45.371298 saving as /var/lib/lava/dispatcher/tmp/907044/tftp-deploy-hpxzdqdk/ramdisk/initrd.cpio.gz
22 05:01:45.371563 total size: 5628169 (5 MB)
23 05:01:45.405913 progress 0 % (0 MB)
24 05:01:45.412953 progress 5 % (0 MB)
25 05:01:45.417191 progress 10 % (0 MB)
26 05:01:45.420929 progress 15 % (0 MB)
27 05:01:45.425021 progress 20 % (1 MB)
28 05:01:45.428645 progress 25 % (1 MB)
29 05:01:45.432702 progress 30 % (1 MB)
30 05:01:45.436757 progress 35 % (1 MB)
31 05:01:45.440340 progress 40 % (2 MB)
32 05:01:45.444342 progress 45 % (2 MB)
33 05:01:45.447873 progress 50 % (2 MB)
34 05:01:45.451841 progress 55 % (2 MB)
35 05:01:45.455809 progress 60 % (3 MB)
36 05:01:45.459366 progress 65 % (3 MB)
37 05:01:45.463408 progress 70 % (3 MB)
38 05:01:45.466952 progress 75 % (4 MB)
39 05:01:45.470940 progress 80 % (4 MB)
40 05:01:45.474527 progress 85 % (4 MB)
41 05:01:45.478488 progress 90 % (4 MB)
42 05:01:45.482287 progress 95 % (5 MB)
43 05:01:45.485586 progress 100 % (5 MB)
44 05:01:45.486250 5 MB downloaded in 0.11 s (46.81 MB/s)
45 05:01:45.486795 end: 1.1.1 http-download (duration 00:00:00) [common]
47 05:01:45.487687 end: 1.1 download-retry (duration 00:00:00) [common]
48 05:01:45.488025 start: 1.2 download-retry (timeout 00:10:00) [common]
49 05:01:45.488333 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 05:01:45.488851 downloading http://storage.kernelci.org/next/pending-fixes/v6.12-rc5-243-g2f5e60c44402/arm64/defconfig/gcc-12/kernel/Image
51 05:01:45.489106 saving as /var/lib/lava/dispatcher/tmp/907044/tftp-deploy-hpxzdqdk/kernel/Image
52 05:01:45.489328 total size: 45713920 (43 MB)
53 05:01:45.489544 No compression specified
54 05:01:45.533101 progress 0 % (0 MB)
55 05:01:45.562306 progress 5 % (2 MB)
56 05:01:45.591226 progress 10 % (4 MB)
57 05:01:45.620316 progress 15 % (6 MB)
58 05:01:45.648874 progress 20 % (8 MB)
59 05:01:45.677421 progress 25 % (10 MB)
60 05:01:45.705978 progress 30 % (13 MB)
61 05:01:45.734537 progress 35 % (15 MB)
62 05:01:45.763550 progress 40 % (17 MB)
63 05:01:45.791889 progress 45 % (19 MB)
64 05:01:45.820830 progress 50 % (21 MB)
65 05:01:45.849457 progress 55 % (24 MB)
66 05:01:45.878280 progress 60 % (26 MB)
67 05:01:45.906841 progress 65 % (28 MB)
68 05:01:45.935196 progress 70 % (30 MB)
69 05:01:45.964135 progress 75 % (32 MB)
70 05:01:45.992439 progress 80 % (34 MB)
71 05:01:46.020543 progress 85 % (37 MB)
72 05:01:46.049323 progress 90 % (39 MB)
73 05:01:46.078083 progress 95 % (41 MB)
74 05:01:46.106356 progress 100 % (43 MB)
75 05:01:46.106897 43 MB downloaded in 0.62 s (70.59 MB/s)
76 05:01:46.107370 end: 1.2.1 http-download (duration 00:00:01) [common]
78 05:01:46.108223 end: 1.2 download-retry (duration 00:00:01) [common]
79 05:01:46.108500 start: 1.3 download-retry (timeout 00:09:59) [common]
80 05:01:46.108764 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 05:01:46.109228 downloading http://storage.kernelci.org/next/pending-fixes/v6.12-rc5-243-g2f5e60c44402/arm64/defconfig/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
82 05:01:46.109494 saving as /var/lib/lava/dispatcher/tmp/907044/tftp-deploy-hpxzdqdk/dtb/meson-g12b-a311d-libretech-cc.dtb
83 05:01:46.109701 total size: 54703 (0 MB)
84 05:01:46.109909 No compression specified
85 05:01:46.156628 progress 59 % (0 MB)
86 05:01:46.157500 progress 100 % (0 MB)
87 05:01:46.158124 0 MB downloaded in 0.05 s (1.08 MB/s)
88 05:01:46.158653 end: 1.3.1 http-download (duration 00:00:00) [common]
90 05:01:46.159474 end: 1.3 download-retry (duration 00:00:00) [common]
91 05:01:46.159737 start: 1.4 download-retry (timeout 00:09:59) [common]
92 05:01:46.160022 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 05:01:46.160500 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 05:01:46.160747 saving as /var/lib/lava/dispatcher/tmp/907044/tftp-deploy-hpxzdqdk/nfsrootfs/full.rootfs.tar
95 05:01:46.160950 total size: 120894716 (115 MB)
96 05:01:46.161159 Using unxz to decompress xz
97 05:01:46.204745 progress 0 % (0 MB)
98 05:01:46.998047 progress 5 % (5 MB)
99 05:01:47.837902 progress 10 % (11 MB)
100 05:01:48.632236 progress 15 % (17 MB)
101 05:01:49.374176 progress 20 % (23 MB)
102 05:01:49.973991 progress 25 % (28 MB)
103 05:01:50.804171 progress 30 % (34 MB)
104 05:01:51.591803 progress 35 % (40 MB)
105 05:01:51.964171 progress 40 % (46 MB)
106 05:01:52.351099 progress 45 % (51 MB)
107 05:01:53.070504 progress 50 % (57 MB)
108 05:01:53.947800 progress 55 % (63 MB)
109 05:01:54.724896 progress 60 % (69 MB)
110 05:01:55.477899 progress 65 % (74 MB)
111 05:01:56.262303 progress 70 % (80 MB)
112 05:01:57.112913 progress 75 % (86 MB)
113 05:01:57.911445 progress 80 % (92 MB)
114 05:01:58.679511 progress 85 % (98 MB)
115 05:01:59.534671 progress 90 % (103 MB)
116 05:02:00.315596 progress 95 % (109 MB)
117 05:02:01.148843 progress 100 % (115 MB)
118 05:02:01.161311 115 MB downloaded in 15.00 s (7.69 MB/s)
119 05:02:01.161908 end: 1.4.1 http-download (duration 00:00:15) [common]
121 05:02:01.162723 end: 1.4 download-retry (duration 00:00:15) [common]
122 05:02:01.162987 start: 1.5 download-retry (timeout 00:09:44) [common]
123 05:02:01.163245 start: 1.5.1 http-download (timeout 00:09:44) [common]
124 05:02:01.163755 downloading http://storage.kernelci.org/next/pending-fixes/v6.12-rc5-243-g2f5e60c44402/arm64/defconfig/gcc-12/modules.tar.xz
125 05:02:01.164057 saving as /var/lib/lava/dispatcher/tmp/907044/tftp-deploy-hpxzdqdk/modules/modules.tar
126 05:02:01.164471 total size: 11599752 (11 MB)
127 05:02:01.164885 Using unxz to decompress xz
128 05:02:01.207021 progress 0 % (0 MB)
129 05:02:01.273892 progress 5 % (0 MB)
130 05:02:01.349177 progress 10 % (1 MB)
131 05:02:01.428735 progress 15 % (1 MB)
132 05:02:01.504538 progress 20 % (2 MB)
133 05:02:01.581758 progress 25 % (2 MB)
134 05:02:01.660780 progress 30 % (3 MB)
135 05:02:01.733023 progress 35 % (3 MB)
136 05:02:01.811908 progress 40 % (4 MB)
137 05:02:01.896572 progress 45 % (5 MB)
138 05:02:01.972771 progress 50 % (5 MB)
139 05:02:02.054732 progress 55 % (6 MB)
140 05:02:02.134689 progress 60 % (6 MB)
141 05:02:02.217933 progress 65 % (7 MB)
142 05:02:02.293229 progress 70 % (7 MB)
143 05:02:02.374242 progress 75 % (8 MB)
144 05:02:02.455549 progress 80 % (8 MB)
145 05:02:02.530676 progress 85 % (9 MB)
146 05:02:02.602668 progress 90 % (9 MB)
147 05:02:02.701033 progress 95 % (10 MB)
148 05:02:02.792268 progress 100 % (11 MB)
149 05:02:02.806789 11 MB downloaded in 1.64 s (6.74 MB/s)
150 05:02:02.807390 end: 1.5.1 http-download (duration 00:00:02) [common]
152 05:02:02.808815 end: 1.5 download-retry (duration 00:00:02) [common]
153 05:02:02.809468 start: 1.6 prepare-tftp-overlay (timeout 00:09:43) [common]
154 05:02:02.810079 start: 1.6.1 extract-nfsrootfs (timeout 00:09:43) [common]
155 05:02:19.133927 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/907044/extract-nfsrootfs-yfjabpqz
156 05:02:19.134540 end: 1.6.1 extract-nfsrootfs (duration 00:00:16) [common]
157 05:02:19.134824 start: 1.6.2 lava-overlay (timeout 00:09:26) [common]
158 05:02:19.135561 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/907044/lava-overlay-ard4bfmh
159 05:02:19.136048 makedir: /var/lib/lava/dispatcher/tmp/907044/lava-overlay-ard4bfmh/lava-907044/bin
160 05:02:19.136394 makedir: /var/lib/lava/dispatcher/tmp/907044/lava-overlay-ard4bfmh/lava-907044/tests
161 05:02:19.136710 makedir: /var/lib/lava/dispatcher/tmp/907044/lava-overlay-ard4bfmh/lava-907044/results
162 05:02:19.137043 Creating /var/lib/lava/dispatcher/tmp/907044/lava-overlay-ard4bfmh/lava-907044/bin/lava-add-keys
163 05:02:19.137573 Creating /var/lib/lava/dispatcher/tmp/907044/lava-overlay-ard4bfmh/lava-907044/bin/lava-add-sources
164 05:02:19.138080 Creating /var/lib/lava/dispatcher/tmp/907044/lava-overlay-ard4bfmh/lava-907044/bin/lava-background-process-start
165 05:02:19.138568 Creating /var/lib/lava/dispatcher/tmp/907044/lava-overlay-ard4bfmh/lava-907044/bin/lava-background-process-stop
166 05:02:19.139083 Creating /var/lib/lava/dispatcher/tmp/907044/lava-overlay-ard4bfmh/lava-907044/bin/lava-common-functions
167 05:02:19.139569 Creating /var/lib/lava/dispatcher/tmp/907044/lava-overlay-ard4bfmh/lava-907044/bin/lava-echo-ipv4
168 05:02:19.140145 Creating /var/lib/lava/dispatcher/tmp/907044/lava-overlay-ard4bfmh/lava-907044/bin/lava-install-packages
169 05:02:19.140633 Creating /var/lib/lava/dispatcher/tmp/907044/lava-overlay-ard4bfmh/lava-907044/bin/lava-installed-packages
170 05:02:19.141104 Creating /var/lib/lava/dispatcher/tmp/907044/lava-overlay-ard4bfmh/lava-907044/bin/lava-os-build
171 05:02:19.141572 Creating /var/lib/lava/dispatcher/tmp/907044/lava-overlay-ard4bfmh/lava-907044/bin/lava-probe-channel
172 05:02:19.142044 Creating /var/lib/lava/dispatcher/tmp/907044/lava-overlay-ard4bfmh/lava-907044/bin/lava-probe-ip
173 05:02:19.142535 Creating /var/lib/lava/dispatcher/tmp/907044/lava-overlay-ard4bfmh/lava-907044/bin/lava-target-ip
174 05:02:19.143019 Creating /var/lib/lava/dispatcher/tmp/907044/lava-overlay-ard4bfmh/lava-907044/bin/lava-target-mac
175 05:02:19.143488 Creating /var/lib/lava/dispatcher/tmp/907044/lava-overlay-ard4bfmh/lava-907044/bin/lava-target-storage
176 05:02:19.143968 Creating /var/lib/lava/dispatcher/tmp/907044/lava-overlay-ard4bfmh/lava-907044/bin/lava-test-case
177 05:02:19.144502 Creating /var/lib/lava/dispatcher/tmp/907044/lava-overlay-ard4bfmh/lava-907044/bin/lava-test-event
178 05:02:19.144976 Creating /var/lib/lava/dispatcher/tmp/907044/lava-overlay-ard4bfmh/lava-907044/bin/lava-test-feedback
179 05:02:19.145449 Creating /var/lib/lava/dispatcher/tmp/907044/lava-overlay-ard4bfmh/lava-907044/bin/lava-test-raise
180 05:02:19.145918 Creating /var/lib/lava/dispatcher/tmp/907044/lava-overlay-ard4bfmh/lava-907044/bin/lava-test-reference
181 05:02:19.146410 Creating /var/lib/lava/dispatcher/tmp/907044/lava-overlay-ard4bfmh/lava-907044/bin/lava-test-runner
182 05:02:19.146899 Creating /var/lib/lava/dispatcher/tmp/907044/lava-overlay-ard4bfmh/lava-907044/bin/lava-test-set
183 05:02:19.147367 Creating /var/lib/lava/dispatcher/tmp/907044/lava-overlay-ard4bfmh/lava-907044/bin/lava-test-shell
184 05:02:19.147842 Updating /var/lib/lava/dispatcher/tmp/907044/lava-overlay-ard4bfmh/lava-907044/bin/lava-add-keys (debian)
185 05:02:19.148406 Updating /var/lib/lava/dispatcher/tmp/907044/lava-overlay-ard4bfmh/lava-907044/bin/lava-add-sources (debian)
186 05:02:19.148910 Updating /var/lib/lava/dispatcher/tmp/907044/lava-overlay-ard4bfmh/lava-907044/bin/lava-install-packages (debian)
187 05:02:19.149400 Updating /var/lib/lava/dispatcher/tmp/907044/lava-overlay-ard4bfmh/lava-907044/bin/lava-installed-packages (debian)
188 05:02:19.149884 Updating /var/lib/lava/dispatcher/tmp/907044/lava-overlay-ard4bfmh/lava-907044/bin/lava-os-build (debian)
189 05:02:19.150311 Creating /var/lib/lava/dispatcher/tmp/907044/lava-overlay-ard4bfmh/lava-907044/environment
190 05:02:19.150675 LAVA metadata
191 05:02:19.150933 - LAVA_JOB_ID=907044
192 05:02:19.151147 - LAVA_DISPATCHER_IP=192.168.6.2
193 05:02:19.151504 start: 1.6.2.1 ssh-authorize (timeout 00:09:26) [common]
194 05:02:19.152485 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
195 05:02:19.152809 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:26) [common]
196 05:02:19.153013 skipped lava-vland-overlay
197 05:02:19.153251 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
198 05:02:19.153501 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:26) [common]
199 05:02:19.153716 skipped lava-multinode-overlay
200 05:02:19.153954 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
201 05:02:19.154202 start: 1.6.2.4 test-definition (timeout 00:09:26) [common]
202 05:02:19.154450 Loading test definitions
203 05:02:19.154719 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:26) [common]
204 05:02:19.154934 Using /lava-907044 at stage 0
205 05:02:19.156077 uuid=907044_1.6.2.4.1 testdef=None
206 05:02:19.156394 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
207 05:02:19.156655 start: 1.6.2.4.2 test-overlay (timeout 00:09:26) [common]
208 05:02:19.158208 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
210 05:02:19.158989 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:26) [common]
211 05:02:19.160921 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
213 05:02:19.161747 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:26) [common]
214 05:02:19.163549 runner path: /var/lib/lava/dispatcher/tmp/907044/lava-overlay-ard4bfmh/lava-907044/0/tests/0_timesync-off test_uuid 907044_1.6.2.4.1
215 05:02:19.164113 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
217 05:02:19.164921 start: 1.6.2.4.5 git-repo-action (timeout 00:09:26) [common]
218 05:02:19.165142 Using /lava-907044 at stage 0
219 05:02:19.165487 Fetching tests from https://github.com/kernelci/test-definitions.git
220 05:02:19.165774 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/907044/lava-overlay-ard4bfmh/lava-907044/0/tests/1_kselftest-rtc'
221 05:02:22.603975 Running '/usr/bin/git checkout kernelci.org
222 05:02:23.051226 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/907044/lava-overlay-ard4bfmh/lava-907044/0/tests/1_kselftest-rtc/automated/linux/kselftest/kselftest.yaml
223 05:02:23.052685 uuid=907044_1.6.2.4.5 testdef=None
224 05:02:23.053030 end: 1.6.2.4.5 git-repo-action (duration 00:00:04) [common]
226 05:02:23.053766 start: 1.6.2.4.6 test-overlay (timeout 00:09:22) [common]
227 05:02:23.056630 end: 1.6.2.4.6 test-overlay (duration 00:00:00) [common]
229 05:02:23.057442 start: 1.6.2.4.7 test-install-overlay (timeout 00:09:22) [common]
230 05:02:23.061142 end: 1.6.2.4.7 test-install-overlay (duration 00:00:00) [common]
232 05:02:23.061994 start: 1.6.2.4.8 test-runscript-overlay (timeout 00:09:22) [common]
233 05:02:23.065548 runner path: /var/lib/lava/dispatcher/tmp/907044/lava-overlay-ard4bfmh/lava-907044/0/tests/1_kselftest-rtc test_uuid 907044_1.6.2.4.5
234 05:02:23.065830 BOARD='meson-g12b-a311d-libretech-cc'
235 05:02:23.066033 BRANCH='next'
236 05:02:23.066227 SKIPFILE='/dev/null'
237 05:02:23.066422 SKIP_INSTALL='True'
238 05:02:23.066615 TESTPROG_URL='http://storage.kernelci.org/next/pending-fixes/v6.12-rc5-243-g2f5e60c44402/arm64/defconfig/gcc-12/kselftest.tar.xz'
239 05:02:23.066813 TST_CASENAME=''
240 05:02:23.067007 TST_CMDFILES='rtc'
241 05:02:23.067549 end: 1.6.2.4.8 test-runscript-overlay (duration 00:00:00) [common]
243 05:02:23.068353 Creating lava-test-runner.conf files
244 05:02:23.068557 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/907044/lava-overlay-ard4bfmh/lava-907044/0 for stage 0
245 05:02:23.068903 - 0_timesync-off
246 05:02:23.069137 - 1_kselftest-rtc
247 05:02:23.069458 end: 1.6.2.4 test-definition (duration 00:00:04) [common]
248 05:02:23.069733 start: 1.6.2.5 compress-overlay (timeout 00:09:22) [common]
249 05:02:46.478246 end: 1.6.2.5 compress-overlay (duration 00:00:23) [common]
250 05:02:46.478704 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:08:59) [common]
251 05:02:46.479001 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
252 05:02:46.479309 end: 1.6.2 lava-overlay (duration 00:00:27) [common]
253 05:02:46.479604 start: 1.6.3 extract-overlay-ramdisk (timeout 00:08:59) [common]
254 05:02:47.174052 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:01) [common]
255 05:02:47.174540 start: 1.6.4 extract-modules (timeout 00:08:58) [common]
256 05:02:47.174793 extracting modules file /var/lib/lava/dispatcher/tmp/907044/tftp-deploy-hpxzdqdk/modules/modules.tar to /var/lib/lava/dispatcher/tmp/907044/extract-nfsrootfs-yfjabpqz
257 05:02:48.525621 extracting modules file /var/lib/lava/dispatcher/tmp/907044/tftp-deploy-hpxzdqdk/modules/modules.tar to /var/lib/lava/dispatcher/tmp/907044/extract-overlay-ramdisk-866un_fv/ramdisk
258 05:02:50.244709 end: 1.6.4 extract-modules (duration 00:00:03) [common]
259 05:02:50.245204 start: 1.6.5 apply-overlay-tftp (timeout 00:08:55) [common]
260 05:02:50.245485 [common] Applying overlay to NFS
261 05:02:50.245702 [common] Applying overlay /var/lib/lava/dispatcher/tmp/907044/compress-overlay-w0s_tn5m/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/907044/extract-nfsrootfs-yfjabpqz
262 05:02:52.975448 end: 1.6.5 apply-overlay-tftp (duration 00:00:03) [common]
263 05:02:52.975927 start: 1.6.6 prepare-kernel (timeout 00:08:52) [common]
264 05:02:52.976231 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:08:52) [common]
265 05:02:52.976465 Converting downloaded kernel to a uImage
266 05:02:52.976775 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/907044/tftp-deploy-hpxzdqdk/kernel/Image /var/lib/lava/dispatcher/tmp/907044/tftp-deploy-hpxzdqdk/kernel/uImage
267 05:02:53.501095 output: Image Name:
268 05:02:53.501529 output: Created: Tue Oct 29 05:02:52 2024
269 05:02:53.501752 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
270 05:02:53.501966 output: Data Size: 45713920 Bytes = 44642.50 KiB = 43.60 MiB
271 05:02:53.502172 output: Load Address: 01080000
272 05:02:53.502375 output: Entry Point: 01080000
273 05:02:53.502576 output:
274 05:02:53.502912 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:01) [common]
275 05:02:53.503189 end: 1.6.6 prepare-kernel (duration 00:00:01) [common]
276 05:02:53.503463 start: 1.6.7 configure-preseed-file (timeout 00:08:52) [common]
277 05:02:53.503723 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
278 05:02:53.504012 start: 1.6.8 compress-ramdisk (timeout 00:08:52) [common]
279 05:02:53.504289 Building ramdisk /var/lib/lava/dispatcher/tmp/907044/extract-overlay-ramdisk-866un_fv/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/907044/extract-overlay-ramdisk-866un_fv/ramdisk
280 05:02:55.657662 >> 166814 blocks
281 05:03:03.421657 Adding RAMdisk u-boot header.
282 05:03:03.422107 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/907044/extract-overlay-ramdisk-866un_fv/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/907044/extract-overlay-ramdisk-866un_fv/ramdisk.cpio.gz.uboot
283 05:03:03.670879 output: Image Name:
284 05:03:03.671309 output: Created: Tue Oct 29 05:03:03 2024
285 05:03:03.671521 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
286 05:03:03.671723 output: Data Size: 23433234 Bytes = 22884.02 KiB = 22.35 MiB
287 05:03:03.671924 output: Load Address: 00000000
288 05:03:03.672418 output: Entry Point: 00000000
289 05:03:03.672866 output:
290 05:03:03.674007 rename /var/lib/lava/dispatcher/tmp/907044/extract-overlay-ramdisk-866un_fv/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/907044/tftp-deploy-hpxzdqdk/ramdisk/ramdisk.cpio.gz.uboot
291 05:03:03.674810 end: 1.6.8 compress-ramdisk (duration 00:00:10) [common]
292 05:03:03.675404 end: 1.6 prepare-tftp-overlay (duration 00:01:01) [common]
293 05:03:03.676015 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:42) [common]
294 05:03:03.676539 No LXC device requested
295 05:03:03.677091 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
296 05:03:03.677648 start: 1.8 deploy-device-env (timeout 00:08:42) [common]
297 05:03:03.678190 end: 1.8 deploy-device-env (duration 00:00:00) [common]
298 05:03:03.678639 Checking files for TFTP limit of 4294967296 bytes.
299 05:03:03.681687 end: 1 tftp-deploy (duration 00:01:18) [common]
300 05:03:03.682325 start: 2 uboot-action (timeout 00:05:00) [common]
301 05:03:03.682894 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
302 05:03:03.683434 end: 2.1 uboot-from-media (duration 00:00:00) [common]
303 05:03:03.684009 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
304 05:03:03.684619 Using kernel file from prepare-kernel: 907044/tftp-deploy-hpxzdqdk/kernel/uImage
305 05:03:03.685305 substitutions:
306 05:03:03.685752 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
307 05:03:03.686189 - {DTB_ADDR}: 0x01070000
308 05:03:03.686629 - {DTB}: 907044/tftp-deploy-hpxzdqdk/dtb/meson-g12b-a311d-libretech-cc.dtb
309 05:03:03.687067 - {INITRD}: 907044/tftp-deploy-hpxzdqdk/ramdisk/ramdisk.cpio.gz.uboot
310 05:03:03.687501 - {KERNEL_ADDR}: 0x01080000
311 05:03:03.687935 - {KERNEL}: 907044/tftp-deploy-hpxzdqdk/kernel/uImage
312 05:03:03.688471 - {LAVA_MAC}: None
313 05:03:03.688947 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/907044/extract-nfsrootfs-yfjabpqz
314 05:03:03.689383 - {NFS_SERVER_IP}: 192.168.6.2
315 05:03:03.689810 - {PRESEED_CONFIG}: None
316 05:03:03.690236 - {PRESEED_LOCAL}: None
317 05:03:03.690662 - {RAMDISK_ADDR}: 0x08000000
318 05:03:03.691084 - {RAMDISK}: 907044/tftp-deploy-hpxzdqdk/ramdisk/ramdisk.cpio.gz.uboot
319 05:03:03.691510 - {ROOT_PART}: None
320 05:03:03.691935 - {ROOT}: None
321 05:03:03.692394 - {SERVER_IP}: 192.168.6.2
322 05:03:03.692817 - {TEE_ADDR}: 0x83000000
323 05:03:03.693239 - {TEE}: None
324 05:03:03.693659 Parsed boot commands:
325 05:03:03.694071 - setenv autoload no
326 05:03:03.694491 - setenv initrd_high 0xffffffff
327 05:03:03.694909 - setenv fdt_high 0xffffffff
328 05:03:03.695325 - dhcp
329 05:03:03.695741 - setenv serverip 192.168.6.2
330 05:03:03.696196 - tftpboot 0x01080000 907044/tftp-deploy-hpxzdqdk/kernel/uImage
331 05:03:03.696626 - tftpboot 0x08000000 907044/tftp-deploy-hpxzdqdk/ramdisk/ramdisk.cpio.gz.uboot
332 05:03:03.697048 - tftpboot 0x01070000 907044/tftp-deploy-hpxzdqdk/dtb/meson-g12b-a311d-libretech-cc.dtb
333 05:03:03.697472 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/907044/extract-nfsrootfs-yfjabpqz,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
334 05:03:03.697909 - bootm 0x01080000 0x08000000 0x01070000
335 05:03:03.698462 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
337 05:03:03.700109 start: 2.3 connect-device (timeout 00:05:00) [common]
338 05:03:03.700582 [common] connect-device Connecting to device using 'telnet conserv1 3007'
339 05:03:03.714540 Setting prompt string to ['lava-test: # ']
340 05:03:03.715497 end: 2.3 connect-device (duration 00:00:00) [common]
341 05:03:03.715887 start: 2.4 uboot-commands (timeout 00:05:00) [common]
342 05:03:03.716276 start: 2.4.1 reset-device (timeout 00:05:00) [common]
343 05:03:03.716581 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
344 05:03:03.717211 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
345 05:03:03.752648 >> OK - accepted request
346 05:03:03.754791 Returned 0 in 0 seconds
347 05:03:03.855969 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
349 05:03:03.857781 end: 2.4.1 reset-device (duration 00:00:00) [common]
350 05:03:03.858390 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
351 05:03:03.858943 Setting prompt string to ['Hit any key to stop autoboot']
352 05:03:03.859424 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
353 05:03:03.861165 Trying 192.168.56.21...
354 05:03:03.861705 Connected to conserv1.
355 05:03:03.862152 Escape character is '^]'.
356 05:03:03.862610
357 05:03:03.863068 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
358 05:03:03.863528
359 05:03:14.865824 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.�!,K��х��}���с0x01
360 05:03:14.866513 bl2_stage_init 0x81
361 05:03:14.871333 hw id: 0x0000 - pwm id 0x01
362 05:03:14.871849 bl2_stage_init 0xc1
363 05:03:14.872357 bl2_stage_init 0x02
364 05:03:14.872808
365 05:03:14.876804 L0:00000000
366 05:03:14.877290 L1:20000703
367 05:03:14.877746 L2:00008067
368 05:03:14.878190 L3:14000000
369 05:03:14.878630 B2:00402000
370 05:03:14.882463 B1:e0f83180
371 05:03:14.882945
372 05:03:14.883387 TE: 58150
373 05:03:14.883818
374 05:03:14.888075 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
375 05:03:14.888542
376 05:03:14.888976 Board ID = 1
377 05:03:14.893577 Set A53 clk to 24M
378 05:03:14.894063 Set A73 clk to 24M
379 05:03:14.894492 Set clk81 to 24M
380 05:03:14.899333 A53 clk: 1200 MHz
381 05:03:14.899795 A73 clk: 1200 MHz
382 05:03:14.900258 CLK81: 166.6M
383 05:03:14.900686 smccc: 00012aab
384 05:03:14.904839 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
385 05:03:14.910435 board id: 1
386 05:03:14.916458 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
387 05:03:14.926845 fw parse done
388 05:03:14.932766 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
389 05:03:14.975399 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
390 05:03:14.986277 PIEI prepare done
391 05:03:14.986753 fastboot data load
392 05:03:14.987188 fastboot data verify
393 05:03:14.991899 verify result: 266
394 05:03:14.997518 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
395 05:03:14.998006 LPDDR4 probe
396 05:03:14.998456 ddr clk to 1584MHz
397 05:03:15.005496 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
398 05:03:15.042723
399 05:03:15.043229 dmc_version 0001
400 05:03:15.049462 Check phy result
401 05:03:15.055254 INFO : End of CA training
402 05:03:15.055724 INFO : End of initialization
403 05:03:15.060907 INFO : Training has run successfully!
404 05:03:15.061384 Check phy result
405 05:03:15.066537 INFO : End of initialization
406 05:03:15.067004 INFO : End of read enable training
407 05:03:15.072145 INFO : End of fine write leveling
408 05:03:15.077761 INFO : End of Write leveling coarse delay
409 05:03:15.078317 INFO : Training has run successfully!
410 05:03:15.078794 Check phy result
411 05:03:15.083262 INFO : End of initialization
412 05:03:15.083755 INFO : End of read dq deskew training
413 05:03:15.088907 INFO : End of MPR read delay center optimization
414 05:03:15.094794 INFO : End of write delay center optimization
415 05:03:15.100106 INFO : End of read delay center optimization
416 05:03:15.100600 INFO : End of max read latency training
417 05:03:15.105739 INFO : Training has run successfully!
418 05:03:15.106218 1D training succeed
419 05:03:15.114914 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
420 05:03:15.162531 Check phy result
421 05:03:15.163054 INFO : End of initialization
422 05:03:15.185172 INFO : End of 2D read delay Voltage center optimization
423 05:03:15.205370 INFO : End of 2D read delay Voltage center optimization
424 05:03:15.257443 INFO : End of 2D write delay Voltage center optimization
425 05:03:15.307006 INFO : End of 2D write delay Voltage center optimization
426 05:03:15.312395 INFO : Training has run successfully!
427 05:03:15.312889
428 05:03:15.313345 channel==0
429 05:03:15.317959 RxClkDly_Margin_A0==88 ps 9
430 05:03:15.318436 TxDqDly_Margin_A0==98 ps 10
431 05:03:15.321345 RxClkDly_Margin_A1==88 ps 9
432 05:03:15.321828 TxDqDly_Margin_A1==88 ps 9
433 05:03:15.326938 TrainedVREFDQ_A0==74
434 05:03:15.327415 TrainedVREFDQ_A1==74
435 05:03:15.327864 VrefDac_Margin_A0==25
436 05:03:15.332574 DeviceVref_Margin_A0==40
437 05:03:15.333053 VrefDac_Margin_A1==25
438 05:03:15.338158 DeviceVref_Margin_A1==40
439 05:03:15.338628
440 05:03:15.339077
441 05:03:15.339519 channel==1
442 05:03:15.339957 RxClkDly_Margin_A0==98 ps 10
443 05:03:15.341536 TxDqDly_Margin_A0==98 ps 10
444 05:03:15.347075 RxClkDly_Margin_A1==98 ps 10
445 05:03:15.347548 TxDqDly_Margin_A1==88 ps 9
446 05:03:15.348027 TrainedVREFDQ_A0==77
447 05:03:15.352655 TrainedVREFDQ_A1==77
448 05:03:15.353143 VrefDac_Margin_A0==22
449 05:03:15.358399 DeviceVref_Margin_A0==37
450 05:03:15.358877 VrefDac_Margin_A1==22
451 05:03:15.359324 DeviceVref_Margin_A1==37
452 05:03:15.359855
453 05:03:15.367267 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
454 05:03:15.367761
455 05:03:15.395525 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000018 00000019 00000017 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000017 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
456 05:03:15.396168 2D training succeed
457 05:03:15.406534 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
458 05:03:15.407205 auto size-- 65535DDR cs0 size: 2048MB
459 05:03:15.407676 DDR cs1 size: 2048MB
460 05:03:15.412098 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
461 05:03:15.412616 cs0 DataBus test pass
462 05:03:15.417701 cs1 DataBus test pass
463 05:03:15.418241 cs0 AddrBus test pass
464 05:03:15.423347 cs1 AddrBus test pass
465 05:03:15.423885
466 05:03:15.424386 100bdlr_step_size ps== 420
467 05:03:15.424894 result report
468 05:03:15.429009 boot times 0Enable ddr reg access
469 05:03:15.439407 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
470 05:03:15.448788 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
471 05:03:16.022915 0.0;M3 CHK:0;cm4_sp_mode 0
472 05:03:16.023564 MVN_1=0x00000000
473 05:03:16.027831 MVN_2=0x00000000
474 05:03:16.033659 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
475 05:03:16.034188 OPS=0x10
476 05:03:16.034655 ring efuse init
477 05:03:16.035105 chipver efuse init
478 05:03:16.039378 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
479 05:03:16.044866 [0.018961 Inits done]
480 05:03:16.045392 secure task start!
481 05:03:16.045854 high task start!
482 05:03:16.049452 low task start!
483 05:03:16.049987 run into bl31
484 05:03:16.056133 NOTICE: BL31: v1.3(release):4fc40b1
485 05:03:16.063922 NOTICE: BL31: Built : 15:58:17, May 22 2019
486 05:03:16.064470 NOTICE: BL31: G12A normal boot!
487 05:03:16.089223 NOTICE: BL31: BL33 decompress pass
488 05:03:16.094812 ERROR: Error initializing runtime service opteed_fast
489 05:03:17.327857
490 05:03:17.328477
491 05:03:17.336188 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
492 05:03:17.336682
493 05:03:17.337142 Model: Libre Computer AML-A311D-CC Alta
494 05:03:17.544745 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
495 05:03:17.568083 DRAM: 2 GiB (effective 3.8 GiB)
496 05:03:17.711031 Core: 408 devices, 31 uclasses, devicetree: separate
497 05:03:17.716867 WDT: Not starting watchdog@f0d0
498 05:03:17.749196 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
499 05:03:17.761594 Loading Environment from FAT... Card did not respond to voltage select! : -110
500 05:03:17.766592 ** Bad device specification mmc 0 **
501 05:03:17.776889 Card did not respond to voltage select! : -110
502 05:03:17.783701 ** Bad device specification mmc 0 **
503 05:03:17.784303 Couldn't find partition mmc 0
504 05:03:17.792934 Card did not respond to voltage select! : -110
505 05:03:17.798611 ** Bad device specification mmc 0 **
506 05:03:17.799088 Couldn't find partition mmc 0
507 05:03:17.803505 Error: could not access storage.
508 05:03:19.065879 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
509 05:03:19.066497 bl2_stage_init 0x01
510 05:03:19.066941 bl2_stage_init 0x81
511 05:03:19.071560 hw id: 0x0000 - pwm id 0x01
512 05:03:19.072087 bl2_stage_init 0xc1
513 05:03:19.072517 bl2_stage_init 0x02
514 05:03:19.072926
515 05:03:19.077101 L0:00000000
516 05:03:19.077586 L1:20000703
517 05:03:19.077998 L2:00008067
518 05:03:19.078402 L3:14000000
519 05:03:19.079960 B2:00402000
520 05:03:19.080463 B1:e0f83180
521 05:03:19.080877
522 05:03:19.081283 TE: 58124
523 05:03:19.081682
524 05:03:19.091100 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
525 05:03:19.091606
526 05:03:19.092060 Board ID = 1
527 05:03:19.092472 Set A53 clk to 24M
528 05:03:19.092869 Set A73 clk to 24M
529 05:03:19.096959 Set clk81 to 24M
530 05:03:19.097460 A53 clk: 1200 MHz
531 05:03:19.097872 A73 clk: 1200 MHz
532 05:03:19.102410 CLK81: 166.6M
533 05:03:19.102891 smccc: 00012a92
534 05:03:19.107966 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
535 05:03:19.108480 board id: 1
536 05:03:19.116563 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
537 05:03:19.127202 fw parse done
538 05:03:19.133156 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
539 05:03:19.175794 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
540 05:03:19.186845 PIEI prepare done
541 05:03:19.187369 fastboot data load
542 05:03:19.187792 fastboot data verify
543 05:03:19.192422 verify result: 266
544 05:03:19.198021 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
545 05:03:19.198509 LPDDR4 probe
546 05:03:19.198922 ddr clk to 1584MHz
547 05:03:19.206009 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
548 05:03:19.243238
549 05:03:19.243762 dmc_version 0001
550 05:03:19.249940 Check phy result
551 05:03:19.255838 INFO : End of CA training
552 05:03:19.256359 INFO : End of initialization
553 05:03:19.261396 INFO : Training has run successfully!
554 05:03:19.261879 Check phy result
555 05:03:19.266976 INFO : End of initialization
556 05:03:19.267463 INFO : End of read enable training
557 05:03:19.272570 INFO : End of fine write leveling
558 05:03:19.278152 INFO : End of Write leveling coarse delay
559 05:03:19.278641 INFO : Training has run successfully!
560 05:03:19.279054 Check phy result
561 05:03:19.283891 INFO : End of initialization
562 05:03:19.284416 INFO : End of read dq deskew training
563 05:03:19.289666 INFO : End of MPR read delay center optimization
564 05:03:19.295024 INFO : End of write delay center optimization
565 05:03:19.300621 INFO : End of read delay center optimization
566 05:03:19.301161 INFO : End of max read latency training
567 05:03:19.306261 INFO : Training has run successfully!
568 05:03:19.306792 1D training succeed
569 05:03:19.315317 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
570 05:03:19.363002 Check phy result
571 05:03:19.363535 INFO : End of initialization
572 05:03:19.384621 INFO : End of 2D read delay Voltage center optimization
573 05:03:19.404651 INFO : End of 2D read delay Voltage center optimization
574 05:03:19.456657 INFO : End of 2D write delay Voltage center optimization
575 05:03:19.505794 INFO : End of 2D write delay Voltage center optimization
576 05:03:19.511347 INFO : Training has run successfully!
577 05:03:19.511836
578 05:03:19.512301 channel==0
579 05:03:19.516957 RxClkDly_Margin_A0==88 ps 9
580 05:03:19.517438 TxDqDly_Margin_A0==98 ps 10
581 05:03:19.522575 RxClkDly_Margin_A1==88 ps 9
582 05:03:19.523053 TxDqDly_Margin_A1==98 ps 10
583 05:03:19.523464 TrainedVREFDQ_A0==74
584 05:03:19.528182 TrainedVREFDQ_A1==74
585 05:03:19.528672 VrefDac_Margin_A0==25
586 05:03:19.529084 DeviceVref_Margin_A0==40
587 05:03:19.533769 VrefDac_Margin_A1==25
588 05:03:19.534269 DeviceVref_Margin_A1==40
589 05:03:19.534681
590 05:03:19.535085
591 05:03:19.539344 channel==1
592 05:03:19.539823 RxClkDly_Margin_A0==98 ps 10
593 05:03:19.540272 TxDqDly_Margin_A0==88 ps 9
594 05:03:19.544959 RxClkDly_Margin_A1==88 ps 9
595 05:03:19.545442 TxDqDly_Margin_A1==88 ps 9
596 05:03:19.550542 TrainedVREFDQ_A0==77
597 05:03:19.551031 TrainedVREFDQ_A1==77
598 05:03:19.551442 VrefDac_Margin_A0==22
599 05:03:19.556212 DeviceVref_Margin_A0==37
600 05:03:19.556686 VrefDac_Margin_A1==24
601 05:03:19.561724 DeviceVref_Margin_A1==37
602 05:03:19.562200
603 05:03:19.562612 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
604 05:03:19.563014
605 05:03:19.595307 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000018 00000019 00000018 00000019 0000001a 00000018 00000016 00000018 00000017 0000001a 00000018 00000018 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
606 05:03:19.595873 2D training succeed
607 05:03:19.601013 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
608 05:03:19.606556 auto size-- 65535DDR cs0 size: 2048MB
609 05:03:19.607045 DDR cs1 size: 2048MB
610 05:03:19.612247 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
611 05:03:19.612919 cs0 DataBus test pass
612 05:03:19.617774 cs1 DataBus test pass
613 05:03:19.618287 cs0 AddrBus test pass
614 05:03:19.618710 cs1 AddrBus test pass
615 05:03:19.619112
616 05:03:19.623345 100bdlr_step_size ps== 420
617 05:03:19.623840 result report
618 05:03:19.628968 boot times 0Enable ddr reg access
619 05:03:19.634221 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
620 05:03:19.647608 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
621 05:03:20.219809 0.0;M3 CHK:0;cm4_sp_mode 0
622 05:03:20.220463 MVN_1=0x00000000
623 05:03:20.225149 MVN_2=0x00000000
624 05:03:20.230955 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
625 05:03:20.231447 OPS=0x10
626 05:03:20.231853 ring efuse init
627 05:03:20.232298 chipver efuse init
628 05:03:20.236565 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
629 05:03:20.242058 [0.018961 Inits done]
630 05:03:20.242518 secure task start!
631 05:03:20.242908 high task start!
632 05:03:20.246649 low task start!
633 05:03:20.247112 run into bl31
634 05:03:20.253563 NOTICE: BL31: v1.3(release):4fc40b1
635 05:03:20.261114 NOTICE: BL31: Built : 15:58:17, May 22 2019
636 05:03:20.261582 NOTICE: BL31: G12A normal boot!
637 05:03:20.287154 NOTICE: BL31: BL33 decompress pass
638 05:03:20.293486 ERROR: Error initializing runtime service opteed_fast
639 05:03:21.525769
640 05:03:21.526402
641 05:03:21.534293 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
642 05:03:21.534775
643 05:03:21.535196 Model: Libre Computer AML-A311D-CC Alta
644 05:03:21.742775 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
645 05:03:21.765984 DRAM: 2 GiB (effective 3.8 GiB)
646 05:03:21.908835 Core: 408 devices, 31 uclasses, devicetree: separate
647 05:03:21.914799 WDT: Not starting watchdog@f0d0
648 05:03:21.947149 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
649 05:03:21.959435 Loading Environment from FAT... Card did not respond to voltage select! : -110
650 05:03:21.964498 ** Bad device specification mmc 0 **
651 05:03:21.974819 Card did not respond to voltage select! : -110
652 05:03:21.982385 ** Bad device specification mmc 0 **
653 05:03:21.982855 Couldn't find partition mmc 0
654 05:03:21.990866 Card did not respond to voltage select! : -110
655 05:03:21.996292 ** Bad device specification mmc 0 **
656 05:03:21.996757 Couldn't find partition mmc 0
657 05:03:22.001380 Error: could not access storage.
658 05:03:22.344874 Net: eth0: ethernet@ff3f0000
659 05:03:22.345474 starting USB...
660 05:03:22.596857 Bus usb@ff500000: Register 3000140 NbrPorts 3
661 05:03:22.597471 Starting the controller
662 05:03:22.603726 USB XHCI 1.10
663 05:03:24.314874 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
664 05:03:24.315503 bl2_stage_init 0x01
665 05:03:24.315925 bl2_stage_init 0x81
666 05:03:24.320301 hw id: 0x0000 - pwm id 0x01
667 05:03:24.320771 bl2_stage_init 0xc1
668 05:03:24.321181 bl2_stage_init 0x02
669 05:03:24.321585
670 05:03:24.325959 L0:00000000
671 05:03:24.326424 L1:20000703
672 05:03:24.326830 L2:00008067
673 05:03:24.327229 L3:14000000
674 05:03:24.328897 B2:00402000
675 05:03:24.329353 B1:e0f83180
676 05:03:24.329760
677 05:03:24.330160 TE: 58159
678 05:03:24.330558
679 05:03:24.339912 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
680 05:03:24.340416
681 05:03:24.340827 Board ID = 1
682 05:03:24.341225 Set A53 clk to 24M
683 05:03:24.341624 Set A73 clk to 24M
684 05:03:24.345634 Set clk81 to 24M
685 05:03:24.346096 A53 clk: 1200 MHz
686 05:03:24.346498 A73 clk: 1200 MHz
687 05:03:24.349133 CLK81: 166.6M
688 05:03:24.349595 smccc: 00012ab5
689 05:03:24.354528 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
690 05:03:24.360158 board id: 1
691 05:03:24.365330 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
692 05:03:24.375968 fw parse done
693 05:03:24.381953 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
694 05:03:24.424594 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
695 05:03:24.435667 PIEI prepare done
696 05:03:24.436182 fastboot data load
697 05:03:24.436596 fastboot data verify
698 05:03:24.441127 verify result: 266
699 05:03:24.446736 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
700 05:03:24.447196 LPDDR4 probe
701 05:03:24.447603 ddr clk to 1584MHz
702 05:03:24.454693 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
703 05:03:24.492085
704 05:03:24.492569 dmc_version 0001
705 05:03:24.498809 Check phy result
706 05:03:24.504715 INFO : End of CA training
707 05:03:24.505176 INFO : End of initialization
708 05:03:24.510200 INFO : Training has run successfully!
709 05:03:24.510656 Check phy result
710 05:03:24.515787 INFO : End of initialization
711 05:03:24.516273 INFO : End of read enable training
712 05:03:24.521335 INFO : End of fine write leveling
713 05:03:24.526936 INFO : End of Write leveling coarse delay
714 05:03:24.527395 INFO : Training has run successfully!
715 05:03:24.527795 Check phy result
716 05:03:24.532642 INFO : End of initialization
717 05:03:24.533100 INFO : End of read dq deskew training
718 05:03:24.538140 INFO : End of MPR read delay center optimization
719 05:03:24.544012 INFO : End of write delay center optimization
720 05:03:24.549421 INFO : End of read delay center optimization
721 05:03:24.549881 INFO : End of max read latency training
722 05:03:24.554944 INFO : Training has run successfully!
723 05:03:24.555403 1D training succeed
724 05:03:24.564214 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
725 05:03:24.611813 Check phy result
726 05:03:24.612356 INFO : End of initialization
727 05:03:24.633425 INFO : End of 2D read delay Voltage center optimization
728 05:03:24.652647 INFO : End of 2D read delay Voltage center optimization
729 05:03:24.704545 INFO : End of 2D write delay Voltage center optimization
730 05:03:24.753958 INFO : End of 2D write delay Voltage center optimization
731 05:03:24.759461 INFO : Training has run successfully!
732 05:03:24.759928
733 05:03:24.760387 channel==0
734 05:03:24.764891 RxClkDly_Margin_A0==88 ps 9
735 05:03:24.765351 TxDqDly_Margin_A0==98 ps 10
736 05:03:24.768257 RxClkDly_Margin_A1==88 ps 9
737 05:03:24.768715 TxDqDly_Margin_A1==88 ps 9
738 05:03:24.773746 TrainedVREFDQ_A0==74
739 05:03:24.774204 TrainedVREFDQ_A1==74
740 05:03:24.774613 VrefDac_Margin_A0==25
741 05:03:24.779324 DeviceVref_Margin_A0==40
742 05:03:24.779781 VrefDac_Margin_A1==25
743 05:03:24.785045 DeviceVref_Margin_A1==40
744 05:03:24.785501
745 05:03:24.785910
746 05:03:24.786307 channel==1
747 05:03:24.786700 RxClkDly_Margin_A0==88 ps 9
748 05:03:24.788506 TxDqDly_Margin_A0==98 ps 10
749 05:03:24.793966 RxClkDly_Margin_A1==88 ps 9
750 05:03:24.794440 TxDqDly_Margin_A1==88 ps 9
751 05:03:24.794852 TrainedVREFDQ_A0==77
752 05:03:24.799754 TrainedVREFDQ_A1==77
753 05:03:24.800246 VrefDac_Margin_A0==23
754 05:03:24.805241 DeviceVref_Margin_A0==37
755 05:03:24.805702 VrefDac_Margin_A1==24
756 05:03:24.806103 DeviceVref_Margin_A1==37
757 05:03:24.806501
758 05:03:24.810904 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
759 05:03:24.811367
760 05:03:24.844397 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000017 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000018 00000019 00000018 00000019 0000001a 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
761 05:03:24.844924 2D training succeed
762 05:03:24.850005 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
763 05:03:24.855639 auto size-- 65535DDR cs0 size: 2048MB
764 05:03:24.856134 DDR cs1 size: 2048MB
765 05:03:24.861178 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
766 05:03:24.861640 cs0 DataBus test pass
767 05:03:24.862046 cs1 DataBus test pass
768 05:03:24.866719 cs0 AddrBus test pass
769 05:03:24.867175 cs1 AddrBus test pass
770 05:03:24.867576
771 05:03:24.872400 100bdlr_step_size ps== 420
772 05:03:24.872869 result report
773 05:03:24.873274 boot times 0Enable ddr reg access
774 05:03:24.881907 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
775 05:03:24.895455 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
776 05:03:25.467514 0.0;M3 CHK:0;cm4_sp_mode 0
777 05:03:25.468156 MVN_1=0x00000000
778 05:03:25.472916 MVN_2=0x00000000
779 05:03:25.478705 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
780 05:03:25.479197 OPS=0x10
781 05:03:25.479591 ring efuse init
782 05:03:25.480031 chipver efuse init
783 05:03:25.484263 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
784 05:03:25.489919 [0.018961 Inits done]
785 05:03:25.490374 secure task start!
786 05:03:25.490764 high task start!
787 05:03:25.494426 low task start!
788 05:03:25.494876 run into bl31
789 05:03:25.501104 NOTICE: BL31: v1.3(release):4fc40b1
790 05:03:25.507929 NOTICE: BL31: Built : 15:58:17, May 22 2019
791 05:03:25.508415 NOTICE: BL31: G12A normal boot!
792 05:03:25.534328 NOTICE: BL31: BL33 decompress pass
793 05:03:25.540057 ERROR: Error initializing runtime service opteed_fast
794 05:03:26.773170
795 05:03:26.773800
796 05:03:26.781442 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
797 05:03:26.781924
798 05:03:26.782343 Model: Libre Computer AML-A311D-CC Alta
799 05:03:26.989766 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
800 05:03:27.013186 DRAM: 2 GiB (effective 3.8 GiB)
801 05:03:27.156143 Core: 408 devices, 31 uclasses, devicetree: separate
802 05:03:27.162034 WDT: Not starting watchdog@f0d0
803 05:03:27.194224 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
804 05:03:27.206677 Loading Environment from FAT... Card did not respond to voltage select! : -110
805 05:03:27.211724 ** Bad device specification mmc 0 **
806 05:03:27.222036 Card did not respond to voltage select! : -110
807 05:03:27.229710 ** Bad device specification mmc 0 **
808 05:03:27.230181 Couldn't find partition mmc 0
809 05:03:27.238028 Card did not respond to voltage select! : -110
810 05:03:27.243566 ** Bad device specification mmc 0 **
811 05:03:27.244063 Couldn't find partition mmc 0
812 05:03:27.248588 Error: could not access storage.
813 05:03:27.592116 Net: eth0: ethernet@ff3f0000
814 05:03:27.592700 starting USB...
815 05:03:27.844167 Bus usb@ff500000: Register 3000140 NbrPorts 3
816 05:03:27.844727 Starting the controller
817 05:03:27.850973 USB XHCI 1.10
818 05:03:30.015589 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
819 05:03:30.016210 bl2_stage_init 0x01
820 05:03:30.016632 bl2_stage_init 0x81
821 05:03:30.021403 hw id: 0x0000 - pwm id 0x01
822 05:03:30.021869 bl2_stage_init 0xc1
823 05:03:30.022281 bl2_stage_init 0x02
824 05:03:30.022683
825 05:03:30.026804 L0:00000000
826 05:03:30.027270 L1:20000703
827 05:03:30.027676 L2:00008067
828 05:03:30.028100 L3:14000000
829 05:03:30.029769 B2:00402000
830 05:03:30.030223 B1:e0f83180
831 05:03:30.030632
832 05:03:30.031032 TE: 58124
833 05:03:30.031429
834 05:03:30.040954 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
835 05:03:30.041419
836 05:03:30.041828 Board ID = 1
837 05:03:30.042226 Set A53 clk to 24M
838 05:03:30.042619 Set A73 clk to 24M
839 05:03:30.046562 Set clk81 to 24M
840 05:03:30.047012 A53 clk: 1200 MHz
841 05:03:30.047419 A73 clk: 1200 MHz
842 05:03:30.049957 CLK81: 166.6M
843 05:03:30.050412 smccc: 00012a92
844 05:03:30.055389 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
845 05:03:30.060981 board id: 1
846 05:03:30.065547 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
847 05:03:30.076921 fw parse done
848 05:03:30.082253 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
849 05:03:30.125165 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
850 05:03:30.136559 PIEI prepare done
851 05:03:30.137018 fastboot data load
852 05:03:30.137433 fastboot data verify
853 05:03:30.142116 verify result: 266
854 05:03:30.147657 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
855 05:03:30.148149 LPDDR4 probe
856 05:03:30.148561 ddr clk to 1584MHz
857 05:03:30.155024 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
858 05:03:30.192928
859 05:03:30.193398 dmc_version 0001
860 05:03:30.199669 Check phy result
861 05:03:30.205460 INFO : End of CA training
862 05:03:30.205914 INFO : End of initialization
863 05:03:30.211047 INFO : Training has run successfully!
864 05:03:30.211501 Check phy result
865 05:03:30.216695 INFO : End of initialization
866 05:03:30.217151 INFO : End of read enable training
867 05:03:30.222255 INFO : End of fine write leveling
868 05:03:30.227870 INFO : End of Write leveling coarse delay
869 05:03:30.228351 INFO : Training has run successfully!
870 05:03:30.228757 Check phy result
871 05:03:30.233465 INFO : End of initialization
872 05:03:30.233918 INFO : End of read dq deskew training
873 05:03:30.239107 INFO : End of MPR read delay center optimization
874 05:03:30.244648 INFO : End of write delay center optimization
875 05:03:30.250261 INFO : End of read delay center optimization
876 05:03:30.250711 INFO : End of max read latency training
877 05:03:30.255857 INFO : Training has run successfully!
878 05:03:30.256350 1D training succeed
879 05:03:30.264702 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
880 05:03:30.313353 Check phy result
881 05:03:30.313823 INFO : End of initialization
882 05:03:30.334560 INFO : End of 2D read delay Voltage center optimization
883 05:03:30.354714 INFO : End of 2D read delay Voltage center optimization
884 05:03:30.405773 INFO : End of 2D write delay Voltage center optimization
885 05:03:30.456217 INFO : End of 2D write delay Voltage center optimization
886 05:03:30.461618 INFO : Training has run successfully!
887 05:03:30.462074
888 05:03:30.462482 channel==0
889 05:03:30.467256 RxClkDly_Margin_A0==88 ps 9
890 05:03:30.467711 TxDqDly_Margin_A0==98 ps 10
891 05:03:30.472867 RxClkDly_Margin_A1==88 ps 9
892 05:03:30.473319 TxDqDly_Margin_A1==98 ps 10
893 05:03:30.473736 TrainedVREFDQ_A0==74
894 05:03:30.478562 TrainedVREFDQ_A1==74
895 05:03:30.479031 VrefDac_Margin_A0==25
896 05:03:30.479430 DeviceVref_Margin_A0==40
897 05:03:30.484149 VrefDac_Margin_A1==25
898 05:03:30.484622 DeviceVref_Margin_A1==40
899 05:03:30.485009
900 05:03:30.485393
901 05:03:30.489689 channel==1
902 05:03:30.490138 RxClkDly_Margin_A0==98 ps 10
903 05:03:30.490525 TxDqDly_Margin_A0==98 ps 10
904 05:03:30.495254 RxClkDly_Margin_A1==88 ps 9
905 05:03:30.495695 TxDqDly_Margin_A1==98 ps 10
906 05:03:30.500879 TrainedVREFDQ_A0==77
907 05:03:30.501325 TrainedVREFDQ_A1==77
908 05:03:30.501714 VrefDac_Margin_A0==22
909 05:03:30.506467 DeviceVref_Margin_A0==37
910 05:03:30.506907 VrefDac_Margin_A1==24
911 05:03:30.512202 DeviceVref_Margin_A1==37
912 05:03:30.512654
913 05:03:30.513046 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
914 05:03:30.517670
915 05:03:30.545602 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000017 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000017 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
916 05:03:30.546092 2D training succeed
917 05:03:30.551303 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
918 05:03:30.556841 auto size-- 65535DDR cs0 size: 2048MB
919 05:03:30.557281 DDR cs1 size: 2048MB
920 05:03:30.562533 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
921 05:03:30.563134 cs0 DataBus test pass
922 05:03:30.567975 cs1 DataBus test pass
923 05:03:30.568455 cs0 AddrBus test pass
924 05:03:30.568840 cs1 AddrBus test pass
925 05:03:30.569222
926 05:03:30.573552 100bdlr_step_size ps== 420
927 05:03:30.574008 result report
928 05:03:30.579163 boot times 0Enable ddr reg access
929 05:03:30.584235 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
930 05:03:30.597385 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
931 05:03:31.171678 0.0;M3 CHK:0;cm4_sp_mode 0
932 05:03:31.172301 MVN_1=0x00000000
933 05:03:31.177188 MVN_2=0x00000000
934 05:03:31.182925 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
935 05:03:31.183380 OPS=0x10
936 05:03:31.183787 ring efuse init
937 05:03:31.184219 chipver efuse init
938 05:03:31.188534 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
939 05:03:31.194178 [0.018961 Inits done]
940 05:03:31.194627 secure task start!
941 05:03:31.195034 high task start!
942 05:03:31.197822 low task start!
943 05:03:31.198270 run into bl31
944 05:03:31.205411 NOTICE: BL31: v1.3(release):4fc40b1
945 05:03:31.212745 NOTICE: BL31: Built : 15:58:17, May 22 2019
946 05:03:31.213204 NOTICE: BL31: G12A normal boot!
947 05:03:31.238483 NOTICE: BL31: BL33 decompress pass
948 05:03:31.243823 ERROR: Error initializing runtime service opteed_fast
949 05:03:32.476934
950 05:03:32.477506
951 05:03:32.485430 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
952 05:03:32.485894
953 05:03:32.486305 Model: Libre Computer AML-A311D-CC Alta
954 05:03:32.693811 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
955 05:03:32.717297 DRAM: 2 GiB (effective 3.8 GiB)
956 05:03:32.860373 Core: 408 devices, 31 uclasses, devicetree: separate
957 05:03:32.866283 WDT: Not starting watchdog@f0d0
958 05:03:32.898365 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
959 05:03:32.910850 Loading Environment from FAT... Card did not respond to voltage select! : -110
960 05:03:32.915879 ** Bad device specification mmc 0 **
961 05:03:32.926168 Card did not respond to voltage select! : -110
962 05:03:32.933506 ** Bad device specification mmc 0 **
963 05:03:32.933981 Couldn't find partition mmc 0
964 05:03:32.942192 Card did not respond to voltage select! : -110
965 05:03:32.947725 ** Bad device specification mmc 0 **
966 05:03:32.948205 Couldn't find partition mmc 0
967 05:03:32.952724 Error: could not access storage.
968 05:03:33.296240 Net: eth0: ethernet@ff3f0000
969 05:03:33.296758 starting USB...
970 05:03:33.548105 Bus usb@ff500000: Register 3000140 NbrPorts 3
971 05:03:33.548621 Starting the controller
972 05:03:33.555053 USB XHCI 1.10
973 05:03:35.109060 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
974 05:03:35.116535 scanning usb for storage devices... 0 Storage Device(s) found
976 05:03:35.168126 Hit any key to stop autoboot: 1
977 05:03:35.169255 end: 2.4.2 bootloader-interrupt (duration 00:00:31) [common]
978 05:03:35.170198 start: 2.4.3 bootloader-commands (timeout 00:04:29) [common]
979 05:03:35.170854 Setting prompt string to ['=>']
980 05:03:35.171465 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:29)
981 05:03:35.184867 0
982 05:03:35.185938 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
983 05:03:35.186584 Sending with 10 millisecond of delay
985 05:03:36.321657 => setenv autoload no
986 05:03:36.332714 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:27)
987 05:03:36.339225 setenv autoload no
988 05:03:36.340121 Sending with 10 millisecond of delay
990 05:03:38.139562 => setenv initrd_high 0xffffffff
991 05:03:38.150475 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:26)
992 05:03:38.151487 setenv initrd_high 0xffffffff
993 05:03:38.152295 Sending with 10 millisecond of delay
995 05:03:39.771807 => setenv fdt_high 0xffffffff
996 05:03:39.782665 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:24)
997 05:03:39.783589 setenv fdt_high 0xffffffff
998 05:03:39.784406 Sending with 10 millisecond of delay
1000 05:03:40.076298 => dhcp
1001 05:03:40.087052 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:24)
1002 05:03:40.087926 dhcp
1003 05:03:40.088467 Speed: 1000, full duplex
1004 05:03:40.088926 BOOTP broadcast 1
1005 05:03:40.096084 DHCP client bound to address 192.168.6.27 (9 ms)
1006 05:03:40.096834 Sending with 10 millisecond of delay
1008 05:03:41.773293 => setenv serverip 192.168.6.2
1009 05:03:41.784130 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:22)
1010 05:03:41.785088 setenv serverip 192.168.6.2
1011 05:03:41.785830 Sending with 10 millisecond of delay
1013 05:03:45.509681 => tftpboot 0x01080000 907044/tftp-deploy-hpxzdqdk/kernel/uImage
1014 05:03:45.520482 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1015 05:03:45.521313 tftpboot 0x01080000 907044/tftp-deploy-hpxzdqdk/kernel/uImage
1016 05:03:45.521771 Speed: 1000, full duplex
1017 05:03:45.522191 Using ethernet@ff3f0000 device
1018 05:03:45.523345 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1019 05:03:45.528785 Filename '907044/tftp-deploy-hpxzdqdk/kernel/uImage'.
1020 05:03:45.532647 Load address: 0x1080000
1021 05:03:48.471202 Loading: *################################################## 43.6 MiB
1022 05:03:48.471792 14.8 MiB/s
1023 05:03:48.472282 done
1024 05:03:48.474936 Bytes transferred = 45713984 (2b98a40 hex)
1025 05:03:48.475717 Sending with 10 millisecond of delay
1027 05:03:53.162902 => tftpboot 0x08000000 907044/tftp-deploy-hpxzdqdk/ramdisk/ramdisk.cpio.gz.uboot
1028 05:03:53.173671 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:11)
1029 05:03:53.174492 tftpboot 0x08000000 907044/tftp-deploy-hpxzdqdk/ramdisk/ramdisk.cpio.gz .uboot
1030 05:03:53.174940 Speed: 1000, full duplex
1031 05:03:53.175355 Using ethernet@ff3f0000 device
1032 05:03:53.176484 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1033 05:03:53.181934 Filename '907044/tftp-deploy-hpxzdqdk/ramdisk/ramdisk.cpio.g.uboot'.
1034 05:03:53.187425 Load address: 0x8000000
1035 05:03:53.188093 Loading: *
1036 05:03:53.193002 TFTP error: 'File not found' (1)
1037 05:03:53.193649 Not retrying...
1039 05:03:53.195359 end: 2.4.3 bootloader-commands (duration 00:00:18) [common]
1042 05:03:53.197781 end: 2.4 uboot-commands (duration 00:00:49) [common]
1044 05:03:53.199556 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'File not found' (7)'
1046 05:03:53.200911 end: 2 uboot-action (duration 00:00:50) [common]
1048 05:03:53.202908 Cleaning after the job
1049 05:03:53.203640 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/907044/tftp-deploy-hpxzdqdk/ramdisk
1050 05:03:53.220817 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/907044/tftp-deploy-hpxzdqdk/kernel
1051 05:03:53.259930 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/907044/tftp-deploy-hpxzdqdk/dtb
1052 05:03:53.260950 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/907044/tftp-deploy-hpxzdqdk/nfsrootfs
1053 05:03:53.292907 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/907044/tftp-deploy-hpxzdqdk/modules
1054 05:03:53.315658 start: 4.1 power-off (timeout 00:00:30) [common]
1055 05:03:53.316454 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1056 05:03:53.347544 >> OK - accepted request
1057 05:03:53.349711 Returned 0 in 0 seconds
1058 05:03:53.450621 end: 4.1 power-off (duration 00:00:00) [common]
1060 05:03:53.451827 start: 4.2 read-feedback (timeout 00:10:00) [common]
1061 05:03:53.452667 Listened to connection for namespace 'common' for up to 1s
1062 05:03:54.453589 Finalising connection for namespace 'common'
1063 05:03:54.454168 Disconnecting from shell: Finalise
1064 05:03:54.454550 =>
1065 05:03:54.555498 end: 4.2 read-feedback (duration 00:00:01) [common]
1066 05:03:54.556396 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/907044
1067 05:03:57.477649 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/907044
1068 05:03:57.478242 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.