Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 00:11:59.533581 lava-dispatcher, installed at version: 2024.01
2 00:11:59.534379 start: 0 validate
3 00:11:59.534849 Start time: 2024-11-01 00:11:59.534819+00:00 (UTC)
4 00:11:59.535415 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 00:11:59.535955 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-igt%2F20240313.0%2Farm64%2Frootfs.cpio.gz exists
6 00:11:59.571510 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 00:11:59.572095 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fpending-fixes%2Fv6.12-rc5-415-g78b16920c1e2%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 00:11:59.602577 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 00:11:59.603213 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fpending-fixes%2Fv6.12-rc5-415-g78b16920c1e2%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 00:11:59.632547 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 00:11:59.633048 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fpending-fixes%2Fv6.12-rc5-415-g78b16920c1e2%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
12 00:11:59.669441 validate duration: 0.13
14 00:11:59.670291 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 00:11:59.670619 start: 1.1 download-retry (timeout 00:10:00) [common]
16 00:11:59.670916 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 00:11:59.671474 Not decompressing ramdisk as can be used compressed.
18 00:11:59.671899 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-igt/20240313.0/arm64/rootfs.cpio.gz
19 00:11:59.672186 saving as /var/lib/lava/dispatcher/tmp/919146/tftp-deploy-ovdj3btp/ramdisk/rootfs.cpio.gz
20 00:11:59.672448 total size: 47897469 (45 MB)
21 00:11:59.718184 progress 0 % (0 MB)
22 00:11:59.749403 progress 5 % (2 MB)
23 00:11:59.778773 progress 10 % (4 MB)
24 00:11:59.808284 progress 15 % (6 MB)
25 00:11:59.837730 progress 20 % (9 MB)
26 00:11:59.867574 progress 25 % (11 MB)
27 00:11:59.897932 progress 30 % (13 MB)
28 00:11:59.927439 progress 35 % (16 MB)
29 00:11:59.957177 progress 40 % (18 MB)
30 00:11:59.986450 progress 45 % (20 MB)
31 00:12:00.015595 progress 50 % (22 MB)
32 00:12:00.044568 progress 55 % (25 MB)
33 00:12:00.074267 progress 60 % (27 MB)
34 00:12:00.103481 progress 65 % (29 MB)
35 00:12:00.132633 progress 70 % (32 MB)
36 00:12:00.161809 progress 75 % (34 MB)
37 00:12:00.190694 progress 80 % (36 MB)
38 00:12:00.219610 progress 85 % (38 MB)
39 00:12:00.248592 progress 90 % (41 MB)
40 00:12:00.277699 progress 95 % (43 MB)
41 00:12:00.305846 progress 100 % (45 MB)
42 00:12:00.306585 45 MB downloaded in 0.63 s (72.03 MB/s)
43 00:12:00.307131 end: 1.1.1 http-download (duration 00:00:01) [common]
45 00:12:00.308038 end: 1.1 download-retry (duration 00:00:01) [common]
46 00:12:00.308334 start: 1.2 download-retry (timeout 00:09:59) [common]
47 00:12:00.308602 start: 1.2.1 http-download (timeout 00:09:59) [common]
48 00:12:00.309063 downloading http://storage.kernelci.org/next/pending-fixes/v6.12-rc5-415-g78b16920c1e2/arm64/defconfig/gcc-12/kernel/Image
49 00:12:00.309303 saving as /var/lib/lava/dispatcher/tmp/919146/tftp-deploy-ovdj3btp/kernel/Image
50 00:12:00.309510 total size: 45715968 (43 MB)
51 00:12:00.309721 No compression specified
52 00:12:00.357132 progress 0 % (0 MB)
53 00:12:00.385535 progress 5 % (2 MB)
54 00:12:00.413107 progress 10 % (4 MB)
55 00:12:00.440865 progress 15 % (6 MB)
56 00:12:00.468667 progress 20 % (8 MB)
57 00:12:00.495722 progress 25 % (10 MB)
58 00:12:00.523541 progress 30 % (13 MB)
59 00:12:00.551384 progress 35 % (15 MB)
60 00:12:00.579508 progress 40 % (17 MB)
61 00:12:00.606616 progress 45 % (19 MB)
62 00:12:00.634043 progress 50 % (21 MB)
63 00:12:00.661537 progress 55 % (24 MB)
64 00:12:00.688842 progress 60 % (26 MB)
65 00:12:00.716092 progress 65 % (28 MB)
66 00:12:00.743829 progress 70 % (30 MB)
67 00:12:00.774173 progress 75 % (32 MB)
68 00:12:00.802413 progress 80 % (34 MB)
69 00:12:00.830015 progress 85 % (37 MB)
70 00:12:00.857466 progress 90 % (39 MB)
71 00:12:00.885465 progress 95 % (41 MB)
72 00:12:00.911902 progress 100 % (43 MB)
73 00:12:00.912434 43 MB downloaded in 0.60 s (72.31 MB/s)
74 00:12:00.912913 end: 1.2.1 http-download (duration 00:00:01) [common]
76 00:12:00.913720 end: 1.2 download-retry (duration 00:00:01) [common]
77 00:12:00.913995 start: 1.3 download-retry (timeout 00:09:59) [common]
78 00:12:00.914257 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 00:12:00.914724 downloading http://storage.kernelci.org/next/pending-fixes/v6.12-rc5-415-g78b16920c1e2/arm64/defconfig/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
80 00:12:00.914990 saving as /var/lib/lava/dispatcher/tmp/919146/tftp-deploy-ovdj3btp/dtb/meson-g12b-a311d-libretech-cc.dtb
81 00:12:00.915200 total size: 54703 (0 MB)
82 00:12:00.915408 No compression specified
83 00:12:00.950346 progress 59 % (0 MB)
84 00:12:00.951235 progress 100 % (0 MB)
85 00:12:00.951845 0 MB downloaded in 0.04 s (1.42 MB/s)
86 00:12:00.952382 end: 1.3.1 http-download (duration 00:00:00) [common]
88 00:12:00.953195 end: 1.3 download-retry (duration 00:00:00) [common]
89 00:12:00.953455 start: 1.4 download-retry (timeout 00:09:59) [common]
90 00:12:00.953717 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 00:12:00.954183 downloading http://storage.kernelci.org/next/pending-fixes/v6.12-rc5-415-g78b16920c1e2/arm64/defconfig/gcc-12/modules.tar.xz
92 00:12:00.954421 saving as /var/lib/lava/dispatcher/tmp/919146/tftp-deploy-ovdj3btp/modules/modules.tar
93 00:12:00.954623 total size: 11602096 (11 MB)
94 00:12:00.954835 Using unxz to decompress xz
95 00:12:00.992227 progress 0 % (0 MB)
96 00:12:01.062724 progress 5 % (0 MB)
97 00:12:01.141119 progress 10 % (1 MB)
98 00:12:01.225547 progress 15 % (1 MB)
99 00:12:01.304002 progress 20 % (2 MB)
100 00:12:01.381959 progress 25 % (2 MB)
101 00:12:01.464207 progress 30 % (3 MB)
102 00:12:01.538614 progress 35 % (3 MB)
103 00:12:01.619047 progress 40 % (4 MB)
104 00:12:01.705485 progress 45 % (5 MB)
105 00:12:01.787484 progress 50 % (5 MB)
106 00:12:01.867150 progress 55 % (6 MB)
107 00:12:01.949613 progress 60 % (6 MB)
108 00:12:02.035562 progress 65 % (7 MB)
109 00:12:02.112563 progress 70 % (7 MB)
110 00:12:02.195339 progress 75 % (8 MB)
111 00:12:02.278250 progress 80 % (8 MB)
112 00:12:02.354512 progress 85 % (9 MB)
113 00:12:02.451358 progress 90 % (9 MB)
114 00:12:02.603067 progress 95 % (10 MB)
115 00:12:02.747134 progress 100 % (11 MB)
116 00:12:02.765271 11 MB downloaded in 1.81 s (6.11 MB/s)
117 00:12:02.765891 end: 1.4.1 http-download (duration 00:00:02) [common]
119 00:12:02.766727 end: 1.4 download-retry (duration 00:00:02) [common]
120 00:12:02.767004 start: 1.5 prepare-tftp-overlay (timeout 00:09:57) [common]
121 00:12:02.767273 start: 1.5.1 extract-nfsrootfs (timeout 00:09:57) [common]
122 00:12:02.767524 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 00:12:02.767783 start: 1.5.2 lava-overlay (timeout 00:09:57) [common]
124 00:12:02.768668 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/919146/lava-overlay-fscj6wug
125 00:12:02.769584 makedir: /var/lib/lava/dispatcher/tmp/919146/lava-overlay-fscj6wug/lava-919146/bin
126 00:12:02.770287 makedir: /var/lib/lava/dispatcher/tmp/919146/lava-overlay-fscj6wug/lava-919146/tests
127 00:12:02.770978 makedir: /var/lib/lava/dispatcher/tmp/919146/lava-overlay-fscj6wug/lava-919146/results
128 00:12:02.771662 Creating /var/lib/lava/dispatcher/tmp/919146/lava-overlay-fscj6wug/lava-919146/bin/lava-add-keys
129 00:12:02.772717 Creating /var/lib/lava/dispatcher/tmp/919146/lava-overlay-fscj6wug/lava-919146/bin/lava-add-sources
130 00:12:02.773735 Creating /var/lib/lava/dispatcher/tmp/919146/lava-overlay-fscj6wug/lava-919146/bin/lava-background-process-start
131 00:12:02.774757 Creating /var/lib/lava/dispatcher/tmp/919146/lava-overlay-fscj6wug/lava-919146/bin/lava-background-process-stop
132 00:12:02.775853 Creating /var/lib/lava/dispatcher/tmp/919146/lava-overlay-fscj6wug/lava-919146/bin/lava-common-functions
133 00:12:02.776926 Creating /var/lib/lava/dispatcher/tmp/919146/lava-overlay-fscj6wug/lava-919146/bin/lava-echo-ipv4
134 00:12:02.777942 Creating /var/lib/lava/dispatcher/tmp/919146/lava-overlay-fscj6wug/lava-919146/bin/lava-install-packages
135 00:12:02.778919 Creating /var/lib/lava/dispatcher/tmp/919146/lava-overlay-fscj6wug/lava-919146/bin/lava-installed-packages
136 00:12:02.779826 Creating /var/lib/lava/dispatcher/tmp/919146/lava-overlay-fscj6wug/lava-919146/bin/lava-os-build
137 00:12:02.780772 Creating /var/lib/lava/dispatcher/tmp/919146/lava-overlay-fscj6wug/lava-919146/bin/lava-probe-channel
138 00:12:02.781667 Creating /var/lib/lava/dispatcher/tmp/919146/lava-overlay-fscj6wug/lava-919146/bin/lava-probe-ip
139 00:12:02.782565 Creating /var/lib/lava/dispatcher/tmp/919146/lava-overlay-fscj6wug/lava-919146/bin/lava-target-ip
140 00:12:02.783460 Creating /var/lib/lava/dispatcher/tmp/919146/lava-overlay-fscj6wug/lava-919146/bin/lava-target-mac
141 00:12:02.784456 Creating /var/lib/lava/dispatcher/tmp/919146/lava-overlay-fscj6wug/lava-919146/bin/lava-target-storage
142 00:12:02.785094 Creating /var/lib/lava/dispatcher/tmp/919146/lava-overlay-fscj6wug/lava-919146/bin/lava-test-case
143 00:12:02.785703 Creating /var/lib/lava/dispatcher/tmp/919146/lava-overlay-fscj6wug/lava-919146/bin/lava-test-event
144 00:12:02.786275 Creating /var/lib/lava/dispatcher/tmp/919146/lava-overlay-fscj6wug/lava-919146/bin/lava-test-feedback
145 00:12:02.786800 Creating /var/lib/lava/dispatcher/tmp/919146/lava-overlay-fscj6wug/lava-919146/bin/lava-test-raise
146 00:12:02.787382 Creating /var/lib/lava/dispatcher/tmp/919146/lava-overlay-fscj6wug/lava-919146/bin/lava-test-reference
147 00:12:02.787937 Creating /var/lib/lava/dispatcher/tmp/919146/lava-overlay-fscj6wug/lava-919146/bin/lava-test-runner
148 00:12:02.788977 Creating /var/lib/lava/dispatcher/tmp/919146/lava-overlay-fscj6wug/lava-919146/bin/lava-test-set
149 00:12:02.789958 Creating /var/lib/lava/dispatcher/tmp/919146/lava-overlay-fscj6wug/lava-919146/bin/lava-test-shell
150 00:12:02.790962 Updating /var/lib/lava/dispatcher/tmp/919146/lava-overlay-fscj6wug/lava-919146/bin/lava-install-packages (oe)
151 00:12:02.791971 Updating /var/lib/lava/dispatcher/tmp/919146/lava-overlay-fscj6wug/lava-919146/bin/lava-installed-packages (oe)
152 00:12:02.792962 Creating /var/lib/lava/dispatcher/tmp/919146/lava-overlay-fscj6wug/lava-919146/environment
153 00:12:02.793769 LAVA metadata
154 00:12:02.794309 - LAVA_JOB_ID=919146
155 00:12:02.794746 - LAVA_DISPATCHER_IP=192.168.6.2
156 00:12:02.795421 start: 1.5.2.1 ssh-authorize (timeout 00:09:57) [common]
157 00:12:02.797263 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 00:12:02.797913 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:57) [common]
159 00:12:02.798367 skipped lava-vland-overlay
160 00:12:02.798887 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 00:12:02.799411 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:57) [common]
162 00:12:02.799886 skipped lava-multinode-overlay
163 00:12:02.800478 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 00:12:02.801031 start: 1.5.2.4 test-definition (timeout 00:09:57) [common]
165 00:12:02.801555 Loading test definitions
166 00:12:02.802150 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:57) [common]
167 00:12:02.802631 Using /lava-919146 at stage 0
168 00:12:02.804555 uuid=919146_1.5.2.4.1 testdef=None
169 00:12:02.804908 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 00:12:02.805187 start: 1.5.2.4.2 test-overlay (timeout 00:09:57) [common]
171 00:12:02.807066 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 00:12:02.807936 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:57) [common]
174 00:12:02.810257 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 00:12:02.811108 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:57) [common]
177 00:12:02.813404 runner path: /var/lib/lava/dispatcher/tmp/919146/lava-overlay-fscj6wug/lava-919146/0/tests/0_igt-gpu-panfrost test_uuid 919146_1.5.2.4.1
178 00:12:02.814083 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 00:12:02.814986 Creating lava-test-runner.conf files
181 00:12:02.815207 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/919146/lava-overlay-fscj6wug/lava-919146/0 for stage 0
182 00:12:02.815587 - 0_igt-gpu-panfrost
183 00:12:02.816033 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 00:12:02.816356 start: 1.5.2.5 compress-overlay (timeout 00:09:57) [common]
185 00:12:02.841209 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 00:12:02.841657 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:57) [common]
187 00:12:02.841936 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 00:12:02.842211 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 00:12:02.842516 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:57) [common]
190 00:12:09.750021 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:07) [common]
191 00:12:09.750490 start: 1.5.4 extract-modules (timeout 00:09:50) [common]
192 00:12:09.750752 extracting modules file /var/lib/lava/dispatcher/tmp/919146/tftp-deploy-ovdj3btp/modules/modules.tar to /var/lib/lava/dispatcher/tmp/919146/extract-overlay-ramdisk-e3wwq6l5/ramdisk
193 00:12:11.153144 end: 1.5.4 extract-modules (duration 00:00:01) [common]
194 00:12:11.153597 start: 1.5.5 apply-overlay-tftp (timeout 00:09:49) [common]
195 00:12:11.153875 [common] Applying overlay /var/lib/lava/dispatcher/tmp/919146/compress-overlay-_n443lu8/overlay-1.5.2.5.tar.gz to ramdisk
196 00:12:11.154090 [common] Applying overlay /var/lib/lava/dispatcher/tmp/919146/compress-overlay-_n443lu8/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/919146/extract-overlay-ramdisk-e3wwq6l5/ramdisk
197 00:12:11.183850 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 00:12:11.184288 start: 1.5.6 prepare-kernel (timeout 00:09:48) [common]
199 00:12:11.184560 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:48) [common]
200 00:12:11.184789 Converting downloaded kernel to a uImage
201 00:12:11.185094 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/919146/tftp-deploy-ovdj3btp/kernel/Image /var/lib/lava/dispatcher/tmp/919146/tftp-deploy-ovdj3btp/kernel/uImage
202 00:12:11.669348 output: Image Name:
203 00:12:11.669740 output: Created: Fri Nov 1 00:12:11 2024
204 00:12:11.669951 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 00:12:11.670156 output: Data Size: 45715968 Bytes = 44644.50 KiB = 43.60 MiB
206 00:12:11.670359 output: Load Address: 01080000
207 00:12:11.670560 output: Entry Point: 01080000
208 00:12:11.670760 output:
209 00:12:11.671093 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
210 00:12:11.671359 end: 1.5.6 prepare-kernel (duration 00:00:00) [common]
211 00:12:11.671662 start: 1.5.7 configure-preseed-file (timeout 00:09:48) [common]
212 00:12:11.671933 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 00:12:11.672238 start: 1.5.8 compress-ramdisk (timeout 00:09:48) [common]
214 00:12:11.672508 Building ramdisk /var/lib/lava/dispatcher/tmp/919146/extract-overlay-ramdisk-e3wwq6l5/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/919146/extract-overlay-ramdisk-e3wwq6l5/ramdisk
215 00:12:18.352157 >> 502413 blocks
216 00:12:39.057290 Adding RAMdisk u-boot header.
217 00:12:39.057957 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/919146/extract-overlay-ramdisk-e3wwq6l5/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/919146/extract-overlay-ramdisk-e3wwq6l5/ramdisk.cpio.gz.uboot
218 00:12:39.702161 output: Image Name:
219 00:12:39.702647 output: Created: Fri Nov 1 00:12:39 2024
220 00:12:39.702902 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 00:12:39.703151 output: Data Size: 65720631 Bytes = 64180.30 KiB = 62.68 MiB
222 00:12:39.703396 output: Load Address: 00000000
223 00:12:39.703641 output: Entry Point: 00000000
224 00:12:39.703875 output:
225 00:12:39.705091 rename /var/lib/lava/dispatcher/tmp/919146/extract-overlay-ramdisk-e3wwq6l5/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/919146/tftp-deploy-ovdj3btp/ramdisk/ramdisk.cpio.gz.uboot
226 00:12:39.706015 end: 1.5.8 compress-ramdisk (duration 00:00:28) [common]
227 00:12:39.706743 end: 1.5 prepare-tftp-overlay (duration 00:00:37) [common]
228 00:12:39.707445 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:20) [common]
229 00:12:39.708059 No LXC device requested
230 00:12:39.708754 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 00:12:39.709442 start: 1.7 deploy-device-env (timeout 00:09:20) [common]
232 00:12:39.710108 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 00:12:39.710676 Checking files for TFTP limit of 4294967296 bytes.
234 00:12:39.714226 end: 1 tftp-deploy (duration 00:00:40) [common]
235 00:12:39.714991 start: 2 uboot-action (timeout 00:05:00) [common]
236 00:12:39.715679 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 00:12:39.716392 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 00:12:39.717052 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 00:12:39.717747 Using kernel file from prepare-kernel: 919146/tftp-deploy-ovdj3btp/kernel/uImage
240 00:12:39.718544 substitutions:
241 00:12:39.719075 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 00:12:39.719608 - {DTB_ADDR}: 0x01070000
243 00:12:39.720158 - {DTB}: 919146/tftp-deploy-ovdj3btp/dtb/meson-g12b-a311d-libretech-cc.dtb
244 00:12:39.720683 - {INITRD}: 919146/tftp-deploy-ovdj3btp/ramdisk/ramdisk.cpio.gz.uboot
245 00:12:39.721210 - {KERNEL_ADDR}: 0x01080000
246 00:12:39.721726 - {KERNEL}: 919146/tftp-deploy-ovdj3btp/kernel/uImage
247 00:12:39.722241 - {LAVA_MAC}: None
248 00:12:39.722817 - {PRESEED_CONFIG}: None
249 00:12:39.723336 - {PRESEED_LOCAL}: None
250 00:12:39.723847 - {RAMDISK_ADDR}: 0x08000000
251 00:12:39.724395 - {RAMDISK}: 919146/tftp-deploy-ovdj3btp/ramdisk/ramdisk.cpio.gz.uboot
252 00:12:39.724917 - {ROOT_PART}: None
253 00:12:39.725429 - {ROOT}: None
254 00:12:39.725956 - {SERVER_IP}: 192.168.6.2
255 00:12:39.726473 - {TEE_ADDR}: 0x83000000
256 00:12:39.726984 - {TEE}: None
257 00:12:39.727496 Parsed boot commands:
258 00:12:39.728115 - setenv autoload no
259 00:12:39.728665 - setenv initrd_high 0xffffffff
260 00:12:39.729184 - setenv fdt_high 0xffffffff
261 00:12:39.729696 - dhcp
262 00:12:39.730218 - setenv serverip 192.168.6.2
263 00:12:39.730726 - tftpboot 0x01080000 919146/tftp-deploy-ovdj3btp/kernel/uImage
264 00:12:39.731235 - tftpboot 0x08000000 919146/tftp-deploy-ovdj3btp/ramdisk/ramdisk.cpio.gz.uboot
265 00:12:39.731743 - tftpboot 0x01070000 919146/tftp-deploy-ovdj3btp/dtb/meson-g12b-a311d-libretech-cc.dtb
266 00:12:39.732356 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 00:12:39.732901 - bootm 0x01080000 0x08000000 0x01070000
268 00:12:39.733595 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 00:12:39.735632 start: 2.3 connect-device (timeout 00:05:00) [common]
271 00:12:39.736285 [common] connect-device Connecting to device using 'telnet conserv1 3007'
272 00:12:39.752848 Setting prompt string to ['lava-test: # ']
273 00:12:39.754731 end: 2.3 connect-device (duration 00:00:00) [common]
274 00:12:39.755552 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 00:12:39.756319 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 00:12:39.757033 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 00:12:39.758481 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
278 00:12:39.796591 >> OK - accepted request
279 00:12:39.798849 Returned 0 in 0 seconds
280 00:12:39.900261 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
282 00:12:39.902359 end: 2.4.1 reset-device (duration 00:00:00) [common]
283 00:12:39.903122 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
284 00:12:39.903795 Setting prompt string to ['Hit any key to stop autoboot']
285 00:12:39.904453 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 00:12:39.906455 Trying 192.168.56.21...
287 00:12:39.907096 Connected to conserv1.
288 00:12:39.907649 Escape character is '^]'.
289 00:12:39.908238
290 00:12:39.908795 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
291 00:12:39.909370
292 00:12:50.652102 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.�!,K��х��}���с0x01
293 00:12:50.652922 bl2_stage_init 0x81
294 00:12:50.657752 hw id: 0x0000 - pwm id 0x01
295 00:12:50.658474 bl2_stage_init 0xc1
296 00:12:50.659000 bl2_stage_init 0x02
297 00:12:50.659507
298 00:12:50.663245 L0:00000000
299 00:12:50.663803 L1:20000703
300 00:12:50.664359 L2:00008067
301 00:12:50.664867 L3:14000000
302 00:12:50.665367 B2:00402000
303 00:12:50.669094 B1:e0f83180
304 00:12:50.669644
305 00:12:50.670151 TE: 58150
306 00:12:50.670656
307 00:12:50.674468 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
308 00:12:50.675011
309 00:12:50.675518 Board ID = 1
310 00:12:50.679938 Set A53 clk to 24M
311 00:12:50.680522 Set A73 clk to 24M
312 00:12:50.681025 Set clk81 to 24M
313 00:12:50.685596 A53 clk: 1200 MHz
314 00:12:50.686133 A73 clk: 1200 MHz
315 00:12:50.686635 CLK81: 166.6M
316 00:12:50.687131 smccc: 00012aab
317 00:12:50.691223 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
318 00:12:50.696816 board id: 1
319 00:12:50.702692 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
320 00:12:50.713081 fw parse done
321 00:12:50.719629 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
322 00:12:50.761686 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
323 00:12:50.772585 PIEI prepare done
324 00:12:50.773147 fastboot data load
325 00:12:50.773656 fastboot data verify
326 00:12:50.778203 verify result: 266
327 00:12:50.783828 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
328 00:12:50.784455 LPDDR4 probe
329 00:12:50.784993 ddr clk to 1584MHz
330 00:12:50.791820 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
331 00:12:50.829289
332 00:12:50.830009 dmc_version 0001
333 00:12:50.835783 Check phy result
334 00:12:50.841620 INFO : End of CA training
335 00:12:50.842235 INFO : End of initialization
336 00:12:50.847214 INFO : Training has run successfully!
337 00:12:50.847787 Check phy result
338 00:12:50.852860 INFO : End of initialization
339 00:12:50.853429 INFO : End of read enable training
340 00:12:50.858460 INFO : End of fine write leveling
341 00:12:50.864108 INFO : End of Write leveling coarse delay
342 00:12:50.864692 INFO : Training has run successfully!
343 00:12:50.865214 Check phy result
344 00:12:50.869749 INFO : End of initialization
345 00:12:50.870303 INFO : End of read dq deskew training
346 00:12:50.875387 INFO : End of MPR read delay center optimization
347 00:12:50.880944 INFO : End of write delay center optimization
348 00:12:50.886459 INFO : End of read delay center optimization
349 00:12:50.887043 INFO : End of max read latency training
350 00:12:50.892133 INFO : Training has run successfully!
351 00:12:50.892698 1D training succeed
352 00:12:50.901258 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
353 00:12:50.948804 Check phy result
354 00:12:50.949447 INFO : End of initialization
355 00:12:50.970423 INFO : End of 2D read delay Voltage center optimization
356 00:12:50.990503 INFO : End of 2D read delay Voltage center optimization
357 00:12:51.042417 INFO : End of 2D write delay Voltage center optimization
358 00:12:51.091698 INFO : End of 2D write delay Voltage center optimization
359 00:12:51.097200 INFO : Training has run successfully!
360 00:12:51.097773
361 00:12:51.098313 channel==0
362 00:12:51.102890 RxClkDly_Margin_A0==88 ps 9
363 00:12:51.103454 TxDqDly_Margin_A0==98 ps 10
364 00:12:51.106105 RxClkDly_Margin_A1==88 ps 9
365 00:12:51.106665 TxDqDly_Margin_A1==98 ps 10
366 00:12:51.111718 TrainedVREFDQ_A0==74
367 00:12:51.112313 TrainedVREFDQ_A1==74
368 00:12:51.112847 VrefDac_Margin_A0==25
369 00:12:51.117291 DeviceVref_Margin_A0==40
370 00:12:51.117843 VrefDac_Margin_A1==25
371 00:12:51.122896 DeviceVref_Margin_A1==40
372 00:12:51.123465
373 00:12:51.124019
374 00:12:51.124543 channel==1
375 00:12:51.125050 RxClkDly_Margin_A0==88 ps 9
376 00:12:51.128505 TxDqDly_Margin_A0==88 ps 9
377 00:12:51.129073 RxClkDly_Margin_A1==98 ps 10
378 00:12:51.134108 TxDqDly_Margin_A1==88 ps 9
379 00:12:51.134664 TrainedVREFDQ_A0==77
380 00:12:51.135184 TrainedVREFDQ_A1==77
381 00:12:51.139707 VrefDac_Margin_A0==22
382 00:12:51.140280 DeviceVref_Margin_A0==37
383 00:12:51.145296 VrefDac_Margin_A1==22
384 00:12:51.145870 DeviceVref_Margin_A1==37
385 00:12:51.146385
386 00:12:51.150935 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
387 00:12:51.151521
388 00:12:51.178885 soc_vref_reg_value 0x 00000019 00000019 00000018 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000019 00000017 00000019 00000018 0000001a 0000001a 00000018 00000017 00000018 00000017 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
389 00:12:51.184500 2D training succeed
390 00:12:51.190174 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
391 00:12:51.190826 auto size-- 65535DDR cs0 size: 2048MB
392 00:12:51.195685 DDR cs1 size: 2048MB
393 00:12:51.196322 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
394 00:12:51.201332 cs0 DataBus test pass
395 00:12:51.201943 cs1 DataBus test pass
396 00:12:51.202476 cs0 AddrBus test pass
397 00:12:51.206924 cs1 AddrBus test pass
398 00:12:51.207476
399 00:12:51.208025 100bdlr_step_size ps== 420
400 00:12:51.208562 result report
401 00:12:51.212503 boot times 0Enable ddr reg access
402 00:12:51.220057 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
403 00:12:51.233490 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
404 00:12:51.805688 0.0;M3 CHK:0;cm4_sp_mode 0
405 00:12:51.806477 MVN_1=0x00000000
406 00:12:51.811027 MVN_2=0x00000000
407 00:12:51.816805 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
408 00:12:51.817413 OPS=0x10
409 00:12:51.817949 ring efuse init
410 00:12:51.818465 chipver efuse init
411 00:12:51.822417 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
412 00:12:51.828050 [0.018961 Inits done]
413 00:12:51.828651 secure task start!
414 00:12:51.829206 high task start!
415 00:12:51.832577 low task start!
416 00:12:51.833173 run into bl31
417 00:12:51.839189 NOTICE: BL31: v1.3(release):4fc40b1
418 00:12:51.847035 NOTICE: BL31: Built : 15:58:17, May 22 2019
419 00:12:51.847545 NOTICE: BL31: G12A normal boot!
420 00:12:51.872919 NOTICE: BL31: BL33 decompress pass
421 00:12:51.878568 ERROR: Error initializing runtime service opteed_fast
422 00:12:53.111530
423 00:12:53.111966
424 00:12:53.119803 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
425 00:12:53.120344
426 00:12:53.120767 Model: Libre Computer AML-A311D-CC Alta
427 00:12:53.328507 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
428 00:12:53.351689 DRAM: 2 GiB (effective 3.8 GiB)
429 00:12:53.495010 Core: 408 devices, 31 uclasses, devicetree: separate
430 00:12:53.500431 WDT: Not starting watchdog@f0d0
431 00:12:53.532722 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
432 00:12:53.545197 Loading Environment from FAT... Card did not respond to voltage select! : -110
433 00:12:53.550209 ** Bad device specification mmc 0 **
434 00:12:53.560485 Card did not respond to voltage select! : -110
435 00:12:53.568143 ** Bad device specification mmc 0 **
436 00:12:53.568522 Couldn't find partition mmc 0
437 00:12:53.576476 Card did not respond to voltage select! : -110
438 00:12:53.582014 ** Bad device specification mmc 0 **
439 00:12:53.582520 Couldn't find partition mmc 0
440 00:12:53.587057 Error: could not access storage.
441 00:12:54.852287 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
442 00:12:54.853088 bl2_stage_init 0x01
443 00:12:54.853654 bl2_stage_init 0x81
444 00:12:54.857819 hw id: 0x0000 - pwm id 0x01
445 00:12:54.858388 bl2_stage_init 0xc1
446 00:12:54.858925 bl2_stage_init 0x02
447 00:12:54.859448
448 00:12:54.863416 L0:00000000
449 00:12:54.864006 L1:20000703
450 00:12:54.864542 L2:00008067
451 00:12:54.865058 L3:14000000
452 00:12:54.869019 B2:00402000
453 00:12:54.869578 B1:e0f83180
454 00:12:54.870106
455 00:12:54.870620 TE: 58167
456 00:12:54.871132
457 00:12:54.874643 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
458 00:12:54.875224
459 00:12:54.875761 Board ID = 1
460 00:12:54.880195 Set A53 clk to 24M
461 00:12:54.880752 Set A73 clk to 24M
462 00:12:54.881281 Set clk81 to 24M
463 00:12:54.885808 A53 clk: 1200 MHz
464 00:12:54.886364 A73 clk: 1200 MHz
465 00:12:54.886896 CLK81: 166.6M
466 00:12:54.887408 smccc: 00012abd
467 00:12:54.891387 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
468 00:12:54.896993 board id: 1
469 00:12:54.902876 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
470 00:12:54.913604 fw parse done
471 00:12:54.919520 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
472 00:12:54.962133 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
473 00:12:54.973009 PIEI prepare done
474 00:12:54.973583 fastboot data load
475 00:12:54.974109 fastboot data verify
476 00:12:54.978675 verify result: 266
477 00:12:54.984310 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
478 00:12:54.984864 LPDDR4 probe
479 00:12:54.985391 ddr clk to 1584MHz
480 00:12:54.992261 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
481 00:12:55.029514
482 00:12:55.030109 dmc_version 0001
483 00:12:55.036190 Check phy result
484 00:12:55.042063 INFO : End of CA training
485 00:12:55.042612 INFO : End of initialization
486 00:12:55.047719 INFO : Training has run successfully!
487 00:12:55.048315 Check phy result
488 00:12:55.053305 INFO : End of initialization
489 00:12:55.053856 INFO : End of read enable training
490 00:12:55.058845 INFO : End of fine write leveling
491 00:12:55.064500 INFO : End of Write leveling coarse delay
492 00:12:55.065057 INFO : Training has run successfully!
493 00:12:55.065590 Check phy result
494 00:12:55.070079 INFO : End of initialization
495 00:12:55.070624 INFO : End of read dq deskew training
496 00:12:55.075643 INFO : End of MPR read delay center optimization
497 00:12:55.081224 INFO : End of write delay center optimization
498 00:12:55.086804 INFO : End of read delay center optimization
499 00:12:55.087354 INFO : End of max read latency training
500 00:12:55.092470 INFO : Training has run successfully!
501 00:12:55.093044 1D training succeed
502 00:12:55.101799 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
503 00:12:55.149257 Check phy result
504 00:12:55.149835 INFO : End of initialization
505 00:12:55.171026 INFO : End of 2D read delay Voltage center optimization
506 00:12:55.190459 INFO : End of 2D read delay Voltage center optimization
507 00:12:55.242467 INFO : End of 2D write delay Voltage center optimization
508 00:12:55.291821 INFO : End of 2D write delay Voltage center optimization
509 00:12:55.297475 INFO : Training has run successfully!
510 00:12:55.298036
511 00:12:55.298574 channel==0
512 00:12:55.303014 RxClkDly_Margin_A0==88 ps 9
513 00:12:55.303567 TxDqDly_Margin_A0==98 ps 10
514 00:12:55.308713 RxClkDly_Margin_A1==88 ps 9
515 00:12:55.309271 TxDqDly_Margin_A1==98 ps 10
516 00:12:55.309815 TrainedVREFDQ_A0==74
517 00:12:55.314212 TrainedVREFDQ_A1==74
518 00:12:55.314783 VrefDac_Margin_A0==25
519 00:12:55.315309 DeviceVref_Margin_A0==40
520 00:12:55.319823 VrefDac_Margin_A1==25
521 00:12:55.320434 DeviceVref_Margin_A1==40
522 00:12:55.320974
523 00:12:55.321495
524 00:12:55.325546 channel==1
525 00:12:55.326112 RxClkDly_Margin_A0==98 ps 10
526 00:12:55.326644 TxDqDly_Margin_A0==88 ps 9
527 00:12:55.331020 RxClkDly_Margin_A1==88 ps 9
528 00:12:55.331572 TxDqDly_Margin_A1==98 ps 10
529 00:12:55.336717 TrainedVREFDQ_A0==76
530 00:12:55.337275 TrainedVREFDQ_A1==77
531 00:12:55.337804 VrefDac_Margin_A0==23
532 00:12:55.342204 DeviceVref_Margin_A0==38
533 00:12:55.342755 VrefDac_Margin_A1==24
534 00:12:55.347836 DeviceVref_Margin_A1==37
535 00:12:55.348402
536 00:12:55.348936 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
537 00:12:55.349452
538 00:12:55.381391 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000016 00000018 00000019 00000017 00000019 00000018 0000001a 0000001a 00000018 00000017 00000018 00000017 00000019 00000018 00000018 00000019 00000019 00000019 00000016 00000019 00000017 dram_vref_reg_value 0x 0000005f
539 00:12:55.382000 2D training succeed
540 00:12:55.387017 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
541 00:12:55.392775 auto size-- 65535DDR cs0 size: 2048MB
542 00:12:55.393330 DDR cs1 size: 2048MB
543 00:12:55.398196 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
544 00:12:55.398757 cs0 DataBus test pass
545 00:12:55.403828 cs1 DataBus test pass
546 00:12:55.404405 cs0 AddrBus test pass
547 00:12:55.404934 cs1 AddrBus test pass
548 00:12:55.405447
549 00:12:55.409415 100bdlr_step_size ps== 420
550 00:12:55.410026 result report
551 00:12:55.415074 boot times 0Enable ddr reg access
552 00:12:55.420355 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
553 00:12:55.433844 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
554 00:12:56.007169 0.0;M3 CHK:0;cm4_sp_mode 0
555 00:12:56.007900 MVN_1=0x00000000
556 00:12:56.012674 MVN_2=0x00000000
557 00:12:56.018443 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
558 00:12:56.019073 OPS=0x10
559 00:12:56.019656 ring efuse init
560 00:12:56.020222 chipver efuse init
561 00:12:56.024059 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
562 00:12:56.029565 [0.018961 Inits done]
563 00:12:56.030107 secure task start!
564 00:12:56.030612 high task start!
565 00:12:56.034168 low task start!
566 00:12:56.034726 run into bl31
567 00:12:56.040699 NOTICE: BL31: v1.3(release):4fc40b1
568 00:12:56.048719 NOTICE: BL31: Built : 15:58:17, May 22 2019
569 00:12:56.049280 NOTICE: BL31: G12A normal boot!
570 00:12:56.074072 NOTICE: BL31: BL33 decompress pass
571 00:12:56.079658 ERROR: Error initializing runtime service opteed_fast
572 00:12:57.312658
573 00:12:57.313484
574 00:12:57.321204 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
575 00:12:57.322213
576 00:12:57.323599 Model: Libre Computer AML-A311D-CC Alta
577 00:12:57.529494 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
578 00:12:57.552908 DRAM: 2 GiB (effective 3.8 GiB)
579 00:12:57.695914 Core: 408 devices, 31 uclasses, devicetree: separate
580 00:12:57.701688 WDT: Not starting watchdog@f0d0
581 00:12:57.733979 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
582 00:12:57.746291 Loading Environment from FAT... Card did not respond to voltage select! : -110
583 00:12:57.751445 ** Bad device specification mmc 0 **
584 00:12:57.761790 Card did not respond to voltage select! : -110
585 00:12:57.769404 ** Bad device specification mmc 0 **
586 00:12:57.769906 Couldn't find partition mmc 0
587 00:12:57.777618 Card did not respond to voltage select! : -110
588 00:12:57.783156 ** Bad device specification mmc 0 **
589 00:12:57.783591 Couldn't find partition mmc 0
590 00:12:57.787388 Error: could not access storage.
591 00:12:58.130829 Net: eth0: ethernet@ff3f0000
592 00:12:58.131396 starting USB...
593 00:12:58.382533 Bus usb@ff500000: Register 3000140 NbrPorts 3
594 00:12:58.383111 Starting the controller
595 00:12:58.389472 USB XHCI 1.10
596 00:13:00.102550 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
597 00:13:00.103158 bl2_stage_init 0x01
598 00:13:00.103580 bl2_stage_init 0x81
599 00:13:00.108244 hw id: 0x0000 - pwm id 0x01
600 00:13:00.108705 bl2_stage_init 0xc1
601 00:13:00.109113 bl2_stage_init 0x02
602 00:13:00.109513
603 00:13:00.113660 L0:00000000
604 00:13:00.114108 L1:20000703
605 00:13:00.114514 L2:00008067
606 00:13:00.114911 L3:14000000
607 00:13:00.119282 B2:00402000
608 00:13:00.119723 B1:e0f83180
609 00:13:00.120164
610 00:13:00.120566 TE: 58124
611 00:13:00.120964
612 00:13:00.124923 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
613 00:13:00.125389
614 00:13:00.125793 Board ID = 1
615 00:13:00.130506 Set A53 clk to 24M
616 00:13:00.130956 Set A73 clk to 24M
617 00:13:00.131357 Set clk81 to 24M
618 00:13:00.136087 A53 clk: 1200 MHz
619 00:13:00.136528 A73 clk: 1200 MHz
620 00:13:00.136929 CLK81: 166.6M
621 00:13:00.137326 smccc: 00012a92
622 00:13:00.141709 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
623 00:13:00.147279 board id: 1
624 00:13:00.153359 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
625 00:13:00.163757 fw parse done
626 00:13:00.169710 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
627 00:13:00.212303 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
628 00:13:00.223203 PIEI prepare done
629 00:13:00.223789 fastboot data load
630 00:13:00.224411 fastboot data verify
631 00:13:00.228864 verify result: 266
632 00:13:00.234433 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
633 00:13:00.235009 LPDDR4 probe
634 00:13:00.235534 ddr clk to 1584MHz
635 00:13:00.242541 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
636 00:13:00.279722
637 00:13:00.280378 dmc_version 0001
638 00:13:00.286433 Check phy result
639 00:13:00.292261 INFO : End of CA training
640 00:13:00.292851 INFO : End of initialization
641 00:13:00.297894 INFO : Training has run successfully!
642 00:13:00.298456 Check phy result
643 00:13:00.303486 INFO : End of initialization
644 00:13:00.304073 INFO : End of read enable training
645 00:13:00.306770 INFO : End of fine write leveling
646 00:13:00.312264 INFO : End of Write leveling coarse delay
647 00:13:00.317889 INFO : Training has run successfully!
648 00:13:00.318460 Check phy result
649 00:13:00.318979 INFO : End of initialization
650 00:13:00.323541 INFO : End of read dq deskew training
651 00:13:00.326953 INFO : End of MPR read delay center optimization
652 00:13:00.332486 INFO : End of write delay center optimization
653 00:13:00.338252 INFO : End of read delay center optimization
654 00:13:00.338837 INFO : End of max read latency training
655 00:13:00.343752 INFO : Training has run successfully!
656 00:13:00.344325 1D training succeed
657 00:13:00.351914 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
658 00:13:00.399433 Check phy result
659 00:13:00.400077 INFO : End of initialization
660 00:13:00.421269 INFO : End of 2D read delay Voltage center optimization
661 00:13:00.441465 INFO : End of 2D read delay Voltage center optimization
662 00:13:00.493697 INFO : End of 2D write delay Voltage center optimization
663 00:13:00.542943 INFO : End of 2D write delay Voltage center optimization
664 00:13:00.548538 INFO : Training has run successfully!
665 00:13:00.549136
666 00:13:00.549674 channel==0
667 00:13:00.554070 RxClkDly_Margin_A0==88 ps 9
668 00:13:00.554666 TxDqDly_Margin_A0==98 ps 10
669 00:13:00.557298 RxClkDly_Margin_A1==88 ps 9
670 00:13:00.557771 TxDqDly_Margin_A1==98 ps 10
671 00:13:00.562743 TrainedVREFDQ_A0==74
672 00:13:00.563204 TrainedVREFDQ_A1==75
673 00:13:00.568480 VrefDac_Margin_A0==25
674 00:13:00.568948 DeviceVref_Margin_A0==40
675 00:13:00.569355 VrefDac_Margin_A1==25
676 00:13:00.574081 DeviceVref_Margin_A1==39
677 00:13:00.574541
678 00:13:00.574951
679 00:13:00.575353 channel==1
680 00:13:00.575749 RxClkDly_Margin_A0==98 ps 10
681 00:13:00.579684 TxDqDly_Margin_A0==98 ps 10
682 00:13:00.580161 RxClkDly_Margin_A1==88 ps 9
683 00:13:00.585243 TxDqDly_Margin_A1==88 ps 9
684 00:13:00.585691 TrainedVREFDQ_A0==77
685 00:13:00.586098 TrainedVREFDQ_A1==77
686 00:13:00.590777 VrefDac_Margin_A0==22
687 00:13:00.591219 DeviceVref_Margin_A0==37
688 00:13:00.596490 VrefDac_Margin_A1==24
689 00:13:00.596955 DeviceVref_Margin_A1==37
690 00:13:00.597358
691 00:13:00.602030 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
692 00:13:00.602481
693 00:13:00.630012 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000019 00000018 00000018 00000016 00000017 00000015 00000017 00000019 00000018 00000019 00000018 0000001a 0000001a 00000018 00000017 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
694 00:13:00.635612 2D training succeed
695 00:13:00.641267 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
696 00:13:00.641716 auto size-- 65535DDR cs0 size: 2048MB
697 00:13:00.646809 DDR cs1 size: 2048MB
698 00:13:00.647242 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
699 00:13:00.652503 cs0 DataBus test pass
700 00:13:00.652952 cs1 DataBus test pass
701 00:13:00.653354 cs0 AddrBus test pass
702 00:13:00.658025 cs1 AddrBus test pass
703 00:13:00.658457
704 00:13:00.658860 100bdlr_step_size ps== 420
705 00:13:00.659268 result report
706 00:13:00.663608 boot times 0Enable ddr reg access
707 00:13:00.671342 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
708 00:13:00.684838 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
709 00:13:01.258466 0.0;M3 CHK:0;cm4_sp_mode 0
710 00:13:01.259072 MVN_1=0x00000000
711 00:13:01.263870 MVN_2=0x00000000
712 00:13:01.269645 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
713 00:13:01.270142 OPS=0x10
714 00:13:01.270555 ring efuse init
715 00:13:01.270944 chipver efuse init
716 00:13:01.275227 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
717 00:13:01.280837 [0.018961 Inits done]
718 00:13:01.281274 secure task start!
719 00:13:01.281665 high task start!
720 00:13:01.285431 low task start!
721 00:13:01.285851 run into bl31
722 00:13:01.292111 NOTICE: BL31: v1.3(release):4fc40b1
723 00:13:01.299897 NOTICE: BL31: Built : 15:58:17, May 22 2019
724 00:13:01.300444 NOTICE: BL31: G12A normal boot!
725 00:13:01.325273 NOTICE: BL31: BL33 decompress pass
726 00:13:01.330919 ERROR: Error initializing runtime service opteed_fast
727 00:13:02.563910
728 00:13:02.564599
729 00:13:02.572203 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
730 00:13:02.572745
731 00:13:02.573194 Model: Libre Computer AML-A311D-CC Alta
732 00:13:02.780708 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
733 00:13:02.804086 DRAM: 2 GiB (effective 3.8 GiB)
734 00:13:02.947099 Core: 408 devices, 31 uclasses, devicetree: separate
735 00:13:02.952940 WDT: Not starting watchdog@f0d0
736 00:13:02.985163 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
737 00:13:02.997762 Loading Environment from FAT... Card did not respond to voltage select! : -110
738 00:13:03.002610 ** Bad device specification mmc 0 **
739 00:13:03.012951 Card did not respond to voltage select! : -110
740 00:13:03.020555 ** Bad device specification mmc 0 **
741 00:13:03.021049 Couldn't find partition mmc 0
742 00:13:03.028879 Card did not respond to voltage select! : -110
743 00:13:03.034460 ** Bad device specification mmc 0 **
744 00:13:03.034919 Couldn't find partition mmc 0
745 00:13:03.039637 Error: could not access storage.
746 00:13:03.383041 Net: eth0: ethernet@ff3f0000
747 00:13:03.383685 starting USB...
748 00:13:03.635005 Bus usb@ff500000: Register 3000140 NbrPorts 3
749 00:13:03.635628 Starting the controller
750 00:13:03.641985 USB XHCI 1.10
751 00:13:05.804110 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
752 00:13:05.804745 bl2_stage_init 0x01
753 00:13:05.805173 bl2_stage_init 0x81
754 00:13:05.809789 hw id: 0x0000 - pwm id 0x01
755 00:13:05.810296 bl2_stage_init 0xc1
756 00:13:05.810718 bl2_stage_init 0x02
757 00:13:05.811126
758 00:13:05.815339 L0:00000000
759 00:13:05.815841 L1:20000703
760 00:13:05.816291 L2:00008067
761 00:13:05.816701 L3:14000000
762 00:13:05.818438 B2:00402000
763 00:13:05.818919 B1:e0f83180
764 00:13:05.819327
765 00:13:05.819728 TE: 58167
766 00:13:05.820169
767 00:13:05.829524 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
768 00:13:05.830074
769 00:13:05.830492 Board ID = 1
770 00:13:05.830893 Set A53 clk to 24M
771 00:13:05.831292 Set A73 clk to 24M
772 00:13:05.835294 Set clk81 to 24M
773 00:13:05.835788 A53 clk: 1200 MHz
774 00:13:05.836233 A73 clk: 1200 MHz
775 00:13:05.838708 CLK81: 166.6M
776 00:13:05.839192 smccc: 00012abd
777 00:13:05.844352 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
778 00:13:05.849867 board id: 1
779 00:13:05.854984 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
780 00:13:05.865407 fw parse done
781 00:13:05.871382 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
782 00:13:05.913960 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
783 00:13:05.924975 PIEI prepare done
784 00:13:05.925516 fastboot data load
785 00:13:05.925932 fastboot data verify
786 00:13:05.930552 verify result: 266
787 00:13:05.936222 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
788 00:13:05.936746 LPDDR4 probe
789 00:13:05.937161 ddr clk to 1584MHz
790 00:13:05.944248 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
791 00:13:05.981467
792 00:13:05.982005 dmc_version 0001
793 00:13:05.988115 Check phy result
794 00:13:05.993952 INFO : End of CA training
795 00:13:05.994428 INFO : End of initialization
796 00:13:05.999571 INFO : Training has run successfully!
797 00:13:06.000080 Check phy result
798 00:13:06.005107 INFO : End of initialization
799 00:13:06.005571 INFO : End of read enable training
800 00:13:06.010819 INFO : End of fine write leveling
801 00:13:06.016349 INFO : End of Write leveling coarse delay
802 00:13:06.016834 INFO : Training has run successfully!
803 00:13:06.017241 Check phy result
804 00:13:06.022029 INFO : End of initialization
805 00:13:06.022535 INFO : End of read dq deskew training
806 00:13:06.027628 INFO : End of MPR read delay center optimization
807 00:13:06.033234 INFO : End of write delay center optimization
808 00:13:06.038887 INFO : End of read delay center optimization
809 00:13:06.039420 INFO : End of max read latency training
810 00:13:06.044390 INFO : Training has run successfully!
811 00:13:06.044885 1D training succeed
812 00:13:06.053538 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
813 00:13:06.101090 Check phy result
814 00:13:06.101602 INFO : End of initialization
815 00:13:06.122866 INFO : End of 2D read delay Voltage center optimization
816 00:13:06.143083 INFO : End of 2D read delay Voltage center optimization
817 00:13:06.195189 INFO : End of 2D write delay Voltage center optimization
818 00:13:06.244614 INFO : End of 2D write delay Voltage center optimization
819 00:13:06.250105 INFO : Training has run successfully!
820 00:13:06.250581
821 00:13:06.250994 channel==0
822 00:13:06.255696 RxClkDly_Margin_A0==88 ps 9
823 00:13:06.256233 TxDqDly_Margin_A0==98 ps 10
824 00:13:06.261432 RxClkDly_Margin_A1==88 ps 9
825 00:13:06.261902 TxDqDly_Margin_A1==98 ps 10
826 00:13:06.262327 TrainedVREFDQ_A0==74
827 00:13:06.266970 TrainedVREFDQ_A1==74
828 00:13:06.267456 VrefDac_Margin_A0==25
829 00:13:06.267864 DeviceVref_Margin_A0==40
830 00:13:06.272492 VrefDac_Margin_A1==25
831 00:13:06.272970 DeviceVref_Margin_A1==40
832 00:13:06.273357
833 00:13:06.273742
834 00:13:06.278026 channel==1
835 00:13:06.278477 RxClkDly_Margin_A0==98 ps 10
836 00:13:06.278866 TxDqDly_Margin_A0==88 ps 9
837 00:13:06.283730 RxClkDly_Margin_A1==98 ps 10
838 00:13:06.284233 TxDqDly_Margin_A1==88 ps 9
839 00:13:06.289326 TrainedVREFDQ_A0==76
840 00:13:06.289815 TrainedVREFDQ_A1==77
841 00:13:06.290208 VrefDac_Margin_A0==22
842 00:13:06.294867 DeviceVref_Margin_A0==38
843 00:13:06.295352 VrefDac_Margin_A1==22
844 00:13:06.300472 DeviceVref_Margin_A1==37
845 00:13:06.300982
846 00:13:06.301381 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
847 00:13:06.301771
848 00:13:06.333996 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000018 00000019 00000018 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 00000019 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
849 00:13:06.334543 2D training succeed
850 00:13:06.339616 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
851 00:13:06.345228 auto size-- 65535DDR cs0 size: 2048MB
852 00:13:06.345683 DDR cs1 size: 2048MB
853 00:13:06.350806 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
854 00:13:06.351269 cs0 DataBus test pass
855 00:13:06.356490 cs1 DataBus test pass
856 00:13:06.356966 cs0 AddrBus test pass
857 00:13:06.357353 cs1 AddrBus test pass
858 00:13:06.357735
859 00:13:06.362024 100bdlr_step_size ps== 420
860 00:13:06.362498 result report
861 00:13:06.367621 boot times 0Enable ddr reg access
862 00:13:06.372965 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
863 00:13:06.386443 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
864 00:13:06.960091 0.0;M3 CHK:0;cm4_sp_mode 0
865 00:13:06.960527 MVN_1=0x00000000
866 00:13:06.965518 MVN_2=0x00000000
867 00:13:06.971300 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
868 00:13:06.971713 OPS=0x10
869 00:13:06.971976 ring efuse init
870 00:13:06.972226 chipver efuse init
871 00:13:06.976875 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
872 00:13:06.982469 [0.018961 Inits done]
873 00:13:06.982770 secure task start!
874 00:13:06.982998 high task start!
875 00:13:06.987114 low task start!
876 00:13:06.987414 run into bl31
877 00:13:06.993723 NOTICE: BL31: v1.3(release):4fc40b1
878 00:13:07.001535 NOTICE: BL31: Built : 15:58:17, May 22 2019
879 00:13:07.001979 NOTICE: BL31: G12A normal boot!
880 00:13:07.026930 NOTICE: BL31: BL33 decompress pass
881 00:13:07.032585 ERROR: Error initializing runtime service opteed_fast
882 00:13:08.265791
883 00:13:08.266409
884 00:13:08.274039 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
885 00:13:08.274568
886 00:13:08.274989 Model: Libre Computer AML-A311D-CC Alta
887 00:13:08.482475 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
888 00:13:08.505874 DRAM: 2 GiB (effective 3.8 GiB)
889 00:13:08.648677 Core: 408 devices, 31 uclasses, devicetree: separate
890 00:13:08.654558 WDT: Not starting watchdog@f0d0
891 00:13:08.686804 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
892 00:13:08.699224 Loading Environment from FAT... Card did not respond to voltage select! : -110
893 00:13:08.704208 ** Bad device specification mmc 0 **
894 00:13:08.714582 Card did not respond to voltage select! : -110
895 00:13:08.722198 ** Bad device specification mmc 0 **
896 00:13:08.722519 Couldn't find partition mmc 0
897 00:13:08.730539 Card did not respond to voltage select! : -110
898 00:13:08.736039 ** Bad device specification mmc 0 **
899 00:13:08.736432 Couldn't find partition mmc 0
900 00:13:08.741085 Error: could not access storage.
901 00:13:09.083696 Net: eth0: ethernet@ff3f0000
902 00:13:09.084159 starting USB...
903 00:13:09.335462 Bus usb@ff500000: Register 3000140 NbrPorts 3
904 00:13:09.335894 Starting the controller
905 00:13:09.342402 USB XHCI 1.10
906 00:13:11.203953 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
907 00:13:11.204587 bl2_stage_init 0x01
908 00:13:11.205012 bl2_stage_init 0x81
909 00:13:11.209574 hw id: 0x0000 - pwm id 0x01
910 00:13:11.210042 bl2_stage_init 0xc1
911 00:13:11.210453 bl2_stage_init 0x02
912 00:13:11.210857
913 00:13:11.215155 L0:00000000
914 00:13:11.215610 L1:20000703
915 00:13:11.216042 L2:00008067
916 00:13:11.216445 L3:14000000
917 00:13:11.220724 B2:00402000
918 00:13:11.221183 B1:e0f83180
919 00:13:11.221590
920 00:13:11.221992 TE: 58167
921 00:13:11.222390
922 00:13:11.226339 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
923 00:13:11.226814
924 00:13:11.227233 Board ID = 1
925 00:13:11.231968 Set A53 clk to 24M
926 00:13:11.232454 Set A73 clk to 24M
927 00:13:11.232859 Set clk81 to 24M
928 00:13:11.237553 A53 clk: 1200 MHz
929 00:13:11.238008 A73 clk: 1200 MHz
930 00:13:11.238409 CLK81: 166.6M
931 00:13:11.238803 smccc: 00012abd
932 00:13:11.243147 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
933 00:13:11.248731 board id: 1
934 00:13:11.254642 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
935 00:13:11.265283 fw parse done
936 00:13:11.271289 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
937 00:13:11.313968 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
938 00:13:11.324758 PIEI prepare done
939 00:13:11.325203 fastboot data load
940 00:13:11.325597 fastboot data verify
941 00:13:11.330452 verify result: 266
942 00:13:11.336082 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
943 00:13:11.336531 LPDDR4 probe
944 00:13:11.336918 ddr clk to 1584MHz
945 00:13:11.344091 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
946 00:13:11.381279
947 00:13:11.381742 dmc_version 0001
948 00:13:11.388101 Check phy result
949 00:13:11.393841 INFO : End of CA training
950 00:13:11.394283 INFO : End of initialization
951 00:13:11.399574 INFO : Training has run successfully!
952 00:13:11.400072 Check phy result
953 00:13:11.405217 INFO : End of initialization
954 00:13:11.405671 INFO : End of read enable training
955 00:13:11.408407 INFO : End of fine write leveling
956 00:13:11.413973 INFO : End of Write leveling coarse delay
957 00:13:11.419637 INFO : Training has run successfully!
958 00:13:11.420113 Check phy result
959 00:13:11.420518 INFO : End of initialization
960 00:13:11.425158 INFO : End of read dq deskew training
961 00:13:11.428671 INFO : End of MPR read delay center optimization
962 00:13:11.434184 INFO : End of write delay center optimization
963 00:13:11.439867 INFO : End of read delay center optimization
964 00:13:11.440362 INFO : End of max read latency training
965 00:13:11.445370 INFO : Training has run successfully!
966 00:13:11.445821 1D training succeed
967 00:13:11.453628 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
968 00:13:11.501170 Check phy result
969 00:13:11.501628 INFO : End of initialization
970 00:13:11.523707 INFO : End of 2D read delay Voltage center optimization
971 00:13:11.543917 INFO : End of 2D read delay Voltage center optimization
972 00:13:11.596066 INFO : End of 2D write delay Voltage center optimization
973 00:13:11.645442 INFO : End of 2D write delay Voltage center optimization
974 00:13:11.651041 INFO : Training has run successfully!
975 00:13:11.651494
976 00:13:11.651906 channel==0
977 00:13:11.656644 RxClkDly_Margin_A0==88 ps 9
978 00:13:11.657095 TxDqDly_Margin_A0==98 ps 10
979 00:13:11.662211 RxClkDly_Margin_A1==78 ps 8
980 00:13:11.662660 TxDqDly_Margin_A1==98 ps 10
981 00:13:11.663068 TrainedVREFDQ_A0==74
982 00:13:11.667886 TrainedVREFDQ_A1==74
983 00:13:11.668357 VrefDac_Margin_A0==25
984 00:13:11.668764 DeviceVref_Margin_A0==40
985 00:13:11.673425 VrefDac_Margin_A1==26
986 00:13:11.673874 DeviceVref_Margin_A1==40
987 00:13:11.674275
988 00:13:11.674673
989 00:13:11.678941 channel==1
990 00:13:11.679390 RxClkDly_Margin_A0==98 ps 10
991 00:13:11.679793 TxDqDly_Margin_A0==98 ps 10
992 00:13:11.684621 RxClkDly_Margin_A1==98 ps 10
993 00:13:11.685070 TxDqDly_Margin_A1==98 ps 10
994 00:13:11.690188 TrainedVREFDQ_A0==76
995 00:13:11.690654 TrainedVREFDQ_A1==77
996 00:13:11.691064 VrefDac_Margin_A0==22
997 00:13:11.695921 DeviceVref_Margin_A0==38
998 00:13:11.696394 VrefDac_Margin_A1==22
999 00:13:11.701313 DeviceVref_Margin_A1==37
1000 00:13:11.701761
1001 00:13:11.702167 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
1002 00:13:11.706905
1003 00:13:11.734875 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000018 00000018 00000016 00000017 00000015 00000018 00000019 00000018 00000019 00000018 0000001a 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000018 00000018 dram_vref_reg_value 0x 00000060
1004 00:13:11.735362 2D training succeed
1005 00:13:11.740522 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
1006 00:13:11.746095 auto size-- 65535DDR cs0 size: 2048MB
1007 00:13:11.746545 DDR cs1 size: 2048MB
1008 00:13:11.751714 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
1009 00:13:11.752200 cs0 DataBus test pass
1010 00:13:11.757311 cs1 DataBus test pass
1011 00:13:11.757763 cs0 AddrBus test pass
1012 00:13:11.758172 cs1 AddrBus test pass
1013 00:13:11.758571
1014 00:13:11.762935 100bdlr_step_size ps== 432
1015 00:13:11.763394 result report
1016 00:13:11.768499 boot times 0Enable ddr reg access
1017 00:13:11.774055 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
1018 00:13:11.787488 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
1019 00:13:12.360400 0.0;M3 CHK:0;cm4_sp_mode 0
1020 00:13:12.360984 MVN_1=0x00000000
1021 00:13:12.365942 MVN_2=0x00000000
1022 00:13:12.371711 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
1023 00:13:12.372253 OPS=0x10
1024 00:13:12.372674 ring efuse init
1025 00:13:12.373075 chipver efuse init
1026 00:13:12.377310 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
1027 00:13:12.382884 [0.018960 Inits done]
1028 00:13:12.383349 secure task start!
1029 00:13:12.383753 high task start!
1030 00:13:12.387470 low task start!
1031 00:13:12.387924 run into bl31
1032 00:13:12.394147 NOTICE: BL31: v1.3(release):4fc40b1
1033 00:13:12.401920 NOTICE: BL31: Built : 15:58:17, May 22 2019
1034 00:13:12.402395 NOTICE: BL31: G12A normal boot!
1035 00:13:12.427245 NOTICE: BL31: BL33 decompress pass
1036 00:13:12.432969 ERROR: Error initializing runtime service opteed_fast
1037 00:13:13.665742
1038 00:13:13.666170
1039 00:13:13.674259 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
1040 00:13:13.674692
1041 00:13:13.675055 Model: Libre Computer AML-A311D-CC Alta
1042 00:13:13.882577 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
1043 00:13:13.905954 DRAM: 2 GiB (effective 3.8 GiB)
1044 00:13:14.049059 Core: 408 devices, 31 uclasses, devicetree: separate
1045 00:13:14.054850 WDT: Not starting watchdog@f0d0
1046 00:13:14.087149 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
1047 00:13:14.099543 Loading Environment from FAT... Card did not respond to voltage select! : -110
1048 00:13:14.104571 ** Bad device specification mmc 0 **
1049 00:13:14.114893 Card did not respond to voltage select! : -110
1050 00:13:14.122516 ** Bad device specification mmc 0 **
1051 00:13:14.122812 Couldn't find partition mmc 0
1052 00:13:14.130905 Card did not respond to voltage select! : -110
1053 00:13:14.136410 ** Bad device specification mmc 0 **
1054 00:13:14.136855 Couldn't find partition mmc 0
1055 00:13:14.141469 Error: could not access storage.
1056 00:13:14.485023 Net: eth0: ethernet@ff3f0000
1057 00:13:14.485662 starting USB...
1058 00:13:14.736871 Bus usb@ff500000: Register 3000140 NbrPorts 3
1059 00:13:14.737432 Starting the controller
1060 00:13:14.743811 USB XHCI 1.10
1061 00:13:16.300886 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
1062 00:13:16.309150 scanning usb for storage devices... 0 Storage Device(s) found
1064 00:13:16.360670 Hit any key to stop autoboot: 1
1065 00:13:16.361499 end: 2.4.2 bootloader-interrupt (duration 00:00:36) [common]
1066 00:13:16.362121 start: 2.4.3 bootloader-commands (timeout 00:04:23) [common]
1067 00:13:16.362579 Setting prompt string to ['=>']
1068 00:13:16.363046 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:23)
1069 00:13:16.376717 0
1070 00:13:16.377564 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1071 00:13:16.378031 Sending with 10 millisecond of delay
1073 00:13:17.512467 => setenv autoload no
1074 00:13:17.523207 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:22)
1075 00:13:17.528030 setenv autoload no
1076 00:13:17.528749 Sending with 10 millisecond of delay
1078 00:13:19.326180 => setenv initrd_high 0xffffffff
1079 00:13:19.336965 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:20)
1080 00:13:19.337880 setenv initrd_high 0xffffffff
1081 00:13:19.338605 Sending with 10 millisecond of delay
1083 00:13:20.956411 => setenv fdt_high 0xffffffff
1084 00:13:20.967212 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:19)
1085 00:13:20.968138 setenv fdt_high 0xffffffff
1086 00:13:20.968853 Sending with 10 millisecond of delay
1088 00:13:21.260686 => dhcp
1089 00:13:21.271448 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1090 00:13:21.272341 dhcp
1091 00:13:21.272780 Speed: 1000, full duplex
1092 00:13:21.273194 BOOTP broadcast 1
1093 00:13:21.284490 DHCP client bound to address 192.168.6.27 (12 ms)
1094 00:13:21.285225 Sending with 10 millisecond of delay
1096 00:13:22.961965 => setenv serverip 192.168.6.2
1097 00:13:22.973330 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:17)
1098 00:13:22.974001 setenv serverip 192.168.6.2
1099 00:13:22.974463 Sending with 10 millisecond of delay
1101 00:13:26.703098 => tftpboot 0x01080000 919146/tftp-deploy-ovdj3btp/kernel/uImage
1102 00:13:26.713982 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:13)
1103 00:13:26.714958 tftpboot 0x01080000 919146/tftp-deploy-ovdj3btp/kernel/uImage
1104 00:13:26.715505 Speed: 1000, full duplex
1105 00:13:26.716065 Using ethernet@ff3f0000 device
1106 00:13:26.716970 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1107 00:13:26.722621 Filename '919146/tftp-deploy-ovdj3btp/kernel/uImage'.
1108 00:13:26.726432 Load address: 0x1080000
1109 00:13:29.628409 Loading: *################################################## 43.6 MiB
1110 00:13:29.628801 15 MiB/s
1111 00:13:29.629012 done
1112 00:13:29.631806 Bytes transferred = 45716032 (2b99240 hex)
1113 00:13:29.632374 Sending with 10 millisecond of delay
1115 00:13:34.318898 => tftpboot 0x08000000 919146/tftp-deploy-ovdj3btp/ramdisk/ramdisk.cpio.gz.uboot
1116 00:13:34.329652 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:05)
1117 00:13:34.330185 tftpboot 0x08000000 919146/tftp-deploy-ovdj3btp/ramdisk/ramdisk.cpio.gz.uboot
1118 00:13:34.330426 Speed: 1000, full duplex
1119 00:13:34.330636 Using ethernet@ff3f0000 device
1120 00:13:34.332263 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1121 00:13:34.344230 Filename '919146/tftp-deploy-ovdj3btp/ramdisk/ramdisk.cpio.gz.uboot'.
1122 00:13:34.344692 Load address: 0x8000000
1123 00:13:36.729250 Loading: *######## UDP wrong checksum 000000ff 0000ccd5
1124 00:13:36.772543 UDP wrong checksum 000000ff 000067c8
1125 00:13:43.517274 T ######################################### UDP wrong checksum 0000000f 0000807a
1126 00:13:48.518891 T UDP wrong checksum 0000000f 0000807a
1127 00:13:49.596530 UDP wrong checksum 000000ff 00005cf6
1128 00:13:49.608391 UDP wrong checksum 000000ff 0000f1e8
1129 00:13:50.191892 UDP wrong checksum 000000ff 000028b7
1130 00:13:50.210558 UDP wrong checksum 000000ff 0000bca9
1131 00:13:55.980386 T UDP wrong checksum 000000ff 00008f8e
1132 00:13:56.020322 UDP wrong checksum 000000ff 00001f81
1133 00:13:58.520920 T UDP wrong checksum 0000000f 0000807a
1134 00:14:04.171026 T UDP wrong checksum 000000ff 00002751
1135 00:14:04.210777 UDP wrong checksum 000000ff 0000b243
1136 00:14:18.524637 T T T UDP wrong checksum 0000000f 0000807a
1137 00:14:33.528935 T T
1138 00:14:33.529357 Retry count exceeded; starting again
1140 00:14:33.530215 end: 2.4.3 bootloader-commands (duration 00:01:17) [common]
1143 00:14:33.531135 end: 2.4 uboot-commands (duration 00:01:54) [common]
1145 00:14:33.531823 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
1147 00:14:33.532417 end: 2 uboot-action (duration 00:01:54) [common]
1149 00:14:33.533249 Cleaning after the job
1150 00:14:33.533564 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/919146/tftp-deploy-ovdj3btp/ramdisk
1151 00:14:33.534490 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/919146/tftp-deploy-ovdj3btp/kernel
1152 00:14:33.540078 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/919146/tftp-deploy-ovdj3btp/dtb
1153 00:14:33.540872 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/919146/tftp-deploy-ovdj3btp/modules
1154 00:14:33.544427 start: 4.1 power-off (timeout 00:00:30) [common]
1155 00:14:33.545016 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1156 00:14:33.578081 >> OK - accepted request
1157 00:14:33.580215 Returned 0 in 0 seconds
1158 00:14:33.681026 end: 4.1 power-off (duration 00:00:00) [common]
1160 00:14:33.682095 start: 4.2 read-feedback (timeout 00:10:00) [common]
1161 00:14:33.682774 Listened to connection for namespace 'common' for up to 1s
1162 00:14:34.683691 Finalising connection for namespace 'common'
1163 00:14:34.684193 Disconnecting from shell: Finalise
1164 00:14:34.684468 =>
1165 00:14:34.785135 end: 4.2 read-feedback (duration 00:00:01) [common]
1166 00:14:34.785637 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/919146
1167 00:14:35.415436 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/919146
1168 00:14:35.416029 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.