Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 1
- Kernel Warnings: 5
- Errors: 0
- Boot result: PASS
- Kernel Errors: 3
1 00:14:59.410339 lava-dispatcher, installed at version: 2024.01
2 00:14:59.411101 start: 0 validate
3 00:14:59.411588 Start time: 2024-11-01 00:14:59.411558+00:00 (UTC)
4 00:14:59.412153 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 00:14:59.412700 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 00:14:59.451044 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 00:14:59.451602 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fpending-fixes%2Fv6.12-rc5-415-g78b16920c1e2%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 00:14:59.481754 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 00:14:59.482369 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fpending-fixes%2Fv6.12-rc5-415-g78b16920c1e2%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 00:14:59.511154 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 00:14:59.511929 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 00:14:59.543011 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 00:14:59.543493 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fpending-fixes%2Fv6.12-rc5-415-g78b16920c1e2%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
14 00:14:59.583313 validate duration: 0.17
16 00:14:59.584174 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 00:14:59.584520 start: 1.1 download-retry (timeout 00:10:00) [common]
18 00:14:59.584850 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 00:14:59.585434 Not decompressing ramdisk as can be used compressed.
20 00:14:59.585875 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 00:14:59.586163 saving as /var/lib/lava/dispatcher/tmp/919150/tftp-deploy-34_gl3d2/ramdisk/initrd.cpio.gz
22 00:14:59.586442 total size: 5628169 (5 MB)
23 00:14:59.623599 progress 0 % (0 MB)
24 00:14:59.627881 progress 5 % (0 MB)
25 00:14:59.632003 progress 10 % (0 MB)
26 00:14:59.635680 progress 15 % (0 MB)
27 00:14:59.639708 progress 20 % (1 MB)
28 00:14:59.643316 progress 25 % (1 MB)
29 00:14:59.647401 progress 30 % (1 MB)
30 00:14:59.651408 progress 35 % (1 MB)
31 00:14:59.655006 progress 40 % (2 MB)
32 00:14:59.659011 progress 45 % (2 MB)
33 00:14:59.662600 progress 50 % (2 MB)
34 00:14:59.666531 progress 55 % (2 MB)
35 00:14:59.670534 progress 60 % (3 MB)
36 00:14:59.674133 progress 65 % (3 MB)
37 00:14:59.678011 progress 70 % (3 MB)
38 00:14:59.681585 progress 75 % (4 MB)
39 00:14:59.685534 progress 80 % (4 MB)
40 00:14:59.688968 progress 85 % (4 MB)
41 00:14:59.692608 progress 90 % (4 MB)
42 00:14:59.696277 progress 95 % (5 MB)
43 00:14:59.699506 progress 100 % (5 MB)
44 00:14:59.700155 5 MB downloaded in 0.11 s (47.21 MB/s)
45 00:14:59.700674 end: 1.1.1 http-download (duration 00:00:00) [common]
47 00:14:59.701572 end: 1.1 download-retry (duration 00:00:00) [common]
48 00:14:59.701863 start: 1.2 download-retry (timeout 00:10:00) [common]
49 00:14:59.702131 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 00:14:59.702602 downloading http://storage.kernelci.org/next/pending-fixes/v6.12-rc5-415-g78b16920c1e2/arm64/defconfig/gcc-12/kernel/Image
51 00:14:59.702840 saving as /var/lib/lava/dispatcher/tmp/919150/tftp-deploy-34_gl3d2/kernel/Image
52 00:14:59.703051 total size: 45715968 (43 MB)
53 00:14:59.703259 No compression specified
54 00:14:59.740807 progress 0 % (0 MB)
55 00:14:59.768103 progress 5 % (2 MB)
56 00:14:59.795195 progress 10 % (4 MB)
57 00:14:59.822767 progress 15 % (6 MB)
58 00:14:59.850403 progress 20 % (8 MB)
59 00:14:59.877379 progress 25 % (10 MB)
60 00:14:59.905124 progress 30 % (13 MB)
61 00:14:59.932434 progress 35 % (15 MB)
62 00:14:59.962211 progress 40 % (17 MB)
63 00:14:59.989133 progress 45 % (19 MB)
64 00:15:00.016135 progress 50 % (21 MB)
65 00:15:00.043348 progress 55 % (24 MB)
66 00:15:00.070268 progress 60 % (26 MB)
67 00:15:00.097583 progress 65 % (28 MB)
68 00:15:00.124987 progress 70 % (30 MB)
69 00:15:00.152452 progress 75 % (32 MB)
70 00:15:00.179731 progress 80 % (34 MB)
71 00:15:00.206871 progress 85 % (37 MB)
72 00:15:00.234055 progress 90 % (39 MB)
73 00:15:00.261443 progress 95 % (41 MB)
74 00:15:00.287787 progress 100 % (43 MB)
75 00:15:00.288341 43 MB downloaded in 0.59 s (74.49 MB/s)
76 00:15:00.288828 end: 1.2.1 http-download (duration 00:00:01) [common]
78 00:15:00.289650 end: 1.2 download-retry (duration 00:00:01) [common]
79 00:15:00.289929 start: 1.3 download-retry (timeout 00:09:59) [common]
80 00:15:00.290195 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 00:15:00.290664 downloading http://storage.kernelci.org/next/pending-fixes/v6.12-rc5-415-g78b16920c1e2/arm64/defconfig/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
82 00:15:00.290944 saving as /var/lib/lava/dispatcher/tmp/919150/tftp-deploy-34_gl3d2/dtb/meson-g12b-a311d-libretech-cc.dtb
83 00:15:00.291157 total size: 54703 (0 MB)
84 00:15:00.291365 No compression specified
85 00:15:00.332899 progress 59 % (0 MB)
86 00:15:00.333748 progress 100 % (0 MB)
87 00:15:00.334308 0 MB downloaded in 0.04 s (1.21 MB/s)
88 00:15:00.334802 end: 1.3.1 http-download (duration 00:00:00) [common]
90 00:15:00.335627 end: 1.3 download-retry (duration 00:00:00) [common]
91 00:15:00.335894 start: 1.4 download-retry (timeout 00:09:59) [common]
92 00:15:00.336205 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 00:15:00.336663 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 00:15:00.336913 saving as /var/lib/lava/dispatcher/tmp/919150/tftp-deploy-34_gl3d2/nfsrootfs/full.rootfs.tar
95 00:15:00.337120 total size: 120894716 (115 MB)
96 00:15:00.337333 Using unxz to decompress xz
97 00:15:00.374311 progress 0 % (0 MB)
98 00:15:01.170127 progress 5 % (5 MB)
99 00:15:02.014646 progress 10 % (11 MB)
100 00:15:02.806381 progress 15 % (17 MB)
101 00:15:03.546611 progress 20 % (23 MB)
102 00:15:04.139699 progress 25 % (28 MB)
103 00:15:04.971288 progress 30 % (34 MB)
104 00:15:05.763418 progress 35 % (40 MB)
105 00:15:06.109394 progress 40 % (46 MB)
106 00:15:06.481804 progress 45 % (51 MB)
107 00:15:07.211081 progress 50 % (57 MB)
108 00:15:08.104253 progress 55 % (63 MB)
109 00:15:08.891036 progress 60 % (69 MB)
110 00:15:09.651718 progress 65 % (74 MB)
111 00:15:10.435352 progress 70 % (80 MB)
112 00:15:11.270654 progress 75 % (86 MB)
113 00:15:12.061606 progress 80 % (92 MB)
114 00:15:12.830161 progress 85 % (98 MB)
115 00:15:13.697576 progress 90 % (103 MB)
116 00:15:14.483273 progress 95 % (109 MB)
117 00:15:15.318332 progress 100 % (115 MB)
118 00:15:15.332216 115 MB downloaded in 15.00 s (7.69 MB/s)
119 00:15:15.333219 end: 1.4.1 http-download (duration 00:00:15) [common]
121 00:15:15.334967 end: 1.4 download-retry (duration 00:00:15) [common]
122 00:15:15.335530 start: 1.5 download-retry (timeout 00:09:44) [common]
123 00:15:15.336158 start: 1.5.1 http-download (timeout 00:09:44) [common]
124 00:15:15.337025 downloading http://storage.kernelci.org/next/pending-fixes/v6.12-rc5-415-g78b16920c1e2/arm64/defconfig/gcc-12/modules.tar.xz
125 00:15:15.337528 saving as /var/lib/lava/dispatcher/tmp/919150/tftp-deploy-34_gl3d2/modules/modules.tar
126 00:15:15.337979 total size: 11602096 (11 MB)
127 00:15:15.338438 Using unxz to decompress xz
128 00:15:15.381558 progress 0 % (0 MB)
129 00:15:15.450335 progress 5 % (0 MB)
130 00:15:15.525965 progress 10 % (1 MB)
131 00:15:15.608346 progress 15 % (1 MB)
132 00:15:15.683975 progress 20 % (2 MB)
133 00:15:15.759645 progress 25 % (2 MB)
134 00:15:15.839004 progress 30 % (3 MB)
135 00:15:15.911408 progress 35 % (3 MB)
136 00:15:15.994381 progress 40 % (4 MB)
137 00:15:16.079002 progress 45 % (5 MB)
138 00:15:16.159124 progress 50 % (5 MB)
139 00:15:16.236949 progress 55 % (6 MB)
140 00:15:16.317287 progress 60 % (6 MB)
141 00:15:16.400787 progress 65 % (7 MB)
142 00:15:16.475735 progress 70 % (7 MB)
143 00:15:16.557092 progress 75 % (8 MB)
144 00:15:16.640130 progress 80 % (8 MB)
145 00:15:16.715399 progress 85 % (9 MB)
146 00:15:16.787219 progress 90 % (9 MB)
147 00:15:16.886005 progress 95 % (10 MB)
148 00:15:16.981790 progress 100 % (11 MB)
149 00:15:16.993278 11 MB downloaded in 1.66 s (6.68 MB/s)
150 00:15:16.993854 end: 1.5.1 http-download (duration 00:00:02) [common]
152 00:15:16.994752 end: 1.5 download-retry (duration 00:00:02) [common]
153 00:15:16.995061 start: 1.6 prepare-tftp-overlay (timeout 00:09:43) [common]
154 00:15:16.995364 start: 1.6.1 extract-nfsrootfs (timeout 00:09:43) [common]
155 00:15:33.389240 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/919150/extract-nfsrootfs-mv_frtrz
156 00:15:33.389859 end: 1.6.1 extract-nfsrootfs (duration 00:00:16) [common]
157 00:15:33.390158 start: 1.6.2 lava-overlay (timeout 00:09:26) [common]
158 00:15:33.390783 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/919150/lava-overlay-ey1nyg6s
159 00:15:33.391251 makedir: /var/lib/lava/dispatcher/tmp/919150/lava-overlay-ey1nyg6s/lava-919150/bin
160 00:15:33.391593 makedir: /var/lib/lava/dispatcher/tmp/919150/lava-overlay-ey1nyg6s/lava-919150/tests
161 00:15:33.391930 makedir: /var/lib/lava/dispatcher/tmp/919150/lava-overlay-ey1nyg6s/lava-919150/results
162 00:15:33.392344 Creating /var/lib/lava/dispatcher/tmp/919150/lava-overlay-ey1nyg6s/lava-919150/bin/lava-add-keys
163 00:15:33.393018 Creating /var/lib/lava/dispatcher/tmp/919150/lava-overlay-ey1nyg6s/lava-919150/bin/lava-add-sources
164 00:15:33.393846 Creating /var/lib/lava/dispatcher/tmp/919150/lava-overlay-ey1nyg6s/lava-919150/bin/lava-background-process-start
165 00:15:33.394508 Creating /var/lib/lava/dispatcher/tmp/919150/lava-overlay-ey1nyg6s/lava-919150/bin/lava-background-process-stop
166 00:15:33.395113 Creating /var/lib/lava/dispatcher/tmp/919150/lava-overlay-ey1nyg6s/lava-919150/bin/lava-common-functions
167 00:15:33.395686 Creating /var/lib/lava/dispatcher/tmp/919150/lava-overlay-ey1nyg6s/lava-919150/bin/lava-echo-ipv4
168 00:15:33.396412 Creating /var/lib/lava/dispatcher/tmp/919150/lava-overlay-ey1nyg6s/lava-919150/bin/lava-install-packages
169 00:15:33.396992 Creating /var/lib/lava/dispatcher/tmp/919150/lava-overlay-ey1nyg6s/lava-919150/bin/lava-installed-packages
170 00:15:33.397528 Creating /var/lib/lava/dispatcher/tmp/919150/lava-overlay-ey1nyg6s/lava-919150/bin/lava-os-build
171 00:15:33.398055 Creating /var/lib/lava/dispatcher/tmp/919150/lava-overlay-ey1nyg6s/lava-919150/bin/lava-probe-channel
172 00:15:33.398626 Creating /var/lib/lava/dispatcher/tmp/919150/lava-overlay-ey1nyg6s/lava-919150/bin/lava-probe-ip
173 00:15:33.399175 Creating /var/lib/lava/dispatcher/tmp/919150/lava-overlay-ey1nyg6s/lava-919150/bin/lava-target-ip
174 00:15:33.399714 Creating /var/lib/lava/dispatcher/tmp/919150/lava-overlay-ey1nyg6s/lava-919150/bin/lava-target-mac
175 00:15:33.400318 Creating /var/lib/lava/dispatcher/tmp/919150/lava-overlay-ey1nyg6s/lava-919150/bin/lava-target-storage
176 00:15:33.400929 Creating /var/lib/lava/dispatcher/tmp/919150/lava-overlay-ey1nyg6s/lava-919150/bin/lava-test-case
177 00:15:33.401504 Creating /var/lib/lava/dispatcher/tmp/919150/lava-overlay-ey1nyg6s/lava-919150/bin/lava-test-event
178 00:15:33.402055 Creating /var/lib/lava/dispatcher/tmp/919150/lava-overlay-ey1nyg6s/lava-919150/bin/lava-test-feedback
179 00:15:33.402616 Creating /var/lib/lava/dispatcher/tmp/919150/lava-overlay-ey1nyg6s/lava-919150/bin/lava-test-raise
180 00:15:33.403134 Creating /var/lib/lava/dispatcher/tmp/919150/lava-overlay-ey1nyg6s/lava-919150/bin/lava-test-reference
181 00:15:33.403684 Creating /var/lib/lava/dispatcher/tmp/919150/lava-overlay-ey1nyg6s/lava-919150/bin/lava-test-runner
182 00:15:33.404267 Creating /var/lib/lava/dispatcher/tmp/919150/lava-overlay-ey1nyg6s/lava-919150/bin/lava-test-set
183 00:15:33.404802 Creating /var/lib/lava/dispatcher/tmp/919150/lava-overlay-ey1nyg6s/lava-919150/bin/lava-test-shell
184 00:15:33.405350 Updating /var/lib/lava/dispatcher/tmp/919150/lava-overlay-ey1nyg6s/lava-919150/bin/lava-add-keys (debian)
185 00:15:33.405970 Updating /var/lib/lava/dispatcher/tmp/919150/lava-overlay-ey1nyg6s/lava-919150/bin/lava-add-sources (debian)
186 00:15:33.406594 Updating /var/lib/lava/dispatcher/tmp/919150/lava-overlay-ey1nyg6s/lava-919150/bin/lava-install-packages (debian)
187 00:15:33.407168 Updating /var/lib/lava/dispatcher/tmp/919150/lava-overlay-ey1nyg6s/lava-919150/bin/lava-installed-packages (debian)
188 00:15:33.407770 Updating /var/lib/lava/dispatcher/tmp/919150/lava-overlay-ey1nyg6s/lava-919150/bin/lava-os-build (debian)
189 00:15:33.408329 Creating /var/lib/lava/dispatcher/tmp/919150/lava-overlay-ey1nyg6s/lava-919150/environment
190 00:15:33.408756 LAVA metadata
191 00:15:33.409034 - LAVA_JOB_ID=919150
192 00:15:33.409254 - LAVA_DISPATCHER_IP=192.168.6.2
193 00:15:33.409675 start: 1.6.2.1 ssh-authorize (timeout 00:09:26) [common]
194 00:15:33.410764 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
195 00:15:33.411124 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:26) [common]
196 00:15:33.411337 skipped lava-vland-overlay
197 00:15:33.411580 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
198 00:15:33.411836 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:26) [common]
199 00:15:33.412099 skipped lava-multinode-overlay
200 00:15:33.412356 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
201 00:15:33.412611 start: 1.6.2.4 test-definition (timeout 00:09:26) [common]
202 00:15:33.412869 Loading test definitions
203 00:15:33.413154 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:26) [common]
204 00:15:33.413375 Using /lava-919150 at stage 0
205 00:15:33.414558 uuid=919150_1.6.2.4.1 testdef=None
206 00:15:33.414909 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
207 00:15:33.415183 start: 1.6.2.4.2 test-overlay (timeout 00:09:26) [common]
208 00:15:33.416959 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
210 00:15:33.417816 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:26) [common]
211 00:15:33.419972 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
213 00:15:33.420893 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:26) [common]
214 00:15:33.422994 runner path: /var/lib/lava/dispatcher/tmp/919150/lava-overlay-ey1nyg6s/lava-919150/0/tests/0_timesync-off test_uuid 919150_1.6.2.4.1
215 00:15:33.423701 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
217 00:15:33.424660 start: 1.6.2.4.5 git-repo-action (timeout 00:09:26) [common]
218 00:15:33.424949 Using /lava-919150 at stage 0
219 00:15:33.425344 Fetching tests from https://github.com/kernelci/test-definitions.git
220 00:15:33.425658 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/919150/lava-overlay-ey1nyg6s/lava-919150/0/tests/1_kselftest-alsa'
221 00:15:36.832388 Running '/usr/bin/git checkout kernelci.org
222 00:15:37.283089 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/919150/lava-overlay-ey1nyg6s/lava-919150/0/tests/1_kselftest-alsa/automated/linux/kselftest/kselftest.yaml
223 00:15:37.284588 uuid=919150_1.6.2.4.5 testdef=None
224 00:15:37.284948 end: 1.6.2.4.5 git-repo-action (duration 00:00:04) [common]
226 00:15:37.285716 start: 1.6.2.4.6 test-overlay (timeout 00:09:22) [common]
227 00:15:37.288680 end: 1.6.2.4.6 test-overlay (duration 00:00:00) [common]
229 00:15:37.289512 start: 1.6.2.4.7 test-install-overlay (timeout 00:09:22) [common]
230 00:15:37.294903 end: 1.6.2.4.7 test-install-overlay (duration 00:00:00) [common]
232 00:15:37.296795 start: 1.6.2.4.8 test-runscript-overlay (timeout 00:09:22) [common]
233 00:15:37.304608 runner path: /var/lib/lava/dispatcher/tmp/919150/lava-overlay-ey1nyg6s/lava-919150/0/tests/1_kselftest-alsa test_uuid 919150_1.6.2.4.5
234 00:15:37.305209 BOARD='meson-g12b-a311d-libretech-cc'
235 00:15:37.305656 BRANCH='next'
236 00:15:37.306091 SKIPFILE='/dev/null'
237 00:15:37.306523 SKIP_INSTALL='True'
238 00:15:37.306953 TESTPROG_URL='http://storage.kernelci.org/next/pending-fixes/v6.12-rc5-415-g78b16920c1e2/arm64/defconfig/gcc-12/kselftest.tar.xz'
239 00:15:37.307391 TST_CASENAME=''
240 00:15:37.307817 TST_CMDFILES='alsa'
241 00:15:37.309079 end: 1.6.2.4.8 test-runscript-overlay (duration 00:00:00) [common]
243 00:15:37.310803 Creating lava-test-runner.conf files
244 00:15:37.311241 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/919150/lava-overlay-ey1nyg6s/lava-919150/0 for stage 0
245 00:15:37.312036 - 0_timesync-off
246 00:15:37.312555 - 1_kselftest-alsa
247 00:15:37.313248 end: 1.6.2.4 test-definition (duration 00:00:04) [common]
248 00:15:37.313840 start: 1.6.2.5 compress-overlay (timeout 00:09:22) [common]
249 00:16:00.950351 end: 1.6.2.5 compress-overlay (duration 00:00:24) [common]
250 00:16:00.950809 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:08:59) [common]
251 00:16:00.951105 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
252 00:16:00.951416 end: 1.6.2 lava-overlay (duration 00:00:28) [common]
253 00:16:00.951709 start: 1.6.3 extract-overlay-ramdisk (timeout 00:08:59) [common]
254 00:16:01.598026 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:01) [common]
255 00:16:01.598484 start: 1.6.4 extract-modules (timeout 00:08:58) [common]
256 00:16:01.598859 extracting modules file /var/lib/lava/dispatcher/tmp/919150/tftp-deploy-34_gl3d2/modules/modules.tar to /var/lib/lava/dispatcher/tmp/919150/extract-nfsrootfs-mv_frtrz
257 00:16:03.040389 extracting modules file /var/lib/lava/dispatcher/tmp/919150/tftp-deploy-34_gl3d2/modules/modules.tar to /var/lib/lava/dispatcher/tmp/919150/extract-overlay-ramdisk-t5vki0v5/ramdisk
258 00:16:04.512456 end: 1.6.4 extract-modules (duration 00:00:03) [common]
259 00:16:04.512960 start: 1.6.5 apply-overlay-tftp (timeout 00:08:55) [common]
260 00:16:04.513259 [common] Applying overlay to NFS
261 00:16:04.513493 [common] Applying overlay /var/lib/lava/dispatcher/tmp/919150/compress-overlay-ir8mp4zb/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/919150/extract-nfsrootfs-mv_frtrz
262 00:16:07.277706 end: 1.6.5 apply-overlay-tftp (duration 00:00:03) [common]
263 00:16:07.278184 start: 1.6.6 prepare-kernel (timeout 00:08:52) [common]
264 00:16:07.278489 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:08:52) [common]
265 00:16:07.278751 Converting downloaded kernel to a uImage
266 00:16:07.279079 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/919150/tftp-deploy-34_gl3d2/kernel/Image /var/lib/lava/dispatcher/tmp/919150/tftp-deploy-34_gl3d2/kernel/uImage
267 00:16:07.744563 output: Image Name:
268 00:16:07.744989 output: Created: Fri Nov 1 00:16:07 2024
269 00:16:07.745200 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
270 00:16:07.745405 output: Data Size: 45715968 Bytes = 44644.50 KiB = 43.60 MiB
271 00:16:07.745605 output: Load Address: 01080000
272 00:16:07.745803 output: Entry Point: 01080000
273 00:16:07.746001 output:
274 00:16:07.746335 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
275 00:16:07.746601 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
276 00:16:07.746871 start: 1.6.7 configure-preseed-file (timeout 00:08:52) [common]
277 00:16:07.747126 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
278 00:16:07.747381 start: 1.6.8 compress-ramdisk (timeout 00:08:52) [common]
279 00:16:07.747644 Building ramdisk /var/lib/lava/dispatcher/tmp/919150/extract-overlay-ramdisk-t5vki0v5/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/919150/extract-overlay-ramdisk-t5vki0v5/ramdisk
280 00:16:09.958146 >> 166826 blocks
281 00:16:18.438442 Adding RAMdisk u-boot header.
282 00:16:18.439192 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/919150/extract-overlay-ramdisk-t5vki0v5/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/919150/extract-overlay-ramdisk-t5vki0v5/ramdisk.cpio.gz.uboot
283 00:16:18.745569 output: Image Name:
284 00:16:18.745993 output: Created: Fri Nov 1 00:16:18 2024
285 00:16:18.746202 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
286 00:16:18.746407 output: Data Size: 23436956 Bytes = 22887.65 KiB = 22.35 MiB
287 00:16:18.746610 output: Load Address: 00000000
288 00:16:18.746807 output: Entry Point: 00000000
289 00:16:18.747006 output:
290 00:16:18.747584 rename /var/lib/lava/dispatcher/tmp/919150/extract-overlay-ramdisk-t5vki0v5/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/919150/tftp-deploy-34_gl3d2/ramdisk/ramdisk.cpio.gz.uboot
291 00:16:18.748030 end: 1.6.8 compress-ramdisk (duration 00:00:11) [common]
292 00:16:18.748596 end: 1.6 prepare-tftp-overlay (duration 00:01:02) [common]
293 00:16:18.749122 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:41) [common]
294 00:16:18.749571 No LXC device requested
295 00:16:18.750065 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
296 00:16:18.750571 start: 1.8 deploy-device-env (timeout 00:08:41) [common]
297 00:16:18.751060 end: 1.8 deploy-device-env (duration 00:00:00) [common]
298 00:16:18.751472 Checking files for TFTP limit of 4294967296 bytes.
299 00:16:18.754194 end: 1 tftp-deploy (duration 00:01:19) [common]
300 00:16:18.754786 start: 2 uboot-action (timeout 00:05:00) [common]
301 00:16:18.755307 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
302 00:16:18.755801 end: 2.1 uboot-from-media (duration 00:00:00) [common]
303 00:16:18.756336 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
304 00:16:18.756862 Using kernel file from prepare-kernel: 919150/tftp-deploy-34_gl3d2/kernel/uImage
305 00:16:18.757485 substitutions:
306 00:16:18.757890 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
307 00:16:18.758291 - {DTB_ADDR}: 0x01070000
308 00:16:18.758693 - {DTB}: 919150/tftp-deploy-34_gl3d2/dtb/meson-g12b-a311d-libretech-cc.dtb
309 00:16:18.759093 - {INITRD}: 919150/tftp-deploy-34_gl3d2/ramdisk/ramdisk.cpio.gz.uboot
310 00:16:18.759487 - {KERNEL_ADDR}: 0x01080000
311 00:16:18.759881 - {KERNEL}: 919150/tftp-deploy-34_gl3d2/kernel/uImage
312 00:16:18.760306 - {LAVA_MAC}: None
313 00:16:18.760738 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/919150/extract-nfsrootfs-mv_frtrz
314 00:16:18.761136 - {NFS_SERVER_IP}: 192.168.6.2
315 00:16:18.761526 - {PRESEED_CONFIG}: None
316 00:16:18.761916 - {PRESEED_LOCAL}: None
317 00:16:18.762304 - {RAMDISK_ADDR}: 0x08000000
318 00:16:18.762690 - {RAMDISK}: 919150/tftp-deploy-34_gl3d2/ramdisk/ramdisk.cpio.gz.uboot
319 00:16:18.763076 - {ROOT_PART}: None
320 00:16:18.763462 - {ROOT}: None
321 00:16:18.763845 - {SERVER_IP}: 192.168.6.2
322 00:16:18.764255 - {TEE_ADDR}: 0x83000000
323 00:16:18.764639 - {TEE}: None
324 00:16:18.765023 Parsed boot commands:
325 00:16:18.765399 - setenv autoload no
326 00:16:18.765782 - setenv initrd_high 0xffffffff
327 00:16:18.766162 - setenv fdt_high 0xffffffff
328 00:16:18.766543 - dhcp
329 00:16:18.766921 - setenv serverip 192.168.6.2
330 00:16:18.767308 - tftpboot 0x01080000 919150/tftp-deploy-34_gl3d2/kernel/uImage
331 00:16:18.767694 - tftpboot 0x08000000 919150/tftp-deploy-34_gl3d2/ramdisk/ramdisk.cpio.gz.uboot
332 00:16:18.768108 - tftpboot 0x01070000 919150/tftp-deploy-34_gl3d2/dtb/meson-g12b-a311d-libretech-cc.dtb
333 00:16:18.768499 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/919150/extract-nfsrootfs-mv_frtrz,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
334 00:16:18.768898 - bootm 0x01080000 0x08000000 0x01070000
335 00:16:18.769411 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
337 00:16:18.770884 start: 2.3 connect-device (timeout 00:05:00) [common]
338 00:16:18.771298 [common] connect-device Connecting to device using 'telnet conserv1 3007'
339 00:16:18.786399 Setting prompt string to ['lava-test: # ']
340 00:16:18.787975 end: 2.3 connect-device (duration 00:00:00) [common]
341 00:16:18.788658 start: 2.4 uboot-commands (timeout 00:05:00) [common]
342 00:16:18.789221 start: 2.4.1 reset-device (timeout 00:05:00) [common]
343 00:16:18.789743 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
344 00:16:18.790863 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
345 00:16:18.828969 >> OK - accepted request
346 00:16:18.831523 Returned 0 in 0 seconds
347 00:16:18.932455 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
349 00:16:18.934103 end: 2.4.1 reset-device (duration 00:00:00) [common]
350 00:16:18.934636 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
351 00:16:18.935121 Setting prompt string to ['Hit any key to stop autoboot']
352 00:16:18.935567 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
353 00:16:18.937144 Trying 192.168.56.21...
354 00:16:18.937631 Connected to conserv1.
355 00:16:18.938032 Escape character is '^]'.
356 00:16:18.938449
357 00:16:18.938860 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
358 00:16:18.939282
359 00:16:29.903552 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
360 00:16:29.904202 bl2_stage_init 0x01
361 00:16:29.904628 bl2_stage_init 0x81
362 00:16:29.908994 hw id: 0x0000 - pwm id 0x01
363 00:16:29.909476 bl2_stage_init 0xc1
364 00:16:29.909911 bl2_stage_init 0x02
365 00:16:29.910336
366 00:16:29.914659 L0:00000000
367 00:16:29.915133 L1:20000703
368 00:16:29.915552 L2:00008067
369 00:16:29.915959 L3:14000000
370 00:16:29.917529 B2:00402000
371 00:16:29.917975 B1:e0f83180
372 00:16:29.918392
373 00:16:29.918787 TE: 58159
374 00:16:29.919180
375 00:16:29.928752 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
376 00:16:29.929192
377 00:16:29.929587 Board ID = 1
378 00:16:29.929975 Set A53 clk to 24M
379 00:16:29.930358 Set A73 clk to 24M
380 00:16:29.934458 Set clk81 to 24M
381 00:16:29.934927 A53 clk: 1200 MHz
382 00:16:29.935318 A73 clk: 1200 MHz
383 00:16:29.937920 CLK81: 166.6M
384 00:16:29.938346 smccc: 00012ab5
385 00:16:29.943554 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
386 00:16:29.949205 board id: 1
387 00:16:29.953687 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
388 00:16:29.964828 fw parse done
389 00:16:29.969903 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
390 00:16:30.013161 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
391 00:16:30.024180 PIEI prepare done
392 00:16:30.024618 fastboot data load
393 00:16:30.025010 fastboot data verify
394 00:16:30.029676 verify result: 266
395 00:16:30.035261 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
396 00:16:30.035692 LPDDR4 probe
397 00:16:30.036124 ddr clk to 1584MHz
398 00:16:30.042945 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
399 00:16:30.080335
400 00:16:30.080886 dmc_version 0001
401 00:16:30.087194 Check phy result
402 00:16:30.093115 INFO : End of CA training
403 00:16:30.093553 INFO : End of initialization
404 00:16:30.098633 INFO : Training has run successfully!
405 00:16:30.099063 Check phy result
406 00:16:30.104253 INFO : End of initialization
407 00:16:30.104682 INFO : End of read enable training
408 00:16:30.109855 INFO : End of fine write leveling
409 00:16:30.115477 INFO : End of Write leveling coarse delay
410 00:16:30.115958 INFO : Training has run successfully!
411 00:16:30.116395 Check phy result
412 00:16:30.121131 INFO : End of initialization
413 00:16:30.121564 INFO : End of read dq deskew training
414 00:16:30.126639 INFO : End of MPR read delay center optimization
415 00:16:30.132321 INFO : End of write delay center optimization
416 00:16:30.137873 INFO : End of read delay center optimization
417 00:16:30.138331 INFO : End of max read latency training
418 00:16:30.143448 INFO : Training has run successfully!
419 00:16:30.143875 1D training succeed
420 00:16:30.152647 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
421 00:16:30.200323 Check phy result
422 00:16:30.200890 INFO : End of initialization
423 00:16:30.222799 INFO : End of 2D read delay Voltage center optimization
424 00:16:30.242833 INFO : End of 2D read delay Voltage center optimization
425 00:16:30.294813 INFO : End of 2D write delay Voltage center optimization
426 00:16:30.344102 INFO : End of 2D write delay Voltage center optimization
427 00:16:30.349506 INFO : Training has run successfully!
428 00:16:30.349948
429 00:16:30.350351 channel==0
430 00:16:30.355163 RxClkDly_Margin_A0==88 ps 9
431 00:16:30.355599 TxDqDly_Margin_A0==98 ps 10
432 00:16:30.360706 RxClkDly_Margin_A1==88 ps 9
433 00:16:30.361137 TxDqDly_Margin_A1==98 ps 10
434 00:16:30.361534 TrainedVREFDQ_A0==74
435 00:16:30.366321 TrainedVREFDQ_A1==74
436 00:16:30.366800 VrefDac_Margin_A0==24
437 00:16:30.367200 DeviceVref_Margin_A0==40
438 00:16:30.371929 VrefDac_Margin_A1==25
439 00:16:30.372433 DeviceVref_Margin_A1==40
440 00:16:30.372831
441 00:16:30.373227
442 00:16:30.377520 channel==1
443 00:16:30.377951 RxClkDly_Margin_A0==98 ps 10
444 00:16:30.378346 TxDqDly_Margin_A0==88 ps 9
445 00:16:30.383162 RxClkDly_Margin_A1==88 ps 9
446 00:16:30.383599 TxDqDly_Margin_A1==88 ps 9
447 00:16:30.388736 TrainedVREFDQ_A0==76
448 00:16:30.389164 TrainedVREFDQ_A1==77
449 00:16:30.389560 VrefDac_Margin_A0==22
450 00:16:30.394292 DeviceVref_Margin_A0==38
451 00:16:30.394717 VrefDac_Margin_A1==24
452 00:16:30.399915 DeviceVref_Margin_A1==37
453 00:16:30.400372
454 00:16:30.400773 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
455 00:16:30.401167
456 00:16:30.433553 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000018 00000018 00000016 00000017 00000015 00000018 00000019 00000018 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
457 00:16:30.434122 2D training succeed
458 00:16:30.439191 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
459 00:16:30.444729 auto size-- 65535DDR cs0 size: 2048MB
460 00:16:30.445201 DDR cs1 size: 2048MB
461 00:16:30.450558 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
462 00:16:30.451379 cs0 DataBus test pass
463 00:16:30.456004 cs1 DataBus test pass
464 00:16:30.456761 cs0 AddrBus test pass
465 00:16:30.457483 cs1 AddrBus test pass
466 00:16:30.458178
467 00:16:30.461583 100bdlr_step_size ps== 420
468 00:16:30.462337 result report
469 00:16:30.467164 boot times 0Enable ddr reg access
470 00:16:30.472447 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
471 00:16:30.485893 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
472 00:16:31.057949 0.0;M3 CHK:0;cm4_sp_mode 0
473 00:16:31.058699 MVN_1=0x00000000
474 00:16:31.063531 MVN_2=0x00000000
475 00:16:31.069246 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
476 00:16:31.069759 OPS=0x10
477 00:16:31.070214 ring efuse init
478 00:16:31.070658 chipver efuse init
479 00:16:31.074754 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
480 00:16:31.080424 [0.018960 Inits done]
481 00:16:31.081013 secure task start!
482 00:16:31.081462 high task start!
483 00:16:31.085026 low task start!
484 00:16:31.085606 run into bl31
485 00:16:31.091628 NOTICE: BL31: v1.3(release):4fc40b1
486 00:16:31.099421 NOTICE: BL31: Built : 15:58:17, May 22 2019
487 00:16:31.100061 NOTICE: BL31: G12A normal boot!
488 00:16:31.124791 NOTICE: BL31: BL33 decompress pass
489 00:16:31.130438 ERROR: Error initializing runtime service opteed_fast
490 00:16:32.363320
491 00:16:32.363965
492 00:16:32.371692 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
493 00:16:32.372231
494 00:16:32.372687 Model: Libre Computer AML-A311D-CC Alta
495 00:16:32.580157 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
496 00:16:32.603582 DRAM: 2 GiB (effective 3.8 GiB)
497 00:16:32.746552 Core: 408 devices, 31 uclasses, devicetree: separate
498 00:16:32.752749 WDT: Not starting watchdog@f0d0
499 00:16:32.784727 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
500 00:16:32.797169 Loading Environment from FAT... Card did not respond to voltage select! : -110
501 00:16:32.802042 ** Bad device specification mmc 0 **
502 00:16:32.812497 Card did not respond to voltage select! : -110
503 00:16:32.820051 ** Bad device specification mmc 0 **
504 00:16:32.820546 Couldn't find partition mmc 0
505 00:16:32.828369 Card did not respond to voltage select! : -110
506 00:16:32.833838 ** Bad device specification mmc 0 **
507 00:16:32.834288 Couldn't find partition mmc 0
508 00:16:32.838922 Error: could not access storage.
509 00:16:34.103849 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
510 00:16:34.104539 bl2_stage_init 0x01
511 00:16:34.104960 bl2_stage_init 0x81
512 00:16:34.109397 hw id: 0x0000 - pwm id 0x01
513 00:16:34.109871 bl2_stage_init 0xc1
514 00:16:34.110280 bl2_stage_init 0x02
515 00:16:34.110679
516 00:16:34.115047 L0:00000000
517 00:16:34.115683 L1:20000703
518 00:16:34.116175 L2:00008067
519 00:16:34.116613 L3:14000000
520 00:16:34.120604 B2:00402000
521 00:16:34.121087 B1:e0f83180
522 00:16:34.121487
523 00:16:34.121886 TE: 58124
524 00:16:34.122281
525 00:16:34.126167 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
526 00:16:34.126648
527 00:16:34.127055 Board ID = 1
528 00:16:34.131783 Set A53 clk to 24M
529 00:16:34.132275 Set A73 clk to 24M
530 00:16:34.132681 Set clk81 to 24M
531 00:16:34.137320 A53 clk: 1200 MHz
532 00:16:34.137771 A73 clk: 1200 MHz
533 00:16:34.138171 CLK81: 166.6M
534 00:16:34.138567 smccc: 00012a92
535 00:16:34.142941 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
536 00:16:34.148588 board id: 1
537 00:16:34.154503 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
538 00:16:34.165182 fw parse done
539 00:16:34.171138 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
540 00:16:34.213785 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
541 00:16:34.224633 PIEI prepare done
542 00:16:34.225149 fastboot data load
543 00:16:34.225556 fastboot data verify
544 00:16:34.230300 verify result: 266
545 00:16:34.235862 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
546 00:16:34.236359 LPDDR4 probe
547 00:16:34.236758 ddr clk to 1584MHz
548 00:16:34.243899 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
549 00:16:34.280394
550 00:16:34.280930 dmc_version 0001
551 00:16:34.287781 Check phy result
552 00:16:34.293720 INFO : End of CA training
553 00:16:34.294236 INFO : End of initialization
554 00:16:34.299268 INFO : Training has run successfully!
555 00:16:34.299761 Check phy result
556 00:16:34.304900 INFO : End of initialization
557 00:16:34.305381 INFO : End of read enable training
558 00:16:34.310429 INFO : End of fine write leveling
559 00:16:34.316086 INFO : End of Write leveling coarse delay
560 00:16:34.316553 INFO : Training has run successfully!
561 00:16:34.316972 Check phy result
562 00:16:34.321706 INFO : End of initialization
563 00:16:34.322199 INFO : End of read dq deskew training
564 00:16:34.327281 INFO : End of MPR read delay center optimization
565 00:16:34.332913 INFO : End of write delay center optimization
566 00:16:34.338479 INFO : End of read delay center optimization
567 00:16:34.338938 INFO : End of max read latency training
568 00:16:34.344115 INFO : Training has run successfully!
569 00:16:34.344590 1D training succeed
570 00:16:34.353201 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
571 00:16:34.400424 Check phy result
572 00:16:34.400945 INFO : End of initialization
573 00:16:34.423771 INFO : End of 2D read delay Voltage center optimization
574 00:16:34.441937 INFO : End of 2D read delay Voltage center optimization
575 00:16:34.494495 INFO : End of 2D write delay Voltage center optimization
576 00:16:34.543738 INFO : End of 2D write delay Voltage center optimization
577 00:16:34.549280 INFO : Training has run successfully!
578 00:16:34.549761
579 00:16:34.550166 channel==0
580 00:16:34.554846 RxClkDly_Margin_A0==88 ps 9
581 00:16:34.555301 TxDqDly_Margin_A0==98 ps 10
582 00:16:34.560476 RxClkDly_Margin_A1==88 ps 9
583 00:16:34.560934 TxDqDly_Margin_A1==98 ps 10
584 00:16:34.561338 TrainedVREFDQ_A0==74
585 00:16:34.566104 TrainedVREFDQ_A1==75
586 00:16:34.566602 VrefDac_Margin_A0==25
587 00:16:34.567006 DeviceVref_Margin_A0==40
588 00:16:34.571667 VrefDac_Margin_A1==23
589 00:16:34.572172 DeviceVref_Margin_A1==39
590 00:16:34.572581
591 00:16:34.572984
592 00:16:34.577277 channel==1
593 00:16:34.577758 RxClkDly_Margin_A0==98 ps 10
594 00:16:34.578161 TxDqDly_Margin_A0==98 ps 10
595 00:16:34.582874 RxClkDly_Margin_A1==98 ps 10
596 00:16:34.583334 TxDqDly_Margin_A1==88 ps 9
597 00:16:34.588463 TrainedVREFDQ_A0==77
598 00:16:34.588924 TrainedVREFDQ_A1==77
599 00:16:34.589326 VrefDac_Margin_A0==22
600 00:16:34.594155 DeviceVref_Margin_A0==37
601 00:16:34.594614 VrefDac_Margin_A1==24
602 00:16:34.599699 DeviceVref_Margin_A1==37
603 00:16:34.600223
604 00:16:34.600635 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
605 00:16:34.605294
606 00:16:34.633261 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000018 00000018 00000019 00000018 00000019 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000017 00000019 00000019 00000019 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
607 00:16:34.633801 2D training succeed
608 00:16:34.638861 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
609 00:16:34.644458 auto size-- 65535DDR cs0 size: 2048MB
610 00:16:34.644916 DDR cs1 size: 2048MB
611 00:16:34.650038 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
612 00:16:34.650491 cs0 DataBus test pass
613 00:16:34.655637 cs1 DataBus test pass
614 00:16:34.656136 cs0 AddrBus test pass
615 00:16:34.656542 cs1 AddrBus test pass
616 00:16:34.656932
617 00:16:34.661267 100bdlr_step_size ps== 420
618 00:16:34.661735 result report
619 00:16:34.666867 boot times 0Enable ddr reg access
620 00:16:34.672272 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
621 00:16:34.685828 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
622 00:16:35.257828 0.0;M3 CHK:0;cm4_sp_mode 0
623 00:16:35.258444 MVN_1=0x00000000
624 00:16:35.263347 MVN_2=0x00000000
625 00:16:35.269048 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
626 00:16:35.269542 OPS=0x10
627 00:16:35.269989 ring efuse init
628 00:16:35.270399 chipver efuse init
629 00:16:35.277322 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
630 00:16:35.277809 [0.018960 Inits done]
631 00:16:35.278210 secure task start!
632 00:16:35.284807 high task start!
633 00:16:35.285257 low task start!
634 00:16:35.285656 run into bl31
635 00:16:35.291429 NOTICE: BL31: v1.3(release):4fc40b1
636 00:16:35.299402 NOTICE: BL31: Built : 15:58:17, May 22 2019
637 00:16:35.299847 NOTICE: BL31: G12A normal boot!
638 00:16:35.324756 NOTICE: BL31: BL33 decompress pass
639 00:16:35.330362 ERROR: Error initializing runtime service opteed_fast
640 00:16:36.563438
641 00:16:36.564068
642 00:16:36.571889 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
643 00:16:36.572395
644 00:16:36.572813 Model: Libre Computer AML-A311D-CC Alta
645 00:16:36.780202 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
646 00:16:36.803653 DRAM: 2 GiB (effective 3.8 GiB)
647 00:16:36.946559 Core: 408 devices, 31 uclasses, devicetree: separate
648 00:16:36.952434 WDT: Not starting watchdog@f0d0
649 00:16:36.984575 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
650 00:16:36.997138 Loading Environment from FAT... Card did not respond to voltage select! : -110
651 00:16:37.002170 ** Bad device specification mmc 0 **
652 00:16:37.012439 Card did not respond to voltage select! : -110
653 00:16:37.020108 ** Bad device specification mmc 0 **
654 00:16:37.020560 Couldn't find partition mmc 0
655 00:16:37.028417 Card did not respond to voltage select! : -110
656 00:16:37.033876 ** Bad device specification mmc 0 **
657 00:16:37.034338 Couldn't find partition mmc 0
658 00:16:37.038936 Error: could not access storage.
659 00:16:37.382520 Net: eth0: ethernet@ff3f0000
660 00:16:37.383118 starting USB...
661 00:16:37.634409 Bus usb@ff500000: Register 3000140 NbrPorts 3
662 00:16:37.634997 Starting the controller
663 00:16:37.641393 USB XHCI 1.10
664 00:16:39.354213 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
665 00:16:39.354657 bl2_stage_init 0x01
666 00:16:39.354897 bl2_stage_init 0x81
667 00:16:39.359721 hw id: 0x0000 - pwm id 0x01
668 00:16:39.360063 bl2_stage_init 0xc1
669 00:16:39.360309 bl2_stage_init 0x02
670 00:16:39.360533
671 00:16:39.365282 L0:00000000
672 00:16:39.365573 L1:20000703
673 00:16:39.365808 L2:00008067
674 00:16:39.366032 L3:14000000
675 00:16:39.370891 B2:00402000
676 00:16:39.371194 B1:e0f83180
677 00:16:39.371424
678 00:16:39.371651 TE: 58124
679 00:16:39.371874
680 00:16:39.376704 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
681 00:16:39.377037
682 00:16:39.377272 Board ID = 1
683 00:16:39.382168 Set A53 clk to 24M
684 00:16:39.382474 Set A73 clk to 24M
685 00:16:39.382706 Set clk81 to 24M
686 00:16:39.387692 A53 clk: 1200 MHz
687 00:16:39.388026 A73 clk: 1200 MHz
688 00:16:39.388265 CLK81: 166.6M
689 00:16:39.388508 smccc: 00012a92
690 00:16:39.393306 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
691 00:16:39.398824 board id: 1
692 00:16:39.404672 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
693 00:16:39.415370 fw parse done
694 00:16:39.420373 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
695 00:16:39.464027 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
696 00:16:39.474877 PIEI prepare done
697 00:16:39.475243 fastboot data load
698 00:16:39.475487 fastboot data verify
699 00:16:39.480627 verify result: 266
700 00:16:39.486120 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
701 00:16:39.486405 LPDDR4 probe
702 00:16:39.486618 ddr clk to 1584MHz
703 00:16:39.494071 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
704 00:16:39.531669
705 00:16:39.532307 dmc_version 0001
706 00:16:39.538027 Check phy result
707 00:16:39.544028 INFO : End of CA training
708 00:16:39.544645 INFO : End of initialization
709 00:16:39.549581 INFO : Training has run successfully!
710 00:16:39.549914 Check phy result
711 00:16:39.555227 INFO : End of initialization
712 00:16:39.555512 INFO : End of read enable training
713 00:16:39.560729 INFO : End of fine write leveling
714 00:16:39.566251 INFO : End of Write leveling coarse delay
715 00:16:39.566513 INFO : Training has run successfully!
716 00:16:39.566726 Check phy result
717 00:16:39.571814 INFO : End of initialization
718 00:16:39.572349 INFO : End of read dq deskew training
719 00:16:39.577750 INFO : End of MPR read delay center optimization
720 00:16:39.583175 INFO : End of write delay center optimization
721 00:16:39.588906 INFO : End of read delay center optimization
722 00:16:39.589445 INFO : End of max read latency training
723 00:16:39.594431 INFO : Training has run successfully!
724 00:16:39.594992 1D training succeed
725 00:16:39.603481 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
726 00:16:39.651220 Check phy result
727 00:16:39.651854 INFO : End of initialization
728 00:16:39.673066 INFO : End of 2D read delay Voltage center optimization
729 00:16:39.693354 INFO : End of 2D read delay Voltage center optimization
730 00:16:39.745212 INFO : End of 2D write delay Voltage center optimization
731 00:16:39.794637 INFO : End of 2D write delay Voltage center optimization
732 00:16:39.800099 INFO : Training has run successfully!
733 00:16:39.800467
734 00:16:39.800714 channel==0
735 00:16:39.805710 RxClkDly_Margin_A0==88 ps 9
736 00:16:39.806076 TxDqDly_Margin_A0==98 ps 10
737 00:16:39.811393 RxClkDly_Margin_A1==88 ps 9
738 00:16:39.811777 TxDqDly_Margin_A1==98 ps 10
739 00:16:39.812043 TrainedVREFDQ_A0==74
740 00:16:39.816897 TrainedVREFDQ_A1==74
741 00:16:39.817303 VrefDac_Margin_A0==25
742 00:16:39.817561 DeviceVref_Margin_A0==40
743 00:16:39.822568 VrefDac_Margin_A1==26
744 00:16:39.822946 DeviceVref_Margin_A1==40
745 00:16:39.823198
746 00:16:39.823432
747 00:16:39.828150 channel==1
748 00:16:39.828474 RxClkDly_Margin_A0==98 ps 10
749 00:16:39.828714 TxDqDly_Margin_A0==98 ps 10
750 00:16:39.833743 RxClkDly_Margin_A1==88 ps 9
751 00:16:39.834142 TxDqDly_Margin_A1==88 ps 9
752 00:16:39.839229 TrainedVREFDQ_A0==77
753 00:16:39.839621 TrainedVREFDQ_A1==77
754 00:16:39.839862 VrefDac_Margin_A0==22
755 00:16:39.844872 DeviceVref_Margin_A0==37
756 00:16:39.845263 VrefDac_Margin_A1==24
757 00:16:39.850515 DeviceVref_Margin_A1==37
758 00:16:39.850894
759 00:16:39.851137 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
760 00:16:39.851371
761 00:16:39.884053 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000018 00000019 00000018 00000019 00000018 0000001a 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
762 00:16:39.884723 2D training succeed
763 00:16:39.889699 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
764 00:16:39.895192 auto size-- 65535DDR cs0 size: 2048MB
765 00:16:39.895705 DDR cs1 size: 2048MB
766 00:16:39.900822 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
767 00:16:39.901315 cs0 DataBus test pass
768 00:16:39.906478 cs1 DataBus test pass
769 00:16:39.907046 cs0 AddrBus test pass
770 00:16:39.907521 cs1 AddrBus test pass
771 00:16:39.908233
772 00:16:39.912106 100bdlr_step_size ps== 420
773 00:16:39.912676 result report
774 00:16:39.917684 boot times 0Enable ddr reg access
775 00:16:39.923020 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
776 00:16:39.936549 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
777 00:16:40.510103 0.0;M3 CHK:0;cm4_sp_mode 0
778 00:16:40.510516 MVN_1=0x00000000
779 00:16:40.515574 MVN_2=0x00000000
780 00:16:40.521282 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
781 00:16:40.521657 OPS=0x10
782 00:16:40.521890 ring efuse init
783 00:16:40.522117 chipver efuse init
784 00:16:40.526927 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
785 00:16:40.532661 [0.018961 Inits done]
786 00:16:40.533199 secure task start!
787 00:16:40.533641 high task start!
788 00:16:40.537125 low task start!
789 00:16:40.537604 run into bl31
790 00:16:40.543711 NOTICE: BL31: v1.3(release):4fc40b1
791 00:16:40.551512 NOTICE: BL31: Built : 15:58:17, May 22 2019
792 00:16:40.552049 NOTICE: BL31: G12A normal boot!
793 00:16:40.576902 NOTICE: BL31: BL33 decompress pass
794 00:16:40.582189 ERROR: Error initializing runtime service opteed_fast
795 00:16:41.815423
796 00:16:41.816130
797 00:16:41.822936 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
798 00:16:41.823515
799 00:16:41.824045 Model: Libre Computer AML-A311D-CC Alta
800 00:16:42.032237 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
801 00:16:42.055578 DRAM: 2 GiB (effective 3.8 GiB)
802 00:16:42.198605 Core: 408 devices, 31 uclasses, devicetree: separate
803 00:16:42.204450 WDT: Not starting watchdog@f0d0
804 00:16:42.236735 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
805 00:16:42.249196 Loading Environment from FAT... Card did not respond to voltage select! : -110
806 00:16:42.254163 ** Bad device specification mmc 0 **
807 00:16:42.264458 Card did not respond to voltage select! : -110
808 00:16:42.272184 ** Bad device specification mmc 0 **
809 00:16:42.272757 Couldn't find partition mmc 0
810 00:16:42.280462 Card did not respond to voltage select! : -110
811 00:16:42.285962 ** Bad device specification mmc 0 **
812 00:16:42.286468 Couldn't find partition mmc 0
813 00:16:42.291067 Error: could not access storage.
814 00:16:42.634595 Net: eth0: ethernet@ff3f0000
815 00:16:42.635219 starting USB...
816 00:16:42.886672 Bus usb@ff500000: Register 3000140 NbrPorts 3
817 00:16:42.887363 Starting the controller
818 00:16:42.893345 USB XHCI 1.10
819 00:16:45.054387 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.�!,K��х��}���с0x01
820 00:16:45.055078 bl2_stage_init 0x81
821 00:16:45.059796 hw id: 0x0000 - pwm id 0x01
822 00:16:45.060359 bl2_stage_init 0xc1
823 00:16:45.060826 bl2_stage_init 0x02
824 00:16:45.061285
825 00:16:45.065553 L0:00000000
826 00:16:45.066054 L1:20000703
827 00:16:45.066506 L2:00008067
828 00:16:45.066951 L3:14000000
829 00:16:45.067398 B2:00402000
830 00:16:45.068516 B1:e0f83180
831 00:16:45.069041
832 00:16:45.069546 TE: 58150
833 00:16:45.070031
834 00:16:45.079581 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
835 00:16:45.080185
836 00:16:45.080654 Board ID = 1
837 00:16:45.081101 Set A53 clk to 24M
838 00:16:45.081542 Set A73 clk to 24M
839 00:16:45.084988 Set clk81 to 24M
840 00:16:45.085483 A53 clk: 1200 MHz
841 00:16:45.085935 A73 clk: 1200 MHz
842 00:16:45.090567 CLK81: 166.6M
843 00:16:45.091080 smccc: 00012aab
844 00:16:45.096279 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
845 00:16:45.096840 board id: 1
846 00:16:45.103685 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
847 00:16:45.115376 fw parse done
848 00:16:45.120705 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
849 00:16:45.163729 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
850 00:16:45.174775 PIEI prepare done
851 00:16:45.175295 fastboot data load
852 00:16:45.175755 fastboot data verify
853 00:16:45.180474 verify result: 266
854 00:16:45.186000 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
855 00:16:45.186495 LPDDR4 probe
856 00:16:45.186948 ddr clk to 1584MHz
857 00:16:45.193112 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
858 00:16:45.230729
859 00:16:45.231294 dmc_version 0001
860 00:16:45.237791 Check phy result
861 00:16:45.243748 INFO : End of CA training
862 00:16:45.244272 INFO : End of initialization
863 00:16:45.249383 INFO : Training has run successfully!
864 00:16:45.249931 Check phy result
865 00:16:45.255030 INFO : End of initialization
866 00:16:45.255528 INFO : End of read enable training
867 00:16:45.260546 INFO : End of fine write leveling
868 00:16:45.266173 INFO : End of Write leveling coarse delay
869 00:16:45.266657 INFO : Training has run successfully!
870 00:16:45.267107 Check phy result
871 00:16:45.271804 INFO : End of initialization
872 00:16:45.272402 INFO : End of read dq deskew training
873 00:16:45.277488 INFO : End of MPR read delay center optimization
874 00:16:45.282962 INFO : End of write delay center optimization
875 00:16:45.288673 INFO : End of read delay center optimization
876 00:16:45.289233 INFO : End of max read latency training
877 00:16:45.294253 INFO : Training has run successfully!
878 00:16:45.294860 1D training succeed
879 00:16:45.302937 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
880 00:16:45.350563 Check phy result
881 00:16:45.351227 INFO : End of initialization
882 00:16:45.372275 INFO : End of 2D read delay Voltage center optimization
883 00:16:45.392727 INFO : End of 2D read delay Voltage center optimization
884 00:16:45.445110 INFO : End of 2D write delay Voltage center optimization
885 00:16:45.494518 INFO : End of 2D write delay Voltage center optimization
886 00:16:45.500063 INFO : Training has run successfully!
887 00:16:45.500624
888 00:16:45.501102 channel==0
889 00:16:45.505629 RxClkDly_Margin_A0==88 ps 9
890 00:16:45.506177 TxDqDly_Margin_A0==98 ps 10
891 00:16:45.511219 RxClkDly_Margin_A1==88 ps 9
892 00:16:45.511767 TxDqDly_Margin_A1==98 ps 10
893 00:16:45.512293 TrainedVREFDQ_A0==74
894 00:16:45.516883 TrainedVREFDQ_A1==74
895 00:16:45.517440 VrefDac_Margin_A0==25
896 00:16:45.517900 DeviceVref_Margin_A0==40
897 00:16:45.522472 VrefDac_Margin_A1==25
898 00:16:45.523013 DeviceVref_Margin_A1==40
899 00:16:45.523451
900 00:16:45.523882
901 00:16:45.527970 channel==1
902 00:16:45.528515 RxClkDly_Margin_A0==98 ps 10
903 00:16:45.528957 TxDqDly_Margin_A0==88 ps 9
904 00:16:45.533585 RxClkDly_Margin_A1==88 ps 9
905 00:16:45.534094 TxDqDly_Margin_A1==88 ps 9
906 00:16:45.539192 TrainedVREFDQ_A0==76
907 00:16:45.539722 TrainedVREFDQ_A1==77
908 00:16:45.540209 VrefDac_Margin_A0==22
909 00:16:45.544790 DeviceVref_Margin_A0==38
910 00:16:45.545299 VrefDac_Margin_A1==24
911 00:16:45.550447 DeviceVref_Margin_A1==37
912 00:16:45.550972
913 00:16:45.551414 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
914 00:16:45.551847
915 00:16:45.583930 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000019 00000017 00000019 00000018 00000019 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
916 00:16:45.584564 2D training succeed
917 00:16:45.589576 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
918 00:16:45.595222 auto size-- 65535DDR cs0 size: 2048MB
919 00:16:45.595745 DDR cs1 size: 2048MB
920 00:16:45.600833 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
921 00:16:45.601341 cs0 DataBus test pass
922 00:16:45.606462 cs1 DataBus test pass
923 00:16:45.606969 cs0 AddrBus test pass
924 00:16:45.607403 cs1 AddrBus test pass
925 00:16:45.607835
926 00:16:45.612085 100bdlr_step_size ps== 420
927 00:16:45.612608 result report
928 00:16:45.617609 boot times 0Enable ddr reg access
929 00:16:45.622186 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
930 00:16:45.636103 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
931 00:16:46.209956 0.0;M3 CHK:0;cm4_sp_mode 0
932 00:16:46.210640 MVN_1=0x00000000
933 00:16:46.215487 MVN_2=0x00000000
934 00:16:46.221244 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
935 00:16:46.221779 OPS=0x10
936 00:16:46.222245 ring efuse init
937 00:16:46.222692 chipver efuse init
938 00:16:46.226835 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
939 00:16:46.232439 [0.018961 Inits done]
940 00:16:46.233001 secure task start!
941 00:16:46.233491 high task start!
942 00:16:46.236185 low task start!
943 00:16:46.236723 run into bl31
944 00:16:46.243630 NOTICE: BL31: v1.3(release):4fc40b1
945 00:16:46.251174 NOTICE: BL31: Built : 15:58:17, May 22 2019
946 00:16:46.251704 NOTICE: BL31: G12A normal boot!
947 00:16:46.276817 NOTICE: BL31: BL33 decompress pass
948 00:16:46.281508 ERROR: Error initializing runtime service opteed_fast
949 00:16:47.515358
950 00:16:47.516091
951 00:16:47.522813 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
952 00:16:47.523361
953 00:16:47.523846 Model: Libre Computer AML-A311D-CC Alta
954 00:16:47.731719 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
955 00:16:47.755305 DRAM: 2 GiB (effective 3.8 GiB)
956 00:16:47.898602 Core: 408 devices, 31 uclasses, devicetree: separate
957 00:16:47.904498 WDT: Not starting watchdog@f0d0
958 00:16:47.936746 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
959 00:16:47.949202 Loading Environment from FAT... Card did not respond to voltage select! : -110
960 00:16:47.954182 ** Bad device specification mmc 0 **
961 00:16:47.964572 Card did not respond to voltage select! : -110
962 00:16:47.972223 ** Bad device specification mmc 0 **
963 00:16:47.972766 Couldn't find partition mmc 0
964 00:16:47.980529 Card did not respond to voltage select! : -110
965 00:16:47.986039 ** Bad device specification mmc 0 **
966 00:16:47.986566 Couldn't find partition mmc 0
967 00:16:47.991068 Error: could not access storage.
968 00:16:48.333482 Net: eth0: ethernet@ff3f0000
969 00:16:48.334135 starting USB...
970 00:16:48.585423 Bus usb@ff500000: Register 3000140 NbrPorts 3
971 00:16:48.586086 Starting the controller
972 00:16:48.592351 USB XHCI 1.10
973 00:16:50.146631 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
974 00:16:50.153947 scanning usb for storage devices... 0 Storage Device(s) found
976 00:16:50.205792 Hit any key to stop autoboot: 1
977 00:16:50.207120 end: 2.4.2 bootloader-interrupt (duration 00:00:31) [common]
978 00:16:50.207828 start: 2.4.3 bootloader-commands (timeout 00:04:29) [common]
979 00:16:50.208480 Setting prompt string to ['=>']
980 00:16:50.209073 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:29)
981 00:16:50.222271 0
982 00:16:50.223308 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
983 00:16:50.223926 Sending with 10 millisecond of delay
985 00:16:51.359599 => setenv autoload no
986 00:16:51.370661 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:27)
987 00:16:51.377067 setenv autoload no
988 00:16:51.377959 Sending with 10 millisecond of delay
990 00:16:53.175833 => setenv initrd_high 0xffffffff
991 00:16:53.186650 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:26)
992 00:16:53.187504 setenv initrd_high 0xffffffff
993 00:16:53.188320 Sending with 10 millisecond of delay
995 00:16:54.805516 => setenv fdt_high 0xffffffff
996 00:16:54.816508 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:24)
997 00:16:54.817566 setenv fdt_high 0xffffffff
998 00:16:54.818451 Sending with 10 millisecond of delay
1000 00:16:55.110615 => dhcp
1001 00:16:55.121574 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:24)
1002 00:16:55.122650 dhcp
1003 00:16:55.123218 Speed: 1000, full duplex
1004 00:16:55.123767 BOOTP broadcast 1
1005 00:16:55.280963 DHCP client bound to address 192.168.6.27 (159 ms)
1006 00:16:55.282001 Sending with 10 millisecond of delay
1008 00:16:56.959420 => setenv serverip 192.168.6.2
1009 00:16:56.970454 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:22)
1010 00:16:56.971607 setenv serverip 192.168.6.2
1011 00:16:56.972499 Sending with 10 millisecond of delay
1013 00:17:00.698921 => tftpboot 0x01080000 919150/tftp-deploy-34_gl3d2/kernel/uImage
1014 00:17:00.709871 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1015 00:17:00.710933 tftpboot 0x01080000 919150/tftp-deploy-34_gl3d2/kernel/uImage
1016 00:17:00.711471 Speed: 1000, full duplex
1017 00:17:00.712090 Using ethernet@ff3f0000 device
1018 00:17:00.712656 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1019 00:17:00.718229 Filename '919150/tftp-deploy-34_gl3d2/kernel/uImage'.
1020 00:17:00.722096 Load address: 0x1080000
1021 00:17:03.750585 Loading: *################################################## 43.6 MiB
1022 00:17:03.751258 14.4 MiB/s
1023 00:17:03.751760 done
1024 00:17:03.755095 Bytes transferred = 45716032 (2b99240 hex)
1025 00:17:03.755949 Sending with 10 millisecond of delay
1027 00:17:08.445369 => tftpboot 0x08000000 919150/tftp-deploy-34_gl3d2/ramdisk/ramdisk.cpio.gz.uboot
1028 00:17:08.456198 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:10)
1029 00:17:08.457070 tftpboot 0x08000000 919150/tftp-deploy-34_gl3d2/ramdisk/ramdisk.cpio.gz.uboot
1030 00:17:08.457568 Speed: 1000, full duplex
1031 00:17:08.458028 Using ethernet@ff3f0000 device
1032 00:17:08.458894 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1033 00:17:08.470770 Filename '919150/tftp-deploy-34_gl3d2/ramdisk/ramdisk.cpio.gz.uboot'.
1034 00:17:08.471380 Load address: 0x8000000
1035 00:17:15.377829 Loading: *#########T ######################################### 22.4 MiB
1036 00:17:15.378488 3.2 MiB/s
1037 00:17:15.378970 done
1038 00:17:15.382233 Bytes transferred = 23437020 (1659edc hex)
1039 00:17:15.383044 Sending with 10 millisecond of delay
1041 00:17:20.552535 => tftpboot 0x01070000 919150/tftp-deploy-34_gl3d2/dtb/meson-g12b-a311d-libretech-cc.dtb
1042 00:17:20.563076 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:03:58)
1043 00:17:20.563559 tftpboot 0x01070000 919150/tftp-deploy-34_gl3d2/dtb/meson-g12b-a311d-libretech-cc.dtb
1044 00:17:20.563813 Speed: 1000, full duplex
1045 00:17:20.564062 Using ethernet@ff3f0000 device
1046 00:17:20.568333 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1047 00:17:20.575624 Filename '919150/tftp-deploy-34_gl3d2/dtb/meson-g12b-a311d-libretech-cc.dtb'.
1048 00:17:20.587492 Load address: 0x1070000
1049 00:17:20.599422 Loading: *################################################## 53.4 KiB
1050 00:17:20.600041 2.9 MiB/s
1051 00:17:20.600566 done
1052 00:17:20.602857 Bytes transferred = 54703 (d5af hex)
1053 00:17:20.603751 Sending with 10 millisecond of delay
1055 00:17:33.911066 => setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/919150/extract-nfsrootfs-mv_frtrz,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
1056 00:17:33.922127 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:03:45)
1057 00:17:33.923330 setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/919150/extract-nfsrootfs-mv_frtrz,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
1058 00:17:33.924198 Sending with 10 millisecond of delay
1060 00:17:36.264690 => bootm 0x01080000 0x08000000 0x01070000
1061 00:17:36.275529 Setting prompt string to ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1062 00:17:36.276252 bootloader-commands: Wait for prompt ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:03:42)
1063 00:17:36.277363 bootm 0x01080000 0x08000000 0x01070000
1064 00:17:36.278134 ## Booting kernel from Legacy Image at 01080000 ...
1065 00:17:36.280581 Image Name:
1066 00:17:36.285983 Image Type: AArch64 Linux Kernel Image (uncompressed)
1067 00:17:36.286573 Data Size: 45715968 Bytes = 43.6 MiB
1068 00:17:36.291555 Load Address: 01080000
1069 00:17:36.292065 Entry Point: 01080000
1070 00:17:36.486752 Verifying Checksum ... OK
1071 00:17:36.487409 ## Loading init Ramdisk from Legacy Image at 08000000 ...
1072 00:17:36.492221 Image Name:
1073 00:17:36.497671 Image Type: AArch64 Linux RAMDisk Image (uncompressed)
1074 00:17:36.498174 Data Size: 23436956 Bytes = 22.4 MiB
1075 00:17:36.503279 Load Address: 00000000
1076 00:17:36.503786 Entry Point: 00000000
1077 00:17:36.605518 Verifying Checksum ... OK
1078 00:17:36.606126 ## Flattened Device Tree blob at 01070000
1079 00:17:36.611025 Booting using the fdt blob at 0x1070000
1080 00:17:36.611729 Working FDT set to 1070000
1081 00:17:36.615415 Loading Kernel Image
1082 00:17:36.766778 Loading Ramdisk to 7e9a6000, end 7ffffe9c ... OK
1083 00:17:36.774984 Loading Device Tree to 000000007e995000, end 000000007e9a55ae ... OK
1084 00:17:36.775365 Working FDT set to 7e995000
1085 00:17:36.775598
1086 00:17:36.776230 end: 2.4.3 bootloader-commands (duration 00:00:47) [common]
1087 00:17:36.776597 start: 2.4.4 auto-login-action (timeout 00:03:42) [common]
1088 00:17:36.776853 Setting prompt string to ['Linux version [0-9]']
1089 00:17:36.777094 Setting prompt string to ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1090 00:17:36.777347 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:05:00)
1091 00:17:36.778212 Starting kernel ...
1092 00:17:36.778503
1093 00:17:36.815076 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x410fd034]
1094 00:17:36.815840 start: 2.4.4.1 login-action (timeout 00:03:42) [common]
1095 00:17:36.816173 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
1096 00:17:36.816419 Setting prompt string to []
1097 00:17:36.816671 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
1098 00:17:36.816906 Using line separator: #'\n'#
1099 00:17:36.817112 No login prompt set.
1100 00:17:36.817333 Parsing kernel messages
1101 00:17:36.817531 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
1102 00:17:36.817934 [login-action] Waiting for messages, (timeout 00:03:42)
1103 00:17:36.818162 Waiting using forced prompt support (timeout 00:01:51)
1104 00:17:36.831699 [ 0.000000] Linux version 6.12.0-rc5 (KernelCI@build-j358312-arm64-gcc-12-defconfig-f7krg) (aarch64-linux-gnu-gcc (Debian 12.2.0-14) 12.2.0, GNU ld (GNU Binutils for Debian) 2.40) #1 SMP PREEMPT Thu Oct 31 23:44:52 UTC 2024
1105 00:17:36.837302 [ 0.000000] KASLR disabled due to lack of seed
1106 00:17:36.842703 [ 0.000000] Machine model: Libre Computer AML-A311D-CC Alta
1107 00:17:36.848225 [ 0.000000] efi: UEFI not found.
1108 00:17:36.853723 [ 0.000000] [Firmware Bug]: Kernel image misaligned at boot, please fix your bootloader!
1109 00:17:36.859286 [ 0.000000] Reserved memory: created CMA memory pool at 0x00000000e4c00000, size 256 MiB
1110 00:17:36.870329 [ 0.000000] OF: reserved mem: initialized node linux,cma, compatible id shared-dma-pool
1111 00:17:36.881528 [ 0.000000] OF: reserved mem: 0x00000000e4c00000..0x00000000f4bfffff (262144 KiB) map reusable linux,cma
1112 00:17:36.887270 [ 0.000000] OF: reserved mem: 0x0000000005000000..0x00000000052fffff (3072 KiB) nomap non-reusable secmon@5000000
1113 00:17:36.897845 [ 0.000000] OF: reserved mem: 0x0000000005300000..0x00000000072fffff (32768 KiB) nomap non-reusable secmon@5300000
1114 00:17:36.908934 [ 0.000000] earlycon: meson0 at MMIO 0x00000000ff803000 (options '115200n8')
1115 00:17:36.914403 [ 0.000000] printk: legacy bootconsole [meson0] enabled
1116 00:17:36.919914 [ 0.000000] NUMA: Faking a node at [mem 0x0000000000000000-0x00000000f4e5afff]
1117 00:17:36.925421 [ 0.000000] NODE_DATA(0) allocated [mem 0xe4666a80-0xe46690bf]
1118 00:17:36.925777 [ 0.000000] Zone ranges:
1119 00:17:36.930994 [ 0.000000] DMA [mem 0x0000000000000000-0x00000000f4e5afff]
1120 00:17:36.936415 [ 0.000000] DMA32 empty
1121 00:17:36.936819 [ 0.000000] Normal empty
1122 00:17:36.941981 [ 0.000000] Movable zone start for each node
1123 00:17:36.947454 [ 0.000000] Early memory node ranges
1124 00:17:36.953031 [ 0.000000] node 0: [mem 0x0000000000000000-0x0000000004ffffff]
1125 00:17:36.958544 [ 0.000000] node 0: [mem 0x0000000005000000-0x00000000072fffff]
1126 00:17:36.964047 [ 0.000000] node 0: [mem 0x0000000007300000-0x00000000f4e5afff]
1127 00:17:36.969597 [ 0.000000] Initmem setup node 0 [mem 0x0000000000000000-0x00000000f4e5afff]
1128 00:17:36.996942 [ 0.000000] On node 0, zone DMA: 12709 pages in unavailable ranges
1129 00:17:37.002472 [ 0.000000] psci: probing for conduit method from DT.
1130 00:17:37.002861 [ 0.000000] psci: PSCIv1.0 detected in firmware.
1131 00:17:37.007950 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
1132 00:17:37.014013 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
1133 00:17:37.018994 [ 0.000000] psci: SMC Calling Convention v1.1
1134 00:17:37.024494 [ 0.000000] percpu: Embedded 25 pages/cpu s61656 r8192 d32552 u102400
1135 00:17:37.030032 [ 0.000000] Detected VIPT I-cache on CPU0
1136 00:17:37.036105 [ 0.000000] CPU features: detected: ARM erratum 845719
1137 00:17:37.041200 [ 0.000000] alternatives: applying boot alternatives
1138 00:17:37.057612 [ 0.000000] Kernel command line: console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/919150/extract-nfsrootfs-mv_frtrz,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp
1139 00:17:37.069319 <6>[ 0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
1140 00:17:37.074151 <6>[ 0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes, linear)
1141 00:17:37.079697 <6>[ 0.000000] Fallback order for Node 0: 0
1142 00:17:37.085166 <6>[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 1003099
1143 00:17:37.090794 <6>[ 0.000000] Policy zone: DMA
1144 00:17:37.096351 <6>[ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
1145 00:17:37.101802 <6>[ 0.000000] software IO TLB: SWIOTLB bounce buffer size adjusted to 3MB
1146 00:17:37.107533 <6>[ 0.000000] software IO TLB: area num 8.
1147 00:17:37.115892 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000dfc00000-0x00000000e0000000] (4MB)
1148 00:17:37.163039 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=6, Nodes=1
1149 00:17:37.168699 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
1150 00:17:37.174092 <6>[ 0.000000] rcu: RCU event tracing is enabled.
1151 00:17:37.179803 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=512 to nr_cpu_ids=6.
1152 00:17:37.185659 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
1153 00:17:37.190712 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
1154 00:17:37.196332 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
1155 00:17:37.201773 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=6
1156 00:17:37.212690 <6>[ 0.000000] RCU Tasks: Setting shift to 3 and lim to 1 rcu_task_cb_adjust=1 rcu_task_cpu_ids=6.
1157 00:17:37.223873 <6>[ 0.000000] RCU Tasks Trace: Setting shift to 3 and lim to 1 rcu_task_cb_adjust=1 rcu_task_cpu_ids=6.
1158 00:17:37.229416 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
1159 00:17:37.234886 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
1160 00:17:37.235487 <6>[ 0.000000] GIC: Using split EOI/Deactivate mode
1161 00:17:37.244718 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
1162 00:17:37.257625 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 24.00MHz (phys).
1163 00:17:37.266705 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x588fe9dc0, max_idle_ns: 440795202592 ns
1164 00:17:37.272208 <6>[ 0.000001] sched_clock: 56 bits at 24MHz, resolution 41ns, wraps every 4398046511097ns
1165 00:17:37.277621 <6>[ 0.008797] Console: colour dummy device 80x25
1166 00:17:37.288977 <6>[ 0.012945] Calibrating delay loop (skipped), value calculated using timer frequency.. 48.00 BogoMIPS (lpj=96000)
1167 00:17:37.294208 <6>[ 0.023295] pid_max: default: 32768 minimum: 301
1168 00:17:37.299865 <6>[ 0.028190] LSM: initializing lsm=capability
1169 00:17:37.305200 <6>[ 0.032731] Mount-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
1170 00:17:37.316294 <6>[ 0.040211] Mountpoint-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
1171 00:17:37.321761 <6>[ 0.050767] rcu: Hierarchical SRCU implementation.
1172 00:17:37.327237 <6>[ 0.053265] rcu: Max phase no-delay instances is 1000.
1173 00:17:37.332710 <6>[ 0.058871] Timer migration: 1 hierarchy levels; 8 children per group; 1 crossnode level
1174 00:17:37.338374 <6>[ 0.071593] EFI services will not be available.
1175 00:17:37.343168 <6>[ 0.075243] smp: Bringing up secondary CPUs ...
1176 00:17:37.359692 <6>[ 0.077134] Detected VIPT I-cache on CPU1
1177 00:17:37.365180 <6>[ 0.077254] CPU1: Booted secondary processor 0x0000000001 [0x410fd034]
1178 00:17:37.370460 <6>[ 0.078598] CPU features: detected: Spectre-v2
1179 00:17:37.376343 <6>[ 0.078613] CPU features: detected: Spectre-v4
1180 00:17:37.382089 <6>[ 0.078618] CPU features: detected: Spectre-BHB
1181 00:17:37.387188 <6>[ 0.078623] CPU features: detected: ARM erratum 858921
1182 00:17:37.392636 <6>[ 0.078630] Detected VIPT I-cache on CPU2
1183 00:17:37.398061 <6>[ 0.078704] arch_timer: Enabling local workaround for ARM erratum 858921
1184 00:17:37.403550 <6>[ 0.078723] arch_timer: CPU2: Trapping CNTVCT access
1185 00:17:37.409076 <6>[ 0.078733] CPU2: Booted secondary processor 0x0000000100 [0x410fd092]
1186 00:17:37.414581 <6>[ 0.079683] Detected VIPT I-cache on CPU3
1187 00:17:37.420115 <6>[ 0.079729] arch_timer: Enabling local workaround for ARM erratum 858921
1188 00:17:37.425690 <6>[ 0.079739] arch_timer: CPU3: Trapping CNTVCT access
1189 00:17:37.431211 <6>[ 0.079747] CPU3: Booted secondary processor 0x0000000101 [0x410fd092]
1190 00:17:37.436721 <6>[ 0.083595] Detected VIPT I-cache on CPU4
1191 00:17:37.442300 <6>[ 0.083642] arch_timer: Enabling local workaround for ARM erratum 858921
1192 00:17:37.447692 <6>[ 0.083652] arch_timer: CPU4: Trapping CNTVCT access
1193 00:17:37.458891 <6>[ 0.083659] CPU4: Booted secondary processor 0x0000000102 [0x410fd092]
1194 00:17:37.459518 <6>[ 0.095655] Detected VIPT I-cache on CPU5
1195 00:17:37.469845 <6>[ 0.095703] arch_timer: Enabling local workaround for ARM erratum 858921
1196 00:17:37.470487 <6>[ 0.095712] arch_timer: CPU5: Trapping CNTVCT access
1197 00:17:37.480798 <6>[ 0.095720] CPU5: Booted secondary processor 0x0000000103 [0x410fd092]
1198 00:17:37.481379 <6>[ 0.095843] smp: Brought up 1 node, 6 CPUs
1199 00:17:37.486506 <6>[ 0.217076] SMP: Total of 6 processors activated.
1200 00:17:37.491954 <6>[ 0.221981] CPU: All CPU(s) started at EL2
1201 00:17:37.497483 <6>[ 0.226324] CPU features: detected: 32-bit EL0 Support
1202 00:17:37.502948 <6>[ 0.231641] CPU features: detected: 32-bit EL1 Support
1203 00:17:37.508508 <6>[ 0.236988] CPU features: detected: CRC32 instructions
1204 00:17:37.514010 <6>[ 0.242390] alternatives: applying system-wide alternatives
1205 00:17:37.531963 <6>[ 0.249573] Memory: 3557432K/4012396K available (17280K kernel code, 4900K rwdata, 11876K rodata, 10432K init, 742K bss, 187800K reserved, 262144K cma-reserved)
1206 00:17:37.532671 <6>[ 0.263934] devtmpfs: initialized
1207 00:17:37.543341 <6>[ 0.273071] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
1208 00:17:37.548446 <6>[ 0.277422] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
1209 00:17:37.553919 <6>[ 0.288212] 21392 pages in range for non-PLT usage
1210 00:17:37.559554 <6>[ 0.288222] 512912 pages in range for PLT usage
1211 00:17:37.564993 <6>[ 0.289785] pinctrl core: initialized pinctrl subsystem
1212 00:17:37.570515 <6>[ 0.301831] DMI not present or invalid.
1213 00:17:37.575971 <6>[ 0.306165] NET: Registered PF_NETLINK/PF_ROUTE protocol family
1214 00:17:37.581691 <6>[ 0.310896] DMA: preallocated 512 KiB GFP_KERNEL pool for atomic allocations
1215 00:17:37.592621 <6>[ 0.317680] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
1216 00:17:37.598027 <6>[ 0.325776] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
1217 00:17:37.603942 <6>[ 0.333253] audit: initializing netlink subsys (disabled)
1218 00:17:37.614900 <5>[ 0.338990] audit: type=2000 audit(0.260:1): state=initialized audit_enabled=0 res=1
1219 00:17:37.620293 <6>[ 0.340397] thermal_sys: Registered thermal governor 'step_wise'
1220 00:17:37.626701 <6>[ 0.346759] thermal_sys: Registered thermal governor 'power_allocator'
1221 00:17:37.631270 <6>[ 0.353020] cpuidle: using governor menu
1222 00:17:37.636638 <6>[ 0.363991] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
1223 00:17:37.642260 <6>[ 0.370927] ASID allocator initialised with 65536 entries
1224 00:17:37.650515 <6>[ 0.378362] Serial: AMBA PL011 UART driver
1225 00:17:37.658307 <6>[ 0.389015] platform ff600000.hdmi-tx: Fixed dependency cycle(s) with /soc/vpu@ff900000
1226 00:17:37.673576 <6>[ 0.404392] platform ff600000.hdmi-tx: Fixed dependency cycle(s) with /soc/vpu@ff900000
1227 00:17:37.684588 <6>[ 0.407057] platform ff900000.vpu: Fixed dependency cycle(s) with /soc/bus@ff600000/hdmi-tx@0
1228 00:17:37.690085 <6>[ 0.420179] platform ff900000.vpu: Fixed dependency cycle(s) with /cvbs-connector
1229 00:17:37.695601 <6>[ 0.423433] platform cvbs-connector: Fixed dependency cycle(s) with /soc/vpu@ff900000
1230 00:17:37.706562 <6>[ 0.431859] platform ff600000.hdmi-tx: Fixed dependency cycle(s) with /hdmi-connector
1231 00:17:37.712152 <6>[ 0.439480] platform hdmi-connector: Fixed dependency cycle(s) with /soc/bus@ff600000/hdmi-tx@0
1232 00:17:37.723114 <6>[ 0.453002] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
1233 00:17:37.728639 <6>[ 0.455303] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
1234 00:17:37.734126 <6>[ 0.461785] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
1235 00:17:37.740165 <6>[ 0.468761] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
1236 00:17:37.751808 <6>[ 0.475230] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
1237 00:17:37.757096 <6>[ 0.482215] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
1238 00:17:37.761773 <6>[ 0.488691] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
1239 00:17:37.767261 <6>[ 0.495670] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
1240 00:17:37.772757 <6>[ 0.503793] ACPI: Interpreter disabled.
1241 00:17:37.778287 <6>[ 0.509080] iommu: Default domain type: Translated
1242 00:17:37.783769 <6>[ 0.511203] iommu: DMA domain TLB invalidation policy: strict mode
1243 00:17:37.789293 <5>[ 0.517906] SCSI subsystem initialized
1244 00:17:37.794788 <6>[ 0.521767] usbcore: registered new interface driver usbfs
1245 00:17:37.800323 <6>[ 0.527260] usbcore: registered new interface driver hub
1246 00:17:37.805818 <6>[ 0.532780] usbcore: registered new device driver usb
1247 00:17:37.811373 <6>[ 0.539048] pps_core: LinuxPPS API ver. 1 registered
1248 00:17:37.816924 <6>[ 0.543197] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
1249 00:17:37.822393 <6>[ 0.552516] PTP clock support registered
1250 00:17:37.827947 <6>[ 0.556755] EDAC MC: Ver: 3.0.0
1251 00:17:37.833543 <6>[ 0.560388] scmi_core: SCMI protocol bus registered
1252 00:17:37.834076 <6>[ 0.565992] FPGA manager framework
1253 00:17:37.839026 <6>[ 0.568782] Advanced Linux Sound Architecture Driver Initialized.
1254 00:17:37.844569 <6>[ 0.575720] vgaarb: loaded
1255 00:17:37.850059 <6>[ 0.578261] clocksource: Switched to clocksource arch_sys_counter
1256 00:17:37.855716 <5>[ 0.584429] VFS: Disk quotas dquot_6.6.0
1257 00:17:37.861215 <6>[ 0.588412] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
1258 00:17:37.866640 <6>[ 0.595620] pnp: PnP ACPI: disabled
1259 00:17:37.872411 <6>[ 0.604178] NET: Registered PF_INET protocol family
1260 00:17:37.877858 <6>[ 0.604445] IP idents hash table entries: 65536 (order: 7, 524288 bytes, linear)
1261 00:17:37.888808 <6>[ 0.614615] tcp_listen_portaddr_hash hash table entries: 2048 (order: 3, 32768 bytes, linear)
1262 00:17:37.894297 <6>[ 0.620617] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
1263 00:17:37.905230 <6>[ 0.628509] TCP established hash table entries: 32768 (order: 6, 262144 bytes, linear)
1264 00:17:37.910736 <6>[ 0.636747] TCP bind hash table entries: 32768 (order: 8, 1048576 bytes, linear)
1265 00:17:37.916246 <6>[ 0.644545] TCP: Hash tables configured (established 32768 bind 32768)
1266 00:17:37.921907 <6>[ 0.651018] UDP hash table entries: 2048 (order: 4, 65536 bytes, linear)
1267 00:17:37.932776 <6>[ 0.657865] UDP-Lite hash table entries: 2048 (order: 4, 65536 bytes, linear)
1268 00:17:37.938485 <6>[ 0.665292] NET: Registered PF_UNIX/PF_LOCAL protocol family
1269 00:17:37.944005 <6>[ 0.671403] RPC: Registered named UNIX socket transport module.
1270 00:17:37.949430 <6>[ 0.677155] RPC: Registered udp transport module.
1271 00:17:37.954894 <6>[ 0.682059] RPC: Registered tcp transport module.
1272 00:17:37.960446 <6>[ 0.686976] RPC: Registered tcp-with-tls transport module.
1273 00:17:37.965942 <6>[ 0.692668] RPC: Registered tcp NFSv4.1 backchannel transport module.
1274 00:17:37.971749 <6>[ 0.699315] PCI: CLS 0 bytes, default 64
1275 00:17:37.972340 <6>[ 0.703632] Unpacking initramfs...
1276 00:17:37.977234 <6>[ 0.712915] kvm [1]: nv: 554 coarse grained trap handlers
1277 00:17:37.982723 <6>[ 0.713217] kvm [1]: IPA Size Limit: 40 bits
1278 00:17:37.988255 <6>[ 0.718898] kvm [1]: vgic interrupt IRQ9
1279 00:17:37.993893 <6>[ 0.721591] kvm [1]: Hyp nVHE mode initialized successfully
1280 00:17:37.999368 <5>[ 0.728850] Initialise system trusted keyrings
1281 00:17:38.004865 <6>[ 0.732193] workingset: timestamp_bits=42 max_order=20 bucket_order=0
1282 00:17:38.010394 <6>[ 0.738919] squashfs: version 4.0 (2009/01/31) Phillip Lougher
1283 00:17:38.015855 <5>[ 0.744947] NFS: Registering the id_resolver key type
1284 00:17:38.021417 <5>[ 0.749974] Key type id_resolver registered
1285 00:17:38.026885 <5>[ 0.754348] Key type id_legacy registered
1286 00:17:38.032373 <6>[ 0.758600] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
1287 00:17:38.037909 <6>[ 0.765473] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
1288 00:17:38.045371 <6>[ 0.773261] 9p: Installing v9fs 9p2000 file system support
1289 00:17:38.083502 <5>[ 0.819964] Key type asymmetric registered
1290 00:17:38.088916 <5>[ 0.820006] Asymmetric key parser 'x509' registered
1291 00:17:38.099925 <6>[ 0.823857] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 245)
1292 00:17:38.100432 <6>[ 0.831385] io scheduler mq-deadline registered
1293 00:17:38.105516 <6>[ 0.836124] io scheduler kyber registered
1294 00:17:38.110957 <6>[ 0.840392] io scheduler bfq registered
1295 00:17:38.117444 <6>[ 0.846298] irq_meson_gpio: 100 to 8 gpio interrupt mux initialized
1296 00:17:38.133604 <6>[ 0.866452] ledtrig-cpu: registered to indicate activity on CPUs
1297 00:17:38.165878 <6>[ 0.897510] soc soc0: Amlogic Meson G12B (A311D) Revision 29:b (10:2) Detected
1298 00:17:38.185221 <6>[ 0.910494] Serial: 8250/16550 driver, 4 port<6>[ 0.915046] ff803000.serial: ttyAML0 at MMIO 0xff803000 (irq = 14, base_baud = 1500000) is a meson_uart
1299 00:17:38.190722 <6>[ 0.924675] printk: legacy console [ttyAML0] enabled
1300 00:17:38.196225 <6>[ 0.924675] printk: legacy console [ttyAML0] enabled
1301 00:17:38.201794 <6>[ 0.929473] printk: legacy bootconsole [meson0] disabled
1302 00:17:38.207384 <6>[ 0.929473] printk: legacy bootconsole [meson0] disabled
1303 00:17:38.212925 <6>[ 0.943040] msm_serial: driver initialized
1304 00:17:38.218503 <6>[ 0.945412] SuperH (H)SCI(F) driver initialized
1305 00:17:38.218939 <6>[ 0.949966] STM32 USART driver initialized
1306 00:17:38.226556 <5>[ 0.956108] random: crng init done
1307 00:17:38.233448 <6>[ 0.965699] loop: module loaded
1308 00:17:38.233922 <6>[ 0.967007] megasas: 07.727.03.00-rc1
1309 00:17:38.238938 <6>[ 0.974409] tun: Universal TUN/TAP device driver, 1.6
1310 00:17:38.244573 <6>[ 0.975609] thunder_xcv, ver 1.0
1311 00:17:38.245007 <6>[ 0.977566] thunder_bgx, ver 1.0
1312 00:17:38.250054 <6>[ 0.981057] nicpf, ver 1.0
1313 00:17:38.255592 <6>[ 0.985657] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
1314 00:17:38.261130 <6>[ 0.991427] hns3: Copyright (c) 2017 Huawei Corporation.
1315 00:17:38.266722 <6>[ 0.997011] hclge is initializing
1316 00:17:38.272240 <6>[ 1.000556] e1000: Intel(R) PRO/1000 Network Driver
1317 00:17:38.277811 <6>[ 1.005634] e1000: Copyright (c) 1999-2006 Intel Corporation.
1318 00:17:38.283348 <6>[ 1.011658] e1000e: Intel(R) PRO/1000 Network Driver
1319 00:17:38.288886 <6>[ 1.016816] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
1320 00:17:38.294527 <6>[ 1.022993] igb: Intel(R) Gigabit Ethernet Network Driver
1321 00:17:38.299962 <6>[ 1.028600] igb: Copyright (c) 2007-2014 Intel Corporation.
1322 00:17:38.305577 <6>[ 1.034430] igbvf: Intel(R) Gigabit Virtual Function Network Driver
1323 00:17:38.311065 <6>[ 1.040907] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
1324 00:17:38.316612 <6>[ 1.047653] sky2: driver version 1.30
1325 00:17:38.322172 <6>[ 1.052739] VFIO - User Level meta-driver version: 0.3
1326 00:17:38.327695 <6>[ 1.060242] usbcore: registered new interface driver usb-storage
1327 00:17:38.333682 <6>[ 1.066356] i2c_dev: i2c /dev entries driver
1328 00:17:38.346323 <6>[ 1.077325] sdhci: Secure Digital Host Controller Interface driver
1329 00:17:38.346754 <6>[ 1.078125] sdhci: Copyright(c) Pierre Ossman
1330 00:17:38.355305 <6>[ 1.083852] Synopsys Designware Multimedia Card Interface Driver
1331 00:17:38.360881 <6>[ 1.090372] sdhci-pltfm: SDHCI platform and OF driver helper
1332 00:17:38.366424 <6>[ 1.098006] meson-sm: secure-monitor enabled
1333 00:17:38.371970 <6>[ 1.100531] usbcore: registered new interface driver usbhid
1334 00:17:38.375812 <6>[ 1.105185] usbhid: USB HID core driver
1335 00:17:38.383451 <6>[ 1.119970] NET: Registered PF_PACKET protocol family
1336 00:17:38.388948 <6>[ 1.120060] 9pnet: Installing 9P2000 support
1337 00:17:38.396066 <5>[ 1.124232] Key type dns_resolver registered
1338 00:17:38.401556 <6>[ 1.135771] registered taskstats version 1
1339 00:17:38.407094 <5>[ 1.135922] Loading compiled-in X.509 certificates
1340 00:17:38.410706 <6>[ 1.144594] Demotion targets for Node 0: null
1341 00:17:38.451969 <6>[ 1.188405] dwc3-meson-g12a ffe09000.usb: USB2 ports: 2
1342 00:17:38.457470 <6>[ 1.188450] dwc3-meson-g12a ffe09000.usb: USB3 ports: 1
1343 00:17:38.466449 <4>[ 1.198694] dwc2 ff400000.usb: supply vusb_d not found, using dummy regulator
1344 00:17:38.472068 <4>[ 1.201186] dwc2 ff400000.usb: supply vusb_a not found, using dummy regulator
1345 00:17:38.483059 <6>[ 1.208781] dwc2 ff400000.usb: EPs: 7, dedicated fifos, 712 entries in SPRAM
1346 00:17:38.486579 <6>[ 1.218042] xhci-hcd xhci-hcd.0.auto: xHCI Host Controller
1347 00:17:38.497705 <6>[ 1.221504] xhci-hcd xhci-hcd.0.auto: new USB bus registered, assigned bus number 1
1348 00:17:38.503223 <6>[ 1.229491] xhci-hcd xhci-hcd.0.auto: hcc params 0x0228fe6c hci version 0x110 quirks 0x0000808000000010
1349 00:17:38.508711 <6>[ 1.239010] xhci-hcd xhci-hcd.0.auto: irq 16, io mem 0xff500000
1350 00:17:38.519793 <6>[ 1.245220] xhci-hcd xhci-hcd.0.auto: xHCI Host Controller
1351 00:17:38.525334 <6>[ 1.250855] xhci-hcd xhci-hcd.0.auto: new USB bus registered, assigned bus number 2
1352 00:17:38.530891 <6>[ 1.258743] xhci-hcd xhci-hcd.0.auto: Host supports USB 3.0 SuperSpeed
1353 00:17:38.536427 <6>[ 1.266061] hub 1-0:1.0: USB hub found
1354 00:17:38.542050 <6>[ 1.269514] hub 1-0:1.0: 2 ports detected
1355 00:17:38.547599 <6>[ 1.275627] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
1356 00:17:38.553070 <6>[ 1.282474] hub 2-0:1.0: USB hub found
1357 00:17:38.556806 <6>[ 1.286038] hub 2-0:1.0: 1 port detected
1358 00:17:38.576737 <6>[ 1.310690] meson-gx-mmc ffe05000.mmc: Got CD GPIO
1359 00:17:38.592553 <6>[ 1.325715] meson-gx-mmc ffe07000.mmc: allocated mmc-pwrseq
1360 00:17:38.630166 <6>[ 1.363038] Trying to probe devices needed for running init ...
1361 00:17:38.790077 <6>[ 1.522295] usb 1-1: new high-speed USB device number 2 using xhci-hcd
1362 00:17:38.930253 <6>[ 1.666599] Freeing initrd memory: 22884K
1363 00:17:38.935673 <6>[ 1.669659] mmc0: new ultra high speed SDR104 SDXC card at address e624
1364 00:17:38.941184 <6>[ 1.672582] mmcblk0: mmc0:e624 SD64G 59.5 GiB
1365 00:17:38.945138 <6>[ 1.678183] mmcblk0: p1
1366 00:17:38.977413 <6>[ 1.713853] hub 1-1:1.0: USB hub found
1367 00:17:38.983117 <6>[ 1.714159] hub 1-1:1.0: 4 ports detected
1368 00:17:39.054189 <6>[ 1.786400] usb 2-1: new SuperSpeed USB device number 2 using xhci-hcd
1369 00:17:39.106025 <6>[ 1.842447] hub 2-1:1.0: USB hub found
1370 00:17:39.111843 <6>[ 1.843275] hub 2-1:1.0: 4 ports detected
1371 00:17:50.909870 <6>[ 13.646322] clk: Disabling unused clocks
1372 00:17:50.915362 <6>[ 13.646493] PM: genpd: Disabling unused power domains
1373 00:17:50.923552 <6>[ 13.650180] ALSA device list:
1374 00:17:50.924146 <6>[ 13.653385] No soundcards found.
1375 00:17:50.929768 <6>[ 13.665259] Freeing unused kernel memory: 10432K
1376 00:17:50.934940 <6>[ 13.665356] Run /init as init process
1377 00:17:50.941900 Loading, please wait...
1378 00:17:50.979894 Starting systemd-udevd version 252.22-1~deb12u1
1379 00:17:51.412697 <6>[ 14.147088] mc: Linux media interface: v0.10
1380 00:17:51.433521 <6>[ 14.164598] videodev: Linux video capture interface: v2.00
1381 00:17:51.439297 <6>[ 14.168789] meson8b-dwmac ff3f0000.ethernet: IRQ eth_wake_irq not found
1382 00:17:51.444650 <6>[ 14.171647] meson8b-dwmac ff3f0000.ethernet: IRQ eth_lpi not found
1383 00:17:51.450186 <6>[ 14.178019] meson8b-dwmac ff3f0000.ethernet: IRQ sfty not found
1384 00:17:51.455730 <6>[ 14.184237] meson8b-dwmac ff3f0000.ethernet: PTP uses main clock
1385 00:17:51.461346 <6>[ 14.191827] meson8b-dwmac ff3f0000.ethernet: User ID: 0x11, Synopsys ID: 0x37
1386 00:17:51.466819 <6>[ 14.197787] meson8b-dwmac ff3f0000.ethernet: DWMAC1000
1387 00:17:51.477927 <6>[ 14.203235] meson8b-dwmac ff3f0000.ethernet: DMA HW capability register supported
1388 00:17:51.483473 <6>[ 14.210947] meson8b-dwmac ff3f0000.ethernet: RX Checksum Offload Engine supported
1389 00:17:51.489011 <6>[ 14.212042] panfrost ffe40000.gpu: clock rate = 24000000
1390 00:17:51.494522 <6>[ 14.218642] meson8b-dwmac ff3f0000.ethernet: COE Type 2
1391 00:17:51.505655 <6>[ 14.218652] meson8b-dwmac ff3f0000.ethernet: TX Checksum insertion supported
1392 00:17:51.511329 <3>[ 14.224515] panfrost ffe40000.gpu: error -ENODEV: _opp_set_regulators: no regulator (mali) found
1393 00:17:51.516825 <6>[ 14.229635] meson8b-dwmac ff3f0000.ethernet: Wake-Up On Lan supported
1394 00:17:51.522439 <6>[ 14.254331] meson8b-dwmac ff3f0000.ethernet: Normal descriptors
1395 00:17:51.533483 <6>[ 14.259017] meson8b-dwmac ff3f0000.ethernet: Ring mode enabled
1396 00:17:51.538994 <6>[ 14.264842] meson8b-dwmac ff3f0000.ethernet: Enable RX Mitigation via HW Watchdog Timer
1397 00:17:51.544565 <6>[ 14.278120] meson-vrtc ff8000a8.rtc: registered as rtc0
1398 00:17:51.555678 <6>[ 14.278560] meson-vrtc ff8000a8.rtc: setting system clock to 1970-01-01T00:00:14 UTC (14)
1399 00:17:51.556189 <6>[ 14.283358] Registered IR keymap rc-empty
1400 00:17:51.561212 <6>[ 14.287938] meson-drm ff900000.vpu: Queued 2 outputs on vpu
1401 00:17:51.572291 <6>[ 14.298193] panfrost ffe40000.gpu: mali-g52 id 0x7212 major 0x0 minor 0x0 status 0x0
1402 00:17:51.577824 <6>[ 14.300097] rc rc0: meson-ir as /devices/platform/soc/ff800000.bus/ff808000.ir/rc/rc0
1403 00:17:51.588936 <6>[ 14.304971] panfrost ffe40000.gpu: features: 00000000,00000cf7, issues: 00000000,00000400
1404 00:17:51.600104 <6>[ 14.321469] panfrost ffe40000.gpu: Features: L2:0x07110206 Shader:0x00000000 Tiler:0x00000809 Mem:0x1 MMU:0x00002830 AS:0xff JS:0x7
1405 00:17:51.605630 <3>[ 14.321736] debugfs: Directory 'ff800280.cec' with parent 'regmap' already present!
1406 00:17:51.616708 <4>[ 14.327585] meson_vdec: module is from the staging directory, the quality is unknown, you have been warned.
1407 00:17:51.622280 <6>[ 14.333477] panfrost ffe40000.gpu: shader_present=0x3 l2_present=0x1
1408 00:17:51.633308 <6>[ 14.358170] input: meson-ir as /devices/platform/soc/ff800000.bus/ff808000.ir/rc/rc0/input0
1409 00:17:51.638864 <4>[ 14.370118] meson-pwm ff802000.pwm: using obsolete compatible, please consider updating dt
1410 00:17:51.644455 <6>[ 14.370748] rc rc0: sw decoder init
1411 00:17:51.649942 <6>[ 14.379148] meson-ir ff808000.ir: receiver initialized
1412 00:17:51.657645 <6>[ 14.384338] [drm] Initialized panfrost 1.2.0 for ffe40000.gpu on minor 0
1413 00:17:51.686099 <6>[ 14.417075] meson-dw-hdmi ff600000.hdmi-tx: Detected HDMI TX controller v2.01a with HDCP (meson_dw_hdmi_phy)
1414 00:17:51.697979 <6>[ 14.422513] meson-dw-hdmi ff600000.hdmi-tx: registered DesignWare HDMI I2C bus driver
1415 00:17:51.702750 <6>[ 14.430140] usbcore: registered new device driver onboard-usb-dev
1416 00:17:51.713864 <6>[ 14.431341] meson-drm ff900000.vpu: bound ff600000.hdmi-tx (ops meson_dw_hdmi_ops [meson_dw_hdmi])
1417 00:17:51.719477 <3>[ 14.445574] meson-drm ff900000.vpu: DSI transceiver device is disabled
1418 00:17:51.725053 <6>[ 14.451677] meson8b-dwmac ff3f0000.ethernet end0: renamed from eth0
1419 00:17:51.731722 <6>[ 14.454871] [drm] Initialized meson 1.0.0 for ff900000.vpu on minor 1
1420 00:17:51.915249 <6>[ 14.627044] Console: switching to colour frame buffer device 128x48
1421 00:17:51.921119 <6>[ 14.646932] meson-drm ff900000.vpu: [drm] fb0: mesondrmfb frame buffer device
1422 00:17:52.019923 <6>[ 14.747783] cpufreq: cpufreq_online: CPU2: Running at unlisted initial frequency: 999999 KHz, changing to: 1000000 KHz
1423 00:17:52.161747 <6>[ 14.897880] hub 1-1:1.0: USB hub found
1424 00:17:52.167116 <6>[ 14.898175] hub 1-1:1.0: 4 ports detected
1425 00:17:52.173592 <6>[ 14.902981] onboard-usb-dev 1-1: USB disconnect, device number 2
1426 00:17:52.490119 <4>[ 15.226312] rc rc0: two consecutive events of type space
1427 00:17:52.542211 <6>[ 15.274299] usb 1-1: new high-speed USB device number 3 using xhci-hcd
1428 00:17:52.737801 <6>[ 15.473932] hub 1-1:1.0: USB hub found
1429 00:17:52.743287 <6>[ 15.474265] hub 1-1:1.0: 4 ports detected
1430 00:17:52.756241 Begin: Loading essential drivers ... done.
1431 00:17:52.761744 Begin: Running /scripts/init-premount ... done.
1432 00:17:52.767199 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
1433 00:17:52.780958 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
1434 00:17:52.781415 Device /sys/class/net/end0 found
1435 00:17:52.781842 done.
1436 00:17:52.799133 Begin: Waiting up to 180 secs for any network device to become available ... done.
1437 00:17:52.868989 IP-Config: end0 hardware address de:ca:d3:e3:c6:63 mtu 1500 DHCP
<6>[ 15.595784] meson8b-dwmac ff3f0000.ethernet end0: Register MEM_TYPE_PAGE_POOL RxQ-0
1438 00:17:52.869582
1439 00:17:52.934973 <6>[ 15.665810] usb 2-1: reset SuperSpeed USB device number 2 using xhci-hcd
1440 00:17:52.948843 <6>[ 15.666373] meson8b-dwmac ff3f0000.ethernet end0: PHY [mdio_mux-0.0:00] driver [RTL8211F Gigabit Ethernet] (irq=32)
1441 00:17:52.954412 <6>[ 15.686271] meson8b-dwmac ff3f0000.ethernet end0: No Safety Features support found
1442 00:17:52.960027 <6>[ 15.688456] meson8b-dwmac ff3f0000.ethernet end0: PTP not supported by HW
1443 00:17:52.970240 <6>[ 15.695802] meson8b-dwmac ff3f0000.ethernet end0: configuring for phy/rgmii link mode
1444 00:17:53.206053 <6>[ 15.937777] usb 2-1: reset SuperSpeed USB device number 2 using xhci-hcd
1445 00:17:54.044203 IP-Config: no response after 2 secs - giving up
1446 00:17:54.109840 IP-Config: end0 hardware address de:ca:d3:e3:c6:63 mtu 1500 DHCP
1447 00:17:55.937925 <6>[ 18.668132] meson8b-dwmac ff3f0000.ethernet end0: Link is Up - 1Gbps/Full - flow control off
1448 00:17:56.318746 IP-Config: end0 guessed broadcast address 192.168.6.255
1449 00:17:56.324375 IP-Config: end0 complete (dhcp from 192.168.6.1):
1450 00:17:56.329747 address: 192.168.6.27 broadcast: 192.168.6.255 netmask: 255.255.255.0
1451 00:17:56.340854 gateway: 192.168.6.1 dns0 : 10.255.253.1 dns1 : 0.0.0.0
1452 00:17:56.341276 rootserver: 192.168.6.1 rootpath:
1453 00:17:56.344401 filename :
1454 00:17:56.443829 done.
1455 00:17:56.454174 Begin: Running /scripts/nfs-bottom ... done.
1456 00:17:56.463176 Begin: Running /scripts/init-bottom ... done.
1457 00:17:56.790211 <30>[ 19.522151] systemd[1]: System time before build time, advancing clock.
1458 00:17:56.837844 <6>[ 19.574228] NET: Registered PF_INET6 protocol family
1459 00:17:56.843255 <6>[ 19.576075] Segment Routing with IPv6
1460 00:17:56.848604 <6>[ 19.577735] In-situ OAM (IOAM) with IPv6
1461 00:17:56.918860 <30>[ 19.627607] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
1462 00:17:56.924828 <30>[ 19.655003] systemd[1]: Detected architecture arm64.
1463 00:17:56.925293
1464 00:17:56.931871 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
1465 00:17:56.932514
1466 00:17:56.943268 <30>[ 19.675969] systemd[1]: Hostname set to <debian-bookworm-arm64>.
1467 00:17:57.626358 <30>[ 20.357732] systemd[1]: Queued start job for default target graphical.target.
1468 00:17:57.657832 <30>[ 20.388794] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
1469 00:17:57.666456 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
1470 00:17:57.677981 <30>[ 20.407261] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
1471 00:17:57.684776 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
1472 00:17:57.696380 <30>[ 20.427353] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
1473 00:17:57.705423 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
1474 00:17:57.716527 <30>[ 20.447037] systemd[1]: Created slice user.slice - User and Session Slice.
1475 00:17:57.722925 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
1476 00:17:57.734043 <30>[ 20.462538] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
1477 00:17:57.745457 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
1478 00:17:57.756544 <30>[ 20.482468] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
1479 00:17:57.763126 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
1480 00:17:57.785337 <30>[ 20.502433] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
1481 00:17:57.790725 <30>[ 20.516560] systemd[1]: Expecting device dev-ttyAML0.device - /dev/ttyAML0...
1482 00:17:57.798417 Expecting device [0;1;39mdev-ttyAML0.device[0m - /dev/ttyAML0...
1483 00:17:57.809498 <30>[ 20.538359] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
1484 00:17:57.815540 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
1485 00:17:57.831405 <30>[ 20.562392] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
1486 00:17:57.845062 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
1487 00:17:57.850599 <30>[ 20.582401] systemd[1]: Reached target paths.target - Path Units.
1488 00:17:57.859060 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
1489 00:17:57.864557 <30>[ 20.598359] systemd[1]: Reached target remote-fs.target - Remote File Systems.
1490 00:17:57.876313 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
1491 00:17:57.881899 <30>[ 20.614360] systemd[1]: Reached target slices.target - Slice Units.
1492 00:17:57.890037 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
1493 00:17:57.895577 <30>[ 20.630378] systemd[1]: Reached target swap.target - Swaps.
1494 00:17:57.903415 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
1495 00:17:57.915355 <30>[ 20.646388] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
1496 00:17:57.924320 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
1497 00:17:57.939542 <30>[ 20.670554] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
1498 00:17:57.948759 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
1499 00:17:57.961586 <30>[ 20.692623] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
1500 00:17:57.970365 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
1501 00:17:57.984265 <30>[ 20.715256] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
1502 00:17:57.997382 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
1503 00:17:58.009123 <30>[ 20.734700] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
1504 00:17:58.011413 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
1505 00:17:58.024304 <30>[ 20.755296] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
1506 00:17:58.033426 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
1507 00:17:58.049263 <30>[ 20.780282] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
1508 00:17:58.054795 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
1509 00:17:58.067584 <30>[ 20.798614] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
1510 00:17:58.076049 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
1511 00:17:58.115424 <30>[ 20.846479] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
1512 00:17:58.122243 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
1513 00:17:58.133741 <30>[ 20.864774] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
1514 00:17:58.141310 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
1515 00:17:58.153831 <30>[ 20.884888] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
1516 00:17:58.161732 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
1517 00:17:58.179450 <30>[ 20.902645] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
1518 00:17:58.188486 <30>[ 20.915584] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
1519 00:17:58.195379 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
1520 00:17:58.239590 <30>[ 20.970628] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
1521 00:17:58.247535 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
1522 00:17:58.266285 <30>[ 20.997259] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
1523 00:17:58.273807 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
1524 00:17:58.285720 <30>[ 21.016768] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
1525 00:17:58.296823 <6>[ 21.021174] device-mapper: ioctl: 4.48.0-ioctl (2023-03-01) initialised: dm-devel@lists.linux.dev
1526 00:17:58.301726 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
1527 00:17:58.314268 <30>[ 21.045252] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
1528 00:17:58.322516 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
1529 00:17:58.333913 <30>[ 21.064940] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
1530 00:17:58.341148 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
1531 00:17:58.353702 <30>[ 21.084757] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
1532 00:17:58.359328 <6>[ 21.087759] fuse: init (API version 7.41)
1533 00:17:58.363254 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
1534 00:17:58.384104 <30>[ 21.115112] systemd[1]: Starting systemd-journald.service - Journal Service...
1535 00:17:58.390478 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
1536 00:17:58.408070 <30>[ 21.139089] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
1537 00:17:58.415742 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
1538 00:17:58.442161 <30>[ 21.172975] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
1539 00:17:58.451523 Starting [0;1;39msystemd-network-g… units from Kernel command line...
1540 00:17:58.470610 <30>[ 21.201553] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
1541 00:17:58.479482 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
1542 00:17:58.497675 <30>[ 21.228606] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
1543 00:17:58.505770 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
1544 00:17:58.522968 <30>[ 21.253886] systemd[1]: Started systemd-journald.service - Journal Service.
1545 00:17:58.529921 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
1546 00:17:58.541538 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
1547 00:17:58.556234 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
1548 00:17:58.568248 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
1549 00:17:58.580541 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
1550 00:17:58.592812 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
1551 00:17:58.606414 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
1552 00:17:58.617952 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
1553 00:17:58.630491 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
1554 00:17:58.644972 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
1555 00:17:58.652126 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
1556 00:17:58.664423 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
1557 00:17:58.680401 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
1558 00:17:58.700400 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
1559 00:17:58.712784 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
1560 00:17:58.759451 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
1561 00:17:58.776807 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
1562 00:17:58.792438 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
1563 00:17:58.811689 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
1564 00:17:58.830072 <46>[ 21.560984] systemd-journald[235]: Received client request to flush runtime journal.
1565 00:17:58.837555 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
1566 00:17:58.865296 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
1567 00:17:58.944103 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
1568 00:17:58.952506 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
1569 00:17:58.968397 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
1570 00:17:58.985440 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
1571 00:17:58.996460 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
1572 00:17:59.048285 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
1573 00:17:59.103370 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
1574 00:17:59.127496 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
1575 00:17:59.227601 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
1576 00:17:59.234102 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
1577 00:17:59.247281 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
1578 00:17:59.287141 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
1579 00:17:59.297835 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
1580 00:17:59.475334 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
1581 00:17:59.527323 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
1582 00:17:59.573289 [[0;32m OK [0m] Found device [0;1;39mdev-ttyAML0.device[0m - /dev/ttyAML0.
1583 00:17:59.580725 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
1584 00:17:59.639417 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
1585 00:17:59.654407 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
1586 00:17:59.689316 <5>[ 22.420396] cfg80211: Loading compiled-in X.509 certificates for regulatory database
1587 00:17:59.726837 <5>[ 22.457725] Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
1588 00:17:59.732426 <5>[ 22.458465] Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
1589 00:17:59.743419 [<4>[ 22.466332] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
1590 00:17:59.743765 <6>[ 22.474843] cfg80211: failed to load regulatory.db
1591 00:17:59.754306 [0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
1592 00:17:59.807912 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
1593 00:17:59.814553 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
1594 00:17:59.837886 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
1595 00:17:59.856109 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
1596 00:17:59.864181 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
1597 00:17:59.879421 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
1598 00:17:59.906743 <46>[ 22.628462] systemd-journald[235]: Oldest entry in /var/log/journal/44a983756b26438995e691b947c527e4/system.journal is older than the configured file retention duration (1month), suggesting rotation.
1599 00:17:59.924287 <46>[ 22.640979] systemd-journald[235]: /var/log/journal/44a983756b26438995e691b947c527e4/system.journal: Journal header limits reached or header out-of-date, rotating.
1600 00:17:59.930614 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
1601 00:17:59.947381 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
1602 00:17:59.955835 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
1603 00:18:00.046851 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
1604 00:18:00.063784 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
1605 00:18:00.070837 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
1606 00:18:00.084311 [[0;32m OK [0m] Reached target [0;1;39musb-gadget.…m - Hardware activated USB gadget.
1607 00:18:00.119590 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
1608 00:18:00.126337 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
1609 00:18:00.134912 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
1610 00:18:00.210527 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
1611 00:18:00.226360 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
1612 00:18:00.248813 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
1613 00:18:00.261548 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
1614 00:18:00.308987 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
1615 00:18:00.320862 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
1616 00:18:00.332292 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
1617 00:18:00.354453 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
1618 00:18:00.399096 Starting [0;1;39malsa-restore.serv…- Save/Restore Sound Card State...
1619 00:18:00.409080 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
1620 00:18:00.423517 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyAM…ice[0m - Serial Getty on ttyAML0.
1621 00:18:00.430667 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
1622 00:18:00.441208 [[0;32m OK [0m] Finished [0;1;39malsa-restore.serv…m - Save/Restore Sound Card State.
1623 00:18:00.455673 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
1624 00:18:00.469645 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
1625 00:18:00.479852 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
1626 00:18:00.490586 [[0;32m OK [0m] Reached target [0;1;39msound.target[0m - Sound Card.
1627 00:18:00.535664 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
1628 00:18:00.578982 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
1629 00:18:00.693184
1630 00:18:00.693856 Debian GNU/Linux 12 debian-bookworm-arm64 ttyAML0
1631 00:18:00.694330
1632 00:18:00.700430 debian-bookworm-arm64 login: root (automatic login)
1633 00:18:00.701049
1634 00:18:00.848974 Linux debian-bookworm-arm64 6.12.0-rc5 #1 SMP PREEMPT Thu Oct 31 23:44:52 UTC 2024 aarch64
1635 00:18:00.849635
1636 00:18:00.854729 The programs included with the Debian GNU/Linux system are free software;
1637 00:18:00.864976 the exact distribution terms for each program are described in the
1638 00:18:00.865928 individual files in /usr/share/doc/*/copyright.
1639 00:18:00.866263
1640 00:18:00.871130 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
1641 00:18:00.874618 permitted by applicable law.
1642 00:18:01.550789 Matched prompt #10: / #
1644 00:18:01.551748 Setting prompt string to ['/ #']
1645 00:18:01.552098 end: 2.4.4.1 login-action (duration 00:00:25) [common]
1647 00:18:01.552861 end: 2.4.4 auto-login-action (duration 00:00:25) [common]
1648 00:18:01.553162 start: 2.4.5 expect-shell-connection (timeout 00:03:17) [common]
1649 00:18:01.553404 Setting prompt string to ['/ #']
1650 00:18:01.553620 Forcing a shell prompt, looking for ['/ #']
1652 00:18:01.604194 / #
1653 00:18:01.604750 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
1654 00:18:01.605008 Waiting using forced prompt support (timeout 00:02:30)
1655 00:18:01.610357
1656 00:18:01.610982 end: 2.4.5 expect-shell-connection (duration 00:00:00) [common]
1657 00:18:01.611305 start: 2.4.6 export-device-env (timeout 00:03:17) [common]
1658 00:18:01.611582 Sending with 10 millisecond of delay
1660 00:18:06.601994 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/919150/extract-nfsrootfs-mv_frtrz'
1661 00:18:06.613993 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/919150/extract-nfsrootfs-mv_frtrz'
1662 00:18:06.614844 Sending with 10 millisecond of delay
1664 00:18:08.713448 / # export NFS_SERVER_IP='192.168.6.2'
1665 00:18:08.724469 export NFS_SERVER_IP='192.168.6.2'
1666 00:18:08.725465 end: 2.4.6 export-device-env (duration 00:00:07) [common]
1667 00:18:08.726129 end: 2.4 uboot-commands (duration 00:01:50) [common]
1668 00:18:08.726786 end: 2 uboot-action (duration 00:01:50) [common]
1669 00:18:08.727458 start: 3 lava-test-retry (timeout 00:06:51) [common]
1670 00:18:08.728165 start: 3.1 lava-test-shell (timeout 00:06:51) [common]
1671 00:18:08.728726 Using namespace: common
1673 00:18:08.830030 / # #
1674 00:18:08.830911 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
1675 00:18:08.836524 #
1676 00:18:08.837415 Using /lava-919150
1678 00:18:08.938692 / # export SHELL=/bin/bash
1679 00:18:08.944589 export SHELL=/bin/bash
1681 00:18:09.046264 / # . /lava-919150/environment
1682 00:18:09.050668 . /lava-919150/environment
1684 00:18:09.155420 / # /lava-919150/bin/lava-test-runner /lava-919150/0
1685 00:18:09.156297 Test shell timeout: 10s (minimum of the action and connection timeout)
1686 00:18:09.160584 /lava-919150/bin/lava-test-runner /lava-919150/0
1687 00:18:09.335585 + export TESTRUN_ID=0_timesync-off
1688 00:18:09.341816 + TESTRUN_ID=0_timesync-off
1689 00:18:09.342406 + cd /lava-919150/0/tests/0_timesync-off
1690 00:18:09.342885 ++ cat uuid
1691 00:18:09.347369 + UUID=919150_1.6.2.4.1
1692 00:18:09.347938 + set +x
1693 00:18:09.350021 <LAVA_SIGNAL_STARTRUN 0_timesync-off 919150_1.6.2.4.1>
1694 00:18:09.350851 Received signal: <STARTRUN> 0_timesync-off 919150_1.6.2.4.1
1695 00:18:09.351348 Starting test lava.0_timesync-off (919150_1.6.2.4.1)
1696 00:18:09.351943 Skipping test definition patterns.
1697 00:18:09.355216 + systemctl stop systemd-timesyncd
1698 00:18:09.393298 + set +x
1699 00:18:09.393918 <LAVA_SIGNAL_ENDRUN 0_timesync-off 919150_1.6.2.4.1>
1700 00:18:09.394666 Received signal: <ENDRUN> 0_timesync-off 919150_1.6.2.4.1
1701 00:18:09.395254 Ending use of test pattern.
1702 00:18:09.395724 Ending test lava.0_timesync-off (919150_1.6.2.4.1), duration 0.04
1704 00:18:09.480122 + export TESTRUN_ID=1_kselftest-alsa
1705 00:18:09.486936 + TESTRUN_ID=1_kselftest-alsa
1706 00:18:09.487301 + cd /lava-919150/0/tests/1_kselftest-alsa
1707 00:18:09.487527 ++ cat uuid
1708 00:18:09.492434 + UUID=919150_1.6.2.4.5
1709 00:18:09.492777 + set +x
1710 00:18:09.497927 <LAVA_SIGNAL_STARTRUN 1_kselftest-alsa 919150_1.6.2.4.5>
1711 00:18:09.498245 + cd ./automated/linux/kselftest/
1712 00:18:09.498702 Received signal: <STARTRUN> 1_kselftest-alsa 919150_1.6.2.4.5
1713 00:18:09.498946 Starting test lava.1_kselftest-alsa (919150_1.6.2.4.5)
1714 00:18:09.499211 Skipping test definition patterns.
1715 00:18:09.526405 + ./kselftest.sh -c alsa -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/next/pending-fixes/v6.12-rc5-415-g78b16920c1e2/arm64/defconfig/gcc-12/kselftest.tar.xz -L '' -S /dev/null -b meson-g12b-a311d-libretech-cc -g next -e '' -p /opt/kselftests/mainline/ -n 1 -i 1 -E ''
1716 00:18:09.562288 INFO: install_deps skipped
1717 00:18:09.677421 --2024-11-01 00:18:09-- http://storage.kernelci.org/next/pending-fixes/v6.12-rc5-415-g78b16920c1e2/arm64/defconfig/gcc-12/kselftest.tar.xz
1718 00:18:09.697512 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
1719 00:18:09.834441 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
1720 00:18:09.968222 HTTP request sent, awaiting response... 200 OK
1721 00:18:09.968634 Length: 7112036 (6.8M) [application/octet-stream]
1722 00:18:09.973621 Saving to: 'kselftest_armhf.tar.gz'
1723 00:18:09.973933
1724 00:18:11.358819
kselftest_armhf.tar 0%[ ] 0 --.-KB/s
kselftest_armhf.tar 0%[ ] 47.54K 177KB/s
kselftest_armhf.tar 3%[ ] 218.67K 407KB/s
kselftest_armhf.tar 12%[=> ] 893.67K 1.08MB/s
kselftest_armhf.tar 51%[=========> ] 3.51M 3.26MB/s
kselftest_armhf.tar 100%[===================>] 6.78M 4.92MB/s
kselftest_armhf.tar 100%[===================>] 6.78M 4.92MB/s in 1.4s
1725 00:18:11.359533
1726 00:18:11.465621 2024-11-01 00:18:11 (4.92 MB/s) - 'kselftest_armhf.tar.gz' saved [7112036/7112036]
1727 00:18:11.466380
1728 00:18:20.551368 skiplist:
1729 00:18:20.552052 ========================================
1730 00:18:20.556910 ========================================
1731 00:18:20.592788 alsa:mixer-test
1732 00:18:20.593401 alsa:pcm-test
1733 00:18:20.593824 alsa:test-pcmtest-driver
1734 00:18:20.596797 alsa:utimer-test
1735 00:18:20.611185 ============== Tests to run ===============
1736 00:18:20.611576 alsa:mixer-test
1737 00:18:20.616721 alsa:pcm-test
1738 00:18:20.617063 alsa:test-pcmtest-driver
1739 00:18:20.617436 alsa:utimer-test
1740 00:18:20.624905 ===========End Tests to run ===============
1741 00:18:20.625254 shardfile-alsa pass
1742 00:18:20.748922 <12>[ 43.483154] kselftest: Running tests in alsa
1743 00:18:20.757319 TAP version 13
1744 00:18:20.764929 1..4
1745 00:18:20.793444 # timeout set to 45
1746 00:18:20.793976 # selftests: alsa: mixer-test
1747 00:18:20.968163 # TAP version 13
1748 00:18:20.968780 # # Card 0/LCALTA - LC-ALTA (LC-ALTA)
1749 00:18:20.973480 # 1..427
1750 00:18:20.973961 # ok 1 get_value.LCALTA.60
1751 00:18:20.974385 # # LCALTA.60 TDMOUT_A SRC SEL
1752 00:18:20.979140 # ok 2 name.LCALTA.60
1753 00:18:20.979659 # ok 3 write_default.LCALTA.60
1754 00:18:20.982543 # ok 4 write_valid.LCALTA.60
1755 00:18:20.987937 # ok 5 write_invalid.LCALTA.60
1756 00:18:20.988423 # ok 6 event_missing.LCALTA.60
1757 00:18:20.993678 # ok 7 event_spurious.LCALTA.60
1758 00:18:20.994142 # ok 8 get_value.LCALTA.59
1759 00:18:20.999160 # # LCALTA.59 TDMOUT_B SRC SEL
1760 00:18:20.999612 # ok 9 name.LCALTA.59
1761 00:18:21.004845 # ok 10 write_default.LCALTA.59
1762 00:18:21.005285 # ok 11 write_valid.LCALTA.59
1763 00:18:21.010308 # ok 12 write_invalid.LCALTA.59
1764 00:18:21.010595 # ok 13 event_missing.LCALTA.59
1765 00:18:21.015918 # ok 14 event_spurious.LCALTA.59
1766 00:18:21.016410 # ok 15 get_value.LCALTA.58
1767 00:18:21.021266 # # LCALTA.58 TDMOUT_C SRC SEL
1768 00:18:21.021757 # ok 16 name.LCALTA.58
1769 00:18:21.022185 # ok 17 write_default.LCALTA.58
1770 00:18:21.026697 # ok 18 write_valid.LCALTA.58
1771 00:18:21.027144 # ok 19 write_invalid.LCALTA.58
1772 00:18:21.032247 # ok 20 event_missing.LCALTA.58
1773 00:18:21.032732 # ok 21 event_spurious.LCALTA.58
1774 00:18:21.037832 # ok 22 get_value.LCALTA.57
1775 00:18:21.038342 # # LCALTA.57 TDMIN_A SRC SEL
1776 00:18:21.043383 # ok 23 name.LCALTA.57
1777 00:18:21.043871 # ok 24 write_default.LCALTA.57
1778 00:18:21.048869 # ok 25 write_valid.LCALTA.57
1779 00:18:21.049318 # ok 26 write_invalid.LCALTA.57
1780 00:18:21.054516 # ok 27 event_missing.LCALTA.57
1781 00:18:21.054993 # ok 28 event_spurious.LCALTA.57
1782 00:18:21.060065 # ok 29 get_value.LCALTA.56
1783 00:18:21.060562 # # LCALTA.56 TDMIN_B SRC SEL
1784 00:18:21.065571 # ok 30 name.LCALTA.56
1785 00:18:21.066042 # ok 31 write_default.LCALTA.56
1786 00:18:21.071082 # ok 32 write_valid.LCALTA.56
1787 00:18:21.082240 # ok 33 write_inva<3>[ 43.805413] fe.dai-link-5: ASoC: no backend DAIs enabled for fe.dai-link-5, possibly missing ALSA mixer-based routing or UCM profile
1788 00:18:21.082818 lid.LCALTA.56
1789 00:18:21.087730 # ok 34 event_missing.LCALTA.56
1790 00:18:21.088285 # ok 35 event_spurious.LCALTA.56
1791 00:18:21.093233 # ok 36 get_value.LCALTA.55
1792 00:18:21.093673 # # LCALTA.55 TDMIN_C SRC SEL
1793 00:18:21.098814 # ok 37 name.LCALTA.55
1794 00:18:21.099268 # ok 38 write_default.LCALTA.55
1795 00:18:21.104350 # ok 39 write_valid.LCALTA.55
1796 00:18:21.104788 # ok 40 write_invalid.LCALTA.55
1797 00:18:21.109890 # ok 41 event_missing.LCALTA.55
1798 00:18:21.110376 # ok 42 event_spurious.LCALTA.55
1799 00:18:21.115495 # ok 43 get_value.LCALTA.54
1800 00:18:21.115923 # # LCALTA.54 ACODEC Left DAC Sel
1801 00:18:21.120993 # ok 44 name.LCALTA.54
1802 00:18:21.121429 # ok 45 write_default.LCALTA.54
1803 00:18:21.126523 # ok 46 write_valid.LCALTA.54
1804 00:18:21.126986 # ok 47 write_invalid.LCALTA.54
1805 00:18:21.132106 # ok 48 event_missing.LCALTA.54
1806 00:18:21.132547 # ok 49 event_spurious.LCALTA.54
1807 00:18:21.137671 # ok 50 get_value.LCALTA.53
1808 00:18:21.138096 # # LCALTA.53 ACODEC Right DAC Sel
1809 00:18:21.143171 # ok 51 name.LCALTA.53
1810 00:18:21.143645 # ok 52 write_default.LCALTA.53
1811 00:18:21.148681 # ok 53 write_valid.LCALTA.53
1812 00:18:21.149129 # ok 54 write_invalid.LCALTA.53
1813 00:18:21.154254 # ok 55 event_missing.LCALTA.53
1814 00:18:21.154685 # ok 56 event_spurious.LCALTA.53
1815 00:18:21.159793 # ok 57 get_value.LCALTA.52
1816 00:18:21.160251 # # LCALTA.52 TOACODEC OUT EN Switch
1817 00:18:21.165384 # ok 58 name.LCALTA.52
1818 00:18:21.165882 # ok 59 write_default.LCALTA.52
1819 00:18:21.170905 # ok 60 write_valid.LCALTA.52
1820 00:18:21.171385 # ok 61 write_invalid.LCALTA.52
1821 00:18:21.176503 # ok 62 event_missing.LCALTA.52
1822 00:18:21.176972 # ok 63 event_spurious.LCALTA.52
1823 00:18:21.182026 # ok 64 get_value.LCALTA.51
1824 00:18:21.182493 # # LCALTA.51 TOACODEC SRC
1825 00:18:21.182891 # ok 65 name.LCALTA.51
1826 00:18:21.187527 # ok 66 write_default.LCALTA.51
1827 00:18:21.188037 # ok 67 write_valid.LCALTA.51
1828 00:18:21.193134 # ok 68 write_invalid.LCALTA.51
1829 00:18:21.193634 # ok 69 event_missing.LCALTA.51
1830 00:18:21.198663 # ok 70 event_spurious.LCALTA.51
1831 00:18:21.199161 # ok 71 get_value.LCALTA.50
1832 00:18:21.204228 # # LCALTA.50 TOHDMITX SPDIF SRC
1833 00:18:21.204692 # ok 72 name.LCALTA.50
1834 00:18:21.209734 # ok 73 write_default.LCALTA.50
1835 00:18:21.210184 # ok 74 write_valid.LCALTA.50
1836 00:18:21.215272 # ok 75 write_invalid.LCALTA.50
1837 00:18:21.215708 # ok 76 event_missing.LCALTA.50
1838 00:18:21.220819 # ok 77 event_spurious.LCALTA.50
1839 00:18:21.221256 # ok 78 get_value.LCALTA.49
1840 00:18:21.226365 # # LCALTA.49 TOHDMITX Switch
1841 00:18:21.226835 # ok 79 name.LCALTA.49
1842 00:18:21.231911 # ok 80 write_default.LCALTA.49
1843 00:18:21.232397 # ok 81 write_valid.LCALTA.49
1844 00:18:21.237575 # ok 82 write_invalid.LCALTA.49
1845 00:18:21.238060 # ok 83 event_missing.LCALTA.49
1846 00:18:21.243001 # ok 84 event_spurious.LCALTA.49
1847 00:18:21.243437 # ok 85 get_value.LCALTA.48
1848 00:18:21.248528 # # LCALTA.48 TOHDMITX I2S SRC
1849 00:18:21.248974 # ok 86 name.LCALTA.48
1850 00:18:21.254145 # ok 87 write_default.LCALTA.48
1851 00:18:21.254700 # ok 88 write_valid.LCALTA.48
1852 00:18:21.259658 # ok 89 write_invalid.LCALTA.48
1853 00:18:21.260170 # ok 90 event_missing.LCALTA.48
1854 00:18:21.265249 # ok 91 event_spurious.LCALTA.48
1855 00:18:21.265725 # ok 92 get_value.LCALTA.47
1856 00:18:21.270795 # # LCALTA.47 TODDR_C SRC SEL
1857 00:18:21.271240 # ok 93 name.LCALTA.47
1858 00:18:21.271641 # ok 94 write_default.LCALTA.47
1859 00:18:21.276280 # ok 95 write_valid.LCALTA.47
1860 00:18:21.276757 # ok 96 write_invalid.LCALTA.47
1861 00:18:21.281820 # ok 97 event_missing.LCALTA.47
1862 00:18:21.287371 # ok 98 event_spurious.LCALTA.47
1863 00:18:21.287818 # ok 99 get_value.LCALTA.46
1864 00:18:21.288259 # # LCALTA.46 TODDR_B SRC SEL
1865 00:18:21.292939 # ok 100 name.LCALTA.46
1866 00:18:21.293370 # ok 101 write_default.LCALTA.46
1867 00:18:21.298519 # ok 102 write_valid.LCALTA.46
1868 00:18:21.298942 # ok 103 write_invalid.LCALTA.46
1869 00:18:21.304035 # ok 104 event_missing.LCALTA.46
1870 00:18:21.309561 # ok 105 event_spurious.LCALTA.46
1871 00:18:21.310005 # ok 106 get_value.LCALTA.45
1872 00:18:21.310402 # # LCALTA.45 TODDR_A SRC SEL
1873 00:18:21.315130 # ok 107 name.LCALTA.45
1874 00:18:21.315556 # ok 108 write_default.LCALTA.45
1875 00:18:21.320674 # ok 109 write_valid.LCALTA.45
1876 00:18:21.321102 # ok 110 write_invalid.LCALTA.45
1877 00:18:21.326192 # ok 111 event_missing.LCALTA.45
1878 00:18:21.326612 # ok 112 event_spurious.LCALTA.45
1879 00:18:21.331748 # ok 113 get_value.LCALTA.44
1880 00:18:21.332216 # # LCALTA.44 FRDDR_C SINK 3 SEL
1881 00:18:21.337310 # ok 114 name.LCALTA.44
1882 00:18:21.337772 # ok 115 write_default.LCALTA.44
1883 00:18:21.342858 # ok 116 write_valid.LCALTA.44
1884 00:18:21.343309 # ok 117 write_invalid.LCALTA.44
1885 00:18:21.348372 # ok 118 event_missing.LCALTA.44
1886 00:18:21.353925 # ok 119 event_spurious.LCALTA.44
1887 00:18:21.354374 # ok 120 get_value.LCALTA.43
1888 00:18:21.359539 # # LCALTA.43 FRDDR_C SINK 2 SEL
1889 00:18:21.360013 # ok 121 name.LCALTA.43
1890 00:18:21.360435 # ok 122 write_default.LCALTA.43
1891 00:18:21.365031 # ok 123 write_valid.LCALTA.43
1892 00:18:21.365469 # ok 124 write_invalid.LCALTA.43
1893 00:18:21.370623 # ok 125 event_missing.LCALTA.43
1894 00:18:21.376139 # ok 126 event_spurious.LCALTA.43
1895 00:18:21.376584 # ok 127 get_value.LCALTA.42
1896 00:18:21.381660 # # LCALTA.42 FRDDR_C SINK 1 SEL
1897 00:18:21.382103 # ok 128 name.LCALTA.42
1898 00:18:21.382509 # ok 129 write_default.LCALTA.42
1899 00:18:21.387215 # ok 130 write_valid.LCALTA.42
1900 00:18:21.392766 # ok 131 write_invalid.LCALTA.42
1901 00:18:21.393216 # ok 132 event_missing.LCALTA.42
1902 00:18:21.398370 # ok 133 event_spurious.LCALTA.42
1903 00:18:21.398809 # ok 134 get_value.LCALTA.41
1904 00:18:21.403877 # # LCALTA.41 FRDDR_C SRC 3 EN Switch
1905 00:18:21.404339 # ok 135 name.LCALTA.41
1906 00:18:21.409407 # ok 136 write_default.LCALTA.41
1907 00:18:21.409838 # ok 137 write_valid.LCALTA.41
1908 00:18:21.414958 # ok 138 write_invalid.LCALTA.41
1909 00:18:21.415393 # ok 139 event_missing.LCALTA.41
1910 00:18:21.420543 # ok 140 event_spurious.LCALTA.41
1911 00:18:21.420983 # ok 141 get_value.LCALTA.40
1912 00:18:21.426052 # # LCALTA.40 FRDDR_C SRC 2 EN Switch
1913 00:18:21.426483 # ok 142 name.LCALTA.40
1914 00:18:21.431582 # ok 143 write_default.LCALTA.40
1915 00:18:21.432042 # ok 144 write_valid.LCALTA.40
1916 00:18:21.437145 # ok 145 write_invalid.LCALTA.40
1917 00:18:21.437570 # ok 146 event_missing.LCALTA.40
1918 00:18:21.442710 # ok 147 event_spurious.LCALTA.40
1919 00:18:21.443155 # ok 148 get_value.LCALTA.39
1920 00:18:21.448249 # # LCALTA.39 FRDDR_C SRC 1 EN Switch
1921 00:18:21.448695 # ok 149 name.LCALTA.39
1922 00:18:21.453804 # ok 150 write_default.LCALTA.39
1923 00:18:21.454245 # ok 151 write_valid.LCALTA.39
1924 00:18:21.459329 # ok 152 write_invalid.LCALTA.39
1925 00:18:21.459775 # ok 153 event_missing.LCALTA.39
1926 00:18:21.464856 # ok 154 event_spurious.LCALTA.39
1927 00:18:21.465298 # ok 155 get_value.LCALTA.38
1928 00:18:21.470559 # # LCALTA.38 FRDDR_B SINK 3 SEL
1929 00:18:21.471001 # ok 156 name.LCALTA.38
1930 00:18:21.476000 # ok 157 write_default.LCALTA.38
1931 00:18:21.476499 # ok 158 write_valid.LCALTA.38
1932 00:18:21.481600 # ok 159 write_invalid.LCALTA.38
1933 00:18:21.482098 # ok 160 event_missing.LCALTA.38
1934 00:18:21.487041 # ok 161 event_spurious.LCALTA.38
1935 00:18:21.487467 # ok 162 get_value.LCALTA.37
1936 00:18:21.492639 # # LCALTA.37 FRDDR_B SINK 2 SEL
1937 00:18:21.493070 # ok 163 name.LCALTA.37
1938 00:18:21.498186 # ok 164 write_default.LCALTA.37
1939 00:18:21.498609 # ok 165 write_valid.LCALTA.37
1940 00:18:21.503707 # ok 166 write_invalid.LCALTA.37
1941 00:18:21.504174 # ok 167 event_missing.LCALTA.37
1942 00:18:21.509255 # ok 168 event_spurious.LCALTA.37
1943 00:18:21.509690 # ok 169 get_value.LCALTA.36
1944 00:18:21.514844 # # LCALTA.36 FRDDR_B SINK 1 SEL
1945 00:18:21.515270 # ok 170 name.LCALTA.36
1946 00:18:21.520423 # ok 171 write_default.LCALTA.36
1947 00:18:21.520857 # ok 172 write_valid.LCALTA.36
1948 00:18:21.525903 # ok 173 write_invalid.LCALTA.36
1949 00:18:21.526322 # ok 174 event_missing.LCALTA.36
1950 00:18:21.531557 # ok 175 event_spurious.LCALTA.36
1951 00:18:21.532004 # ok 176 get_value.LCALTA.35
1952 00:18:21.536980 # # LCALTA.35 FRDDR_B SRC 3 EN Switch
1953 00:18:21.537404 # ok 177 name.LCALTA.35
1954 00:18:21.542564 # ok 178 write_default.LCALTA.35
1955 00:18:21.548075 # ok 179 write_valid.LCALTA.35
1956 00:18:21.548507 # ok 180 write_invalid.LCALTA.35
1957 00:18:21.553587 # ok 181 event_missing.LCALTA.35
1958 00:18:21.554009 # ok 182 event_spurious.LCALTA.35
1959 00:18:21.559245 # ok 183 get_value.LCALTA.34
1960 00:18:21.559671 # # LCALTA.34 FRDDR_B SRC 2 EN Switch
1961 00:18:21.564706 # ok 184 name.LCALTA.34
1962 00:18:21.565135 # ok 185 write_default.LCALTA.34
1963 00:18:21.570311 # ok 186 write_valid.LCALTA.34
1964 00:18:21.570734 # ok 187 write_invalid.LCALTA.34
1965 00:18:21.575820 # ok 188 event_missing.LCALTA.34
1966 00:18:21.576264 # ok 189 event_spurious.LCALTA.34
1967 00:18:21.581429 # ok 190 get_value.LCALTA.33
1968 00:18:21.581856 # # LCALTA.33 FRDDR_B SRC 1 EN Switch
1969 00:18:21.586939 # ok 191 name.LCALTA.33
1970 00:18:21.587371 # ok 192 write_default.LCALTA.33
1971 00:18:21.592564 # ok 193 write_valid.LCALTA.33
1972 00:18:21.592993 # ok 194 write_invalid.LCALTA.33
1973 00:18:21.598026 # ok 195 event_missing.LCALTA.33
1974 00:18:21.598447 # ok 196 event_spurious.LCALTA.33
1975 00:18:21.603568 # ok 197 get_value.LCALTA.32
1976 00:18:21.604015 # # LCALTA.32 FRDDR_A SINK 3 SEL
1977 00:18:21.609097 # ok 198 name.LCALTA.32
1978 00:18:21.609513 # ok 199 write_default.LCALTA.32
1979 00:18:21.614647 # ok 200 write_valid.LCALTA.32
1980 00:18:21.615140 # ok 201 write_invalid.LCALTA.32
1981 00:18:21.620204 # ok 202 event_missing.LCALTA.32
1982 00:18:21.620656 # ok 203 event_spurious.LCALTA.32
1983 00:18:21.625741 # ok 204 get_value.LCALTA.31
1984 00:18:21.626178 # # LCALTA.31 FRDDR_A SINK 2 SEL
1985 00:18:21.631281 # ok 205 name.LCALTA.31
1986 00:18:21.631714 # ok 206 write_default.LCALTA.31
1987 00:18:21.636849 # ok 207 write_valid.LCALTA.31
1988 00:18:21.637289 # ok 208 write_invalid.LCALTA.31
1989 00:18:21.642449 # ok 209 event_missing.LCALTA.31
1990 00:18:21.642909 # ok 210 event_spurious.LCALTA.31
1991 00:18:21.647971 # ok 211 get_value.LCALTA.30
1992 00:18:21.648438 # # LCALTA.30 FRDDR_A SINK 1 SEL
1993 00:18:21.653569 # ok 212 name.LCALTA.30
1994 00:18:21.654014 # ok 213 write_default.LCALTA.30
1995 00:18:21.659026 # ok 214 write_valid.LCALTA.30
1996 00:18:21.659474 # ok 215 write_invalid.LCALTA.30
1997 00:18:21.664583 # ok 216 event_missing.LCALTA.30
1998 00:18:21.665022 # ok 217 event_spurious.LCALTA.30
1999 00:18:21.670097 # ok 218 get_value.LCALTA.29
2000 00:18:21.675667 # # LCALTA.29 FRDDR_A SRC 3 EN Switch
2001 00:18:21.676133 # ok 219 name.LCALTA.29
2002 00:18:21.676547 # ok 220 write_default.LCALTA.29
2003 00:18:21.681196 # ok 221 write_valid.LCALTA.29
2004 00:18:21.681628 # ok 222 write_invalid.LCALTA.29
2005 00:18:21.686755 # ok 223 event_missing.LCALTA.29
2006 00:18:21.692363 # ok 224 event_spurious.LCALTA.29
2007 00:18:21.692925 # ok 225 get_value.LCALTA.28
2008 00:18:21.697896 # # LCALTA.28 FRDDR_A SRC 2 EN Switch
2009 00:18:21.698413 # ok 226 name.LCALTA.28
2010 00:18:21.703462 # ok 227 write_default.LCALTA.28
2011 00:18:21.703919 # ok 228 write_valid.LCALTA.28
2012 00:18:21.708935 # ok 229 write_invalid.LCALTA.28
2013 00:18:21.709381 # ok 230 event_missing.LCALTA.28
2014 00:18:21.714590 # ok 231 event_spurious.LCALTA.28
2015 00:18:21.715022 # ok 232 get_value.LCALTA.27
2016 00:18:21.720057 # # LCALTA.27 FRDDR_A SRC 1 EN Switch
2017 00:18:21.720492 # ok 233 name.LCALTA.27
2018 00:18:21.725584 # ok 234 write_default.LCALTA.27
2019 00:18:21.726021 # ok 235 write_valid.LCALTA.27
2020 00:18:21.731130 # ok 236 write_invalid.LCALTA.27
2021 00:18:21.731565 # ok 237 event_missing.LCALTA.27
2022 00:18:21.736736 # ok 238 event_spurious.LCALTA.27
2023 00:18:21.737186 # ok 239 get_value.LCALTA.26
2024 00:18:21.742232 # # LCALTA.26 ELD
2025 00:18:21.742662 # ok 240 name.LCALTA.26
2026 00:18:21.743058 # # ELD is not writeable
2027 00:18:21.747755 # ok 241 # SKIP write_default.LCALTA.26
2028 00:18:21.748228 # # ELD is not writeable
2029 00:18:21.753308 # ok 242 # SKIP write_valid.LCALTA.26
2030 00:18:21.753741 # # ELD is not writeable
2031 00:18:21.758864 # ok 243 # SKIP write_invalid.LCALTA.26
2032 00:18:21.764451 # ok 244 event_missing.LCALTA.26
2033 00:18:21.764888 # ok 245 event_spurious.LCALTA.26
2034 00:18:21.769977 # ok 246 get_value.LCALTA.25
2035 00:18:21.770414 # # LCALTA.25 IEC958 Playback Default
2036 00:18:21.775595 # ok 247 name.LCALTA.25
2037 00:18:21.776051 # ok 248 write_default.LCALTA.25
2038 00:18:21.781055 # ok 249 # SKIP write_valid.LCALTA.25
2039 00:18:21.781480 # ok 250 # SKIP write_invalid.LCALTA.25
2040 00:18:21.786592 # ok 251 event_missing.LCALTA.25
2041 00:18:21.787022 # ok 252 event_spurious.LCALTA.25
2042 00:18:21.792196 # ok 253 get_value.LCALTA.24
2043 00:18:21.792622 # # LCALTA.24 IEC958 Playback Mask
2044 00:18:21.797738 # ok 254 name.LCALTA.24
2045 00:18:21.803193 # # IEC958 Playback Mask is not writeable
2046 00:18:21.803620 # ok 255 # SKIP write_default.LCALTA.24
2047 00:18:21.808732 # # IEC958 Playback Mask is not writeable
2048 00:18:21.809155 # ok 256 # SKIP write_valid.LCALTA.24
2049 00:18:21.814342 # # IEC958 Playback Mask is not writeable
2050 00:18:21.819934 # ok 257 # SKIP write_invalid.LCALTA.24
2051 00:18:21.820431 # ok 258 event_missing.LCALTA.24
2052 00:18:21.825459 # ok 259 event_spurious.LCALTA.24
2053 00:18:21.825887 # ok 260 get_value.LCALTA.23
2054 00:18:21.830993 # # LCALTA.23 Playback Channel Map
2055 00:18:21.831416 # ok 261 name.LCALTA.23
2056 00:18:21.836598 # # Playback Channel Map is not writeable
2057 00:18:21.842098 # ok 262 # SKIP write_default.LCALTA.23
2058 00:18:21.842549 # # Playback Channel Map is not writeable
2059 00:18:21.847600 # ok 263 # SKIP write_valid.LCALTA.23
2060 00:18:21.853161 # # Playback Channel Map is not writeable
2061 00:18:21.853595 # ok 264 # SKIP write_invalid.LCALTA.23
2062 00:18:21.858748 # ok 265 event_missing.LCALTA.23
2063 00:18:21.859174 # ok 266 event_spurious.LCALTA.23
2064 00:18:21.864215 # ok 267 get_value.LCALTA.22
2065 00:18:21.864637 # # LCALTA.22 TDMOUT_A Gain Enable Switch
2066 00:18:21.869800 # ok 268 name.LCALTA.22
2067 00:18:21.870222 # ok 269 write_default.LCALTA.22
2068 00:18:21.875374 # ok 270 write_valid.LCALTA.22
2069 00:18:21.875804 # ok 271 write_invalid.LCALTA.22
2070 00:18:21.880906 # ok 272 event_missing.LCALTA.22
2071 00:18:21.881370 # ok 273 event_spurious.LCALTA.22
2072 00:18:21.886489 # ok 274 get_value.LCALTA.21
2073 00:18:21.886933 # # LCALTA.21 TDMOUT_A Lane 3 Volume
2074 00:18:21.892019 # ok 275 name.LCALTA.21
2075 00:18:21.892462 # ok 276 write_default.LCALTA.21
2076 00:18:21.897610 # ok 277 write_valid.LCALTA.21
2077 00:18:21.898132 # ok 278 write_invalid.LCALTA.21
2078 00:18:21.903042 # ok 279 event_missing.LCALTA.21
2079 00:18:21.908580 # ok 280 event_spurious.LCALTA.21
2080 00:18:21.909077 # ok 281 get_value.LCALTA.20
2081 00:18:21.914233 # # LCALTA.20 TDMOUT_A Lane 2 Volume
2082 00:18:21.914694 # ok 282 name.LCALTA.20
2083 00:18:21.915102 # ok 283 write_default.LCALTA.20
2084 00:18:21.919720 # ok 284 write_valid.LCALTA.20
2085 00:18:21.925248 # ok 285 write_invalid.LCALTA.20
2086 00:18:21.925701 # ok 286 event_missing.LCALTA.20
2087 00:18:21.930821 # ok 287 event_spurious.LCALTA.20
2088 00:18:21.931291 # ok 288 get_value.LCALTA.19
2089 00:18:21.936459 # # LCALTA.19 TDMOUT_A Lane 1 Volume
2090 00:18:21.936992 # ok 289 name.LCALTA.19
2091 00:18:21.941903 # ok 290 write_default.LCALTA.19
2092 00:18:21.942346 # ok 291 write_valid.LCALTA.19
2093 00:18:21.947448 # ok 292 write_invalid.LCALTA.19
2094 00:18:21.947883 # ok 293 event_missing.LCALTA.19
2095 00:18:21.952986 # ok 294 event_spurious.LCALTA.19
2096 00:18:21.953410 # ok 295 get_value.LCALTA.18
2097 00:18:21.958610 # # LCALTA.18 TDMOUT_A Lane 0 Volume
2098 00:18:21.959034 # ok 296 name.LCALTA.18
2099 00:18:21.964082 # ok 297 write_default.LCALTA.18
2100 00:18:21.964530 # ok 298 write_valid.LCALTA.18
2101 00:18:21.969647 # ok 299 write_invalid.LCALTA.18
2102 00:18:21.970080 # ok 300 event_missing.LCALTA.18
2103 00:18:21.975155 # ok 301 event_spurious.LCALTA.18
2104 00:18:21.975592 # ok 302 get_value.LCALTA.17
2105 00:18:21.980756 # # LCALTA.17 TDMOUT_B Gain Enable Switch
2106 00:18:21.981226 # ok 303 name.LCALTA.17
2107 00:18:21.986265 # ok 304 write_default.LCALTA.17
2108 00:18:21.986712 # ok 305 write_valid.LCALTA.17
2109 00:18:21.991799 # ok 306 write_invalid.LCALTA.17
2110 00:18:21.992269 # ok 307 event_missing.LCALTA.17
2111 00:18:21.997344 # ok 308 event_spurious.LCALTA.17
2112 00:18:21.997774 # ok 309 get_value.LCALTA.16
2113 00:18:22.002901 # # LCALTA.16 TDMOUT_B Lane 3 Volume
2114 00:18:22.003372 # ok 310 name.LCALTA.16
2115 00:18:22.008477 # ok 311 write_default.LCALTA.16
2116 00:18:22.008915 # ok 312 write_valid.LCALTA.16
2117 00:18:22.013997 # ok 313 write_invalid.LCALTA.16
2118 00:18:22.019621 # ok 314 event_missing.LCALTA.16
2119 00:18:22.020091 # ok 315 event_spurious.LCALTA.16
2120 00:18:22.025094 # ok 316 get_value.LCALTA.15
2121 00:18:22.025517 # # LCALTA.15 TDMOUT_B Lane 2 Volume
2122 00:18:22.030650 # ok 317 name.LCALTA.15
2123 00:18:22.031068 # ok 318 write_default.LCALTA.15
2124 00:18:22.036194 # ok 319 write_valid.LCALTA.15
2125 00:18:22.036621 # ok 320 write_invalid.LCALTA.15
2126 00:18:22.041796 # ok 321 event_missing.LCALTA.15
2127 00:18:22.042242 # ok 322 event_spurious.LCALTA.15
2128 00:18:22.047299 # ok 323 get_value.LCALTA.14
2129 00:18:22.047736 # # LCALTA.14 TDMOUT_B Lane 1 Volume
2130 00:18:22.052877 # ok 324 name.LCALTA.14
2131 00:18:22.053374 # ok 325 write_default.LCALTA.14
2132 00:18:22.058412 # ok 326 write_valid.LCALTA.14
2133 00:18:22.058856 # ok 327 write_invalid.LCALTA.14
2134 00:18:22.063920 # ok 328 event_missing.LCALTA.14
2135 00:18:22.064388 # ok 329 event_spurious.LCALTA.14
2136 00:18:22.069487 # ok 330 get_value.LCALTA.13
2137 00:18:22.069911 # # LCALTA.13 TDMOUT_B Lane 0 Volume
2138 00:18:22.074994 # ok 331 name.LCALTA.13
2139 00:18:22.075415 # ok 332 write_default.LCALTA.13
2140 00:18:22.080632 # ok 333 write_valid.LCALTA.13
2141 00:18:22.081060 # ok 334 write_invalid.LCALTA.13
2142 00:18:22.086134 # ok 335 event_missing.LCALTA.13
2143 00:18:22.086576 # ok 336 event_spurious.LCALTA.13
2144 00:18:22.091702 # ok 337 get_value.LCALTA.12
2145 00:18:22.092164 # # LCALTA.12 TDMOUT_C Gain Enable Switch
2146 00:18:22.097208 # ok 338 name.LCALTA.12
2147 00:18:22.097641 # ok 339 write_default.LCALTA.12
2148 00:18:22.102784 # ok 340 write_valid.LCALTA.12
2149 00:18:22.103217 # ok 341 write_invalid.LCALTA.12
2150 00:18:22.108334 # ok 342 event_missing.LCALTA.12
2151 00:18:22.113853 # ok 343 event_spurious.LCALTA.12
2152 00:18:22.114289 # ok 344 get_value.LCALTA.11
2153 00:18:22.119415 # # LCALTA.11 TDMOUT_C Lane 3 Volume
2154 00:18:22.119850 # ok 345 name.LCALTA.11
2155 00:18:22.120286 # ok 346 write_default.LCALTA.11
2156 00:18:22.124927 # ok 347 write_valid.LCALTA.11
2157 00:18:22.130525 # ok 348 write_invalid.LCALTA.11
2158 00:18:22.130990 # ok 349 event_missing.LCALTA.11
2159 00:18:22.136052 # ok 350 event_spurious.LCALTA.11
2160 00:18:22.136500 # ok 351 get_value.LCALTA.10
2161 00:18:22.141665 # # LCALTA.10 TDMOUT_C Lane 2 Volume
2162 00:18:22.142101 # ok 352 name.LCALTA.10
2163 00:18:22.147116 # ok 353 write_default.LCALTA.10
2164 00:18:22.147550 # ok 354 write_valid.LCALTA.10
2165 00:18:22.152745 # ok 355 write_invalid.LCALTA.10
2166 00:18:22.153177 # ok 356 event_missing.LCALTA.10
2167 00:18:22.158214 # ok 357 event_spurious.LCALTA.10
2168 00:18:22.158641 # ok 358 get_value.LCALTA.9
2169 00:18:22.163701 # # LCALTA.9 TDMOUT_C Lane 1 Volume
2170 00:18:22.164163 # ok 359 name.LCALTA.9
2171 00:18:22.169207 # ok 360 write_default.LCALTA.9
2172 00:18:22.169633 # ok 361 write_valid.LCALTA.9
2173 00:18:22.174785 # ok 362 write_invalid.LCALTA.9
2174 00:18:22.175212 # ok 363 event_missing.LCALTA.9
2175 00:18:22.180298 # ok 364 event_spurious.LCALTA.9
2176 00:18:22.180730 # ok 365 get_value.LCALTA.8
2177 00:18:22.185857 # # LCALTA.8 TDMOUT_C Lane 0 Volume
2178 00:18:22.186294 # ok 366 name.LCALTA.8
2179 00:18:22.191406 # ok 367 write_default.LCALTA.8
2180 00:18:22.191834 # ok 368 write_valid.LCALTA.8
2181 00:18:22.196937 # ok 369 write_invalid.LCALTA.8
2182 00:18:22.197366 # ok 370 event_missing.LCALTA.8
2183 00:18:22.202630 # ok 371 event_spurious.LCALTA.8
2184 00:18:22.203051 # ok 372 get_value.LCALTA.7
2185 00:18:22.208190 # # LCALTA.7 ACODEC Unmute Ramp Switch
2186 00:18:22.208625 # ok 373 name.LCALTA.7
2187 00:18:22.213725 # ok 374 write_default.LCALTA.7
2188 00:18:22.214184 # ok 375 write_valid.LCALTA.7
2189 00:18:22.219231 # ok 376 write_invalid.LCALTA.7
2190 00:18:22.219677 # ok 377 event_missing.LCALTA.7
2191 00:18:22.224758 # ok 378 event_spurious.LCALTA.7
2192 00:18:22.225205 # ok 379 get_value.LCALTA.6
2193 00:18:22.230302 # # LCALTA.6 ACODEC Mute Ramp Switch
2194 00:18:22.230750 # ok 380 name.LCALTA.6
2195 00:18:22.235890 # ok 381 write_default.LCALTA.6
2196 00:18:22.236362 # ok 382 write_valid.LCALTA.6
2197 00:18:22.241397 # ok 383 write_invalid.LCALTA.6
2198 00:18:22.241858 # ok 384 event_missing.LCALTA.6
2199 00:18:22.246919 # ok 385 event_spurious.LCALTA.6
2200 00:18:22.247367 # ok 386 get_value.LCALTA.5
2201 00:18:22.252482 # # LCALTA.5 ACODEC Volume Ramp Switch
2202 00:18:22.252934 # ok 387 name.LCALTA.5
2203 00:18:22.257993 # ok 388 write_default.LCALTA.5
2204 00:18:22.258430 # ok 389 write_valid.LCALTA.5
2205 00:18:22.263610 # ok 390 write_invalid.LCALTA.5
2206 00:18:22.264069 # ok 391 event_missing.LCALTA.5
2207 00:18:22.269137 # ok 392 event_spurious.LCALTA.5
2208 00:18:22.269574 # ok 393 get_value.LCALTA.4
2209 00:18:22.274668 # # LCALTA.4 ACODEC Ramp Rate
2210 00:18:22.275107 # ok 394 name.LCALTA.4
2211 00:18:22.275511 # ok 395 write_default.LCALTA.4
2212 00:18:22.280202 # ok 396 write_valid.LCALTA.4
2213 00:18:22.280642 # ok 397 write_invalid.LCALTA.4
2214 00:18:22.285767 # ok 398 event_missing.LCALTA.4
2215 00:18:22.291315 # ok 399 event_spurious.LCALTA.4
2216 00:18:22.291755 # ok 400 get_value.LCALTA.3
2217 00:18:22.296873 # # LCALTA.3 ACODEC Playback Volume
2218 00:18:22.297319 # ok 401 name.LCALTA.3
2219 00:18:22.297722 # ok 402 write_default.LCALTA.3
2220 00:18:22.302319 # ok 403 write_valid.LCALTA.3
2221 00:18:22.302755 # ok 404 write_invalid.LCALTA.3
2222 00:18:22.307931 # ok 405 event_missing.LCALTA.3
2223 00:18:22.308393 # ok 406 event_spurious.LCALTA.3
2224 00:18:22.313436 # ok 407 get_value.LCALTA.2
2225 00:18:22.319008 # # LCALTA.2 ACODEC Playback Switch
2226 00:18:22.319473 # ok 408 name.LCALTA.2
2227 00:18:22.319882 # ok 409 write_default.LCALTA.2
2228 00:18:22.324615 # ok 410 write_valid.LCALTA.2
2229 00:18:22.325056 # ok 411 write_invalid.LCALTA.2
2230 00:18:22.330147 # ok 412 event_missing.LCALTA.2
2231 00:18:22.330585 # ok 413 event_spurious.LCALTA.2
2232 00:18:22.335700 # ok 414 get_value.LCALTA.1
2233 00:18:22.341182 # # LCALTA.1 ACODEC Playback Channel Mode
2234 00:18:22.341620 # ok 415 name.LCALTA.1
2235 00:18:22.342022 # ok 416 write_default.LCALTA.1
2236 00:18:22.346774 # ok 417 write_valid.LCALTA.1
2237 00:18:22.347226 # ok 418 write_invalid.LCALTA.1
2238 00:18:22.352321 # ok 419 event_missing.LCALTA.1
2239 00:18:22.357860 # ok 420 event_spurious.LCALTA.1
2240 00:18:22.358304 # ok 421 get_value.LCALTA.0
2241 00:18:22.363413 # # LCALTA.0 TOACODEC Lane Select
2242 00:18:22.363873 # ok 422 name.LCALTA.0
2243 00:18:22.364312 # ok 423 write_default.LCALTA.0
2244 00:18:22.369036 # ok 424 write_valid.LCALTA.0
2245 00:18:22.369557 # ok 425 write_invalid.LCALTA.0
2246 00:18:22.374500 # ok 426 event_missing.LCALTA.0
2247 00:18:22.374964 # ok 427 event_spurious.LCALTA.0
2248 00:18:22.380006 # # Totals: pass:416 fail:0 xfail:0 xpass:0 skip:11 error:0
2249 00:18:22.385582 ok 1 selftests: alsa: mixer-test
2250 00:18:22.386034 # timeout set to 45
2251 00:18:22.391077 # selftests: alsa: pcm-test
2252 00:18:22.391530 # TAP version 13
2253 00:18:22.396625 # # Card 0/LCALTA - LC-ALTA (LC-ALTA)
2254 00:18:22.397082 # # LCALTA.0 - fe.dai-link-0 (*)
2255 00:18:22.402193 # # LCALTA.0 - fe.dai-link-1 (*)
2256 00:18:22.402637 # # LCALTA.0 - fe.dai-link-2 (*)
2257 00:18:22.407813 # # LCALTA.0 - fe.dai-link-3 (*)
2258 00:18:22.408292 # # LCALTA.0 - fe.dai-link-4 (*)
2259 00:18:22.413374 # # LCALTA.0 - fe.dai-link-5 (*)
2260 00:18:22.413836 # 1..42
2261 00:18:22.418912 # # default.time1.LCALTA.5.0.CAPTURE - 8kHz mono large periods
2262 00:18:22.424454 # ok 1 # SKIP default.time1.LCALTA.5.0.CAPTURE
2263 00:18:22.424917 # # snd_pcm_hw_params: Invalid argument
2264 00:18:22.430048 # # default.time2.LCALTA.5.0.CAPTURE - 8kHz stereo large periods
2265 00:18:22.435513 # ok 2 # SKIP default.time2.LCALTA.5.0.CAPTURE
2266 00:18:22.441064 # # snd_pcm_hw_params: Invalid argument
2267 00:18:22.446764 # # default.time3.LCALTA.5.0.CAPTURE - 44.1kHz stereo large periods
2268 00:18:22.452210 # ok 3 # SKIP default.time3.LCALTA.5.0.CAPTURE
2269 00:18:22.452679 # # snd_pcm_hw_params: Invalid argument
2270 00:18:22.457685 # # default.time4.LCALTA.5.0.CAPTURE - 48kHz stereo small periods
2271 00:18:22.463296 # ok 4 # SKIP default.time4.LCALTA.5.0.CAPTURE
2272 00:18:22.468828 # # snd_pcm_hw_params: Invalid argument
2273 00:18:22.474334 # # default.time5.LCALTA.5.0.CAPTURE - 48kHz stereo large periods
2274 00:18:22.474803 # ok 5 # SKIP default.time5.LCALTA.5.0.CAPTURE
2275 00:18:22.479850 # # snd_pcm_hw_params: Invalid argument
2276 00:18:22.485354 # # default.time6.LCALTA.5.0.CAPTURE - 48kHz 6 channel large periods
2277 00:18:22.490934 # ok 6 # SKIP default.time6.LCALTA.5.0.CAPTURE
2278 00:18:22.496453 # # snd_pcm_hw_params: Invalid argument
2279 00:18:22.502041 # # default.time7.LCALTA.5.0.CAPTURE - 96kHz stereo large periods
2280 00:18:22.502508 # ok 7 # SKIP default.time7.LCALTA.5.0.CAPTURE
2281 00:18:22.507668 # # snd_pcm_hw_params: Invalid argument
2282 00:18:22.513116 # # default.time1.LCALTA.4.0.CAPTURE - 8kHz mono large periods
2283 00:18:22.518674 # ok 8 # SKIP default.time1.LCALTA.4.0.CAPTURE
2284 00:18:22.519125 # # snd_pcm_hw_params: Invalid argument
2285 00:18:22.524338 # # default.time2.LCALTA.4.0.CAPTURE - 8kHz stereo large periods
2286 00:18:22.529862 # ok 9 # SKIP default.time2.LCALTA.4.0.CAPTURE
2287 00:18:22.535378 # # snd_pcm_hw_params: Invalid argument
2288 00:18:22.540963 # # default.time3.LCALTA.4.0.CAPTURE - 44.1kHz stereo large periods
2289 00:18:22.546472 # ok 10 # SKIP default.time3.LCALTA.4.0.CAPTURE
2290 00:18:22.546921 # # snd_pcm_hw_params: Invalid argument
2291 00:18:22.552048 # # default.time4.LCALTA.4.0.CAPTURE - 48kHz stereo small periods
2292 00:18:22.557555 # ok 11 # SKIP default.time4.LCALTA.4.0.CAPTURE
2293 00:18:22.563115 # # snd_pcm_hw_params: Invalid argument
2294 00:18:22.568716 # # default.time5.LCALTA.4.0.CAPTURE - 48kHz stereo large periods
2295 00:18:22.574209 # ok 12 # SKIP default.time5.LCALTA.4.0.CAPTURE
2296 00:18:22.574661 # # snd_pcm_hw_params: Invalid argument
2297 00:18:22.579735 # # default.time6.LCALTA.4.0.CAPTURE - 48kHz 6 channel large periods
2298 00:18:22.585301 # ok 13 # SKIP default.time6.LCALTA.4.0.CAPTURE
2299 00:18:22.590878 # # snd_pcm_hw_params: Invalid argument
2300 00:18:22.596447 # # default.time7.LCALTA.4.0.CAPTURE - 96kHz stereo large periods
2301 00:18:22.601981 # ok 14 # SKIP default.time7.LCALTA.4.0.CAPTURE
2302 00:18:22.602429 # # snd_pcm_hw_params: Invalid argument
2303 00:18:22.607504 # # default.time1.LCALTA.3.0.CAPTURE - 8kHz mono large periods
2304 00:18:22.613092 # ok 15 # SKIP default.time1.LCALTA.3.0.CAPTURE
2305 00:18:22.618689 # # snd_pcm_hw_params: Invalid argument
2306 00:18:22.624102 # # default.time2.LCALTA.3.0.CAPTURE - 8kHz stereo large periods
2307 00:18:22.624556 # ok 16 # SKIP default.time2.LCALTA.3.0.CAPTURE
2308 00:18:22.629670 # # snd_pcm_hw_params: Invalid argument
2309 00:18:22.635163 # # default.time3.LCALTA.3.0.CAPTURE - 44.1kHz stereo large periods
2310 00:18:22.640738 # ok 17 # SKIP default.time3.LCALTA.3.0.CAPTURE
2311 00:18:22.646308 # # snd_pcm_hw_params: Invalid argument
2312 00:18:22.651820 # # default.time4.LCALTA.3.0.CAPTURE - 48kHz stereo small periods
2313 00:18:22.652291 # ok 18 # SKIP default.time4.LCALTA.3.0.CAPTURE
2314 00:18:22.657390 # # snd_pcm_hw_params: Invalid argument
2315 00:18:22.662962 # # default.time5.LCALTA.3.0.CAPTURE - 48kHz stereo large periods
2316 00:18:22.668550 # ok 19 # SKIP default.time5.LCALTA.3.0.CAPTURE
2317 00:18:22.669003 # # snd_pcm_hw_params: Invalid argument
2318 00:18:22.679637 # # default.time6.LCALTA.3.0.CAPTURE - 48kHz 6 channel large periods
2319 00:18:22.680135 # ok 20 # SKIP default.time6.LCALTA.3.0.CAPTURE
2320 00:18:22.685024 # # snd_pcm_hw_params: Invalid argument
2321 00:18:22.690609 # # default.time7.LCALTA.3.0.CAPTURE - 96kHz stereo large periods
2322 00:18:22.696199 # ok 21 # SKIP default.time7.LCALTA.3.0.CAPTURE
2323 00:18:22.696751 # # snd_pcm_hw_params: Invalid argument
2324 00:18:22.701858 # # default.time1.LCALTA.2.0.PLAYBACK - 8kHz mono large periods
2325 00:18:22.707379 # ok 22 # SKIP default.time1.LCALTA.2.0.PLAYBACK
2326 00:18:22.712860 # # snd_pcm_hw_params: Invalid argument
2327 00:18:22.718422 # # default.time2.LCALTA.2.0.PLAYBACK - 8kHz stereo large periods
2328 00:18:22.723962 # ok 23 # SKIP default.time2.LCALTA.2.0.PLAYBACK
2329 00:18:22.724430 # # snd_pcm_hw_params: Invalid argument
2330 00:18:22.729564 # # default.time3.LCALTA.2.0.PLAYBACK - 44.1kHz stereo large periods
2331 00:18:22.735088 # ok 24 # SKIP default.time3.LCALTA.2.0.PLAYBACK
2332 00:18:22.740767 # # snd_pcm_hw_params: Invalid argument
2333 00:18:22.746178 # # default.time4.LCALTA.2.0.PLAYBACK - 48kHz stereo small periods
2334 00:18:22.751830 # ok 25 # SKIP default.time4.LCALTA.2.0.PLAYBACK
2335 00:18:22.752297 # # snd_pcm_hw_params: Invalid argument
2336 00:18:22.757276 # # default.time5.LCALTA.2.0.PLAYBACK - 48kHz stereo large periods
2337 00:18:22.762804 # ok 26 # SKIP default.time5.LCALTA.2.0.PLAYBACK
2338 00:18:22.768352 # # snd_pcm_hw_params: Invalid argument
2339 00:18:22.773886 # # default.time6.LCALTA.2.0.PLAYBACK - 48kHz 6 channel large periods
2340 00:18:22.779505 # ok 27 # SKIP default.time6.LCALTA.2.0.PLAYBACK
2341 00:18:22.779929 # # snd_pcm_hw_params: Invalid argument
2342 00:18:22.784998 # # default.time7.LCALTA.2.0.PLAYBACK - 96kHz stereo large periods
2343 00:18:22.790582 # ok 28 # SKIP default.time7.LCALTA.2.0.PLAYBACK
2344 00:18:22.796064 # # snd_pcm_hw_params: Invalid argument
2345 00:18:22.801674 # # default.time1.LCALTA.1.0.PLAYBACK - 8kHz mono large periods
2346 00:18:22.807103 # ok 29 # SKIP default.time1.LCALTA.1.0.PLAYBACK
2347 00:18:22.807529 # # snd_pcm_hw_params: Invalid argument
2348 00:18:22.812710 # # default.time2.LCALTA.1.0.PLAYBACK - 8kHz stereo large periods
2349 00:18:22.818267 # ok 30 # SKIP default.time2.LCALTA.1.0.PLAYBACK
2350 00:18:22.823791 # # snd_pcm_hw_params: Invalid argument
2351 00:18:22.829330 # # default.time3.LCALTA.1.0.PLAYBACK - 44.1kHz stereo large periods
2352 00:18:22.834854 # ok 31 # SKIP default.time3.LCALTA.1.0.PLAYBACK
2353 00:18:22.835282 # # snd_pcm_hw_params: Invalid argument
2354 00:18:22.840448 # # default.time4.LCALTA.1.0.PLAYBACK - 48kHz stereo small periods
2355 00:18:22.845901 # ok 32 # SKIP default.time4.LCALTA.1.0.PLAYBACK
2356 00:18:22.851505 # # snd_pcm_hw_params: Invalid argument
2357 00:18:22.857020 # # default.time5.LCALTA.1.0.PLAYBACK - 48kHz stereo large periods
2358 00:18:22.862674 # ok 33 # SKIP default.time5.LCALTA.1.0.PLAYBACK
2359 00:18:22.863109 # # snd_pcm_hw_params: Invalid argument
2360 00:18:22.868215 # # default.time6.LCALTA.1.0.PLAYBACK - 48kHz 6 channel large periods
2361 00:18:22.873757 # ok 34 # SKIP default.time6.LCALTA.1.0.PLAYBACK
2362 00:18:22.879294 # # snd_pcm_hw_params: Invalid argument
2363 00:18:22.884797 # # default.time7.LCALTA.1.0.PLAYBACK - 96kHz stereo large periods
2364 00:18:22.890326 # ok 35 # SKIP default.time7.LCALTA.1.0.PLAYBACK
2365 00:18:22.890643 # # snd_pcm_hw_params: Invalid argument
2366 00:18:22.895844 # # default.time1.LCALTA.0.0.PLAYBACK - 8kHz mono large periods
2367 00:18:22.901417 # ok 36 # SKIP default.time1.LCALTA.0.0.PLAYBACK
2368 00:18:22.906964 # # snd_pcm_hw_params: Invalid argument
2369 00:18:22.912596 # # default.time2.LCALTA.0.0.PLAYBACK - 8kHz stereo large periods
2370 00:18:22.912902 # ok 37 # SKIP default.time2.LCALTA.0.0.PLAYBACK
2371 00:18:22.918057 # # snd_pcm_hw_params: Invalid argument
2372 00:18:22.923640 # # default.time3.LCALTA.0.0.PLAYBACK - 44.1kHz stereo large periods
2373 00:18:22.929077 # ok 38 # SKIP default.time3.LCALTA.0.0.PLAYBACK
2374 00:18:22.934615 # # snd_pcm_hw_params: Invalid argument
2375 00:18:22.940185 # # default.time4.LCALTA.0.0.PLAYBACK - 48kHz stereo small periods
2376 00:18:22.940480 # ok 39 # SKIP default.time4.LCALTA.0.0.PLAYBACK
2377 00:18:22.945709 # # snd_pcm_hw_params: Invalid argument
2378 00:18:22.951358 # # default.time5.LCALTA.0.0.PLAYBACK - 48kHz stereo large periods
2379 00:18:22.956903 # ok 40 # SKIP default.time5.LCALTA.0.0.PLAYBACK
2380 00:18:22.962459 # # snd_pcm_hw_params: Invalid argument
2381 00:18:22.968007 # # default.time6.LCALTA.0.0.PLAYBACK - 48kHz 6 channel large periods
2382 00:18:22.968284 # ok 41 # SKIP default.time6.LCALTA.0.0.PLAYBACK
2383 00:18:22.973724 # # snd_pcm_hw_params: Invalid argument
2384 00:18:22.979272 # # default.time7.LCALTA.0.0.PLAYBACK - 96kHz stereo large periods
2385 00:18:22.984850 # ok 42 # SKIP default.time7.LCALTA.0.0.PLAYBACK
2386 00:18:22.990340 # # snd_pcm_hw_params: Invalid argument
2387 00:18:22.995881 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:42 error:0
2388 00:18:22.996480 ok 2 selftests: alsa: pcm-test
2389 00:18:22.996945 # timeout set to 45
2390 00:18:23.001448 # selftests: alsa: test-pcmtest-driver
2391 00:18:23.002013 # TAP version 13
2392 00:18:23.002467 # 1..5
2393 00:18:23.007013 # # Starting 5 tests from 1 test cases.
2394 00:18:23.012510 # # RUN pcmtest.playback ...
2395 00:18:23.018040 # # SKIP Can't read patterns. Probably, module isn't loaded
2396 00:18:23.018596 # # OK pcmtest.playback
2397 00:18:23.029116 # ok 1 pcmtest.playback # SKIP Can't read patterns. Probably, module isn't loaded
2398 00:18:23.029711 # # RUN pcmtest.capture ...
2399 00:18:23.034814 # # SKIP Can't read patterns. Probably, module isn't loaded
2400 00:18:23.040370 # # OK pcmtest.capture
2401 00:18:23.045901 # ok 2 pcmtest.capture # SKIP Can't read patterns. Probably, module isn't loaded
2402 00:18:23.051376 # # RUN pcmtest.ni_capture ...
2403 00:18:23.057013 # # SKIP Can't read patterns. Probably, module isn't loaded
2404 00:18:23.062414 # # OK pcmtest.ni_capture
2405 00:18:23.068008 # ok 3 pcmtest.ni_capture # SKIP Can't read patterns. Probably, module isn't loaded
2406 00:18:23.073544 # # RUN pcmtest.ni_playback ...
2407 00:18:23.079059 # # SKIP Can't read patterns. Probably, module isn't loaded
2408 00:18:23.079616 # # OK pcmtest.ni_playback
2409 00:18:23.090139 # ok 4 pcmtest.ni_playback # SKIP Can't read patterns. Probably, module isn't loaded
2410 00:18:23.090721 # # RUN pcmtest.reset_ioctl ...
2411 00:18:23.095776 # # SKIP Can't read patterns. Probably, module isn't loaded
2412 00:18:23.101272 # # OK pcmtest.reset_ioctl
2413 00:18:23.106847 # ok 5 pcmtest.reset_ioctl # SKIP Can't read patterns. Probably, module isn't loaded
2414 00:18:23.112375 # # PASSED: 5 / 5 tests passed.
2415 00:18:23.117938 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:5 error:0
2416 00:18:23.123418 ok 3 selftests: alsa: test-pcmtest-driver
2417 00:18:23.123964 # timeout set to 45
2418 00:18:23.124502 # selftests: alsa: utimer-test
2419 00:18:23.129037 # TAP version 13
2420 00:18:23.129565 # 1..2
2421 00:18:23.130004 # # Starting 2 tests from 2 test cases.
2422 00:18:23.134522 # # RUN global.wrong_timers_test ...
2423 00:18:23.140093 # # OK global.wrong_timers_test
2424 00:18:23.140621 # ok 1 global.wrong_timers_test
2425 00:18:23.145656 # # RUN timer_f.utimer ...
2426 00:18:23.156716 # # utimer-test.c:55:utimer:Expected ioctl(timer_dev_fd, SNDRV_TIMER_IOCTL_CREATE, self->utimer_info) (-1) == 0 (0)
2427 00:18:23.162303 # # utimer: Test terminated by assertion
2428 00:18:23.162850 # # FAIL timer_f.utimer
2429 00:18:23.163296 # not ok 2 timer_f.utimer
2430 00:18:23.167896 # # FAILED: 1 / 2 tests passed.
2431 00:18:23.173398 # # Totals: pass:1 fail:1 xfail:0 xpass:0 skip:0 error:0
2432 00:18:23.176451 not ok 4 selftests: alsa: utimer-test # exit=1
2433 00:18:23.727404 alsa_mixer-test_get_value_LCALTA_60 pass
2434 00:18:23.732905 alsa_mixer-test_name_LCALTA_60 pass
2435 00:18:23.733454 alsa_mixer-test_write_default_LCALTA_60 pass
2436 00:18:23.738382 alsa_mixer-test_write_valid_LCALTA_60 pass
2437 00:18:23.741917 alsa_mixer-test_write_invalid_LCALTA_60 pass
2438 00:18:23.747423 alsa_mixer-test_event_missing_LCALTA_60 pass
2439 00:18:23.752956 alsa_mixer-test_event_spurious_LCALTA_60 pass
2440 00:18:23.753512 alsa_mixer-test_get_value_LCALTA_59 pass
2441 00:18:23.758479 alsa_mixer-test_name_LCALTA_59 pass
2442 00:18:23.764050 alsa_mixer-test_write_default_LCALTA_59 pass
2443 00:18:23.764608 alsa_mixer-test_write_valid_LCALTA_59 pass
2444 00:18:23.769578 alsa_mixer-test_write_invalid_LCALTA_59 pass
2445 00:18:23.775133 alsa_mixer-test_event_missing_LCALTA_59 pass
2446 00:18:23.775681 alsa_mixer-test_event_spurious_LCALTA_59 pass
2447 00:18:23.780663 alsa_mixer-test_get_value_LCALTA_58 pass
2448 00:18:23.786218 alsa_mixer-test_name_LCALTA_58 pass
2449 00:18:23.786751 alsa_mixer-test_write_default_LCALTA_58 pass
2450 00:18:23.791737 alsa_mixer-test_write_valid_LCALTA_58 pass
2451 00:18:23.797296 alsa_mixer-test_write_invalid_LCALTA_58 pass
2452 00:18:23.802879 alsa_mixer-test_event_missing_LCALTA_58 pass
2453 00:18:23.803407 alsa_mixer-test_event_spurious_LCALTA_58 pass
2454 00:18:23.808369 alsa_mixer-test_get_value_LCALTA_57 pass
2455 00:18:23.814041 alsa_mixer-test_name_LCALTA_57 pass
2456 00:18:23.814588 alsa_mixer-test_write_default_LCALTA_57 pass
2457 00:18:23.819640 alsa_mixer-test_write_valid_LCALTA_57 pass
2458 00:18:23.825168 alsa_mixer-test_write_invalid_LCALTA_57 pass
2459 00:18:23.825706 alsa_mixer-test_event_missing_LCALTA_57 pass
2460 00:18:23.830677 alsa_mixer-test_event_spurious_LCALTA_57 pass
2461 00:18:23.836258 alsa_mixer-test_get_value_LCALTA_56 pass
2462 00:18:23.836797 alsa_mixer-test_name_LCALTA_56 pass
2463 00:18:23.841786 alsa_mixer-test_write_default_LCALTA_56 pass
2464 00:18:23.847310 alsa_mixer-test_write_valid_LCALTA_56 pass
2465 00:18:23.847868 alsa_mixer-test_write_invalid_LCALTA_56 pass
2466 00:18:23.852886 alsa_mixer-test_event_missing_LCALTA_56 pass
2467 00:18:23.858418 alsa_mixer-test_event_spurious_LCALTA_56 pass
2468 00:18:23.864072 alsa_mixer-test_get_value_LCALTA_55 pass
2469 00:18:23.864628 alsa_mixer-test_name_LCALTA_55 pass
2470 00:18:23.869538 alsa_mixer-test_write_default_LCALTA_55 pass
2471 00:18:23.875062 alsa_mixer-test_write_valid_LCALTA_55 pass
2472 00:18:23.875612 alsa_mixer-test_write_invalid_LCALTA_55 pass
2473 00:18:23.880584 alsa_mixer-test_event_missing_LCALTA_55 pass
2474 00:18:23.886169 alsa_mixer-test_event_spurious_LCALTA_55 pass
2475 00:18:23.886726 alsa_mixer-test_get_value_LCALTA_54 pass
2476 00:18:23.891681 alsa_mixer-test_name_LCALTA_54 pass
2477 00:18:23.897198 alsa_mixer-test_write_default_LCALTA_54 pass
2478 00:18:23.897737 alsa_mixer-test_write_valid_LCALTA_54 pass
2479 00:18:23.902799 alsa_mixer-test_write_invalid_LCALTA_54 pass
2480 00:18:23.908480 alsa_mixer-test_event_missing_LCALTA_54 pass
2481 00:18:23.913907 alsa_mixer-test_event_spurious_LCALTA_54 pass
2482 00:18:23.914477 alsa_mixer-test_get_value_LCALTA_53 pass
2483 00:18:23.919439 alsa_mixer-test_name_LCALTA_53 pass
2484 00:18:23.925047 alsa_mixer-test_write_default_LCALTA_53 pass
2485 00:18:23.925604 alsa_mixer-test_write_valid_LCALTA_53 pass
2486 00:18:23.930557 alsa_mixer-test_write_invalid_LCALTA_53 pass
2487 00:18:23.936105 alsa_mixer-test_event_missing_LCALTA_53 pass
2488 00:18:23.936661 alsa_mixer-test_event_spurious_LCALTA_53 pass
2489 00:18:23.941642 alsa_mixer-test_get_value_LCALTA_52 pass
2490 00:18:23.947218 alsa_mixer-test_name_LCALTA_52 pass
2491 00:18:23.947767 alsa_mixer-test_write_default_LCALTA_52 pass
2492 00:18:23.952766 alsa_mixer-test_write_valid_LCALTA_52 pass
2493 00:18:23.958285 alsa_mixer-test_write_invalid_LCALTA_52 pass
2494 00:18:23.958837 alsa_mixer-test_event_missing_LCALTA_52 pass
2495 00:18:23.963818 alsa_mixer-test_event_spurious_LCALTA_52 pass
2496 00:18:23.969337 alsa_mixer-test_get_value_LCALTA_51 pass
2497 00:18:23.969885 alsa_mixer-test_name_LCALTA_51 pass
2498 00:18:23.974875 alsa_mixer-test_write_default_LCALTA_51 pass
2499 00:18:23.980448 alsa_mixer-test_write_valid_LCALTA_51 pass
2500 00:18:23.986044 alsa_mixer-test_write_invalid_LCALTA_51 pass
2501 00:18:23.986577 alsa_mixer-test_event_missing_LCALTA_51 pass
2502 00:18:23.991525 alsa_mixer-test_event_spurious_LCALTA_51 pass
2503 00:18:23.997084 alsa_mixer-test_get_value_LCALTA_50 pass
2504 00:18:23.997634 alsa_mixer-test_name_LCALTA_50 pass
2505 00:18:24.002641 alsa_mixer-test_write_default_LCALTA_50 pass
2506 00:18:24.008226 alsa_mixer-test_write_valid_LCALTA_50 pass
2507 00:18:24.008765 alsa_mixer-test_write_invalid_LCALTA_50 pass
2508 00:18:24.013705 alsa_mixer-test_event_missing_LCALTA_50 pass
2509 00:18:24.019299 alsa_mixer-test_event_spurious_LCALTA_50 pass
2510 00:18:24.019827 alsa_mixer-test_get_value_LCALTA_49 pass
2511 00:18:24.024835 alsa_mixer-test_name_LCALTA_49 pass
2512 00:18:24.030349 alsa_mixer-test_write_default_LCALTA_49 pass
2513 00:18:24.030877 alsa_mixer-test_write_valid_LCALTA_49 pass
2514 00:18:24.035916 alsa_mixer-test_write_invalid_LCALTA_49 pass
2515 00:18:24.041449 alsa_mixer-test_event_missing_LCALTA_49 pass
2516 00:18:24.047011 alsa_mixer-test_event_spurious_LCALTA_49 pass
2517 00:18:24.047535 alsa_mixer-test_get_value_LCALTA_48 pass
2518 00:18:24.052524 alsa_mixer-test_name_LCALTA_48 pass
2519 00:18:24.058086 alsa_mixer-test_write_default_LCALTA_48 pass
2520 00:18:24.058623 alsa_mixer-test_write_valid_LCALTA_48 pass
2521 00:18:24.063663 alsa_mixer-test_write_invalid_LCALTA_48 pass
2522 00:18:24.069198 alsa_mixer-test_event_missing_LCALTA_48 pass
2523 00:18:24.069737 alsa_mixer-test_event_spurious_LCALTA_48 pass
2524 00:18:24.074714 alsa_mixer-test_get_value_LCALTA_47 pass
2525 00:18:24.080318 alsa_mixer-test_name_LCALTA_47 pass
2526 00:18:24.080864 alsa_mixer-test_write_default_LCALTA_47 pass
2527 00:18:24.085935 alsa_mixer-test_write_valid_LCALTA_47 pass
2528 00:18:24.091343 alsa_mixer-test_write_invalid_LCALTA_47 pass
2529 00:18:24.097018 alsa_mixer-test_event_missing_LCALTA_47 pass
2530 00:18:24.097551 alsa_mixer-test_event_spurious_LCALTA_47 pass
2531 00:18:24.102486 alsa_mixer-test_get_value_LCALTA_46 pass
2532 00:18:24.103017 alsa_mixer-test_name_LCALTA_46 pass
2533 00:18:24.108074 alsa_mixer-test_write_default_LCALTA_46 pass
2534 00:18:24.113574 alsa_mixer-test_write_valid_LCALTA_46 pass
2535 00:18:24.119106 alsa_mixer-test_write_invalid_LCALTA_46 pass
2536 00:18:24.119643 alsa_mixer-test_event_missing_LCALTA_46 pass
2537 00:18:24.124633 alsa_mixer-test_event_spurious_LCALTA_46 pass
2538 00:18:24.130179 alsa_mixer-test_get_value_LCALTA_45 pass
2539 00:18:24.130711 alsa_mixer-test_name_LCALTA_45 pass
2540 00:18:24.135751 alsa_mixer-test_write_default_LCALTA_45 pass
2541 00:18:24.141316 alsa_mixer-test_write_valid_LCALTA_45 pass
2542 00:18:24.141864 alsa_mixer-test_write_invalid_LCALTA_45 pass
2543 00:18:24.146944 alsa_mixer-test_event_missing_LCALTA_45 pass
2544 00:18:24.152404 alsa_mixer-test_event_spurious_LCALTA_45 pass
2545 00:18:24.158071 alsa_mixer-test_get_value_LCALTA_44 pass
2546 00:18:24.158619 alsa_mixer-test_name_LCALTA_44 pass
2547 00:18:24.163486 alsa_mixer-test_write_default_LCALTA_44 pass
2548 00:18:24.169072 alsa_mixer-test_write_valid_LCALTA_44 pass
2549 00:18:24.169621 alsa_mixer-test_write_invalid_LCALTA_44 pass
2550 00:18:24.174574 alsa_mixer-test_event_missing_LCALTA_44 pass
2551 00:18:24.180149 alsa_mixer-test_event_spurious_LCALTA_44 pass
2552 00:18:24.180690 alsa_mixer-test_get_value_LCALTA_43 pass
2553 00:18:24.185684 alsa_mixer-test_name_LCALTA_43 pass
2554 00:18:24.191206 alsa_mixer-test_write_default_LCALTA_43 pass
2555 00:18:24.191741 alsa_mixer-test_write_valid_LCALTA_43 pass
2556 00:18:24.196754 alsa_mixer-test_write_invalid_LCALTA_43 pass
2557 00:18:24.202307 alsa_mixer-test_event_missing_LCALTA_43 pass
2558 00:18:24.202832 alsa_mixer-test_event_spurious_LCALTA_43 pass
2559 00:18:24.207816 alsa_mixer-test_get_value_LCALTA_42 pass
2560 00:18:24.213450 alsa_mixer-test_name_LCALTA_42 pass
2561 00:18:24.213986 alsa_mixer-test_write_default_LCALTA_42 pass
2562 00:18:24.219033 alsa_mixer-test_write_valid_LCALTA_42 pass
2563 00:18:24.224464 alsa_mixer-test_write_invalid_LCALTA_42 pass
2564 00:18:24.230031 alsa_mixer-test_event_missing_LCALTA_42 pass
2565 00:18:24.230553 alsa_mixer-test_event_spurious_LCALTA_42 pass
2566 00:18:24.235583 alsa_mixer-test_get_value_LCALTA_41 pass
2567 00:18:24.241135 alsa_mixer-test_name_LCALTA_41 pass
2568 00:18:24.241661 alsa_mixer-test_write_default_LCALTA_41 pass
2569 00:18:24.246690 alsa_mixer-test_write_valid_LCALTA_41 pass
2570 00:18:24.252274 alsa_mixer-test_write_invalid_LCALTA_41 pass
2571 00:18:24.252825 alsa_mixer-test_event_missing_LCALTA_41 pass
2572 00:18:24.257796 alsa_mixer-test_event_spurious_LCALTA_41 pass
2573 00:18:24.263338 alsa_mixer-test_get_value_LCALTA_40 pass
2574 00:18:24.263882 alsa_mixer-test_name_LCALTA_40 pass
2575 00:18:24.268924 alsa_mixer-test_write_default_LCALTA_40 pass
2576 00:18:24.274449 alsa_mixer-test_write_valid_LCALTA_40 pass
2577 00:18:24.274983 alsa_mixer-test_write_invalid_LCALTA_40 pass
2578 00:18:24.280091 alsa_mixer-test_event_missing_LCALTA_40 pass
2579 00:18:24.285529 alsa_mixer-test_event_spurious_LCALTA_40 pass
2580 00:18:24.291061 alsa_mixer-test_get_value_LCALTA_39 pass
2581 00:18:24.291590 alsa_mixer-test_name_LCALTA_39 pass
2582 00:18:24.296615 alsa_mixer-test_write_default_LCALTA_39 pass
2583 00:18:24.302132 alsa_mixer-test_write_valid_LCALTA_39 pass
2584 00:18:24.302668 alsa_mixer-test_write_invalid_LCALTA_39 pass
2585 00:18:24.307674 alsa_mixer-test_event_missing_LCALTA_39 pass
2586 00:18:24.313245 alsa_mixer-test_event_spurious_LCALTA_39 pass
2587 00:18:24.313799 alsa_mixer-test_get_value_LCALTA_38 pass
2588 00:18:24.318910 alsa_mixer-test_name_LCALTA_38 pass
2589 00:18:24.324413 alsa_mixer-test_write_default_LCALTA_38 pass
2590 00:18:24.324995 alsa_mixer-test_write_valid_LCALTA_38 pass
2591 00:18:24.330052 alsa_mixer-test_write_invalid_LCALTA_38 pass
2592 00:18:24.335380 alsa_mixer-test_event_missing_LCALTA_38 pass
2593 00:18:24.341012 alsa_mixer-test_event_spurious_LCALTA_38 pass
2594 00:18:24.341442 alsa_mixer-test_get_value_LCALTA_37 pass
2595 00:18:24.346500 alsa_mixer-test_name_LCALTA_37 pass
2596 00:18:24.352034 alsa_mixer-test_write_default_LCALTA_37 pass
2597 00:18:24.352452 alsa_mixer-test_write_valid_LCALTA_37 pass
2598 00:18:24.357550 alsa_mixer-test_write_invalid_LCALTA_37 pass
2599 00:18:24.363130 alsa_mixer-test_event_missing_LCALTA_37 pass
2600 00:18:24.363686 alsa_mixer-test_event_spurious_LCALTA_37 pass
2601 00:18:24.368659 alsa_mixer-test_get_value_LCALTA_36 pass
2602 00:18:24.375611 alsa_mixer-test_name_LCALTA_36 pass
2603 00:18:24.376058 alsa_mixer-test_write_default_LCALTA_36 pass
2604 00:18:24.379808 alsa_mixer-test_write_valid_LCALTA_36 pass
2605 00:18:24.386165 alsa_mixer-test_write_invalid_LCALTA_36 pass
2606 00:18:24.386565 alsa_mixer-test_event_missing_LCALTA_36 pass
2607 00:18:24.390982 alsa_mixer-test_event_spurious_LCALTA_36 pass
2608 00:18:24.396469 alsa_mixer-test_get_value_LCALTA_35 pass
2609 00:18:24.396980 alsa_mixer-test_name_LCALTA_35 pass
2610 00:18:24.402008 alsa_mixer-test_write_default_LCALTA_35 pass
2611 00:18:24.407578 alsa_mixer-test_write_valid_LCALTA_35 pass
2612 00:18:24.413085 alsa_mixer-test_write_invalid_LCALTA_35 pass
2613 00:18:24.413679 alsa_mixer-test_event_missing_LCALTA_35 pass
2614 00:18:24.418645 alsa_mixer-test_event_spurious_LCALTA_35 pass
2615 00:18:24.424205 alsa_mixer-test_get_value_LCALTA_34 pass
2616 00:18:24.424789 alsa_mixer-test_name_LCALTA_34 pass
2617 00:18:24.429724 alsa_mixer-test_write_default_LCALTA_34 pass
2618 00:18:24.435279 alsa_mixer-test_write_valid_LCALTA_34 pass
2619 00:18:24.435869 alsa_mixer-test_write_invalid_LCALTA_34 pass
2620 00:18:24.440868 alsa_mixer-test_event_missing_LCALTA_34 pass
2621 00:18:24.446373 alsa_mixer-test_event_spurious_LCALTA_34 pass
2622 00:18:24.446977 alsa_mixer-test_get_value_LCALTA_33 pass
2623 00:18:24.452002 alsa_mixer-test_name_LCALTA_33 pass
2624 00:18:24.457502 alsa_mixer-test_write_default_LCALTA_33 pass
2625 00:18:24.458093 alsa_mixer-test_write_valid_LCALTA_33 pass
2626 00:18:24.463103 alsa_mixer-test_write_invalid_LCALTA_33 pass
2627 00:18:24.468671 alsa_mixer-test_event_missing_LCALTA_33 pass
2628 00:18:24.474153 alsa_mixer-test_event_spurious_LCALTA_33 pass
2629 00:18:24.474818 alsa_mixer-test_get_value_LCALTA_32 pass
2630 00:18:24.479797 alsa_mixer-test_name_LCALTA_32 pass
2631 00:18:24.485392 alsa_mixer-test_write_default_LCALTA_32 pass
2632 00:18:24.486393 alsa_mixer-test_write_valid_LCALTA_32 pass
2633 00:18:24.491509 alsa_mixer-test_write_invalid_LCALTA_32 pass
2634 00:18:24.496447 alsa_mixer-test_event_missing_LCALTA_32 pass
2635 00:18:24.497340 alsa_mixer-test_event_spurious_LCALTA_32 pass
2636 00:18:24.502112 alsa_mixer-test_get_value_LCALTA_31 pass
2637 00:18:24.507408 alsa_mixer-test_name_LCALTA_31 pass
2638 00:18:24.507892 alsa_mixer-test_write_default_LCALTA_31 pass
2639 00:18:24.512939 alsa_mixer-test_write_valid_LCALTA_31 pass
2640 00:18:24.518428 alsa_mixer-test_write_invalid_LCALTA_31 pass
2641 00:18:24.524042 alsa_mixer-test_event_missing_LCALTA_31 pass
2642 00:18:24.524552 alsa_mixer-test_event_spurious_LCALTA_31 pass
2643 00:18:24.529592 alsa_mixer-test_get_value_LCALTA_30 pass
2644 00:18:24.530106 alsa_mixer-test_name_LCALTA_30 pass
2645 00:18:24.535089 alsa_mixer-test_write_default_LCALTA_30 pass
2646 00:18:24.540602 alsa_mixer-test_write_valid_LCALTA_30 pass
2647 00:18:24.546040 alsa_mixer-test_write_invalid_LCALTA_30 pass
2648 00:18:24.546359 alsa_mixer-test_event_missing_LCALTA_30 pass
2649 00:18:24.551566 alsa_mixer-test_event_spurious_LCALTA_30 pass
2650 00:18:24.557131 alsa_mixer-test_get_value_LCALTA_29 pass
2651 00:18:24.557423 alsa_mixer-test_name_LCALTA_29 pass
2652 00:18:24.562657 alsa_mixer-test_write_default_LCALTA_29 pass
2653 00:18:24.568263 alsa_mixer-test_write_valid_LCALTA_29 pass
2654 00:18:24.568768 alsa_mixer-test_write_invalid_LCALTA_29 pass
2655 00:18:24.573851 alsa_mixer-test_event_missing_LCALTA_29 pass
2656 00:18:24.579385 alsa_mixer-test_event_spurious_LCALTA_29 pass
2657 00:18:24.584991 alsa_mixer-test_get_value_LCALTA_28 pass
2658 00:18:24.585520 alsa_mixer-test_name_LCALTA_28 pass
2659 00:18:24.590449 alsa_mixer-test_write_default_LCALTA_28 pass
2660 00:18:24.596085 alsa_mixer-test_write_valid_LCALTA_28 pass
2661 00:18:24.596619 alsa_mixer-test_write_invalid_LCALTA_28 pass
2662 00:18:24.601550 alsa_mixer-test_event_missing_LCALTA_28 pass
2663 00:18:24.607130 alsa_mixer-test_event_spurious_LCALTA_28 pass
2664 00:18:24.607661 alsa_mixer-test_get_value_LCALTA_27 pass
2665 00:18:24.612621 alsa_mixer-test_name_LCALTA_27 pass
2666 00:18:24.618156 alsa_mixer-test_write_default_LCALTA_27 pass
2667 00:18:24.618673 alsa_mixer-test_write_valid_LCALTA_27 pass
2668 00:18:24.623716 alsa_mixer-test_write_invalid_LCALTA_27 pass
2669 00:18:24.629263 alsa_mixer-test_event_missing_LCALTA_27 pass
2670 00:18:24.629787 alsa_mixer-test_event_spurious_LCALTA_27 pass
2671 00:18:24.634844 alsa_mixer-test_get_value_LCALTA_26 pass
2672 00:18:24.640360 alsa_mixer-test_name_LCALTA_26 pass
2673 00:18:24.640889 alsa_mixer-test_write_default_LCALTA_26 skip
2674 00:18:24.645982 alsa_mixer-test_write_valid_LCALTA_26 skip
2675 00:18:24.651437 alsa_mixer-test_write_invalid_LCALTA_26 skip
2676 00:18:24.657062 alsa_mixer-test_event_missing_LCALTA_26 pass
2677 00:18:24.657587 alsa_mixer-test_event_spurious_LCALTA_26 pass
2678 00:18:24.662548 alsa_mixer-test_get_value_LCALTA_25 pass
2679 00:18:24.668181 alsa_mixer-test_name_LCALTA_25 pass
2680 00:18:24.668704 alsa_mixer-test_write_default_LCALTA_25 pass
2681 00:18:24.673620 alsa_mixer-test_write_valid_LCALTA_25 skip
2682 00:18:24.679215 alsa_mixer-test_write_invalid_LCALTA_25 skip
2683 00:18:24.679743 alsa_mixer-test_event_missing_LCALTA_25 pass
2684 00:18:24.684764 alsa_mixer-test_event_spurious_LCALTA_25 pass
2685 00:18:24.690268 alsa_mixer-test_get_value_LCALTA_24 pass
2686 00:18:24.690794 alsa_mixer-test_name_LCALTA_24 pass
2687 00:18:24.695918 alsa_mixer-test_write_default_LCALTA_24 skip
2688 00:18:24.701376 alsa_mixer-test_write_valid_LCALTA_24 skip
2689 00:18:24.701959 alsa_mixer-test_write_invalid_LCALTA_24 skip
2690 00:18:24.707139 alsa_mixer-test_event_missing_LCALTA_24 pass
2691 00:18:24.712512 alsa_mixer-test_event_spurious_LCALTA_24 pass
2692 00:18:24.718049 alsa_mixer-test_get_value_LCALTA_23 pass
2693 00:18:24.718591 alsa_mixer-test_name_LCALTA_23 pass
2694 00:18:24.723585 alsa_mixer-test_write_default_LCALTA_23 skip
2695 00:18:24.729146 alsa_mixer-test_write_valid_LCALTA_23 skip
2696 00:18:24.729687 alsa_mixer-test_write_invalid_LCALTA_23 skip
2697 00:18:24.734621 alsa_mixer-test_event_missing_LCALTA_23 pass
2698 00:18:24.740199 alsa_mixer-test_event_spurious_LCALTA_23 pass
2699 00:18:24.740726 alsa_mixer-test_get_value_LCALTA_22 pass
2700 00:18:24.745745 alsa_mixer-test_name_LCALTA_22 pass
2701 00:18:24.751322 alsa_mixer-test_write_default_LCALTA_22 pass
2702 00:18:24.751852 alsa_mixer-test_write_valid_LCALTA_22 pass
2703 00:18:24.756861 alsa_mixer-test_write_invalid_LCALTA_22 pass
2704 00:18:24.762373 alsa_mixer-test_event_missing_LCALTA_22 pass
2705 00:18:24.768022 alsa_mixer-test_event_spurious_LCALTA_22 pass
2706 00:18:24.768549 alsa_mixer-test_get_value_LCALTA_21 pass
2707 00:18:24.773466 alsa_mixer-test_name_LCALTA_21 pass
2708 00:18:24.779347 alsa_mixer-test_write_default_LCALTA_21 pass
2709 00:18:24.779891 alsa_mixer-test_write_valid_LCALTA_21 pass
2710 00:18:24.784807 alsa_mixer-test_write_invalid_LCALTA_21 pass
2711 00:18:24.790303 alsa_mixer-test_event_missing_LCALTA_21 pass
2712 00:18:24.790818 alsa_mixer-test_event_spurious_LCALTA_21 pass
2713 00:18:24.796084 alsa_mixer-test_get_value_LCALTA_20 pass
2714 00:18:24.801327 alsa_mixer-test_name_LCALTA_20 pass
2715 00:18:24.801848 alsa_mixer-test_write_default_LCALTA_20 pass
2716 00:18:24.806781 alsa_mixer-test_write_valid_LCALTA_20 pass
2717 00:18:24.812280 alsa_mixer-test_write_invalid_LCALTA_20 pass
2718 00:18:24.812803 alsa_mixer-test_event_missing_LCALTA_20 pass
2719 00:18:24.817882 alsa_mixer-test_event_spurious_LCALTA_20 pass
2720 00:18:24.823413 alsa_mixer-test_get_value_LCALTA_19 pass
2721 00:18:24.823974 alsa_mixer-test_name_LCALTA_19 pass
2722 00:18:24.829068 alsa_mixer-test_write_default_LCALTA_19 pass
2723 00:18:24.834540 alsa_mixer-test_write_valid_LCALTA_19 pass
2724 00:18:24.840066 alsa_mixer-test_write_invalid_LCALTA_19 pass
2725 00:18:24.840598 alsa_mixer-test_event_missing_LCALTA_19 pass
2726 00:18:24.845624 alsa_mixer-test_event_spurious_LCALTA_19 pass
2727 00:18:24.851144 alsa_mixer-test_get_value_LCALTA_18 pass
2728 00:18:24.851687 alsa_mixer-test_name_LCALTA_18 pass
2729 00:18:24.856703 alsa_mixer-test_write_default_LCALTA_18 pass
2730 00:18:24.862237 alsa_mixer-test_write_valid_LCALTA_18 pass
2731 00:18:24.862760 alsa_mixer-test_write_invalid_LCALTA_18 pass
2732 00:18:24.867782 alsa_mixer-test_event_missing_LCALTA_18 pass
2733 00:18:24.873325 alsa_mixer-test_event_spurious_LCALTA_18 pass
2734 00:18:24.873846 alsa_mixer-test_get_value_LCALTA_17 pass
2735 00:18:24.878861 alsa_mixer-test_name_LCALTA_17 pass
2736 00:18:24.884418 alsa_mixer-test_write_default_LCALTA_17 pass
2737 00:18:24.884940 alsa_mixer-test_write_valid_LCALTA_17 pass
2738 00:18:24.890011 alsa_mixer-test_write_invalid_LCALTA_17 pass
2739 00:18:24.899104 alsa_mixer-test_event_missing_LCALTA_17 pass
2740 00:18:24.904363 alsa_mixer-test_event_spurious_LCALTA_17 pass
2741 00:18:24.904960 alsa_mixer-test_get_value_LCALTA_16 pass
2742 00:18:24.906637 alsa_mixer-test_name_LCALTA_16 pass
2743 00:18:24.912408 alsa_mixer-test_write_default_LCALTA_16 pass
2744 00:18:24.912811 alsa_mixer-test_write_valid_LCALTA_16 pass
2745 00:18:24.918000 alsa_mixer-test_write_invalid_LCALTA_16 pass
2746 00:18:24.923539 alsa_mixer-test_event_missing_LCALTA_16 pass
2747 00:18:24.924115 alsa_mixer-test_event_spurious_LCALTA_16 pass
2748 00:18:24.928971 alsa_mixer-test_get_value_LCALTA_15 pass
2749 00:18:24.934413 alsa_mixer-test_name_LCALTA_15 pass
2750 00:18:24.934767 alsa_mixer-test_write_default_LCALTA_15 pass
2751 00:18:24.940045 alsa_mixer-test_write_valid_LCALTA_15 pass
2752 00:18:24.945607 alsa_mixer-test_write_invalid_LCALTA_15 pass
2753 00:18:24.951064 alsa_mixer-test_event_missing_LCALTA_15 pass
2754 00:18:24.951338 alsa_mixer-test_event_spurious_LCALTA_15 pass
2755 00:18:24.956665 alsa_mixer-test_get_value_LCALTA_14 pass
2756 00:18:24.956940 alsa_mixer-test_name_LCALTA_14 pass
2757 00:18:24.962264 alsa_mixer-test_write_default_LCALTA_14 pass
2758 00:18:24.967709 alsa_mixer-test_write_valid_LCALTA_14 pass
2759 00:18:24.973647 alsa_mixer-test_write_invalid_LCALTA_14 pass
2760 00:18:24.974161 alsa_mixer-test_event_missing_LCALTA_14 pass
2761 00:18:24.980776 alsa_mixer-test_event_spurious_LCALTA_14 pass
2762 00:18:24.984626 alsa_mixer-test_get_value_LCALTA_13 pass
2763 00:18:24.985134 alsa_mixer-test_name_LCALTA_13 pass
2764 00:18:24.990229 alsa_mixer-test_write_default_LCALTA_13 pass
2765 00:18:24.995306 alsa_mixer-test_write_valid_LCALTA_13 pass
2766 00:18:24.995669 alsa_mixer-test_write_invalid_LCALTA_13 pass
2767 00:18:25.000848 alsa_mixer-test_event_missing_LCALTA_13 pass
2768 00:18:25.006364 alsa_mixer-test_event_spurious_LCALTA_13 pass
2769 00:18:25.011975 alsa_mixer-test_get_value_LCALTA_12 pass
2770 00:18:25.012349 alsa_mixer-test_name_LCALTA_12 pass
2771 00:18:25.017449 alsa_mixer-test_write_default_LCALTA_12 pass
2772 00:18:25.022934 alsa_mixer-test_write_valid_LCALTA_12 pass
2773 00:18:25.023202 alsa_mixer-test_write_invalid_LCALTA_12 pass
2774 00:18:25.028534 alsa_mixer-test_event_missing_LCALTA_12 pass
2775 00:18:25.034169 alsa_mixer-test_event_spurious_LCALTA_12 pass
2776 00:18:25.034486 alsa_mixer-test_get_value_LCALTA_11 pass
2777 00:18:25.039736 alsa_mixer-test_name_LCALTA_11 pass
2778 00:18:25.045242 alsa_mixer-test_write_default_LCALTA_11 pass
2779 00:18:25.045527 alsa_mixer-test_write_valid_LCALTA_11 pass
2780 00:18:25.050811 alsa_mixer-test_write_invalid_LCALTA_11 pass
2781 00:18:25.056373 alsa_mixer-test_event_missing_LCALTA_11 pass
2782 00:18:25.056857 alsa_mixer-test_event_spurious_LCALTA_11 pass
2783 00:18:25.061914 alsa_mixer-test_get_value_LCALTA_10 pass
2784 00:18:25.067501 alsa_mixer-test_name_LCALTA_10 pass
2785 00:18:25.067918 alsa_mixer-test_write_default_LCALTA_10 pass
2786 00:18:25.073141 alsa_mixer-test_write_valid_LCALTA_10 pass
2787 00:18:25.078584 alsa_mixer-test_write_invalid_LCALTA_10 pass
2788 00:18:25.084138 alsa_mixer-test_event_missing_LCALTA_10 pass
2789 00:18:25.084508 alsa_mixer-test_event_spurious_LCALTA_10 pass
2790 00:18:25.089755 alsa_mixer-test_get_value_LCALTA_9 pass
2791 00:18:25.095211 alsa_mixer-test_name_LCALTA_9 pass
2792 00:18:25.095558 alsa_mixer-test_write_default_LCALTA_9 pass
2793 00:18:25.100794 alsa_mixer-test_write_valid_LCALTA_9 pass
2794 00:18:25.106386 alsa_mixer-test_write_invalid_LCALTA_9 pass
2795 00:18:25.106789 alsa_mixer-test_event_missing_LCALTA_9 pass
2796 00:18:25.111834 alsa_mixer-test_event_spurious_LCALTA_9 pass
2797 00:18:25.117413 alsa_mixer-test_get_value_LCALTA_8 pass
2798 00:18:25.117943 alsa_mixer-test_name_LCALTA_8 pass
2799 00:18:25.122931 alsa_mixer-test_write_default_LCALTA_8 pass
2800 00:18:25.128402 alsa_mixer-test_write_valid_LCALTA_8 pass
2801 00:18:25.128918 alsa_mixer-test_write_invalid_LCALTA_8 pass
2802 00:18:25.133990 alsa_mixer-test_event_missing_LCALTA_8 pass
2803 00:18:25.139543 alsa_mixer-test_event_spurious_LCALTA_8 pass
2804 00:18:25.140081 alsa_mixer-test_get_value_LCALTA_7 pass
2805 00:18:25.145092 alsa_mixer-test_name_LCALTA_7 pass
2806 00:18:25.150676 alsa_mixer-test_write_default_LCALTA_7 pass
2807 00:18:25.151199 alsa_mixer-test_write_valid_LCALTA_7 pass
2808 00:18:25.156226 alsa_mixer-test_write_invalid_LCALTA_7 pass
2809 00:18:25.161724 alsa_mixer-test_event_missing_LCALTA_7 pass
2810 00:18:25.162231 alsa_mixer-test_event_spurious_LCALTA_7 pass
2811 00:18:25.167323 alsa_mixer-test_get_value_LCALTA_6 pass
2812 00:18:25.172821 alsa_mixer-test_name_LCALTA_6 pass
2813 00:18:25.173336 alsa_mixer-test_write_default_LCALTA_6 pass
2814 00:18:25.178425 alsa_mixer-test_write_valid_LCALTA_6 pass
2815 00:18:25.183918 alsa_mixer-test_write_invalid_LCALTA_6 pass
2816 00:18:25.184519 alsa_mixer-test_event_missing_LCALTA_6 pass
2817 00:18:25.189569 alsa_mixer-test_event_spurious_LCALTA_6 pass
2818 00:18:25.195071 alsa_mixer-test_get_value_LCALTA_5 pass
2819 00:18:25.195591 alsa_mixer-test_name_LCALTA_5 pass
2820 00:18:25.200566 alsa_mixer-test_write_default_LCALTA_5 pass
2821 00:18:25.206167 alsa_mixer-test_write_valid_LCALTA_5 pass
2822 00:18:25.206757 alsa_mixer-test_write_invalid_LCALTA_5 pass
2823 00:18:25.211723 alsa_mixer-test_event_missing_LCALTA_5 pass
2824 00:18:25.217221 alsa_mixer-test_event_spurious_LCALTA_5 pass
2825 00:18:25.217745 alsa_mixer-test_get_value_LCALTA_4 pass
2826 00:18:25.222808 alsa_mixer-test_name_LCALTA_4 pass
2827 00:18:25.228325 alsa_mixer-test_write_default_LCALTA_4 pass
2828 00:18:25.228850 alsa_mixer-test_write_valid_LCALTA_4 pass
2829 00:18:25.233847 alsa_mixer-test_write_invalid_LCALTA_4 pass
2830 00:18:25.239406 alsa_mixer-test_event_missing_LCALTA_4 pass
2831 00:18:25.245107 alsa_mixer-test_event_spurious_LCALTA_4 pass
2832 00:18:25.245627 alsa_mixer-test_get_value_LCALTA_3 pass
2833 00:18:25.250482 alsa_mixer-test_name_LCALTA_3 pass
2834 00:18:25.250996 alsa_mixer-test_write_default_LCALTA_3 pass
2835 00:18:25.256133 alsa_mixer-test_write_valid_LCALTA_3 pass
2836 00:18:25.261600 alsa_mixer-test_write_invalid_LCALTA_3 pass
2837 00:18:25.267122 alsa_mixer-test_event_missing_LCALTA_3 pass
2838 00:18:25.267660 alsa_mixer-test_event_spurious_LCALTA_3 pass
2839 00:18:25.272670 alsa_mixer-test_get_value_LCALTA_2 pass
2840 00:18:25.273192 alsa_mixer-test_name_LCALTA_2 pass
2841 00:18:25.278243 alsa_mixer-test_write_default_LCALTA_2 pass
2842 00:18:25.283883 alsa_mixer-test_write_valid_LCALTA_2 pass
2843 00:18:25.289315 alsa_mixer-test_write_invalid_LCALTA_2 pass
2844 00:18:25.289831 alsa_mixer-test_event_missing_LCALTA_2 pass
2845 00:18:25.294870 alsa_mixer-test_event_spurious_LCALTA_2 pass
2846 00:18:25.300457 alsa_mixer-test_get_value_LCALTA_1 pass
2847 00:18:25.300980 alsa_mixer-test_name_LCALTA_1 pass
2848 00:18:25.306087 alsa_mixer-test_write_default_LCALTA_1 pass
2849 00:18:25.311527 alsa_mixer-test_write_valid_LCALTA_1 pass
2850 00:18:25.312166 alsa_mixer-test_write_invalid_LCALTA_1 pass
2851 00:18:25.317157 alsa_mixer-test_event_missing_LCALTA_1 pass
2852 00:18:25.322603 alsa_mixer-test_event_spurious_LCALTA_1 pass
2853 00:18:25.323134 alsa_mixer-test_get_value_LCALTA_0 pass
2854 00:18:25.328125 alsa_mixer-test_name_LCALTA_0 pass
2855 00:18:25.333695 alsa_mixer-test_write_default_LCALTA_0 pass
2856 00:18:25.334218 alsa_mixer-test_write_valid_LCALTA_0 pass
2857 00:18:25.339204 alsa_mixer-test_write_invalid_LCALTA_0 pass
2858 00:18:25.344798 alsa_mixer-test_event_missing_LCALTA_0 pass
2859 00:18:25.345309 alsa_mixer-test_event_spurious_LCALTA_0 pass
2860 00:18:25.350348 alsa_mixer-test pass
2861 00:18:25.355951 alsa_pcm-test_default_time1_LCALTA_5_0_CAPTURE skip
2862 00:18:25.356508 alsa_pcm-test_default_time2_LCALTA_5_0_CAPTURE skip
2863 00:18:25.361454 alsa_pcm-test_default_time3_LCALTA_5_0_CAPTURE skip
2864 00:18:25.367131 alsa_pcm-test_default_time4_LCALTA_5_0_CAPTURE skip
2865 00:18:25.372470 alsa_pcm-test_default_time5_LCALTA_5_0_CAPTURE skip
2866 00:18:25.378098 alsa_pcm-test_default_time6_LCALTA_5_0_CAPTURE skip
2867 00:18:25.378650 alsa_pcm-test_default_time7_LCALTA_5_0_CAPTURE skip
2868 00:18:25.383753 alsa_pcm-test_default_time1_LCALTA_4_0_CAPTURE skip
2869 00:18:25.389178 alsa_pcm-test_default_time2_LCALTA_4_0_CAPTURE skip
2870 00:18:25.394696 alsa_pcm-test_default_time3_LCALTA_4_0_CAPTURE skip
2871 00:18:25.400226 alsa_pcm-test_default_time4_LCALTA_4_0_CAPTURE skip
2872 00:18:25.405879 alsa_pcm-test_default_time5_LCALTA_4_0_CAPTURE skip
2873 00:18:25.406436 alsa_pcm-test_default_time6_LCALTA_4_0_CAPTURE skip
2874 00:18:25.412074 alsa_pcm-test_default_time7_LCALTA_4_0_CAPTURE skip
2875 00:18:25.416975 alsa_pcm-test_default_time1_LCALTA_3_0_CAPTURE skip
2876 00:18:25.422437 alsa_pcm-test_default_time2_LCALTA_3_0_CAPTURE skip
2877 00:18:25.428114 alsa_pcm-test_default_time3_LCALTA_3_0_CAPTURE skip
2878 00:18:25.433546 alsa_pcm-test_default_time4_LCALTA_3_0_CAPTURE skip
2879 00:18:25.434065 alsa_pcm-test_default_time5_LCALTA_3_0_CAPTURE skip
2880 00:18:25.439091 alsa_pcm-test_default_time6_LCALTA_3_0_CAPTURE skip
2881 00:18:25.444591 alsa_pcm-test_default_time7_LCALTA_3_0_CAPTURE skip
2882 00:18:25.450168 alsa_pcm-test_default_time1_LCALTA_2_0_PLAYBACK skip
2883 00:18:25.455695 alsa_pcm-test_default_time2_LCALTA_2_0_PLAYBACK skip
2884 00:18:25.461228 alsa_pcm-test_default_time3_LCALTA_2_0_PLAYBACK skip
2885 00:18:25.461720 alsa_pcm-test_default_time4_LCALTA_2_0_PLAYBACK skip
2886 00:18:25.466815 alsa_pcm-test_default_time5_LCALTA_2_0_PLAYBACK skip
2887 00:18:25.472343 alsa_pcm-test_default_time6_LCALTA_2_0_PLAYBACK skip
2888 00:18:25.478023 alsa_pcm-test_default_time7_LCALTA_2_0_PLAYBACK skip
2889 00:18:25.483461 alsa_pcm-test_default_time1_LCALTA_1_0_PLAYBACK skip
2890 00:18:25.489084 alsa_pcm-test_default_time2_LCALTA_1_0_PLAYBACK skip
2891 00:18:25.494501 alsa_pcm-test_default_time3_LCALTA_1_0_PLAYBACK skip
2892 00:18:25.494987 alsa_pcm-test_default_time4_LCALTA_1_0_PLAYBACK skip
2893 00:18:25.500095 alsa_pcm-test_default_time5_LCALTA_1_0_PLAYBACK skip
2894 00:18:25.505766 alsa_pcm-test_default_time6_LCALTA_1_0_PLAYBACK skip
2895 00:18:25.511230 alsa_pcm-test_default_time7_LCALTA_1_0_PLAYBACK skip
2896 00:18:25.516831 alsa_pcm-test_default_time1_LCALTA_0_0_PLAYBACK skip
2897 00:18:25.522969 alsa_pcm-test_default_time2_LCALTA_0_0_PLAYBACK skip
2898 00:18:25.523510 alsa_pcm-test_default_time3_LCALTA_0_0_PLAYBACK skip
2899 00:18:25.527893 alsa_pcm-test_default_time4_LCALTA_0_0_PLAYBACK skip
2900 00:18:25.533421 alsa_pcm-test_default_time5_LCALTA_0_0_PLAYBACK skip
2901 00:18:25.539063 alsa_pcm-test_default_time6_LCALTA_0_0_PLAYBACK skip
2902 00:18:25.544644 alsa_pcm-test_default_time7_LCALTA_0_0_PLAYBACK skip
2903 00:18:25.545183 alsa_pcm-test pass
2904 00:18:25.557727 alsa_test-pcmtest-driver_pcmtest_playback_Can_t_read_patterns_Probably_module_isn_t_loaded skip
2905 00:18:25.561263 alsa_test-pcmtest-driver_pcmtest_capture_Can_t_read_patterns_Probably_module_isn_t_loaded skip
2906 00:18:25.572271 alsa_test-pcmtest-driver_pcmtest_ni_capture_Can_t_read_patterns_Probably_module_isn_t_loaded skip
2907 00:18:25.577858 alsa_test-pcmtest-driver_pcmtest_ni_playback_Can_t_read_patterns_Probably_module_isn_t_loaded skip
2908 00:18:25.588983 alsa_test-pcmtest-driver_pcmtest_reset_ioctl_Can_t_read_patterns_Probably_module_isn_t_loaded skip
2909 00:18:25.589652 alsa_test-pcmtest-driver pass
2910 00:18:25.594488 alsa_utimer-test_global_wrong_timers_test pass
2911 00:18:25.600060 alsa_utimer-test_timer_f_utimer fail
2912 00:18:25.600651 alsa_utimer-test fail
2913 00:18:25.605979 + ../../utils/send-to-lava.sh ./output/result.txt
2914 00:18:25.611299 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-alsa RESULT=pass>
2915 00:18:25.612439 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-alsa RESULT=pass
2917 00:18:25.616711 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_60 RESULT=pass>
2918 00:18:25.617614 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_60 RESULT=pass
2920 00:18:25.624597 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_60 RESULT=pass>
2921 00:18:25.625552 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_60 RESULT=pass
2923 00:18:25.649532 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_60 RESULT=pass>
2924 00:18:25.650496 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_60 RESULT=pass
2926 00:18:25.698385 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_60 RESULT=pass>
2927 00:18:25.699327 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_60 RESULT=pass
2929 00:18:25.747917 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_60 RESULT=pass>
2930 00:18:25.748904 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_60 RESULT=pass
2932 00:18:25.793719 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_60 RESULT=pass>
2933 00:18:25.794399 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_60 RESULT=pass
2935 00:18:25.843802 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_60 RESULT=pass>
2936 00:18:25.844541 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_60 RESULT=pass
2938 00:18:25.895749 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_59 RESULT=pass>
2939 00:18:25.896426 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_59 RESULT=pass
2941 00:18:25.950581 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_59 RESULT=pass>
2942 00:18:25.951255 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_59 RESULT=pass
2944 00:18:25.998410 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_59 RESULT=pass>
2945 00:18:25.999039 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_59 RESULT=pass
2947 00:18:26.045317 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_59 RESULT=pass>
2948 00:18:26.045948 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_59 RESULT=pass
2950 00:18:26.090359 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_59 RESULT=pass>
2951 00:18:26.091036 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_59 RESULT=pass
2953 00:18:26.135747 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_59 RESULT=pass>
2954 00:18:26.136428 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_59 RESULT=pass
2956 00:18:26.186189 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_59 RESULT=pass>
2957 00:18:26.186820 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_59 RESULT=pass
2959 00:18:26.233314 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_58 RESULT=pass>
2960 00:18:26.233933 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_58 RESULT=pass
2962 00:18:26.278094 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_58 RESULT=pass>
2963 00:18:26.278713 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_58 RESULT=pass
2965 00:18:26.323954 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_58 RESULT=pass>
2966 00:18:26.324621 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_58 RESULT=pass
2968 00:18:26.372626 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_58 RESULT=pass>
2969 00:18:26.373539 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_58 RESULT=pass
2971 00:18:26.421318 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_58 RESULT=pass>
2972 00:18:26.422154 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_58 RESULT=pass
2974 00:18:26.470720 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_58 RESULT=pass>
2975 00:18:26.471545 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_58 RESULT=pass
2977 00:18:26.515349 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_58 RESULT=pass>
2978 00:18:26.516158 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_58 RESULT=pass
2980 00:18:26.559913 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_57 RESULT=pass>
2981 00:18:26.560747 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_57 RESULT=pass
2983 00:18:26.606753 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_57 RESULT=pass>
2984 00:18:26.607591 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_57 RESULT=pass
2986 00:18:26.664995 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_57 RESULT=pass>
2987 00:18:26.665896 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_57 RESULT=pass
2989 00:18:26.721163 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_57 RESULT=pass>
2990 00:18:26.721873 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_57 RESULT=pass
2992 00:18:26.777534 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_57 RESULT=pass>
2993 00:18:26.778184 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_57 RESULT=pass
2995 00:18:26.824053 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_57 RESULT=pass>
2996 00:18:26.824706 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_57 RESULT=pass
2998 00:18:26.869625 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_57 RESULT=pass>
2999 00:18:26.870255 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_57 RESULT=pass
3001 00:18:26.915861 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_56 RESULT=pass>
3002 00:18:26.916513 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_56 RESULT=pass
3004 00:18:26.962501 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_56 RESULT=pass>
3005 00:18:26.963157 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_56 RESULT=pass
3007 00:18:27.023410 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_56 RESULT=pass>
3008 00:18:27.024063 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_56 RESULT=pass
3010 00:18:27.070644 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_56 RESULT=pass>
3011 00:18:27.071475 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_56 RESULT=pass
3013 00:18:27.122780 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_56 RESULT=pass>
3014 00:18:27.123410 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_56 RESULT=pass
3016 00:18:27.171662 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_56 RESULT=pass>
3017 00:18:27.172309 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_56 RESULT=pass
3019 00:18:27.221517 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_56 RESULT=pass>
3020 00:18:27.222387 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_56 RESULT=pass
3022 00:18:27.267929 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_55 RESULT=pass>
3023 00:18:27.268919 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_55 RESULT=pass
3025 00:18:27.315386 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_55 RESULT=pass>
3026 00:18:27.316227 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_55 RESULT=pass
3028 00:18:27.368631 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_55 RESULT=pass>
3029 00:18:27.369503 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_55 RESULT=pass
3031 00:18:27.419599 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_55 RESULT=pass>
3032 00:18:27.420497 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_55 RESULT=pass
3034 00:18:27.469288 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_55 RESULT=pass>
3035 00:18:27.470156 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_55 RESULT=pass
3037 00:18:27.522709 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_55 RESULT=pass>
3038 00:18:27.523558 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_55 RESULT=pass
3040 00:18:27.572859 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_55 RESULT=pass>
3041 00:18:27.573542 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_55 RESULT=pass
3043 00:18:27.620013 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_54 RESULT=pass>
3044 00:18:27.620634 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_54 RESULT=pass
3046 00:18:27.665028 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_54 RESULT=pass>
3047 00:18:27.665865 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_54 RESULT=pass
3049 00:18:27.716827 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_54 RESULT=pass>
3050 00:18:27.717534 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_54 RESULT=pass
3052 00:18:27.766037 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_54 RESULT=pass>
3053 00:18:27.766681 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_54 RESULT=pass
3055 00:18:27.811302 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_54 RESULT=pass>
3056 00:18:27.812167 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_54 RESULT=pass
3058 00:18:27.868062 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_54 RESULT=pass>
3059 00:18:27.868827 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_54 RESULT=pass
3061 00:18:27.916259 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_54 RESULT=pass>
3062 00:18:27.916984 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_54 RESULT=pass
3064 00:18:27.962024 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_53 RESULT=pass>
3065 00:18:27.962747 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_53 RESULT=pass
3067 00:18:28.009512 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_53 RESULT=pass>
3068 00:18:28.010239 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_53 RESULT=pass
3070 00:18:28.064687 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_53 RESULT=pass>
3071 00:18:28.065443 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_53 RESULT=pass
3073 00:18:28.108540 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_53 RESULT=pass>
3074 00:18:28.109281 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_53 RESULT=pass
3076 00:18:28.159825 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_53 RESULT=pass>
3077 00:18:28.160634 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_53 RESULT=pass
3079 00:18:28.204837 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_53 RESULT=pass>
3080 00:18:28.205579 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_53 RESULT=pass
3082 00:18:28.266122 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_53 RESULT=pass>
3083 00:18:28.266860 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_53 RESULT=pass
3085 00:18:28.312565 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_52 RESULT=pass>
3086 00:18:28.313316 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_52 RESULT=pass
3088 00:18:28.365438 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_52 RESULT=pass>
3089 00:18:28.366157 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_52 RESULT=pass
3091 00:18:28.412571 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_52 RESULT=pass>
3092 00:18:28.413283 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_52 RESULT=pass
3094 00:18:28.460304 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_52 RESULT=pass>
3095 00:18:28.461041 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_52 RESULT=pass
3097 00:18:28.518040 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_52 RESULT=pass>
3098 00:18:28.518781 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_52 RESULT=pass
3100 00:18:28.564633 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_52 RESULT=pass>
3101 00:18:28.565368 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_52 RESULT=pass
3103 00:18:28.609459 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_52 RESULT=pass>
3104 00:18:28.610196 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_52 RESULT=pass
3106 00:18:28.661621 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_51 RESULT=pass>
3107 00:18:28.662340 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_51 RESULT=pass
3109 00:18:28.714088 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_51 RESULT=pass>
3110 00:18:28.714803 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_51 RESULT=pass
3112 00:18:28.770123 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_51 RESULT=pass>
3113 00:18:28.770769 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_51 RESULT=pass
3115 00:18:28.814712 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_51 RESULT=pass>
3116 00:18:28.815344 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_51 RESULT=pass
3118 00:18:28.860802 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_51 RESULT=pass>
3119 00:18:28.861642 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_51 RESULT=pass
3121 00:18:28.910747 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_51 RESULT=pass>
3122 00:18:28.912196 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_51 RESULT=pass
3124 00:18:28.962481 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_51 RESULT=pass>
3125 00:18:28.963535 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_51 RESULT=pass
3127 00:18:29.014041 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_50 RESULT=pass>
3128 00:18:29.015039 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_50 RESULT=pass
3130 00:18:29.059448 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_50 RESULT=pass>
3131 00:18:29.060340 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_50 RESULT=pass
3133 00:18:29.112135 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_50 RESULT=pass>
3134 00:18:29.113011 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_50 RESULT=pass
3136 00:18:29.166848 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_50 RESULT=pass>
3137 00:18:29.167676 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_50 RESULT=pass
3139 00:18:29.212368 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_50 RESULT=pass>
3140 00:18:29.213209 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_50 RESULT=pass
3142 00:18:29.267760 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_50 RESULT=pass>
3143 00:18:29.268618 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_50 RESULT=pass
3145 00:18:29.311596 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_50 RESULT=pass>
3146 00:18:29.312437 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_50 RESULT=pass
3148 00:18:29.361214 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_49 RESULT=pass>
3149 00:18:29.362081 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_49 RESULT=pass
3151 00:18:29.415895 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_49 RESULT=pass>
3152 00:18:29.416567 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_49 RESULT=pass
3154 00:18:29.470698 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_49 RESULT=pass>
3155 00:18:29.471331 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_49 RESULT=pass
3157 00:18:29.524762 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_49 RESULT=pass>
3158 00:18:29.525602 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_49 RESULT=pass
3160 00:18:29.569779 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_49 RESULT=pass>
3161 00:18:29.570571 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_49 RESULT=pass
3163 00:18:29.615822 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_49 RESULT=pass>
3164 00:18:29.616677 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_49 RESULT=pass
3166 00:18:29.670275 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_49 RESULT=pass>
3167 00:18:29.671134 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_49 RESULT=pass
3169 00:18:29.716123 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_48 RESULT=pass>
3170 00:18:29.717009 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_48 RESULT=pass
3172 00:18:29.771144 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_48 RESULT=pass>
3173 00:18:29.772015 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_48 RESULT=pass
3175 00:18:29.815505 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_48 RESULT=pass>
3176 00:18:29.816350 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_48 RESULT=pass
3178 00:18:29.858793 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_48 RESULT=pass>
3179 00:18:29.859566 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_48 RESULT=pass
3181 00:18:29.908699 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_48 RESULT=pass>
3182 00:18:29.909500 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_48 RESULT=pass
3184 00:18:29.952608 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_48 RESULT=pass>
3185 00:18:29.953366 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_48 RESULT=pass
3187 00:18:29.997350 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_48 RESULT=pass>
3188 00:18:29.998158 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_48 RESULT=pass
3190 00:18:30.040902 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_47 RESULT=pass>
3191 00:18:30.041673 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_47 RESULT=pass
3193 00:18:30.088984 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_47 RESULT=pass>
3194 00:18:30.089758 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_47 RESULT=pass
3196 00:18:30.139596 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_47 RESULT=pass>
3197 00:18:30.140454 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_47 RESULT=pass
3199 00:18:30.192835 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_47 RESULT=pass>
3200 00:18:30.193614 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_47 RESULT=pass
3202 00:18:30.238432 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_47 RESULT=pass>
3203 00:18:30.239251 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_47 RESULT=pass
3205 00:18:30.284146 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_47 RESULT=pass>
3206 00:18:30.284967 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_47 RESULT=pass
3208 00:18:30.329295 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_47 RESULT=pass>
3209 00:18:30.330123 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_47 RESULT=pass
3211 00:18:30.380053 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_46 RESULT=pass>
3212 00:18:30.380835 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_46 RESULT=pass
3214 00:18:30.430654 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_46 RESULT=pass>
3215 00:18:30.431452 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_46 RESULT=pass
3217 00:18:30.476565 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_46 RESULT=pass>
3218 00:18:30.477328 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_46 RESULT=pass
3220 00:18:30.533473 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_46 RESULT=pass>
3221 00:18:30.534283 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_46 RESULT=pass
3223 00:18:30.590584 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_46 RESULT=pass>
3224 00:18:30.591354 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_46 RESULT=pass
3226 00:18:30.639042 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_46 RESULT=pass>
3227 00:18:30.639826 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_46 RESULT=pass
3229 00:18:30.690657 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_46 RESULT=pass>
3230 00:18:30.691416 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_46 RESULT=pass
3232 00:18:30.742438 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_45 RESULT=pass>
3233 00:18:30.743216 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_45 RESULT=pass
3235 00:18:30.799794 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_45 RESULT=pass>
3236 00:18:30.800686 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_45 RESULT=pass
3238 00:18:30.849650 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_45 RESULT=pass>
3239 00:18:30.850422 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_45 RESULT=pass
3241 00:18:30.900552 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_45 RESULT=pass>
3242 00:18:30.901310 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_45 RESULT=pass
3244 00:18:30.945166 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_45 RESULT=pass>
3245 00:18:30.945931 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_45 RESULT=pass
3247 00:18:30.992555 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_45 RESULT=pass>
3248 00:18:30.993294 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_45 RESULT=pass
3250 00:18:31.043226 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_45 RESULT=pass>
3251 00:18:31.044058 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_45 RESULT=pass
3253 00:18:31.087334 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_44 RESULT=pass>
3254 00:18:31.088085 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_44 RESULT=pass
3256 00:18:31.130635 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_44 RESULT=pass>
3257 00:18:31.131406 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_44 RESULT=pass
3259 00:18:31.178786 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_44 RESULT=pass>
3260 00:18:31.179566 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_44 RESULT=pass
3262 00:18:31.225074 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_44 RESULT=pass>
3263 00:18:31.225937 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_44 RESULT=pass
3265 00:18:31.275293 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_44 RESULT=pass>
3266 00:18:31.276113 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_44 RESULT=pass
3268 00:18:31.325864 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_44 RESULT=pass>
3269 00:18:31.326730 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_44 RESULT=pass
3271 00:18:31.371818 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_44 RESULT=pass>
3272 00:18:31.372682 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_44 RESULT=pass
3274 00:18:31.417175 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_43 RESULT=pass>
3275 00:18:31.418032 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_43 RESULT=pass
3277 00:18:31.469722 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_43 RESULT=pass>
3278 00:18:31.470732 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_43 RESULT=pass
3280 00:18:31.526073 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_43 RESULT=pass>
3281 00:18:31.526753 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_43 RESULT=pass
3283 00:18:31.575826 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_43 RESULT=pass>
3284 00:18:31.576513 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_43 RESULT=pass
3286 00:18:31.621458 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_43 RESULT=pass>
3287 00:18:31.622098 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_43 RESULT=pass
3289 00:18:31.674628 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_43 RESULT=pass>
3290 00:18:31.675309 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_43 RESULT=pass
3292 00:18:31.722223 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_43 RESULT=pass>
3293 00:18:31.722929 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_43 RESULT=pass
3295 00:18:31.771124 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_42 RESULT=pass>
3296 00:18:31.772052 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_42 RESULT=pass
3298 00:18:31.826821 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_42 RESULT=pass>
3299 00:18:31.827469 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_42 RESULT=pass
3301 00:18:31.882840 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_42 RESULT=pass>
3302 00:18:31.883633 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_42 RESULT=pass
3304 00:18:31.927199 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_42 RESULT=pass>
3305 00:18:31.927789 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_42 RESULT=pass
3307 00:18:31.974741 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_42 RESULT=pass>
3308 00:18:31.975329 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_42 RESULT=pass
3310 00:18:32.020176 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_42 RESULT=pass>
3311 00:18:32.020766 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_42 RESULT=pass
3313 00:18:32.076366 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_42 RESULT=pass>
3314 00:18:32.077010 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_42 RESULT=pass
3316 00:18:32.128032 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_41 RESULT=pass>
3317 00:18:32.128649 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_41 RESULT=pass
3319 00:18:32.173975 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_41 RESULT=pass>
3320 00:18:32.174619 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_41 RESULT=pass
3322 00:18:32.221607 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_41 RESULT=pass>
3323 00:18:32.222292 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_41 RESULT=pass
3325 00:18:32.269582 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_41 RESULT=pass>
3326 00:18:32.270231 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_41 RESULT=pass
3328 00:18:32.327336 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_41 RESULT=pass>
3329 00:18:32.328027 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_41 RESULT=pass
3331 00:18:32.379153 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_41 RESULT=pass>
3332 00:18:32.379776 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_41 RESULT=pass
3334 00:18:32.426038 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_41 RESULT=pass>
3335 00:18:32.426644 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_41 RESULT=pass
3337 00:18:32.473223 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_40 RESULT=pass>
3338 00:18:32.473834 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_40 RESULT=pass
3340 00:18:32.532783 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_40 RESULT=pass>
3341 00:18:32.533417 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_40 RESULT=pass
3343 00:18:32.582758 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_40 RESULT=pass>
3344 00:18:32.583399 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_40 RESULT=pass
3346 00:18:32.642747 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_40 RESULT=pass>
3347 00:18:32.643328 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_40 RESULT=pass
3349 00:18:32.709074 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_40 RESULT=pass>
3350 00:18:32.709675 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_40 RESULT=pass
3352 00:18:32.758769 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_40 RESULT=pass>
3353 00:18:32.759396 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_40 RESULT=pass
3355 00:18:32.824036 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_40 RESULT=pass>
3356 00:18:32.824730 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_40 RESULT=pass
3358 00:18:32.876648 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_39 RESULT=pass>
3359 00:18:32.877259 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_39 RESULT=pass
3361 00:18:32.929336 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_39 RESULT=pass>
3362 00:18:32.929946 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_39 RESULT=pass
3364 00:18:32.984052 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_39 RESULT=pass>
3365 00:18:32.984662 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_39 RESULT=pass
3367 00:18:33.040304 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_39 RESULT=pass>
3368 00:18:33.040911 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_39 RESULT=pass
3370 00:18:33.097899 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_39 RESULT=pass>
3371 00:18:33.098502 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_39 RESULT=pass
3373 00:18:33.148722 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_39 RESULT=pass>
3374 00:18:33.149381 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_39 RESULT=pass
3376 00:18:33.208567 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_39 RESULT=pass>
3377 00:18:33.209216 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_39 RESULT=pass
3379 00:18:33.261364 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_38 RESULT=pass>
3380 00:18:33.262005 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_38 RESULT=pass
3382 00:18:33.314879 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_38 RESULT=pass>
3383 00:18:33.315513 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_38 RESULT=pass
3385 00:18:33.367919 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_38 RESULT=pass>
3386 00:18:33.368556 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_38 RESULT=pass
3388 00:18:33.414516 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_38 RESULT=pass>
3389 00:18:33.415108 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_38 RESULT=pass
3391 00:18:33.463398 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_38 RESULT=pass>
3392 00:18:33.464025 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_38 RESULT=pass
3394 00:18:33.522489 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_38 RESULT=pass>
3395 00:18:33.523112 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_38 RESULT=pass
3397 00:18:33.575928 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_38 RESULT=pass>
3398 00:18:33.576573 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_38 RESULT=pass
3400 00:18:33.632809 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_37 RESULT=pass>
3401 00:18:33.633440 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_37 RESULT=pass
3403 00:18:33.687903 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_37 RESULT=pass>
3404 00:18:33.688546 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_37 RESULT=pass
3406 00:18:33.742264 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_37 RESULT=pass>
3407 00:18:33.742902 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_37 RESULT=pass
3409 00:18:33.794704 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_37 RESULT=pass>
3410 00:18:33.795315 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_37 RESULT=pass
3412 00:18:33.849282 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_37 RESULT=pass>
3413 00:18:33.849884 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_37 RESULT=pass
3415 00:18:33.910514 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_37 RESULT=pass>
3416 00:18:33.911132 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_37 RESULT=pass
3418 00:18:33.958264 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_37 RESULT=pass>
3419 00:18:33.958881 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_37 RESULT=pass
3421 00:18:34.018296 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_36 RESULT=pass>
3422 00:18:34.018912 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_36 RESULT=pass
3424 00:18:34.068736 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_36 RESULT=pass>
3425 00:18:34.069314 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_36 RESULT=pass
3427 00:18:34.116174 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_36 RESULT=pass>
3428 00:18:34.116768 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_36 RESULT=pass
3430 00:18:34.162352 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_36 RESULT=pass>
3431 00:18:34.162962 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_36 RESULT=pass
3433 00:18:34.215123 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_36 RESULT=pass>
3434 00:18:34.215757 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_36 RESULT=pass
3436 00:18:34.271410 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_36 RESULT=pass>
3437 00:18:34.272066 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_36 RESULT=pass
3439 00:18:34.320711 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_36 RESULT=pass>
3440 00:18:34.321325 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_36 RESULT=pass
3442 00:18:34.365210 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_35 RESULT=pass>
3443 00:18:34.365844 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_35 RESULT=pass
3445 00:18:34.425493 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_35 RESULT=pass>
3446 00:18:34.426108 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_35 RESULT=pass
3448 00:18:34.482594 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_35 RESULT=pass>
3449 00:18:34.483224 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_35 RESULT=pass
3451 00:18:34.527586 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_35 RESULT=pass>
3452 00:18:34.528183 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_35 RESULT=pass
3454 00:18:34.575354 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_35 RESULT=pass>
3455 00:18:34.575917 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_35 RESULT=pass
3457 00:18:34.622514 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_35 RESULT=pass>
3458 00:18:34.623093 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_35 RESULT=pass
3460 00:18:34.668560 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_35 RESULT=pass>
3461 00:18:34.669145 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_35 RESULT=pass
3463 00:18:34.715240 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_34 RESULT=pass>
3464 00:18:34.715809 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_34 RESULT=pass
3466 00:18:34.760486 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_34 RESULT=pass>
3467 00:18:34.761034 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_34 RESULT=pass
3469 00:18:34.815928 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_34 RESULT=pass>
3470 00:18:34.816544 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_34 RESULT=pass
3472 00:18:34.867548 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_34 RESULT=pass>
3473 00:18:34.868128 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_34 RESULT=pass
3475 00:18:34.920590 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_34 RESULT=pass>
3476 00:18:34.921162 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_34 RESULT=pass
3478 00:18:34.970475 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_34 RESULT=pass>
3479 00:18:34.971051 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_34 RESULT=pass
3481 00:18:35.026610 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_34 RESULT=pass>
3482 00:18:35.027181 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_34 RESULT=pass
3484 00:18:35.075878 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_33 RESULT=pass>
3485 00:18:35.076462 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_33 RESULT=pass
3487 00:18:35.120693 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_33 RESULT=pass>
3488 00:18:35.121257 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_33 RESULT=pass
3490 00:18:35.178918 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_33 RESULT=pass>
3491 00:18:35.179532 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_33 RESULT=pass
3493 00:18:35.229408 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_33 RESULT=pass>
3494 00:18:35.230020 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_33 RESULT=pass
3496 00:18:35.280174 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_33 RESULT=pass>
3497 00:18:35.280806 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_33 RESULT=pass
3499 00:18:35.324077 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_33 RESULT=pass>
3500 00:18:35.324659 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_33 RESULT=pass
3502 00:18:35.370934 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_33 RESULT=pass>
3503 00:18:35.371542 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_33 RESULT=pass
3505 00:18:35.421301 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_32 RESULT=pass>
3506 00:18:35.421889 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_32 RESULT=pass
3508 00:18:35.484541 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_32 RESULT=pass>
3509 00:18:35.485470 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_32 RESULT=pass
3511 00:18:35.540566 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_32 RESULT=pass>
3512 00:18:35.541428 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_32 RESULT=pass
3514 00:18:35.590151 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_32 RESULT=pass>
3515 00:18:35.591013 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_32 RESULT=pass
3517 00:18:35.638250 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_32 RESULT=pass>
3518 00:18:35.639109 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_32 RESULT=pass
3520 00:18:35.683909 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_32 RESULT=pass>
3521 00:18:35.684788 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_32 RESULT=pass
3523 00:18:35.726787 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_32 RESULT=pass>
3524 00:18:35.727630 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_32 RESULT=pass
3526 00:18:35.782541 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_31 RESULT=pass>
3527 00:18:35.783699 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_31 RESULT=pass
3529 00:18:35.828438 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_31 RESULT=pass>
3530 00:18:35.829355 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_31 RESULT=pass
3532 00:18:35.880932 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_31 RESULT=pass>
3533 00:18:35.881837 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_31 RESULT=pass
3535 00:18:35.924256 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_31 RESULT=pass>
3536 00:18:35.925152 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_31 RESULT=pass
3538 00:18:35.975534 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_31 RESULT=pass>
3539 00:18:35.976481 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_31 RESULT=pass
3541 00:18:36.025439 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_31 RESULT=pass>
3542 00:18:36.026313 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_31 RESULT=pass
3544 00:18:36.072589 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_31 RESULT=pass>
3545 00:18:36.073541 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_31 RESULT=pass
3547 00:18:36.128058 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_30 RESULT=pass>
3548 00:18:36.128983 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_30 RESULT=pass
3550 00:18:36.171619 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_30 RESULT=pass>
3551 00:18:36.172556 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_30 RESULT=pass
3553 00:18:36.220268 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_30 RESULT=pass>
3554 00:18:36.221147 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_30 RESULT=pass
3556 00:18:36.266055 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_30 RESULT=pass>
3557 00:18:36.266906 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_30 RESULT=pass
3559 00:18:36.311512 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_30 RESULT=pass>
3560 00:18:36.312402 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_30 RESULT=pass
3562 00:18:36.360588 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_30 RESULT=pass>
3563 00:18:36.361445 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_30 RESULT=pass
3565 00:18:36.414913 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_30 RESULT=pass>
3566 00:18:36.415765 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_30 RESULT=pass
3568 00:18:36.472061 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_29 RESULT=pass>
3569 00:18:36.472923 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_29 RESULT=pass
3571 00:18:36.518284 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_29 RESULT=pass>
3572 00:18:36.519129 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_29 RESULT=pass
3574 00:18:36.569924 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_29 RESULT=pass>
3575 00:18:36.570786 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_29 RESULT=pass
3577 00:18:36.622826 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_29 RESULT=pass>
3578 00:18:36.623686 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_29 RESULT=pass
3580 00:18:36.674808 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_29 RESULT=pass>
3581 00:18:36.675669 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_29 RESULT=pass
3583 00:18:36.722367 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_29 RESULT=pass>
3584 00:18:36.723223 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_29 RESULT=pass
3586 00:18:36.769288 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_29 RESULT=pass>
3587 00:18:36.770149 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_29 RESULT=pass
3589 00:18:36.819947 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_28 RESULT=pass>
3590 00:18:36.820866 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_28 RESULT=pass
3592 00:18:36.871453 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_28 RESULT=pass>
3593 00:18:36.872370 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_28 RESULT=pass
3595 00:18:36.925719 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_28 RESULT=pass>
3596 00:18:36.926568 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_28 RESULT=pass
3598 00:18:36.982334 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_28 RESULT=pass>
3599 00:18:36.983187 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_28 RESULT=pass
3601 00:18:37.031518 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_28 RESULT=pass>
3602 00:18:37.032428 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_28 RESULT=pass
3604 00:18:37.075874 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_28 RESULT=pass>
3605 00:18:37.076764 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_28 RESULT=pass
3607 00:18:37.128690 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_28 RESULT=pass>
3608 00:18:37.129551 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_28 RESULT=pass
3610 00:18:37.180384 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_27 RESULT=pass>
3611 00:18:37.181242 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_27 RESULT=pass
3613 00:18:37.234187 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_27 RESULT=pass>
3614 00:18:37.235060 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_27 RESULT=pass
3616 00:18:37.284083 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_27 RESULT=pass>
3617 00:18:37.284926 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_27 RESULT=pass
3619 00:18:37.335427 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_27 RESULT=pass>
3620 00:18:37.336334 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_27 RESULT=pass
3622 00:18:37.381196 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_27 RESULT=pass>
3623 00:18:37.381945 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_27 RESULT=pass
3625 00:18:37.436438 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_27 RESULT=pass>
3626 00:18:37.437271 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_27 RESULT=pass
3628 00:18:37.491659 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_27 RESULT=pass>
3629 00:18:37.492437 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_27 RESULT=pass
3631 00:18:37.545090 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_26 RESULT=pass>
3632 00:18:37.545953 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_26 RESULT=pass
3634 00:18:37.596727 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_26 RESULT=pass>
3635 00:18:37.597566 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_26 RESULT=pass
3637 00:18:37.651023 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_26 RESULT=skip>
3638 00:18:37.651837 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_26 RESULT=skip
3640 00:18:37.702070 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_26 RESULT=skip>
3641 00:18:37.702851 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_26 RESULT=skip
3643 00:18:37.748782 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_26 RESULT=skip>
3644 00:18:37.749600 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_26 RESULT=skip
3646 00:18:37.796668 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_26 RESULT=pass>
3647 00:18:37.797425 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_26 RESULT=pass
3649 00:18:37.850539 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_26 RESULT=pass>
3650 00:18:37.851369 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_26 RESULT=pass
3652 00:18:37.903454 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_25 RESULT=pass>
3653 00:18:37.904224 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_25 RESULT=pass
3655 00:18:37.948188 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_25 RESULT=pass>
3656 00:18:37.949006 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_25 RESULT=pass
3658 00:18:38.001557 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_25 RESULT=pass>
3659 00:18:38.002296 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_25 RESULT=pass
3661 00:18:38.048855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_25 RESULT=skip>
3662 00:18:38.049658 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_25 RESULT=skip
3664 00:18:38.101085 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_25 RESULT=skip>
3665 00:18:38.101919 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_25 RESULT=skip
3667 00:18:38.155599 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_25 RESULT=pass>
3668 00:18:38.156471 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_25 RESULT=pass
3670 00:18:38.201547 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_25 RESULT=pass>
3671 00:18:38.202297 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_25 RESULT=pass
3673 00:18:38.250230 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_24 RESULT=pass>
3674 00:18:38.251037 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_24 RESULT=pass
3676 00:18:38.300602 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_24 RESULT=pass>
3677 00:18:38.301365 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_24 RESULT=pass
3679 00:18:38.352172 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_24 RESULT=skip>
3680 00:18:38.352963 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_24 RESULT=skip
3682 00:18:38.404222 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_24 RESULT=skip>
3683 00:18:38.404971 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_24 RESULT=skip
3685 00:18:38.451350 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_24 RESULT=skip>
3686 00:18:38.452198 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_24 RESULT=skip
3688 00:18:38.496512 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_24 RESULT=pass>
3689 00:18:38.497266 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_24 RESULT=pass
3691 00:18:38.545018 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_24 RESULT=pass>
3692 00:18:38.545870 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_24 RESULT=pass
3694 00:18:38.599526 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_23 RESULT=pass>
3695 00:18:38.600306 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_23 RESULT=pass
3697 00:18:38.658154 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_23 RESULT=pass>
3698 00:18:38.658987 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_23 RESULT=pass
3700 00:18:38.704692 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_23 RESULT=skip>
3701 00:18:38.705454 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_23 RESULT=skip
3703 00:18:38.757780 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_23 RESULT=skip>
3704 00:18:38.758601 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_23 RESULT=skip
3706 00:18:38.802674 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_23 RESULT=skip>
3707 00:18:38.803435 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_23 RESULT=skip
3709 00:18:38.857032 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_23 RESULT=pass>
3710 00:18:38.857863 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_23 RESULT=pass
3712 00:18:38.900248 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_23 RESULT=pass>
3713 00:18:38.900973 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_23 RESULT=pass
3715 00:18:38.950434 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_22 RESULT=pass>
3716 00:18:38.951260 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_22 RESULT=pass
3718 00:18:38.992907 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_22 RESULT=pass>
3719 00:18:38.993635 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_22 RESULT=pass
3721 00:18:39.035561 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_22 RESULT=pass>
3722 00:18:39.036418 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_22 RESULT=pass
3724 00:18:39.087744 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_22 RESULT=pass>
3725 00:18:39.088640 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_22 RESULT=pass
3727 00:18:39.137731 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_22 RESULT=pass>
3728 00:18:39.138474 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_22 RESULT=pass
3730 00:18:39.190322 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_22 RESULT=pass>
3731 00:18:39.191170 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_22 RESULT=pass
3733 00:18:39.235780 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_22 RESULT=pass>
3734 00:18:39.236573 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_22 RESULT=pass
3736 00:18:39.286252 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_21 RESULT=pass>
3737 00:18:39.287104 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_21 RESULT=pass
3739 00:18:39.330066 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_21 RESULT=pass>
3740 00:18:39.330816 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_21 RESULT=pass
3742 00:18:39.383904 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_21 RESULT=pass>
3743 00:18:39.384783 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_21 RESULT=pass
3745 00:18:39.437373 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_21 RESULT=pass>
3746 00:18:39.438241 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_21 RESULT=pass
3748 00:18:39.487660 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_21 RESULT=pass>
3749 00:18:39.488587 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_21 RESULT=pass
3751 00:18:39.537981 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_21 RESULT=pass>
3752 00:18:39.538844 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_21 RESULT=pass
3754 00:18:39.594460 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_21 RESULT=pass>
3755 00:18:39.595335 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_21 RESULT=pass
3757 00:18:39.652977 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_20 RESULT=pass>
3758 00:18:39.653847 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_20 RESULT=pass
3760 00:18:39.700429 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_20 RESULT=pass>
3761 00:18:39.701278 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_20 RESULT=pass
3763 00:18:39.752760 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_20 RESULT=pass>
3764 00:18:39.753660 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_20 RESULT=pass
3766 00:18:39.818064 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_20 RESULT=pass>
3767 00:18:39.818918 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_20 RESULT=pass
3769 00:18:39.862996 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_20 RESULT=pass>
3770 00:18:39.863852 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_20 RESULT=pass
3772 00:18:39.909708 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_20 RESULT=pass>
3773 00:18:39.910445 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_20 RESULT=pass
3775 00:18:39.968594 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_20 RESULT=pass>
3776 00:18:39.969430 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_20 RESULT=pass
3778 00:18:40.013336 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_19 RESULT=pass>
3779 00:18:40.014078 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_19 RESULT=pass
3781 00:18:40.057504 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_19 RESULT=pass>
3782 00:18:40.058322 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_19 RESULT=pass
3784 00:18:40.105313 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_19 RESULT=pass>
3785 00:18:40.105973 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_19 RESULT=pass
3787 00:18:40.152988 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_19 RESULT=pass>
3788 00:18:40.153646 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_19 RESULT=pass
3790 00:18:40.201582 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_19 RESULT=pass>
3791 00:18:40.202277 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_19 RESULT=pass
3793 00:18:40.249564 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_19 RESULT=pass>
3794 00:18:40.250190 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_19 RESULT=pass
3796 00:18:40.305692 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_19 RESULT=pass>
3797 00:18:40.306467 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_19 RESULT=pass
3799 00:18:40.350913 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_18 RESULT=pass>
3800 00:18:40.351697 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_18 RESULT=pass
3802 00:18:40.402381 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_18 RESULT=pass>
3803 00:18:40.403113 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_18 RESULT=pass
3805 00:18:40.448034 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_18 RESULT=pass>
3806 00:18:40.448843 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_18 RESULT=pass
3808 00:18:40.500258 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_18 RESULT=pass>
3809 00:18:40.500989 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_18 RESULT=pass
3811 00:18:40.553658 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_18 RESULT=pass>
3812 00:18:40.554452 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_18 RESULT=pass
3814 00:18:40.605777 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_18 RESULT=pass>
3815 00:18:40.606536 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_18 RESULT=pass
3817 00:18:40.663334 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_18 RESULT=pass>
3818 00:18:40.664146 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_18 RESULT=pass
3820 00:18:40.714831 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_17 RESULT=pass>
3821 00:18:40.715557 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_17 RESULT=pass
3823 00:18:40.778756 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_17 RESULT=pass>
3824 00:18:40.779620 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_17 RESULT=pass
3826 00:18:40.824985 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_17 RESULT=pass>
3827 00:18:40.825846 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_17 RESULT=pass
3829 00:18:40.875856 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_17 RESULT=pass>
3830 00:18:40.876757 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_17 RESULT=pass
3832 00:18:40.926676 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_17 RESULT=pass>
3833 00:18:40.927427 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_17 RESULT=pass
3835 00:18:40.985587 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_17 RESULT=pass>
3836 00:18:40.986419 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_17 RESULT=pass
3838 00:18:41.032146 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_17 RESULT=pass>
3839 00:18:41.033005 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_17 RESULT=pass
3841 00:18:41.077125 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_16 RESULT=pass>
3842 00:18:41.078001 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_16 RESULT=pass
3844 00:18:41.131886 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_16 RESULT=pass>
3845 00:18:41.132737 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_16 RESULT=pass
3847 00:18:41.186557 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_16 RESULT=pass>
3848 00:18:41.187350 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_16 RESULT=pass
3850 00:18:41.240843 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_16 RESULT=pass>
3851 00:18:41.241638 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_16 RESULT=pass
3853 00:18:41.285949 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_16 RESULT=pass>
3854 00:18:41.286767 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_16 RESULT=pass
3856 00:18:41.335522 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_16 RESULT=pass>
3857 00:18:41.336329 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_16 RESULT=pass
3859 00:18:41.386834 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_16 RESULT=pass>
3860 00:18:41.387649 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_16 RESULT=pass
3862 00:18:41.437432 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_15 RESULT=pass>
3863 00:18:41.438170 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_15 RESULT=pass
3865 00:18:41.491434 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_15 RESULT=pass>
3866 00:18:41.492303 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_15 RESULT=pass
3868 00:18:41.538253 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_15 RESULT=pass>
3869 00:18:41.538996 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_15 RESULT=pass
3871 00:18:41.594077 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_15 RESULT=pass>
3872 00:18:41.594882 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_15 RESULT=pass
3874 00:18:41.652324 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_15 RESULT=pass>
3875 00:18:41.653069 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_15 RESULT=pass
3877 00:18:41.698091 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_15 RESULT=pass>
3878 00:18:41.698907 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_15 RESULT=pass
3880 00:18:41.752866 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_15 RESULT=pass>
3881 00:18:41.753637 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_15 RESULT=pass
3883 00:18:41.796896 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_14 RESULT=pass>
3884 00:18:41.797717 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_14 RESULT=pass
3886 00:18:41.842799 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_14 RESULT=pass>
3887 00:18:41.843438 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_14 RESULT=pass
3889 00:18:41.898727 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_14 RESULT=pass>
3890 00:18:41.899654 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_14 RESULT=pass
3892 00:18:41.953942 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_14 RESULT=pass>
3893 00:18:41.954837 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_14 RESULT=pass
3895 00:18:42.005127 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_14 RESULT=pass>
3896 00:18:42.005999 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_14 RESULT=pass
3898 00:18:42.056718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_14 RESULT=pass>
3899 00:18:42.057597 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_14 RESULT=pass
3901 00:18:42.108368 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_14 RESULT=pass>
3902 00:18:42.109259 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_14 RESULT=pass
3904 00:18:42.162461 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_13 RESULT=pass>
3905 00:18:42.163357 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_13 RESULT=pass
3907 00:18:42.221270 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_13 RESULT=pass>
3908 00:18:42.222312 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_13 RESULT=pass
3910 00:18:42.273552 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_13 RESULT=pass>
3911 00:18:42.274198 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_13 RESULT=pass
3913 00:18:42.319930 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_13 RESULT=pass>
3914 00:18:42.320601 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_13 RESULT=pass
3916 00:18:42.370710 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_13 RESULT=pass>
3917 00:18:42.371367 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_13 RESULT=pass
3919 00:18:42.420694 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_13 RESULT=pass>
3920 00:18:42.421367 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_13 RESULT=pass
3922 00:18:42.628099 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_13 RESULT=pass>
3923 00:18:42.628724 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_13 RESULT=pass
3925 00:18:42.673486 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_12 RESULT=pass>
3926 00:18:42.674306 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_12 RESULT=pass
3928 00:18:42.728094 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_12 RESULT=pass>
3929 00:18:42.728955 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_12 RESULT=pass
3931 00:18:42.789903 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_12 RESULT=pass>
3932 00:18:42.790758 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_12 RESULT=pass
3934 00:18:42.834321 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_12 RESULT=pass>
3935 00:18:42.835166 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_12 RESULT=pass
3937 00:18:42.889862 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_12 RESULT=pass>
3938 00:18:42.890774 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_12 RESULT=pass
3940 00:18:42.944755 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_12 RESULT=pass>
3941 00:18:42.945696 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_12 RESULT=pass
3943 00:18:42.990797 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_12 RESULT=pass>
3944 00:18:42.991678 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_12 RESULT=pass
3946 00:18:43.045312 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_11 RESULT=pass>
3947 00:18:43.046168 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_11 RESULT=pass
3949 00:18:43.095175 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_11 RESULT=pass>
3950 00:18:43.096109 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_11 RESULT=pass
3952 00:18:43.146557 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_11 RESULT=pass>
3953 00:18:43.147396 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_11 RESULT=pass
3955 00:18:43.202231 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_11 RESULT=pass>
3956 00:18:43.203156 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_11 RESULT=pass
3958 00:18:43.256948 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_11 RESULT=pass>
3959 00:18:43.257608 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_11 RESULT=pass
3961 00:18:43.301781 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_11 RESULT=pass>
3962 00:18:43.302430 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_11 RESULT=pass
3964 00:18:43.353787 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_11 RESULT=pass>
3965 00:18:43.354730 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_11 RESULT=pass
3967 00:18:43.408875 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_10 RESULT=pass>
3968 00:18:43.409793 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_10 RESULT=pass
3970 00:18:43.464667 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_10 RESULT=pass>
3971 00:18:43.465533 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_10 RESULT=pass
3973 00:18:43.515518 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_10 RESULT=pass>
3974 00:18:43.516416 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_10 RESULT=pass
3976 00:18:43.568414 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_10 RESULT=pass>
3977 00:18:43.569293 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_10 RESULT=pass
3979 00:18:43.622851 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_10 RESULT=pass>
3980 00:18:43.623707 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_10 RESULT=pass
3982 00:18:43.668820 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_10 RESULT=pass>
3983 00:18:43.669757 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_10 RESULT=pass
3985 00:18:43.720884 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_10 RESULT=pass>
3986 00:18:43.721811 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_10 RESULT=pass
3988 00:18:43.772243 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_9 RESULT=pass>
3989 00:18:43.773250 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_9 RESULT=pass
3991 00:18:43.822447 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_9 RESULT=pass>
3992 00:18:43.823522 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_9 RESULT=pass
3994 00:18:43.870096 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_9 RESULT=pass>
3995 00:18:43.871021 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_9 RESULT=pass
3997 00:18:43.934298 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_9 RESULT=pass>
3998 00:18:43.935202 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_9 RESULT=pass
4000 00:18:43.987449 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_9 RESULT=pass>
4001 00:18:43.988373 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_9 RESULT=pass
4003 00:18:44.033834 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_9 RESULT=pass>
4004 00:18:44.034647 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_9 RESULT=pass
4006 00:18:44.085227 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_9 RESULT=pass>
4007 00:18:44.086068 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_9 RESULT=pass
4009 00:18:44.142503 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_8 RESULT=pass>
4010 00:18:44.143300 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_8 RESULT=pass
4012 00:18:44.183886 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_8 RESULT=pass>
4013 00:18:44.184734 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_8 RESULT=pass
4015 00:18:44.233549 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_8 RESULT=pass>
4016 00:18:44.234351 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_8 RESULT=pass
4018 00:18:44.278128 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_8 RESULT=pass>
4019 00:18:44.279015 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_8 RESULT=pass
4021 00:18:44.341896 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_8 RESULT=pass>
4022 00:18:44.342718 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_8 RESULT=pass
4024 00:18:44.388128 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_8 RESULT=pass>
4025 00:18:44.388919 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_8 RESULT=pass
4027 00:18:44.442397 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_8 RESULT=pass>
4028 00:18:44.443175 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_8 RESULT=pass
4030 00:18:44.487190 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_7 RESULT=pass>
4031 00:18:44.488000 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_7 RESULT=pass
4033 00:18:44.532466 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_7 RESULT=pass>
4034 00:18:44.533273 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_7 RESULT=pass
4036 00:18:44.589968 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_7 RESULT=pass>
4037 00:18:44.590768 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_7 RESULT=pass
4039 00:18:44.643976 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_7 RESULT=pass>
4040 00:18:44.644787 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_7 RESULT=pass
4042 00:18:44.690553 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_7 RESULT=pass>
4043 00:18:44.691403 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_7 RESULT=pass
4045 00:18:44.744527 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_7 RESULT=pass>
4046 00:18:44.745310 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_7 RESULT=pass
4048 00:18:44.798195 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_7 RESULT=pass>
4049 00:18:44.799007 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_7 RESULT=pass
4051 00:18:44.856550 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_6 RESULT=pass>
4052 00:18:44.857331 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_6 RESULT=pass
4054 00:18:44.900990 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_6 RESULT=pass>
4055 00:18:44.901861 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_6 RESULT=pass
4057 00:18:44.959045 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_6 RESULT=pass>
4058 00:18:44.959828 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_6 RESULT=pass
4060 00:18:45.011129 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_6 RESULT=pass>
4061 00:18:45.011970 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_6 RESULT=pass
4063 00:18:45.066242 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_6 RESULT=pass>
4064 00:18:45.067050 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_6 RESULT=pass
4066 00:18:45.121086 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_6 RESULT=pass>
4067 00:18:45.121858 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_6 RESULT=pass
4069 00:18:45.188958 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_6 RESULT=pass>
4070 00:18:45.189770 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_6 RESULT=pass
4072 00:18:45.240088 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_5 RESULT=pass>
4073 00:18:45.240927 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_5 RESULT=pass
4075 00:18:45.291645 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_5 RESULT=pass>
4076 00:18:45.292473 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_5 RESULT=pass
4078 00:18:45.343713 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_5 RESULT=pass>
4079 00:18:45.344519 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_5 RESULT=pass
4081 00:18:45.388577 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_5 RESULT=pass>
4082 00:18:45.389362 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_5 RESULT=pass
4084 00:18:45.440520 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_5 RESULT=pass>
4085 00:18:45.441293 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_5 RESULT=pass
4087 00:18:45.493354 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_5 RESULT=pass>
4088 00:18:45.494171 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_5 RESULT=pass
4090 00:18:45.540113 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_5 RESULT=pass>
4091 00:18:45.540922 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_5 RESULT=pass
4093 00:18:45.599067 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_4 RESULT=pass>
4094 00:18:45.600411 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_4 RESULT=pass
4096 00:18:45.670608 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_4 RESULT=pass>
4097 00:18:45.671356 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_4 RESULT=pass
4099 00:18:45.729859 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_4 RESULT=pass>
4100 00:18:45.730796 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_4 RESULT=pass
4102 00:18:45.774745 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_4 RESULT=pass>
4103 00:18:45.775663 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_4 RESULT=pass
4105 00:18:45.830140 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_4 RESULT=pass>
4106 00:18:45.830951 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_4 RESULT=pass
4108 00:18:45.874668 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_4 RESULT=pass>
4109 00:18:45.875524 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_4 RESULT=pass
4111 00:18:45.925110 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_4 RESULT=pass>
4112 00:18:45.925956 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_4 RESULT=pass
4114 00:18:45.974089 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_3 RESULT=pass>
4115 00:18:45.974924 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_3 RESULT=pass
4117 00:18:46.023552 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_3 RESULT=pass>
4118 00:18:46.024377 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_3 RESULT=pass
4120 00:18:46.067355 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_3 RESULT=pass>
4121 00:18:46.068103 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_3 RESULT=pass
4123 00:18:46.118563 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_3 RESULT=pass>
4124 00:18:46.119305 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_3 RESULT=pass
4126 00:18:46.172759 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_3 RESULT=pass>
4127 00:18:46.173644 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_3 RESULT=pass
4129 00:18:46.223447 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_3 RESULT=pass>
4130 00:18:46.224273 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_3 RESULT=pass
4132 00:18:46.277237 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_3 RESULT=pass>
4133 00:18:46.277892 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_3 RESULT=pass
4135 00:18:46.327743 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_2 RESULT=pass>
4136 00:18:46.328669 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_2 RESULT=pass
4138 00:18:46.373509 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_2 RESULT=pass>
4139 00:18:46.374362 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_2 RESULT=pass
4141 00:18:46.426258 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_2 RESULT=pass>
4142 00:18:46.427103 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_2 RESULT=pass
4144 00:18:46.479011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_2 RESULT=pass>
4145 00:18:46.479887 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_2 RESULT=pass
4147 00:18:46.533300 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_2 RESULT=pass>
4148 00:18:46.534120 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_2 RESULT=pass
4150 00:18:46.581253 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_2 RESULT=pass>
4151 00:18:46.582074 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_2 RESULT=pass
4153 00:18:46.634888 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_2 RESULT=pass>
4154 00:18:46.635739 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_2 RESULT=pass
4156 00:18:46.679440 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_1 RESULT=pass>
4157 00:18:46.680225 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_1 RESULT=pass
4159 00:18:46.730515 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_1 RESULT=pass>
4160 00:18:46.731331 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_1 RESULT=pass
4162 00:18:46.784286 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_1 RESULT=pass>
4163 00:18:46.785060 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_1 RESULT=pass
4165 00:18:46.831330 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_1 RESULT=pass>
4166 00:18:46.832110 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_1 RESULT=pass
4168 00:18:46.886224 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_1 RESULT=pass>
4169 00:18:46.887030 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_1 RESULT=pass
4171 00:18:46.939904 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_1 RESULT=pass>
4172 00:18:46.940706 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_1 RESULT=pass
4174 00:18:46.988177 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_1 RESULT=pass>
4175 00:18:46.988935 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_1 RESULT=pass
4177 00:18:47.047478 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_0 RESULT=pass>
4178 00:18:47.048298 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_0 RESULT=pass
4180 00:18:47.099970 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_0 RESULT=pass>
4181 00:18:47.100798 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_0 RESULT=pass
4183 00:18:47.158073 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_0 RESULT=pass>
4184 00:18:47.158871 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_0 RESULT=pass
4186 00:18:47.210526 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_0 RESULT=pass>
4187 00:18:47.211305 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_0 RESULT=pass
4189 00:18:47.256748 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_0 RESULT=pass>
4190 00:18:47.257374 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_0 RESULT=pass
4192 00:18:47.309861 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_0 RESULT=pass>
4193 00:18:47.310754 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_0 RESULT=pass
4195 00:18:47.362747 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_0 RESULT=pass>
4196 00:18:47.363549 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_0 RESULT=pass
4198 00:18:47.406582 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test RESULT=pass
4200 00:18:47.409490 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test RESULT=pass>
4201 00:18:47.465226 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_5_0_CAPTURE RESULT=skip>
4202 00:18:47.465978 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_5_0_CAPTURE RESULT=skip
4204 00:18:47.517497 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_5_0_CAPTURE RESULT=skip>
4205 00:18:47.518265 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_5_0_CAPTURE RESULT=skip
4207 00:18:47.567757 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_5_0_CAPTURE RESULT=skip>
4208 00:18:47.568613 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_5_0_CAPTURE RESULT=skip
4210 00:18:47.618647 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_5_0_CAPTURE RESULT=skip>
4211 00:18:47.619410 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_5_0_CAPTURE RESULT=skip
4213 00:18:47.668191 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_5_0_CAPTURE RESULT=skip>
4214 00:18:47.668960 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_5_0_CAPTURE RESULT=skip
4216 00:18:47.720539 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_5_0_CAPTURE RESULT=skip>
4217 00:18:47.721294 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_5_0_CAPTURE RESULT=skip
4219 00:18:47.767424 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_5_0_CAPTURE RESULT=skip>
4220 00:18:47.768188 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_5_0_CAPTURE RESULT=skip
4222 00:18:47.810420 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_4_0_CAPTURE RESULT=skip>
4223 00:18:47.811349 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_4_0_CAPTURE RESULT=skip
4225 00:18:47.856056 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_4_0_CAPTURE RESULT=skip>
4226 00:18:47.856944 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_4_0_CAPTURE RESULT=skip
4228 00:18:47.908642 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_4_0_CAPTURE RESULT=skip>
4229 00:18:47.909489 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_4_0_CAPTURE RESULT=skip
4231 00:18:47.958129 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_4_0_CAPTURE RESULT=skip>
4232 00:18:47.958990 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_4_0_CAPTURE RESULT=skip
4234 00:18:48.008449 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_4_0_CAPTURE RESULT=skip>
4235 00:18:48.009256 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_4_0_CAPTURE RESULT=skip
4237 00:18:48.058122 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_4_0_CAPTURE RESULT=skip>
4238 00:18:48.058927 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_4_0_CAPTURE RESULT=skip
4240 00:18:48.108445 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_4_0_CAPTURE RESULT=skip>
4241 00:18:48.109210 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_4_0_CAPTURE RESULT=skip
4243 00:18:48.154099 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_3_0_CAPTURE RESULT=skip>
4244 00:18:48.154843 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_3_0_CAPTURE RESULT=skip
4246 00:18:48.196418 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_3_0_CAPTURE RESULT=skip>
4247 00:18:48.197166 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_3_0_CAPTURE RESULT=skip
4249 00:18:48.250505 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_3_0_CAPTURE RESULT=skip>
4250 00:18:48.251275 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_3_0_CAPTURE RESULT=skip
4252 00:18:48.301146 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_3_0_CAPTURE RESULT=skip>
4253 00:18:48.301923 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_3_0_CAPTURE RESULT=skip
4255 00:18:48.354109 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_3_0_CAPTURE RESULT=skip>
4256 00:18:48.354858 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_3_0_CAPTURE RESULT=skip
4258 00:18:48.409486 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_3_0_CAPTURE RESULT=skip>
4259 00:18:48.410250 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_3_0_CAPTURE RESULT=skip
4261 00:18:48.452717 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_3_0_CAPTURE RESULT=skip>
4262 00:18:48.453556 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_3_0_CAPTURE RESULT=skip
4264 00:18:48.502245 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_2_0_PLAYBACK RESULT=skip>
4265 00:18:48.503051 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_2_0_PLAYBACK RESULT=skip
4267 00:18:48.546590 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_2_0_PLAYBACK RESULT=skip>
4268 00:18:48.547360 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_2_0_PLAYBACK RESULT=skip
4270 00:18:48.597485 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_2_0_PLAYBACK RESULT=skip>
4271 00:18:48.598269 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_2_0_PLAYBACK RESULT=skip
4273 00:18:48.654110 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_2_0_PLAYBACK RESULT=skip>
4274 00:18:48.654944 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_2_0_PLAYBACK RESULT=skip
4276 00:18:48.703143 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_2_0_PLAYBACK RESULT=skip>
4277 00:18:48.703913 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_2_0_PLAYBACK RESULT=skip
4279 00:18:48.756173 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_2_0_PLAYBACK RESULT=skip>
4280 00:18:48.756975 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_2_0_PLAYBACK RESULT=skip
4282 00:18:48.801471 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_2_0_PLAYBACK RESULT=skip>
4283 00:18:48.802434 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_2_0_PLAYBACK RESULT=skip
4285 00:18:48.857400 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_1_0_PLAYBACK RESULT=skip>
4286 00:18:48.858318 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_1_0_PLAYBACK RESULT=skip
4288 00:18:48.907005 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_1_0_PLAYBACK RESULT=skip>
4289 00:18:48.907790 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_1_0_PLAYBACK RESULT=skip
4291 00:18:48.969603 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_1_0_PLAYBACK RESULT=skip>
4292 00:18:48.970408 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_1_0_PLAYBACK RESULT=skip
4294 00:18:49.025174 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_1_0_PLAYBACK RESULT=skip>
4295 00:18:49.025982 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_1_0_PLAYBACK RESULT=skip
4297 00:18:49.075574 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_1_0_PLAYBACK RESULT=skip>
4298 00:18:49.076408 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_1_0_PLAYBACK RESULT=skip
4300 00:18:49.118326 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_1_0_PLAYBACK RESULT=skip>
4301 00:18:49.119100 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_1_0_PLAYBACK RESULT=skip
4303 00:18:49.170322 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_1_0_PLAYBACK RESULT=skip>
4304 00:18:49.171099 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_1_0_PLAYBACK RESULT=skip
4306 00:18:49.219097 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_0_0_PLAYBACK RESULT=skip>
4307 00:18:49.219891 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_0_0_PLAYBACK RESULT=skip
4309 00:18:49.279095 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_0_0_PLAYBACK RESULT=skip>
4310 00:18:49.279888 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_0_0_PLAYBACK RESULT=skip
4312 00:18:49.334155 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_0_0_PLAYBACK RESULT=skip>
4313 00:18:49.334937 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_0_0_PLAYBACK RESULT=skip
4315 00:18:49.377779 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_0_0_PLAYBACK RESULT=skip>
4316 00:18:49.378588 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_0_0_PLAYBACK RESULT=skip
4318 00:18:49.423374 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_0_0_PLAYBACK RESULT=skip>
4319 00:18:49.424154 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_0_0_PLAYBACK RESULT=skip
4321 00:18:49.472084 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_0_0_PLAYBACK RESULT=skip>
4322 00:18:49.472898 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_0_0_PLAYBACK RESULT=skip
4324 00:18:49.525933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_0_0_PLAYBACK RESULT=skip>
4325 00:18:49.526739 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_0_0_PLAYBACK RESULT=skip
4327 00:18:49.568770 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test RESULT=pass>
4328 00:18:49.569639 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test RESULT=pass
4330 00:18:49.631859 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_playback_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip>
4331 00:18:49.632703 Received signal: <TESTCASE> TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_playback_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip
4333 00:18:49.677692 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_capture_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip>
4334 00:18:49.678492 Received signal: <TESTCASE> TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_capture_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip
4336 00:18:49.726735 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_ni_capture_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip>
4337 00:18:49.727511 Received signal: <TESTCASE> TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_ni_capture_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip
4339 00:18:49.776387 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_ni_playback_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip>
4340 00:18:49.777169 Received signal: <TESTCASE> TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_ni_playback_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip
4342 00:18:49.827669 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_reset_ioctl_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip>
4343 00:18:49.828469 Received signal: <TESTCASE> TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_reset_ioctl_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip
4345 00:18:49.870233 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_test-pcmtest-driver RESULT=pass>
4346 00:18:49.871033 Received signal: <TESTCASE> TEST_CASE_ID=alsa_test-pcmtest-driver RESULT=pass
4348 00:18:49.923152 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_utimer-test_global_wrong_timers_test RESULT=pass>
4349 00:18:49.923962 Received signal: <TESTCASE> TEST_CASE_ID=alsa_utimer-test_global_wrong_timers_test RESULT=pass
4351 00:18:49.972703 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_utimer-test_timer_f_utimer RESULT=fail>
4352 00:18:49.973505 Received signal: <TESTCASE> TEST_CASE_ID=alsa_utimer-test_timer_f_utimer RESULT=fail
4354 00:18:50.019770 Received signal: <TESTCASE> TEST_CASE_ID=alsa_utimer-test RESULT=fail
4356 00:18:50.025020 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_utimer-test RESULT=fail>
4357 00:18:50.025534 + set +x
4358 00:18:50.030908 <LAVA_SIGNAL_ENDRUN 1_kselftest-alsa 919150_1.6.2.4.5>
4359 00:18:50.031393 <LAVA_TEST_RUNNER EXIT>
4360 00:18:50.032094 Received signal: <ENDRUN> 1_kselftest-alsa 919150_1.6.2.4.5
4361 00:18:50.032584 Ending use of test pattern.
4362 00:18:50.033034 Ending test lava.1_kselftest-alsa (919150_1.6.2.4.5), duration 40.53
4364 00:18:50.034669 ok: lava_test_shell seems to have completed
4365 00:18:50.059163 alsa_mixer-test: pass
alsa_mixer-test_event_missing_LCALTA_0: pass
alsa_mixer-test_event_missing_LCALTA_1: pass
alsa_mixer-test_event_missing_LCALTA_10: pass
alsa_mixer-test_event_missing_LCALTA_11: pass
alsa_mixer-test_event_missing_LCALTA_12: pass
alsa_mixer-test_event_missing_LCALTA_13: pass
alsa_mixer-test_event_missing_LCALTA_14: pass
alsa_mixer-test_event_missing_LCALTA_15: pass
alsa_mixer-test_event_missing_LCALTA_16: pass
alsa_mixer-test_event_missing_LCALTA_17: pass
alsa_mixer-test_event_missing_LCALTA_18: pass
alsa_mixer-test_event_missing_LCALTA_19: pass
alsa_mixer-test_event_missing_LCALTA_2: pass
alsa_mixer-test_event_missing_LCALTA_20: pass
alsa_mixer-test_event_missing_LCALTA_21: pass
alsa_mixer-test_event_missing_LCALTA_22: pass
alsa_mixer-test_event_missing_LCALTA_23: pass
alsa_mixer-test_event_missing_LCALTA_24: pass
alsa_mixer-test_event_missing_LCALTA_25: pass
alsa_mixer-test_event_missing_LCALTA_26: pass
alsa_mixer-test_event_missing_LCALTA_27: pass
alsa_mixer-test_event_missing_LCALTA_28: pass
alsa_mixer-test_event_missing_LCALTA_29: pass
alsa_mixer-test_event_missing_LCALTA_3: pass
alsa_mixer-test_event_missing_LCALTA_30: pass
alsa_mixer-test_event_missing_LCALTA_31: pass
alsa_mixer-test_event_missing_LCALTA_32: pass
alsa_mixer-test_event_missing_LCALTA_33: pass
alsa_mixer-test_event_missing_LCALTA_34: pass
alsa_mixer-test_event_missing_LCALTA_35: pass
alsa_mixer-test_event_missing_LCALTA_36: pass
alsa_mixer-test_event_missing_LCALTA_37: pass
alsa_mixer-test_event_missing_LCALTA_38: pass
alsa_mixer-test_event_missing_LCALTA_39: pass
alsa_mixer-test_event_missing_LCALTA_4: pass
alsa_mixer-test_event_missing_LCALTA_40: pass
alsa_mixer-test_event_missing_LCALTA_41: pass
alsa_mixer-test_event_missing_LCALTA_42: pass
alsa_mixer-test_event_missing_LCALTA_43: pass
alsa_mixer-test_event_missing_LCALTA_44: pass
alsa_mixer-test_event_missing_LCALTA_45: pass
alsa_mixer-test_event_missing_LCALTA_46: pass
alsa_mixer-test_event_missing_LCALTA_47: pass
alsa_mixer-test_event_missing_LCALTA_48: pass
alsa_mixer-test_event_missing_LCALTA_49: pass
alsa_mixer-test_event_missing_LCALTA_5: pass
alsa_mixer-test_event_missing_LCALTA_50: pass
alsa_mixer-test_event_missing_LCALTA_51: pass
alsa_mixer-test_event_missing_LCALTA_52: pass
alsa_mixer-test_event_missing_LCALTA_53: pass
alsa_mixer-test_event_missing_LCALTA_54: pass
alsa_mixer-test_event_missing_LCALTA_55: pass
alsa_mixer-test_event_missing_LCALTA_56: pass
alsa_mixer-test_event_missing_LCALTA_57: pass
alsa_mixer-test_event_missing_LCALTA_58: pass
alsa_mixer-test_event_missing_LCALTA_59: pass
alsa_mixer-test_event_missing_LCALTA_6: pass
alsa_mixer-test_event_missing_LCALTA_60: pass
alsa_mixer-test_event_missing_LCALTA_7: pass
alsa_mixer-test_event_missing_LCALTA_8: pass
alsa_mixer-test_event_missing_LCALTA_9: pass
alsa_mixer-test_event_spurious_LCALTA_0: pass
alsa_mixer-test_event_spurious_LCALTA_1: pass
alsa_mixer-test_event_spurious_LCALTA_10: pass
alsa_mixer-test_event_spurious_LCALTA_11: pass
alsa_mixer-test_event_spurious_LCALTA_12: pass
alsa_mixer-test_event_spurious_LCALTA_13: pass
alsa_mixer-test_event_spurious_LCALTA_14: pass
alsa_mixer-test_event_spurious_LCALTA_15: pass
alsa_mixer-test_event_spurious_LCALTA_16: pass
alsa_mixer-test_event_spurious_LCALTA_17: pass
alsa_mixer-test_event_spurious_LCALTA_18: pass
alsa_mixer-test_event_spurious_LCALTA_19: pass
alsa_mixer-test_event_spurious_LCALTA_2: pass
alsa_mixer-test_event_spurious_LCALTA_20: pass
alsa_mixer-test_event_spurious_LCALTA_21: pass
alsa_mixer-test_event_spurious_LCALTA_22: pass
alsa_mixer-test_event_spurious_LCALTA_23: pass
alsa_mixer-test_event_spurious_LCALTA_24: pass
alsa_mixer-test_event_spurious_LCALTA_25: pass
alsa_mixer-test_event_spurious_LCALTA_26: pass
alsa_mixer-test_event_spurious_LCALTA_27: pass
alsa_mixer-test_event_spurious_LCALTA_28: pass
alsa_mixer-test_event_spurious_LCALTA_29: pass
alsa_mixer-test_event_spurious_LCALTA_3: pass
alsa_mixer-test_event_spurious_LCALTA_30: pass
alsa_mixer-test_event_spurious_LCALTA_31: pass
alsa_mixer-test_event_spurious_LCALTA_32: pass
alsa_mixer-test_event_spurious_LCALTA_33: pass
alsa_mixer-test_event_spurious_LCALTA_34: pass
alsa_mixer-test_event_spurious_LCALTA_35: pass
alsa_mixer-test_event_spurious_LCALTA_36: pass
alsa_mixer-test_event_spurious_LCALTA_37: pass
alsa_mixer-test_event_spurious_LCALTA_38: pass
alsa_mixer-test_event_spurious_LCALTA_39: pass
alsa_mixer-test_event_spurious_LCALTA_4: pass
alsa_mixer-test_event_spurious_LCALTA_40: pass
alsa_mixer-test_event_spurious_LCALTA_41: pass
alsa_mixer-test_event_spurious_LCALTA_42: pass
alsa_mixer-test_event_spurious_LCALTA_43: pass
alsa_mixer-test_event_spurious_LCALTA_44: pass
alsa_mixer-test_event_spurious_LCALTA_45: pass
alsa_mixer-test_event_spurious_LCALTA_46: pass
alsa_mixer-test_event_spurious_LCALTA_47: pass
alsa_mixer-test_event_spurious_LCALTA_48: pass
alsa_mixer-test_event_spurious_LCALTA_49: pass
alsa_mixer-test_event_spurious_LCALTA_5: pass
alsa_mixer-test_event_spurious_LCALTA_50: pass
alsa_mixer-test_event_spurious_LCALTA_51: pass
alsa_mixer-test_event_spurious_LCALTA_52: pass
alsa_mixer-test_event_spurious_LCALTA_53: pass
alsa_mixer-test_event_spurious_LCALTA_54: pass
alsa_mixer-test_event_spurious_LCALTA_55: pass
alsa_mixer-test_event_spurious_LCALTA_56: pass
alsa_mixer-test_event_spurious_LCALTA_57: pass
alsa_mixer-test_event_spurious_LCALTA_58: pass
alsa_mixer-test_event_spurious_LCALTA_59: pass
alsa_mixer-test_event_spurious_LCALTA_6: pass
alsa_mixer-test_event_spurious_LCALTA_60: pass
alsa_mixer-test_event_spurious_LCALTA_7: pass
alsa_mixer-test_event_spurious_LCALTA_8: pass
alsa_mixer-test_event_spurious_LCALTA_9: pass
alsa_mixer-test_get_value_LCALTA_0: pass
alsa_mixer-test_get_value_LCALTA_1: pass
alsa_mixer-test_get_value_LCALTA_10: pass
alsa_mixer-test_get_value_LCALTA_11: pass
alsa_mixer-test_get_value_LCALTA_12: pass
alsa_mixer-test_get_value_LCALTA_13: pass
alsa_mixer-test_get_value_LCALTA_14: pass
alsa_mixer-test_get_value_LCALTA_15: pass
alsa_mixer-test_get_value_LCALTA_16: pass
alsa_mixer-test_get_value_LCALTA_17: pass
alsa_mixer-test_get_value_LCALTA_18: pass
alsa_mixer-test_get_value_LCALTA_19: pass
alsa_mixer-test_get_value_LCALTA_2: pass
alsa_mixer-test_get_value_LCALTA_20: pass
alsa_mixer-test_get_value_LCALTA_21: pass
alsa_mixer-test_get_value_LCALTA_22: pass
alsa_mixer-test_get_value_LCALTA_23: pass
alsa_mixer-test_get_value_LCALTA_24: pass
alsa_mixer-test_get_value_LCALTA_25: pass
alsa_mixer-test_get_value_LCALTA_26: pass
alsa_mixer-test_get_value_LCALTA_27: pass
alsa_mixer-test_get_value_LCALTA_28: pass
alsa_mixer-test_get_value_LCALTA_29: pass
alsa_mixer-test_get_value_LCALTA_3: pass
alsa_mixer-test_get_value_LCALTA_30: pass
alsa_mixer-test_get_value_LCALTA_31: pass
alsa_mixer-test_get_value_LCALTA_32: pass
alsa_mixer-test_get_value_LCALTA_33: pass
alsa_mixer-test_get_value_LCALTA_34: pass
alsa_mixer-test_get_value_LCALTA_35: pass
alsa_mixer-test_get_value_LCALTA_36: pass
alsa_mixer-test_get_value_LCALTA_37: pass
alsa_mixer-test_get_value_LCALTA_38: pass
alsa_mixer-test_get_value_LCALTA_39: pass
alsa_mixer-test_get_value_LCALTA_4: pass
alsa_mixer-test_get_value_LCALTA_40: pass
alsa_mixer-test_get_value_LCALTA_41: pass
alsa_mixer-test_get_value_LCALTA_42: pass
alsa_mixer-test_get_value_LCALTA_43: pass
alsa_mixer-test_get_value_LCALTA_44: pass
alsa_mixer-test_get_value_LCALTA_45: pass
alsa_mixer-test_get_value_LCALTA_46: pass
alsa_mixer-test_get_value_LCALTA_47: pass
alsa_mixer-test_get_value_LCALTA_48: pass
alsa_mixer-test_get_value_LCALTA_49: pass
alsa_mixer-test_get_value_LCALTA_5: pass
alsa_mixer-test_get_value_LCALTA_50: pass
alsa_mixer-test_get_value_LCALTA_51: pass
alsa_mixer-test_get_value_LCALTA_52: pass
alsa_mixer-test_get_value_LCALTA_53: pass
alsa_mixer-test_get_value_LCALTA_54: pass
alsa_mixer-test_get_value_LCALTA_55: pass
alsa_mixer-test_get_value_LCALTA_56: pass
alsa_mixer-test_get_value_LCALTA_57: pass
alsa_mixer-test_get_value_LCALTA_58: pass
alsa_mixer-test_get_value_LCALTA_59: pass
alsa_mixer-test_get_value_LCALTA_6: pass
alsa_mixer-test_get_value_LCALTA_60: pass
alsa_mixer-test_get_value_LCALTA_7: pass
alsa_mixer-test_get_value_LCALTA_8: pass
alsa_mixer-test_get_value_LCALTA_9: pass
alsa_mixer-test_name_LCALTA_0: pass
alsa_mixer-test_name_LCALTA_1: pass
alsa_mixer-test_name_LCALTA_10: pass
alsa_mixer-test_name_LCALTA_11: pass
alsa_mixer-test_name_LCALTA_12: pass
alsa_mixer-test_name_LCALTA_13: pass
alsa_mixer-test_name_LCALTA_14: pass
alsa_mixer-test_name_LCALTA_15: pass
alsa_mixer-test_name_LCALTA_16: pass
alsa_mixer-test_name_LCALTA_17: pass
alsa_mixer-test_name_LCALTA_18: pass
alsa_mixer-test_name_LCALTA_19: pass
alsa_mixer-test_name_LCALTA_2: pass
alsa_mixer-test_name_LCALTA_20: pass
alsa_mixer-test_name_LCALTA_21: pass
alsa_mixer-test_name_LCALTA_22: pass
alsa_mixer-test_name_LCALTA_23: pass
alsa_mixer-test_name_LCALTA_24: pass
alsa_mixer-test_name_LCALTA_25: pass
alsa_mixer-test_name_LCALTA_26: pass
alsa_mixer-test_name_LCALTA_27: pass
alsa_mixer-test_name_LCALTA_28: pass
alsa_mixer-test_name_LCALTA_29: pass
alsa_mixer-test_name_LCALTA_3: pass
alsa_mixer-test_name_LCALTA_30: pass
alsa_mixer-test_name_LCALTA_31: pass
alsa_mixer-test_name_LCALTA_32: pass
alsa_mixer-test_name_LCALTA_33: pass
alsa_mixer-test_name_LCALTA_34: pass
alsa_mixer-test_name_LCALTA_35: pass
alsa_mixer-test_name_LCALTA_36: pass
alsa_mixer-test_name_LCALTA_37: pass
alsa_mixer-test_name_LCALTA_38: pass
alsa_mixer-test_name_LCALTA_39: pass
alsa_mixer-test_name_LCALTA_4: pass
alsa_mixer-test_name_LCALTA_40: pass
alsa_mixer-test_name_LCALTA_41: pass
alsa_mixer-test_name_LCALTA_42: pass
alsa_mixer-test_name_LCALTA_43: pass
alsa_mixer-test_name_LCALTA_44: pass
alsa_mixer-test_name_LCALTA_45: pass
alsa_mixer-test_name_LCALTA_46: pass
alsa_mixer-test_name_LCALTA_47: pass
alsa_mixer-test_name_LCALTA_48: pass
alsa_mixer-test_name_LCALTA_49: pass
alsa_mixer-test_name_LCALTA_5: pass
alsa_mixer-test_name_LCALTA_50: pass
alsa_mixer-test_name_LCALTA_51: pass
alsa_mixer-test_name_LCALTA_52: pass
alsa_mixer-test_name_LCALTA_53: pass
alsa_mixer-test_name_LCALTA_54: pass
alsa_mixer-test_name_LCALTA_55: pass
alsa_mixer-test_name_LCALTA_56: pass
alsa_mixer-test_name_LCALTA_57: pass
alsa_mixer-test_name_LCALTA_58: pass
alsa_mixer-test_name_LCALTA_59: pass
alsa_mixer-test_name_LCALTA_6: pass
alsa_mixer-test_name_LCALTA_60: pass
alsa_mixer-test_name_LCALTA_7: pass
alsa_mixer-test_name_LCALTA_8: pass
alsa_mixer-test_name_LCALTA_9: pass
alsa_mixer-test_write_default_LCALTA_0: pass
alsa_mixer-test_write_default_LCALTA_1: pass
alsa_mixer-test_write_default_LCALTA_10: pass
alsa_mixer-test_write_default_LCALTA_11: pass
alsa_mixer-test_write_default_LCALTA_12: pass
alsa_mixer-test_write_default_LCALTA_13: pass
alsa_mixer-test_write_default_LCALTA_14: pass
alsa_mixer-test_write_default_LCALTA_15: pass
alsa_mixer-test_write_default_LCALTA_16: pass
alsa_mixer-test_write_default_LCALTA_17: pass
alsa_mixer-test_write_default_LCALTA_18: pass
alsa_mixer-test_write_default_LCALTA_19: pass
alsa_mixer-test_write_default_LCALTA_2: pass
alsa_mixer-test_write_default_LCALTA_20: pass
alsa_mixer-test_write_default_LCALTA_21: pass
alsa_mixer-test_write_default_LCALTA_22: pass
alsa_mixer-test_write_default_LCALTA_23: skip
alsa_mixer-test_write_default_LCALTA_24: skip
alsa_mixer-test_write_default_LCALTA_25: pass
alsa_mixer-test_write_default_LCALTA_26: skip
alsa_mixer-test_write_default_LCALTA_27: pass
alsa_mixer-test_write_default_LCALTA_28: pass
alsa_mixer-test_write_default_LCALTA_29: pass
alsa_mixer-test_write_default_LCALTA_3: pass
alsa_mixer-test_write_default_LCALTA_30: pass
alsa_mixer-test_write_default_LCALTA_31: pass
alsa_mixer-test_write_default_LCALTA_32: pass
alsa_mixer-test_write_default_LCALTA_33: pass
alsa_mixer-test_write_default_LCALTA_34: pass
alsa_mixer-test_write_default_LCALTA_35: pass
alsa_mixer-test_write_default_LCALTA_36: pass
alsa_mixer-test_write_default_LCALTA_37: pass
alsa_mixer-test_write_default_LCALTA_38: pass
alsa_mixer-test_write_default_LCALTA_39: pass
alsa_mixer-test_write_default_LCALTA_4: pass
alsa_mixer-test_write_default_LCALTA_40: pass
alsa_mixer-test_write_default_LCALTA_41: pass
alsa_mixer-test_write_default_LCALTA_42: pass
alsa_mixer-test_write_default_LCALTA_43: pass
alsa_mixer-test_write_default_LCALTA_44: pass
alsa_mixer-test_write_default_LCALTA_45: pass
alsa_mixer-test_write_default_LCALTA_46: pass
alsa_mixer-test_write_default_LCALTA_47: pass
alsa_mixer-test_write_default_LCALTA_48: pass
alsa_mixer-test_write_default_LCALTA_49: pass
alsa_mixer-test_write_default_LCALTA_5: pass
alsa_mixer-test_write_default_LCALTA_50: pass
alsa_mixer-test_write_default_LCALTA_51: pass
alsa_mixer-test_write_default_LCALTA_52: pass
alsa_mixer-test_write_default_LCALTA_53: pass
alsa_mixer-test_write_default_LCALTA_54: pass
alsa_mixer-test_write_default_LCALTA_55: pass
alsa_mixer-test_write_default_LCALTA_56: pass
alsa_mixer-test_write_default_LCALTA_57: pass
alsa_mixer-test_write_default_LCALTA_58: pass
alsa_mixer-test_write_default_LCALTA_59: pass
alsa_mixer-test_write_default_LCALTA_6: pass
alsa_mixer-test_write_default_LCALTA_60: pass
alsa_mixer-test_write_default_LCALTA_7: pass
alsa_mixer-test_write_default_LCALTA_8: pass
alsa_mixer-test_write_default_LCALTA_9: pass
alsa_mixer-test_write_invalid_LCALTA_0: pass
alsa_mixer-test_write_invalid_LCALTA_1: pass
alsa_mixer-test_write_invalid_LCALTA_10: pass
alsa_mixer-test_write_invalid_LCALTA_11: pass
alsa_mixer-test_write_invalid_LCALTA_12: pass
alsa_mixer-test_write_invalid_LCALTA_13: pass
alsa_mixer-test_write_invalid_LCALTA_14: pass
alsa_mixer-test_write_invalid_LCALTA_15: pass
alsa_mixer-test_write_invalid_LCALTA_16: pass
alsa_mixer-test_write_invalid_LCALTA_17: pass
alsa_mixer-test_write_invalid_LCALTA_18: pass
alsa_mixer-test_write_invalid_LCALTA_19: pass
alsa_mixer-test_write_invalid_LCALTA_2: pass
alsa_mixer-test_write_invalid_LCALTA_20: pass
alsa_mixer-test_write_invalid_LCALTA_21: pass
alsa_mixer-test_write_invalid_LCALTA_22: pass
alsa_mixer-test_write_invalid_LCALTA_23: skip
alsa_mixer-test_write_invalid_LCALTA_24: skip
alsa_mixer-test_write_invalid_LCALTA_25: skip
alsa_mixer-test_write_invalid_LCALTA_26: skip
alsa_mixer-test_write_invalid_LCALTA_27: pass
alsa_mixer-test_write_invalid_LCALTA_28: pass
alsa_mixer-test_write_invalid_LCALTA_29: pass
alsa_mixer-test_write_invalid_LCALTA_3: pass
alsa_mixer-test_write_invalid_LCALTA_30: pass
alsa_mixer-test_write_invalid_LCALTA_31: pass
alsa_mixer-test_write_invalid_LCALTA_32: pass
alsa_mixer-test_write_invalid_LCALTA_33: pass
alsa_mixer-test_write_invalid_LCALTA_34: pass
alsa_mixer-test_write_invalid_LCALTA_35: pass
alsa_mixer-test_write_invalid_LCALTA_36: pass
alsa_mixer-test_write_invalid_LCALTA_37: pass
alsa_mixer-test_write_invalid_LCALTA_38: pass
alsa_mixer-test_write_invalid_LCALTA_39: pass
alsa_mixer-test_write_invalid_LCALTA_4: pass
alsa_mixer-test_write_invalid_LCALTA_40: pass
alsa_mixer-test_write_invalid_LCALTA_41: pass
alsa_mixer-test_write_invalid_LCALTA_42: pass
alsa_mixer-test_write_invalid_LCALTA_43: pass
alsa_mixer-test_write_invalid_LCALTA_44: pass
alsa_mixer-test_write_invalid_LCALTA_45: pass
alsa_mixer-test_write_invalid_LCALTA_46: pass
alsa_mixer-test_write_invalid_LCALTA_47: pass
alsa_mixer-test_write_invalid_LCALTA_48: pass
alsa_mixer-test_write_invalid_LCALTA_49: pass
alsa_mixer-test_write_invalid_LCALTA_5: pass
alsa_mixer-test_write_invalid_LCALTA_50: pass
alsa_mixer-test_write_invalid_LCALTA_51: pass
alsa_mixer-test_write_invalid_LCALTA_52: pass
alsa_mixer-test_write_invalid_LCALTA_53: pass
alsa_mixer-test_write_invalid_LCALTA_54: pass
alsa_mixer-test_write_invalid_LCALTA_55: pass
alsa_mixer-test_write_invalid_LCALTA_56: pass
alsa_mixer-test_write_invalid_LCALTA_57: pass
alsa_mixer-test_write_invalid_LCALTA_58: pass
alsa_mixer-test_write_invalid_LCALTA_59: pass
alsa_mixer-test_write_invalid_LCALTA_6: pass
alsa_mixer-test_write_invalid_LCALTA_60: pass
alsa_mixer-test_write_invalid_LCALTA_7: pass
alsa_mixer-test_write_invalid_LCALTA_8: pass
alsa_mixer-test_write_invalid_LCALTA_9: pass
alsa_mixer-test_write_valid_LCALTA_0: pass
alsa_mixer-test_write_valid_LCALTA_1: pass
alsa_mixer-test_write_valid_LCALTA_10: pass
alsa_mixer-test_write_valid_LCALTA_11: pass
alsa_mixer-test_write_valid_LCALTA_12: pass
alsa_mixer-test_write_valid_LCALTA_13: pass
alsa_mixer-test_write_valid_LCALTA_14: pass
alsa_mixer-test_write_valid_LCALTA_15: pass
alsa_mixer-test_write_valid_LCALTA_16: pass
alsa_mixer-test_write_valid_LCALTA_17: pass
alsa_mixer-test_write_valid_LCALTA_18: pass
alsa_mixer-test_write_valid_LCALTA_19: pass
alsa_mixer-test_write_valid_LCALTA_2: pass
alsa_mixer-test_write_valid_LCALTA_20: pass
alsa_mixer-test_write_valid_LCALTA_21: pass
alsa_mixer-test_write_valid_LCALTA_22: pass
alsa_mixer-test_write_valid_LCALTA_23: skip
alsa_mixer-test_write_valid_LCALTA_24: skip
alsa_mixer-test_write_valid_LCALTA_25: skip
alsa_mixer-test_write_valid_LCALTA_26: skip
alsa_mixer-test_write_valid_LCALTA_27: pass
alsa_mixer-test_write_valid_LCALTA_28: pass
alsa_mixer-test_write_valid_LCALTA_29: pass
alsa_mixer-test_write_valid_LCALTA_3: pass
alsa_mixer-test_write_valid_LCALTA_30: pass
alsa_mixer-test_write_valid_LCALTA_31: pass
alsa_mixer-test_write_valid_LCALTA_32: pass
alsa_mixer-test_write_valid_LCALTA_33: pass
alsa_mixer-test_write_valid_LCALTA_34: pass
alsa_mixer-test_write_valid_LCALTA_35: pass
alsa_mixer-test_write_valid_LCALTA_36: pass
alsa_mixer-test_write_valid_LCALTA_37: pass
alsa_mixer-test_write_valid_LCALTA_38: pass
alsa_mixer-test_write_valid_LCALTA_39: pass
alsa_mixer-test_write_valid_LCALTA_4: pass
alsa_mixer-test_write_valid_LCALTA_40: pass
alsa_mixer-test_write_valid_LCALTA_41: pass
alsa_mixer-test_write_valid_LCALTA_42: pass
alsa_mixer-test_write_valid_LCALTA_43: pass
alsa_mixer-test_write_valid_LCALTA_44: pass
alsa_mixer-test_write_valid_LCALTA_45: pass
alsa_mixer-test_write_valid_LCALTA_46: pass
alsa_mixer-test_write_valid_LCALTA_47: pass
alsa_mixer-test_write_valid_LCALTA_48: pass
alsa_mixer-test_write_valid_LCALTA_49: pass
alsa_mixer-test_write_valid_LCALTA_5: pass
alsa_mixer-test_write_valid_LCALTA_50: pass
alsa_mixer-test_write_valid_LCALTA_51: pass
alsa_mixer-test_write_valid_LCALTA_52: pass
alsa_mixer-test_write_valid_LCALTA_53: pass
alsa_mixer-test_write_valid_LCALTA_54: pass
alsa_mixer-test_write_valid_LCALTA_55: pass
alsa_mixer-test_write_valid_LCALTA_56: pass
alsa_mixer-test_write_valid_LCALTA_57: pass
alsa_mixer-test_write_valid_LCALTA_58: pass
alsa_mixer-test_write_valid_LCALTA_59: pass
alsa_mixer-test_write_valid_LCALTA_6: pass
alsa_mixer-test_write_valid_LCALTA_60: pass
alsa_mixer-test_write_valid_LCALTA_7: pass
alsa_mixer-test_write_valid_LCALTA_8: pass
alsa_mixer-test_write_valid_LCALTA_9: pass
alsa_pcm-test: pass
alsa_pcm-test_default_time1_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time1_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time1_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time1_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time1_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time1_LCALTA_5_0_CAPTURE: skip
alsa_pcm-test_default_time2_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time2_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time2_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time2_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time2_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time2_LCALTA_5_0_CAPTURE: skip
alsa_pcm-test_default_time3_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time3_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time3_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time3_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time3_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time3_LCALTA_5_0_CAPTURE: skip
alsa_pcm-test_default_time4_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time4_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time4_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time4_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time4_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time4_LCALTA_5_0_CAPTURE: skip
alsa_pcm-test_default_time5_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time5_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time5_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time5_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time5_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time5_LCALTA_5_0_CAPTURE: skip
alsa_pcm-test_default_time6_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time6_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time6_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time6_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time6_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time6_LCALTA_5_0_CAPTURE: skip
alsa_pcm-test_default_time7_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time7_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time7_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time7_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time7_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time7_LCALTA_5_0_CAPTURE: skip
alsa_test-pcmtest-driver: pass
alsa_test-pcmtest-driver_pcmtest_capture_Can_t_read_patterns_Probably_module_isn_t_loaded: skip
alsa_test-pcmtest-driver_pcmtest_ni_capture_Can_t_read_patterns_Probably_module_isn_t_loaded: skip
alsa_test-pcmtest-driver_pcmtest_ni_playback_Can_t_read_patterns_Probably_module_isn_t_loaded: skip
alsa_test-pcmtest-driver_pcmtest_playback_Can_t_read_patterns_Probably_module_isn_t_loaded: skip
alsa_test-pcmtest-driver_pcmtest_reset_ioctl_Can_t_read_patterns_Probably_module_isn_t_loaded: skip
alsa_utimer-test: fail
alsa_utimer-test_global_wrong_timers_test: pass
alsa_utimer-test_timer_f_utimer: fail
shardfile-alsa: pass
4366 00:18:50.061064 end: 3.1 lava-test-shell (duration 00:00:41) [common]
4367 00:18:50.061682 end: 3 lava-test-retry (duration 00:00:41) [common]
4368 00:18:50.062296 start: 4 finalize (timeout 00:06:10) [common]
4369 00:18:50.062907 start: 4.1 power-off (timeout 00:00:30) [common]
4370 00:18:50.063907 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
4371 00:18:50.100430 >> OK - accepted request
4372 00:18:50.102592 Returned 0 in 0 seconds
4373 00:18:50.203824 end: 4.1 power-off (duration 00:00:00) [common]
4375 00:18:50.205707 start: 4.2 read-feedback (timeout 00:06:09) [common]
4376 00:18:50.206893 Listened to connection for namespace 'common' for up to 1s
4377 00:18:51.207627 Finalising connection for namespace 'common'
4378 00:18:51.208188 Disconnecting from shell: Finalise
4379 00:18:51.208511 / #
4380 00:18:51.309365 end: 4.2 read-feedback (duration 00:00:01) [common]
4381 00:18:51.310257 end: 4 finalize (duration 00:00:01) [common]
4382 00:18:51.311000 Cleaning after the job
4383 00:18:51.311722 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/919150/tftp-deploy-34_gl3d2/ramdisk
4384 00:18:51.316381 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/919150/tftp-deploy-34_gl3d2/kernel
4385 00:18:51.333297 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/919150/tftp-deploy-34_gl3d2/dtb
4386 00:18:51.335021 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/919150/tftp-deploy-34_gl3d2/nfsrootfs
4387 00:18:51.377398 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/919150/tftp-deploy-34_gl3d2/modules
4388 00:18:51.383769 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/919150
4389 00:18:55.167766 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/919150
4390 00:18:55.168798 Job finished correctly