Boot log: meson-sm1-s905d3-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 02:14:13.826047 lava-dispatcher, installed at version: 2024.01
2 02:14:13.827044 start: 0 validate
3 02:14:13.827613 Start time: 2024-11-04 02:14:13.827575+00:00 (UTC)
4 02:14:13.828361 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 02:14:13.829026 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230703.0%2Farm64%2Frootfs.cpio.gz exists
6 02:14:13.871006 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 02:14:13.871793 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fpending-fixes%2Fv6.12-rc5-576-g10616629aaf32%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 02:14:13.904731 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 02:14:13.905379 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fpending-fixes%2Fv6.12-rc5-576-g10616629aaf32%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-sm1-s905d3-libretech-cc.dtb exists
10 02:14:13.941648 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 02:14:13.942358 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fpending-fixes%2Fv6.12-rc5-576-g10616629aaf32%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
12 02:14:13.981629 validate duration: 0.15
14 02:14:13.982551 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 02:14:13.982883 start: 1.1 download-retry (timeout 00:10:00) [common]
16 02:14:13.983204 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 02:14:13.983834 Not decompressing ramdisk as can be used compressed.
18 02:14:13.984327 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230703.0/arm64/rootfs.cpio.gz
19 02:14:13.984609 saving as /var/lib/lava/dispatcher/tmp/932213/tftp-deploy-0alo0hjn/ramdisk/rootfs.cpio.gz
20 02:14:13.984886 total size: 8181887 (7 MB)
21 02:14:14.021857 progress 0 % (0 MB)
22 02:14:14.028121 progress 5 % (0 MB)
23 02:14:14.033528 progress 10 % (0 MB)
24 02:14:14.039161 progress 15 % (1 MB)
25 02:14:14.044371 progress 20 % (1 MB)
26 02:14:14.049991 progress 25 % (1 MB)
27 02:14:14.055120 progress 30 % (2 MB)
28 02:14:14.060776 progress 35 % (2 MB)
29 02:14:14.065939 progress 40 % (3 MB)
30 02:14:14.071430 progress 45 % (3 MB)
31 02:14:14.076882 progress 50 % (3 MB)
32 02:14:14.082505 progress 55 % (4 MB)
33 02:14:14.087697 progress 60 % (4 MB)
34 02:14:14.093228 progress 65 % (5 MB)
35 02:14:14.098377 progress 70 % (5 MB)
36 02:14:14.103968 progress 75 % (5 MB)
37 02:14:14.109121 progress 80 % (6 MB)
38 02:14:14.114545 progress 85 % (6 MB)
39 02:14:14.119419 progress 90 % (7 MB)
40 02:14:14.124568 progress 95 % (7 MB)
41 02:14:14.129364 progress 100 % (7 MB)
42 02:14:14.130028 7 MB downloaded in 0.15 s (53.77 MB/s)
43 02:14:14.130584 end: 1.1.1 http-download (duration 00:00:00) [common]
45 02:14:14.131487 end: 1.1 download-retry (duration 00:00:00) [common]
46 02:14:14.131793 start: 1.2 download-retry (timeout 00:10:00) [common]
47 02:14:14.132104 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 02:14:14.132613 downloading http://storage.kernelci.org/next/pending-fixes/v6.12-rc5-576-g10616629aaf32/arm64/defconfig/gcc-12/kernel/Image
49 02:14:14.132864 saving as /var/lib/lava/dispatcher/tmp/932213/tftp-deploy-0alo0hjn/kernel/Image
50 02:14:14.133081 total size: 45715968 (43 MB)
51 02:14:14.133298 No compression specified
52 02:14:14.168504 progress 0 % (0 MB)
53 02:14:14.203142 progress 5 % (2 MB)
54 02:14:14.237796 progress 10 % (4 MB)
55 02:14:14.268466 progress 15 % (6 MB)
56 02:14:14.296556 progress 20 % (8 MB)
57 02:14:14.324361 progress 25 % (10 MB)
58 02:14:14.353118 progress 30 % (13 MB)
59 02:14:14.381175 progress 35 % (15 MB)
60 02:14:14.409061 progress 40 % (17 MB)
61 02:14:14.436423 progress 45 % (19 MB)
62 02:14:14.464570 progress 50 % (21 MB)
63 02:14:14.492299 progress 55 % (24 MB)
64 02:14:14.521072 progress 60 % (26 MB)
65 02:14:14.548881 progress 65 % (28 MB)
66 02:14:14.577639 progress 70 % (30 MB)
67 02:14:14.605278 progress 75 % (32 MB)
68 02:14:14.632957 progress 80 % (34 MB)
69 02:14:14.660352 progress 85 % (37 MB)
70 02:14:14.687994 progress 90 % (39 MB)
71 02:14:14.715600 progress 95 % (41 MB)
72 02:14:14.742362 progress 100 % (43 MB)
73 02:14:14.742941 43 MB downloaded in 0.61 s (71.49 MB/s)
74 02:14:14.743426 end: 1.2.1 http-download (duration 00:00:01) [common]
76 02:14:14.744273 end: 1.2 download-retry (duration 00:00:01) [common]
77 02:14:14.744556 start: 1.3 download-retry (timeout 00:09:59) [common]
78 02:14:14.744820 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 02:14:14.745298 downloading http://storage.kernelci.org/next/pending-fixes/v6.12-rc5-576-g10616629aaf32/arm64/defconfig/gcc-12/dtbs/amlogic/meson-sm1-s905d3-libretech-cc.dtb
80 02:14:14.745573 saving as /var/lib/lava/dispatcher/tmp/932213/tftp-deploy-0alo0hjn/dtb/meson-sm1-s905d3-libretech-cc.dtb
81 02:14:14.745784 total size: 53209 (0 MB)
82 02:14:14.745999 No compression specified
83 02:14:14.779443 progress 61 % (0 MB)
84 02:14:14.780388 progress 100 % (0 MB)
85 02:14:14.780998 0 MB downloaded in 0.04 s (1.44 MB/s)
86 02:14:14.781539 end: 1.3.1 http-download (duration 00:00:00) [common]
88 02:14:14.782443 end: 1.3 download-retry (duration 00:00:00) [common]
89 02:14:14.782759 start: 1.4 download-retry (timeout 00:09:59) [common]
90 02:14:14.783077 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 02:14:14.783614 downloading http://storage.kernelci.org/next/pending-fixes/v6.12-rc5-576-g10616629aaf32/arm64/defconfig/gcc-12/modules.tar.xz
92 02:14:14.783902 saving as /var/lib/lava/dispatcher/tmp/932213/tftp-deploy-0alo0hjn/modules/modules.tar
93 02:14:14.784159 total size: 11610988 (11 MB)
94 02:14:14.784377 Using unxz to decompress xz
95 02:14:14.818593 progress 0 % (0 MB)
96 02:14:14.892591 progress 5 % (0 MB)
97 02:14:14.967010 progress 10 % (1 MB)
98 02:14:15.062922 progress 15 % (1 MB)
99 02:14:15.156084 progress 20 % (2 MB)
100 02:14:15.235630 progress 25 % (2 MB)
101 02:14:15.311792 progress 30 % (3 MB)
102 02:14:15.390811 progress 35 % (3 MB)
103 02:14:15.463933 progress 40 % (4 MB)
104 02:14:15.539913 progress 45 % (5 MB)
105 02:14:15.624616 progress 50 % (5 MB)
106 02:14:15.702442 progress 55 % (6 MB)
107 02:14:15.790100 progress 60 % (6 MB)
108 02:14:15.872025 progress 65 % (7 MB)
109 02:14:15.953276 progress 70 % (7 MB)
110 02:14:16.032431 progress 75 % (8 MB)
111 02:14:16.116667 progress 80 % (8 MB)
112 02:14:16.198056 progress 85 % (9 MB)
113 02:14:16.277755 progress 90 % (9 MB)
114 02:14:16.356786 progress 95 % (10 MB)
115 02:14:16.434794 progress 100 % (11 MB)
116 02:14:16.446344 11 MB downloaded in 1.66 s (6.66 MB/s)
117 02:14:16.447112 end: 1.4.1 http-download (duration 00:00:02) [common]
119 02:14:16.448809 end: 1.4 download-retry (duration 00:00:02) [common]
120 02:14:16.449350 start: 1.5 prepare-tftp-overlay (timeout 00:09:58) [common]
121 02:14:16.449881 start: 1.5.1 extract-nfsrootfs (timeout 00:09:58) [common]
122 02:14:16.450389 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 02:14:16.450905 start: 1.5.2 lava-overlay (timeout 00:09:58) [common]
124 02:14:16.451976 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/932213/lava-overlay-wvooy5tt
125 02:14:16.452908 makedir: /var/lib/lava/dispatcher/tmp/932213/lava-overlay-wvooy5tt/lava-932213/bin
126 02:14:16.453600 makedir: /var/lib/lava/dispatcher/tmp/932213/lava-overlay-wvooy5tt/lava-932213/tests
127 02:14:16.454258 makedir: /var/lib/lava/dispatcher/tmp/932213/lava-overlay-wvooy5tt/lava-932213/results
128 02:14:16.454906 Creating /var/lib/lava/dispatcher/tmp/932213/lava-overlay-wvooy5tt/lava-932213/bin/lava-add-keys
129 02:14:16.455885 Creating /var/lib/lava/dispatcher/tmp/932213/lava-overlay-wvooy5tt/lava-932213/bin/lava-add-sources
130 02:14:16.456914 Creating /var/lib/lava/dispatcher/tmp/932213/lava-overlay-wvooy5tt/lava-932213/bin/lava-background-process-start
131 02:14:16.457924 Creating /var/lib/lava/dispatcher/tmp/932213/lava-overlay-wvooy5tt/lava-932213/bin/lava-background-process-stop
132 02:14:16.458952 Creating /var/lib/lava/dispatcher/tmp/932213/lava-overlay-wvooy5tt/lava-932213/bin/lava-common-functions
133 02:14:16.459919 Creating /var/lib/lava/dispatcher/tmp/932213/lava-overlay-wvooy5tt/lava-932213/bin/lava-echo-ipv4
134 02:14:16.460899 Creating /var/lib/lava/dispatcher/tmp/932213/lava-overlay-wvooy5tt/lava-932213/bin/lava-install-packages
135 02:14:16.461814 Creating /var/lib/lava/dispatcher/tmp/932213/lava-overlay-wvooy5tt/lava-932213/bin/lava-installed-packages
136 02:14:16.462723 Creating /var/lib/lava/dispatcher/tmp/932213/lava-overlay-wvooy5tt/lava-932213/bin/lava-os-build
137 02:14:16.463630 Creating /var/lib/lava/dispatcher/tmp/932213/lava-overlay-wvooy5tt/lava-932213/bin/lava-probe-channel
138 02:14:16.464586 Creating /var/lib/lava/dispatcher/tmp/932213/lava-overlay-wvooy5tt/lava-932213/bin/lava-probe-ip
139 02:14:16.465518 Creating /var/lib/lava/dispatcher/tmp/932213/lava-overlay-wvooy5tt/lava-932213/bin/lava-target-ip
140 02:14:16.466443 Creating /var/lib/lava/dispatcher/tmp/932213/lava-overlay-wvooy5tt/lava-932213/bin/lava-target-mac
141 02:14:16.467391 Creating /var/lib/lava/dispatcher/tmp/932213/lava-overlay-wvooy5tt/lava-932213/bin/lava-target-storage
142 02:14:16.468388 Creating /var/lib/lava/dispatcher/tmp/932213/lava-overlay-wvooy5tt/lava-932213/bin/lava-test-case
143 02:14:16.469334 Creating /var/lib/lava/dispatcher/tmp/932213/lava-overlay-wvooy5tt/lava-932213/bin/lava-test-event
144 02:14:16.470262 Creating /var/lib/lava/dispatcher/tmp/932213/lava-overlay-wvooy5tt/lava-932213/bin/lava-test-feedback
145 02:14:16.471176 Creating /var/lib/lava/dispatcher/tmp/932213/lava-overlay-wvooy5tt/lava-932213/bin/lava-test-raise
146 02:14:16.472132 Creating /var/lib/lava/dispatcher/tmp/932213/lava-overlay-wvooy5tt/lava-932213/bin/lava-test-reference
147 02:14:16.473072 Creating /var/lib/lava/dispatcher/tmp/932213/lava-overlay-wvooy5tt/lava-932213/bin/lava-test-runner
148 02:14:16.474031 Creating /var/lib/lava/dispatcher/tmp/932213/lava-overlay-wvooy5tt/lava-932213/bin/lava-test-set
149 02:14:16.474946 Creating /var/lib/lava/dispatcher/tmp/932213/lava-overlay-wvooy5tt/lava-932213/bin/lava-test-shell
150 02:14:16.475890 Updating /var/lib/lava/dispatcher/tmp/932213/lava-overlay-wvooy5tt/lava-932213/bin/lava-install-packages (oe)
151 02:14:16.476918 Updating /var/lib/lava/dispatcher/tmp/932213/lava-overlay-wvooy5tt/lava-932213/bin/lava-installed-packages (oe)
152 02:14:16.477777 Creating /var/lib/lava/dispatcher/tmp/932213/lava-overlay-wvooy5tt/lava-932213/environment
153 02:14:16.478512 LAVA metadata
154 02:14:16.479006 - LAVA_JOB_ID=932213
155 02:14:16.479441 - LAVA_DISPATCHER_IP=192.168.6.2
156 02:14:16.480182 start: 1.5.2.1 ssh-authorize (timeout 00:09:58) [common]
157 02:14:16.482043 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 02:14:16.482653 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:57) [common]
159 02:14:16.483078 skipped lava-vland-overlay
160 02:14:16.483578 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 02:14:16.484143 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:57) [common]
162 02:14:16.484594 skipped lava-multinode-overlay
163 02:14:16.485102 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 02:14:16.485623 start: 1.5.2.4 test-definition (timeout 00:09:57) [common]
165 02:14:16.486116 Loading test definitions
166 02:14:16.486680 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:57) [common]
167 02:14:16.487132 Using /lava-932213 at stage 0
168 02:14:16.488824 uuid=932213_1.5.2.4.1 testdef=None
169 02:14:16.489159 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 02:14:16.489449 start: 1.5.2.4.2 test-overlay (timeout 00:09:57) [common]
171 02:14:16.491309 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 02:14:16.492167 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:57) [common]
174 02:14:16.494498 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 02:14:16.495357 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:57) [common]
177 02:14:16.497671 runner path: /var/lib/lava/dispatcher/tmp/932213/lava-overlay-wvooy5tt/lava-932213/0/tests/0_dmesg test_uuid 932213_1.5.2.4.1
178 02:14:16.498270 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 02:14:16.499065 Creating lava-test-runner.conf files
181 02:14:16.499282 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/932213/lava-overlay-wvooy5tt/lava-932213/0 for stage 0
182 02:14:16.499654 - 0_dmesg
183 02:14:16.500045 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 02:14:16.500348 start: 1.5.2.5 compress-overlay (timeout 00:09:57) [common]
185 02:14:16.524309 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 02:14:16.524765 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:57) [common]
187 02:14:16.525053 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 02:14:16.525341 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 02:14:16.525624 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:57) [common]
190 02:14:17.465817 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
191 02:14:17.466297 start: 1.5.4 extract-modules (timeout 00:09:57) [common]
192 02:14:17.466565 extracting modules file /var/lib/lava/dispatcher/tmp/932213/tftp-deploy-0alo0hjn/modules/modules.tar to /var/lib/lava/dispatcher/tmp/932213/extract-overlay-ramdisk-ek5jkin1/ramdisk
193 02:14:18.828356 end: 1.5.4 extract-modules (duration 00:00:01) [common]
194 02:14:18.828854 start: 1.5.5 apply-overlay-tftp (timeout 00:09:55) [common]
195 02:14:18.829122 [common] Applying overlay /var/lib/lava/dispatcher/tmp/932213/compress-overlay-vzv4ktrb/overlay-1.5.2.5.tar.gz to ramdisk
196 02:14:18.829334 [common] Applying overlay /var/lib/lava/dispatcher/tmp/932213/compress-overlay-vzv4ktrb/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/932213/extract-overlay-ramdisk-ek5jkin1/ramdisk
197 02:14:18.860767 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 02:14:18.861197 start: 1.5.6 prepare-kernel (timeout 00:09:55) [common]
199 02:14:18.861468 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:55) [common]
200 02:14:18.861695 Converting downloaded kernel to a uImage
201 02:14:18.862001 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/932213/tftp-deploy-0alo0hjn/kernel/Image /var/lib/lava/dispatcher/tmp/932213/tftp-deploy-0alo0hjn/kernel/uImage
202 02:14:19.324787 output: Image Name:
203 02:14:19.325207 output: Created: Mon Nov 4 02:14:18 2024
204 02:14:19.325414 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 02:14:19.325619 output: Data Size: 45715968 Bytes = 44644.50 KiB = 43.60 MiB
206 02:14:19.325838 output: Load Address: 01080000
207 02:14:19.326052 output: Entry Point: 01080000
208 02:14:19.326253 output:
209 02:14:19.326591 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
210 02:14:19.326858 end: 1.5.6 prepare-kernel (duration 00:00:00) [common]
211 02:14:19.327127 start: 1.5.7 configure-preseed-file (timeout 00:09:55) [common]
212 02:14:19.327385 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 02:14:19.327641 start: 1.5.8 compress-ramdisk (timeout 00:09:55) [common]
214 02:14:19.327911 Building ramdisk /var/lib/lava/dispatcher/tmp/932213/extract-overlay-ramdisk-ek5jkin1/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/932213/extract-overlay-ramdisk-ek5jkin1/ramdisk
215 02:14:21.790037 >> 181611 blocks
216 02:14:30.213387 Adding RAMdisk u-boot header.
217 02:14:30.214075 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/932213/extract-overlay-ramdisk-ek5jkin1/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/932213/extract-overlay-ramdisk-ek5jkin1/ramdisk.cpio.gz.uboot
218 02:14:30.502673 output: Image Name:
219 02:14:30.503172 output: Created: Mon Nov 4 02:14:30 2024
220 02:14:30.503424 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 02:14:30.503668 output: Data Size: 26061861 Bytes = 25451.04 KiB = 24.85 MiB
222 02:14:30.503905 output: Load Address: 00000000
223 02:14:30.504440 output: Entry Point: 00000000
224 02:14:30.504953 output:
225 02:14:30.506267 rename /var/lib/lava/dispatcher/tmp/932213/extract-overlay-ramdisk-ek5jkin1/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/932213/tftp-deploy-0alo0hjn/ramdisk/ramdisk.cpio.gz.uboot
226 02:14:30.507160 end: 1.5.8 compress-ramdisk (duration 00:00:11) [common]
227 02:14:30.507859 end: 1.5 prepare-tftp-overlay (duration 00:00:14) [common]
228 02:14:30.508587 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:43) [common]
229 02:14:30.509196 No LXC device requested
230 02:14:30.509845 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 02:14:30.510490 start: 1.7 deploy-device-env (timeout 00:09:43) [common]
232 02:14:30.511118 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 02:14:30.511651 Checking files for TFTP limit of 4294967296 bytes.
234 02:14:30.515096 end: 1 tftp-deploy (duration 00:00:17) [common]
235 02:14:30.515817 start: 2 uboot-action (timeout 00:05:00) [common]
236 02:14:30.516518 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 02:14:30.517155 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 02:14:30.517804 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 02:14:30.518466 Using kernel file from prepare-kernel: 932213/tftp-deploy-0alo0hjn/kernel/uImage
240 02:14:30.519241 substitutions:
241 02:14:30.519759 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 02:14:30.520315 - {DTB_ADDR}: 0x01070000
243 02:14:30.520827 - {DTB}: 932213/tftp-deploy-0alo0hjn/dtb/meson-sm1-s905d3-libretech-cc.dtb
244 02:14:30.521339 - {INITRD}: 932213/tftp-deploy-0alo0hjn/ramdisk/ramdisk.cpio.gz.uboot
245 02:14:30.521846 - {KERNEL_ADDR}: 0x01080000
246 02:14:30.522349 - {KERNEL}: 932213/tftp-deploy-0alo0hjn/kernel/uImage
247 02:14:30.522852 - {LAVA_MAC}: None
248 02:14:30.523404 - {PRESEED_CONFIG}: None
249 02:14:30.523912 - {PRESEED_LOCAL}: None
250 02:14:30.524448 - {RAMDISK_ADDR}: 0x08000000
251 02:14:30.524950 - {RAMDISK}: 932213/tftp-deploy-0alo0hjn/ramdisk/ramdisk.cpio.gz.uboot
252 02:14:30.525455 - {ROOT_PART}: None
253 02:14:30.525948 - {ROOT}: None
254 02:14:30.526450 - {SERVER_IP}: 192.168.6.2
255 02:14:30.526960 - {TEE_ADDR}: 0x83000000
256 02:14:30.527460 - {TEE}: None
257 02:14:30.527962 Parsed boot commands:
258 02:14:30.528491 - setenv autoload no
259 02:14:30.529004 - setenv initrd_high 0xffffffff
260 02:14:30.529516 - setenv fdt_high 0xffffffff
261 02:14:30.530021 - dhcp
262 02:14:30.530527 - setenv serverip 192.168.6.2
263 02:14:30.531034 - tftpboot 0x01080000 932213/tftp-deploy-0alo0hjn/kernel/uImage
264 02:14:30.531539 - tftpboot 0x08000000 932213/tftp-deploy-0alo0hjn/ramdisk/ramdisk.cpio.gz.uboot
265 02:14:30.532076 - tftpboot 0x01070000 932213/tftp-deploy-0alo0hjn/dtb/meson-sm1-s905d3-libretech-cc.dtb
266 02:14:30.532596 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 02:14:30.533117 - bootm 0x01080000 0x08000000 0x01070000
268 02:14:30.533753 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 02:14:30.535702 start: 2.3 connect-device (timeout 00:05:00) [common]
271 02:14:30.536311 [common] connect-device Connecting to device using 'telnet conserv1 3008'
272 02:14:30.552613 Setting prompt string to ['lava-test: # ']
273 02:14:30.554435 end: 2.3 connect-device (duration 00:00:00) [common]
274 02:14:30.555187 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 02:14:30.556077 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 02:14:30.556825 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 02:14:30.558236 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=solitude-01'
278 02:14:30.596683 >> OK - accepted request
279 02:14:30.598853 Returned 0 in 0 seconds
280 02:14:30.700194 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
282 02:14:30.702200 end: 2.4.1 reset-device (duration 00:00:00) [common]
283 02:14:30.702914 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
284 02:14:30.703570 Setting prompt string to ['Hit any key to stop autoboot']
285 02:14:30.704158 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 02:14:30.706085 Trying 192.168.56.21...
287 02:14:30.706685 Connected to conserv1.
288 02:14:30.707200 Escape character is '^]'.
289 02:14:30.707741
290 02:14:30.708324 ser2net port telnet,3008 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.3.3:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
291 02:14:30.708872
292 02:14:37.960774 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
293 02:14:37.961596 bl2_stage_init 0x01
294 02:14:37.962152 bl2_stage_init 0x81
295 02:14:37.966217 hw id: 0x0000 - pwm id 0x01
296 02:14:37.966809 bl2_stage_init 0xc1
297 02:14:37.971839 bl2_stage_init 0x02
298 02:14:37.972447
299 02:14:37.972961 L0:00000000
300 02:14:37.973466 L1:00000703
301 02:14:37.973967 L2:00008067
302 02:14:37.974464 L3:15000000
303 02:14:37.977515 S1:00000000
304 02:14:37.978070 B2:20282000
305 02:14:37.978575 B1:a0f83180
306 02:14:37.979077
307 02:14:37.979579 TE: 68352
308 02:14:37.980109
309 02:14:37.982980 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
310 02:14:37.983525
311 02:14:37.988591 Board ID = 1
312 02:14:37.989164 Set cpu clk to 24M
313 02:14:37.989668 Set clk81 to 24M
314 02:14:37.992179 Use GP1_pll as DSU clk.
315 02:14:37.992720 DSU clk: 1200 Mhz
316 02:14:37.997658 CPU clk: 1200 MHz
317 02:14:37.998203 Set clk81 to 166.6M
318 02:14:38.003217 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
319 02:14:38.003768 board id: 1
320 02:14:38.012493 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
321 02:14:38.023469 fw parse done
322 02:14:38.029480 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
323 02:14:38.072519 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
324 02:14:38.083609 PIEI prepare done
325 02:14:38.084088 fastboot data load
326 02:14:38.084323 fastboot data verify
327 02:14:38.089241 verify result: 266
328 02:14:38.094866 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
329 02:14:38.095448 LPDDR4 probe
330 02:14:38.095871 ddr clk to 1584MHz
331 02:14:38.102923 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
332 02:14:38.140772
333 02:14:38.141418 dmc_version 0001
334 02:14:38.147595 Check phy result
335 02:14:38.153554 INFO : End of CA training
336 02:14:38.154028 INFO : End of initialization
337 02:14:38.159179 INFO : Training has run successfully!
338 02:14:38.159640 Check phy result
339 02:14:38.164743 INFO : End of initialization
340 02:14:38.165189 INFO : End of read enable training
341 02:14:38.170551 INFO : End of fine write leveling
342 02:14:38.176026 INFO : End of Write leveling coarse delay
343 02:14:38.176480 INFO : Training has run successfully!
344 02:14:38.176875 Check phy result
345 02:14:38.181595 INFO : End of initialization
346 02:14:38.182039 INFO : End of read dq deskew training
347 02:14:38.187209 INFO : End of MPR read delay center optimization
348 02:14:38.192802 INFO : End of write delay center optimization
349 02:14:38.198482 INFO : End of read delay center optimization
350 02:14:38.198928 INFO : End of max read latency training
351 02:14:38.204029 INFO : Training has run successfully!
352 02:14:38.204493 1D training succeed
353 02:14:38.213134 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
354 02:14:38.261609 Check phy result
355 02:14:38.262134 INFO : End of initialization
356 02:14:38.288932 INFO : End of 2D read delay Voltage center optimization
357 02:14:38.312985 INFO : End of 2D read delay Voltage center optimization
358 02:14:38.369609 INFO : End of 2D write delay Voltage center optimization
359 02:14:38.423589 INFO : End of 2D write delay Voltage center optimization
360 02:14:38.429068 INFO : Training has run successfully!
361 02:14:38.429395
362 02:14:38.429607 channel==0
363 02:14:38.434669 RxClkDly_Margin_A0==78 ps 8
364 02:14:38.435029 TxDqDly_Margin_A0==98 ps 10
365 02:14:38.440329 RxClkDly_Margin_A1==88 ps 9
366 02:14:38.440701 TxDqDly_Margin_A1==98 ps 10
367 02:14:38.440918 TrainedVREFDQ_A0==74
368 02:14:38.445880 TrainedVREFDQ_A1==75
369 02:14:38.446176 VrefDac_Margin_A0==24
370 02:14:38.446380 DeviceVref_Margin_A0==40
371 02:14:38.451566 VrefDac_Margin_A1==23
372 02:14:38.451890 DeviceVref_Margin_A1==39
373 02:14:38.452142
374 02:14:38.452352
375 02:14:38.457067 channel==1
376 02:14:38.457340 RxClkDly_Margin_A0==88 ps 9
377 02:14:38.457558 TxDqDly_Margin_A0==98 ps 10
378 02:14:38.462677 RxClkDly_Margin_A1==78 ps 8
379 02:14:38.462969 TxDqDly_Margin_A1==88 ps 9
380 02:14:38.469500 TrainedVREFDQ_A0==78
381 02:14:38.469879 TrainedVREFDQ_A1==77
382 02:14:38.470087 VrefDac_Margin_A0==22
383 02:14:38.474133 DeviceVref_Margin_A0==36
384 02:14:38.474484 VrefDac_Margin_A1==22
385 02:14:38.479921 DeviceVref_Margin_A1==37
386 02:14:38.480305
387 02:14:38.480617 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
388 02:14:38.480830
389 02:14:38.513089 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000018 00000018 00000019 00000018 00000017 00000018 00000015 00000017 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001c 00000017 00000016 00000016 dram_vref_reg_value 0x 00000061
390 02:14:38.513713 2D training succeed
391 02:14:38.520370 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
392 02:14:38.524432 auto size-- 65535DDR cs0 size: 2048MB
393 02:14:38.525959 DDR cs1 size: 2048MB
394 02:14:38.529930 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
395 02:14:38.530646 cs0 DataBus test pass
396 02:14:38.535542 cs1 DataBus test pass
397 02:14:38.535930 cs0 AddrBus test pass
398 02:14:38.536273 cs1 AddrBus test pass
399 02:14:38.536539
400 02:14:38.541170 100bdlr_step_size ps== 471
401 02:14:38.541548 result report
402 02:14:38.546695 boot times 0Enable ddr reg access
403 02:14:38.551861 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
404 02:14:38.565871 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
405 02:14:39.224771 bl2z: ptr: 05129330, size: 00001e40
406 02:14:39.231705 0.0;M3 CHK:0;cm4_sp_mode 0
407 02:14:39.232108 MVN_1=0x00000000
408 02:14:39.232323 MVN_2=0x00000000
409 02:14:39.243152 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
410 02:14:39.243544 OPS=0x04
411 02:14:39.243754 ring efuse init
412 02:14:39.248726 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
413 02:14:39.249025 [0.017355 Inits done]
414 02:14:39.249230 secure task start!
415 02:14:39.256847 high task start!
416 02:14:39.257272 low task start!
417 02:14:39.257705 run into bl31
418 02:14:39.265515 NOTICE: BL31: v1.3(release):4fc40b1
419 02:14:39.273600 NOTICE: BL31: Built : 15:57:33, May 22 2019
420 02:14:39.273948 NOTICE: BL31: G12A normal boot!
421 02:14:39.288922 NOTICE: BL31: BL33 decompress pass
422 02:14:39.294675 ERROR: Error initializing runtime service opteed_fast
423 02:14:42.013642 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0; SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
424 02:14:42.014309 bl2_stage_init 0x01
425 02:14:42.014786 bl2_stage_init 0x81
426 02:14:42.019268 hw id: 0x0000 - pwm id 0x01
427 02:14:42.019797 bl2_stage_init 0xc1
428 02:14:42.024945 bl2_stage_init 0x02
429 02:14:42.025495
430 02:14:42.025939 L0:00000000
431 02:14:42.026368 L1:00000703
432 02:14:42.026793 L2:00008067
433 02:14:42.027220 L3:15000000
434 02:14:42.030385 S1:00000000
435 02:14:42.030872 B2:20282000
436 02:14:42.031304 B1:a0f83180
437 02:14:42.031728
438 02:14:42.032203 TE: 70286
439 02:14:42.032632
440 02:14:42.036101 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
441 02:14:42.036592
442 02:14:42.041671 Board ID = 1
443 02:14:42.042155 Set cpu clk to 24M
444 02:14:42.042584 Set clk81 to 24M
445 02:14:42.047157 Use GP1_pll as DSU clk.
446 02:14:42.047633 DSU clk: 1200 Mhz
447 02:14:42.048095 CPU clk: 1200 MHz
448 02:14:42.052928 Set clk81 to 166.6M
449 02:14:42.058365 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
450 02:14:42.058856 board id: 1
451 02:14:42.065662 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
452 02:14:42.076354 fw parse done
453 02:14:42.082254 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
454 02:14:42.125036 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
455 02:14:42.135824 PIEI prepare done
456 02:14:42.136383 fastboot data load
457 02:14:42.136822 fastboot data verify
458 02:14:42.141484 verify result: 266
459 02:14:42.147070 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
460 02:14:42.147563 LPDDR4 probe
461 02:14:42.148022 ddr clk to 1584MHz
462 02:14:42.155049 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
463 02:14:42.192332
464 02:14:42.192819 dmc_version 0001
465 02:14:42.199096 Check phy result
466 02:14:42.205037 INFO : End of CA training
467 02:14:42.205526 INFO : End of initialization
468 02:14:42.210478 INFO : Training has run successfully!
469 02:14:42.210958 Check phy result
470 02:14:42.216121 INFO : End of initialization
471 02:14:42.216597 INFO : End of read enable training
472 02:14:42.221671 INFO : End of fine write leveling
473 02:14:42.227221 INFO : End of Write leveling coarse delay
474 02:14:42.227688 INFO : Training has run successfully!
475 02:14:42.228157 Check phy result
476 02:14:42.232863 INFO : End of initialization
477 02:14:42.233334 INFO : End of read dq deskew training
478 02:14:42.238425 INFO : End of MPR read delay center optimization
479 02:14:42.244089 INFO : End of write delay center optimization
480 02:14:42.249622 INFO : End of read delay center optimization
481 02:14:42.250085 INFO : End of max read latency training
482 02:14:42.255258 INFO : Training has run successfully!
483 02:14:42.255724 1D training succeed
484 02:14:42.264394 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
485 02:14:42.312264 Check phy result
486 02:14:42.312849 INFO : End of initialization
487 02:14:42.334370 INFO : End of 2D read delay Voltage center optimization
488 02:14:42.353561 INFO : End of 2D read delay Voltage center optimization
489 02:14:42.405416 INFO : End of 2D write delay Voltage center optimization
490 02:14:42.454593 INFO : End of 2D write delay Voltage center optimization
491 02:14:42.460277 INFO : Training has run successfully!
492 02:14:42.460770
493 02:14:42.461223 channel==0
494 02:14:42.465791 RxClkDly_Margin_A0==88 ps 9
495 02:14:42.466278 TxDqDly_Margin_A0==98 ps 10
496 02:14:42.471351 RxClkDly_Margin_A1==88 ps 9
497 02:14:42.471833 TxDqDly_Margin_A1==98 ps 10
498 02:14:42.472327 TrainedVREFDQ_A0==74
499 02:14:42.477028 TrainedVREFDQ_A1==74
500 02:14:42.477517 VrefDac_Margin_A0==24
501 02:14:42.477961 DeviceVref_Margin_A0==40
502 02:14:42.482576 VrefDac_Margin_A1==23
503 02:14:42.483053 DeviceVref_Margin_A1==40
504 02:14:42.483501
505 02:14:42.483935
506 02:14:42.488261 channel==1
507 02:14:42.488754 RxClkDly_Margin_A0==78 ps 8
508 02:14:42.489198 TxDqDly_Margin_A0==88 ps 9
509 02:14:42.493758 RxClkDly_Margin_A1==78 ps 8
510 02:14:42.494250 TxDqDly_Margin_A1==88 ps 9
511 02:14:42.499365 TrainedVREFDQ_A0==75
512 02:14:42.499863 TrainedVREFDQ_A1==77
513 02:14:42.500360 VrefDac_Margin_A0==22
514 02:14:42.505065 DeviceVref_Margin_A0==38
515 02:14:42.505555 VrefDac_Margin_A1==22
516 02:14:42.510619 DeviceVref_Margin_A1==37
517 02:14:42.511107
518 02:14:42.511556 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
519 02:14:42.512027
520 02:14:42.544229 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000016 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000018 00000018 00000019 00000018 00000017 00000018 00000015 00000017 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001c 00000017 00000016 00000017 dram_vref_reg_value 0x 00000061
521 02:14:42.544785 2D training succeed
522 02:14:42.549825 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
523 02:14:42.555397 auto size-- 65535DDR cs0 size: 2048MB
524 02:14:42.555925 DDR cs1 size: 2048MB
525 02:14:42.561084 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
526 02:14:42.561569 cs0 DataBus test pass
527 02:14:42.566537 cs1 DataBus test pass
528 02:14:42.567028 cs0 AddrBus test pass
529 02:14:42.567475 cs1 AddrBus test pass
530 02:14:42.567908
531 02:14:42.572264 100bdlr_step_size ps== 478
532 02:14:42.572763 result report
533 02:14:42.577774 boot times 0Enable ddr reg access
534 02:14:42.582914 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
535 02:14:42.596766 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
536 02:14:43.252211 bl2z: ptr: 05129330, size: 00001e40
537 02:14:43.259840 0.0;M3 CHK:0;cm4_sp_mode 0
538 02:14:43.260405 MVN_1=0x00000000
539 02:14:43.260856 MVN_2=0x00000000
540 02:14:43.271216 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
541 02:14:43.271728 OPS=0x04
542 02:14:43.272219 ring efuse init
543 02:14:43.276918 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
544 02:14:43.277440 [0.017319 Inits done]
545 02:14:43.277892 secure task start!
546 02:14:43.284058 high task start!
547 02:14:43.284549 low task start!
548 02:14:43.284995 run into bl31
549 02:14:43.292586 NOTICE: BL31: v1.3(release):4fc40b1
550 02:14:43.300488 NOTICE: BL31: Built : 15:57:33, May 22 2019
551 02:14:43.300993 NOTICE: BL31: G12A normal boot!
552 02:14:43.316080 NOTICE: BL31: BL33 decompress pass
553 02:14:43.321704 ERROR: Error initializing runtime service opteed_fast
554 02:14:44.711437 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
555 02:14:44.711870 bl2_stage_init 0x01
556 02:14:44.712352 bl2_stage_init 0x81
557 02:14:44.716909 hw id: 0x0000 - pwm id 0x01
558 02:14:44.717350 bl2_stage_init 0xc1
559 02:14:44.722448 bl2_stage_init 0x02
560 02:14:44.722879
561 02:14:44.723149 L0:00000000
562 02:14:44.723378 L1:00000703
563 02:14:44.723601 L2:00008067
564 02:14:44.723821 L3:15000000
565 02:14:44.728186 S1:00000000
566 02:14:44.728612 B2:20282000
567 02:14:44.728982 B1:a0f83180
568 02:14:44.729337
569 02:14:44.729709 TE: 68964
570 02:14:44.730075
571 02:14:44.733683 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
572 02:14:44.734115
573 02:14:44.739331 Board ID = 1
574 02:14:44.739631 Set cpu clk to 24M
575 02:14:44.739861 Set clk81 to 24M
576 02:14:44.744782 Use GP1_pll as DSU clk.
577 02:14:44.745086 DSU clk: 1200 Mhz
578 02:14:44.745320 CPU clk: 1200 MHz
579 02:14:44.750453 Set clk81 to 166.6M
580 02:14:44.756136 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
581 02:14:44.756553 board id: 1
582 02:14:44.763280 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
583 02:14:44.774051 fw parse done
584 02:14:44.780058 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
585 02:14:44.822515 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
586 02:14:44.833558 PIEI prepare done
587 02:14:44.834076 fastboot data load
588 02:14:44.834536 fastboot data verify
589 02:14:44.839152 verify result: 266
590 02:14:44.844794 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
591 02:14:44.845335 LPDDR4 probe
592 02:14:44.845797 ddr clk to 1584MHz
593 02:14:44.852769 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
594 02:14:44.889942
595 02:14:44.890459 dmc_version 0001
596 02:14:44.896632 Check phy result
597 02:14:44.902542 INFO : End of CA training
598 02:14:44.903055 INFO : End of initialization
599 02:14:44.908132 INFO : Training has run successfully!
600 02:14:44.908636 Check phy result
601 02:14:44.913725 INFO : End of initialization
602 02:14:44.914224 INFO : End of read enable training
603 02:14:44.919364 INFO : End of fine write leveling
604 02:14:44.925011 INFO : End of Write leveling coarse delay
605 02:14:44.925517 INFO : Training has run successfully!
606 02:14:44.925965 Check phy result
607 02:14:44.930601 INFO : End of initialization
608 02:14:44.931096 INFO : End of read dq deskew training
609 02:14:44.936286 INFO : End of MPR read delay center optimization
610 02:14:44.941798 INFO : End of write delay center optimization
611 02:14:44.947329 INFO : End of read delay center optimization
612 02:14:44.947840 INFO : End of max read latency training
613 02:14:44.952973 INFO : Training has run successfully!
614 02:14:44.953480 1D training succeed
615 02:14:44.962150 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
616 02:14:45.009738 Check phy result
617 02:14:45.010260 INFO : End of initialization
618 02:14:45.032129 INFO : End of 2D read delay Voltage center optimization
619 02:14:45.051264 INFO : End of 2D read delay Voltage center optimization
620 02:14:45.103211 INFO : End of 2D write delay Voltage center optimization
621 02:14:45.152431 INFO : End of 2D write delay Voltage center optimization
622 02:14:45.157890 INFO : Training has run successfully!
623 02:14:45.158396
624 02:14:45.158851 channel==0
625 02:14:45.163601 RxClkDly_Margin_A0==78 ps 8
626 02:14:45.164148 TxDqDly_Margin_A0==88 ps 9
627 02:14:45.166932 RxClkDly_Margin_A1==88 ps 9
628 02:14:45.167425 TxDqDly_Margin_A1==88 ps 9
629 02:14:45.172569 TrainedVREFDQ_A0==74
630 02:14:45.173074 TrainedVREFDQ_A1==74
631 02:14:45.173523 VrefDac_Margin_A0==24
632 02:14:45.178086 DeviceVref_Margin_A0==40
633 02:14:45.178587 VrefDac_Margin_A1==22
634 02:14:45.183600 DeviceVref_Margin_A1==40
635 02:14:45.184123
636 02:14:45.184580
637 02:14:45.185023 channel==1
638 02:14:45.185459 RxClkDly_Margin_A0==88 ps 9
639 02:14:45.187079 TxDqDly_Margin_A0==98 ps 10
640 02:14:45.192564 RxClkDly_Margin_A1==78 ps 8
641 02:14:45.193060 TxDqDly_Margin_A1==88 ps 9
642 02:14:45.193510 TrainedVREFDQ_A0==78
643 02:14:45.198292 TrainedVREFDQ_A1==75
644 02:14:45.198793 VrefDac_Margin_A0==22
645 02:14:45.203890 DeviceVref_Margin_A0==36
646 02:14:45.204432 VrefDac_Margin_A1==22
647 02:14:45.204884 DeviceVref_Margin_A1==39
648 02:14:45.205325
649 02:14:45.212749 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
650 02:14:45.213257
651 02:14:45.240839 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000018 00000018 00000018 00000018 00000017 00000018 00000015 00000017 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001c 00000017 00000016 00000017 dram_vref_reg_value 0x 00000061
652 02:14:45.241409 2D training succeed
653 02:14:45.246486 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
654 02:14:45.251957 auto size-- 65535DDR cs0 size: 2048MB
655 02:14:45.252491 DDR cs1 size: 2048MB
656 02:14:45.257524 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
657 02:14:45.258021 cs0 DataBus test pass
658 02:14:45.263143 cs1 DataBus test pass
659 02:14:45.263642 cs0 AddrBus test pass
660 02:14:45.264141 cs1 AddrBus test pass
661 02:14:45.268774
662 02:14:45.269276 100bdlr_step_size ps== 478
663 02:14:45.269732 result report
664 02:14:45.274362 boot times 0Enable ddr reg access
665 02:14:45.280564 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
666 02:14:45.294259 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
667 02:14:45.949267 bl2z: ptr: 05129330, size: 00001e40
668 02:14:45.955533 0.0;M3 CHK:0;cm4_sp_mode 0
669 02:14:45.956112 MVN_1=0x00000000
670 02:14:45.956574 MVN_2=0x00000000
671 02:14:45.966868 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
672 02:14:45.967392 OPS=0x04
673 02:14:45.967855 ring efuse init
674 02:14:45.972502 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
675 02:14:45.973015 [0.017310 Inits done]
676 02:14:45.973467 secure task start!
677 02:14:45.980459 high task start!
678 02:14:45.980957 low task start!
679 02:14:45.981406 run into bl31
680 02:14:45.989041 NOTICE: BL31: v1.3(release):4fc40b1
681 02:14:45.996856 NOTICE: BL31: Built : 15:57:33, May 22 2019
682 02:14:45.997366 NOTICE: BL31: G12A normal boot!
683 02:14:46.012506 NOTICE: BL31: BL33 decompress pass
684 02:14:46.018081 ERROR: Error initializing runtime service opteed_fast
685 02:14:46.813486
686 02:14:46.814111
687 02:14:46.818896 U-Boot 2024.01-rc4+ (Dec 14 2023 - 02:26:00 -0500) Libre Computer AML-S905D3-CC
688 02:14:46.819406
689 02:14:46.822452 Model: Libre Computer AML-S905D3-CC Solitude
690 02:14:46.969361 SoC: Amlogic Meson SM1 (S905D3) Revision 2b:c (4:2)
691 02:14:46.984769 DRAM: 2 GiB (effective 3.8 GiB)
692 02:14:47.085781 Core: 406 devices, 33 uclasses, devicetree: separate
693 02:14:47.091769 WDT: Not starting watchdog@f0d0
694 02:14:47.116679 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
695 02:14:47.128886 Loading Environment from FAT... Card did not respond to voltage select! : -110
696 02:14:47.133875 ** Bad device specification mmc 0 **
697 02:14:47.143925 Card did not respond to voltage select! : -110
698 02:14:47.151726 ** Bad device specification mmc 0 **
699 02:14:47.152255 Couldn't find partition mmc 0
700 02:14:47.159936 Card did not respond to voltage select! : -110
701 02:14:47.165438 ** Bad device specification mmc 0 **
702 02:14:47.165927 Couldn't find partition mmc 0
703 02:14:47.170502 Error: could not access storage.
704 02:14:47.467970 Net: eth0: ethernet@ff3f0000
705 02:14:47.468642 starting USB...
706 02:14:47.712630 Bus usb@ff500000: Register 3000140 NbrPorts 3
707 02:14:47.713198 Starting the controller
708 02:14:47.719613 USB XHCI 1.10
709 02:14:49.273963 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
710 02:14:49.282238 scanning usb for storage devices... 0 Storage Device(s) found
712 02:14:49.333829 Hit any key to stop autoboot: 1
713 02:14:49.334653 end: 2.4.2 bootloader-interrupt (duration 00:00:19) [common]
714 02:14:49.335298 start: 2.4.3 bootloader-commands (timeout 00:04:41) [common]
715 02:14:49.335865 Setting prompt string to ['=>']
716 02:14:49.336465 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:41)
717 02:14:49.348363 0
718 02:14:49.349338 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
720 02:14:49.450674 => setenv autoload no
721 02:14:49.451507 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
722 02:14:49.457173 setenv autoload no
724 02:14:49.558775 => setenv initrd_high 0xffffffff
725 02:14:49.559746 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
726 02:14:49.564190 setenv initrd_high 0xffffffff
728 02:14:49.665761 => setenv fdt_high 0xffffffff
729 02:14:49.666556 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
730 02:14:49.671560 setenv fdt_high 0xffffffff
732 02:14:49.773169 => dhcp
733 02:14:49.773893 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
734 02:14:49.778138 dhcp
735 02:14:50.683966 ethernet@ff3f0000 Waiting for PHY auto negotiation to complete.. done
736 02:14:50.684646 Speed: 1000, full duplex
737 02:14:50.685113 BOOTP broadcast 1
738 02:14:50.694436 DHCP client bound to address 192.168.6.21 (9 ms)
740 02:14:50.795956 => setenv serverip 192.168.6.2
741 02:14:50.796717 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
742 02:14:50.801283 setenv serverip 192.168.6.2
744 02:14:50.902809 => tftpboot 0x01080000 932213/tftp-deploy-0alo0hjn/kernel/uImage
745 02:14:50.903517 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
746 02:14:50.910355 tftpboot 0x01080000 932213/tftp-deploy-0alo0hjn/kernel/uImage
747 02:14:50.910895 Speed: 1000, full duplex
748 02:14:50.911354 Using ethernet@ff3f0000 device
749 02:14:50.915765 TFTP from server 192.168.6.2; our IP address is 192.168.6.21
750 02:14:50.921335 Filename '932213/tftp-deploy-0alo0hjn/kernel/uImage'.
751 02:14:50.925302 Load address: 0x1080000
752 02:14:53.822343 Loading: *################################################## 43.6 MiB
753 02:14:53.823010 15 MiB/s
754 02:14:53.823462 done
755 02:14:53.826716 Bytes transferred = 45716032 (2b99240 hex)
757 02:14:53.928411 => tftpboot 0x08000000 932213/tftp-deploy-0alo0hjn/ramdisk/ramdisk.cpio.gz.uboot
758 02:14:53.929233 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:37)
759 02:14:53.936353 tftpboot 0x08000000 932213/tftp-deploy-0alo0hjn/ramdisk/ramdisk.cpio.gz.uboot
760 02:14:53.936905 Speed: 1000, full duplex
761 02:14:53.937347 Using ethernet@ff3f0000 device
762 02:14:53.941856 TFTP from server 192.168.6.2; our IP address is 192.168.6.21
763 02:14:53.951468 Filename '932213/tftp-deploy-0alo0hjn/ramdisk/ramdisk.cpio.gz.uboot'.
764 02:14:53.951895 Load address: 0x8000000
765 02:14:55.707033 Loading: *################################################# UDP wrong checksum 00000005 0000f51b
766 02:14:56.013096 UDP wrong checksum 000000ff 0000ecb4
767 02:14:56.065815 UDP wrong checksum 000000ff 000085a7
768 02:15:00.708572 T UDP wrong checksum 00000005 0000f51b
769 02:15:10.709538 T T UDP wrong checksum 00000005 0000f51b
770 02:15:18.329778 T UDP wrong checksum 000000ff 0000e60a
771 02:15:18.340104 UDP wrong checksum 000000ff 000079fd
772 02:15:21.171604 T UDP wrong checksum 000000ff 0000a6ce
773 02:15:21.182090 UDP wrong checksum 000000ff 00003bc1
774 02:15:23.164253 UDP wrong checksum 00000005 00004f4c
775 02:15:26.234172 T UDP wrong checksum 000000ff 00003f92
776 02:15:26.294863 UDP wrong checksum 000000ff 0000db84
777 02:15:30.712537 UDP wrong checksum 00000005 0000f51b
778 02:15:34.225006 T UDP wrong checksum 000000ff 000015c1
779 02:15:34.265725 UDP wrong checksum 000000ff 0000a1b3
780 02:15:50.626978 T T T UDP wrong checksum 000000ff 0000c0a5
781 02:15:50.666164 UDP wrong checksum 000000ff 00004598
782 02:15:50.719222
783 02:15:50.719731 Retry count exceeded; starting again
785 02:15:50.721221 end: 2.4.3 bootloader-commands (duration 00:01:01) [common]
788 02:15:50.723113 end: 2.4 uboot-commands (duration 00:01:20) [common]
790 02:15:50.724571 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
792 02:15:50.725664 end: 2 uboot-action (duration 00:01:20) [common]
794 02:15:50.727292 Cleaning after the job
795 02:15:50.727879 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/932213/tftp-deploy-0alo0hjn/ramdisk
796 02:15:50.729231 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/932213/tftp-deploy-0alo0hjn/kernel
797 02:15:50.776750 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/932213/tftp-deploy-0alo0hjn/dtb
798 02:15:50.777539 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/932213/tftp-deploy-0alo0hjn/modules
799 02:15:50.798066 start: 4.1 power-off (timeout 00:00:30) [common]
800 02:15:50.798724 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=solitude-01'
801 02:15:50.831717 >> OK - accepted request
802 02:15:50.833966 Returned 0 in 0 seconds
803 02:15:50.934715 end: 4.1 power-off (duration 00:00:00) [common]
805 02:15:50.935655 start: 4.2 read-feedback (timeout 00:10:00) [common]
806 02:15:50.936313 Listened to connection for namespace 'common' for up to 1s
807 02:15:51.937283 Finalising connection for namespace 'common'
808 02:15:51.938043 Disconnecting from shell: Finalise
809 02:15:51.938614 =>
810 02:15:52.039708 end: 4.2 read-feedback (duration 00:00:01) [common]
811 02:15:52.040496 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/932213
812 02:15:52.335947 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/932213
813 02:15:52.336782 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.