Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 02:34:53.772670 lava-dispatcher, installed at version: 2024.01
2 02:34:53.773413 start: 0 validate
3 02:34:53.773920 Start time: 2024-11-04 02:34:53.773890+00:00 (UTC)
4 02:34:53.774471 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 02:34:53.775003 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-igt%2F20240313.0%2Farm64%2Frootfs.cpio.gz exists
6 02:34:53.816185 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 02:34:53.816736 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fpending-fixes%2Fv6.12-rc5-576-g10616629aaf32%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 02:34:53.848187 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 02:34:53.848809 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fpending-fixes%2Fv6.12-rc5-576-g10616629aaf32%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 02:34:53.878934 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 02:34:53.879429 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fpending-fixes%2Fv6.12-rc5-576-g10616629aaf32%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
12 02:34:53.915473 validate duration: 0.14
14 02:34:53.916365 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 02:34:53.916717 start: 1.1 download-retry (timeout 00:10:00) [common]
16 02:34:53.917028 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 02:34:53.917608 Not decompressing ramdisk as can be used compressed.
18 02:34:53.918037 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-igt/20240313.0/arm64/rootfs.cpio.gz
19 02:34:53.918285 saving as /var/lib/lava/dispatcher/tmp/932144/tftp-deploy-njsy2zcp/ramdisk/rootfs.cpio.gz
20 02:34:53.918546 total size: 47897469 (45 MB)
21 02:34:53.953338 progress 0 % (0 MB)
22 02:34:53.984968 progress 5 % (2 MB)
23 02:34:54.015453 progress 10 % (4 MB)
24 02:34:54.045415 progress 15 % (6 MB)
25 02:34:54.075796 progress 20 % (9 MB)
26 02:34:54.105541 progress 25 % (11 MB)
27 02:34:54.135359 progress 30 % (13 MB)
28 02:34:54.165741 progress 35 % (16 MB)
29 02:34:54.195136 progress 40 % (18 MB)
30 02:34:54.225398 progress 45 % (20 MB)
31 02:34:54.255318 progress 50 % (22 MB)
32 02:34:54.285360 progress 55 % (25 MB)
33 02:34:54.315503 progress 60 % (27 MB)
34 02:34:54.345313 progress 65 % (29 MB)
35 02:34:54.375637 progress 70 % (32 MB)
36 02:34:54.404996 progress 75 % (34 MB)
37 02:34:54.434483 progress 80 % (36 MB)
38 02:34:54.464116 progress 85 % (38 MB)
39 02:34:54.493537 progress 90 % (41 MB)
40 02:34:54.523145 progress 95 % (43 MB)
41 02:34:54.552095 progress 100 % (45 MB)
42 02:34:54.552829 45 MB downloaded in 0.63 s (72.02 MB/s)
43 02:34:54.553372 end: 1.1.1 http-download (duration 00:00:01) [common]
45 02:34:54.554247 end: 1.1 download-retry (duration 00:00:01) [common]
46 02:34:54.554540 start: 1.2 download-retry (timeout 00:09:59) [common]
47 02:34:54.554811 start: 1.2.1 http-download (timeout 00:09:59) [common]
48 02:34:54.555282 downloading http://storage.kernelci.org/next/pending-fixes/v6.12-rc5-576-g10616629aaf32/arm64/defconfig/gcc-12/kernel/Image
49 02:34:54.555530 saving as /var/lib/lava/dispatcher/tmp/932144/tftp-deploy-njsy2zcp/kernel/Image
50 02:34:54.555740 total size: 45715968 (43 MB)
51 02:34:54.555952 No compression specified
52 02:34:54.593825 progress 0 % (0 MB)
53 02:34:54.622097 progress 5 % (2 MB)
54 02:34:54.650134 progress 10 % (4 MB)
55 02:34:54.678246 progress 15 % (6 MB)
56 02:34:54.706354 progress 20 % (8 MB)
57 02:34:54.734052 progress 25 % (10 MB)
58 02:34:54.762112 progress 30 % (13 MB)
59 02:34:54.790451 progress 35 % (15 MB)
60 02:34:54.818815 progress 40 % (17 MB)
61 02:34:54.846610 progress 45 % (19 MB)
62 02:34:54.874993 progress 50 % (21 MB)
63 02:34:54.903143 progress 55 % (24 MB)
64 02:34:54.931349 progress 60 % (26 MB)
65 02:34:54.959184 progress 65 % (28 MB)
66 02:34:54.987320 progress 70 % (30 MB)
67 02:34:55.015379 progress 75 % (32 MB)
68 02:34:55.043478 progress 80 % (34 MB)
69 02:34:55.071199 progress 85 % (37 MB)
70 02:34:55.099413 progress 90 % (39 MB)
71 02:34:55.127415 progress 95 % (41 MB)
72 02:34:55.155124 progress 100 % (43 MB)
73 02:34:55.155646 43 MB downloaded in 0.60 s (72.68 MB/s)
74 02:34:55.156160 end: 1.2.1 http-download (duration 00:00:01) [common]
76 02:34:55.156979 end: 1.2 download-retry (duration 00:00:01) [common]
77 02:34:55.157256 start: 1.3 download-retry (timeout 00:09:59) [common]
78 02:34:55.157522 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 02:34:55.157991 downloading http://storage.kernelci.org/next/pending-fixes/v6.12-rc5-576-g10616629aaf32/arm64/defconfig/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
80 02:34:55.158264 saving as /var/lib/lava/dispatcher/tmp/932144/tftp-deploy-njsy2zcp/dtb/meson-g12b-a311d-libretech-cc.dtb
81 02:34:55.158476 total size: 54703 (0 MB)
82 02:34:55.158688 No compression specified
83 02:34:55.202135 progress 59 % (0 MB)
84 02:34:55.202959 progress 100 % (0 MB)
85 02:34:55.203499 0 MB downloaded in 0.05 s (1.16 MB/s)
86 02:34:55.203960 end: 1.3.1 http-download (duration 00:00:00) [common]
88 02:34:55.204817 end: 1.3 download-retry (duration 00:00:00) [common]
89 02:34:55.205078 start: 1.4 download-retry (timeout 00:09:59) [common]
90 02:34:55.205344 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 02:34:55.205793 downloading http://storage.kernelci.org/next/pending-fixes/v6.12-rc5-576-g10616629aaf32/arm64/defconfig/gcc-12/modules.tar.xz
92 02:34:55.206038 saving as /var/lib/lava/dispatcher/tmp/932144/tftp-deploy-njsy2zcp/modules/modules.tar
93 02:34:55.206244 total size: 11610988 (11 MB)
94 02:34:55.206454 Using unxz to decompress xz
95 02:34:55.251046 progress 0 % (0 MB)
96 02:34:55.316239 progress 5 % (0 MB)
97 02:34:55.389330 progress 10 % (1 MB)
98 02:34:55.484443 progress 15 % (1 MB)
99 02:34:55.576096 progress 20 % (2 MB)
100 02:34:55.654506 progress 25 % (2 MB)
101 02:34:55.729148 progress 30 % (3 MB)
102 02:34:55.806463 progress 35 % (3 MB)
103 02:34:55.878104 progress 40 % (4 MB)
104 02:34:55.952481 progress 45 % (5 MB)
105 02:34:56.035420 progress 50 % (5 MB)
106 02:34:56.112355 progress 55 % (6 MB)
107 02:34:56.198981 progress 60 % (6 MB)
108 02:34:56.279018 progress 65 % (7 MB)
109 02:34:56.358530 progress 70 % (7 MB)
110 02:34:56.436466 progress 75 % (8 MB)
111 02:34:56.518663 progress 80 % (8 MB)
112 02:34:56.597545 progress 85 % (9 MB)
113 02:34:56.675054 progress 90 % (9 MB)
114 02:34:56.752000 progress 95 % (10 MB)
115 02:34:56.827900 progress 100 % (11 MB)
116 02:34:56.839303 11 MB downloaded in 1.63 s (6.78 MB/s)
117 02:34:56.840050 end: 1.4.1 http-download (duration 00:00:02) [common]
119 02:34:56.841743 end: 1.4 download-retry (duration 00:00:02) [common]
120 02:34:56.842290 start: 1.5 prepare-tftp-overlay (timeout 00:09:57) [common]
121 02:34:56.842825 start: 1.5.1 extract-nfsrootfs (timeout 00:09:57) [common]
122 02:34:56.843339 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 02:34:56.843860 start: 1.5.2 lava-overlay (timeout 00:09:57) [common]
124 02:34:56.844897 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/932144/lava-overlay-sp89xgpe
125 02:34:56.845748 makedir: /var/lib/lava/dispatcher/tmp/932144/lava-overlay-sp89xgpe/lava-932144/bin
126 02:34:56.846412 makedir: /var/lib/lava/dispatcher/tmp/932144/lava-overlay-sp89xgpe/lava-932144/tests
127 02:34:56.847063 makedir: /var/lib/lava/dispatcher/tmp/932144/lava-overlay-sp89xgpe/lava-932144/results
128 02:34:56.847706 Creating /var/lib/lava/dispatcher/tmp/932144/lava-overlay-sp89xgpe/lava-932144/bin/lava-add-keys
129 02:34:56.848764 Creating /var/lib/lava/dispatcher/tmp/932144/lava-overlay-sp89xgpe/lava-932144/bin/lava-add-sources
130 02:34:56.849769 Creating /var/lib/lava/dispatcher/tmp/932144/lava-overlay-sp89xgpe/lava-932144/bin/lava-background-process-start
131 02:34:56.850761 Creating /var/lib/lava/dispatcher/tmp/932144/lava-overlay-sp89xgpe/lava-932144/bin/lava-background-process-stop
132 02:34:56.851789 Creating /var/lib/lava/dispatcher/tmp/932144/lava-overlay-sp89xgpe/lava-932144/bin/lava-common-functions
133 02:34:56.852794 Creating /var/lib/lava/dispatcher/tmp/932144/lava-overlay-sp89xgpe/lava-932144/bin/lava-echo-ipv4
134 02:34:56.853750 Creating /var/lib/lava/dispatcher/tmp/932144/lava-overlay-sp89xgpe/lava-932144/bin/lava-install-packages
135 02:34:56.854732 Creating /var/lib/lava/dispatcher/tmp/932144/lava-overlay-sp89xgpe/lava-932144/bin/lava-installed-packages
136 02:34:56.855668 Creating /var/lib/lava/dispatcher/tmp/932144/lava-overlay-sp89xgpe/lava-932144/bin/lava-os-build
137 02:34:56.856679 Creating /var/lib/lava/dispatcher/tmp/932144/lava-overlay-sp89xgpe/lava-932144/bin/lava-probe-channel
138 02:34:56.857652 Creating /var/lib/lava/dispatcher/tmp/932144/lava-overlay-sp89xgpe/lava-932144/bin/lava-probe-ip
139 02:34:56.858597 Creating /var/lib/lava/dispatcher/tmp/932144/lava-overlay-sp89xgpe/lava-932144/bin/lava-target-ip
140 02:34:56.859539 Creating /var/lib/lava/dispatcher/tmp/932144/lava-overlay-sp89xgpe/lava-932144/bin/lava-target-mac
141 02:34:56.860513 Creating /var/lib/lava/dispatcher/tmp/932144/lava-overlay-sp89xgpe/lava-932144/bin/lava-target-storage
142 02:34:56.861475 Creating /var/lib/lava/dispatcher/tmp/932144/lava-overlay-sp89xgpe/lava-932144/bin/lava-test-case
143 02:34:56.862427 Creating /var/lib/lava/dispatcher/tmp/932144/lava-overlay-sp89xgpe/lava-932144/bin/lava-test-event
144 02:34:56.863370 Creating /var/lib/lava/dispatcher/tmp/932144/lava-overlay-sp89xgpe/lava-932144/bin/lava-test-feedback
145 02:34:56.864343 Creating /var/lib/lava/dispatcher/tmp/932144/lava-overlay-sp89xgpe/lava-932144/bin/lava-test-raise
146 02:34:56.865330 Creating /var/lib/lava/dispatcher/tmp/932144/lava-overlay-sp89xgpe/lava-932144/bin/lava-test-reference
147 02:34:56.866291 Creating /var/lib/lava/dispatcher/tmp/932144/lava-overlay-sp89xgpe/lava-932144/bin/lava-test-runner
148 02:34:56.867235 Creating /var/lib/lava/dispatcher/tmp/932144/lava-overlay-sp89xgpe/lava-932144/bin/lava-test-set
149 02:34:56.868206 Creating /var/lib/lava/dispatcher/tmp/932144/lava-overlay-sp89xgpe/lava-932144/bin/lava-test-shell
150 02:34:56.869165 Updating /var/lib/lava/dispatcher/tmp/932144/lava-overlay-sp89xgpe/lava-932144/bin/lava-install-packages (oe)
151 02:34:56.870186 Updating /var/lib/lava/dispatcher/tmp/932144/lava-overlay-sp89xgpe/lava-932144/bin/lava-installed-packages (oe)
152 02:34:56.871059 Creating /var/lib/lava/dispatcher/tmp/932144/lava-overlay-sp89xgpe/lava-932144/environment
153 02:34:56.871815 LAVA metadata
154 02:34:56.872373 - LAVA_JOB_ID=932144
155 02:34:56.872829 - LAVA_DISPATCHER_IP=192.168.6.2
156 02:34:56.873508 start: 1.5.2.1 ssh-authorize (timeout 00:09:57) [common]
157 02:34:56.875304 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 02:34:56.875922 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:57) [common]
159 02:34:56.876440 skipped lava-vland-overlay
160 02:34:56.876963 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 02:34:56.877496 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:57) [common]
162 02:34:56.877939 skipped lava-multinode-overlay
163 02:34:56.878444 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 02:34:56.878962 start: 1.5.2.4 test-definition (timeout 00:09:57) [common]
165 02:34:56.879451 Loading test definitions
166 02:34:56.880050 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:57) [common]
167 02:34:56.880526 Using /lava-932144 at stage 0
168 02:34:56.882681 uuid=932144_1.5.2.4.1 testdef=None
169 02:34:56.883274 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 02:34:56.883829 start: 1.5.2.4.2 test-overlay (timeout 00:09:57) [common]
171 02:34:56.885869 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 02:34:56.886738 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:57) [common]
174 02:34:56.888992 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 02:34:56.889890 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:57) [common]
177 02:34:56.892075 runner path: /var/lib/lava/dispatcher/tmp/932144/lava-overlay-sp89xgpe/lava-932144/0/tests/0_igt-gpu-panfrost test_uuid 932144_1.5.2.4.1
178 02:34:56.892717 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 02:34:56.893607 Creating lava-test-runner.conf files
181 02:34:56.893838 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/932144/lava-overlay-sp89xgpe/lava-932144/0 for stage 0
182 02:34:56.894211 - 0_igt-gpu-panfrost
183 02:34:56.894615 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 02:34:56.894937 start: 1.5.2.5 compress-overlay (timeout 00:09:57) [common]
185 02:34:56.918756 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 02:34:56.919173 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:57) [common]
187 02:34:56.919472 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 02:34:56.919763 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 02:34:56.920065 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:57) [common]
190 02:35:03.784045 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:07) [common]
191 02:35:03.784508 start: 1.5.4 extract-modules (timeout 00:09:50) [common]
192 02:35:03.784759 extracting modules file /var/lib/lava/dispatcher/tmp/932144/tftp-deploy-njsy2zcp/modules/modules.tar to /var/lib/lava/dispatcher/tmp/932144/extract-overlay-ramdisk-j4l7jnbz/ramdisk
193 02:35:05.159834 end: 1.5.4 extract-modules (duration 00:00:01) [common]
194 02:35:05.160323 start: 1.5.5 apply-overlay-tftp (timeout 00:09:49) [common]
195 02:35:05.160604 [common] Applying overlay /var/lib/lava/dispatcher/tmp/932144/compress-overlay-y8qm529q/overlay-1.5.2.5.tar.gz to ramdisk
196 02:35:05.160822 [common] Applying overlay /var/lib/lava/dispatcher/tmp/932144/compress-overlay-y8qm529q/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/932144/extract-overlay-ramdisk-j4l7jnbz/ramdisk
197 02:35:05.190544 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 02:35:05.190930 start: 1.5.6 prepare-kernel (timeout 00:09:49) [common]
199 02:35:05.191202 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:49) [common]
200 02:35:05.191432 Converting downloaded kernel to a uImage
201 02:35:05.191736 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/932144/tftp-deploy-njsy2zcp/kernel/Image /var/lib/lava/dispatcher/tmp/932144/tftp-deploy-njsy2zcp/kernel/uImage
202 02:35:05.679480 output: Image Name:
203 02:35:05.679913 output: Created: Mon Nov 4 02:35:05 2024
204 02:35:05.680165 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 02:35:05.680375 output: Data Size: 45715968 Bytes = 44644.50 KiB = 43.60 MiB
206 02:35:05.680580 output: Load Address: 01080000
207 02:35:05.680782 output: Entry Point: 01080000
208 02:35:05.680984 output:
209 02:35:05.681322 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
210 02:35:05.681593 end: 1.5.6 prepare-kernel (duration 00:00:00) [common]
211 02:35:05.681864 start: 1.5.7 configure-preseed-file (timeout 00:09:48) [common]
212 02:35:05.682122 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 02:35:05.682383 start: 1.5.8 compress-ramdisk (timeout 00:09:48) [common]
214 02:35:05.682642 Building ramdisk /var/lib/lava/dispatcher/tmp/932144/extract-overlay-ramdisk-j4l7jnbz/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/932144/extract-overlay-ramdisk-j4l7jnbz/ramdisk
215 02:35:12.389549 >> 502416 blocks
216 02:35:33.917618 Adding RAMdisk u-boot header.
217 02:35:33.918343 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/932144/extract-overlay-ramdisk-j4l7jnbz/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/932144/extract-overlay-ramdisk-j4l7jnbz/ramdisk.cpio.gz.uboot
218 02:35:34.590669 output: Image Name:
219 02:35:34.591095 output: Created: Mon Nov 4 02:35:33 2024
220 02:35:34.591561 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 02:35:34.592072 output: Data Size: 65715643 Bytes = 64175.43 KiB = 62.67 MiB
222 02:35:34.592531 output: Load Address: 00000000
223 02:35:34.592979 output: Entry Point: 00000000
224 02:35:34.593419 output:
225 02:35:34.595239 rename /var/lib/lava/dispatcher/tmp/932144/extract-overlay-ramdisk-j4l7jnbz/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/932144/tftp-deploy-njsy2zcp/ramdisk/ramdisk.cpio.gz.uboot
226 02:35:34.596051 end: 1.5.8 compress-ramdisk (duration 00:00:29) [common]
227 02:35:34.596674 end: 1.5 prepare-tftp-overlay (duration 00:00:38) [common]
228 02:35:34.597268 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:19) [common]
229 02:35:34.597776 No LXC device requested
230 02:35:34.598333 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 02:35:34.598903 start: 1.7 deploy-device-env (timeout 00:09:19) [common]
232 02:35:34.599456 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 02:35:34.599914 Checking files for TFTP limit of 4294967296 bytes.
234 02:35:34.602858 end: 1 tftp-deploy (duration 00:00:41) [common]
235 02:35:34.603485 start: 2 uboot-action (timeout 00:05:00) [common]
236 02:35:34.604099 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 02:35:34.604663 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 02:35:34.605245 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 02:35:34.605828 Using kernel file from prepare-kernel: 932144/tftp-deploy-njsy2zcp/kernel/uImage
240 02:35:34.606502 substitutions:
241 02:35:34.606959 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 02:35:34.607408 - {DTB_ADDR}: 0x01070000
243 02:35:34.607857 - {DTB}: 932144/tftp-deploy-njsy2zcp/dtb/meson-g12b-a311d-libretech-cc.dtb
244 02:35:34.608345 - {INITRD}: 932144/tftp-deploy-njsy2zcp/ramdisk/ramdisk.cpio.gz.uboot
245 02:35:34.608793 - {KERNEL_ADDR}: 0x01080000
246 02:35:34.609232 - {KERNEL}: 932144/tftp-deploy-njsy2zcp/kernel/uImage
247 02:35:34.609673 - {LAVA_MAC}: None
248 02:35:34.610158 - {PRESEED_CONFIG}: None
249 02:35:34.610605 - {PRESEED_LOCAL}: None
250 02:35:34.611046 - {RAMDISK_ADDR}: 0x08000000
251 02:35:34.611482 - {RAMDISK}: 932144/tftp-deploy-njsy2zcp/ramdisk/ramdisk.cpio.gz.uboot
252 02:35:34.611919 - {ROOT_PART}: None
253 02:35:34.612386 - {ROOT}: None
254 02:35:34.612829 - {SERVER_IP}: 192.168.6.2
255 02:35:34.613272 - {TEE_ADDR}: 0x83000000
256 02:35:34.613707 - {TEE}: None
257 02:35:34.614141 Parsed boot commands:
258 02:35:34.614566 - setenv autoload no
259 02:35:34.615001 - setenv initrd_high 0xffffffff
260 02:35:34.615433 - setenv fdt_high 0xffffffff
261 02:35:34.615865 - dhcp
262 02:35:34.616334 - setenv serverip 192.168.6.2
263 02:35:34.616767 - tftpboot 0x01080000 932144/tftp-deploy-njsy2zcp/kernel/uImage
264 02:35:34.617201 - tftpboot 0x08000000 932144/tftp-deploy-njsy2zcp/ramdisk/ramdisk.cpio.gz.uboot
265 02:35:34.617634 - tftpboot 0x01070000 932144/tftp-deploy-njsy2zcp/dtb/meson-g12b-a311d-libretech-cc.dtb
266 02:35:34.618067 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 02:35:34.618505 - bootm 0x01080000 0x08000000 0x01070000
268 02:35:34.619057 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 02:35:34.620729 start: 2.3 connect-device (timeout 00:05:00) [common]
271 02:35:34.621229 [common] connect-device Connecting to device using 'telnet conserv1 3007'
272 02:35:34.635247 Setting prompt string to ['lava-test: # ']
273 02:35:34.636866 end: 2.3 connect-device (duration 00:00:00) [common]
274 02:35:34.637569 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 02:35:34.638173 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 02:35:34.638737 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 02:35:34.639974 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
278 02:35:34.676750 >> OK - accepted request
279 02:35:34.678929 Returned 0 in 0 seconds
280 02:35:34.780156 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
282 02:35:34.781852 end: 2.4.1 reset-device (duration 00:00:00) [common]
283 02:35:34.782486 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
284 02:35:34.783045 Setting prompt string to ['Hit any key to stop autoboot']
285 02:35:34.783555 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 02:35:34.785309 Trying 192.168.56.21...
287 02:35:34.785825 Connected to conserv1.
288 02:35:34.786294 Escape character is '^]'.
289 02:35:34.786747
290 02:35:34.787219 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
291 02:35:34.787690
292 02:35:45.794210 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
293 02:35:45.794851 bl2_stage_init 0x01
294 02:35:45.795347 bl2_stage_init 0x81
295 02:35:45.799760 hw id: 0x0000 - pwm id 0x01
296 02:35:45.800361 bl2_stage_init 0xc1
297 02:35:45.800820 bl2_stage_init 0x02
298 02:35:45.801265
299 02:35:45.805277 L0:00000000
300 02:35:45.805768 L1:20000703
301 02:35:45.806214 L2:00008067
302 02:35:45.806660 L3:14000000
303 02:35:45.808155 B2:00402000
304 02:35:45.808630 B1:e0f83180
305 02:35:45.809070
306 02:35:45.809499 TE: 58167
307 02:35:45.809926
308 02:35:45.819245 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
309 02:35:45.819730
310 02:35:45.820213 Board ID = 1
311 02:35:45.820640 Set A53 clk to 24M
312 02:35:45.821065 Set A73 clk to 24M
313 02:35:45.824932 Set clk81 to 24M
314 02:35:45.825392 A53 clk: 1200 MHz
315 02:35:45.825817 A73 clk: 1200 MHz
316 02:35:45.830475 CLK81: 166.6M
317 02:35:45.830928 smccc: 00012abe
318 02:35:45.836151 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
319 02:35:45.836609 board id: 1
320 02:35:45.841665 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
321 02:35:45.855422 fw parse done
322 02:35:45.861394 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
323 02:35:45.904122 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
324 02:35:45.914898 PIEI prepare done
325 02:35:45.915362 fastboot data load
326 02:35:45.915797 fastboot data verify
327 02:35:45.920602 verify result: 266
328 02:35:45.926246 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
329 02:35:45.926732 LPDDR4 probe
330 02:35:45.927172 ddr clk to 1584MHz
331 02:35:45.934164 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
332 02:35:45.970446
333 02:35:45.970960 dmc_version 0001
334 02:35:45.977164 Check phy result
335 02:35:45.983973 INFO : End of CA training
336 02:35:45.984488 INFO : End of initialization
337 02:35:45.989601 INFO : Training has run successfully!
338 02:35:45.990075 Check phy result
339 02:35:45.995239 INFO : End of initialization
340 02:35:45.995705 INFO : End of read enable training
341 02:35:45.998500 INFO : End of fine write leveling
342 02:35:46.004059 INFO : End of Write leveling coarse delay
343 02:35:46.009626 INFO : Training has run successfully!
344 02:35:46.010091 Check phy result
345 02:35:46.010537 INFO : End of initialization
346 02:35:46.015228 INFO : End of read dq deskew training
347 02:35:46.018634 INFO : End of MPR read delay center optimization
348 02:35:46.024212 INFO : End of write delay center optimization
349 02:35:46.029748 INFO : End of read delay center optimization
350 02:35:46.030226 INFO : End of max read latency training
351 02:35:46.035381 INFO : Training has run successfully!
352 02:35:46.035843 1D training succeed
353 02:35:46.042591 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
354 02:35:46.091091 Check phy result
355 02:35:46.091569 INFO : End of initialization
356 02:35:46.112841 INFO : End of 2D read delay Voltage center optimization
357 02:35:46.133082 INFO : End of 2D read delay Voltage center optimization
358 02:35:46.185088 INFO : End of 2D write delay Voltage center optimization
359 02:35:46.234468 INFO : End of 2D write delay Voltage center optimization
360 02:35:46.240136 INFO : Training has run successfully!
361 02:35:46.240596
362 02:35:46.241042 channel==0
363 02:35:46.245662 RxClkDly_Margin_A0==88 ps 9
364 02:35:46.246123 TxDqDly_Margin_A0==98 ps 10
365 02:35:46.251304 RxClkDly_Margin_A1==88 ps 9
366 02:35:46.251781 TxDqDly_Margin_A1==88 ps 9
367 02:35:46.252304 TrainedVREFDQ_A0==74
368 02:35:46.256873 TrainedVREFDQ_A1==74
369 02:35:46.257346 VrefDac_Margin_A0==25
370 02:35:46.257787 DeviceVref_Margin_A0==40
371 02:35:46.262464 VrefDac_Margin_A1==24
372 02:35:46.262924 DeviceVref_Margin_A1==40
373 02:35:46.263358
374 02:35:46.263796
375 02:35:46.264274 channel==1
376 02:35:46.268130 RxClkDly_Margin_A0==98 ps 10
377 02:35:46.268597 TxDqDly_Margin_A0==98 ps 10
378 02:35:46.273659 RxClkDly_Margin_A1==88 ps 9
379 02:35:46.274121 TxDqDly_Margin_A1==88 ps 9
380 02:35:46.279301 TrainedVREFDQ_A0==77
381 02:35:46.279766 TrainedVREFDQ_A1==77
382 02:35:46.280249 VrefDac_Margin_A0==23
383 02:35:46.284877 DeviceVref_Margin_A0==37
384 02:35:46.285338 VrefDac_Margin_A1==24
385 02:35:46.290461 DeviceVref_Margin_A1==37
386 02:35:46.290924
387 02:35:46.291367 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
388 02:35:46.291809
389 02:35:46.324202 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000018 00000017 00000016 00000018 00000015 00000018 00000019 00000017 00000019 00000018 0000001a 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000018 00000018 dram_vref_reg_value 0x 00000060
390 02:35:46.324783 2D training succeed
391 02:35:46.329666 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
392 02:35:46.335256 auto size-- 65535DDR cs0 size: 2048MB
393 02:35:46.335725 DDR cs1 size: 2048MB
394 02:35:46.340869 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
395 02:35:46.341336 cs0 DataBus test pass
396 02:35:46.346464 cs1 DataBus test pass
397 02:35:46.346926 cs0 AddrBus test pass
398 02:35:46.347372 cs1 AddrBus test pass
399 02:35:46.347813
400 02:35:46.352082 100bdlr_step_size ps== 420
401 02:35:46.352559 result report
402 02:35:46.357661 boot times 0Enable ddr reg access
403 02:35:46.362929 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
404 02:35:46.376416 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
405 02:35:46.950020 0.0;M3 CHK:0;cm4_sp_mode 0
406 02:35:46.950535 MVN_1=0x00000000
407 02:35:46.955558 MVN_2=0x00000000
408 02:35:46.961340 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
409 02:35:46.961827 OPS=0x10
410 02:35:46.962274 ring efuse init
411 02:35:46.962717 chipver efuse init
412 02:35:46.966915 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
413 02:35:46.972530 [0.018961 Inits done]
414 02:35:46.972990 secure task start!
415 02:35:46.973433 high task start!
416 02:35:46.977107 low task start!
417 02:35:46.977567 run into bl31
418 02:35:46.983726 NOTICE: BL31: v1.3(release):4fc40b1
419 02:35:46.991566 NOTICE: BL31: Built : 15:58:17, May 22 2019
420 02:35:46.992064 NOTICE: BL31: G12A normal boot!
421 02:35:47.016937 NOTICE: BL31: BL33 decompress pass
422 02:35:47.022630 ERROR: Error initializing runtime service opteed_fast
423 02:35:48.255651
424 02:35:48.256312
425 02:35:48.263977 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
426 02:35:48.264491
427 02:35:48.264938 Model: Libre Computer AML-A311D-CC Alta
428 02:35:48.472376 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
429 02:35:48.495766 DRAM: 2 GiB (effective 3.8 GiB)
430 02:35:48.638711 Core: 408 devices, 31 uclasses, devicetree: separate
431 02:35:48.644647 WDT: Not starting watchdog@f0d0
432 02:35:48.676881 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
433 02:35:48.689407 Loading Environment from FAT... Card did not respond to voltage select! : -110
434 02:35:48.694353 ** Bad device specification mmc 0 **
435 02:35:48.704668 Card did not respond to voltage select! : -110
436 02:35:48.712327 ** Bad device specification mmc 0 **
437 02:35:48.712792 Couldn't find partition mmc 0
438 02:35:48.720668 Card did not respond to voltage select! : -110
439 02:35:48.726182 ** Bad device specification mmc 0 **
440 02:35:48.726645 Couldn't find partition mmc 0
441 02:35:48.731228 Error: could not access storage.
442 02:35:49.994504 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
443 02:35:49.995062 bl2_stage_init 0x01
444 02:35:49.995520 bl2_stage_init 0x81
445 02:35:50.000085 hw id: 0x0000 - pwm id 0x01
446 02:35:50.000573 bl2_stage_init 0xc1
447 02:35:50.001023 bl2_stage_init 0x02
448 02:35:50.001460
449 02:35:50.005781 L0:00000000
450 02:35:50.006245 L1:20000703
451 02:35:50.006687 L2:00008067
452 02:35:50.007123 L3:14000000
453 02:35:50.011274 B2:00402000
454 02:35:50.011735 B1:e0f83180
455 02:35:50.012221
456 02:35:50.012661 TE: 58167
457 02:35:50.013100
458 02:35:50.016902 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
459 02:35:50.017376
460 02:35:50.017824 Board ID = 1
461 02:35:50.022479 Set A53 clk to 24M
462 02:35:50.022942 Set A73 clk to 24M
463 02:35:50.023387 Set clk81 to 24M
464 02:35:50.028083 A53 clk: 1200 MHz
465 02:35:50.028551 A73 clk: 1200 MHz
466 02:35:50.028994 CLK81: 166.6M
467 02:35:50.029430 smccc: 00012abe
468 02:35:50.033729 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
469 02:35:50.039278 board id: 1
470 02:35:50.045156 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
471 02:35:50.055809 fw parse done
472 02:35:50.061840 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
473 02:35:50.104417 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
474 02:35:50.115307 PIEI prepare done
475 02:35:50.115784 fastboot data load
476 02:35:50.116285 fastboot data verify
477 02:35:50.120918 verify result: 266
478 02:35:50.126523 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
479 02:35:50.126985 LPDDR4 probe
480 02:35:50.127427 ddr clk to 1584MHz
481 02:35:50.134489 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
482 02:35:50.171738
483 02:35:50.172233 dmc_version 0001
484 02:35:50.178420 Check phy result
485 02:35:50.184295 INFO : End of CA training
486 02:35:50.184757 INFO : End of initialization
487 02:35:50.189903 INFO : Training has run successfully!
488 02:35:50.190365 Check phy result
489 02:35:50.195495 INFO : End of initialization
490 02:35:50.195952 INFO : End of read enable training
491 02:35:50.198815 INFO : End of fine write leveling
492 02:35:50.204334 INFO : End of Write leveling coarse delay
493 02:35:50.209926 INFO : Training has run successfully!
494 02:35:50.210388 Check phy result
495 02:35:50.210831 INFO : End of initialization
496 02:35:50.215535 INFO : End of read dq deskew training
497 02:35:50.221162 INFO : End of MPR read delay center optimization
498 02:35:50.221632 INFO : End of write delay center optimization
499 02:35:50.226879 INFO : End of read delay center optimization
500 02:35:50.232337 INFO : End of max read latency training
501 02:35:50.232797 INFO : Training has run successfully!
502 02:35:50.237936 1D training succeed
503 02:35:50.243911 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
504 02:35:50.291463 Check phy result
505 02:35:50.291925 INFO : End of initialization
506 02:35:50.313227 INFO : End of 2D read delay Voltage center optimization
507 02:35:50.333472 INFO : End of 2D read delay Voltage center optimization
508 02:35:50.385499 INFO : End of 2D write delay Voltage center optimization
509 02:35:50.434963 INFO : End of 2D write delay Voltage center optimization
510 02:35:50.440711 INFO : Training has run successfully!
511 02:35:50.441175
512 02:35:50.441622 channel==0
513 02:35:50.446087 RxClkDly_Margin_A0==88 ps 9
514 02:35:50.446549 TxDqDly_Margin_A0==98 ps 10
515 02:35:50.451749 RxClkDly_Margin_A1==88 ps 9
516 02:35:50.452264 TxDqDly_Margin_A1==98 ps 10
517 02:35:50.452713 TrainedVREFDQ_A0==74
518 02:35:50.456742 TrainedVREFDQ_A1==74
519 02:35:50.459734 VrefDac_Margin_A0==25
520 02:35:50.460240 DeviceVref_Margin_A0==40
521 02:35:50.460687 VrefDac_Margin_A1==25
522 02:35:50.465225 DeviceVref_Margin_A1==40
523 02:35:50.465686
524 02:35:50.466125
525 02:35:50.466555 channel==1
526 02:35:50.470894 RxClkDly_Margin_A0==98 ps 10
527 02:35:50.471358 TxDqDly_Margin_A0==98 ps 10
528 02:35:50.471803 RxClkDly_Margin_A1==98 ps 10
529 02:35:50.476461 TxDqDly_Margin_A1==88 ps 9
530 02:35:50.476931 TrainedVREFDQ_A0==77
531 02:35:50.482363 TrainedVREFDQ_A1==77
532 02:35:50.482833 VrefDac_Margin_A0==22
533 02:35:50.483271 DeviceVref_Margin_A0==37
534 02:35:50.487924 VrefDac_Margin_A1==22
535 02:35:50.488412 DeviceVref_Margin_A1==37
536 02:35:50.488852
537 02:35:50.493552 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
538 02:35:50.494017
539 02:35:50.521589 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000017 00000018 00000018 00000019 00000018 00000019 0000001a 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
540 02:35:50.527171 2D training succeed
541 02:35:50.532829 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
542 02:35:50.533301 auto size-- 65535DDR cs0 size: 2048MB
543 02:35:50.538382 DDR cs1 size: 2048MB
544 02:35:50.538846 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
545 02:35:50.543972 cs0 DataBus test pass
546 02:35:50.544467 cs1 DataBus test pass
547 02:35:50.549578 cs0 AddrBus test pass
548 02:35:50.550046 cs1 AddrBus test pass
549 02:35:50.550488
550 02:35:50.550925 100bdlr_step_size ps== 420
551 02:35:50.555176 result report
552 02:35:50.555641 boot times 0Enable ddr reg access
553 02:35:50.563502 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
554 02:35:50.576993 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
555 02:35:51.150807 0.0;M3 CHK:0;cm4_sp_mode 0
556 02:35:51.151321 MVN_1=0x00000000
557 02:35:51.156249 MVN_2=0x00000000
558 02:35:51.162097 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
559 02:35:51.162601 OPS=0x10
560 02:35:51.163077 ring efuse init
561 02:35:51.163530 chipver efuse init
562 02:35:51.170521 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
563 02:35:51.171024 [0.018961 Inits done]
564 02:35:51.171452 secure task start!
565 02:35:51.177862 high task start!
566 02:35:51.178320 low task start!
567 02:35:51.178746 run into bl31
568 02:35:51.184572 NOTICE: BL31: v1.3(release):4fc40b1
569 02:35:51.192343 NOTICE: BL31: Built : 15:58:17, May 22 2019
570 02:35:51.192805 NOTICE: BL31: G12A normal boot!
571 02:35:51.217664 NOTICE: BL31: BL33 decompress pass
572 02:35:51.222391 ERROR: Error initializing runtime service opteed_fast
573 02:35:52.456290
574 02:35:52.456960
575 02:35:52.464714 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
576 02:35:52.465208
577 02:35:52.465671 Model: Libre Computer AML-A311D-CC Alta
578 02:35:52.673004 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
579 02:35:52.696453 DRAM: 2 GiB (effective 3.8 GiB)
580 02:35:52.839475 Core: 408 devices, 31 uclasses, devicetree: separate
581 02:35:52.845366 WDT: Not starting watchdog@f0d0
582 02:35:52.877571 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
583 02:35:52.889933 Loading Environment from FAT... Card did not respond to voltage select! : -110
584 02:35:52.895013 ** Bad device specification mmc 0 **
585 02:35:52.905349 Card did not respond to voltage select! : -110
586 02:35:52.913009 ** Bad device specification mmc 0 **
587 02:35:52.913480 Couldn't find partition mmc 0
588 02:35:52.921341 Card did not respond to voltage select! : -110
589 02:35:52.926867 ** Bad device specification mmc 0 **
590 02:35:52.927341 Couldn't find partition mmc 0
591 02:35:52.931398 Error: could not access storage.
592 02:35:53.274549 Net: eth0: ethernet@ff3f0000
593 02:35:53.275095 starting USB...
594 02:35:53.526299 Bus usb@ff500000: Register 3000140 NbrPorts 3
595 02:35:53.526992 Starting the controller
596 02:35:53.533238 USB XHCI 1.10
597 02:35:55.246514 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.�!,K��х��}���с0x01
598 02:35:55.247155 bl2_stage_init 0x81
599 02:35:55.252099 hw id: 0x0000 - pwm id 0x01
600 02:35:55.252577 bl2_stage_init 0xc1
601 02:35:55.252995 bl2_stage_init 0x02
602 02:35:55.253403
603 02:35:55.257784 L0:00000000
604 02:35:55.258252 L1:20000703
605 02:35:55.258665 L2:00008067
606 02:35:55.259071 L3:14000000
607 02:35:55.259469 B2:00402000
608 02:35:55.263256 B1:e0f83180
609 02:35:55.263719
610 02:35:55.264164 TE: 58150
611 02:35:55.264569
612 02:35:55.268971 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
613 02:35:55.269459
614 02:35:55.269876 Board ID = 1
615 02:35:55.277459 Set A53 clk to 24M
616 02:35:55.277930 Set A73 clk to 24M
617 02:35:55.278338 Set clk81 to 24M
618 02:35:55.279902 A53 clk: 1200 MHz
619 02:35:55.280382 A73 clk: 1200 MHz
620 02:35:55.280791 CLK81: 166.6M
621 02:35:55.281191 smccc: 00012aac
622 02:35:55.285394 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
623 02:35:55.291109 board id: 1
624 02:35:55.296965 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
625 02:35:55.307605 fw parse done
626 02:35:55.313577 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
627 02:35:55.356168 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
628 02:35:55.367075 PIEI prepare done
629 02:35:55.367538 fastboot data load
630 02:35:55.367949 fastboot data verify
631 02:35:55.372700 verify result: 266
632 02:35:55.378288 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
633 02:35:55.378753 LPDDR4 probe
634 02:35:55.379160 ddr clk to 1584MHz
635 02:35:55.386219 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
636 02:35:55.423618
637 02:35:55.424157 dmc_version 0001
638 02:35:55.430302 Check phy result
639 02:35:55.436206 INFO : End of CA training
640 02:35:55.436673 INFO : End of initialization
641 02:35:55.441675 INFO : Training has run successfully!
642 02:35:55.442133 Check phy result
643 02:35:55.447315 INFO : End of initialization
644 02:35:55.447773 INFO : End of read enable training
645 02:35:55.450725 INFO : End of fine write leveling
646 02:35:55.456285 INFO : End of Write leveling coarse delay
647 02:35:55.461886 INFO : Training has run successfully!
648 02:35:55.462355 Check phy result
649 02:35:55.462766 INFO : End of initialization
650 02:35:55.467468 INFO : End of read dq deskew training
651 02:35:55.470913 INFO : End of MPR read delay center optimization
652 02:35:55.476494 INFO : End of write delay center optimization
653 02:35:55.482083 INFO : End of read delay center optimization
654 02:35:55.482549 INFO : End of max read latency training
655 02:35:55.487673 INFO : Training has run successfully!
656 02:35:55.488162 1D training succeed
657 02:35:55.495728 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
658 02:35:55.543220 Check phy result
659 02:35:55.543715 INFO : End of initialization
660 02:35:55.564985 INFO : End of 2D read delay Voltage center optimization
661 02:35:55.584349 INFO : End of 2D read delay Voltage center optimization
662 02:35:55.637248 INFO : End of 2D write delay Voltage center optimization
663 02:35:55.686662 INFO : End of 2D write delay Voltage center optimization
664 02:35:55.692267 INFO : Training has run successfully!
665 02:35:55.692737
666 02:35:55.693149 channel==0
667 02:35:55.697801 RxClkDly_Margin_A0==88 ps 9
668 02:35:55.698270 TxDqDly_Margin_A0==98 ps 10
669 02:35:55.703403 RxClkDly_Margin_A1==88 ps 9
670 02:35:55.703868 TxDqDly_Margin_A1==98 ps 10
671 02:35:55.704331 TrainedVREFDQ_A0==74
672 02:35:55.709012 TrainedVREFDQ_A1==74
673 02:35:55.709479 VrefDac_Margin_A0==25
674 02:35:55.709890 DeviceVref_Margin_A0==40
675 02:35:55.714645 VrefDac_Margin_A1==25
676 02:35:55.715108 DeviceVref_Margin_A1==40
677 02:35:55.715515
678 02:35:55.715916
679 02:35:55.720244 channel==1
680 02:35:55.720716 RxClkDly_Margin_A0==98 ps 10
681 02:35:55.721124 TxDqDly_Margin_A0==98 ps 10
682 02:35:55.725807 RxClkDly_Margin_A1==88 ps 9
683 02:35:55.726272 TxDqDly_Margin_A1==88 ps 9
684 02:35:55.731397 TrainedVREFDQ_A0==77
685 02:35:55.731865 TrainedVREFDQ_A1==77
686 02:35:55.732309 VrefDac_Margin_A0==22
687 02:35:55.737007 DeviceVref_Margin_A0==37
688 02:35:55.737471 VrefDac_Margin_A1==24
689 02:35:55.742655 DeviceVref_Margin_A1==37
690 02:35:55.743131
691 02:35:55.743541 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
692 02:35:55.743937
693 02:35:55.776153 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000019 00000017 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 0000001a 00000018 00000017 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
694 02:35:55.776701 2D training succeed
695 02:35:55.781821 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
696 02:35:55.787417 auto size-- 65535DDR cs0 size: 2048MB
697 02:35:55.787882 DDR cs1 size: 2048MB
698 02:35:55.792992 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
699 02:35:55.793453 cs0 DataBus test pass
700 02:35:55.798659 cs1 DataBus test pass
701 02:35:55.799117 cs0 AddrBus test pass
702 02:35:55.799522 cs1 AddrBus test pass
703 02:35:55.799923
704 02:35:55.804240 100bdlr_step_size ps== 420
705 02:35:55.804718 result report
706 02:35:55.809801 boot times 0Enable ddr reg access
707 02:35:55.815048 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
708 02:35:55.828569 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
709 02:35:56.402304 0.0;M3 CHK:0;cm4_sp_mode 0
710 02:35:56.402939 MVN_1=0x00000000
711 02:35:56.407830 MVN_2=0x00000000
712 02:35:56.413647 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
713 02:35:56.414147 OPS=0x10
714 02:35:56.414545 ring efuse init
715 02:35:56.414939 chipver efuse init
716 02:35:56.419128 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
717 02:35:56.424683 [0.018961 Inits done]
718 02:35:56.425133 secure task start!
719 02:35:56.425526 high task start!
720 02:35:56.429285 low task start!
721 02:35:56.429727 run into bl31
722 02:35:56.435894 NOTICE: BL31: v1.3(release):4fc40b1
723 02:35:56.443720 NOTICE: BL31: Built : 15:58:17, May 22 2019
724 02:35:56.444214 NOTICE: BL31: G12A normal boot!
725 02:35:56.469083 NOTICE: BL31: BL33 decompress pass
726 02:35:56.474776 ERROR: Error initializing runtime service opteed_fast
727 02:35:57.707630
728 02:35:57.708345
729 02:35:57.716116 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
730 02:35:57.716593
731 02:35:57.717008 Model: Libre Computer AML-A311D-CC Alta
732 02:35:57.924523 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
733 02:35:57.947959 DRAM: 2 GiB (effective 3.8 GiB)
734 02:35:58.090933 Core: 408 devices, 31 uclasses, devicetree: separate
735 02:35:58.096658 WDT: Not starting watchdog@f0d0
736 02:35:58.129528 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
737 02:35:58.141412 Loading Environment from FAT... Card did not respond to voltage select! : -110
738 02:35:58.146441 ** Bad device specification mmc 0 **
739 02:35:58.156891 Card did not respond to voltage select! : -110
740 02:35:58.164413 ** Bad device specification mmc 0 **
741 02:35:58.164874 Couldn't find partition mmc 0
742 02:35:58.172762 Card did not respond to voltage select! : -110
743 02:35:58.178278 ** Bad device specification mmc 0 **
744 02:35:58.178736 Couldn't find partition mmc 0
745 02:35:58.183347 Error: could not access storage.
746 02:35:58.526464 Net: eth0: ethernet@ff3f0000
747 02:35:58.527079 starting USB...
748 02:35:58.777650 Bus usb@ff500000: Register 3000140 NbrPorts 3
749 02:35:58.778259 Starting the controller
750 02:35:58.784595 USB XHCI 1.10
751 02:36:00.944949 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
752 02:36:00.945572 bl2_stage_init 0x01
753 02:36:00.946001 bl2_stage_init 0x81
754 02:36:00.950427 hw id: 0x0000 - pwm id 0x01
755 02:36:00.950892 bl2_stage_init 0xc1
756 02:36:00.951308 bl2_stage_init 0x02
757 02:36:00.951711
758 02:36:00.956064 L0:00000000
759 02:36:00.956528 L1:20000703
760 02:36:00.956937 L2:00008067
761 02:36:00.957337 L3:14000000
762 02:36:00.959091 B2:00402000
763 02:36:00.959546 B1:e0f83180
764 02:36:00.959951
765 02:36:00.960400 TE: 58124
766 02:36:00.960804
767 02:36:00.970214 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
768 02:36:00.970711
769 02:36:00.971126 Board ID = 1
770 02:36:00.971524 Set A53 clk to 24M
771 02:36:00.971920 Set A73 clk to 24M
772 02:36:00.975843 Set clk81 to 24M
773 02:36:00.976336 A53 clk: 1200 MHz
774 02:36:00.976745 A73 clk: 1200 MHz
775 02:36:00.979281 CLK81: 166.6M
776 02:36:00.979731 smccc: 00012a91
777 02:36:00.984760 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
778 02:36:00.990462 board id: 1
779 02:36:00.995499 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
780 02:36:01.006156 fw parse done
781 02:36:01.012170 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
782 02:36:01.054644 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
783 02:36:01.065664 PIEI prepare done
784 02:36:01.066146 fastboot data load
785 02:36:01.066558 fastboot data verify
786 02:36:01.071261 verify result: 266
787 02:36:01.076837 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
788 02:36:01.077311 LPDDR4 probe
789 02:36:01.077718 ddr clk to 1584MHz
790 02:36:01.084840 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
791 02:36:01.122072
792 02:36:01.122575 dmc_version 0001
793 02:36:01.128796 Check phy result
794 02:36:01.134637 INFO : End of CA training
795 02:36:01.135099 INFO : End of initialization
796 02:36:01.140278 INFO : Training has run successfully!
797 02:36:01.140740 Check phy result
798 02:36:01.145831 INFO : End of initialization
799 02:36:01.146291 INFO : End of read enable training
800 02:36:01.151428 INFO : End of fine write leveling
801 02:36:01.156996 INFO : End of Write leveling coarse delay
802 02:36:01.157462 INFO : Training has run successfully!
803 02:36:01.157867 Check phy result
804 02:36:01.162628 INFO : End of initialization
805 02:36:01.163085 INFO : End of read dq deskew training
806 02:36:01.168282 INFO : End of MPR read delay center optimization
807 02:36:01.173830 INFO : End of write delay center optimization
808 02:36:01.179444 INFO : End of read delay center optimization
809 02:36:01.179907 INFO : End of max read latency training
810 02:36:01.185027 INFO : Training has run successfully!
811 02:36:01.185489 1D training succeed
812 02:36:01.194170 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
813 02:36:01.241840 Check phy result
814 02:36:01.242395 INFO : End of initialization
815 02:36:01.263572 INFO : End of 2D read delay Voltage center optimization
816 02:36:01.283793 INFO : End of 2D read delay Voltage center optimization
817 02:36:01.335883 INFO : End of 2D write delay Voltage center optimization
818 02:36:01.385236 INFO : End of 2D write delay Voltage center optimization
819 02:36:01.390787 INFO : Training has run successfully!
820 02:36:01.391276
821 02:36:01.391689 channel==0
822 02:36:01.396445 RxClkDly_Margin_A0==88 ps 9
823 02:36:01.396928 TxDqDly_Margin_A0==98 ps 10
824 02:36:01.401995 RxClkDly_Margin_A1==88 ps 9
825 02:36:01.402462 TxDqDly_Margin_A1==98 ps 10
826 02:36:01.402873 TrainedVREFDQ_A0==74
827 02:36:01.407621 TrainedVREFDQ_A1==74
828 02:36:01.408140 VrefDac_Margin_A0==25
829 02:36:01.408553 DeviceVref_Margin_A0==40
830 02:36:01.413174 VrefDac_Margin_A1==25
831 02:36:01.413653 DeviceVref_Margin_A1==40
832 02:36:01.414042
833 02:36:01.414423
834 02:36:01.418742 channel==1
835 02:36:01.419193 RxClkDly_Margin_A0==98 ps 10
836 02:36:01.419586 TxDqDly_Margin_A0==98 ps 10
837 02:36:01.424439 RxClkDly_Margin_A1==98 ps 10
838 02:36:01.424895 TxDqDly_Margin_A1==88 ps 9
839 02:36:01.429998 TrainedVREFDQ_A0==77
840 02:36:01.430473 TrainedVREFDQ_A1==77
841 02:36:01.430862 VrefDac_Margin_A0==22
842 02:36:01.435526 DeviceVref_Margin_A0==37
843 02:36:01.436007 VrefDac_Margin_A1==22
844 02:36:01.441172 DeviceVref_Margin_A1==37
845 02:36:01.441628
846 02:36:01.442014 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
847 02:36:01.446770
848 02:36:01.474728 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000018 00000018 00000016 00000017 00000015 00000017 00000019 00000017 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
849 02:36:01.475251 2D training succeed
850 02:36:01.480438 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
851 02:36:01.485967 auto size-- 65535DDR cs0 size: 2048MB
852 02:36:01.486420 DDR cs1 size: 2048MB
853 02:36:01.491564 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
854 02:36:01.492049 cs0 DataBus test pass
855 02:36:01.497166 cs1 DataBus test pass
856 02:36:01.497607 cs0 AddrBus test pass
857 02:36:01.497993 cs1 AddrBus test pass
858 02:36:01.498375
859 02:36:01.502780 100bdlr_step_size ps== 420
860 02:36:01.503257 result report
861 02:36:01.508440 boot times 0Enable ddr reg access
862 02:36:01.513772 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
863 02:36:01.527322 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
864 02:36:02.100938 0.0;M3 CHK:0;cm4_sp_mode 0
865 02:36:02.101562 MVN_1=0x00000000
866 02:36:02.106461 MVN_2=0x00000000
867 02:36:02.112171 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
868 02:36:02.112633 OPS=0x10
869 02:36:02.113043 ring efuse init
870 02:36:02.113442 chipver efuse init
871 02:36:02.120357 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
872 02:36:02.120838 [0.018961 Inits done]
873 02:36:02.121243 secure task start!
874 02:36:02.127915 high task start!
875 02:36:02.128457 low task start!
876 02:36:02.128895 run into bl31
877 02:36:02.134598 NOTICE: BL31: v1.3(release):4fc40b1
878 02:36:02.142381 NOTICE: BL31: Built : 15:58:17, May 22 2019
879 02:36:02.142853 NOTICE: BL31: G12A normal boot!
880 02:36:02.167725 NOTICE: BL31: BL33 decompress pass
881 02:36:02.173522 ERROR: Error initializing runtime service opteed_fast
882 02:36:03.406334
883 02:36:03.406954
884 02:36:03.414717 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
885 02:36:03.415192
886 02:36:03.415608 Model: Libre Computer AML-A311D-CC Alta
887 02:36:03.623088 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
888 02:36:03.646525 DRAM: 2 GiB (effective 3.8 GiB)
889 02:36:03.789489 Core: 408 devices, 31 uclasses, devicetree: separate
890 02:36:03.795312 WDT: Not starting watchdog@f0d0
891 02:36:03.827562 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
892 02:36:03.840114 Loading Environment from FAT... Card did not respond to voltage select! : -110
893 02:36:03.845008 ** Bad device specification mmc 0 **
894 02:36:03.855332 Card did not respond to voltage select! : -110
895 02:36:03.862994 ** Bad device specification mmc 0 **
896 02:36:03.863457 Couldn't find partition mmc 0
897 02:36:03.871340 Card did not respond to voltage select! : -110
898 02:36:03.876871 ** Bad device specification mmc 0 **
899 02:36:03.877334 Couldn't find partition mmc 0
900 02:36:03.881917 Error: could not access storage.
901 02:36:04.224376 Net: eth0: ethernet@ff3f0000
902 02:36:04.224962 starting USB...
903 02:36:04.476295 Bus usb@ff500000: Register 3000140 NbrPorts 3
904 02:36:04.476909 Starting the controller
905 02:36:04.483202 USB XHCI 1.10
906 02:36:06.344674 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
907 02:36:06.345287 bl2_stage_init 0x01
908 02:36:06.345706 bl2_stage_init 0x81
909 02:36:06.350332 hw id: 0x0000 - pwm id 0x01
910 02:36:06.350814 bl2_stage_init 0xc1
911 02:36:06.351230 bl2_stage_init 0x02
912 02:36:06.351630
913 02:36:06.355860 L0:00000000
914 02:36:06.356358 L1:20000703
915 02:36:06.356769 L2:00008067
916 02:36:06.357168 L3:14000000
917 02:36:06.361460 B2:00402000
918 02:36:06.361913 B1:e0f83180
919 02:36:06.362314
920 02:36:06.362713 TE: 58159
921 02:36:06.363111
922 02:36:06.367155 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
923 02:36:06.367617
924 02:36:06.368059 Board ID = 1
925 02:36:06.372655 Set A53 clk to 24M
926 02:36:06.373113 Set A73 clk to 24M
927 02:36:06.373517 Set clk81 to 24M
928 02:36:06.378260 A53 clk: 1200 MHz
929 02:36:06.378720 A73 clk: 1200 MHz
930 02:36:06.379124 CLK81: 166.6M
931 02:36:06.379519 smccc: 00012ab5
932 02:36:06.383858 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
933 02:36:06.389367 board id: 1
934 02:36:06.395373 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
935 02:36:06.406107 fw parse done
936 02:36:06.412080 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
937 02:36:06.454481 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
938 02:36:06.465362 PIEI prepare done
939 02:36:06.465829 fastboot data load
940 02:36:06.466222 fastboot data verify
941 02:36:06.471108 verify result: 266
942 02:36:06.476622 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
943 02:36:06.477078 LPDDR4 probe
944 02:36:06.477469 ddr clk to 1584MHz
945 02:36:06.484522 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
946 02:36:06.521894
947 02:36:06.522401 dmc_version 0001
948 02:36:06.528568 Check phy result
949 02:36:06.534400 INFO : End of CA training
950 02:36:06.534850 INFO : End of initialization
951 02:36:06.540125 INFO : Training has run successfully!
952 02:36:06.540588 Check phy result
953 02:36:06.545622 INFO : End of initialization
954 02:36:06.546137 INFO : End of read enable training
955 02:36:06.551258 INFO : End of fine write leveling
956 02:36:06.556799 INFO : End of Write leveling coarse delay
957 02:36:06.557315 INFO : Training has run successfully!
958 02:36:06.557733 Check phy result
959 02:36:06.562456 INFO : End of initialization
960 02:36:06.562935 INFO : End of read dq deskew training
961 02:36:06.568258 INFO : End of MPR read delay center optimization
962 02:36:06.573660 INFO : End of write delay center optimization
963 02:36:06.579227 INFO : End of read delay center optimization
964 02:36:06.579694 INFO : End of max read latency training
965 02:36:06.584815 INFO : Training has run successfully!
966 02:36:06.585277 1D training succeed
967 02:36:06.593989 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
968 02:36:06.641508 Check phy result
969 02:36:06.642011 INFO : End of initialization
970 02:36:06.663168 INFO : End of 2D read delay Voltage center optimization
971 02:36:06.683236 INFO : End of 2D read delay Voltage center optimization
972 02:36:06.735194 INFO : End of 2D write delay Voltage center optimization
973 02:36:06.784428 INFO : End of 2D write delay Voltage center optimization
974 02:36:06.789988 INFO : Training has run successfully!
975 02:36:06.790502
976 02:36:06.790938 channel==0
977 02:36:06.795606 RxClkDly_Margin_A0==88 ps 9
978 02:36:06.796110 TxDqDly_Margin_A0==98 ps 10
979 02:36:06.801159 RxClkDly_Margin_A1==88 ps 9
980 02:36:06.801655 TxDqDly_Margin_A1==88 ps 9
981 02:36:06.802082 TrainedVREFDQ_A0==74
982 02:36:06.806801 TrainedVREFDQ_A1==74
983 02:36:06.807274 VrefDac_Margin_A0==25
984 02:36:06.807718 DeviceVref_Margin_A0==40
985 02:36:06.812386 VrefDac_Margin_A1==25
986 02:36:06.812857 DeviceVref_Margin_A1==40
987 02:36:06.813263
988 02:36:06.813700
989 02:36:06.814106 channel==1
990 02:36:06.818177 RxClkDly_Margin_A0==98 ps 10
991 02:36:06.818653 TxDqDly_Margin_A0==88 ps 9
992 02:36:06.823580 RxClkDly_Margin_A1==98 ps 10
993 02:36:06.824099 TxDqDly_Margin_A1==88 ps 9
994 02:36:06.829165 TrainedVREFDQ_A0==77
995 02:36:06.829654 TrainedVREFDQ_A1==77
996 02:36:06.830085 VrefDac_Margin_A0==22
997 02:36:06.834780 DeviceVref_Margin_A0==37
998 02:36:06.835251 VrefDac_Margin_A1==22
999 02:36:06.840344 DeviceVref_Margin_A1==37
1000 02:36:06.840848
1001 02:36:06.841264 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
1002 02:36:06.841684
1003 02:36:06.873990 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000018 00000015 00000017 00000018 00000017 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 0000005f
1004 02:36:06.874541 2D training succeed
1005 02:36:06.879528 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
1006 02:36:06.885136 auto size-- 65535DDR cs0 size: 2048MB
1007 02:36:06.885609 DDR cs1 size: 2048MB
1008 02:36:06.890713 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
1009 02:36:06.891177 cs0 DataBus test pass
1010 02:36:06.896383 cs1 DataBus test pass
1011 02:36:06.896845 cs0 AddrBus test pass
1012 02:36:06.897258 cs1 AddrBus test pass
1013 02:36:06.897659
1014 02:36:06.902038 100bdlr_step_size ps== 420
1015 02:36:06.902507 result report
1016 02:36:06.907523 boot times 0Enable ddr reg access
1017 02:36:06.912847 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
1018 02:36:06.926311 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
1019 02:36:07.498298 0.0;M3 CHK:0;cm4_sp_mode 0
1020 02:36:07.498900 MVN_1=0x00000000
1021 02:36:07.503761 MVN_2=0x00000000
1022 02:36:07.509609 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
1023 02:36:07.510079 OPS=0x10
1024 02:36:07.510639 ring efuse init
1025 02:36:07.511070 chipver efuse init
1026 02:36:07.515243 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
1027 02:36:07.520790 [0.018960 Inits done]
1028 02:36:07.521253 secure task start!
1029 02:36:07.521665 high task start!
1030 02:36:07.525389 low task start!
1031 02:36:07.525850 run into bl31
1032 02:36:07.531944 NOTICE: BL31: v1.3(release):4fc40b1
1033 02:36:07.539753 NOTICE: BL31: Built : 15:58:17, May 22 2019
1034 02:36:07.540264 NOTICE: BL31: G12A normal boot!
1035 02:36:07.565237 NOTICE: BL31: BL33 decompress pass
1036 02:36:07.570898 ERROR: Error initializing runtime service opteed_fast
1037 02:36:08.803778
1038 02:36:08.804412
1039 02:36:08.812197 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
1040 02:36:08.812679
1041 02:36:08.813207 Model: Libre Computer AML-A311D-CC Alta
1042 02:36:09.020618 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
1043 02:36:09.044102 DRAM: 2 GiB (effective 3.8 GiB)
1044 02:36:09.187016 Core: 408 devices, 31 uclasses, devicetree: separate
1045 02:36:09.192901 WDT: Not starting watchdog@f0d0
1046 02:36:09.225074 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
1047 02:36:09.237566 Loading Environment from FAT... Card did not respond to voltage select! : -110
1048 02:36:09.242589 ** Bad device specification mmc 0 **
1049 02:36:09.252894 Card did not respond to voltage select! : -110
1050 02:36:09.260562 ** Bad device specification mmc 0 **
1051 02:36:09.261082 Couldn't find partition mmc 0
1052 02:36:09.268955 Card did not respond to voltage select! : -110
1053 02:36:09.274499 ** Bad device specification mmc 0 **
1054 02:36:09.274964 Couldn't find partition mmc 0
1055 02:36:09.279552 Error: could not access storage.
1056 02:36:09.621986 Net: eth0: ethernet@ff3f0000
1057 02:36:09.622590 starting USB...
1058 02:36:09.873763 Bus usb@ff500000: Register 3000140 NbrPorts 3
1059 02:36:09.874355 Starting the controller
1060 02:36:09.880656 USB XHCI 1.10
1061 02:36:11.436813 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
1062 02:36:11.445151 scanning usb for storage devices... 0 Storage Device(s) found
1064 02:36:11.496730 Hit any key to stop autoboot: 1
1065 02:36:11.497585 end: 2.4.2 bootloader-interrupt (duration 00:00:37) [common]
1066 02:36:11.498294 start: 2.4.3 bootloader-commands (timeout 00:04:23) [common]
1067 02:36:11.498759 Setting prompt string to ['=>']
1068 02:36:11.499225 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:23)
1069 02:36:11.512699 0
1070 02:36:11.513614 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1071 02:36:11.514102 Sending with 10 millisecond of delay
1073 02:36:12.648931 => setenv autoload no
1074 02:36:12.659729 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:22)
1075 02:36:12.664598 setenv autoload no
1076 02:36:12.665323 Sending with 10 millisecond of delay
1078 02:36:14.462182 => setenv initrd_high 0xffffffff
1079 02:36:14.472960 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:20)
1080 02:36:14.473784 setenv initrd_high 0xffffffff
1081 02:36:14.474488 Sending with 10 millisecond of delay
1083 02:36:16.090915 => setenv fdt_high 0xffffffff
1084 02:36:16.101682 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:19)
1085 02:36:16.102509 setenv fdt_high 0xffffffff
1086 02:36:16.103208 Sending with 10 millisecond of delay
1088 02:36:16.395042 => dhcp
1089 02:36:16.405739 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1090 02:36:16.406519 dhcp
1091 02:36:16.406942 Speed: 1000, full duplex
1092 02:36:16.407352 BOOTP broadcast 1
1093 02:36:16.418904 DHCP client bound to address 192.168.6.27 (13 ms)
1094 02:36:16.419619 Sending with 10 millisecond of delay
1096 02:36:18.096139 => setenv serverip 192.168.6.2
1097 02:36:18.106916 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:16)
1098 02:36:18.107766 setenv serverip 192.168.6.2
1099 02:36:18.108502 Sending with 10 millisecond of delay
1101 02:36:21.832279 => tftpboot 0x01080000 932144/tftp-deploy-njsy2zcp/kernel/uImage
1102 02:36:21.843076 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:13)
1103 02:36:21.843900 tftpboot 0x01080000 932144/tftp-deploy-njsy2zcp/kernel/uImage
1104 02:36:21.844415 Speed: 1000, full duplex
1105 02:36:21.844835 Using ethernet@ff3f0000 device
1106 02:36:21.845947 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1107 02:36:21.851439 Filename '932144/tftp-deploy-njsy2zcp/kernel/uImage'.
1108 02:36:21.855417 Load address: 0x1080000
1109 02:36:22.365191 Loading: *######## UDP wrong checksum 000000ff 00000e39
1110 02:36:22.386717 UDP wrong checksum 000000ff 0000922b
1111 02:36:24.869733 ########################################## 43.6 MiB
1112 02:36:24.870341 14.5 MiB/s
1113 02:36:24.870769 done
1114 02:36:24.874168 Bytes transferred = 45716032 (2b99240 hex)
1115 02:36:24.874983 Sending with 10 millisecond of delay
1117 02:36:29.563535 => tftpboot 0x08000000 932144/tftp-deploy-njsy2zcp/ramdisk/ramdisk.cpio.gz.uboot
1118 02:36:29.574638 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:05)
1119 02:36:29.575718 tftpboot 0x08000000 932144/tftp-deploy-njsy2zcp/ramdisk/ramdisk.cpio.gz.uboot
1120 02:36:29.576331 Speed: 1000, full duplex
1121 02:36:29.576877 Using ethernet@ff3f0000 device
1122 02:36:29.577348 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1123 02:36:29.589234 Filename '932144/tftp-deploy-njsy2zcp/ramdisk/ramdisk.cpio.gz.uboot'.
1124 02:36:29.589575 Load address: 0x8000000
1125 02:36:40.719680 Loading: *####T ############################################# UDP wrong checksum 0000000f 0000d442
1126 02:36:45.720128 T UDP wrong checksum 0000000f 0000d442
1127 02:36:55.722156 T T UDP wrong checksum 0000000f 0000d442
1128 02:37:14.974175 T T T UDP wrong checksum 000000ff 0000105f
1129 02:37:15.017832 UDP wrong checksum 000000ff 00009a51
1130 02:37:15.725949 T UDP wrong checksum 0000000f 0000d442
1131 02:37:30.729973 T T
1132 02:37:30.730582 Retry count exceeded; starting again
1134 02:37:30.732035 end: 2.4.3 bootloader-commands (duration 00:01:19) [common]
1137 02:37:30.733872 end: 2.4 uboot-commands (duration 00:01:56) [common]
1139 02:37:30.735278 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
1141 02:37:30.736309 end: 2 uboot-action (duration 00:01:56) [common]
1143 02:37:30.737804 Cleaning after the job
1144 02:37:30.738335 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/932144/tftp-deploy-njsy2zcp/ramdisk
1145 02:37:30.740657 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/932144/tftp-deploy-njsy2zcp/kernel
1146 02:37:30.787039 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/932144/tftp-deploy-njsy2zcp/dtb
1147 02:37:30.787809 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/932144/tftp-deploy-njsy2zcp/modules
1148 02:37:30.808267 start: 4.1 power-off (timeout 00:00:30) [common]
1149 02:37:30.808881 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1150 02:37:30.843736 >> OK - accepted request
1151 02:37:30.845488 Returned 0 in 0 seconds
1152 02:37:30.946186 end: 4.1 power-off (duration 00:00:00) [common]
1154 02:37:30.947085 start: 4.2 read-feedback (timeout 00:10:00) [common]
1155 02:37:30.947736 Listened to connection for namespace 'common' for up to 1s
1156 02:37:31.948661 Finalising connection for namespace 'common'
1157 02:37:31.949309 Disconnecting from shell: Finalise
1158 02:37:31.949816 =>
1159 02:37:32.050713 end: 4.2 read-feedback (duration 00:00:01) [common]
1160 02:37:32.051292 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/932144
1161 02:37:32.726571 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/932144
1162 02:37:32.727173 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.