Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 1
- Kernel Warnings: 6
- Errors: 0
- Boot result: PASS
- Kernel Errors: 3
1 02:42:54.263624 lava-dispatcher, installed at version: 2024.01
2 02:42:54.264476 start: 0 validate
3 02:42:54.264959 Start time: 2024-11-04 02:42:54.264929+00:00 (UTC)
4 02:42:54.265501 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 02:42:54.266051 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 02:42:54.307826 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 02:42:54.308416 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fpending-fixes%2Fv6.12-rc5-576-g10616629aaf32%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 02:42:54.339631 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 02:42:54.340308 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fpending-fixes%2Fv6.12-rc5-576-g10616629aaf32%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 02:42:54.374415 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 02:42:54.375191 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 02:42:54.408916 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 02:42:54.409420 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fpending-fixes%2Fv6.12-rc5-576-g10616629aaf32%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
14 02:42:54.448946 validate duration: 0.18
16 02:42:54.449778 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 02:42:54.450095 start: 1.1 download-retry (timeout 00:10:00) [common]
18 02:42:54.450403 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 02:42:54.450969 Not decompressing ramdisk as can be used compressed.
20 02:42:54.451412 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 02:42:54.451690 saving as /var/lib/lava/dispatcher/tmp/932188/tftp-deploy-cpxqodw7/ramdisk/initrd.cpio.gz
22 02:42:54.451953 total size: 5628169 (5 MB)
23 02:42:54.488156 progress 0 % (0 MB)
24 02:42:54.495928 progress 5 % (0 MB)
25 02:42:54.504171 progress 10 % (0 MB)
26 02:42:54.511297 progress 15 % (0 MB)
27 02:42:54.516049 progress 20 % (1 MB)
28 02:42:54.519924 progress 25 % (1 MB)
29 02:42:54.524194 progress 30 % (1 MB)
30 02:42:54.528346 progress 35 % (1 MB)
31 02:42:54.532002 progress 40 % (2 MB)
32 02:42:54.536107 progress 45 % (2 MB)
33 02:42:54.539910 progress 50 % (2 MB)
34 02:42:54.544051 progress 55 % (2 MB)
35 02:42:54.548160 progress 60 % (3 MB)
36 02:42:54.551815 progress 65 % (3 MB)
37 02:42:54.555864 progress 70 % (3 MB)
38 02:42:54.559498 progress 75 % (4 MB)
39 02:42:54.566546 progress 80 % (4 MB)
40 02:42:54.570979 progress 85 % (4 MB)
41 02:42:54.575894 progress 90 % (4 MB)
42 02:42:54.580672 progress 95 % (5 MB)
43 02:42:54.584677 progress 100 % (5 MB)
44 02:42:54.585476 5 MB downloaded in 0.13 s (40.21 MB/s)
45 02:42:54.586168 end: 1.1.1 http-download (duration 00:00:00) [common]
47 02:42:54.587329 end: 1.1 download-retry (duration 00:00:00) [common]
48 02:42:54.587724 start: 1.2 download-retry (timeout 00:10:00) [common]
49 02:42:54.588141 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 02:42:54.588752 downloading http://storage.kernelci.org/next/pending-fixes/v6.12-rc5-576-g10616629aaf32/arm64/defconfig/gcc-12/kernel/Image
51 02:42:54.589066 saving as /var/lib/lava/dispatcher/tmp/932188/tftp-deploy-cpxqodw7/kernel/Image
52 02:42:54.589343 total size: 45715968 (43 MB)
53 02:42:54.589615 No compression specified
54 02:42:54.628620 progress 0 % (0 MB)
55 02:42:54.657528 progress 5 % (2 MB)
56 02:42:54.687215 progress 10 % (4 MB)
57 02:42:54.716814 progress 15 % (6 MB)
58 02:42:54.746248 progress 20 % (8 MB)
59 02:42:54.775320 progress 25 % (10 MB)
60 02:42:54.804218 progress 30 % (13 MB)
61 02:42:54.833589 progress 35 % (15 MB)
62 02:42:54.863147 progress 40 % (17 MB)
63 02:42:54.892087 progress 45 % (19 MB)
64 02:42:54.921735 progress 50 % (21 MB)
65 02:42:54.950999 progress 55 % (24 MB)
66 02:42:54.980558 progress 60 % (26 MB)
67 02:42:55.009733 progress 65 % (28 MB)
68 02:42:55.039014 progress 70 % (30 MB)
69 02:42:55.069766 progress 75 % (32 MB)
70 02:42:55.098430 progress 80 % (34 MB)
71 02:42:55.127483 progress 85 % (37 MB)
72 02:42:55.156852 progress 90 % (39 MB)
73 02:42:55.185765 progress 95 % (41 MB)
74 02:42:55.214270 progress 100 % (43 MB)
75 02:42:55.214822 43 MB downloaded in 0.63 s (69.70 MB/s)
76 02:42:55.215300 end: 1.2.1 http-download (duration 00:00:01) [common]
78 02:42:55.216186 end: 1.2 download-retry (duration 00:00:01) [common]
79 02:42:55.216474 start: 1.3 download-retry (timeout 00:09:59) [common]
80 02:42:55.216748 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 02:42:55.217223 downloading http://storage.kernelci.org/next/pending-fixes/v6.12-rc5-576-g10616629aaf32/arm64/defconfig/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
82 02:42:55.217496 saving as /var/lib/lava/dispatcher/tmp/932188/tftp-deploy-cpxqodw7/dtb/meson-g12b-a311d-libretech-cc.dtb
83 02:42:55.217706 total size: 54703 (0 MB)
84 02:42:55.217917 No compression specified
85 02:42:55.257856 progress 59 % (0 MB)
86 02:42:55.258698 progress 100 % (0 MB)
87 02:42:55.259241 0 MB downloaded in 0.04 s (1.26 MB/s)
88 02:42:55.259730 end: 1.3.1 http-download (duration 00:00:00) [common]
90 02:42:55.260625 end: 1.3 download-retry (duration 00:00:00) [common]
91 02:42:55.260899 start: 1.4 download-retry (timeout 00:09:59) [common]
92 02:42:55.261170 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 02:42:55.261629 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 02:42:55.261871 saving as /var/lib/lava/dispatcher/tmp/932188/tftp-deploy-cpxqodw7/nfsrootfs/full.rootfs.tar
95 02:42:55.262080 total size: 120894716 (115 MB)
96 02:42:55.262293 Using unxz to decompress xz
97 02:42:55.298258 progress 0 % (0 MB)
98 02:42:56.087265 progress 5 % (5 MB)
99 02:42:56.923677 progress 10 % (11 MB)
100 02:42:57.728595 progress 15 % (17 MB)
101 02:42:58.472140 progress 20 % (23 MB)
102 02:42:59.068441 progress 25 % (28 MB)
103 02:42:59.904040 progress 30 % (34 MB)
104 02:43:00.701338 progress 35 % (40 MB)
105 02:43:01.062369 progress 40 % (46 MB)
106 02:43:01.435084 progress 45 % (51 MB)
107 02:43:02.149382 progress 50 % (57 MB)
108 02:43:03.030623 progress 55 % (63 MB)
109 02:43:03.808539 progress 60 % (69 MB)
110 02:43:04.581617 progress 65 % (74 MB)
111 02:43:05.367207 progress 70 % (80 MB)
112 02:43:06.192362 progress 75 % (86 MB)
113 02:43:06.972679 progress 80 % (92 MB)
114 02:43:07.732526 progress 85 % (98 MB)
115 02:43:08.588710 progress 90 % (103 MB)
116 02:43:09.363039 progress 95 % (109 MB)
117 02:43:10.199840 progress 100 % (115 MB)
118 02:43:10.212212 115 MB downloaded in 14.95 s (7.71 MB/s)
119 02:43:10.212908 end: 1.4.1 http-download (duration 00:00:15) [common]
121 02:43:10.214558 end: 1.4 download-retry (duration 00:00:15) [common]
122 02:43:10.215091 start: 1.5 download-retry (timeout 00:09:44) [common]
123 02:43:10.215618 start: 1.5.1 http-download (timeout 00:09:44) [common]
124 02:43:10.216454 downloading http://storage.kernelci.org/next/pending-fixes/v6.12-rc5-576-g10616629aaf32/arm64/defconfig/gcc-12/modules.tar.xz
125 02:43:10.216929 saving as /var/lib/lava/dispatcher/tmp/932188/tftp-deploy-cpxqodw7/modules/modules.tar
126 02:43:10.217345 total size: 11610988 (11 MB)
127 02:43:10.217769 Using unxz to decompress xz
128 02:43:10.264078 progress 0 % (0 MB)
129 02:43:10.330015 progress 5 % (0 MB)
130 02:43:10.403123 progress 10 % (1 MB)
131 02:43:10.497959 progress 15 % (1 MB)
132 02:43:10.589275 progress 20 % (2 MB)
133 02:43:10.668682 progress 25 % (2 MB)
134 02:43:10.744911 progress 30 % (3 MB)
135 02:43:10.822283 progress 35 % (3 MB)
136 02:43:10.895068 progress 40 % (4 MB)
137 02:43:10.969595 progress 45 % (5 MB)
138 02:43:11.052657 progress 50 % (5 MB)
139 02:43:11.128606 progress 55 % (6 MB)
140 02:43:11.214178 progress 60 % (6 MB)
141 02:43:11.294482 progress 65 % (7 MB)
142 02:43:11.375198 progress 70 % (7 MB)
143 02:43:11.453403 progress 75 % (8 MB)
144 02:43:11.537053 progress 80 % (8 MB)
145 02:43:11.618373 progress 85 % (9 MB)
146 02:43:11.698196 progress 90 % (9 MB)
147 02:43:11.775160 progress 95 % (10 MB)
148 02:43:11.851332 progress 100 % (11 MB)
149 02:43:11.862699 11 MB downloaded in 1.65 s (6.73 MB/s)
150 02:43:11.863317 end: 1.5.1 http-download (duration 00:00:02) [common]
152 02:43:11.864407 end: 1.5 download-retry (duration 00:00:02) [common]
153 02:43:11.864949 start: 1.6 prepare-tftp-overlay (timeout 00:09:43) [common]
154 02:43:11.865474 start: 1.6.1 extract-nfsrootfs (timeout 00:09:43) [common]
155 02:43:28.252533 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/932188/extract-nfsrootfs-4umrveq0
156 02:43:28.253144 end: 1.6.1 extract-nfsrootfs (duration 00:00:16) [common]
157 02:43:28.253443 start: 1.6.2 lava-overlay (timeout 00:09:26) [common]
158 02:43:28.254187 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/932188/lava-overlay-ztp0gbux
159 02:43:28.254713 makedir: /var/lib/lava/dispatcher/tmp/932188/lava-overlay-ztp0gbux/lava-932188/bin
160 02:43:28.255073 makedir: /var/lib/lava/dispatcher/tmp/932188/lava-overlay-ztp0gbux/lava-932188/tests
161 02:43:28.255397 makedir: /var/lib/lava/dispatcher/tmp/932188/lava-overlay-ztp0gbux/lava-932188/results
162 02:43:28.255741 Creating /var/lib/lava/dispatcher/tmp/932188/lava-overlay-ztp0gbux/lava-932188/bin/lava-add-keys
163 02:43:28.256318 Creating /var/lib/lava/dispatcher/tmp/932188/lava-overlay-ztp0gbux/lava-932188/bin/lava-add-sources
164 02:43:28.256860 Creating /var/lib/lava/dispatcher/tmp/932188/lava-overlay-ztp0gbux/lava-932188/bin/lava-background-process-start
165 02:43:28.257370 Creating /var/lib/lava/dispatcher/tmp/932188/lava-overlay-ztp0gbux/lava-932188/bin/lava-background-process-stop
166 02:43:28.257906 Creating /var/lib/lava/dispatcher/tmp/932188/lava-overlay-ztp0gbux/lava-932188/bin/lava-common-functions
167 02:43:28.258415 Creating /var/lib/lava/dispatcher/tmp/932188/lava-overlay-ztp0gbux/lava-932188/bin/lava-echo-ipv4
168 02:43:28.258916 Creating /var/lib/lava/dispatcher/tmp/932188/lava-overlay-ztp0gbux/lava-932188/bin/lava-install-packages
169 02:43:28.259405 Creating /var/lib/lava/dispatcher/tmp/932188/lava-overlay-ztp0gbux/lava-932188/bin/lava-installed-packages
170 02:43:28.259970 Creating /var/lib/lava/dispatcher/tmp/932188/lava-overlay-ztp0gbux/lava-932188/bin/lava-os-build
171 02:43:28.260532 Creating /var/lib/lava/dispatcher/tmp/932188/lava-overlay-ztp0gbux/lava-932188/bin/lava-probe-channel
172 02:43:28.261023 Creating /var/lib/lava/dispatcher/tmp/932188/lava-overlay-ztp0gbux/lava-932188/bin/lava-probe-ip
173 02:43:28.261511 Creating /var/lib/lava/dispatcher/tmp/932188/lava-overlay-ztp0gbux/lava-932188/bin/lava-target-ip
174 02:43:28.262016 Creating /var/lib/lava/dispatcher/tmp/932188/lava-overlay-ztp0gbux/lava-932188/bin/lava-target-mac
175 02:43:28.262568 Creating /var/lib/lava/dispatcher/tmp/932188/lava-overlay-ztp0gbux/lava-932188/bin/lava-target-storage
176 02:43:28.263079 Creating /var/lib/lava/dispatcher/tmp/932188/lava-overlay-ztp0gbux/lava-932188/bin/lava-test-case
177 02:43:28.263567 Creating /var/lib/lava/dispatcher/tmp/932188/lava-overlay-ztp0gbux/lava-932188/bin/lava-test-event
178 02:43:28.264082 Creating /var/lib/lava/dispatcher/tmp/932188/lava-overlay-ztp0gbux/lava-932188/bin/lava-test-feedback
179 02:43:28.264589 Creating /var/lib/lava/dispatcher/tmp/932188/lava-overlay-ztp0gbux/lava-932188/bin/lava-test-raise
180 02:43:28.265096 Creating /var/lib/lava/dispatcher/tmp/932188/lava-overlay-ztp0gbux/lava-932188/bin/lava-test-reference
181 02:43:28.265587 Creating /var/lib/lava/dispatcher/tmp/932188/lava-overlay-ztp0gbux/lava-932188/bin/lava-test-runner
182 02:43:28.266103 Creating /var/lib/lava/dispatcher/tmp/932188/lava-overlay-ztp0gbux/lava-932188/bin/lava-test-set
183 02:43:28.266644 Creating /var/lib/lava/dispatcher/tmp/932188/lava-overlay-ztp0gbux/lava-932188/bin/lava-test-shell
184 02:43:28.267145 Updating /var/lib/lava/dispatcher/tmp/932188/lava-overlay-ztp0gbux/lava-932188/bin/lava-add-keys (debian)
185 02:43:28.267687 Updating /var/lib/lava/dispatcher/tmp/932188/lava-overlay-ztp0gbux/lava-932188/bin/lava-add-sources (debian)
186 02:43:28.268230 Updating /var/lib/lava/dispatcher/tmp/932188/lava-overlay-ztp0gbux/lava-932188/bin/lava-install-packages (debian)
187 02:43:28.268751 Updating /var/lib/lava/dispatcher/tmp/932188/lava-overlay-ztp0gbux/lava-932188/bin/lava-installed-packages (debian)
188 02:43:28.269254 Updating /var/lib/lava/dispatcher/tmp/932188/lava-overlay-ztp0gbux/lava-932188/bin/lava-os-build (debian)
189 02:43:28.269697 Creating /var/lib/lava/dispatcher/tmp/932188/lava-overlay-ztp0gbux/lava-932188/environment
190 02:43:28.270072 LAVA metadata
191 02:43:28.270336 - LAVA_JOB_ID=932188
192 02:43:28.270556 - LAVA_DISPATCHER_IP=192.168.6.2
193 02:43:28.270916 start: 1.6.2.1 ssh-authorize (timeout 00:09:26) [common]
194 02:43:28.271879 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
195 02:43:28.272255 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:26) [common]
196 02:43:28.272470 skipped lava-vland-overlay
197 02:43:28.272713 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
198 02:43:28.272970 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:26) [common]
199 02:43:28.273189 skipped lava-multinode-overlay
200 02:43:28.273435 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
201 02:43:28.273687 start: 1.6.2.4 test-definition (timeout 00:09:26) [common]
202 02:43:28.273938 Loading test definitions
203 02:43:28.274213 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:26) [common]
204 02:43:28.274437 Using /lava-932188 at stage 0
205 02:43:28.275545 uuid=932188_1.6.2.4.1 testdef=None
206 02:43:28.275863 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
207 02:43:28.276162 start: 1.6.2.4.2 test-overlay (timeout 00:09:26) [common]
208 02:43:28.277732 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
210 02:43:28.278535 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:26) [common]
211 02:43:28.280480 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
213 02:43:28.281327 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:26) [common]
214 02:43:28.283160 runner path: /var/lib/lava/dispatcher/tmp/932188/lava-overlay-ztp0gbux/lava-932188/0/tests/0_timesync-off test_uuid 932188_1.6.2.4.1
215 02:43:28.283720 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
217 02:43:28.284612 start: 1.6.2.4.5 git-repo-action (timeout 00:09:26) [common]
218 02:43:28.284842 Using /lava-932188 at stage 0
219 02:43:28.285197 Fetching tests from https://github.com/kernelci/test-definitions.git
220 02:43:28.285493 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/932188/lava-overlay-ztp0gbux/lava-932188/0/tests/1_kselftest-alsa'
221 02:43:31.655417 Running '/usr/bin/git checkout kernelci.org
222 02:43:32.107155 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/932188/lava-overlay-ztp0gbux/lava-932188/0/tests/1_kselftest-alsa/automated/linux/kselftest/kselftest.yaml
223 02:43:32.109730 uuid=932188_1.6.2.4.5 testdef=None
224 02:43:32.110407 end: 1.6.2.4.5 git-repo-action (duration 00:00:04) [common]
226 02:43:32.112082 start: 1.6.2.4.6 test-overlay (timeout 00:09:22) [common]
227 02:43:32.118067 end: 1.6.2.4.6 test-overlay (duration 00:00:00) [common]
229 02:43:32.119853 start: 1.6.2.4.7 test-install-overlay (timeout 00:09:22) [common]
230 02:43:32.127908 end: 1.6.2.4.7 test-install-overlay (duration 00:00:00) [common]
232 02:43:32.129793 start: 1.6.2.4.8 test-runscript-overlay (timeout 00:09:22) [common]
233 02:43:32.137513 runner path: /var/lib/lava/dispatcher/tmp/932188/lava-overlay-ztp0gbux/lava-932188/0/tests/1_kselftest-alsa test_uuid 932188_1.6.2.4.5
234 02:43:32.138129 BOARD='meson-g12b-a311d-libretech-cc'
235 02:43:32.138621 BRANCH='next'
236 02:43:32.139071 SKIPFILE='/dev/null'
237 02:43:32.139517 SKIP_INSTALL='True'
238 02:43:32.139957 TESTPROG_URL='http://storage.kernelci.org/next/pending-fixes/v6.12-rc5-576-g10616629aaf32/arm64/defconfig/gcc-12/kselftest.tar.xz'
239 02:43:32.140442 TST_CASENAME=''
240 02:43:32.140887 TST_CMDFILES='alsa'
241 02:43:32.141997 end: 1.6.2.4.8 test-runscript-overlay (duration 00:00:00) [common]
243 02:43:32.143721 Creating lava-test-runner.conf files
244 02:43:32.144261 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/932188/lava-overlay-ztp0gbux/lava-932188/0 for stage 0
245 02:43:32.145038 - 0_timesync-off
246 02:43:32.145560 - 1_kselftest-alsa
247 02:43:32.146275 end: 1.6.2.4 test-definition (duration 00:00:04) [common]
248 02:43:32.146885 start: 1.6.2.5 compress-overlay (timeout 00:09:22) [common]
249 02:43:55.463609 end: 1.6.2.5 compress-overlay (duration 00:00:23) [common]
250 02:43:55.464062 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:08:59) [common]
251 02:43:55.464371 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
252 02:43:55.464687 end: 1.6.2 lava-overlay (duration 00:00:27) [common]
253 02:43:55.464991 start: 1.6.3 extract-overlay-ramdisk (timeout 00:08:59) [common]
254 02:43:56.083691 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:01) [common]
255 02:43:56.084198 start: 1.6.4 extract-modules (timeout 00:08:58) [common]
256 02:43:56.084463 extracting modules file /var/lib/lava/dispatcher/tmp/932188/tftp-deploy-cpxqodw7/modules/modules.tar to /var/lib/lava/dispatcher/tmp/932188/extract-nfsrootfs-4umrveq0
257 02:43:57.477186 extracting modules file /var/lib/lava/dispatcher/tmp/932188/tftp-deploy-cpxqodw7/modules/modules.tar to /var/lib/lava/dispatcher/tmp/932188/extract-overlay-ramdisk-vda87287/ramdisk
258 02:43:58.873577 end: 1.6.4 extract-modules (duration 00:00:03) [common]
259 02:43:58.874061 start: 1.6.5 apply-overlay-tftp (timeout 00:08:56) [common]
260 02:43:58.874344 [common] Applying overlay to NFS
261 02:43:58.874562 [common] Applying overlay /var/lib/lava/dispatcher/tmp/932188/compress-overlay-h7lr_rvv/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/932188/extract-nfsrootfs-4umrveq0
262 02:44:01.581440 end: 1.6.5 apply-overlay-tftp (duration 00:00:03) [common]
263 02:44:01.581910 start: 1.6.6 prepare-kernel (timeout 00:08:53) [common]
264 02:44:01.582187 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:08:53) [common]
265 02:44:01.582421 Converting downloaded kernel to a uImage
266 02:44:01.582732 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/932188/tftp-deploy-cpxqodw7/kernel/Image /var/lib/lava/dispatcher/tmp/932188/tftp-deploy-cpxqodw7/kernel/uImage
267 02:44:02.071601 output: Image Name:
268 02:44:02.072061 output: Created: Mon Nov 4 02:44:01 2024
269 02:44:02.072282 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
270 02:44:02.072492 output: Data Size: 45715968 Bytes = 44644.50 KiB = 43.60 MiB
271 02:44:02.072698 output: Load Address: 01080000
272 02:44:02.072900 output: Entry Point: 01080000
273 02:44:02.073101 output:
274 02:44:02.073439 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
275 02:44:02.073709 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
276 02:44:02.073982 start: 1.6.7 configure-preseed-file (timeout 00:08:52) [common]
277 02:44:02.074239 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
278 02:44:02.074500 start: 1.6.8 compress-ramdisk (timeout 00:08:52) [common]
279 02:44:02.074770 Building ramdisk /var/lib/lava/dispatcher/tmp/932188/extract-overlay-ramdisk-vda87287/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/932188/extract-overlay-ramdisk-vda87287/ramdisk
280 02:44:04.256115 >> 166828 blocks
281 02:44:11.930843 Adding RAMdisk u-boot header.
282 02:44:11.931492 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/932188/extract-overlay-ramdisk-vda87287/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/932188/extract-overlay-ramdisk-vda87287/ramdisk.cpio.gz.uboot
283 02:44:12.176853 output: Image Name:
284 02:44:12.177256 output: Created: Mon Nov 4 02:44:11 2024
285 02:44:12.177472 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
286 02:44:12.177682 output: Data Size: 23432018 Bytes = 22882.83 KiB = 22.35 MiB
287 02:44:12.177887 output: Load Address: 00000000
288 02:44:12.178087 output: Entry Point: 00000000
289 02:44:12.178291 output:
290 02:44:12.178978 rename /var/lib/lava/dispatcher/tmp/932188/extract-overlay-ramdisk-vda87287/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/932188/tftp-deploy-cpxqodw7/ramdisk/ramdisk.cpio.gz.uboot
291 02:44:12.179404 end: 1.6.8 compress-ramdisk (duration 00:00:10) [common]
292 02:44:12.179694 end: 1.6 prepare-tftp-overlay (duration 00:01:00) [common]
293 02:44:12.180102 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:42) [common]
294 02:44:12.180584 No LXC device requested
295 02:44:12.181106 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
296 02:44:12.181622 start: 1.8 deploy-device-env (timeout 00:08:42) [common]
297 02:44:12.182117 end: 1.8 deploy-device-env (duration 00:00:00) [common]
298 02:44:12.182528 Checking files for TFTP limit of 4294967296 bytes.
299 02:44:12.185227 end: 1 tftp-deploy (duration 00:01:18) [common]
300 02:44:12.185807 start: 2 uboot-action (timeout 00:05:00) [common]
301 02:44:12.186332 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
302 02:44:12.186829 end: 2.1 uboot-from-media (duration 00:00:00) [common]
303 02:44:12.187333 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
304 02:44:12.187860 Using kernel file from prepare-kernel: 932188/tftp-deploy-cpxqodw7/kernel/uImage
305 02:44:12.188525 substitutions:
306 02:44:12.188940 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
307 02:44:12.189347 - {DTB_ADDR}: 0x01070000
308 02:44:12.189747 - {DTB}: 932188/tftp-deploy-cpxqodw7/dtb/meson-g12b-a311d-libretech-cc.dtb
309 02:44:12.190149 - {INITRD}: 932188/tftp-deploy-cpxqodw7/ramdisk/ramdisk.cpio.gz.uboot
310 02:44:12.190544 - {KERNEL_ADDR}: 0x01080000
311 02:44:12.190939 - {KERNEL}: 932188/tftp-deploy-cpxqodw7/kernel/uImage
312 02:44:12.191335 - {LAVA_MAC}: None
313 02:44:12.191766 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/932188/extract-nfsrootfs-4umrveq0
314 02:44:12.192199 - {NFS_SERVER_IP}: 192.168.6.2
315 02:44:12.192596 - {PRESEED_CONFIG}: None
316 02:44:12.192989 - {PRESEED_LOCAL}: None
317 02:44:12.193379 - {RAMDISK_ADDR}: 0x08000000
318 02:44:12.193765 - {RAMDISK}: 932188/tftp-deploy-cpxqodw7/ramdisk/ramdisk.cpio.gz.uboot
319 02:44:12.194158 - {ROOT_PART}: None
320 02:44:12.194548 - {ROOT}: None
321 02:44:12.194935 - {SERVER_IP}: 192.168.6.2
322 02:44:12.195321 - {TEE_ADDR}: 0x83000000
323 02:44:12.195709 - {TEE}: None
324 02:44:12.196140 Parsed boot commands:
325 02:44:12.196528 - setenv autoload no
326 02:44:12.196917 - setenv initrd_high 0xffffffff
327 02:44:12.197302 - setenv fdt_high 0xffffffff
328 02:44:12.197686 - dhcp
329 02:44:12.198069 - setenv serverip 192.168.6.2
330 02:44:12.198456 - tftpboot 0x01080000 932188/tftp-deploy-cpxqodw7/kernel/uImage
331 02:44:12.198846 - tftpboot 0x08000000 932188/tftp-deploy-cpxqodw7/ramdisk/ramdisk.cpio.gz.uboot
332 02:44:12.199234 - tftpboot 0x01070000 932188/tftp-deploy-cpxqodw7/dtb/meson-g12b-a311d-libretech-cc.dtb
333 02:44:12.199624 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/932188/extract-nfsrootfs-4umrveq0,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
334 02:44:12.200062 - bootm 0x01080000 0x08000000 0x01070000
335 02:44:12.200570 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
337 02:44:12.202053 start: 2.3 connect-device (timeout 00:05:00) [common]
338 02:44:12.202473 [common] connect-device Connecting to device using 'telnet conserv1 3007'
339 02:44:12.219228 Setting prompt string to ['lava-test: # ']
340 02:44:12.220766 end: 2.3 connect-device (duration 00:00:00) [common]
341 02:44:12.221368 start: 2.4 uboot-commands (timeout 00:05:00) [common]
342 02:44:12.221940 start: 2.4.1 reset-device (timeout 00:05:00) [common]
343 02:44:12.222465 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
344 02:44:12.223631 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
345 02:44:12.257923 >> OK - accepted request
346 02:44:12.260117 Returned 0 in 0 seconds
347 02:44:12.361225 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
349 02:44:12.362771 end: 2.4.1 reset-device (duration 00:00:00) [common]
350 02:44:12.363313 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
351 02:44:12.363811 Setting prompt string to ['Hit any key to stop autoboot']
352 02:44:12.364308 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
353 02:44:12.365828 Trying 192.168.56.21...
354 02:44:12.366304 Connected to conserv1.
355 02:44:12.366714 Escape character is '^]'.
356 02:44:12.367121
357 02:44:12.367532 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
358 02:44:12.367941
359 02:44:23.987590 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
360 02:44:23.988265 bl2_stage_init 0x01
361 02:44:23.988713 bl2_stage_init 0x81
362 02:44:23.992931 hw id: 0x0000 - pwm id 0x01
363 02:44:23.993393 bl2_stage_init 0xc1
364 02:44:23.993800 bl2_stage_init 0x02
365 02:44:23.994189
366 02:44:23.998678 L0:00000000
367 02:44:23.999132 L1:20000703
368 02:44:23.999540 L2:00008067
369 02:44:23.999946 L3:14000000
370 02:44:24.001472 B2:00402000
371 02:44:24.001905 B1:e0f83180
372 02:44:24.002312
373 02:44:24.002701 TE: 58124
374 02:44:24.003087
375 02:44:24.012624 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
376 02:44:24.013051
377 02:44:24.013438 Board ID = 1
378 02:44:24.013821 Set A53 clk to 24M
379 02:44:24.014200 Set A73 clk to 24M
380 02:44:24.018088 Set clk81 to 24M
381 02:44:24.018501 A53 clk: 1200 MHz
382 02:44:24.018887 A73 clk: 1200 MHz
383 02:44:24.021748 CLK81: 166.6M
384 02:44:24.022167 smccc: 00012a91
385 02:44:24.027332 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
386 02:44:24.032935 board id: 1
387 02:44:24.038193 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
388 02:44:24.048539 fw parse done
389 02:44:24.054503 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
390 02:44:24.097127 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
391 02:44:24.108098 PIEI prepare done
392 02:44:24.108502 fastboot data load
393 02:44:24.108886 fastboot data verify
394 02:44:24.113684 verify result: 266
395 02:44:24.119433 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
396 02:44:24.119842 LPDDR4 probe
397 02:44:24.120271 ddr clk to 1584MHz
398 02:44:24.127317 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
399 02:44:24.164589
400 02:44:24.165007 dmc_version 0001
401 02:44:24.171266 Check phy result
402 02:44:24.177088 INFO : End of CA training
403 02:44:24.177498 INFO : End of initialization
404 02:44:24.182683 INFO : Training has run successfully!
405 02:44:24.183093 Check phy result
406 02:44:24.188263 INFO : End of initialization
407 02:44:24.188678 INFO : End of read enable training
408 02:44:24.193845 INFO : End of fine write leveling
409 02:44:24.199455 INFO : End of Write leveling coarse delay
410 02:44:24.199871 INFO : Training has run successfully!
411 02:44:24.200293 Check phy result
412 02:44:24.205040 INFO : End of initialization
413 02:44:24.205455 INFO : End of read dq deskew training
414 02:44:24.210656 INFO : End of MPR read delay center optimization
415 02:44:24.216354 INFO : End of write delay center optimization
416 02:44:24.221918 INFO : End of read delay center optimization
417 02:44:24.222341 INFO : End of max read latency training
418 02:44:24.227495 INFO : Training has run successfully!
419 02:44:24.227905 1D training succeed
420 02:44:24.236637 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
421 02:44:24.284312 Check phy result
422 02:44:24.284721 INFO : End of initialization
423 02:44:24.306875 INFO : End of 2D read delay Voltage center optimization
424 02:44:24.327083 INFO : End of 2D read delay Voltage center optimization
425 02:44:24.379173 INFO : End of 2D write delay Voltage center optimization
426 02:44:24.428540 INFO : End of 2D write delay Voltage center optimization
427 02:44:24.434113 INFO : Training has run successfully!
428 02:44:24.434528
429 02:44:24.434921 channel==0
430 02:44:24.439690 RxClkDly_Margin_A0==88 ps 9
431 02:44:24.440155 TxDqDly_Margin_A0==98 ps 10
432 02:44:24.445294 RxClkDly_Margin_A1==88 ps 9
433 02:44:24.445709 TxDqDly_Margin_A1==98 ps 10
434 02:44:24.446100 TrainedVREFDQ_A0==74
435 02:44:24.450892 TrainedVREFDQ_A1==74
436 02:44:24.451305 VrefDac_Margin_A0==24
437 02:44:24.451693 DeviceVref_Margin_A0==40
438 02:44:24.456526 VrefDac_Margin_A1==25
439 02:44:24.456939 DeviceVref_Margin_A1==40
440 02:44:24.457325
441 02:44:24.457712
442 02:44:24.462065 channel==1
443 02:44:24.462473 RxClkDly_Margin_A0==98 ps 10
444 02:44:24.462862 TxDqDly_Margin_A0==98 ps 10
445 02:44:24.467633 RxClkDly_Margin_A1==98 ps 10
446 02:44:24.468062 TxDqDly_Margin_A1==98 ps 10
447 02:44:24.473370 TrainedVREFDQ_A0==77
448 02:44:24.473785 TrainedVREFDQ_A1==77
449 02:44:24.474173 VrefDac_Margin_A0==22
450 02:44:24.478924 DeviceVref_Margin_A0==37
451 02:44:24.479352 VrefDac_Margin_A1==24
452 02:44:24.484536 DeviceVref_Margin_A1==37
453 02:44:24.484951
454 02:44:24.485346 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
455 02:44:24.490095
456 02:44:24.518087 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000018 00000018 00000016 00000018 00000016 00000017 00000019 00000017 00000019 00000018 0000001a 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
457 02:44:24.518584 2D training succeed
458 02:44:24.523711 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
459 02:44:24.529289 auto size-- 65535DDR cs0 size: 2048MB
460 02:44:24.529701 DDR cs1 size: 2048MB
461 02:44:24.534895 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
462 02:44:24.535326 cs0 DataBus test pass
463 02:44:24.540532 cs1 DataBus test pass
464 02:44:24.540948 cs0 AddrBus test pass
465 02:44:24.541339 cs1 AddrBus test pass
466 02:44:24.541724
467 02:44:24.546092 100bdlr_step_size ps== 420
468 02:44:24.546519 result report
469 02:44:24.551693 boot times 0Enable ddr reg access
470 02:44:24.557219 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
471 02:44:24.570746 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
472 02:44:25.143774 0.0;M3 CHK:0;cm4_sp_mode 0
473 02:44:25.144376 MVN_1=0x00000000
474 02:44:25.149186 MVN_2=0x00000000
475 02:44:25.154935 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
476 02:44:25.155364 OPS=0x10
477 02:44:25.155773 ring efuse init
478 02:44:25.156210 chipver efuse init
479 02:44:25.163175 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
480 02:44:25.163614 [0.018960 Inits done]
481 02:44:25.170717 secure task start!
482 02:44:25.171140 high task start!
483 02:44:25.171545 low task start!
484 02:44:25.171944 run into bl31
485 02:44:25.177445 NOTICE: BL31: v1.3(release):4fc40b1
486 02:44:25.185200 NOTICE: BL31: Built : 15:58:17, May 22 2019
487 02:44:25.185634 NOTICE: BL31: G12A normal boot!
488 02:44:25.210634 NOTICE: BL31: BL33 decompress pass
489 02:44:25.215376 ERROR: Error initializing runtime service opteed_fast
490 02:44:26.449222
491 02:44:26.449617
492 02:44:26.457598 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
493 02:44:26.458079
494 02:44:26.458501 Model: Libre Computer AML-A311D-CC Alta
495 02:44:26.666122 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
496 02:44:26.689417 DRAM: 2 GiB (effective 3.8 GiB)
497 02:44:26.832402 Core: 408 devices, 31 uclasses, devicetree: separate
498 02:44:26.838239 WDT: Not starting watchdog@f0d0
499 02:44:26.870472 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
500 02:44:26.882987 Loading Environment from FAT... Card did not respond to voltage select! : -110
501 02:44:26.887961 ** Bad device specification mmc 0 **
502 02:44:26.898248 Card did not respond to voltage select! : -110
503 02:44:26.905908 ** Bad device specification mmc 0 **
504 02:44:26.906340 Couldn't find partition mmc 0
505 02:44:26.914254 Card did not respond to voltage select! : -110
506 02:44:26.919854 ** Bad device specification mmc 0 **
507 02:44:26.920316 Couldn't find partition mmc 0
508 02:44:26.924909 Error: could not access storage.
509 02:44:28.187799 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
510 02:44:28.188453 bl2_stage_init 0x01
511 02:44:28.188894 bl2_stage_init 0x81
512 02:44:28.193332 hw id: 0x0000 - pwm id 0x01
513 02:44:28.193775 bl2_stage_init 0xc1
514 02:44:28.194187 bl2_stage_init 0x02
515 02:44:28.194590
516 02:44:28.199026 L0:00000000
517 02:44:28.199459 L1:20000703
518 02:44:28.199866 L2:00008067
519 02:44:28.200304 L3:14000000
520 02:44:28.204524 B2:00402000
521 02:44:28.204956 B1:e0f83180
522 02:44:28.205360
523 02:44:28.205759 TE: 58124
524 02:44:28.206155
525 02:44:28.210128 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
526 02:44:28.210556
527 02:44:28.210958 Board ID = 1
528 02:44:28.215773 Set A53 clk to 24M
529 02:44:28.216236 Set A73 clk to 24M
530 02:44:28.216646 Set clk81 to 24M
531 02:44:28.221323 A53 clk: 1200 MHz
532 02:44:28.221746 A73 clk: 1200 MHz
533 02:44:28.222149 CLK81: 166.6M
534 02:44:28.222541 smccc: 00012a91
535 02:44:28.227026 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
536 02:44:28.232509 board id: 1
537 02:44:28.238374 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
538 02:44:28.249051 fw parse done
539 02:44:28.254099 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
540 02:44:28.297631 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
541 02:44:28.308510 PIEI prepare done
542 02:44:28.308940 fastboot data load
543 02:44:28.309348 fastboot data verify
544 02:44:28.314113 verify result: 266
545 02:44:28.319715 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
546 02:44:28.320179 LPDDR4 probe
547 02:44:28.320578 ddr clk to 1584MHz
548 02:44:28.327706 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
549 02:44:28.365077
550 02:44:28.365513 dmc_version 0001
551 02:44:28.371644 Check phy result
552 02:44:28.377522 INFO : End of CA training
553 02:44:28.377944 INFO : End of initialization
554 02:44:28.383116 INFO : Training has run successfully!
555 02:44:28.383542 Check phy result
556 02:44:28.388737 INFO : End of initialization
557 02:44:28.389162 INFO : End of read enable training
558 02:44:28.394298 INFO : End of fine write leveling
559 02:44:28.399928 INFO : End of Write leveling coarse delay
560 02:44:28.400379 INFO : Training has run successfully!
561 02:44:28.400781 Check phy result
562 02:44:28.405527 INFO : End of initialization
563 02:44:28.405951 INFO : End of read dq deskew training
564 02:44:28.411116 INFO : End of MPR read delay center optimization
565 02:44:28.416723 INFO : End of write delay center optimization
566 02:44:28.422321 INFO : End of read delay center optimization
567 02:44:28.422738 INFO : End of max read latency training
568 02:44:28.427915 INFO : Training has run successfully!
569 02:44:28.428371 1D training succeed
570 02:44:28.437104 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
571 02:44:28.484716 Check phy result
572 02:44:28.485147 INFO : End of initialization
573 02:44:28.506534 INFO : End of 2D read delay Voltage center optimization
574 02:44:28.526716 INFO : End of 2D read delay Voltage center optimization
575 02:44:28.578739 INFO : End of 2D write delay Voltage center optimization
576 02:44:28.628150 INFO : End of 2D write delay Voltage center optimization
577 02:44:28.633684 INFO : Training has run successfully!
578 02:44:28.634107
579 02:44:28.634519 channel==0
580 02:44:28.639282 RxClkDly_Margin_A0==88 ps 9
581 02:44:28.639706 TxDqDly_Margin_A0==98 ps 10
582 02:44:28.644945 RxClkDly_Margin_A1==88 ps 9
583 02:44:28.645385 TxDqDly_Margin_A1==98 ps 10
584 02:44:28.645791 TrainedVREFDQ_A0==74
585 02:44:28.650475 TrainedVREFDQ_A1==74
586 02:44:28.650897 VrefDac_Margin_A0==25
587 02:44:28.651297 DeviceVref_Margin_A0==40
588 02:44:28.656076 VrefDac_Margin_A1==25
589 02:44:28.656500 DeviceVref_Margin_A1==40
590 02:44:28.656897
591 02:44:28.657295
592 02:44:28.661674 channel==1
593 02:44:28.662096 RxClkDly_Margin_A0==98 ps 10
594 02:44:28.662497 TxDqDly_Margin_A0==88 ps 9
595 02:44:28.667255 RxClkDly_Margin_A1==98 ps 10
596 02:44:28.667677 TxDqDly_Margin_A1==88 ps 9
597 02:44:28.672873 TrainedVREFDQ_A0==76
598 02:44:28.673299 TrainedVREFDQ_A1==77
599 02:44:28.673705 VrefDac_Margin_A0==22
600 02:44:28.678466 DeviceVref_Margin_A0==38
601 02:44:28.678883 VrefDac_Margin_A1==22
602 02:44:28.684079 DeviceVref_Margin_A1==37
603 02:44:28.684499
604 02:44:28.684898 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
605 02:44:28.685296
606 02:44:28.717669 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000018 00000018 00000016 00000017 00000015 00000018 00000019 00000017 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
607 02:44:28.718126 2D training succeed
608 02:44:28.723255 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
609 02:44:28.728855 auto size-- 65535DDR cs0 size: 2048MB
610 02:44:28.729295 DDR cs1 size: 2048MB
611 02:44:28.734441 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
612 02:44:28.734869 cs0 DataBus test pass
613 02:44:28.740100 cs1 DataBus test pass
614 02:44:28.740529 cs0 AddrBus test pass
615 02:44:28.740929 cs1 AddrBus test pass
616 02:44:28.741322
617 02:44:28.745656 100bdlr_step_size ps== 420
618 02:44:28.746092 result report
619 02:44:28.751274 boot times 0Enable ddr reg access
620 02:44:28.756621 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
621 02:44:28.770157 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
622 02:44:29.343584 0.0;M3 CHK:0;cm4_sp_mode 0
623 02:44:29.344120 MVN_1=0x00000000
624 02:44:29.348893 MVN_2=0x00000000
625 02:44:29.354707 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
626 02:44:29.355190 OPS=0x10
627 02:44:29.355628 ring efuse init
628 02:44:29.356055 chipver efuse init
629 02:44:29.360307 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
630 02:44:29.365859 [0.018961 Inits done]
631 02:44:29.366272 secure task start!
632 02:44:29.366654 high task start!
633 02:44:29.370437 low task start!
634 02:44:29.370849 run into bl31
635 02:44:29.376962 NOTICE: BL31: v1.3(release):4fc40b1
636 02:44:29.384884 NOTICE: BL31: Built : 15:58:17, May 22 2019
637 02:44:29.385298 NOTICE: BL31: G12A normal boot!
638 02:44:29.410306 NOTICE: BL31: BL33 decompress pass
639 02:44:29.415831 ERROR: Error initializing runtime service opteed_fast
640 02:44:30.648797
641 02:44:30.649301
642 02:44:30.657220 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
643 02:44:30.657655
644 02:44:30.658065 Model: Libre Computer AML-A311D-CC Alta
645 02:44:30.865574 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
646 02:44:30.888890 DRAM: 2 GiB (effective 3.8 GiB)
647 02:44:31.031897 Core: 408 devices, 31 uclasses, devicetree: separate
648 02:44:31.037812 WDT: Not starting watchdog@f0d0
649 02:44:31.069981 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
650 02:44:31.082594 Loading Environment from FAT... Card did not respond to voltage select! : -110
651 02:44:31.087535 ** Bad device specification mmc 0 **
652 02:44:31.097846 Card did not respond to voltage select! : -110
653 02:44:31.105523 ** Bad device specification mmc 0 **
654 02:44:31.105948 Couldn't find partition mmc 0
655 02:44:31.113797 Card did not respond to voltage select! : -110
656 02:44:31.119322 ** Bad device specification mmc 0 **
657 02:44:31.119761 Couldn't find partition mmc 0
658 02:44:31.124348 Error: could not access storage.
659 02:44:31.467919 Net: eth0: ethernet@ff3f0000
660 02:44:31.468408 starting USB...
661 02:44:31.719970 Bus usb@ff500000: Register 3000140 NbrPorts 3
662 02:44:31.720514 Starting the controller
663 02:44:31.726773 USB XHCI 1.10
664 02:44:33.438218 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.�!,K��х��}���с0x01
665 02:44:33.438853 bl2_stage_init 0x81
666 02:44:33.443822 hw id: 0x0000 - pwm id 0x01
667 02:44:33.444319 bl2_stage_init 0xc1
668 02:44:33.444735 bl2_stage_init 0x02
669 02:44:33.445140
670 02:44:33.449314 L0:00000000
671 02:44:33.449748 L1:20000703
672 02:44:33.450152 L2:00008067
673 02:44:33.450552 L3:14000000
674 02:44:33.450946 B2:00402000
675 02:44:33.452179 B1:e0f83180
676 02:44:33.452615
677 02:44:33.453022 TE: 58150
678 02:44:33.453423
679 02:44:33.463254 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
680 02:44:33.463712
681 02:44:33.464159 Board ID = 1
682 02:44:33.464565 Set A53 clk to 24M
683 02:44:33.464963 Set A73 clk to 24M
684 02:44:33.468999 Set clk81 to 24M
685 02:44:33.469433 A53 clk: 1200 MHz
686 02:44:33.469831 A73 clk: 1200 MHz
687 02:44:33.474519 CLK81: 166.6M
688 02:44:33.474954 smccc: 00012aab
689 02:44:33.480127 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
690 02:44:33.480566 board id: 1
691 02:44:33.488665 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
692 02:44:33.499252 fw parse done
693 02:44:33.505198 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
694 02:44:33.547812 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
695 02:44:33.558762 PIEI prepare done
696 02:44:33.559201 fastboot data load
697 02:44:33.559606 fastboot data verify
698 02:44:33.564421 verify result: 266
699 02:44:33.569993 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
700 02:44:33.570424 LPDDR4 probe
701 02:44:33.570823 ddr clk to 1584MHz
702 02:44:33.577981 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
703 02:44:33.615281
704 02:44:33.615709 dmc_version 0001
705 02:44:33.621911 Check phy result
706 02:44:33.627810 INFO : End of CA training
707 02:44:33.628263 INFO : End of initialization
708 02:44:33.633346 INFO : Training has run successfully!
709 02:44:33.633768 Check phy result
710 02:44:33.638944 INFO : End of initialization
711 02:44:33.639370 INFO : End of read enable training
712 02:44:33.642284 INFO : End of fine write leveling
713 02:44:33.647843 INFO : End of Write leveling coarse delay
714 02:44:33.653393 INFO : Training has run successfully!
715 02:44:33.653816 Check phy result
716 02:44:33.654213 INFO : End of initialization
717 02:44:33.658975 INFO : End of read dq deskew training
718 02:44:33.664594 INFO : End of MPR read delay center optimization
719 02:44:33.665020 INFO : End of write delay center optimization
720 02:44:33.670190 INFO : End of read delay center optimization
721 02:44:33.675814 INFO : End of max read latency training
722 02:44:33.676272 INFO : Training has run successfully!
723 02:44:33.681383 1D training succeed
724 02:44:33.687353 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
725 02:44:33.734981 Check phy result
726 02:44:33.735407 INFO : End of initialization
727 02:44:33.757382 INFO : End of 2D read delay Voltage center optimization
728 02:44:33.777560 INFO : End of 2D read delay Voltage center optimization
729 02:44:33.829483 INFO : End of 2D write delay Voltage center optimization
730 02:44:33.878653 INFO : End of 2D write delay Voltage center optimization
731 02:44:33.884232 INFO : Training has run successfully!
732 02:44:33.884653
733 02:44:33.885054 channel==0
734 02:44:33.889930 RxClkDly_Margin_A0==88 ps 9
735 02:44:33.890352 TxDqDly_Margin_A0==98 ps 10
736 02:44:33.893314 RxClkDly_Margin_A1==88 ps 9
737 02:44:33.893734 TxDqDly_Margin_A1==98 ps 10
738 02:44:33.898965 TrainedVREFDQ_A0==74
739 02:44:33.899387 TrainedVREFDQ_A1==74
740 02:44:33.899789 VrefDac_Margin_A0==24
741 02:44:33.904401 DeviceVref_Margin_A0==40
742 02:44:33.904824 VrefDac_Margin_A1==25
743 02:44:33.910106 DeviceVref_Margin_A1==40
744 02:44:33.910524
745 02:44:33.910930
746 02:44:33.911327 channel==1
747 02:44:33.911721 RxClkDly_Margin_A0==98 ps 10
748 02:44:33.913550 TxDqDly_Margin_A0==98 ps 10
749 02:44:33.919114 RxClkDly_Margin_A1==98 ps 10
750 02:44:33.919540 TxDqDly_Margin_A1==98 ps 10
751 02:44:33.919945 TrainedVREFDQ_A0==77
752 02:44:33.924718 TrainedVREFDQ_A1==77
753 02:44:33.925159 VrefDac_Margin_A0==22
754 02:44:33.930256 DeviceVref_Margin_A0==37
755 02:44:33.930677 VrefDac_Margin_A1==22
756 02:44:33.931072 DeviceVref_Margin_A1==37
757 02:44:33.931469
758 02:44:33.939303 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
759 02:44:33.939732
760 02:44:33.967304 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000017 00000019 00000017 00000019 00000018 0000001a 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
761 02:44:33.967754 2D training succeed
762 02:44:33.978354 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
763 02:44:33.978784 auto size-- 65535DDR cs0 size: 2048MB
764 02:44:33.979186 DDR cs1 size: 2048MB
765 02:44:33.983953 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
766 02:44:33.984410 cs0 DataBus test pass
767 02:44:33.989560 cs1 DataBus test pass
768 02:44:33.989987 cs0 AddrBus test pass
769 02:44:33.995182 cs1 AddrBus test pass
770 02:44:33.995607
771 02:44:33.996038 100bdlr_step_size ps== 420
772 02:44:33.996450 result report
773 02:44:34.000781 boot times 0Enable ddr reg access
774 02:44:34.007362 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
775 02:44:34.020762 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
776 02:44:34.592845 0.0;M3 CHK:0;cm4_sp_mode 0
777 02:44:34.593415 MVN_1=0x00000000
778 02:44:34.598295 MVN_2=0x00000000
779 02:44:34.604093 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
780 02:44:34.604578 OPS=0x10
781 02:44:34.604972 ring efuse init
782 02:44:34.605358 chipver efuse init
783 02:44:34.609645 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
784 02:44:34.615276 [0.018961 Inits done]
785 02:44:34.615701 secure task start!
786 02:44:34.616118 high task start!
787 02:44:34.619840 low task start!
788 02:44:34.620286 run into bl31
789 02:44:34.626444 NOTICE: BL31: v1.3(release):4fc40b1
790 02:44:34.634252 NOTICE: BL31: Built : 15:58:17, May 22 2019
791 02:44:34.634673 NOTICE: BL31: G12A normal boot!
792 02:44:34.659567 NOTICE: BL31: BL33 decompress pass
793 02:44:34.665263 ERROR: Error initializing runtime service opteed_fast
794 02:44:35.898312
795 02:44:35.898821
796 02:44:35.906634 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
797 02:44:35.907074
798 02:44:35.907483 Model: Libre Computer AML-A311D-CC Alta
799 02:44:36.115169 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
800 02:44:36.138480 DRAM: 2 GiB (effective 3.8 GiB)
801 02:44:36.281417 Core: 408 devices, 31 uclasses, devicetree: separate
802 02:44:36.287326 WDT: Not starting watchdog@f0d0
803 02:44:36.319548 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
804 02:44:36.332162 Loading Environment from FAT... Card did not respond to voltage select! : -110
805 02:44:36.337085 ** Bad device specification mmc 0 **
806 02:44:36.347336 Card did not respond to voltage select! : -110
807 02:44:36.354984 ** Bad device specification mmc 0 **
808 02:44:36.355414 Couldn't find partition mmc 0
809 02:44:36.363333 Card did not respond to voltage select! : -110
810 02:44:36.368840 ** Bad device specification mmc 0 **
811 02:44:36.369269 Couldn't find partition mmc 0
812 02:44:36.373904 Error: could not access storage.
813 02:44:36.717404 Net: eth0: ethernet@ff3f0000
814 02:44:36.717861 starting USB...
815 02:44:36.969309 Bus usb@ff500000: Register 3000140 NbrPorts 3
816 02:44:36.969756 Starting the controller
817 02:44:36.976177 USB XHCI 1.10
818 02:44:39.138080 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
819 02:44:39.138700 bl2_stage_init 0x01
820 02:44:39.139118 bl2_stage_init 0x81
821 02:44:39.143664 hw id: 0x0000 - pwm id 0x01
822 02:44:39.144126 bl2_stage_init 0xc1
823 02:44:39.144534 bl2_stage_init 0x02
824 02:44:39.144933
825 02:44:39.149131 L0:00000000
826 02:44:39.149558 L1:20000703
827 02:44:39.149955 L2:00008067
828 02:44:39.150347 L3:14000000
829 02:44:39.154834 B2:00402000
830 02:44:39.155264 B1:e0f83180
831 02:44:39.155667
832 02:44:39.156098 TE: 58124
833 02:44:39.156504
834 02:44:39.160358 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
835 02:44:39.160792
836 02:44:39.161192 Board ID = 1
837 02:44:39.165954 Set A53 clk to 24M
838 02:44:39.166376 Set A73 clk to 24M
839 02:44:39.166773 Set clk81 to 24M
840 02:44:39.171782 A53 clk: 1200 MHz
841 02:44:39.172238 A73 clk: 1200 MHz
842 02:44:39.172633 CLK81: 166.6M
843 02:44:39.173026 smccc: 00012a92
844 02:44:39.177184 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
845 02:44:39.182802 board id: 1
846 02:44:39.188834 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
847 02:44:39.199342 fw parse done
848 02:44:39.205383 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
849 02:44:39.247810 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
850 02:44:39.258692 PIEI prepare done
851 02:44:39.259119 fastboot data load
852 02:44:39.259522 fastboot data verify
853 02:44:39.264290 verify result: 266
854 02:44:39.269897 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
855 02:44:39.270327 LPDDR4 probe
856 02:44:39.270728 ddr clk to 1584MHz
857 02:44:39.277870 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
858 02:44:39.315108
859 02:44:39.315530 dmc_version 0001
860 02:44:39.321774 Check phy result
861 02:44:39.327674 INFO : End of CA training
862 02:44:39.328137 INFO : End of initialization
863 02:44:39.333340 INFO : Training has run successfully!
864 02:44:39.333762 Check phy result
865 02:44:39.338875 INFO : End of initialization
866 02:44:39.339325 INFO : End of read enable training
867 02:44:39.344543 INFO : End of fine write leveling
868 02:44:39.350074 INFO : End of Write leveling coarse delay
869 02:44:39.350500 INFO : Training has run successfully!
870 02:44:39.350900 Check phy result
871 02:44:39.355689 INFO : End of initialization
872 02:44:39.356139 INFO : End of read dq deskew training
873 02:44:39.361272 INFO : End of MPR read delay center optimization
874 02:44:39.366871 INFO : End of write delay center optimization
875 02:44:39.372544 INFO : End of read delay center optimization
876 02:44:39.372965 INFO : End of max read latency training
877 02:44:39.378072 INFO : Training has run successfully!
878 02:44:39.378499 1D training succeed
879 02:44:39.387259 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
880 02:44:39.434862 Check phy result
881 02:44:39.435293 INFO : End of initialization
882 02:44:39.456642 INFO : End of 2D read delay Voltage center optimization
883 02:44:39.476016 INFO : End of 2D read delay Voltage center optimization
884 02:44:39.528079 INFO : End of 2D write delay Voltage center optimization
885 02:44:39.577642 INFO : End of 2D write delay Voltage center optimization
886 02:44:39.583088 INFO : Training has run successfully!
887 02:44:39.583550
888 02:44:39.583964 channel==0
889 02:44:39.588646 RxClkDly_Margin_A0==88 ps 9
890 02:44:39.589136 TxDqDly_Margin_A0==98 ps 10
891 02:44:39.594175 RxClkDly_Margin_A1==88 ps 9
892 02:44:39.594617 TxDqDly_Margin_A1==98 ps 10
893 02:44:39.595041 TrainedVREFDQ_A0==74
894 02:44:39.599787 TrainedVREFDQ_A1==74
895 02:44:39.600326 VrefDac_Margin_A0==25
896 02:44:39.600734 DeviceVref_Margin_A0==40
897 02:44:39.605410 VrefDac_Margin_A1==25
898 02:44:39.605901 DeviceVref_Margin_A1==40
899 02:44:39.606314
900 02:44:39.606706
901 02:44:39.611006 channel==1
902 02:44:39.611459 RxClkDly_Margin_A0==78 ps 8
903 02:44:39.611845 TxDqDly_Margin_A0==88 ps 9
904 02:44:39.616601 RxClkDly_Margin_A1==88 ps 9
905 02:44:39.617032 TxDqDly_Margin_A1==88 ps 9
906 02:44:39.622189 TrainedVREFDQ_A0==77
907 02:44:39.622670 TrainedVREFDQ_A1==77
908 02:44:39.623062 VrefDac_Margin_A0==23
909 02:44:39.627776 DeviceVref_Margin_A0==37
910 02:44:39.628259 VrefDac_Margin_A1==24
911 02:44:39.633428 DeviceVref_Margin_A1==37
912 02:44:39.633852
913 02:44:39.634243 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
914 02:44:39.634627
915 02:44:39.667053 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000017 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000017 00000019 00000017 00000019 00000018 00000019 00000019 00000018 00000017 00000018 00000017 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
916 02:44:39.667613 2D training succeed
917 02:44:39.672655 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
918 02:44:39.678229 auto size-- 65535DDR cs0 size: 2048MB
919 02:44:39.678676 DDR cs1 size: 2048MB
920 02:44:39.683832 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
921 02:44:39.684353 cs0 DataBus test pass
922 02:44:39.689398 cs1 DataBus test pass
923 02:44:39.689820 cs0 AddrBus test pass
924 02:44:39.690203 cs1 AddrBus test pass
925 02:44:39.690585
926 02:44:39.694994 100bdlr_step_size ps== 420
927 02:44:39.695429 result report
928 02:44:39.700655 boot times 0Enable ddr reg access
929 02:44:39.705759 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
930 02:44:39.718323 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
931 02:44:40.292488 0.0;M3 CHK:0;cm4_sp_mode 0
932 02:44:40.293110 MVN_1=0x00000000
933 02:44:40.297824 MVN_2=0x00000000
934 02:44:40.303688 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
935 02:44:40.304221 OPS=0x10
936 02:44:40.304642 ring efuse init
937 02:44:40.305044 chipver efuse init
938 02:44:40.309176 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
939 02:44:40.314780 [0.018960 Inits done]
940 02:44:40.315233 secure task start!
941 02:44:40.315640 high task start!
942 02:44:40.319377 low task start!
943 02:44:40.319850 run into bl31
944 02:44:40.326013 NOTICE: BL31: v1.3(release):4fc40b1
945 02:44:40.333807 NOTICE: BL31: Built : 15:58:17, May 22 2019
946 02:44:40.334270 NOTICE: BL31: G12A normal boot!
947 02:44:40.359201 NOTICE: BL31: BL33 decompress pass
948 02:44:40.364832 ERROR: Error initializing runtime service opteed_fast
949 02:44:41.597786
950 02:44:41.598390
951 02:44:41.606079 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
952 02:44:41.606550
953 02:44:41.606959 Model: Libre Computer AML-A311D-CC Alta
954 02:44:41.814573 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
955 02:44:41.837989 DRAM: 2 GiB (effective 3.8 GiB)
956 02:44:41.980991 Core: 408 devices, 31 uclasses, devicetree: separate
957 02:44:41.986770 WDT: Not starting watchdog@f0d0
958 02:44:42.019017 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
959 02:44:42.031594 Loading Environment from FAT... Card did not respond to voltage select! : -110
960 02:44:42.036479 ** Bad device specification mmc 0 **
961 02:44:42.046859 Card did not respond to voltage select! : -110
962 02:44:42.054456 ** Bad device specification mmc 0 **
963 02:44:42.054933 Couldn't find partition mmc 0
964 02:44:42.062797 Card did not respond to voltage select! : -110
965 02:44:42.068301 ** Bad device specification mmc 0 **
966 02:44:42.068756 Couldn't find partition mmc 0
967 02:44:42.073364 Error: could not access storage.
968 02:44:42.415876 Net: eth0: ethernet@ff3f0000
969 02:44:42.416458 starting USB...
970 02:44:42.667738 Bus usb@ff500000: Register 3000140 NbrPorts 3
971 02:44:42.668372 Starting the controller
972 02:44:42.674592 USB XHCI 1.10
973 02:44:44.228739 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
974 02:44:44.237014 scanning usb for storage devices... 0 Storage Device(s) found
976 02:44:44.288573 Hit any key to stop autoboot: 1
977 02:44:44.289375 end: 2.4.2 bootloader-interrupt (duration 00:00:32) [common]
978 02:44:44.289979 start: 2.4.3 bootloader-commands (timeout 00:04:28) [common]
979 02:44:44.290467 Setting prompt string to ['=>']
980 02:44:44.290952 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:28)
981 02:44:44.304550 0
982 02:44:44.305414 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
983 02:44:44.305894 Sending with 10 millisecond of delay
985 02:44:45.440506 => setenv autoload no
986 02:44:45.451271 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:27)
987 02:44:45.456238 setenv autoload no
988 02:44:45.456981 Sending with 10 millisecond of delay
990 02:44:47.253750 => setenv initrd_high 0xffffffff
991 02:44:47.264506 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:25)
992 02:44:47.265335 setenv initrd_high 0xffffffff
993 02:44:47.266033 Sending with 10 millisecond of delay
995 02:44:48.882172 => setenv fdt_high 0xffffffff
996 02:44:48.892894 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:23)
997 02:44:48.893654 setenv fdt_high 0xffffffff
998 02:44:48.894344 Sending with 10 millisecond of delay
1000 02:44:49.186038 => dhcp
1001 02:44:49.196624 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:23)
1002 02:44:49.197352 dhcp
1003 02:44:49.197770 Speed: 1000, full duplex
1004 02:44:49.198174 BOOTP broadcast 1
1005 02:44:49.209457 DHCP client bound to address 192.168.6.27 (13 ms)
1006 02:44:49.210129 Sending with 10 millisecond of delay
1008 02:44:50.886149 => setenv serverip 192.168.6.2
1009 02:44:50.896870 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:21)
1010 02:44:50.897715 setenv serverip 192.168.6.2
1011 02:44:50.898395 Sending with 10 millisecond of delay
1013 02:44:54.621335 => tftpboot 0x01080000 932188/tftp-deploy-cpxqodw7/kernel/uImage
1014 02:44:54.632117 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1015 02:44:54.632962 tftpboot 0x01080000 932188/tftp-deploy-cpxqodw7/kernel/uImage
1016 02:44:54.633407 Speed: 1000, full duplex
1017 02:44:54.633821 Using ethernet@ff3f0000 device
1018 02:44:54.635009 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1019 02:44:54.640579 Filename '932188/tftp-deploy-cpxqodw7/kernel/uImage'.
1020 02:44:54.644391 Load address: 0x1080000
1021 02:44:57.642523 Loading: *################################################## 43.6 MiB
1022 02:44:57.643150 14.5 MiB/s
1023 02:44:57.643581 done
1024 02:44:57.646968 Bytes transferred = 45716032 (2b99240 hex)
1025 02:44:57.647704 Sending with 10 millisecond of delay
1027 02:45:02.333488 => tftpboot 0x08000000 932188/tftp-deploy-cpxqodw7/ramdisk/ramdisk.cpio.gz.uboot
1028 02:45:02.344278 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:10)
1029 02:45:02.345090 tftpboot 0x08000000 932188/tftp-deploy-cpxqodw7/ramdisk/ramdisk.cpio.gz.uboot
1030 02:45:02.345531 Speed: 1000, full duplex
1031 02:45:02.345945 Using ethernet@ff3f0000 device
1032 02:45:02.347072 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1033 02:45:02.358861 Filename '932188/tftp-deploy-cpxqodw7/ramdisk/ramdisk.cpio.gz.uboot'.
1034 02:45:02.359323 Load address: 0x8000000
1035 02:45:09.447796 Loading: *###########T ################################### UDP wrong checksum 000000ff 00001301
1036 02:45:09.487557 # UDP wrong checksum 000000ff 0000aef3
1037 02:45:09.622419 ### 22.3 MiB
1038 02:45:09.622950 3.1 MiB/s
1039 02:45:09.623375 done
1040 02:45:09.626663 Bytes transferred = 23432082 (1658b92 hex)
1041 02:45:09.627392 Sending with 10 millisecond of delay
1043 02:45:14.794483 => tftpboot 0x01070000 932188/tftp-deploy-cpxqodw7/dtb/meson-g12b-a311d-libretech-cc.dtb
1044 02:45:14.805242 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:03:57)
1045 02:45:14.806036 tftpboot 0x01070000 932188/tftp-deploy-cpxqodw7/dtb/meson-g12b-a311d-libretech-cc.dtb
1046 02:45:14.806476 Speed: 1000, full duplex
1047 02:45:14.806885 Using ethernet@ff3f0000 device
1048 02:45:14.810354 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1049 02:45:14.817722 Filename '932188/tftp-deploy-cpxqodw7/dtb/meson-g12b-a311d-libretech-cc.dtb'.
1050 02:45:14.828636 Load address: 0x1070000
1051 02:45:14.840494 Loading: *################################################## 53.4 KiB
1052 02:45:14.840949 3.1 MiB/s
1053 02:45:14.841359 done
1054 02:45:14.845174 Bytes transferred = 54703 (d5af hex)
1055 02:45:14.845884 Sending with 10 millisecond of delay
1057 02:45:28.140144 => setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/932188/extract-nfsrootfs-4umrveq0,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
1058 02:45:28.150979 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:03:44)
1059 02:45:28.151898 setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/932188/extract-nfsrootfs-4umrveq0,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
1060 02:45:28.152684 Sending with 10 millisecond of delay
1062 02:45:30.491398 => bootm 0x01080000 0x08000000 0x01070000
1063 02:45:30.502251 Setting prompt string to ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1064 02:45:30.502795 bootloader-commands: Wait for prompt ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:03:42)
1065 02:45:30.503793 bootm 0x01080000 0x08000000 0x01070000
1066 02:45:30.504273 ## Booting kernel from Legacy Image at 01080000 ...
1067 02:45:30.507274 Image Name:
1068 02:45:30.512787 Image Type: AArch64 Linux Kernel Image (uncompressed)
1069 02:45:30.513240 Data Size: 45715968 Bytes = 43.6 MiB
1070 02:45:30.518320 Load Address: 01080000
1071 02:45:30.518774 Entry Point: 01080000
1072 02:45:30.713475 Verifying Checksum ... OK
1073 02:45:30.714022 ## Loading init Ramdisk from Legacy Image at 08000000 ...
1074 02:45:30.718996 Image Name:
1075 02:45:30.724536 Image Type: AArch64 Linux RAMDisk Image (uncompressed)
1076 02:45:30.724990 Data Size: 23432018 Bytes = 22.3 MiB
1077 02:45:30.730011 Load Address: 00000000
1078 02:45:30.730459 Entry Point: 00000000
1079 02:45:30.832394 Verifying Checksum ... OK
1080 02:45:30.832920 ## Flattened Device Tree blob at 01070000
1081 02:45:30.837711 Booting using the fdt blob at 0x1070000
1082 02:45:30.838155 Working FDT set to 1070000
1083 02:45:30.842196 Loading Kernel Image
1084 02:45:30.993044 Loading Ramdisk to 7e9a7000, end 7ffffb52 ... OK
1085 02:45:31.001186 Loading Device Tree to 000000007e996000, end 000000007e9a65ae ... OK
1086 02:45:31.001636 Working FDT set to 7e996000
1087 02:45:31.002047
1088 02:45:31.002922 end: 2.4.3 bootloader-commands (duration 00:00:47) [common]
1089 02:45:31.003491 start: 2.4.4 auto-login-action (timeout 00:03:41) [common]
1090 02:45:31.003953 Setting prompt string to ['Linux version [0-9]']
1091 02:45:31.004458 Setting prompt string to ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1092 02:45:31.004921 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:05:00)
1093 02:45:31.005922 Starting kernel ...
1094 02:45:31.006363
1095 02:45:31.041393 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x410fd034]
1096 02:45:31.042272 start: 2.4.4.1 login-action (timeout 00:03:41) [common]
1097 02:45:31.042783 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
1098 02:45:31.043232 Setting prompt string to []
1099 02:45:31.043711 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
1100 02:45:31.044191 Using line separator: #'\n'#
1101 02:45:31.044595 No login prompt set.
1102 02:45:31.045022 Parsing kernel messages
1103 02:45:31.045418 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
1104 02:45:31.046190 [login-action] Waiting for messages, (timeout 00:03:41)
1105 02:45:31.046631 Waiting using forced prompt support (timeout 00:01:51)
1106 02:45:31.057989 [ 0.000000] Linux version 6.12.0-rc5 (KernelCI@build-j361247-arm64-gcc-12-defconfig-wxqvs) (aarch64-linux-gnu-gcc (Debian 12.2.0-14) 12.2.0, GNU ld (GNU Binutils for Debian) 2.40) #1 SMP PREEMPT Mon Nov 4 01:54:17 UTC 2024
1107 02:45:31.063427 [ 0.000000] KASLR disabled due to lack of seed
1108 02:45:31.069015 [ 0.000000] Machine model: Libre Computer AML-A311D-CC Alta
1109 02:45:31.074517 [ 0.000000] efi: UEFI not found.
1110 02:45:31.080091 [ 0.000000] [Firmware Bug]: Kernel image misaligned at boot, please fix your bootloader!
1111 02:45:31.085704 [ 0.000000] Reserved memory: created CMA memory pool at 0x00000000e4c00000, size 256 MiB
1112 02:45:31.096744 [ 0.000000] OF: reserved mem: initialized node linux,cma, compatible id shared-dma-pool
1113 02:45:31.107619 [ 0.000000] OF: reserved mem: 0x00000000e4c00000..0x00000000f4bfffff (262144 KiB) map reusable linux,cma
1114 02:45:31.113251 [ 0.000000] OF: reserved mem: 0x0000000005000000..0x00000000052fffff (3072 KiB) nomap non-reusable secmon@5000000
1115 02:45:31.124266 [ 0.000000] OF: reserved mem: 0x0000000005300000..0x00000000072fffff (32768 KiB) nomap non-reusable secmon@5300000
1116 02:45:31.135109 [ 0.000000] earlycon: meson0 at MMIO 0x00000000ff803000 (options '115200n8')
1117 02:45:31.140668 [ 0.000000] printk: legacy bootconsole [meson0] enabled
1118 02:45:31.146207 [ 0.000000] NUMA: Faking a node at [mem 0x0000000000000000-0x00000000f4e5afff]
1119 02:45:31.151706 [ 0.000000] NODE_DATA(0) allocated [mem 0xe4666a80-0xe46690bf]
1120 02:45:31.152157 [ 0.000000] Zone ranges:
1121 02:45:31.157221 [ 0.000000] DMA [mem 0x0000000000000000-0x00000000f4e5afff]
1122 02:45:31.162740 [ 0.000000] DMA32 empty
1123 02:45:31.163163 [ 0.000000] Normal empty
1124 02:45:31.168302 [ 0.000000] Movable zone start for each node
1125 02:45:31.173804 [ 0.000000] Early memory node ranges
1126 02:45:31.179316 [ 0.000000] node 0: [mem 0x0000000000000000-0x0000000004ffffff]
1127 02:45:31.184832 [ 0.000000] node 0: [mem 0x0000000005000000-0x00000000072fffff]
1128 02:45:31.190354 [ 0.000000] node 0: [mem 0x0000000007300000-0x00000000f4e5afff]
1129 02:45:31.195871 [ 0.000000] Initmem setup node 0 [mem 0x0000000000000000-0x00000000f4e5afff]
1130 02:45:31.223234 [ 0.000000] On node 0, zone DMA: 12709 pages in unavailable ranges
1131 02:45:31.228778 [ 0.000000] psci: probing for conduit method from DT.
1132 02:45:31.229206 [ 0.000000] psci: PSCIv1.0 detected in firmware.
1133 02:45:31.234292 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
1134 02:45:31.239809 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
1135 02:45:31.245310 [ 0.000000] psci: SMC Calling Convention v1.1
1136 02:45:31.250848 [ 0.000000] percpu: Embedded 25 pages/cpu s61656 r8192 d32552 u102400
1137 02:45:31.256352 [ 0.000000] Detected VIPT I-cache on CPU0
1138 02:45:31.261888 [ 0.000000] CPU features: detected: ARM erratum 845719
1139 02:45:31.267441 [ 0.000000] alternatives: applying boot alternatives
1140 02:45:31.283972 [ 0.000000] Kernel command line: console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/932188/extract-nfsrootfs-4umrveq0,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp
1141 02:45:31.295006 <6>[ 0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
1142 02:45:31.300605 <6>[ 0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes, linear)
1143 02:45:31.306048 <6>[ 0.000000] Fallback order for Node 0: 0
1144 02:45:31.311585 <6>[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 1003099
1145 02:45:31.317095 <6>[ 0.000000] Policy zone: DMA
1146 02:45:31.322614 <6>[ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
1147 02:45:31.328163 <6>[ 0.000000] software IO TLB: SWIOTLB bounce buffer size adjusted to 3MB
1148 02:45:31.333652 <6>[ 0.000000] software IO TLB: area num 8.
1149 02:45:31.342715 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000dfc00000-0x00000000e0000000] (4MB)
1150 02:45:31.389286 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=6, Nodes=1
1151 02:45:31.394805 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
1152 02:45:31.398359 <6>[ 0.000000] rcu: RCU event tracing is enabled.
1153 02:45:31.403863 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=512 to nr_cpu_ids=6.
1154 02:45:31.409380 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
1155 02:45:31.414899 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
1156 02:45:31.425937 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
1157 02:45:31.431467 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=6
1158 02:45:31.436973 <6>[ 0.000000] RCU Tasks: Setting shift to 3 and lim to 1 rcu_task_cb_adjust=1 rcu_task_cpu_ids=6.
1159 02:45:31.448032 <6>[ 0.000000] RCU Tasks Trace: Setting shift to 3 and lim to 1 rcu_task_cb_adjust=1 rcu_task_cpu_ids=6.
1160 02:45:31.453596 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
1161 02:45:31.459018 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
1162 02:45:31.464548 <6>[ 0.000000] GIC: Using split EOI/Deactivate mode
1163 02:45:31.470969 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
1164 02:45:31.483659 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 24.00MHz (phys).
1165 02:45:31.494718 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x588fe9dc0, max_idle_ns: 440795202592 ns
1166 02:45:31.500235 <6>[ 0.000001] sched_clock: 56 bits at 24MHz, resolution 41ns, wraps every 4398046511097ns
1167 02:45:31.505744 <6>[ 0.008797] Console: colour dummy device 80x25
1168 02:45:31.516760 <6>[ 0.012941] Calibrating delay loop (skipped), value calculated using timer frequency.. 48.00 BogoMIPS (lpj=96000)
1169 02:45:31.522302 <6>[ 0.023294] pid_max: default: 32768 minimum: 301
1170 02:45:31.527834 <6>[ 0.028189] LSM: initializing lsm=capability
1171 02:45:31.533337 <6>[ 0.032730] Mount-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
1172 02:45:31.538835 <6>[ 0.040211] Mountpoint-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
1173 02:45:31.544351 <6>[ 0.050769] rcu: Hierarchical SRCU implementation.
1174 02:45:31.549886 <6>[ 0.053268] rcu: Max phase no-delay instances is 1000.
1175 02:45:31.560924 <6>[ 0.058870] Timer migration: 1 hierarchy levels; 8 children per group; 1 crossnode level
1176 02:45:31.569401 <6>[ 0.071580] EFI services will not be available.
1177 02:45:31.569867 <6>[ 0.075239] smp: Bringing up secondary CPUs ...
1178 02:45:31.585685 <6>[ 0.077135] Detected VIPT I-cache on CPU1
1179 02:45:31.591176 <6>[ 0.077258] CPU1: Booted secondary processor 0x0000000001 [0x410fd034]
1180 02:45:31.596697 <6>[ 0.078603] CPU features: detected: Spectre-v2
1181 02:45:31.602217 <6>[ 0.078617] CPU features: detected: Spectre-v4
1182 02:45:31.607748 <6>[ 0.078623] CPU features: detected: Spectre-BHB
1183 02:45:31.613263 <6>[ 0.078628] CPU features: detected: ARM erratum 858921
1184 02:45:31.618782 <6>[ 0.078635] Detected VIPT I-cache on CPU2
1185 02:45:31.624293 <6>[ 0.078708] arch_timer: Enabling local workaround for ARM erratum 858921
1186 02:45:31.629821 <6>[ 0.078726] arch_timer: CPU2: Trapping CNTVCT access
1187 02:45:31.635315 <6>[ 0.078735] CPU2: Booted secondary processor 0x0000000100 [0x410fd092]
1188 02:45:31.640869 <6>[ 0.079680] Detected VIPT I-cache on CPU3
1189 02:45:31.646379 <6>[ 0.079726] arch_timer: Enabling local workaround for ARM erratum 858921
1190 02:45:31.651894 <6>[ 0.079736] arch_timer: CPU3: Trapping CNTVCT access
1191 02:45:31.657420 <6>[ 0.079743] CPU3: Booted secondary processor 0x0000000101 [0x410fd092]
1192 02:45:31.662924 <6>[ 0.083598] Detected VIPT I-cache on CPU4
1193 02:45:31.668474 <6>[ 0.083644] arch_timer: Enabling local workaround for ARM erratum 858921
1194 02:45:31.673972 <6>[ 0.083654] arch_timer: CPU4: Trapping CNTVCT access
1195 02:45:31.685016 <6>[ 0.083661] CPU4: Booted secondary processor 0x0000000102 [0x410fd092]
1196 02:45:31.685450 <6>[ 0.095651] Detected VIPT I-cache on CPU5
1197 02:45:31.696036 <6>[ 0.095699] arch_timer: Enabling local workaround for ARM erratum 858921
1198 02:45:31.696472 <6>[ 0.095708] arch_timer: CPU5: Trapping CNTVCT access
1199 02:45:31.707082 <6>[ 0.095716] CPU5: Booted secondary processor 0x0000000103 [0x410fd092]
1200 02:45:31.707515 <6>[ 0.095837] smp: Brought up 1 node, 6 CPUs
1201 02:45:31.712642 <6>[ 0.217068] SMP: Total of 6 processors activated.
1202 02:45:31.718138 <6>[ 0.221973] CPU: All CPU(s) started at EL2
1203 02:45:31.723718 <6>[ 0.226316] CPU features: detected: 32-bit EL0 Support
1204 02:45:31.729187 <6>[ 0.231632] CPU features: detected: 32-bit EL1 Support
1205 02:45:31.734695 <6>[ 0.236979] CPU features: detected: CRC32 instructions
1206 02:45:31.740214 <6>[ 0.242382] alternatives: applying system-wide alternatives
1207 02:45:31.758275 <6>[ 0.249652] Memory: 3557436K/4012396K available (17280K kernel code, 4900K rwdata, 11876K rodata, 10432K init, 742K bss, 187796K reserved, 262144K cma-reserved)
1208 02:45:31.758714 <6>[ 0.263925] devtmpfs: initialized
1209 02:45:31.769335 <6>[ 0.273201] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
1210 02:45:31.774839 <6>[ 0.277560] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
1211 02:45:31.780337 <6>[ 0.288357] 21392 pages in range for non-PLT usage
1212 02:45:31.785871 <6>[ 0.288367] 512912 pages in range for PLT usage
1213 02:45:31.791395 <6>[ 0.289919] pinctrl core: initialized pinctrl subsystem
1214 02:45:31.796918 <6>[ 0.301970] DMI not present or invalid.
1215 02:45:31.802435 <6>[ 0.306301] NET: Registered PF_NETLINK/PF_ROUTE protocol family
1216 02:45:31.807953 <6>[ 0.311041] DMA: preallocated 512 KiB GFP_KERNEL pool for atomic allocations
1217 02:45:31.818995 <6>[ 0.317814] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
1218 02:45:31.824533 <6>[ 0.325913] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
1219 02:45:31.830012 <6>[ 0.333392] audit: initializing netlink subsys (disabled)
1220 02:45:31.841082 <5>[ 0.339129] audit: type=2000 audit(0.260:1): state=initialized audit_enabled=0 res=1
1221 02:45:31.846679 <6>[ 0.340552] thermal_sys: Registered thermal governor 'step_wise'
1222 02:45:31.852143 <6>[ 0.346898] thermal_sys: Registered thermal governor 'power_allocator'
1223 02:45:31.857646 <6>[ 0.353159] cpuidle: using governor menu
1224 02:45:31.863159 <6>[ 0.364194] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
1225 02:45:31.868708 <6>[ 0.371074] ASID allocator initialised with 65536 entries
1226 02:45:31.876938 <6>[ 0.378632] Serial: AMBA PL011 UART driver
1227 02:45:31.884800 <6>[ 0.389196] platform ff600000.hdmi-tx: Fixed dependency cycle(s) with /soc/vpu@ff900000
1228 02:45:31.899960 <6>[ 0.404620] platform ff600000.hdmi-tx: Fixed dependency cycle(s) with /soc/vpu@ff900000
1229 02:45:31.910995 <6>[ 0.407288] platform ff900000.vpu: Fixed dependency cycle(s) with /soc/bus@ff600000/hdmi-tx@0
1230 02:45:31.916541 <6>[ 0.420415] platform ff900000.vpu: Fixed dependency cycle(s) with /cvbs-connector
1231 02:45:31.922021 <6>[ 0.423667] platform cvbs-connector: Fixed dependency cycle(s) with /soc/vpu@ff900000
1232 02:45:31.933052 <6>[ 0.432091] platform ff600000.hdmi-tx: Fixed dependency cycle(s) with /hdmi-connector
1233 02:45:31.938675 <6>[ 0.439716] platform hdmi-connector: Fixed dependency cycle(s) with /soc/bus@ff600000/hdmi-tx@0
1234 02:45:31.949670 <6>[ 0.453302] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
1235 02:45:31.955189 <6>[ 0.455535] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
1236 02:45:31.960676 <6>[ 0.462016] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
1237 02:45:31.966234 <6>[ 0.468994] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
1238 02:45:31.977290 <6>[ 0.475463] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
1239 02:45:31.982750 <6>[ 0.482448] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
1240 02:45:31.988268 <6>[ 0.488918] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
1241 02:45:31.993786 <6>[ 0.495902] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
1242 02:45:31.999376 <6>[ 0.503919] ACPI: Interpreter disabled.
1243 02:45:32.004891 <6>[ 0.509308] iommu: Default domain type: Translated
1244 02:45:32.010414 <6>[ 0.511435] iommu: DMA domain TLB invalidation policy: strict mode
1245 02:45:32.015920 <5>[ 0.518142] SCSI subsystem initialized
1246 02:45:32.021384 <6>[ 0.522066] usbcore: registered new interface driver usbfs
1247 02:45:32.026909 <6>[ 0.527494] usbcore: registered new interface driver hub
1248 02:45:32.032396 <6>[ 0.533009] usbcore: registered new device driver usb
1249 02:45:32.037962 <6>[ 0.539270] pps_core: LinuxPPS API ver. 1 registered
1250 02:45:32.043769 <6>[ 0.543430] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
1251 02:45:32.049025 <6>[ 0.552751] PTP clock support registered
1252 02:45:32.054487 <6>[ 0.556990] EDAC MC: Ver: 3.0.0
1253 02:45:32.060028 <6>[ 0.560641] scmi_core: SCMI protocol bus registered
1254 02:45:32.060472 <6>[ 0.566297] FPGA manager framework
1255 02:45:32.065526 <6>[ 0.569011] Advanced Linux Sound Architecture Driver Initialized.
1256 02:45:32.071083 <6>[ 0.575979] vgaarb: loaded
1257 02:45:32.076588 <6>[ 0.578512] clocksource: Switched to clocksource arch_sys_counter
1258 02:45:32.082097 <5>[ 0.584650] VFS: Disk quotas dquot_6.6.0
1259 02:45:32.087715 <6>[ 0.588644] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
1260 02:45:32.093173 <6>[ 0.595857] pnp: PnP ACPI: disabled
1261 02:45:32.098697 <6>[ 0.604350] NET: Registered PF_INET protocol family
1262 02:45:32.104222 <6>[ 0.604677] IP idents hash table entries: 65536 (order: 7, 524288 bytes, linear)
1263 02:45:32.115240 <6>[ 0.614828] tcp_listen_portaddr_hash hash table entries: 2048 (order: 3, 32768 bytes, linear)
1264 02:45:32.120760 <6>[ 0.620848] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
1265 02:45:32.131807 <6>[ 0.628741] TCP established hash table entries: 32768 (order: 6, 262144 bytes, linear)
1266 02:45:32.137309 <6>[ 0.636981] TCP bind hash table entries: 32768 (order: 8, 1048576 bytes, linear)
1267 02:45:32.142827 <6>[ 0.644776] TCP: Hash tables configured (established 32768 bind 32768)
1268 02:45:32.148365 <6>[ 0.651253] UDP hash table entries: 2048 (order: 4, 65536 bytes, linear)
1269 02:45:32.159436 <6>[ 0.658098] UDP-Lite hash table entries: 2048 (order: 4, 65536 bytes, linear)
1270 02:45:32.164886 <6>[ 0.665519] NET: Registered PF_UNIX/PF_LOCAL protocol family
1271 02:45:32.170476 <6>[ 0.671606] RPC: Registered named UNIX socket transport module.
1272 02:45:32.175938 <6>[ 0.677386] RPC: Registered udp transport module.
1273 02:45:32.181480 <6>[ 0.682292] RPC: Registered tcp transport module.
1274 02:45:32.187001 <6>[ 0.687207] RPC: Registered tcp-with-tls transport module.
1275 02:45:32.192522 <6>[ 0.692900] RPC: Registered tcp NFSv4.1 backchannel transport module.
1276 02:45:32.198022 <6>[ 0.699548] PCI: CLS 0 bytes, default 64
1277 02:45:32.198458 <6>[ 0.703874] Unpacking initramfs...
1278 02:45:32.203555 <6>[ 0.710081] kvm [1]: nv: 554 coarse grained trap handlers
1279 02:45:32.209078 <6>[ 0.713198] kvm [1]: IPA Size Limit: 40 bits
1280 02:45:32.214593 <6>[ 0.718849] kvm [1]: vgic interrupt IRQ9
1281 02:45:32.220174 <6>[ 0.721559] kvm [1]: Hyp nVHE mode initialized successfully
1282 02:45:32.225763 <5>[ 0.728631] Initialise system trusted keyrings
1283 02:45:32.231160 <6>[ 0.732203] workingset: timestamp_bits=42 max_order=20 bucket_order=0
1284 02:45:32.236692 <6>[ 0.738854] squashfs: version 4.0 (2009/01/31) Phillip Lougher
1285 02:45:32.242203 <5>[ 0.744957] NFS: Registering the id_resolver key type
1286 02:45:32.247727 <5>[ 0.749942] Key type id_resolver registered
1287 02:45:32.253222 <5>[ 0.754312] Key type id_legacy registered
1288 02:45:32.258751 <6>[ 0.758549] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
1289 02:45:32.264278 <6>[ 0.765437] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
1290 02:45:32.271703 <6>[ 0.773286] 9p: Installing v9fs 9p2000 file system support
1291 02:45:32.309086 <5>[ 0.819260] Key type asymmetric registered
1292 02:45:32.314603 <5>[ 0.819297] Asymmetric key parser 'x509' registered
1293 02:45:32.323768 <6>[ 0.823167] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 245)
1294 02:45:32.329171 <6>[ 0.830688] io scheduler mq-deadline registered
1295 02:45:32.334730 <6>[ 0.835422] io scheduler kyber registered
1296 02:45:32.335165 <6>[ 0.839696] io scheduler bfq registered
1297 02:45:32.343122 <6>[ 0.848270] irq_meson_gpio: 100 to 8 gpio interrupt mux initialized
1298 02:45:32.364122 <6>[ 0.870546] ledtrig-cpu: registered to indicate activity on CPUs
1299 02:45:32.396799 <6>[ 0.901950] soc soc0: Amlogic Meson G12B (A311D) Revision 29:b (10:2) Detected
1300 02:45:32.416391 <6>[ 0.915320] Serial: 8250/16550 driver, 4 port<6>[ 0.919870] ff803000.serial: ttyAML0 at MMIO 0xff803000 (irq = 14, base_baud = 1500000) is a meson_uart
1301 02:45:32.419771 <6>[ 0.929496] printk: legacy console [ttyAML0] enabled
1302 02:45:32.425240 <6>[ 0.929496] printk: legacy console [ttyAML0] enabled
1303 02:45:32.430793 <6>[ 0.934301] printk: legacy bootconsole [meson0] disabled
1304 02:45:32.436647 <6>[ 0.934301] printk: legacy bootconsole [meson0] disabled
1305 02:45:32.442203 <6>[ 0.951325] msm_serial: driver initialized
1306 02:45:32.447750 <6>[ 0.951816] SuperH (H)SCI(F) driver initialized
1307 02:45:32.453296 <6>[ 0.955075] STM32 USART driver initialized
1308 02:45:32.453722 <5>[ 0.961221] random: crng init done
1309 02:45:32.458841 <6>[ 0.966778] loop: module loaded
1310 02:45:32.465942 <6>[ 0.968067] megasas: 07.727.03.00-rc1
1311 02:45:32.471548 <6>[ 0.977245] tun: Universal TUN/TAP device driver, 1.6
1312 02:45:32.472081 <6>[ 0.978475] thunder_xcv, ver 1.0
1313 02:45:32.477066 <6>[ 0.980428] thunder_bgx, ver 1.0
1314 02:45:32.477535 <6>[ 0.983883] nicpf, ver 1.0
1315 02:45:32.488165 <6>[ 0.988439] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
1316 02:45:32.493775 <6>[ 0.994265] hns3: Copyright (c) 2017 Huawei Corporation.
1317 02:45:32.494206 <6>[ 0.999848] hclge is initializing
1318 02:45:32.499231 <6>[ 1.003390] e1000: Intel(R) PRO/1000 Network Driver
1319 02:45:32.504805 <6>[ 1.008471] e1000: Copyright (c) 1999-2006 Intel Corporation.
1320 02:45:32.510312 <6>[ 1.014496] e1000e: Intel(R) PRO/1000 Network Driver
1321 02:45:32.515844 <6>[ 1.019650] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
1322 02:45:32.521404 <6>[ 1.025838] igb: Intel(R) Gigabit Ethernet Network Driver
1323 02:45:32.532516 <6>[ 1.031442] igb: Copyright (c) 2007-2014 Intel Corporation.
1324 02:45:32.538068 <6>[ 1.037274] igbvf: Intel(R) Gigabit Virtual Function Network Driver
1325 02:45:32.543605 <6>[ 1.043745] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
1326 02:45:32.549140 <6>[ 1.050502] sky2: driver version 1.30
1327 02:45:32.549569 <6>[ 1.055616] VFIO - User Level meta-driver version: 0.3
1328 02:45:32.562880 <6>[ 1.063098] usbcore: registered new interface driver usb-storage
1329 02:45:32.563311 <6>[ 1.069148] i2c_dev: i2c /dev entries driver
1330 02:45:32.575657 <6>[ 1.080277] sdhci: Secure Digital Host Controller Interface driver
1331 02:45:32.576149 <6>[ 1.081083] sdhci: Copyright(c) Pierre Ossman
1332 02:45:32.586772 <6>[ 1.086872] Synopsys Designware Multimedia Card Interface Driver
1333 02:45:32.592306 <6>[ 1.093336] sdhci-pltfm: SDHCI platform and OF driver helper
1334 02:45:32.592735 <6>[ 1.100975] meson-sm: secure-monitor enabled
1335 02:45:32.605178 <6>[ 1.103501] usbcore: registered new interface driver usbhid
1336 02:45:32.605611 <6>[ 1.108135] usbhid: USB HID core driver
1337 02:45:32.612834 <6>[ 1.122993] NET: Registered PF_PACKET protocol family
1338 02:45:32.618368 <6>[ 1.123081] 9pnet: Installing 9P2000 support
1339 02:45:32.625488 <5>[ 1.127226] Key type dns_resolver registered
1340 02:45:32.631030 <6>[ 1.138878] registered taskstats version 1
1341 02:45:32.636584 <5>[ 1.139028] Loading compiled-in X.509 certificates
1342 02:45:32.640191 <6>[ 1.147964] Demotion targets for Node 0: null
1343 02:45:32.667132 <6>[ 1.177284] dwc3-meson-g12a ffe09000.usb: USB2 ports: 2
1344 02:45:32.672700 <6>[ 1.177323] dwc3-meson-g12a ffe09000.usb: USB3 ports: 1
1345 02:45:32.683771 <4>[ 1.186453] dwc2 ff400000.usb: supply vusb_d not found, using dummy regulator
1346 02:45:32.689309 <4>[ 1.190082] dwc2 ff400000.usb: supply vusb_a not found, using dummy regulator
1347 02:45:32.694864 <6>[ 1.197574] dwc2 ff400000.usb: EPs: 7, dedicated fifos, 712 entries in SPRAM
1348 02:45:32.700408 <6>[ 1.206922] xhci-hcd xhci-hcd.0.auto: xHCI Host Controller
1349 02:45:32.711464 <6>[ 1.210339] xhci-hcd xhci-hcd.0.auto: new USB bus registered, assigned bus number 1
1350 02:45:32.722594 <6>[ 1.218360] xhci-hcd xhci-hcd.0.auto: hcc params 0x0228fe6c hci version 0x110 quirks 0x0000808000000010
1351 02:45:32.728177 <6>[ 1.227887] xhci-hcd xhci-hcd.0.auto: irq 16, io mem 0xff500000
1352 02:45:32.733685 <6>[ 1.234105] xhci-hcd xhci-hcd.0.auto: xHCI Host Controller
1353 02:45:32.739231 <6>[ 1.239726] xhci-hcd xhci-hcd.0.auto: new USB bus registered, assigned bus number 2
1354 02:45:32.744765 <6>[ 1.247613] xhci-hcd xhci-hcd.0.auto: Host supports USB 3.0 SuperSpeed
1355 02:45:32.750325 <6>[ 1.254902] hub 1-0:1.0: USB hub found
1356 02:45:32.755870 <6>[ 1.258361] hub 1-0:1.0: 2 ports detected
1357 02:45:32.761416 <6>[ 1.264429] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
1358 02:45:32.766966 <6>[ 1.271341] hub 2-0:1.0: USB hub found
1359 02:45:32.772054 <6>[ 1.274926] hub 2-0:1.0: 1 port detected
1360 02:45:32.795950 <6>[ 1.303544] meson-gx-mmc ffe05000.mmc: Got CD GPIO
1361 02:45:32.807080 <6>[ 1.313906] meson-gx-mmc ffe07000.mmc: allocated mmc-pwrseq
1362 02:45:32.842602 <6>[ 1.349071] Trying to probe devices needed for running init ...
1363 02:45:33.008697 <6>[ 1.514550] usb 1-1: new high-speed USB device number 2 using xhci-hcd
1364 02:45:33.149258 <6>[ 1.653891] mmc0: new ultra high speed SDR104 SDXC card at address e624
1365 02:45:33.155462 <6>[ 1.656121] mmcblk0: mmc0:e624 SD64G 59.5 GiB
1366 02:45:33.155927 <6>[ 1.662128] mmcblk0: p1
1367 02:45:33.167283 <6>[ 1.675635] Freeing initrd memory: 22880K
1368 02:45:33.192565 <6>[ 1.702700] hub 1-1:1.0: USB hub found
1369 02:45:33.198300 <6>[ 1.703022] hub 1-1:1.0: 4 ports detected
1370 02:45:33.268814 <6>[ 1.774651] usb 2-1: new SuperSpeed USB device number 2 using xhci-hcd
1371 02:45:33.305199 <6>[ 1.815347] hub 2-1:1.0: USB hub found
1372 02:45:33.311006 <6>[ 1.816169] hub 2-1:1.0: 4 ports detected
1373 02:45:45.140800 <6>[ 13.650576] clk: Disabling unused clocks
1374 02:45:45.146073 <6>[ 13.650745] PM: genpd: Disabling unused power domains
1375 02:45:45.154510 <6>[ 13.654437] ALSA device list:
1376 02:45:45.154957 <6>[ 13.657636] No soundcards found.
1377 02:45:45.160783 <6>[ 13.669765] Freeing unused kernel memory: 10432K
1378 02:45:45.166001 <6>[ 13.669863] Run /init as init process
1379 02:45:45.171826 Loading, please wait...
1380 02:45:45.208129 Starting systemd-udevd version 252.22-1~deb12u1
1381 02:45:45.659137 <6>[ 14.167030] mc: Linux media interface: v0.10
1382 02:45:45.673980 <6>[ 14.176106] videodev: Linux video capture interface: v2.00
1383 02:45:45.679387 <4>[ 14.184168] meson-pwm ff802000.pwm: using obsolete compatible, please consider updating dt
1384 02:45:45.684950 <6>[ 14.190271] panfrost ffe40000.gpu: clock rate = 24000000
1385 02:45:45.694701 <3>[ 14.192741] panfrost ffe40000.gpu: error -ENODEV: _opp_set_regulators: no regulator (mali) found
1386 02:45:45.706836 <6>[ 14.211462] panfrost ffe40000.gpu: mali-g52 id 0x7212 major 0x0 minor 0x0 status 0x0
1387 02:45:45.712279 <6>[ 14.214008] panfrost ffe40000.gpu: features: 00000000,00000cf7, issues: 00000000,00000400
1388 02:45:45.728936 <6>[ 14.222267] panfrost ffe40000.gpu: Features: L2:0x07110206 Shader:0x00000000 Tiler:0x00000809 Mem:0x1 MMU:0x00002830 AS:0xff JS:0x7
1389 02:45:45.734473 <6>[ 14.234358] panfrost ffe40000.gpu: shader_present=0x3 l2_present=0x1
1390 02:45:45.740064 <6>[ 14.241315] meson-vrtc ff8000a8.rtc: registered as rtc0
1391 02:45:45.745650 <6>[ 14.246408] meson-vrtc ff8000a8.rtc: setting system clock to 1970-01-01T00:00:14 UTC (14)
1392 02:45:45.756752 <4>[ 14.249286] meson_vdec: module is from the staging directory, the quality is unknown, you have been warned.
1393 02:45:45.763433 <6>[ 14.249873] meson-drm ff900000.vpu: Queued 2 outputs on vpu
1394 02:45:45.780760 <6>[ 14.285447] meson8b-dwmac ff3f0000.ethernet: IRQ eth_wake_irq not found
1395 02:45:45.786390 <6>[ 14.286743] meson8b-dwmac ff3f0000.ethernet: IRQ eth_lpi not found
1396 02:45:45.791920 <6>[ 14.293126] meson8b-dwmac ff3f0000.ethernet: IRQ sfty not found
1397 02:45:45.797440 <6>[ 14.294543] [drm] Initialized panfrost 1.2.0 for ffe40000.gpu on minor 0
1398 02:45:45.802984 <6>[ 14.299393] meson8b-dwmac ff3f0000.ethernet: PTP uses main clock
1399 02:45:45.814024 <6>[ 14.306280] meson-dw-hdmi ff600000.hdmi-tx: Detected HDMI TX controller v2.01a with HDCP (meson_dw_hdmi_phy)
1400 02:45:45.819582 <6>[ 14.307622] Registered IR keymap rc-empty
1401 02:45:45.825125 <6>[ 14.307718] rc rc0: meson-ir as /devices/platform/soc/ff800000.bus/ff808000.ir/rc/rc0
1402 02:45:45.836205 <6>[ 14.307872] input: meson-ir as /devices/platform/soc/ff800000.bus/ff808000.ir/rc/rc0/input0
1403 02:45:45.841771 <6>[ 14.308153] rc rc0: sw decoder init
1404 02:45:45.847300 <6>[ 14.308191] meson-ir ff808000.ir: receiver initialized
1405 02:45:45.852867 <6>[ 14.313116] meson8b-dwmac ff3f0000.ethernet: User ID: 0x11, Synopsys ID: 0x37
1406 02:45:45.858422 <3>[ 14.317065] debugfs: Directory 'ff800280.cec' with parent 'regmap' already present!
1407 02:45:45.869516 <6>[ 14.352644] cpufreq: cpufreq_online: CPU2: Running at unlisted initial frequency: 999999 KHz, changing to: 1000000 KHz
1408 02:45:45.880589 <6>[ 14.356063] meson-dw-hdmi ff600000.hdmi-tx: registered DesignWare HDMI I2C bus driver
1409 02:45:45.886135 <6>[ 14.359858] meson8b-dwmac ff3f0000.ethernet: DWMAC1000
1410 02:45:45.891733 <6>[ 14.375655] meson-drm ff900000.vpu: bound ff600000.hdmi-tx (ops meson_dw_hdmi_ops [meson_dw_hdmi])
1411 02:45:45.902795 <6>[ 14.378666] meson8b-dwmac ff3f0000.ethernet: DMA HW capability register supported
1412 02:45:45.908331 <6>[ 14.378674] meson8b-dwmac ff3f0000.ethernet: RX Checksum Offload Engine supported
1413 02:45:45.913888 <6>[ 14.378679] meson8b-dwmac ff3f0000.ethernet: COE Type 2
1414 02:45:45.919426 <6>[ 14.378687] meson8b-dwmac ff3f0000.ethernet: TX Checksum insertion supported
1415 02:45:45.930637 <6>[ 14.378691] meson8b-dwmac ff3f0000.ethernet: Wake-Up On Lan supported
1416 02:45:45.936256 <3>[ 14.386883] meson-drm ff900000.vpu: DSI transceiver device is disabled
1417 02:45:45.941768 <6>[ 14.410875] meson8b-dwmac ff3f0000.ethernet: Normal descriptors
1418 02:45:45.947319 <6>[ 14.423837] [drm] Initialized meson 1.0.0 for ff900000.vpu on minor 1
1419 02:45:45.952881 <6>[ 14.429562] meson8b-dwmac ff3f0000.ethernet: Ring mode enabled
1420 02:45:45.963929 <6>[ 14.461863] meson8b-dwmac ff3f0000.ethernet: Enable RX Mitigation via HW Watchdog Timer
1421 02:45:45.969465 <6>[ 14.462094] usbcore: registered new device driver onboard-usb-dev
1422 02:45:46.145699 <6>[ 14.480993] meson8b-dwmac ff3f0000.ethernet end0: renamed from eth0
1423 02:45:46.151275 <6>[ 14.631294] Console: switching to colour frame buffer device 128x48
1424 02:45:46.158019 <6>[ 14.657635] meson-drm ff900000.vpu: [drm] fb0: mesondrmfb frame buffer device
1425 02:45:46.376673 <6>[ 14.886719] hub 1-1:1.0: USB hub found
1426 02:45:46.382141 <6>[ 14.887047] hub 1-1:1.0: 4 ports detected
1427 02:45:46.388577 <6>[ 14.892364] onboard-usb-dev 1-1: USB disconnect, device number 2
1428 02:45:46.632467 <4>[ 15.142539] rc rc0: two consecutive events of type space
1429 02:45:46.756649 <6>[ 15.262538] usb 1-1: new high-speed USB device number 3 using xhci-hcd
1430 02:45:46.952714 <6>[ 15.462810] hub 1-1:1.0: USB hub found
1431 02:45:46.958431 <6>[ 15.463124] hub 1-1:1.0: 4 ports detected
1432 02:45:46.964998 Begin: Loading essential drivers ... done.
1433 02:45:46.970539 Begin: Running /scripts/init-premount ... done.
1434 02:45:46.976119 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
1435 02:45:46.987717 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
1436 02:45:46.988309 Device /sys/class/net/end0 found
1437 02:45:46.988782 done.
1438 02:45:46.997637 Begin: Waiting up to 180 secs for any network device to become available ... done.
1439 02:45:47.059561 IP-Config: end0 hardware address de:ca:d3:e3:c6:63 mtu 1500 DHCP
<6>[ 15.561350] meson8b-dwmac ff3f0000.ethernet end0: Register MEM_TYPE_PAGE_POOL RxQ-0
1440 02:45:47.060148
1441 02:45:47.146179 <6>[ 15.650699] meson8b-dwmac ff3f0000.ethernet end0: PHY [mdio_mux-0.0:00] driver [RTL8211F Gigabit Ethernet] (irq=32)
1442 02:45:47.157224 <6>[ 15.654709] usb 2-1: reset SuperSpeed USB device number 2 using xhci-hcd
1443 02:45:47.162856 <6>[ 15.667233] meson8b-dwmac ff3f0000.ethernet end0: No Safety Features support found
1444 02:45:47.168342 <6>[ 15.670520] meson8b-dwmac ff3f0000.ethernet end0: PTP not supported by HW
1445 02:45:47.178581 <6>[ 15.678911] meson8b-dwmac ff3f0000.ethernet end0: configuring for phy/rgmii link mode
1446 02:45:47.420983 <6>[ 15.926681] usb 2-1: reset SuperSpeed USB device number 2 using xhci-hcd
1447 02:45:48.238173 IP-Config: no response after 2 secs - giving up
1448 02:45:48.279604 IP-Config: end0 hardware address de:ca:d3:e3:c6:63 mtu 1500 DHCP
1449 02:45:50.154501 <6>[ 18.658448] meson8b-dwmac ff3f0000.ethernet end0: Link is Up - 1Gbps/Full - flow control off
1450 02:45:50.501812 IP-Config: end0 guessed broadcast address 192.168.6.255
1451 02:45:50.507300 IP-Config: end0 complete (dhcp from 192.168.6.1):
1452 02:45:50.512821 address: 192.168.6.27 broadcast: 192.168.6.255 netmask: 255.255.255.0
1453 02:45:50.521815 gateway: 192.168.6.1 dns0 : 10.255.253.1 dns1 : 0.0.0.0
1454 02:45:50.527360 rootserver: 192.168.6.1 rootpath:
1455 02:45:50.527877 filename :
1456 02:45:50.642652 done.
1457 02:45:50.652775 Begin: Running /scripts/nfs-bottom ... done.
1458 02:45:50.668895 Begin: Running /scripts/init-bottom ... done.
1459 02:45:50.993788 <30>[ 19.499273] systemd[1]: System time before build time, advancing clock.
1460 02:45:51.043090 <6>[ 19.553022] NET: Registered PF_INET6 protocol family
1461 02:45:51.048574 <6>[ 19.555242] Segment Routing with IPv6
1462 02:45:51.053876 <6>[ 19.556531] In-situ OAM (IOAM) with IPv6
1463 02:45:51.127892 <30>[ 19.610223] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
1464 02:45:51.133450 <30>[ 19.637609] systemd[1]: Detected architecture arm64.
1465 02:45:51.133978
1466 02:45:51.141872 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
1467 02:45:51.142391
1468 02:45:51.150086 <30>[ 19.656236] systemd[1]: Hostname set to <debian-bookworm-arm64>.
1469 02:45:51.828225 <30>[ 20.333138] systemd[1]: Queued start job for default target graphical.target.
1470 02:45:51.872326 <30>[ 20.376880] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
1471 02:45:51.880046 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
1472 02:45:51.891045 <30>[ 20.395515] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
1473 02:45:51.899523 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
1474 02:45:51.911205 <30>[ 20.415568] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
1475 02:45:51.924417 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
1476 02:45:51.930025 <30>[ 20.435280] systemd[1]: Created slice user.slice - User and Session Slice.
1477 02:45:51.936477 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
1478 02:45:51.947473 <30>[ 20.450793] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
1479 02:45:51.958998 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
1480 02:45:51.970090 <30>[ 20.470717] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
1481 02:45:51.976715 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
1482 02:45:51.998823 <30>[ 20.490700] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
1483 02:45:52.004417 <30>[ 20.504764] systemd[1]: Expecting device dev-ttyAML0.device - /dev/ttyAML0...
1484 02:45:52.012092 Expecting device [0;1;39mdev-ttyAML0.device[0m - /dev/ttyAML0...
1485 02:45:52.023074 <30>[ 20.526604] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
1486 02:45:52.030308 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
1487 02:45:52.046042 <30>[ 20.550621] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
1488 02:45:52.059754 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
1489 02:45:52.065351 <30>[ 20.570641] systemd[1]: Reached target paths.target - Path Units.
1490 02:45:52.073797 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
1491 02:45:52.079304 <30>[ 20.586627] systemd[1]: Reached target remote-fs.target - Remote File Systems.
1492 02:45:52.090991 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
1493 02:45:52.096605 <30>[ 20.602614] systemd[1]: Reached target slices.target - Slice Units.
1494 02:45:52.104746 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
1495 02:45:52.110322 <30>[ 20.618625] systemd[1]: Reached target swap.target - Swaps.
1496 02:45:52.118166 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
1497 02:45:52.130068 <30>[ 20.634648] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
1498 02:45:52.138983 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
1499 02:45:52.154232 <30>[ 20.658798] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
1500 02:45:52.163481 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
1501 02:45:52.175391 <30>[ 20.679938] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
1502 02:45:52.189266 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
1503 02:45:52.194831 <30>[ 20.699526] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
1504 02:45:52.207920 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
1505 02:45:52.213598 <30>[ 20.718982] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
1506 02:45:52.220325 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
1507 02:45:52.231340 <30>[ 20.735581] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
1508 02:45:52.240196 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
1509 02:45:52.252070 <30>[ 20.756615] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
1510 02:45:52.257655 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
1511 02:45:52.270287 <30>[ 20.774853] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
1512 02:45:52.278796 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
1513 02:45:52.322203 <30>[ 20.826767] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
1514 02:45:52.328958 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
1515 02:45:52.340662 <30>[ 20.845212] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
1516 02:45:52.348280 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
1517 02:45:52.363705 <30>[ 20.868251] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
1518 02:45:52.371178 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
1519 02:45:52.392673 <30>[ 20.891225] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
1520 02:45:52.403787 <30>[ 20.906857] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
1521 02:45:52.410899 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
1522 02:45:52.427091 <30>[ 20.931643] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
1523 02:45:52.435071 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
1524 02:45:52.451109 <30>[ 20.955665] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
1525 02:45:52.458734 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
1526 02:45:52.472093 <6>[ 20.976640] device-mapper: ioctl: 4.48.0-ioctl (2023-03-01) initialised: dm-devel@lists.linux.dev
1527 02:45:52.483189 <30>[ 20.979982] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
1528 02:45:52.488104 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
1529 02:45:52.503058 <30>[ 21.007586] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
1530 02:45:52.511354 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
1531 02:45:52.527057 <30>[ 21.031599] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
1532 02:45:52.534293 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
1533 02:45:52.546205 <6>[ 21.056281] fuse: init (API version 7.41)
1534 02:45:52.557282 <30>[ 21.057588] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
1535 02:45:52.561222 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
1536 02:45:52.587588 <30>[ 21.092160] systemd[1]: Starting systemd-journald.service - Journal Service...
1537 02:45:52.594009 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
1538 02:45:52.617522 <30>[ 21.122036] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
1539 02:45:52.625023 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
1540 02:45:52.639059 <30>[ 21.143586] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
1541 02:45:52.648365 Starting [0;1;39msystemd-network-g… units from Kernel command line...
1542 02:45:52.690618 <30>[ 21.195196] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
1543 02:45:52.699408 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
1544 02:45:52.718939 <30>[ 21.223493] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
1545 02:45:52.727010 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
1546 02:45:52.750140 <30>[ 21.254730] systemd[1]: Started systemd-journald.service - Journal Service.
1547 02:45:52.757020 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
1548 02:45:52.775296 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
1549 02:45:52.783300 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
1550 02:45:52.799242 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
1551 02:45:52.811828 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
1552 02:45:52.824896 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
1553 02:45:52.840952 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
1554 02:45:52.852692 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
1555 02:45:52.865058 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
1556 02:45:52.877097 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
1557 02:45:52.888848 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
1558 02:45:52.900266 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
1559 02:45:52.912045 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
1560 02:45:52.928059 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
1561 02:45:52.941508 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
1562 02:45:52.990520 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
1563 02:45:53.008037 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
1564 02:45:53.024269 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
1565 02:45:53.035852 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
1566 02:45:53.050469 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
1567 02:45:53.065316 <46>[ 21.569863] systemd-journald[235]: Received client request to flush runtime journal.
1568 02:45:53.072690 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
1569 02:45:53.087273 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
1570 02:45:53.103622 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
1571 02:45:53.115147 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
1572 02:45:53.128311 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
1573 02:45:53.141363 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
1574 02:45:53.209157 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
1575 02:45:53.270564 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
1576 02:45:53.390883 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
1577 02:45:53.398378 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
1578 02:45:53.410818 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
1579 02:45:53.425846 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
1580 02:45:53.485772 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
1581 02:45:53.496526 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
1582 02:45:53.734706 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
1583 02:45:53.741200 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
1584 02:45:53.797801 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
1585 02:45:53.815225 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
1586 02:45:53.830531 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
1587 02:45:53.918477 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
1588 02:45:53.936946 [[0;32m OK [0m] Found device [0;1;39mdev-ttyAML0.device[0m - /dev/ttyAML0.
1589 02:45:53.954041 <5>[ 22.458736] cfg80211: Loading compiled-in X.509 certificates for regulatory database
1590 02:45:53.993528 <5>[ 22.498067] Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
1591 02:45:53.999169 <5>[ 22.499046] Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
1592 02:45:54.004643 <4>[ 22.507566] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
1593 02:45:54.010204 <6>[ 22.514988] cfg80211: failed to load regulatory.db
1594 02:45:54.023000 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
1595 02:45:54.030561 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
1596 02:45:54.046616 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
1597 02:45:54.061654 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
1598 02:45:54.084307 <46>[ 22.577805] systemd-journald[235]: Oldest entry in /var/log/journal/44a983756b26438995e691b947c527e4/system.journal is older than the configured file retention duration (1month), suggesting rotation.
1599 02:45:54.095554 <46>[ 22.590371] systemd-journald[235]: /var/log/journal/44a983756b26438995e691b947c527e4/system.journal: Journal header limits reached or header out-of-date, rotating.
1600 02:45:54.106169 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
1601 02:45:54.130258 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
1602 02:45:54.136687 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
1603 02:45:54.162465 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
1604 02:45:54.246381 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
1605 02:45:54.253287 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
1606 02:45:54.271614 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
1607 02:45:54.278430 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
1608 02:45:54.287088 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
1609 02:45:54.346596 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
1610 02:45:54.382293 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
1611 02:45:54.407005 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
1612 02:45:54.419039 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
1613 02:45:54.475944 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
1614 02:45:54.482774 [[0;32m OK [0m] Reached target [0;1;39musb-gadget.…m - Hardware activated USB gadget.
1615 02:45:54.494811 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
1616 02:45:54.549320 Starting [0;1;39malsa-restore.serv…- Save/Restore Sound Card State...
1617 02:45:54.557744 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
1618 02:45:54.566079 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
1619 02:45:54.601078 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
1620 02:45:54.618606 [[0;32m OK [0m] Finished [0;1;39malsa-restore.serv…m - Save/Restore Sound Card State.
1621 02:45:54.626110 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
1622 02:45:54.638292 [[0;32m OK [0m] Reached target [0;1;39msound.target[0m - Sound Card.
1623 02:45:54.669566 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
1624 02:45:54.690328 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyAM…ice[0m - Serial Getty on ttyAML0.
1625 02:45:54.697518 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
1626 02:45:54.708614 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
1627 02:45:54.726871 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
1628 02:45:54.734356 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
1629 02:45:54.782388 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
1630 02:45:54.833495 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
1631 02:45:54.909324
1632 02:45:54.909735 Debian GNU/Linux 12 debian-bookworm-arm64 ttyAML0
1633 02:45:54.909983
1634 02:45:54.916509 debian-bookworm-arm64 login: root (automatic login)
1635 02:45:54.916849
1636 02:45:55.045519 Linux debian-bookworm-arm64 6.12.0-rc5 #1 SMP PREEMPT Mon Nov 4 01:54:17 UTC 2024 aarch64
1637 02:45:55.045930
1638 02:45:55.051087 The programs included with the Debian GNU/Linux system are free software;
1639 02:45:55.056593 the exact distribution terms for each program are described in the
1640 02:45:55.062135 individual files in /usr/share/doc/*/copyright.
1641 02:45:55.062473
1642 02:45:55.067680 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
1643 02:45:55.070928 permitted by applicable law.
1644 02:45:55.782905 Matched prompt #10: / #
1646 02:45:55.784580 Setting prompt string to ['/ #']
1647 02:45:55.785196 end: 2.4.4.1 login-action (duration 00:00:25) [common]
1649 02:45:55.786579 end: 2.4.4 auto-login-action (duration 00:00:25) [common]
1650 02:45:55.787121 start: 2.4.5 expect-shell-connection (timeout 00:03:16) [common]
1651 02:45:55.787560 Setting prompt string to ['/ #']
1652 02:45:55.787966 Forcing a shell prompt, looking for ['/ #']
1654 02:45:55.838965 / #
1655 02:45:55.839656 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
1656 02:45:55.840142 Waiting using forced prompt support (timeout 00:02:30)
1657 02:45:55.845243
1658 02:45:55.846024 end: 2.4.5 expect-shell-connection (duration 00:00:00) [common]
1659 02:45:55.846569 start: 2.4.6 export-device-env (timeout 00:03:16) [common]
1660 02:45:55.847026 Sending with 10 millisecond of delay
1662 02:46:00.835869 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/932188/extract-nfsrootfs-4umrveq0'
1663 02:46:00.846875 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/932188/extract-nfsrootfs-4umrveq0'
1664 02:46:00.847653 Sending with 10 millisecond of delay
1666 02:46:02.945553 / # export NFS_SERVER_IP='192.168.6.2'
1667 02:46:02.956480 export NFS_SERVER_IP='192.168.6.2'
1668 02:46:02.957346 end: 2.4.6 export-device-env (duration 00:00:07) [common]
1669 02:46:02.957939 end: 2.4 uboot-commands (duration 00:01:51) [common]
1670 02:46:02.958519 end: 2 uboot-action (duration 00:01:51) [common]
1671 02:46:02.959099 start: 3 lava-test-retry (timeout 00:06:51) [common]
1672 02:46:02.959680 start: 3.1 lava-test-shell (timeout 00:06:51) [common]
1673 02:46:02.960197 Using namespace: common
1675 02:46:03.061390 / # #
1676 02:46:03.062045 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
1677 02:46:03.067064 #
1678 02:46:03.067791 Using /lava-932188
1680 02:46:03.168963 / # export SHELL=/bin/bash
1681 02:46:03.174666 export SHELL=/bin/bash
1683 02:46:03.276067 / # . /lava-932188/environment
1684 02:46:03.280879 . /lava-932188/environment
1686 02:46:03.385697 / # /lava-932188/bin/lava-test-runner /lava-932188/0
1687 02:46:03.386362 Test shell timeout: 10s (minimum of the action and connection timeout)
1688 02:46:03.390650 /lava-932188/bin/lava-test-runner /lava-932188/0
1689 02:46:03.582876 + export TESTRUN_ID=0_timesync-off
1690 02:46:03.590773 + TESTRUN_ID=0_timesync-off
1691 02:46:03.591247 + cd /lava-932188/0/tests/0_timesync-off
1692 02:46:03.591675 ++ cat uuid
1693 02:46:03.598229 + UUID=932188_1.6.2.4.1
1694 02:46:03.598683 + set +x
1695 02:46:03.606805 <LAVA_SIGNAL_STARTRUN 0_timesync-off 932188_1.6.2.4.1>
1696 02:46:03.607308 + systemctl stop systemd-timesyncd
1697 02:46:03.608048 Received signal: <STARTRUN> 0_timesync-off 932188_1.6.2.4.1
1698 02:46:03.608514 Starting test lava.0_timesync-off (932188_1.6.2.4.1)
1699 02:46:03.609059 Skipping test definition patterns.
1700 02:46:03.652179 + set +x
1701 02:46:03.652721 <LAVA_SIGNAL_ENDRUN 0_timesync-off 932188_1.6.2.4.1>
1702 02:46:03.653400 Received signal: <ENDRUN> 0_timesync-off 932188_1.6.2.4.1
1703 02:46:03.653892 Ending use of test pattern.
1704 02:46:03.654303 Ending test lava.0_timesync-off (932188_1.6.2.4.1), duration 0.05
1706 02:46:03.752019 + export TESTRUN_ID=1_kselftest-alsa
1707 02:46:03.760377 + TESTRUN_ID=1_kselftest-alsa
1708 02:46:03.760853 + cd /lava-932188/0/tests/1_kselftest-alsa
1709 02:46:03.761279 ++ cat uuid
1710 02:46:03.766266 + UUID=932188_1.6.2.4.5
1711 02:46:03.766713 + set +x
1712 02:46:03.771788 <LAVA_SIGNAL_STARTRUN 1_kselftest-alsa 932188_1.6.2.4.5>
1713 02:46:03.772263 + cd ./automated/linux/kselftest/
1714 02:46:03.772950 Received signal: <STARTRUN> 1_kselftest-alsa 932188_1.6.2.4.5
1715 02:46:03.773380 Starting test lava.1_kselftest-alsa (932188_1.6.2.4.5)
1716 02:46:03.773867 Skipping test definition patterns.
1717 02:46:03.800570 + ./kselftest.sh -c alsa -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/next/pending-fixes/v6.12-rc5-576-g10616629aaf32/arm64/defconfig/gcc-12/kselftest.tar.xz -L '' -S /dev/null -b meson-g12b-a311d-libretech-cc -g next -e '' -p /opt/kselftests/mainline/ -n 1 -i 1 -E ''
1718 02:46:03.835835 INFO: install_deps skipped
1719 02:46:03.950790 --2024-11-04 02:46:03-- http://storage.kernelci.org/next/pending-fixes/v6.12-rc5-576-g10616629aaf32/arm64/defconfig/gcc-12/kselftest.tar.xz
1720 02:46:03.986829 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
1721 02:46:04.128118 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
1722 02:46:04.266942 HTTP request sent, awaiting response... 200 OK
1723 02:46:04.267513 Length: 6928964 (6.6M) [application/octet-stream]
1724 02:46:04.272234 Saving to: 'kselftest_armhf.tar.gz'
1725 02:46:04.272682
1726 02:46:05.701137
kselftest_armhf.tar 0%[ ] 0 --.-KB/s
kselftest_armhf.tar 0%[ ] 49.92K 179KB/s
kselftest_armhf.tar 3%[ ] 218.67K 393KB/s
kselftest_armhf.tar 13%[=> ] 893.67K 1.05MB/s
kselftest_armhf.tar 53%[=========> ] 3.51M 3.15MB/s
kselftest_armhf.tar 98%[==================> ] 6.52M 4.59MB/s
kselftest_armhf.tar 100%[===================>] 6.61M 4.65MB/s in 1.4s
1727 02:46:05.701783
1728 02:46:05.788082 2024-11-04 02:46:05 (4.65 MB/s) - 'kselftest_armhf.tar.gz' saved [6928964/6928964]
1729 02:46:05.788677
1730 02:46:14.970524 skiplist:
1731 02:46:14.971158 ========================================
1732 02:46:14.975919 ========================================
1733 02:46:15.013974 alsa:mixer-test
1734 02:46:15.014467 alsa:pcm-test
1735 02:46:15.014880 alsa:test-pcmtest-driver
1736 02:46:15.018190 alsa:utimer-test
1737 02:46:15.029371 ============== Tests to run ===============
1738 02:46:15.029816 alsa:mixer-test
1739 02:46:15.034948 alsa:pcm-test
1740 02:46:15.035368 alsa:test-pcmtest-driver
1741 02:46:15.035766 alsa:utimer-test
1742 02:46:15.043230 ===========End Tests to run ===============
1743 02:46:15.043666 shardfile-alsa pass
1744 02:46:15.143879 <12>[ 43.651829] kselftest: Running tests in alsa
1745 02:46:15.150364 TAP version 13
1746 02:46:15.161452 1..4
1747 02:46:15.181931 # timeout set to 45
1748 02:46:15.182364 # selftests: alsa: mixer-test
1749 02:46:15.346921 # TAP version 13
1750 02:46:15.347454 # # Card 0/LCALTA - LC-ALTA (LC-ALTA)
1751 02:46:15.352421 # 1..427
1752 02:46:15.352884 # ok 1 get_value.LCALTA.60
1753 02:46:15.353288 # # LCALTA.60 TDMOUT_A SRC SEL
1754 02:46:15.357889 # ok 2 name.LCALTA.60
1755 02:46:15.358312 # ok 3 write_default.LCALTA.60
1756 02:46:15.363470 # ok 4 write_valid.LCALTA.60
1757 02:46:15.363891 # ok 5 write_invalid.LCALTA.60
1758 02:46:15.369035 # ok 6 event_missing.LCALTA.60
1759 02:46:15.369457 # ok 7 event_spurious.LCALTA.60
1760 02:46:15.374612 # ok 8 get_value.LCALTA.59
1761 02:46:15.375033 # # LCALTA.59 TDMOUT_B SRC SEL
1762 02:46:15.380203 # ok 9 name.LCALTA.59
1763 02:46:15.380625 # ok 10 write_default.LCALTA.59
1764 02:46:15.385751 # ok 11 write_valid.LCALTA.59
1765 02:46:15.386173 # ok 12 write_invalid.LCALTA.59
1766 02:46:15.391224 # ok 13 event_missing.LCALTA.59
1767 02:46:15.391646 # ok 14 event_spurious.LCALTA.59
1768 02:46:15.396797 # ok 15 get_value.LCALTA.58
1769 02:46:15.397221 # # LCALTA.58 TDMOUT_C SRC SEL
1770 02:46:15.402254 # ok 16 name.LCALTA.58
1771 02:46:15.402673 # ok 17 write_default.LCALTA.58
1772 02:46:15.407905 # ok 18 write_valid.LCALTA.58
1773 02:46:15.408364 # ok 19 write_invalid.LCALTA.58
1774 02:46:15.413388 # ok 20 event_missing.LCALTA.58
1775 02:46:15.413815 # ok 21 event_spurious.LCALTA.58
1776 02:46:15.418968 # ok 22 get_value.LCALTA.57
1777 02:46:15.419392 # # LCALTA.57 TDMIN_A SRC SEL
1778 02:46:15.419792 # ok 23 name.LCALTA.57
1779 02:46:15.424482 # ok 24 write_default.LCALTA.57
1780 02:46:15.424904 # ok 25 write_valid.LCALTA.57
1781 02:46:15.430028 # ok 26 write_invalid.LCALTA.57
1782 02:46:15.430451 # ok 27 event_missing.LCALTA.57
1783 02:46:15.435675 # ok 28 event_spurious.LCALTA.57
1784 02:46:15.436125 # ok 29 get_value.LCALTA.56
1785 02:46:15.441164 # # LCALTA.56 TDMIN_B SRC SEL
1786 02:46:15.441590 # ok 30 name.LCALTA.56
1787 02:46:15.446718 # ok 31 write_default.LCALTA.56
1788 02:46:15.447136 # ok 32 write_valid.LCALTA.56
1789 02:46:15.452293 # ok 33 write_invalid.LCALTA.56
1790 02:46:15.463470 # ok 34 event_missing.LCAL<3>[ 43.961673] fe.dai-link-5: ASoC: no backend DAIs enabled for fe.dai-link-5, possibly missing ALSA mixer-based routing or UCM profile
1791 02:46:15.464081 TA.56
1792 02:46:15.468999 # ok 35 event_spurious.LCALTA.56
1793 02:46:15.469532 # ok 36 get_value.LCALTA.55
1794 02:46:15.474552 # # LCALTA.55 TDMIN_C SRC SEL
1795 02:46:15.475070 # ok 37 name.LCALTA.55
1796 02:46:15.480009 # ok 38 write_default.LCALTA.55
1797 02:46:15.480528 # ok 39 write_valid.LCALTA.55
1798 02:46:15.485513 # ok 40 write_invalid.LCALTA.55
1799 02:46:15.486022 # ok 41 event_missing.LCALTA.55
1800 02:46:15.491060 # ok 42 event_spurious.LCALTA.55
1801 02:46:15.491571 # ok 43 get_value.LCALTA.54
1802 02:46:15.496607 # # LCALTA.54 ACODEC Left DAC Sel
1803 02:46:15.497120 # ok 44 name.LCALTA.54
1804 02:46:15.502144 # ok 45 write_default.LCALTA.54
1805 02:46:15.502652 # ok 46 write_valid.LCALTA.54
1806 02:46:15.507736 # ok 47 write_invalid.LCALTA.54
1807 02:46:15.508287 # ok 48 event_missing.LCALTA.54
1808 02:46:15.513274 # ok 49 event_spurious.LCALTA.54
1809 02:46:15.513782 # ok 50 get_value.LCALTA.53
1810 02:46:15.518819 # # LCALTA.53 ACODEC Right DAC Sel
1811 02:46:15.519330 # ok 51 name.LCALTA.53
1812 02:46:15.524381 # ok 52 write_default.LCALTA.53
1813 02:46:15.524894 # ok 53 write_valid.LCALTA.53
1814 02:46:15.529896 # ok 54 write_invalid.LCALTA.53
1815 02:46:15.530402 # ok 55 event_missing.LCALTA.53
1816 02:46:15.535452 # ok 56 event_spurious.LCALTA.53
1817 02:46:15.536057 # ok 57 get_value.LCALTA.52
1818 02:46:15.540987 # # LCALTA.52 TOACODEC OUT EN Switch
1819 02:46:15.541510 # ok 58 name.LCALTA.52
1820 02:46:15.546555 # ok 59 write_default.LCALTA.52
1821 02:46:15.547087 # ok 60 write_valid.LCALTA.52
1822 02:46:15.552121 # ok 61 write_invalid.LCALTA.52
1823 02:46:15.552672 # ok 62 event_missing.LCALTA.52
1824 02:46:15.557699 # ok 63 event_spurious.LCALTA.52
1825 02:46:15.558349 # ok 64 get_value.LCALTA.51
1826 02:46:15.563247 # # LCALTA.51 TOACODEC SRC
1827 02:46:15.563843 # ok 65 name.LCALTA.51
1828 02:46:15.568801 # ok 66 write_default.LCALTA.51
1829 02:46:15.569392 # ok 67 write_valid.LCALTA.51
1830 02:46:15.574259 # ok 68 write_invalid.LCALTA.51
1831 02:46:15.574788 # ok 69 event_missing.LCALTA.51
1832 02:46:15.579801 # ok 70 event_spurious.LCALTA.51
1833 02:46:15.580441 # ok 71 get_value.LCALTA.50
1834 02:46:15.585392 # # LCALTA.50 TOHDMITX SPDIF SRC
1835 02:46:15.585917 # ok 72 name.LCALTA.50
1836 02:46:15.586368 # ok 73 write_default.LCALTA.50
1837 02:46:15.590895 # ok 74 write_valid.LCALTA.50
1838 02:46:15.591415 # ok 75 write_invalid.LCALTA.50
1839 02:46:15.596442 # ok 76 event_missing.LCALTA.50
1840 02:46:15.602082 # ok 77 event_spurious.LCALTA.50
1841 02:46:15.602814 # ok 78 get_value.LCALTA.49
1842 02:46:15.603429 # # LCALTA.49 TOHDMITX Switch
1843 02:46:15.607518 # ok 79 name.LCALTA.49
1844 02:46:15.608072 # ok 80 write_default.LCALTA.49
1845 02:46:15.613061 # ok 81 write_valid.LCALTA.49
1846 02:46:15.613582 # ok 82 write_invalid.LCALTA.49
1847 02:46:15.618610 # ok 83 event_missing.LCALTA.49
1848 02:46:15.619132 # ok 84 event_spurious.LCALTA.49
1849 02:46:15.624246 # ok 85 get_value.LCALTA.48
1850 02:46:15.624807 # # LCALTA.48 TOHDMITX I2S SRC
1851 02:46:15.629787 # ok 86 name.LCALTA.48
1852 02:46:15.630409 # ok 87 write_default.LCALTA.48
1853 02:46:15.635286 # ok 88 write_valid.LCALTA.48
1854 02:46:15.635824 # ok 89 write_invalid.LCALTA.48
1855 02:46:15.640833 # ok 90 event_missing.LCALTA.48
1856 02:46:15.641361 # ok 91 event_spurious.LCALTA.48
1857 02:46:15.646387 # ok 92 get_value.LCALTA.47
1858 02:46:15.646907 # # LCALTA.47 TODDR_C SRC SEL
1859 02:46:15.651916 # ok 93 name.LCALTA.47
1860 02:46:15.652469 # ok 94 write_default.LCALTA.47
1861 02:46:15.657468 # ok 95 write_valid.LCALTA.47
1862 02:46:15.657997 # ok 96 write_invalid.LCALTA.47
1863 02:46:15.663021 # ok 97 event_missing.LCALTA.47
1864 02:46:15.663542 # ok 98 event_spurious.LCALTA.47
1865 02:46:15.668566 # ok 99 get_value.LCALTA.46
1866 02:46:15.669162 # # LCALTA.46 TODDR_B SRC SEL
1867 02:46:15.669646 # ok 100 name.LCALTA.46
1868 02:46:15.674112 # ok 101 write_default.LCALTA.46
1869 02:46:15.679724 # ok 102 write_valid.LCALTA.46
1870 02:46:15.680291 # ok 103 write_invalid.LCALTA.46
1871 02:46:15.685248 # ok 104 event_missing.LCALTA.46
1872 02:46:15.685774 # ok 105 event_spurious.LCALTA.46
1873 02:46:15.690808 # ok 106 get_value.LCALTA.45
1874 02:46:15.691333 # # LCALTA.45 TODDR_A SRC SEL
1875 02:46:15.691788 # ok 107 name.LCALTA.45
1876 02:46:15.696294 # ok 108 write_default.LCALTA.45
1877 02:46:15.701853 # ok 109 write_valid.LCALTA.45
1878 02:46:15.702374 # ok 110 write_invalid.LCALTA.45
1879 02:46:15.707395 # ok 111 event_missing.LCALTA.45
1880 02:46:15.707920 # ok 112 event_spurious.LCALTA.45
1881 02:46:15.712937 # ok 113 get_value.LCALTA.44
1882 02:46:15.713461 # # LCALTA.44 FRDDR_C SINK 3 SEL
1883 02:46:15.718505 # ok 114 name.LCALTA.44
1884 02:46:15.719026 # ok 115 write_default.LCALTA.44
1885 02:46:15.724086 # ok 116 write_valid.LCALTA.44
1886 02:46:15.724611 # ok 117 write_invalid.LCALTA.44
1887 02:46:15.729592 # ok 118 event_missing.LCALTA.44
1888 02:46:15.730118 # ok 119 event_spurious.LCALTA.44
1889 02:46:15.735142 # ok 120 get_value.LCALTA.43
1890 02:46:15.735668 # # LCALTA.43 FRDDR_C SINK 2 SEL
1891 02:46:15.740679 # ok 121 name.LCALTA.43
1892 02:46:15.741200 # ok 122 write_default.LCALTA.43
1893 02:46:15.746221 # ok 123 write_valid.LCALTA.43
1894 02:46:15.746754 # ok 124 write_invalid.LCALTA.43
1895 02:46:15.751844 # ok 125 event_missing.LCALTA.43
1896 02:46:15.752401 # ok 126 event_spurious.LCALTA.43
1897 02:46:15.757332 # ok 127 get_value.LCALTA.42
1898 02:46:15.757855 # # LCALTA.42 FRDDR_C SINK 1 SEL
1899 02:46:15.762845 # ok 128 name.LCALTA.42
1900 02:46:15.763369 # ok 129 write_default.LCALTA.42
1901 02:46:15.768405 # ok 130 write_valid.LCALTA.42
1902 02:46:15.768933 # ok 131 write_invalid.LCALTA.42
1903 02:46:15.773948 # ok 132 event_missing.LCALTA.42
1904 02:46:15.774474 # ok 133 event_spurious.LCALTA.42
1905 02:46:15.779504 # ok 134 get_value.LCALTA.41
1906 02:46:15.780069 # # LCALTA.41 FRDDR_C SRC 3 EN Switch
1907 02:46:15.785079 # ok 135 name.LCALTA.41
1908 02:46:15.785602 # ok 136 write_default.LCALTA.41
1909 02:46:15.790622 # ok 137 write_valid.LCALTA.41
1910 02:46:15.791153 # ok 138 write_invalid.LCALTA.41
1911 02:46:15.796180 # ok 139 event_missing.LCALTA.41
1912 02:46:15.796711 # ok 140 event_spurious.LCALTA.41
1913 02:46:15.801761 # ok 141 get_value.LCALTA.40
1914 02:46:15.802306 # # LCALTA.40 FRDDR_C SRC 2 EN Switch
1915 02:46:15.807263 # ok 142 name.LCALTA.40
1916 02:46:15.807810 # ok 143 write_default.LCALTA.40
1917 02:46:15.812828 # ok 144 write_valid.LCALTA.40
1918 02:46:15.813347 # ok 145 write_invalid.LCALTA.40
1919 02:46:15.818335 # ok 146 event_missing.LCALTA.40
1920 02:46:15.818846 # ok 147 event_spurious.LCALTA.40
1921 02:46:15.823877 # ok 148 get_value.LCALTA.39
1922 02:46:15.829425 # # LCALTA.39 FRDDR_C SRC 1 EN Switch
1923 02:46:15.829935 # ok 149 name.LCALTA.39
1924 02:46:15.830366 # ok 150 write_default.LCALTA.39
1925 02:46:15.834942 # ok 151 write_valid.LCALTA.39
1926 02:46:15.835454 # ok 152 write_invalid.LCALTA.39
1927 02:46:15.840487 # ok 153 event_missing.LCALTA.39
1928 02:46:15.846086 # ok 154 event_spurious.LCALTA.39
1929 02:46:15.846596 # ok 155 get_value.LCALTA.38
1930 02:46:15.851604 # # LCALTA.38 FRDDR_B SINK 3 SEL
1931 02:46:15.852147 # ok 156 name.LCALTA.38
1932 02:46:15.852582 # ok 157 write_default.LCALTA.38
1933 02:46:15.857129 # ok 158 write_valid.LCALTA.38
1934 02:46:15.857655 # ok 159 write_invalid.LCALTA.38
1935 02:46:15.862700 # ok 160 event_missing.LCALTA.38
1936 02:46:15.868266 # ok 161 event_spurious.LCALTA.38
1937 02:46:15.868780 # ok 162 get_value.LCALTA.37
1938 02:46:15.873802 # # LCALTA.37 FRDDR_B SINK 2 SEL
1939 02:46:15.874316 # ok 163 name.LCALTA.37
1940 02:46:15.874750 # ok 164 write_default.LCALTA.37
1941 02:46:15.879334 # ok 165 write_valid.LCALTA.37
1942 02:46:15.884868 # ok 166 write_invalid.LCALTA.37
1943 02:46:15.885419 # ok 167 event_missing.LCALTA.37
1944 02:46:15.890490 # ok 168 event_spurious.LCALTA.37
1945 02:46:15.891041 # ok 169 get_value.LCALTA.36
1946 02:46:15.895973 # # LCALTA.36 FRDDR_B SINK 1 SEL
1947 02:46:15.896539 # ok 170 name.LCALTA.36
1948 02:46:15.901542 # ok 171 write_default.LCALTA.36
1949 02:46:15.902069 # ok 172 write_valid.LCALTA.36
1950 02:46:15.907046 # ok 173 write_invalid.LCALTA.36
1951 02:46:15.907575 # ok 174 event_missing.LCALTA.36
1952 02:46:15.912602 # ok 175 event_spurious.LCALTA.36
1953 02:46:15.913125 # ok 176 get_value.LCALTA.35
1954 02:46:15.918150 # # LCALTA.35 FRDDR_B SRC 3 EN Switch
1955 02:46:15.918677 # ok 177 name.LCALTA.35
1956 02:46:15.923700 # ok 178 write_default.LCALTA.35
1957 02:46:15.924252 # ok 179 write_valid.LCALTA.35
1958 02:46:15.929234 # ok 180 write_invalid.LCALTA.35
1959 02:46:15.929751 # ok 181 event_missing.LCALTA.35
1960 02:46:15.934821 # ok 182 event_spurious.LCALTA.35
1961 02:46:15.935343 # ok 183 get_value.LCALTA.34
1962 02:46:15.940448 # # LCALTA.34 FRDDR_B SRC 2 EN Switch
1963 02:46:15.941020 # ok 184 name.LCALTA.34
1964 02:46:15.945923 # ok 185 write_default.LCALTA.34
1965 02:46:15.946469 # ok 186 write_valid.LCALTA.34
1966 02:46:15.951486 # ok 187 write_invalid.LCALTA.34
1967 02:46:15.952048 # ok 188 event_missing.LCALTA.34
1968 02:46:15.957026 # ok 189 event_spurious.LCALTA.34
1969 02:46:15.957557 # ok 190 get_value.LCALTA.33
1970 02:46:15.962556 # # LCALTA.33 FRDDR_B SRC 1 EN Switch
1971 02:46:15.963090 # ok 191 name.LCALTA.33
1972 02:46:15.968104 # ok 192 write_default.LCALTA.33
1973 02:46:15.968642 # ok 193 write_valid.LCALTA.33
1974 02:46:15.973655 # ok 194 write_invalid.LCALTA.33
1975 02:46:15.974191 # ok 195 event_missing.LCALTA.33
1976 02:46:15.979193 # ok 196 event_spurious.LCALTA.33
1977 02:46:15.979725 # ok 197 get_value.LCALTA.32
1978 02:46:15.984741 # # LCALTA.32 FRDDR_A SINK 3 SEL
1979 02:46:15.985273 # ok 198 name.LCALTA.32
1980 02:46:15.990655 # ok 199 write_default.LCALTA.32
1981 02:46:15.991271 # ok 200 write_valid.LCALTA.32
1982 02:46:15.996450 # ok 201 write_invalid.LCALTA.32
1983 02:46:16.000170 # ok 202 event_missing.LCALTA.32
1984 02:46:16.002326 # ok 203 event_spurious.LCALTA.32
1985 02:46:16.002968 # ok 204 get_value.LCALTA.31
1986 02:46:16.007871 # # LCALTA.31 FRDDR_A SINK 2 SEL
1987 02:46:16.008929 # ok 205 name.LCALTA.31
1988 02:46:16.012532 # ok 206 write_default.LCALTA.31
1989 02:46:16.013157 # ok 207 write_valid.LCALTA.31
1990 02:46:16.018099 # ok 208 write_invalid.LCALTA.31
1991 02:46:16.018784 # ok 209 event_missing.LCALTA.31
1992 02:46:16.023654 # ok 210 event_spurious.LCALTA.31
1993 02:46:16.024307 # ok 211 get_value.LCALTA.30
1994 02:46:16.029137 # # LCALTA.30 FRDDR_A SINK 1 SEL
1995 02:46:16.029725 # ok 212 name.LCALTA.30
1996 02:46:16.034736 # ok 213 write_default.LCALTA.30
1997 02:46:16.035437 # ok 214 write_valid.LCALTA.30
1998 02:46:16.040382 # ok 215 write_invalid.LCALTA.30
1999 02:46:16.046155 # ok 216 event_missing.LCALTA.30
2000 02:46:16.046839 # ok 217 event_spurious.LCALTA.30
2001 02:46:16.051272 # ok 218 get_value.LCALTA.29
2002 02:46:16.051720 # # LCALTA.29 FRDDR_A SRC 3 EN Switch
2003 02:46:16.057030 # ok 219 name.LCALTA.29
2004 02:46:16.057611 # ok 220 write_default.LCALTA.29
2005 02:46:16.063442 # ok 221 write_valid.LCALTA.29
2006 02:46:16.063909 # ok 222 write_invalid.LCALTA.29
2007 02:46:16.067888 # ok 223 event_missing.LCALTA.29
2008 02:46:16.068278 # ok 224 event_spurious.LCALTA.29
2009 02:46:16.075136 # ok 225 get_value.LCALTA.28
2010 02:46:16.075782 # # LCALTA.28 FRDDR_A SRC 2 EN Switch
2011 02:46:16.079335 # ok 226 name.LCALTA.28
2012 02:46:16.079938 # ok 227 write_default.LCALTA.28
2013 02:46:16.084592 # ok 228 write_valid.LCALTA.28
2014 02:46:16.084981 # ok 229 write_invalid.LCALTA.28
2015 02:46:16.089971 # ok 230 event_missing.LCALTA.28
2016 02:46:16.090291 # ok 231 event_spurious.LCALTA.28
2017 02:46:16.095490 # ok 232 get_value.LCALTA.27
2018 02:46:16.095792 # # LCALTA.27 FRDDR_A SRC 1 EN Switch
2019 02:46:16.101455 # ok 233 name.LCALTA.27
2020 02:46:16.101779 # ok 234 write_default.LCALTA.27
2021 02:46:16.106585 # ok 235 write_valid.LCALTA.27
2022 02:46:16.106890 # ok 236 write_invalid.LCALTA.27
2023 02:46:16.112618 # ok 237 event_missing.LCALTA.27
2024 02:46:16.113223 # ok 238 event_spurious.LCALTA.27
2025 02:46:16.117826 # ok 239 get_value.LCALTA.26
2026 02:46:16.118379 # # LCALTA.26 ELD
2027 02:46:16.123326 # ok 240 name.LCALTA.26
2028 02:46:16.123623 # # ELD is not writeable
2029 02:46:16.128923 # ok 241 # SKIP write_default.LCALTA.26
2030 02:46:16.129469 # # ELD is not writeable
2031 02:46:16.134471 # ok 242 # SKIP write_valid.LCALTA.26
2032 02:46:16.135013 # # ELD is not writeable
2033 02:46:16.140050 # ok 243 # SKIP write_invalid.LCALTA.26
2034 02:46:16.140602 # ok 244 event_missing.LCALTA.26
2035 02:46:16.145565 # ok 245 event_spurious.LCALTA.26
2036 02:46:16.146101 # ok 246 get_value.LCALTA.25
2037 02:46:16.151136 # # LCALTA.25 IEC958 Playback Default
2038 02:46:16.151679 # ok 247 name.LCALTA.25
2039 02:46:16.156680 # ok 248 write_default.LCALTA.25
2040 02:46:16.157213 # ok 249 # SKIP write_valid.LCALTA.25
2041 02:46:16.162220 # ok 250 # SKIP write_invalid.LCALTA.25
2042 02:46:16.167743 # ok 251 event_missing.LCALTA.25
2043 02:46:16.168313 # ok 252 event_spurious.LCALTA.25
2044 02:46:16.173323 # ok 253 get_value.LCALTA.24
2045 02:46:16.173860 # # LCALTA.24 IEC958 Playback Mask
2046 02:46:16.174326 # ok 254 name.LCALTA.24
2047 02:46:16.178868 # # IEC958 Playback Mask is not writeable
2048 02:46:16.184393 # ok 255 # SKIP write_default.LCALTA.24
2049 02:46:16.184925 # # IEC958 Playback Mask is not writeable
2050 02:46:16.189951 # ok 256 # SKIP write_valid.LCALTA.24
2051 02:46:16.195482 # # IEC958 Playback Mask is not writeable
2052 02:46:16.196054 # ok 257 # SKIP write_invalid.LCALTA.24
2053 02:46:16.201039 # ok 258 event_missing.LCALTA.24
2054 02:46:16.201571 # ok 259 event_spurious.LCALTA.24
2055 02:46:16.206596 # ok 260 get_value.LCALTA.23
2056 02:46:16.207128 # # LCALTA.23 Playback Channel Map
2057 02:46:16.212158 # ok 261 name.LCALTA.23
2058 02:46:16.217680 # # Playback Channel Map is not writeable
2059 02:46:16.218217 # ok 262 # SKIP write_default.LCALTA.23
2060 02:46:16.223256 # # Playback Channel Map is not writeable
2061 02:46:16.223789 # ok 263 # SKIP write_valid.LCALTA.23
2062 02:46:16.228750 # # Playback Channel Map is not writeable
2063 02:46:16.234337 # ok 264 # SKIP write_invalid.LCALTA.23
2064 02:46:16.234867 # ok 265 event_missing.LCALTA.23
2065 02:46:16.239870 # ok 266 event_spurious.LCALTA.23
2066 02:46:16.240443 # ok 267 get_value.LCALTA.22
2067 02:46:16.245433 # # LCALTA.22 TDMOUT_A Gain Enable Switch
2068 02:46:16.245974 # ok 268 name.LCALTA.22
2069 02:46:16.250970 # ok 269 write_default.LCALTA.22
2070 02:46:16.251500 # ok 270 write_valid.LCALTA.22
2071 02:46:16.256480 # ok 271 write_invalid.LCALTA.22
2072 02:46:16.257011 # ok 272 event_missing.LCALTA.22
2073 02:46:16.262026 # ok 273 event_spurious.LCALTA.22
2074 02:46:16.267574 # ok 274 get_value.LCALTA.21
2075 02:46:16.268134 # # LCALTA.21 TDMOUT_A Lane 3 Volume
2076 02:46:16.268594 # ok 275 name.LCALTA.21
2077 02:46:16.273144 # ok 276 write_default.LCALTA.21
2078 02:46:16.278723 # ok 277 write_valid.LCALTA.21
2079 02:46:16.279272 # ok 278 write_invalid.LCALTA.21
2080 02:46:16.284267 # ok 279 event_missing.LCALTA.21
2081 02:46:16.284800 # ok 280 event_spurious.LCALTA.21
2082 02:46:16.289793 # ok 281 get_value.LCALTA.20
2083 02:46:16.290325 # # LCALTA.20 TDMOUT_A Lane 2 Volume
2084 02:46:16.295329 # ok 282 name.LCALTA.20
2085 02:46:16.295855 # ok 283 write_default.LCALTA.20
2086 02:46:16.300860 # ok 284 write_valid.LCALTA.20
2087 02:46:16.301389 # ok 285 write_invalid.LCALTA.20
2088 02:46:16.306433 # ok 286 event_missing.LCALTA.20
2089 02:46:16.306963 # ok 287 event_spurious.LCALTA.20
2090 02:46:16.312005 # ok 288 get_value.LCALTA.19
2091 02:46:16.312533 # # LCALTA.19 TDMOUT_A Lane 1 Volume
2092 02:46:16.317524 # ok 289 name.LCALTA.19
2093 02:46:16.318056 # ok 290 write_default.LCALTA.19
2094 02:46:16.323066 # ok 291 write_valid.LCALTA.19
2095 02:46:16.323589 # ok 292 write_invalid.LCALTA.19
2096 02:46:16.328618 # ok 293 event_missing.LCALTA.19
2097 02:46:16.329147 # ok 294 event_spurious.LCALTA.19
2098 02:46:16.334163 # ok 295 get_value.LCALTA.18
2099 02:46:16.334692 # # LCALTA.18 TDMOUT_A Lane 0 Volume
2100 02:46:16.339710 # ok 296 name.LCALTA.18
2101 02:46:16.340279 # ok 297 write_default.LCALTA.18
2102 02:46:16.345241 # ok 298 write_valid.LCALTA.18
2103 02:46:16.345765 # ok 299 write_invalid.LCALTA.18
2104 02:46:16.350798 # ok 300 event_missing.LCALTA.18
2105 02:46:16.351324 # ok 301 event_spurious.LCALTA.18
2106 02:46:16.356367 # ok 302 get_value.LCALTA.17
2107 02:46:16.361885 # # LCALTA.17 TDMOUT_B Gain Enable Switch
2108 02:46:16.362421 # ok 303 name.LCALTA.17
2109 02:46:16.362888 # ok 304 write_default.LCALTA.17
2110 02:46:16.367437 # ok 305 write_valid.LCALTA.17
2111 02:46:16.373003 # ok 306 write_invalid.LCALTA.17
2112 02:46:16.373534 # ok 307 event_missing.LCALTA.17
2113 02:46:16.378533 # ok 308 event_spurious.LCALTA.17
2114 02:46:16.379065 # ok 309 get_value.LCALTA.16
2115 02:46:16.384098 # # LCALTA.16 TDMOUT_B Lane 3 Volume
2116 02:46:16.384636 # ok 310 name.LCALTA.16
2117 02:46:16.389626 # ok 311 write_default.LCALTA.16
2118 02:46:16.390155 # ok 312 write_valid.LCALTA.16
2119 02:46:16.395182 # ok 313 write_invalid.LCALTA.16
2120 02:46:16.395715 # ok 314 event_missing.LCALTA.16
2121 02:46:16.400727 # ok 315 event_spurious.LCALTA.16
2122 02:46:16.401253 # ok 316 get_value.LCALTA.15
2123 02:46:16.406274 # # LCALTA.15 TDMOUT_B Lane 2 Volume
2124 02:46:16.406805 # ok 317 name.LCALTA.15
2125 02:46:16.411807 # ok 318 write_default.LCALTA.15
2126 02:46:16.412365 # ok 319 write_valid.LCALTA.15
2127 02:46:16.417359 # ok 320 write_invalid.LCALTA.15
2128 02:46:16.417891 # ok 321 event_missing.LCALTA.15
2129 02:46:16.422940 # ok 322 event_spurious.LCALTA.15
2130 02:46:16.423474 # ok 323 get_value.LCALTA.14
2131 02:46:16.428435 # # LCALTA.14 TDMOUT_B Lane 1 Volume
2132 02:46:16.428968 # ok 324 name.LCALTA.14
2133 02:46:16.433997 # ok 325 write_default.LCALTA.14
2134 02:46:16.434527 # ok 326 write_valid.LCALTA.14
2135 02:46:16.439556 # ok 327 write_invalid.LCALTA.14
2136 02:46:16.440126 # ok 328 event_missing.LCALTA.14
2137 02:46:16.445101 # ok 329 event_spurious.LCALTA.14
2138 02:46:16.445627 # ok 330 get_value.LCALTA.13
2139 02:46:16.450636 # # LCALTA.13 TDMOUT_B Lane 0 Volume
2140 02:46:16.451165 # ok 331 name.LCALTA.13
2141 02:46:16.456204 # ok 332 write_default.LCALTA.13
2142 02:46:16.456736 # ok 333 write_valid.LCALTA.13
2143 02:46:16.461733 # ok 334 write_invalid.LCALTA.13
2144 02:46:16.462261 # ok 335 event_missing.LCALTA.13
2145 02:46:16.467278 # ok 336 event_spurious.LCALTA.13
2146 02:46:16.467808 # ok 337 get_value.LCALTA.12
2147 02:46:16.472898 # # LCALTA.12 TDMOUT_C Gain Enable Switch
2148 02:46:16.473428 # ok 338 name.LCALTA.12
2149 02:46:16.478365 # ok 339 write_default.LCALTA.12
2150 02:46:16.483950 # ok 340 write_valid.LCALTA.12
2151 02:46:16.484507 # ok 341 write_invalid.LCALTA.12
2152 02:46:16.489460 # ok 342 event_missing.LCALTA.12
2153 02:46:16.489992 # ok 343 event_spurious.LCALTA.12
2154 02:46:16.495021 # ok 344 get_value.LCALTA.11
2155 02:46:16.495550 # # LCALTA.11 TDMOUT_C Lane 3 Volume
2156 02:46:16.500554 # ok 345 name.LCALTA.11
2157 02:46:16.501084 # ok 346 write_default.LCALTA.11
2158 02:46:16.506102 # ok 347 write_valid.LCALTA.11
2159 02:46:16.506628 # ok 348 write_invalid.LCALTA.11
2160 02:46:16.511644 # ok 349 event_missing.LCALTA.11
2161 02:46:16.512198 # ok 350 event_spurious.LCALTA.11
2162 02:46:16.517188 # ok 351 get_value.LCALTA.10
2163 02:46:16.517712 # # LCALTA.10 TDMOUT_C Lane 2 Volume
2164 02:46:16.522745 # ok 352 name.LCALTA.10
2165 02:46:16.523275 # ok 353 write_default.LCALTA.10
2166 02:46:16.528305 # ok 354 write_valid.LCALTA.10
2167 02:46:16.528837 # ok 355 write_invalid.LCALTA.10
2168 02:46:16.533913 # ok 356 event_missing.LCALTA.10
2169 02:46:16.534437 # ok 357 event_spurious.LCALTA.10
2170 02:46:16.539388 # ok 358 get_value.LCALTA.9
2171 02:46:16.539909 # # LCALTA.9 TDMOUT_C Lane 1 Volume
2172 02:46:16.544958 # ok 359 name.LCALTA.9
2173 02:46:16.545484 # ok 360 write_default.LCALTA.9
2174 02:46:16.550460 # ok 361 write_valid.LCALTA.9
2175 02:46:16.550991 # ok 362 write_invalid.LCALTA.9
2176 02:46:16.556079 # ok 363 event_missing.LCALTA.9
2177 02:46:16.556606 # ok 364 event_spurious.LCALTA.9
2178 02:46:16.561577 # ok 365 get_value.LCALTA.8
2179 02:46:16.562105 # # LCALTA.8 TDMOUT_C Lane 0 Volume
2180 02:46:16.567095 # ok 366 name.LCALTA.8
2181 02:46:16.567626 # ok 367 write_default.LCALTA.8
2182 02:46:16.572639 # ok 368 write_valid.LCALTA.8
2183 02:46:16.573171 # ok 369 write_invalid.LCALTA.8
2184 02:46:16.578201 # ok 370 event_missing.LCALTA.8
2185 02:46:16.578732 # ok 371 event_spurious.LCALTA.8
2186 02:46:16.583738 # ok 372 get_value.LCALTA.7
2187 02:46:16.584295 # # LCALTA.7 ACODEC Unmute Ramp Switch
2188 02:46:16.589299 # ok 373 name.LCALTA.7
2189 02:46:16.589830 # ok 374 write_default.LCALTA.7
2190 02:46:16.594919 # ok 375 write_valid.LCALTA.7
2191 02:46:16.595451 # ok 376 write_invalid.LCALTA.7
2192 02:46:16.600419 # ok 377 event_missing.LCALTA.7
2193 02:46:16.600947 # ok 378 event_spurious.LCALTA.7
2194 02:46:16.605963 # ok 379 get_value.LCALTA.6
2195 02:46:16.606489 # # LCALTA.6 ACODEC Mute Ramp Switch
2196 02:46:16.611501 # ok 380 name.LCALTA.6
2197 02:46:16.612060 # ok 381 write_default.LCALTA.6
2198 02:46:16.617050 # ok 382 write_valid.LCALTA.6
2199 02:46:16.617578 # ok 383 write_invalid.LCALTA.6
2200 02:46:16.622564 # ok 384 event_missing.LCALTA.6
2201 02:46:16.623085 # ok 385 event_spurious.LCALTA.6
2202 02:46:16.628108 # ok 386 get_value.LCALTA.5
2203 02:46:16.628631 # # LCALTA.5 ACODEC Volume Ramp Switch
2204 02:46:16.633645 # ok 387 name.LCALTA.5
2205 02:46:16.634178 # ok 388 write_default.LCALTA.5
2206 02:46:16.639233 # ok 389 write_valid.LCALTA.5
2207 02:46:16.639767 # ok 390 write_invalid.LCALTA.5
2208 02:46:16.644790 # ok 391 event_missing.LCALTA.5
2209 02:46:16.645317 # ok 392 event_spurious.LCALTA.5
2210 02:46:16.650311 # ok 393 get_value.LCALTA.4
2211 02:46:16.650841 # # LCALTA.4 ACODEC Ramp Rate
2212 02:46:16.655921 # ok 394 name.LCALTA.4
2213 02:46:16.656478 # ok 395 write_default.LCALTA.4
2214 02:46:16.661423 # ok 396 write_valid.LCALTA.4
2215 02:46:16.661951 # ok 397 write_invalid.LCALTA.4
2216 02:46:16.666976 # ok 398 event_missing.LCALTA.4
2217 02:46:16.667500 # ok 399 event_spurious.LCALTA.4
2218 02:46:16.672521 # ok 400 get_value.LCALTA.3
2219 02:46:16.673057 # # LCALTA.3 ACODEC Playback Volume
2220 02:46:16.678067 # ok 401 name.LCALTA.3
2221 02:46:16.678593 # ok 402 write_default.LCALTA.3
2222 02:46:16.683603 # ok 403 write_valid.LCALTA.3
2223 02:46:16.684155 # ok 404 write_invalid.LCALTA.3
2224 02:46:16.689123 # ok 405 event_missing.LCALTA.3
2225 02:46:16.689652 # ok 406 event_spurious.LCALTA.3
2226 02:46:16.694689 # ok 407 get_value.LCALTA.2
2227 02:46:16.695217 # # LCALTA.2 ACODEC Playback Switch
2228 02:46:16.700267 # ok 408 name.LCALTA.2
2229 02:46:16.700799 # ok 409 write_default.LCALTA.2
2230 02:46:16.705810 # ok 410 write_valid.LCALTA.2
2231 02:46:16.706342 # ok 411 write_invalid.LCALTA.2
2232 02:46:16.711333 # ok 412 event_missing.LCALTA.2
2233 02:46:16.711859 # ok 413 event_spurious.LCALTA.2
2234 02:46:16.716936 # ok 414 get_value.LCALTA.1
2235 02:46:16.717462 # # LCALTA.1 ACODEC Playback Channel Mode
2236 02:46:16.722421 # ok 415 name.LCALTA.1
2237 02:46:16.722948 # ok 416 write_default.LCALTA.1
2238 02:46:16.728008 # ok 417 write_valid.LCALTA.1
2239 02:46:16.728538 # ok 418 write_invalid.LCALTA.1
2240 02:46:16.733536 # ok 419 event_missing.LCALTA.1
2241 02:46:16.734061 # ok 420 event_spurious.LCALTA.1
2242 02:46:16.739052 # ok 421 get_value.LCALTA.0
2243 02:46:16.739582 # # LCALTA.0 TOACODEC Lane Select
2244 02:46:16.744593 # ok 422 name.LCALTA.0
2245 02:46:16.745121 # ok 423 write_default.LCALTA.0
2246 02:46:16.750181 # ok 424 write_valid.LCALTA.0
2247 02:46:16.750710 # ok 425 write_invalid.LCALTA.0
2248 02:46:16.755689 # ok 426 event_missing.LCALTA.0
2249 02:46:16.756253 # ok 427 event_spurious.LCALTA.0
2250 02:46:16.761247 # # Totals: pass:416 fail:0 xfail:0 xpass:0 skip:11 error:0
2251 02:46:16.766825 ok 1 selftests: alsa: mixer-test
2252 02:46:16.767357 # timeout set to 45
2253 02:46:16.767812 # selftests: alsa: pcm-test
2254 02:46:16.772345 # TAP version 13
2255 02:46:16.772884 # # Card 0/LCALTA - LC-ALTA (LC-ALTA)
2256 02:46:16.777942 # # LCALTA.0 - fe.dai-link-0 (*)
2257 02:46:16.778472 # # LCALTA.0 - fe.dai-link-1 (*)
2258 02:46:16.783428 # # LCALTA.0 - fe.dai-link-2 (*)
2259 02:46:16.783949 # # LCALTA.0 - fe.dai-link-3 (*)
2260 02:46:16.788988 # # LCALTA.0 - fe.dai-link-4 (*)
2261 02:46:16.789511 # # LCALTA.0 - fe.dai-link-5 (*)
2262 02:46:16.794525 # 1..42
2263 02:46:16.800092 # # default.time1.LCALTA.5.0.CAPTURE - 8kHz mono large periods
2264 02:46:16.800626 # ok 1 # SKIP default.time1.LCALTA.5.0.CAPTURE
2265 02:46:16.805616 # # snd_pcm_hw_params: Invalid argument
2266 02:46:16.811164 # # default.time2.LCALTA.5.0.CAPTURE - 8kHz stereo large periods
2267 02:46:16.816710 # ok 2 # SKIP default.time2.LCALTA.5.0.CAPTURE
2268 02:46:16.817241 # # snd_pcm_hw_params: Invalid argument
2269 02:46:16.822275 # # default.time3.LCALTA.5.0.CAPTURE - 44.1kHz stereo large periods
2270 02:46:16.827832 # ok 3 # SKIP default.time3.LCALTA.5.0.CAPTURE
2271 02:46:16.833348 # # snd_pcm_hw_params: Invalid argument
2272 02:46:16.838951 # # default.time4.LCALTA.5.0.CAPTURE - 48kHz stereo small periods
2273 02:46:16.844434 # ok 4 # SKIP default.time4.LCALTA.5.0.CAPTURE
2274 02:46:16.844957 # # snd_pcm_hw_params: Invalid argument
2275 02:46:16.849991 # # default.time5.LCALTA.5.0.CAPTURE - 48kHz stereo large periods
2276 02:46:16.855539 # ok 5 # SKIP default.time5.LCALTA.5.0.CAPTURE
2277 02:46:16.861079 # # snd_pcm_hw_params: Invalid argument
2278 02:46:16.866644 # # default.time6.LCALTA.5.0.CAPTURE - 48kHz 6 channel large periods
2279 02:46:16.872216 # ok 6 # SKIP default.time6.LCALTA.5.0.CAPTURE
2280 02:46:16.872745 # # snd_pcm_hw_params: Invalid argument
2281 02:46:16.877736 # # default.time7.LCALTA.5.0.CAPTURE - 96kHz stereo large periods
2282 02:46:16.883257 # ok 7 # SKIP default.time7.LCALTA.5.0.CAPTURE
2283 02:46:16.888837 # # snd_pcm_hw_params: Invalid argument
2284 02:46:16.894363 # # default.time1.LCALTA.4.0.CAPTURE - 8kHz mono large periods
2285 02:46:16.894891 # ok 8 # SKIP default.time1.LCALTA.4.0.CAPTURE
2286 02:46:16.899957 # # snd_pcm_hw_params: Invalid argument
2287 02:46:16.905473 # # default.time2.LCALTA.4.0.CAPTURE - 8kHz stereo large periods
2288 02:46:16.910999 # ok 9 # SKIP default.time2.LCALTA.4.0.CAPTURE
2289 02:46:16.911527 # # snd_pcm_hw_params: Invalid argument
2290 02:46:16.922064 # # default.time3.LCALTA.4.0.CAPTURE - 44.1kHz stereo large periods
2291 02:46:16.922595 # ok 10 # SKIP default.time3.LCALTA.4.0.CAPTURE
2292 02:46:16.927651 # # snd_pcm_hw_params: Invalid argument
2293 02:46:16.933212 # # default.time4.LCALTA.4.0.CAPTURE - 48kHz stereo small periods
2294 02:46:16.938718 # ok 11 # SKIP default.time4.LCALTA.4.0.CAPTURE
2295 02:46:16.939243 # # snd_pcm_hw_params: Invalid argument
2296 02:46:16.944294 # # default.time5.LCALTA.4.0.CAPTURE - 48kHz stereo large periods
2297 02:46:16.949840 # ok 12 # SKIP default.time5.LCALTA.4.0.CAPTURE
2298 02:46:16.955378 # # snd_pcm_hw_params: Invalid argument
2299 02:46:16.960965 # # default.time6.LCALTA.4.0.CAPTURE - 48kHz 6 channel large periods
2300 02:46:16.966479 # ok 13 # SKIP default.time6.LCALTA.4.0.CAPTURE
2301 02:46:16.967001 # # snd_pcm_hw_params: Invalid argument
2302 02:46:16.972061 # # default.time7.LCALTA.4.0.CAPTURE - 96kHz stereo large periods
2303 02:46:16.977580 # ok 14 # SKIP default.time7.LCALTA.4.0.CAPTURE
2304 02:46:16.983123 # # snd_pcm_hw_params: Invalid argument
2305 02:46:16.988650 # # default.time1.LCALTA.3.0.CAPTURE - 8kHz mono large periods
2306 02:46:16.994215 # ok 15 # SKIP default.time1.LCALTA.3.0.CAPTURE
2307 02:46:16.994737 # # snd_pcm_hw_params: Invalid argument
2308 02:46:16.999762 # # default.time2.LCALTA.3.0.CAPTURE - 8kHz stereo large periods
2309 02:46:17.005306 # ok 16 # SKIP default.time2.LCALTA.3.0.CAPTURE
2310 02:46:17.010845 # # snd_pcm_hw_params: Invalid argument
2311 02:46:17.016381 # # default.time3.LCALTA.3.0.CAPTURE - 44.1kHz stereo large periods
2312 02:46:17.016908 # ok 17 # SKIP default.time3.LCALTA.3.0.CAPTURE
2313 02:46:17.021970 # # snd_pcm_hw_params: Invalid argument
2314 02:46:17.027492 # # default.time4.LCALTA.3.0.CAPTURE - 48kHz stereo small periods
2315 02:46:17.033031 # ok 18 # SKIP default.time4.LCALTA.3.0.CAPTURE
2316 02:46:17.038593 # # snd_pcm_hw_params: Invalid argument
2317 02:46:17.044234 # # default.time5.LCALTA.3.0.CAPTURE - 48kHz stereo large periods
2318 02:46:17.044934 # ok 19 # SKIP default.time5.LCALTA.3.0.CAPTURE
2319 02:46:17.049606 # # snd_pcm_hw_params: Invalid argument
2320 02:46:17.055150 # # default.time6.LCALTA.3.0.CAPTURE - 48kHz 6 channel large periods
2321 02:46:17.060697 # ok 20 # SKIP default.time6.LCALTA.3.0.CAPTURE
2322 02:46:17.066251 # # snd_pcm_hw_params: Invalid argument
2323 02:46:17.071779 # # default.time7.LCALTA.3.0.CAPTURE - 96kHz stereo large periods
2324 02:46:17.072426 # ok 21 # SKIP default.time7.LCALTA.3.0.CAPTURE
2325 02:46:17.077300 # # snd_pcm_hw_params: Invalid argument
2326 02:46:17.082876 # # default.time1.LCALTA.2.0.PLAYBACK - 8kHz mono large periods
2327 02:46:17.088423 # ok 22 # SKIP default.time1.LCALTA.2.0.PLAYBACK
2328 02:46:17.089011 # # snd_pcm_hw_params: Invalid argument
2329 02:46:17.093975 # # default.time2.LCALTA.2.0.PLAYBACK - 8kHz stereo large periods
2330 02:46:17.099531 # ok 23 # SKIP default.time2.LCALTA.2.0.PLAYBACK
2331 02:46:17.105079 # # snd_pcm_hw_params: Invalid argument
2332 02:46:17.110650 # # default.time3.LCALTA.2.0.PLAYBACK - 44.1kHz stereo large periods
2333 02:46:17.116196 # ok 24 # SKIP default.time3.LCALTA.2.0.PLAYBACK
2334 02:46:17.116785 # # snd_pcm_hw_params: Invalid argument
2335 02:46:17.121693 # # default.time4.LCALTA.2.0.PLAYBACK - 48kHz stereo small periods
2336 02:46:17.127239 # ok 25 # SKIP default.time4.LCALTA.2.0.PLAYBACK
2337 02:46:17.132792 # # snd_pcm_hw_params: Invalid argument
2338 02:46:17.138335 # # default.time5.LCALTA.2.0.PLAYBACK - 48kHz stereo large periods
2339 02:46:17.143887 # ok 26 # SKIP default.time5.LCALTA.2.0.PLAYBACK
2340 02:46:17.144486 # # snd_pcm_hw_params: Invalid argument
2341 02:46:17.149430 # # default.time6.LCALTA.2.0.PLAYBACK - 48kHz 6 channel large periods
2342 02:46:17.154983 # ok 27 # SKIP default.time6.LCALTA.2.0.PLAYBACK
2343 02:46:17.160531 # # snd_pcm_hw_params: Invalid argument
2344 02:46:17.166079 # # default.time7.LCALTA.2.0.PLAYBACK - 96kHz stereo large periods
2345 02:46:17.171623 # ok 28 # SKIP default.time7.LCALTA.2.0.PLAYBACK
2346 02:46:17.172273 # # snd_pcm_hw_params: Invalid argument
2347 02:46:17.177173 # # default.time1.LCALTA.1.0.PLAYBACK - 8kHz mono large periods
2348 02:46:17.182723 # ok 29 # SKIP default.time1.LCALTA.1.0.PLAYBACK
2349 02:46:17.188280 # # snd_pcm_hw_params: Invalid argument
2350 02:46:17.193808 # # default.time2.LCALTA.1.0.PLAYBACK - 8kHz stereo large periods
2351 02:46:17.199363 # ok 30 # SKIP default.time2.LCALTA.1.0.PLAYBACK
2352 02:46:17.199931 # # snd_pcm_hw_params: Invalid argument
2353 02:46:17.204914 # # default.time3.LCALTA.1.0.PLAYBACK - 44.1kHz stereo large periods
2354 02:46:17.210458 # ok 31 # SKIP default.time3.LCALTA.1.0.PLAYBACK
2355 02:46:17.216012 # # snd_pcm_hw_params: Invalid argument
2356 02:46:17.221559 # # default.time4.LCALTA.1.0.PLAYBACK - 48kHz stereo small periods
2357 02:46:17.227096 # ok 32 # SKIP default.time4.LCALTA.1.0.PLAYBACK
2358 02:46:17.227727 # # snd_pcm_hw_params: Invalid argument
2359 02:46:17.232647 # # default.time5.LCALTA.1.0.PLAYBACK - 48kHz stereo large periods
2360 02:46:17.238186 # ok 33 # SKIP default.time5.LCALTA.1.0.PLAYBACK
2361 02:46:17.243736 # # snd_pcm_hw_params: Invalid argument
2362 02:46:17.249291 # # default.time6.LCALTA.1.0.PLAYBACK - 48kHz 6 channel large periods
2363 02:46:17.254836 # ok 34 # SKIP default.time6.LCALTA.1.0.PLAYBACK
2364 02:46:17.255401 # # snd_pcm_hw_params: Invalid argument
2365 02:46:17.260373 # # default.time7.LCALTA.1.0.PLAYBACK - 96kHz stereo large periods
2366 02:46:17.265908 # ok 35 # SKIP default.time7.LCALTA.1.0.PLAYBACK
2367 02:46:17.271458 # # snd_pcm_hw_params: Invalid argument
2368 02:46:17.277022 # # default.time1.LCALTA.0.0.PLAYBACK - 8kHz mono large periods
2369 02:46:17.282582 # ok 36 # SKIP default.time1.LCALTA.0.0.PLAYBACK
2370 02:46:17.283160 # # snd_pcm_hw_params: Invalid argument
2371 02:46:17.288128 # # default.time2.LCALTA.0.0.PLAYBACK - 8kHz stereo large periods
2372 02:46:17.293666 # ok 37 # SKIP default.time2.LCALTA.0.0.PLAYBACK
2373 02:46:17.299198 # # snd_pcm_hw_params: Invalid argument
2374 02:46:17.304749 # # default.time3.LCALTA.0.0.PLAYBACK - 44.1kHz stereo large periods
2375 02:46:17.310306 # ok 38 # SKIP default.time3.LCALTA.0.0.PLAYBACK
2376 02:46:17.310895 # # snd_pcm_hw_params: Invalid argument
2377 02:46:17.315846 # # default.time4.LCALTA.0.0.PLAYBACK - 48kHz stereo small periods
2378 02:46:17.321388 # ok 39 # SKIP default.time4.LCALTA.0.0.PLAYBACK
2379 02:46:17.326923 # # snd_pcm_hw_params: Invalid argument
2380 02:46:17.332472 # # default.time5.LCALTA.0.0.PLAYBACK - 48kHz stereo large periods
2381 02:46:17.338000 # ok 40 # SKIP default.time5.LCALTA.0.0.PLAYBACK
2382 02:46:17.338583 # # snd_pcm_hw_params: Invalid argument
2383 02:46:17.343552 # # default.time6.LCALTA.0.0.PLAYBACK - 48kHz 6 channel large periods
2384 02:46:17.349114 # ok 41 # SKIP default.time6.LCALTA.0.0.PLAYBACK
2385 02:46:17.354658 # # snd_pcm_hw_params: Invalid argument
2386 02:46:17.360220 # # default.time7.LCALTA.0.0.PLAYBACK - 96kHz stereo large periods
2387 02:46:17.365764 # ok 42 # SKIP default.time7.LCALTA.0.0.PLAYBACK
2388 02:46:17.366340 # # snd_pcm_hw_params: Invalid argument
2389 02:46:17.371331 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:42 error:0
2390 02:46:17.376825 ok 2 selftests: alsa: pcm-test
2391 02:46:17.377413 # timeout set to 45
2392 02:46:17.382402 # selftests: alsa: test-pcmtest-driver
2393 02:46:17.382978 # TAP version 13
2394 02:46:17.383524 # 1..5
2395 02:46:17.387960 # # Starting 5 tests from 1 test cases.
2396 02:46:17.388585 # # RUN pcmtest.playback ...
2397 02:46:17.393489 # # SKIP Can't read patterns. Probably, module isn't loaded
2398 02:46:17.399065 # # OK pcmtest.playback
2399 02:46:17.404584 # ok 1 pcmtest.playback # SKIP Can't read patterns. Probably, module isn't loaded
2400 02:46:17.410122 # # RUN pcmtest.capture ...
2401 02:46:17.415676 # # SKIP Can't read patterns. Probably, module isn't loaded
2402 02:46:17.421198 # # OK pcmtest.capture
2403 02:46:17.426769 # ok 2 pcmtest.capture # SKIP Can't read patterns. Probably, module isn't loaded
2404 02:46:17.432344 # # RUN pcmtest.ni_capture ...
2405 02:46:17.437866 # # SKIP Can't read patterns. Probably, module isn't loaded
2406 02:46:17.438458 # # OK pcmtest.ni_capture
2407 02:46:17.448960 # ok 3 pcmtest.ni_capture # SKIP Can't read patterns. Probably, module isn't loaded
2408 02:46:17.449584 # # RUN pcmtest.ni_playback ...
2409 02:46:17.454511 # # SKIP Can't read patterns. Probably, module isn't loaded
2410 02:46:17.460088 # # OK pcmtest.ni_playback
2411 02:46:17.465635 # ok 4 pcmtest.ni_playback # SKIP Can't read patterns. Probably, module isn't loaded
2412 02:46:17.471171 # # RUN pcmtest.reset_ioctl ...
2413 02:46:17.476709 # # SKIP Can't read patterns. Probably, module isn't loaded
2414 02:46:17.482255 # # OK pcmtest.reset_ioctl
2415 02:46:17.487792 # ok 5 pcmtest.reset_ioctl # SKIP Can't read patterns. Probably, module isn't loaded
2416 02:46:17.493333 # # PASSED: 5 / 5 tests passed.
2417 02:46:17.498970 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:5 error:0
2418 02:46:17.499588 ok 3 selftests: alsa: test-pcmtest-driver
2419 02:46:17.504452 # timeout set to 45
2420 02:46:17.505046 # selftests: alsa: utimer-test
2421 02:46:17.505593 # TAP version 13
2422 02:46:17.506132 # 1..2
2423 02:46:17.510027 # # Starting 2 tests from 2 test cases.
2424 02:46:17.515498 # # RUN global.wrong_timers_test ...
2425 02:46:17.521084 # # OK global.wrong_timers_test
2426 02:46:17.521682 # ok 1 global.wrong_timers_test
2427 02:46:17.526616 # # RUN timer_f.utimer ...
2428 02:46:17.532196 # # utimer-test.c:55:utimer:Expected ioctl(timer_dev_fd, SNDRV_TIMER_IOCTL_CREATE, self->utimer_info) (-1) == 0 (0)
2429 02:46:17.537730 # # utimer: Test terminated by assertion
2430 02:46:17.543272 # # FAIL timer_f.utimer
2431 02:46:17.543874 # not ok 2 timer_f.utimer
2432 02:46:17.548819 # # FAILED: 1 / 2 tests passed.
2433 02:46:17.556227 # # Totals: pass:1 fail:1 xfail:0 xpass:0 skip:0 error:0
2434 02:46:17.556828 not ok 4 selftests: alsa: utimer-test # exit=1
2435 02:46:18.069189 alsa_mixer-test_get_value_LCALTA_60 pass
2436 02:46:18.074616 alsa_mixer-test_name_LCALTA_60 pass
2437 02:46:18.075227 alsa_mixer-test_write_default_LCALTA_60 pass
2438 02:46:18.080153 alsa_mixer-test_write_valid_LCALTA_60 pass
2439 02:46:18.085698 alsa_mixer-test_write_invalid_LCALTA_60 pass
2440 02:46:18.091260 alsa_mixer-test_event_missing_LCALTA_60 pass
2441 02:46:18.091859 alsa_mixer-test_event_spurious_LCALTA_60 pass
2442 02:46:18.096788 alsa_mixer-test_get_value_LCALTA_59 pass
2443 02:46:18.102380 alsa_mixer-test_name_LCALTA_59 pass
2444 02:46:18.102971 alsa_mixer-test_write_default_LCALTA_59 pass
2445 02:46:18.107907 alsa_mixer-test_write_valid_LCALTA_59 pass
2446 02:46:18.113443 alsa_mixer-test_write_invalid_LCALTA_59 pass
2447 02:46:18.114048 alsa_mixer-test_event_missing_LCALTA_59 pass
2448 02:46:18.118988 alsa_mixer-test_event_spurious_LCALTA_59 pass
2449 02:46:18.124526 alsa_mixer-test_get_value_LCALTA_58 pass
2450 02:46:18.125124 alsa_mixer-test_name_LCALTA_58 pass
2451 02:46:18.130055 alsa_mixer-test_write_default_LCALTA_58 pass
2452 02:46:18.135598 alsa_mixer-test_write_valid_LCALTA_58 pass
2453 02:46:18.136242 alsa_mixer-test_write_invalid_LCALTA_58 pass
2454 02:46:18.141167 alsa_mixer-test_event_missing_LCALTA_58 pass
2455 02:46:18.146725 alsa_mixer-test_event_spurious_LCALTA_58 pass
2456 02:46:18.152246 alsa_mixer-test_get_value_LCALTA_57 pass
2457 02:46:18.152829 alsa_mixer-test_name_LCALTA_57 pass
2458 02:46:18.157889 alsa_mixer-test_write_default_LCALTA_57 pass
2459 02:46:18.163421 alsa_mixer-test_write_valid_LCALTA_57 pass
2460 02:46:18.164048 alsa_mixer-test_write_invalid_LCALTA_57 pass
2461 02:46:18.168958 alsa_mixer-test_event_missing_LCALTA_57 pass
2462 02:46:18.174519 alsa_mixer-test_event_spurious_LCALTA_57 pass
2463 02:46:18.175106 alsa_mixer-test_get_value_LCALTA_56 pass
2464 02:46:18.180084 alsa_mixer-test_name_LCALTA_56 pass
2465 02:46:18.185608 alsa_mixer-test_write_default_LCALTA_56 pass
2466 02:46:18.186183 alsa_mixer-test_write_valid_LCALTA_56 pass
2467 02:46:18.191148 alsa_mixer-test_write_invalid_LCALTA_56 pass
2468 02:46:18.196714 alsa_mixer-test_event_missing_LCALTA_56 pass
2469 02:46:18.202243 alsa_mixer-test_event_spurious_LCALTA_56 pass
2470 02:46:18.202849 alsa_mixer-test_get_value_LCALTA_55 pass
2471 02:46:18.207808 alsa_mixer-test_name_LCALTA_55 pass
2472 02:46:18.213324 alsa_mixer-test_write_default_LCALTA_55 pass
2473 02:46:18.213911 alsa_mixer-test_write_valid_LCALTA_55 pass
2474 02:46:18.218889 alsa_mixer-test_write_invalid_LCALTA_55 pass
2475 02:46:18.224448 alsa_mixer-test_event_missing_LCALTA_55 pass
2476 02:46:18.225035 alsa_mixer-test_event_spurious_LCALTA_55 pass
2477 02:46:18.230025 alsa_mixer-test_get_value_LCALTA_54 pass
2478 02:46:18.235553 alsa_mixer-test_name_LCALTA_54 pass
2479 02:46:18.236182 alsa_mixer-test_write_default_LCALTA_54 pass
2480 02:46:18.241134 alsa_mixer-test_write_valid_LCALTA_54 pass
2481 02:46:18.246613 alsa_mixer-test_write_invalid_LCALTA_54 pass
2482 02:46:18.247199 alsa_mixer-test_event_missing_LCALTA_54 pass
2483 02:46:18.252214 alsa_mixer-test_event_spurious_LCALTA_54 pass
2484 02:46:18.257711 alsa_mixer-test_get_value_LCALTA_53 pass
2485 02:46:18.258295 alsa_mixer-test_name_LCALTA_53 pass
2486 02:46:18.263241 alsa_mixer-test_write_default_LCALTA_53 pass
2487 02:46:18.268820 alsa_mixer-test_write_valid_LCALTA_53 pass
2488 02:46:18.274363 alsa_mixer-test_write_invalid_LCALTA_53 pass
2489 02:46:18.274953 alsa_mixer-test_event_missing_LCALTA_53 pass
2490 02:46:18.279917 alsa_mixer-test_event_spurious_LCALTA_53 pass
2491 02:46:18.285454 alsa_mixer-test_get_value_LCALTA_52 pass
2492 02:46:18.286042 alsa_mixer-test_name_LCALTA_52 pass
2493 02:46:18.291087 alsa_mixer-test_write_default_LCALTA_52 pass
2494 02:46:18.296568 alsa_mixer-test_write_valid_LCALTA_52 pass
2495 02:46:18.297153 alsa_mixer-test_write_invalid_LCALTA_52 pass
2496 02:46:18.302164 alsa_mixer-test_event_missing_LCALTA_52 pass
2497 02:46:18.307648 alsa_mixer-test_event_spurious_LCALTA_52 pass
2498 02:46:18.308278 alsa_mixer-test_get_value_LCALTA_51 pass
2499 02:46:18.313222 alsa_mixer-test_name_LCALTA_51 pass
2500 02:46:18.318713 alsa_mixer-test_write_default_LCALTA_51 pass
2501 02:46:18.319303 alsa_mixer-test_write_valid_LCALTA_51 pass
2502 02:46:18.324275 alsa_mixer-test_write_invalid_LCALTA_51 pass
2503 02:46:18.329824 alsa_mixer-test_event_missing_LCALTA_51 pass
2504 02:46:18.335367 alsa_mixer-test_event_spurious_LCALTA_51 pass
2505 02:46:18.335958 alsa_mixer-test_get_value_LCALTA_50 pass
2506 02:46:18.340919 alsa_mixer-test_name_LCALTA_50 pass
2507 02:46:18.346461 alsa_mixer-test_write_default_LCALTA_50 pass
2508 02:46:18.347030 alsa_mixer-test_write_valid_LCALTA_50 pass
2509 02:46:18.352116 alsa_mixer-test_write_invalid_LCALTA_50 pass
2510 02:46:18.357560 alsa_mixer-test_event_missing_LCALTA_50 pass
2511 02:46:18.358144 alsa_mixer-test_event_spurious_LCALTA_50 pass
2512 02:46:18.363146 alsa_mixer-test_get_value_LCALTA_49 pass
2513 02:46:18.368639 alsa_mixer-test_name_LCALTA_49 pass
2514 02:46:18.369230 alsa_mixer-test_write_default_LCALTA_49 pass
2515 02:46:18.374243 alsa_mixer-test_write_valid_LCALTA_49 pass
2516 02:46:18.379730 alsa_mixer-test_write_invalid_LCALTA_49 pass
2517 02:46:18.385289 alsa_mixer-test_event_missing_LCALTA_49 pass
2518 02:46:18.385877 alsa_mixer-test_event_spurious_LCALTA_49 pass
2519 02:46:18.390824 alsa_mixer-test_get_value_LCALTA_48 pass
2520 02:46:18.391409 alsa_mixer-test_name_LCALTA_48 pass
2521 02:46:18.396385 alsa_mixer-test_write_default_LCALTA_48 pass
2522 02:46:18.401933 alsa_mixer-test_write_valid_LCALTA_48 pass
2523 02:46:18.407472 alsa_mixer-test_write_invalid_LCALTA_48 pass
2524 02:46:18.408089 alsa_mixer-test_event_missing_LCALTA_48 pass
2525 02:46:18.413114 alsa_mixer-test_event_spurious_LCALTA_48 pass
2526 02:46:18.418555 alsa_mixer-test_get_value_LCALTA_47 pass
2527 02:46:18.419137 alsa_mixer-test_name_LCALTA_47 pass
2528 02:46:18.424186 alsa_mixer-test_write_default_LCALTA_47 pass
2529 02:46:18.429671 alsa_mixer-test_write_valid_LCALTA_47 pass
2530 02:46:18.430271 alsa_mixer-test_write_invalid_LCALTA_47 pass
2531 02:46:18.435234 alsa_mixer-test_event_missing_LCALTA_47 pass
2532 02:46:18.440729 alsa_mixer-test_event_spurious_LCALTA_47 pass
2533 02:46:18.446303 alsa_mixer-test_get_value_LCALTA_46 pass
2534 02:46:18.446889 alsa_mixer-test_name_LCALTA_46 pass
2535 02:46:18.451853 alsa_mixer-test_write_default_LCALTA_46 pass
2536 02:46:18.457400 alsa_mixer-test_write_valid_LCALTA_46 pass
2537 02:46:18.457994 alsa_mixer-test_write_invalid_LCALTA_46 pass
2538 02:46:18.462938 alsa_mixer-test_event_missing_LCALTA_46 pass
2539 02:46:18.468486 alsa_mixer-test_event_spurious_LCALTA_46 pass
2540 02:46:18.469073 alsa_mixer-test_get_value_LCALTA_45 pass
2541 02:46:18.474115 alsa_mixer-test_name_LCALTA_45 pass
2542 02:46:18.479600 alsa_mixer-test_write_default_LCALTA_45 pass
2543 02:46:18.480228 alsa_mixer-test_write_valid_LCALTA_45 pass
2544 02:46:18.485158 alsa_mixer-test_write_invalid_LCALTA_45 pass
2545 02:46:18.490644 alsa_mixer-test_event_missing_LCALTA_45 pass
2546 02:46:18.491225 alsa_mixer-test_event_spurious_LCALTA_45 pass
2547 02:46:18.496243 alsa_mixer-test_get_value_LCALTA_44 pass
2548 02:46:18.501773 alsa_mixer-test_name_LCALTA_44 pass
2549 02:46:18.502363 alsa_mixer-test_write_default_LCALTA_44 pass
2550 02:46:18.507315 alsa_mixer-test_write_valid_LCALTA_44 pass
2551 02:46:18.512855 alsa_mixer-test_write_invalid_LCALTA_44 pass
2552 02:46:18.518411 alsa_mixer-test_event_missing_LCALTA_44 pass
2553 02:46:18.519000 alsa_mixer-test_event_spurious_LCALTA_44 pass
2554 02:46:18.524030 alsa_mixer-test_get_value_LCALTA_43 pass
2555 02:46:18.529506 alsa_mixer-test_name_LCALTA_43 pass
2556 02:46:18.530115 alsa_mixer-test_write_default_LCALTA_43 pass
2557 02:46:18.535127 alsa_mixer-test_write_valid_LCALTA_43 pass
2558 02:46:18.540611 alsa_mixer-test_write_invalid_LCALTA_43 pass
2559 02:46:18.541200 alsa_mixer-test_event_missing_LCALTA_43 pass
2560 02:46:18.546171 alsa_mixer-test_event_spurious_LCALTA_43 pass
2561 02:46:18.551660 alsa_mixer-test_get_value_LCALTA_42 pass
2562 02:46:18.552290 alsa_mixer-test_name_LCALTA_42 pass
2563 02:46:18.557227 alsa_mixer-test_write_default_LCALTA_42 pass
2564 02:46:18.562765 alsa_mixer-test_write_valid_LCALTA_42 pass
2565 02:46:18.563346 alsa_mixer-test_write_invalid_LCALTA_42 pass
2566 02:46:18.568371 alsa_mixer-test_event_missing_LCALTA_42 pass
2567 02:46:18.573887 alsa_mixer-test_event_spurious_LCALTA_42 pass
2568 02:46:18.579407 alsa_mixer-test_get_value_LCALTA_41 pass
2569 02:46:18.580033 alsa_mixer-test_name_LCALTA_41 pass
2570 02:46:18.584990 alsa_mixer-test_write_default_LCALTA_41 pass
2571 02:46:18.590525 alsa_mixer-test_write_valid_LCALTA_41 pass
2572 02:46:18.591106 alsa_mixer-test_write_invalid_LCALTA_41 pass
2573 02:46:18.596161 alsa_mixer-test_event_missing_LCALTA_41 pass
2574 02:46:18.601631 alsa_mixer-test_event_spurious_LCALTA_41 pass
2575 02:46:18.602213 alsa_mixer-test_get_value_LCALTA_40 pass
2576 02:46:18.607168 alsa_mixer-test_name_LCALTA_40 pass
2577 02:46:18.612696 alsa_mixer-test_write_default_LCALTA_40 pass
2578 02:46:18.613277 alsa_mixer-test_write_valid_LCALTA_40 pass
2579 02:46:18.618255 alsa_mixer-test_write_invalid_LCALTA_40 pass
2580 02:46:18.623794 alsa_mixer-test_event_missing_LCALTA_40 pass
2581 02:46:18.629343 alsa_mixer-test_event_spurious_LCALTA_40 pass
2582 02:46:18.629919 alsa_mixer-test_get_value_LCALTA_39 pass
2583 02:46:18.634877 alsa_mixer-test_name_LCALTA_39 pass
2584 02:46:18.640404 alsa_mixer-test_write_default_LCALTA_39 pass
2585 02:46:18.640988 alsa_mixer-test_write_valid_LCALTA_39 pass
2586 02:46:18.646004 alsa_mixer-test_write_invalid_LCALTA_39 pass
2587 02:46:18.651531 alsa_mixer-test_event_missing_LCALTA_39 pass
2588 02:46:18.652151 alsa_mixer-test_event_spurious_LCALTA_39 pass
2589 02:46:18.657149 alsa_mixer-test_get_value_LCALTA_38 pass
2590 02:46:18.662627 alsa_mixer-test_name_LCALTA_38 pass
2591 02:46:18.663207 alsa_mixer-test_write_default_LCALTA_38 pass
2592 02:46:18.668200 alsa_mixer-test_write_valid_LCALTA_38 pass
2593 02:46:18.673738 alsa_mixer-test_write_invalid_LCALTA_38 pass
2594 02:46:18.674310 alsa_mixer-test_event_missing_LCALTA_38 pass
2595 02:46:18.679263 alsa_mixer-test_event_spurious_LCALTA_38 pass
2596 02:46:18.684806 alsa_mixer-test_get_value_LCALTA_37 pass
2597 02:46:18.685395 alsa_mixer-test_name_LCALTA_37 pass
2598 02:46:18.690353 alsa_mixer-test_write_default_LCALTA_37 pass
2599 02:46:18.695889 alsa_mixer-test_write_valid_LCALTA_37 pass
2600 02:46:18.701449 alsa_mixer-test_write_invalid_LCALTA_37 pass
2601 02:46:18.702040 alsa_mixer-test_event_missing_LCALTA_37 pass
2602 02:46:18.707004 alsa_mixer-test_event_spurious_LCALTA_37 pass
2603 02:46:18.712549 alsa_mixer-test_get_value_LCALTA_36 pass
2604 02:46:18.713144 alsa_mixer-test_name_LCALTA_36 pass
2605 02:46:18.718127 alsa_mixer-test_write_default_LCALTA_36 pass
2606 02:46:18.723633 alsa_mixer-test_write_valid_LCALTA_36 pass
2607 02:46:18.724258 alsa_mixer-test_write_invalid_LCALTA_36 pass
2608 02:46:18.729187 alsa_mixer-test_event_missing_LCALTA_36 pass
2609 02:46:18.734716 alsa_mixer-test_event_spurious_LCALTA_36 pass
2610 02:46:18.735298 alsa_mixer-test_get_value_LCALTA_35 pass
2611 02:46:18.740270 alsa_mixer-test_name_LCALTA_35 pass
2612 02:46:18.745830 alsa_mixer-test_write_default_LCALTA_35 pass
2613 02:46:18.746411 alsa_mixer-test_write_valid_LCALTA_35 pass
2614 02:46:18.751365 alsa_mixer-test_write_invalid_LCALTA_35 pass
2615 02:46:18.756909 alsa_mixer-test_event_missing_LCALTA_35 pass
2616 02:46:18.762468 alsa_mixer-test_event_spurious_LCALTA_35 pass
2617 02:46:18.763045 alsa_mixer-test_get_value_LCALTA_34 pass
2618 02:46:18.768040 alsa_mixer-test_name_LCALTA_34 pass
2619 02:46:18.773553 alsa_mixer-test_write_default_LCALTA_34 pass
2620 02:46:18.774147 alsa_mixer-test_write_valid_LCALTA_34 pass
2621 02:46:18.779139 alsa_mixer-test_write_invalid_LCALTA_34 pass
2622 02:46:18.784659 alsa_mixer-test_event_missing_LCALTA_34 pass
2623 02:46:18.785248 alsa_mixer-test_event_spurious_LCALTA_34 pass
2624 02:46:18.790204 alsa_mixer-test_get_value_LCALTA_33 pass
2625 02:46:18.795755 alsa_mixer-test_name_LCALTA_33 pass
2626 02:46:18.796387 alsa_mixer-test_write_default_LCALTA_33 pass
2627 02:46:18.801290 alsa_mixer-test_write_valid_LCALTA_33 pass
2628 02:46:18.806830 alsa_mixer-test_write_invalid_LCALTA_33 pass
2629 02:46:18.812375 alsa_mixer-test_event_missing_LCALTA_33 pass
2630 02:46:18.812974 alsa_mixer-test_event_spurious_LCALTA_33 pass
2631 02:46:18.817939 alsa_mixer-test_get_value_LCALTA_32 pass
2632 02:46:18.818532 alsa_mixer-test_name_LCALTA_32 pass
2633 02:46:18.823466 alsa_mixer-test_write_default_LCALTA_32 pass
2634 02:46:18.829026 alsa_mixer-test_write_valid_LCALTA_32 pass
2635 02:46:18.834574 alsa_mixer-test_write_invalid_LCALTA_32 pass
2636 02:46:18.835146 alsa_mixer-test_event_missing_LCALTA_32 pass
2637 02:46:18.840175 alsa_mixer-test_event_spurious_LCALTA_32 pass
2638 02:46:18.845666 alsa_mixer-test_get_value_LCALTA_31 pass
2639 02:46:18.846254 alsa_mixer-test_name_LCALTA_31 pass
2640 02:46:18.851208 alsa_mixer-test_write_default_LCALTA_31 pass
2641 02:46:18.856731 alsa_mixer-test_write_valid_LCALTA_31 pass
2642 02:46:18.857316 alsa_mixer-test_write_invalid_LCALTA_31 pass
2643 02:46:18.862296 alsa_mixer-test_event_missing_LCALTA_31 pass
2644 02:46:18.867844 alsa_mixer-test_event_spurious_LCALTA_31 pass
2645 02:46:18.873412 alsa_mixer-test_get_value_LCALTA_30 pass
2646 02:46:18.874005 alsa_mixer-test_name_LCALTA_30 pass
2647 02:46:18.878926 alsa_mixer-test_write_default_LCALTA_30 pass
2648 02:46:18.884489 alsa_mixer-test_write_valid_LCALTA_30 pass
2649 02:46:18.885073 alsa_mixer-test_write_invalid_LCALTA_30 pass
2650 02:46:18.890019 alsa_mixer-test_event_missing_LCALTA_30 pass
2651 02:46:18.895558 alsa_mixer-test_event_spurious_LCALTA_30 pass
2652 02:46:18.896189 alsa_mixer-test_get_value_LCALTA_29 pass
2653 02:46:18.901124 alsa_mixer-test_name_LCALTA_29 pass
2654 02:46:18.906679 alsa_mixer-test_write_default_LCALTA_29 pass
2655 02:46:18.907259 alsa_mixer-test_write_valid_LCALTA_29 pass
2656 02:46:18.912237 alsa_mixer-test_write_invalid_LCALTA_29 pass
2657 02:46:18.917778 alsa_mixer-test_event_missing_LCALTA_29 pass
2658 02:46:18.918366 alsa_mixer-test_event_spurious_LCALTA_29 pass
2659 02:46:18.923315 alsa_mixer-test_get_value_LCALTA_28 pass
2660 02:46:18.928869 alsa_mixer-test_name_LCALTA_28 pass
2661 02:46:18.929456 alsa_mixer-test_write_default_LCALTA_28 pass
2662 02:46:18.934403 alsa_mixer-test_write_valid_LCALTA_28 pass
2663 02:46:18.939945 alsa_mixer-test_write_invalid_LCALTA_28 pass
2664 02:46:18.945504 alsa_mixer-test_event_missing_LCALTA_28 pass
2665 02:46:18.946089 alsa_mixer-test_event_spurious_LCALTA_28 pass
2666 02:46:18.951042 alsa_mixer-test_get_value_LCALTA_27 pass
2667 02:46:18.956597 alsa_mixer-test_name_LCALTA_27 pass
2668 02:46:18.957190 alsa_mixer-test_write_default_LCALTA_27 pass
2669 02:46:18.962178 alsa_mixer-test_write_valid_LCALTA_27 pass
2670 02:46:18.967694 alsa_mixer-test_write_invalid_LCALTA_27 pass
2671 02:46:18.968310 alsa_mixer-test_event_missing_LCALTA_27 pass
2672 02:46:18.973238 alsa_mixer-test_event_spurious_LCALTA_27 pass
2673 02:46:18.978783 alsa_mixer-test_get_value_LCALTA_26 pass
2674 02:46:18.979367 alsa_mixer-test_name_LCALTA_26 pass
2675 02:46:18.984328 alsa_mixer-test_write_default_LCALTA_26 skip
2676 02:46:18.989856 alsa_mixer-test_write_valid_LCALTA_26 skip
2677 02:46:18.990438 alsa_mixer-test_write_invalid_LCALTA_26 skip
2678 02:46:18.995424 alsa_mixer-test_event_missing_LCALTA_26 pass
2679 02:46:19.000957 alsa_mixer-test_event_spurious_LCALTA_26 pass
2680 02:46:19.006534 alsa_mixer-test_get_value_LCALTA_25 pass
2681 02:46:19.007116 alsa_mixer-test_name_LCALTA_25 pass
2682 02:46:19.012077 alsa_mixer-test_write_default_LCALTA_25 pass
2683 02:46:19.017597 alsa_mixer-test_write_valid_LCALTA_25 skip
2684 02:46:19.018181 alsa_mixer-test_write_invalid_LCALTA_25 skip
2685 02:46:19.023164 alsa_mixer-test_event_missing_LCALTA_25 pass
2686 02:46:19.028675 alsa_mixer-test_event_spurious_LCALTA_25 pass
2687 02:46:19.029269 alsa_mixer-test_get_value_LCALTA_24 pass
2688 02:46:19.034252 alsa_mixer-test_name_LCALTA_24 pass
2689 02:46:19.039812 alsa_mixer-test_write_default_LCALTA_24 skip
2690 02:46:19.040438 alsa_mixer-test_write_valid_LCALTA_24 skip
2691 02:46:19.045354 alsa_mixer-test_write_invalid_LCALTA_24 skip
2692 02:46:19.050882 alsa_mixer-test_event_missing_LCALTA_24 pass
2693 02:46:19.056444 alsa_mixer-test_event_spurious_LCALTA_24 pass
2694 02:46:19.057036 alsa_mixer-test_get_value_LCALTA_23 pass
2695 02:46:19.062001 alsa_mixer-test_name_LCALTA_23 pass
2696 02:46:19.067544 alsa_mixer-test_write_default_LCALTA_23 skip
2697 02:46:19.068177 alsa_mixer-test_write_valid_LCALTA_23 skip
2698 02:46:19.073083 alsa_mixer-test_write_invalid_LCALTA_23 skip
2699 02:46:19.078597 alsa_mixer-test_event_missing_LCALTA_23 pass
2700 02:46:19.079190 alsa_mixer-test_event_spurious_LCALTA_23 pass
2701 02:46:19.084189 alsa_mixer-test_get_value_LCALTA_22 pass
2702 02:46:19.089721 alsa_mixer-test_name_LCALTA_22 pass
2703 02:46:19.090310 alsa_mixer-test_write_default_LCALTA_22 pass
2704 02:46:19.095256 alsa_mixer-test_write_valid_LCALTA_22 pass
2705 02:46:19.100815 alsa_mixer-test_write_invalid_LCALTA_22 pass
2706 02:46:19.101412 alsa_mixer-test_event_missing_LCALTA_22 pass
2707 02:46:19.106378 alsa_mixer-test_event_spurious_LCALTA_22 pass
2708 02:46:19.111934 alsa_mixer-test_get_value_LCALTA_21 pass
2709 02:46:19.112563 alsa_mixer-test_name_LCALTA_21 pass
2710 02:46:19.117445 alsa_mixer-test_write_default_LCALTA_21 pass
2711 02:46:19.122976 alsa_mixer-test_write_valid_LCALTA_21 pass
2712 02:46:19.128558 alsa_mixer-test_write_invalid_LCALTA_21 pass
2713 02:46:19.129141 alsa_mixer-test_event_missing_LCALTA_21 pass
2714 02:46:19.134092 alsa_mixer-test_event_spurious_LCALTA_21 pass
2715 02:46:19.139603 alsa_mixer-test_get_value_LCALTA_20 pass
2716 02:46:19.140216 alsa_mixer-test_name_LCALTA_20 pass
2717 02:46:19.145192 alsa_mixer-test_write_default_LCALTA_20 pass
2718 02:46:19.150742 alsa_mixer-test_write_valid_LCALTA_20 pass
2719 02:46:19.151335 alsa_mixer-test_write_invalid_LCALTA_20 pass
2720 02:46:19.156281 alsa_mixer-test_event_missing_LCALTA_20 pass
2721 02:46:19.161818 alsa_mixer-test_event_spurious_LCALTA_20 pass
2722 02:46:19.162406 alsa_mixer-test_get_value_LCALTA_19 pass
2723 02:46:19.167372 alsa_mixer-test_name_LCALTA_19 pass
2724 02:46:19.172933 alsa_mixer-test_write_default_LCALTA_19 pass
2725 02:46:19.173521 alsa_mixer-test_write_valid_LCALTA_19 pass
2726 02:46:19.178463 alsa_mixer-test_write_invalid_LCALTA_19 pass
2727 02:46:19.184006 alsa_mixer-test_event_missing_LCALTA_19 pass
2728 02:46:19.189563 alsa_mixer-test_event_spurious_LCALTA_19 pass
2729 02:46:19.190148 alsa_mixer-test_get_value_LCALTA_18 pass
2730 02:46:19.195104 alsa_mixer-test_name_LCALTA_18 pass
2731 02:46:19.200647 alsa_mixer-test_write_default_LCALTA_18 pass
2732 02:46:19.201239 alsa_mixer-test_write_valid_LCALTA_18 pass
2733 02:46:19.206199 alsa_mixer-test_write_invalid_LCALTA_18 pass
2734 02:46:19.211737 alsa_mixer-test_event_missing_LCALTA_18 pass
2735 02:46:19.212364 alsa_mixer-test_event_spurious_LCALTA_18 pass
2736 02:46:19.217293 alsa_mixer-test_get_value_LCALTA_17 pass
2737 02:46:19.222815 alsa_mixer-test_name_LCALTA_17 pass
2738 02:46:19.223407 alsa_mixer-test_write_default_LCALTA_17 pass
2739 02:46:19.228392 alsa_mixer-test_write_valid_LCALTA_17 pass
2740 02:46:19.233922 alsa_mixer-test_write_invalid_LCALTA_17 pass
2741 02:46:19.239453 alsa_mixer-test_event_missing_LCALTA_17 pass
2742 02:46:19.239943 alsa_mixer-test_event_spurious_LCALTA_17 pass
2743 02:46:19.245001 alsa_mixer-test_get_value_LCALTA_16 pass
2744 02:46:19.245476 alsa_mixer-test_name_LCALTA_16 pass
2745 02:46:19.250567 alsa_mixer-test_write_default_LCALTA_16 pass
2746 02:46:19.256100 alsa_mixer-test_write_valid_LCALTA_16 pass
2747 02:46:19.261637 alsa_mixer-test_write_invalid_LCALTA_16 pass
2748 02:46:19.262086 alsa_mixer-test_event_missing_LCALTA_16 pass
2749 02:46:19.267162 alsa_mixer-test_event_spurious_LCALTA_16 pass
2750 02:46:19.272739 alsa_mixer-test_get_value_LCALTA_15 pass
2751 02:46:19.273210 alsa_mixer-test_name_LCALTA_15 pass
2752 02:46:19.278286 alsa_mixer-test_write_default_LCALTA_15 pass
2753 02:46:19.283826 alsa_mixer-test_write_valid_LCALTA_15 pass
2754 02:46:19.284306 alsa_mixer-test_write_invalid_LCALTA_15 pass
2755 02:46:19.289378 alsa_mixer-test_event_missing_LCALTA_15 pass
2756 02:46:19.294912 alsa_mixer-test_event_spurious_LCALTA_15 pass
2757 02:46:19.300454 alsa_mixer-test_get_value_LCALTA_14 pass
2758 02:46:19.300915 alsa_mixer-test_name_LCALTA_14 pass
2759 02:46:19.306049 alsa_mixer-test_write_default_LCALTA_14 pass
2760 02:46:19.311583 alsa_mixer-test_write_valid_LCALTA_14 pass
2761 02:46:19.312076 alsa_mixer-test_write_invalid_LCALTA_14 pass
2762 02:46:19.317204 alsa_mixer-test_event_missing_LCALTA_14 pass
2763 02:46:19.322669 alsa_mixer-test_event_spurious_LCALTA_14 pass
2764 02:46:19.323162 alsa_mixer-test_get_value_LCALTA_13 pass
2765 02:46:19.328216 alsa_mixer-test_name_LCALTA_13 pass
2766 02:46:19.333753 alsa_mixer-test_write_default_LCALTA_13 pass
2767 02:46:19.334215 alsa_mixer-test_write_valid_LCALTA_13 pass
2768 02:46:19.339307 alsa_mixer-test_write_invalid_LCALTA_13 pass
2769 02:46:19.344862 alsa_mixer-test_event_missing_LCALTA_13 pass
2770 02:46:19.345325 alsa_mixer-test_event_spurious_LCALTA_13 pass
2771 02:46:19.350375 alsa_mixer-test_get_value_LCALTA_12 pass
2772 02:46:19.355931 alsa_mixer-test_name_LCALTA_12 pass
2773 02:46:19.356415 alsa_mixer-test_write_default_LCALTA_12 pass
2774 02:46:19.361486 alsa_mixer-test_write_valid_LCALTA_12 pass
2775 02:46:19.367032 alsa_mixer-test_write_invalid_LCALTA_12 pass
2776 02:46:19.372593 alsa_mixer-test_event_missing_LCALTA_12 pass
2777 02:46:19.373055 alsa_mixer-test_event_spurious_LCALTA_12 pass
2778 02:46:19.378194 alsa_mixer-test_get_value_LCALTA_11 pass
2779 02:46:19.383654 alsa_mixer-test_name_LCALTA_11 pass
2780 02:46:19.384136 alsa_mixer-test_write_default_LCALTA_11 pass
2781 02:46:19.389230 alsa_mixer-test_write_valid_LCALTA_11 pass
2782 02:46:19.394783 alsa_mixer-test_write_invalid_LCALTA_11 pass
2783 02:46:19.395236 alsa_mixer-test_event_missing_LCALTA_11 pass
2784 02:46:19.400347 alsa_mixer-test_event_spurious_LCALTA_11 pass
2785 02:46:19.405857 alsa_mixer-test_get_value_LCALTA_10 pass
2786 02:46:19.406307 alsa_mixer-test_name_LCALTA_10 pass
2787 02:46:19.411409 alsa_mixer-test_write_default_LCALTA_10 pass
2788 02:46:19.416980 alsa_mixer-test_write_valid_LCALTA_10 pass
2789 02:46:19.417453 alsa_mixer-test_write_invalid_LCALTA_10 pass
2790 02:46:19.422486 alsa_mixer-test_event_missing_LCALTA_10 pass
2791 02:46:19.428077 alsa_mixer-test_event_spurious_LCALTA_10 pass
2792 02:46:19.433591 alsa_mixer-test_get_value_LCALTA_9 pass
2793 02:46:19.434051 alsa_mixer-test_name_LCALTA_9 pass
2794 02:46:19.439198 alsa_mixer-test_write_default_LCALTA_9 pass
2795 02:46:19.444705 alsa_mixer-test_write_valid_LCALTA_9 pass
2796 02:46:19.445166 alsa_mixer-test_write_invalid_LCALTA_9 pass
2797 02:46:19.450269 alsa_mixer-test_event_missing_LCALTA_9 pass
2798 02:46:19.455767 alsa_mixer-test_event_spurious_LCALTA_9 pass
2799 02:46:19.456245 alsa_mixer-test_get_value_LCALTA_8 pass
2800 02:46:19.461362 alsa_mixer-test_name_LCALTA_8 pass
2801 02:46:19.466866 alsa_mixer-test_write_default_LCALTA_8 pass
2802 02:46:19.467339 alsa_mixer-test_write_valid_LCALTA_8 pass
2803 02:46:19.472425 alsa_mixer-test_write_invalid_LCALTA_8 pass
2804 02:46:19.477984 alsa_mixer-test_event_missing_LCALTA_8 pass
2805 02:46:19.478440 alsa_mixer-test_event_spurious_LCALTA_8 pass
2806 02:46:19.483524 alsa_mixer-test_get_value_LCALTA_7 pass
2807 02:46:19.489051 alsa_mixer-test_name_LCALTA_7 pass
2808 02:46:19.489510 alsa_mixer-test_write_default_LCALTA_7 pass
2809 02:46:19.494597 alsa_mixer-test_write_valid_LCALTA_7 pass
2810 02:46:19.500251 alsa_mixer-test_write_invalid_LCALTA_7 pass
2811 02:46:19.500700 alsa_mixer-test_event_missing_LCALTA_7 pass
2812 02:46:19.505719 alsa_mixer-test_event_spurious_LCALTA_7 pass
2813 02:46:19.511292 alsa_mixer-test_get_value_LCALTA_6 pass
2814 02:46:19.511752 alsa_mixer-test_name_LCALTA_6 pass
2815 02:46:19.516807 alsa_mixer-test_write_default_LCALTA_6 pass
2816 02:46:19.522369 alsa_mixer-test_write_valid_LCALTA_6 pass
2817 02:46:19.522817 alsa_mixer-test_write_invalid_LCALTA_6 pass
2818 02:46:19.527893 alsa_mixer-test_event_missing_LCALTA_6 pass
2819 02:46:19.533439 alsa_mixer-test_event_spurious_LCALTA_6 pass
2820 02:46:19.533895 alsa_mixer-test_get_value_LCALTA_5 pass
2821 02:46:19.538965 alsa_mixer-test_name_LCALTA_5 pass
2822 02:46:19.544503 alsa_mixer-test_write_default_LCALTA_5 pass
2823 02:46:19.544978 alsa_mixer-test_write_valid_LCALTA_5 pass
2824 02:46:19.550083 alsa_mixer-test_write_invalid_LCALTA_5 pass
2825 02:46:19.555622 alsa_mixer-test_event_missing_LCALTA_5 pass
2826 02:46:19.556097 alsa_mixer-test_event_spurious_LCALTA_5 pass
2827 02:46:19.561262 alsa_mixer-test_get_value_LCALTA_4 pass
2828 02:46:19.566705 alsa_mixer-test_name_LCALTA_4 pass
2829 02:46:19.567164 alsa_mixer-test_write_default_LCALTA_4 pass
2830 02:46:19.572291 alsa_mixer-test_write_valid_LCALTA_4 pass
2831 02:46:19.577804 alsa_mixer-test_write_invalid_LCALTA_4 pass
2832 02:46:19.578301 alsa_mixer-test_event_missing_LCALTA_4 pass
2833 02:46:19.583385 alsa_mixer-test_event_spurious_LCALTA_4 pass
2834 02:46:19.588882 alsa_mixer-test_get_value_LCALTA_3 pass
2835 02:46:19.589343 alsa_mixer-test_name_LCALTA_3 pass
2836 02:46:19.594466 alsa_mixer-test_write_default_LCALTA_3 pass
2837 02:46:19.600021 alsa_mixer-test_write_valid_LCALTA_3 pass
2838 02:46:19.600481 alsa_mixer-test_write_invalid_LCALTA_3 pass
2839 02:46:19.605548 alsa_mixer-test_event_missing_LCALTA_3 pass
2840 02:46:19.611096 alsa_mixer-test_event_spurious_LCALTA_3 pass
2841 02:46:19.611551 alsa_mixer-test_get_value_LCALTA_2 pass
2842 02:46:19.616637 alsa_mixer-test_name_LCALTA_2 pass
2843 02:46:19.622270 alsa_mixer-test_write_default_LCALTA_2 pass
2844 02:46:19.622720 alsa_mixer-test_write_valid_LCALTA_2 pass
2845 02:46:19.627703 alsa_mixer-test_write_invalid_LCALTA_2 pass
2846 02:46:19.633315 alsa_mixer-test_event_missing_LCALTA_2 pass
2847 02:46:19.638808 alsa_mixer-test_event_spurious_LCALTA_2 pass
2848 02:46:19.639265 alsa_mixer-test_get_value_LCALTA_1 pass
2849 02:46:19.644377 alsa_mixer-test_name_LCALTA_1 pass
2850 02:46:19.644838 alsa_mixer-test_write_default_LCALTA_1 pass
2851 02:46:19.649922 alsa_mixer-test_write_valid_LCALTA_1 pass
2852 02:46:19.655486 alsa_mixer-test_write_invalid_LCALTA_1 pass
2853 02:46:19.661013 alsa_mixer-test_event_missing_LCALTA_1 pass
2854 02:46:19.661477 alsa_mixer-test_event_spurious_LCALTA_1 pass
2855 02:46:19.666555 alsa_mixer-test_get_value_LCALTA_0 pass
2856 02:46:19.666997 alsa_mixer-test_name_LCALTA_0 pass
2857 02:46:19.672101 alsa_mixer-test_write_default_LCALTA_0 pass
2858 02:46:19.677653 alsa_mixer-test_write_valid_LCALTA_0 pass
2859 02:46:19.683265 alsa_mixer-test_write_invalid_LCALTA_0 pass
2860 02:46:19.683719 alsa_mixer-test_event_missing_LCALTA_0 pass
2861 02:46:19.688768 alsa_mixer-test_event_spurious_LCALTA_0 pass
2862 02:46:19.689222 alsa_mixer-test pass
2863 02:46:19.694288 alsa_pcm-test_default_time1_LCALTA_5_0_CAPTURE skip
2864 02:46:19.699816 alsa_pcm-test_default_time2_LCALTA_5_0_CAPTURE skip
2865 02:46:19.705386 alsa_pcm-test_default_time3_LCALTA_5_0_CAPTURE skip
2866 02:46:19.710932 alsa_pcm-test_default_time4_LCALTA_5_0_CAPTURE skip
2867 02:46:19.711384 alsa_pcm-test_default_time5_LCALTA_5_0_CAPTURE skip
2868 02:46:19.716471 alsa_pcm-test_default_time6_LCALTA_5_0_CAPTURE skip
2869 02:46:19.722027 alsa_pcm-test_default_time7_LCALTA_5_0_CAPTURE skip
2870 02:46:19.727572 alsa_pcm-test_default_time1_LCALTA_4_0_CAPTURE skip
2871 02:46:19.733136 alsa_pcm-test_default_time2_LCALTA_4_0_CAPTURE skip
2872 02:46:19.738651 alsa_pcm-test_default_time3_LCALTA_4_0_CAPTURE skip
2873 02:46:19.739107 alsa_pcm-test_default_time4_LCALTA_4_0_CAPTURE skip
2874 02:46:19.744287 alsa_pcm-test_default_time5_LCALTA_4_0_CAPTURE skip
2875 02:46:19.749750 alsa_pcm-test_default_time6_LCALTA_4_0_CAPTURE skip
2876 02:46:19.755300 alsa_pcm-test_default_time7_LCALTA_4_0_CAPTURE skip
2877 02:46:19.760855 alsa_pcm-test_default_time1_LCALTA_3_0_CAPTURE skip
2878 02:46:19.766406 alsa_pcm-test_default_time2_LCALTA_3_0_CAPTURE skip
2879 02:46:19.766873 alsa_pcm-test_default_time3_LCALTA_3_0_CAPTURE skip
2880 02:46:19.771962 alsa_pcm-test_default_time4_LCALTA_3_0_CAPTURE skip
2881 02:46:19.777490 alsa_pcm-test_default_time5_LCALTA_3_0_CAPTURE skip
2882 02:46:19.783032 alsa_pcm-test_default_time6_LCALTA_3_0_CAPTURE skip
2883 02:46:19.788593 alsa_pcm-test_default_time7_LCALTA_3_0_CAPTURE skip
2884 02:46:19.794166 alsa_pcm-test_default_time1_LCALTA_2_0_PLAYBACK skip
2885 02:46:19.794623 alsa_pcm-test_default_time2_LCALTA_2_0_PLAYBACK skip
2886 02:46:19.799674 alsa_pcm-test_default_time3_LCALTA_2_0_PLAYBACK skip
2887 02:46:19.805301 alsa_pcm-test_default_time4_LCALTA_2_0_PLAYBACK skip
2888 02:46:19.810771 alsa_pcm-test_default_time5_LCALTA_2_0_PLAYBACK skip
2889 02:46:19.816309 alsa_pcm-test_default_time6_LCALTA_2_0_PLAYBACK skip
2890 02:46:19.821863 alsa_pcm-test_default_time7_LCALTA_2_0_PLAYBACK skip
2891 02:46:19.822320 alsa_pcm-test_default_time1_LCALTA_1_0_PLAYBACK skip
2892 02:46:19.827408 alsa_pcm-test_default_time2_LCALTA_1_0_PLAYBACK skip
2893 02:46:19.832953 alsa_pcm-test_default_time3_LCALTA_1_0_PLAYBACK skip
2894 02:46:19.838515 alsa_pcm-test_default_time4_LCALTA_1_0_PLAYBACK skip
2895 02:46:19.844083 alsa_pcm-test_default_time5_LCALTA_1_0_PLAYBACK skip
2896 02:46:19.849600 alsa_pcm-test_default_time6_LCALTA_1_0_PLAYBACK skip
2897 02:46:19.855153 alsa_pcm-test_default_time7_LCALTA_1_0_PLAYBACK skip
2898 02:46:19.855605 alsa_pcm-test_default_time1_LCALTA_0_0_PLAYBACK skip
2899 02:46:19.860665 alsa_pcm-test_default_time2_LCALTA_0_0_PLAYBACK skip
2900 02:46:19.866284 alsa_pcm-test_default_time3_LCALTA_0_0_PLAYBACK skip
2901 02:46:19.871776 alsa_pcm-test_default_time4_LCALTA_0_0_PLAYBACK skip
2902 02:46:19.877341 alsa_pcm-test_default_time5_LCALTA_0_0_PLAYBACK skip
2903 02:46:19.882907 alsa_pcm-test_default_time6_LCALTA_0_0_PLAYBACK skip
2904 02:46:19.883367 alsa_pcm-test_default_time7_LCALTA_0_0_PLAYBACK skip
2905 02:46:19.888420 alsa_pcm-test pass
2906 02:46:19.893951 alsa_test-pcmtest-driver_pcmtest_playback_Can_t_read_patterns_Probably_module_isn_t_loaded skip
2907 02:46:19.905041 alsa_test-pcmtest-driver_pcmtest_capture_Can_t_read_patterns_Probably_module_isn_t_loaded skip
2908 02:46:19.910626 alsa_test-pcmtest-driver_pcmtest_ni_capture_Can_t_read_patterns_Probably_module_isn_t_loaded skip
2909 02:46:19.921711 alsa_test-pcmtest-driver_pcmtest_ni_playback_Can_t_read_patterns_Probably_module_isn_t_loaded skip
2910 02:46:19.927320 alsa_test-pcmtest-driver_pcmtest_reset_ioctl_Can_t_read_patterns_Probably_module_isn_t_loaded skip
2911 02:46:19.932803 alsa_test-pcmtest-driver pass
2912 02:46:19.938386 alsa_utimer-test_global_wrong_timers_test pass
2913 02:46:19.938918 alsa_utimer-test_timer_f_utimer fail
2914 02:46:19.943908 alsa_utimer-test fail
2915 02:46:19.944424 + ../../utils/send-to-lava.sh ./output/result.txt
2916 02:46:19.949431 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-alsa RESULT=pass>
2917 02:46:19.950353 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-alsa RESULT=pass
2919 02:46:19.960584 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_60 RESULT=pass>
2920 02:46:19.961410 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_60 RESULT=pass
2922 02:46:19.966389 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_60 RESULT=pass>
2923 02:46:19.967136 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_60 RESULT=pass
2925 02:46:19.981531 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_60 RESULT=pass>
2926 02:46:19.982338 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_60 RESULT=pass
2928 02:46:20.034876 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_60 RESULT=pass>
2929 02:46:20.035589 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_60 RESULT=pass
2931 02:46:20.093897 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_60 RESULT=pass>
2932 02:46:20.094657 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_60 RESULT=pass
2934 02:46:20.148197 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_60 RESULT=pass>
2935 02:46:20.148892 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_60 RESULT=pass
2937 02:46:20.200460 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_60 RESULT=pass>
2938 02:46:20.201195 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_60 RESULT=pass
2940 02:46:20.251662 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_59 RESULT=pass>
2941 02:46:20.252485 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_59 RESULT=pass
2943 02:46:20.305194 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_59 RESULT=pass>
2944 02:46:20.305930 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_59 RESULT=pass
2946 02:46:20.374067 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_59 RESULT=pass>
2947 02:46:20.374791 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_59 RESULT=pass
2949 02:46:20.421268 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_59 RESULT=pass>
2950 02:46:20.421996 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_59 RESULT=pass
2952 02:46:20.472146 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_59 RESULT=pass>
2953 02:46:20.472889 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_59 RESULT=pass
2955 02:46:20.523552 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_59 RESULT=pass>
2956 02:46:20.524313 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_59 RESULT=pass
2958 02:46:20.579933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_59 RESULT=pass>
2959 02:46:20.580699 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_59 RESULT=pass
2961 02:46:20.636972 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_58 RESULT=pass>
2962 02:46:20.637689 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_58 RESULT=pass
2964 02:46:20.686895 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_58 RESULT=pass>
2965 02:46:20.687615 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_58 RESULT=pass
2967 02:46:20.739910 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_58 RESULT=pass>
2968 02:46:20.740662 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_58 RESULT=pass
2970 02:46:20.796486 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_58 RESULT=pass>
2971 02:46:20.797220 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_58 RESULT=pass
2973 02:46:20.850075 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_58 RESULT=pass>
2974 02:46:20.850798 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_58 RESULT=pass
2976 02:46:20.901391 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_58 RESULT=pass>
2977 02:46:20.902134 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_58 RESULT=pass
2979 02:46:20.954315 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_58 RESULT=pass>
2980 02:46:20.955037 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_58 RESULT=pass
2982 02:46:21.004231 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_57 RESULT=pass>
2983 02:46:21.004958 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_57 RESULT=pass
2985 02:46:21.061462 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_57 RESULT=pass>
2986 02:46:21.062178 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_57 RESULT=pass
2988 02:46:21.114727 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_57 RESULT=pass>
2989 02:46:21.115461 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_57 RESULT=pass
2991 02:46:21.171940 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_57 RESULT=pass>
2992 02:46:21.172688 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_57 RESULT=pass
2994 02:46:21.217849 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_57 RESULT=pass>
2995 02:46:21.218570 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_57 RESULT=pass
2997 02:46:21.272668 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_57 RESULT=pass>
2998 02:46:21.273436 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_57 RESULT=pass
3000 02:46:21.327010 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_57 RESULT=pass>
3001 02:46:21.327740 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_57 RESULT=pass
3003 02:46:21.381681 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_56 RESULT=pass>
3004 02:46:21.382422 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_56 RESULT=pass
3006 02:46:21.428057 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_56 RESULT=pass>
3007 02:46:21.428809 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_56 RESULT=pass
3009 02:46:21.486102 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_56 RESULT=pass>
3010 02:46:21.486873 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_56 RESULT=pass
3012 02:46:21.535132 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_56 RESULT=pass>
3013 02:46:21.535871 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_56 RESULT=pass
3015 02:46:21.581171 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_56 RESULT=pass>
3016 02:46:21.581905 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_56 RESULT=pass
3018 02:46:21.640803 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_56 RESULT=pass>
3019 02:46:21.641663 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_56 RESULT=pass
3021 02:46:21.692340 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_56 RESULT=pass>
3022 02:46:21.693340 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_56 RESULT=pass
3024 02:46:21.742675 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_55 RESULT=pass>
3025 02:46:21.743658 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_55 RESULT=pass
3027 02:46:21.796787 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_55 RESULT=pass>
3028 02:46:21.797739 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_55 RESULT=pass
3030 02:46:21.850008 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_55 RESULT=pass>
3031 02:46:21.850979 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_55 RESULT=pass
3033 02:46:21.910948 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_55 RESULT=pass>
3034 02:46:21.911929 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_55 RESULT=pass
3036 02:46:21.961280 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_55 RESULT=pass>
3037 02:46:21.962252 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_55 RESULT=pass
3039 02:46:22.020045 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_55 RESULT=pass>
3040 02:46:22.021053 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_55 RESULT=pass
3042 02:46:22.071373 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_55 RESULT=pass>
3043 02:46:22.072415 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_55 RESULT=pass
3045 02:46:22.131119 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_54 RESULT=pass>
3046 02:46:22.132112 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_54 RESULT=pass
3048 02:46:22.187900 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_54 RESULT=pass>
3049 02:46:22.188747 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_54 RESULT=pass
3051 02:46:22.242166 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_54 RESULT=pass>
3052 02:46:22.243006 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_54 RESULT=pass
3054 02:46:22.306190 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_54 RESULT=pass>
3055 02:46:22.307066 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_54 RESULT=pass
3057 02:46:22.362341 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_54 RESULT=pass>
3058 02:46:22.363319 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_54 RESULT=pass
3060 02:46:22.426430 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_54 RESULT=pass>
3061 02:46:22.427426 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_54 RESULT=pass
3063 02:46:22.481442 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_54 RESULT=pass>
3064 02:46:22.482397 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_54 RESULT=pass
3066 02:46:22.533875 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_53 RESULT=pass>
3067 02:46:22.534858 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_53 RESULT=pass
3069 02:46:22.586600 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_53 RESULT=pass>
3070 02:46:22.587572 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_53 RESULT=pass
3072 02:46:22.639804 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_53 RESULT=pass>
3073 02:46:22.640830 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_53 RESULT=pass
3075 02:46:22.701187 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_53 RESULT=pass>
3076 02:46:22.702151 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_53 RESULT=pass
3078 02:46:22.765155 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_53 RESULT=pass>
3079 02:46:22.766137 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_53 RESULT=pass
3081 02:46:22.822040 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_53 RESULT=pass>
3082 02:46:22.822857 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_53 RESULT=pass
3084 02:46:22.879561 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_53 RESULT=pass>
3085 02:46:22.880385 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_53 RESULT=pass
3087 02:46:22.930795 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_52 RESULT=pass>
3088 02:46:22.931602 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_52 RESULT=pass
3090 02:46:22.986842 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_52 RESULT=pass>
3091 02:46:22.987646 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_52 RESULT=pass
3093 02:46:23.042089 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_52 RESULT=pass>
3094 02:46:23.042879 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_52 RESULT=pass
3096 02:46:23.097974 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_52 RESULT=pass>
3097 02:46:23.098767 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_52 RESULT=pass
3099 02:46:23.148039 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_52 RESULT=pass>
3100 02:46:23.148839 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_52 RESULT=pass
3102 02:46:23.206025 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_52 RESULT=pass>
3103 02:46:23.206809 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_52 RESULT=pass
3105 02:46:23.257982 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_52 RESULT=pass>
3106 02:46:23.258762 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_52 RESULT=pass
3108 02:46:23.314319 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_51 RESULT=pass>
3109 02:46:23.315116 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_51 RESULT=pass
3111 02:46:23.366281 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_51 RESULT=pass>
3112 02:46:23.367072 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_51 RESULT=pass
3114 02:46:23.418071 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_51 RESULT=pass>
3115 02:46:23.418916 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_51 RESULT=pass
3117 02:46:23.475397 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_51 RESULT=pass>
3118 02:46:23.476172 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_51 RESULT=pass
3120 02:46:23.527024 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_51 RESULT=pass>
3121 02:46:23.527761 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_51 RESULT=pass
3123 02:46:23.584654 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_51 RESULT=pass>
3124 02:46:23.585394 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_51 RESULT=pass
3126 02:46:23.644522 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_51 RESULT=pass>
3127 02:46:23.645249 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_51 RESULT=pass
3129 02:46:23.699640 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_50 RESULT=pass>
3130 02:46:23.700404 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_50 RESULT=pass
3132 02:46:23.756192 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_50 RESULT=pass>
3133 02:46:23.756920 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_50 RESULT=pass
3135 02:46:23.801434 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_50 RESULT=pass>
3136 02:46:23.802168 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_50 RESULT=pass
3138 02:46:23.856494 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_50 RESULT=pass>
3139 02:46:23.857213 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_50 RESULT=pass
3141 02:46:23.902523 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_50 RESULT=pass>
3142 02:46:23.903249 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_50 RESULT=pass
3144 02:46:23.951751 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_50 RESULT=pass>
3145 02:46:23.952527 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_50 RESULT=pass
3147 02:46:24.011291 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_50 RESULT=pass>
3148 02:46:24.012096 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_50 RESULT=pass
3150 02:46:24.066817 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_49 RESULT=pass>
3151 02:46:24.067582 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_49 RESULT=pass
3153 02:46:24.117724 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_49 RESULT=pass>
3154 02:46:24.118451 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_49 RESULT=pass
3156 02:46:24.174537 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_49 RESULT=pass>
3157 02:46:24.175254 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_49 RESULT=pass
3159 02:46:24.218290 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_49 RESULT=pass>
3160 02:46:24.219005 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_49 RESULT=pass
3162 02:46:24.279150 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_49 RESULT=pass>
3163 02:46:24.279871 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_49 RESULT=pass
3165 02:46:24.329691 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_49 RESULT=pass>
3166 02:46:24.330423 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_49 RESULT=pass
3168 02:46:24.385171 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_49 RESULT=pass>
3169 02:46:24.385896 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_49 RESULT=pass
3171 02:46:24.429230 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_48 RESULT=pass>
3172 02:46:24.429935 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_48 RESULT=pass
3174 02:46:24.483121 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_48 RESULT=pass>
3175 02:46:24.483857 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_48 RESULT=pass
3177 02:46:24.543063 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_48 RESULT=pass>
3178 02:46:24.543779 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_48 RESULT=pass
3180 02:46:24.589136 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_48 RESULT=pass>
3181 02:46:24.589850 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_48 RESULT=pass
3183 02:46:24.640474 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_48 RESULT=pass>
3184 02:46:24.641183 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_48 RESULT=pass
3186 02:46:24.691794 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_48 RESULT=pass>
3187 02:46:24.692558 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_48 RESULT=pass
3189 02:46:24.743816 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_48 RESULT=pass>
3190 02:46:24.744541 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_48 RESULT=pass
3192 02:46:24.797837 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_47 RESULT=pass>
3193 02:46:24.798565 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_47 RESULT=pass
3195 02:46:24.858908 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_47 RESULT=pass>
3196 02:46:24.859623 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_47 RESULT=pass
3198 02:46:24.909645 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_47 RESULT=pass>
3199 02:46:24.910453 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_47 RESULT=pass
3201 02:46:24.965890 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_47 RESULT=pass>
3202 02:46:24.966661 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_47 RESULT=pass
3204 02:46:25.015601 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_47 RESULT=pass>
3205 02:46:25.016393 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_47 RESULT=pass
3207 02:46:25.072602 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_47 RESULT=pass>
3208 02:46:25.073325 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_47 RESULT=pass
3210 02:46:25.124620 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_47 RESULT=pass>
3211 02:46:25.125328 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_47 RESULT=pass
3213 02:46:25.180215 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_46 RESULT=pass>
3214 02:46:25.180909 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_46 RESULT=pass
3216 02:46:25.224661 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_46 RESULT=pass>
3217 02:46:25.225340 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_46 RESULT=pass
3219 02:46:25.281375 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_46 RESULT=pass>
3220 02:46:25.282141 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_46 RESULT=pass
3222 02:46:25.332672 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_46 RESULT=pass>
3223 02:46:25.333393 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_46 RESULT=pass
3225 02:46:25.382697 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_46 RESULT=pass>
3226 02:46:25.383418 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_46 RESULT=pass
3228 02:46:25.438080 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_46 RESULT=pass>
3229 02:46:25.438802 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_46 RESULT=pass
3231 02:46:25.493949 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_46 RESULT=pass>
3232 02:46:25.494716 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_46 RESULT=pass
3234 02:46:25.549592 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_45 RESULT=pass>
3235 02:46:25.550335 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_45 RESULT=pass
3237 02:46:25.607793 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_45 RESULT=pass>
3238 02:46:25.608757 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_45 RESULT=pass
3240 02:46:25.654807 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_45 RESULT=pass>
3241 02:46:25.655563 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_45 RESULT=pass
3243 02:46:25.705871 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_45 RESULT=pass>
3244 02:46:25.706595 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_45 RESULT=pass
3246 02:46:25.764252 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_45 RESULT=pass>
3247 02:46:25.764965 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_45 RESULT=pass
3249 02:46:25.824859 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_45 RESULT=pass>
3250 02:46:25.825575 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_45 RESULT=pass
3252 02:46:25.882670 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_45 RESULT=pass>
3253 02:46:25.883383 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_45 RESULT=pass
3255 02:46:25.932648 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_44 RESULT=pass>
3256 02:46:25.933367 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_44 RESULT=pass
3258 02:46:25.986054 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_44 RESULT=pass>
3259 02:46:25.986796 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_44 RESULT=pass
3261 02:46:26.040740 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_44 RESULT=pass>
3262 02:46:26.041456 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_44 RESULT=pass
3264 02:46:26.092921 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_44 RESULT=pass>
3265 02:46:26.093642 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_44 RESULT=pass
3267 02:46:26.143456 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_44 RESULT=pass>
3268 02:46:26.144172 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_44 RESULT=pass
3270 02:46:26.195116 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_44 RESULT=pass>
3271 02:46:26.195818 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_44 RESULT=pass
3273 02:46:26.239864 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_44 RESULT=pass>
3274 02:46:26.240661 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_44 RESULT=pass
3276 02:46:26.311852 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_43 RESULT=pass>
3277 02:46:26.313148 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_43 RESULT=pass
3279 02:46:26.373255 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_43 RESULT=pass>
3280 02:46:26.374155 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_43 RESULT=pass
3282 02:46:26.426024 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_43 RESULT=pass>
3283 02:46:26.426801 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_43 RESULT=pass
3285 02:46:26.478176 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_43 RESULT=pass>
3286 02:46:26.478913 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_43 RESULT=pass
3288 02:46:26.538108 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_43 RESULT=pass>
3289 02:46:26.538859 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_43 RESULT=pass
3291 02:46:26.600951 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_43 RESULT=pass>
3292 02:46:26.601668 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_43 RESULT=pass
3294 02:46:26.652947 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_43 RESULT=pass>
3295 02:46:26.653648 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_43 RESULT=pass
3297 02:46:26.710401 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_42 RESULT=pass>
3298 02:46:26.711098 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_42 RESULT=pass
3300 02:46:26.765628 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_42 RESULT=pass>
3301 02:46:26.766333 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_42 RESULT=pass
3303 02:46:26.821650 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_42 RESULT=pass>
3304 02:46:26.822358 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_42 RESULT=pass
3306 02:46:26.877266 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_42 RESULT=pass>
3307 02:46:26.877961 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_42 RESULT=pass
3309 02:46:26.935272 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_42 RESULT=pass>
3310 02:46:26.935969 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_42 RESULT=pass
3312 02:46:26.985890 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_42 RESULT=pass>
3313 02:46:26.986584 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_42 RESULT=pass
3315 02:46:27.033895 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_42 RESULT=pass>
3316 02:46:27.034601 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_42 RESULT=pass
3318 02:46:27.079312 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_41 RESULT=pass>
3319 02:46:27.080053 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_41 RESULT=pass
3321 02:46:27.138257 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_41 RESULT=pass>
3322 02:46:27.138962 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_41 RESULT=pass
3324 02:46:27.192438 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_41 RESULT=pass>
3325 02:46:27.193150 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_41 RESULT=pass
3327 02:46:27.248121 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_41 RESULT=pass>
3328 02:46:27.248821 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_41 RESULT=pass
3330 02:46:27.302749 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_41 RESULT=pass>
3331 02:46:27.303472 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_41 RESULT=pass
3333 02:46:27.348648 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_41 RESULT=pass>
3334 02:46:27.349353 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_41 RESULT=pass
3336 02:46:27.405752 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_41 RESULT=pass>
3337 02:46:27.406456 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_41 RESULT=pass
3339 02:46:27.457788 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_40 RESULT=pass>
3340 02:46:27.458496 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_40 RESULT=pass
3342 02:46:27.517062 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_40 RESULT=pass>
3343 02:46:27.517912 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_40 RESULT=pass
3345 02:46:27.573330 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_40 RESULT=pass>
3346 02:46:27.574064 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_40 RESULT=pass
3348 02:46:27.626080 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_40 RESULT=pass>
3349 02:46:27.626800 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_40 RESULT=pass
3351 02:46:27.684738 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_40 RESULT=pass>
3352 02:46:27.685447 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_40 RESULT=pass
3354 02:46:27.733360 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_40 RESULT=pass>
3355 02:46:27.734062 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_40 RESULT=pass
3357 02:46:27.785985 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_40 RESULT=pass>
3358 02:46:27.786716 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_40 RESULT=pass
3360 02:46:27.837967 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_39 RESULT=pass>
3361 02:46:27.838668 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_39 RESULT=pass
3363 02:46:27.891891 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_39 RESULT=pass>
3364 02:46:27.892633 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_39 RESULT=pass
3366 02:46:27.945587 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_39 RESULT=pass>
3367 02:46:27.946289 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_39 RESULT=pass
3369 02:46:27.997668 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_39 RESULT=pass>
3370 02:46:27.998366 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_39 RESULT=pass
3372 02:46:28.047250 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_39 RESULT=pass>
3373 02:46:28.047962 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_39 RESULT=pass
3375 02:46:28.100495 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_39 RESULT=pass>
3376 02:46:28.101198 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_39 RESULT=pass
3378 02:46:28.159208 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_39 RESULT=pass>
3379 02:46:28.159900 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_39 RESULT=pass
3381 02:46:28.210078 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_38 RESULT=pass>
3382 02:46:28.210765 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_38 RESULT=pass
3384 02:46:28.271844 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_38 RESULT=pass>
3385 02:46:28.272574 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_38 RESULT=pass
3387 02:46:28.329744 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_38 RESULT=pass>
3388 02:46:28.330466 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_38 RESULT=pass
3390 02:46:28.386855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_38 RESULT=pass>
3391 02:46:28.387543 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_38 RESULT=pass
3393 02:46:28.446340 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_38 RESULT=pass>
3394 02:46:28.447079 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_38 RESULT=pass
3396 02:46:28.498460 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_38 RESULT=pass>
3397 02:46:28.499150 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_38 RESULT=pass
3399 02:46:28.554507 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_38 RESULT=pass>
3400 02:46:28.555204 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_38 RESULT=pass
3402 02:46:28.612469 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_37 RESULT=pass>
3403 02:46:28.613168 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_37 RESULT=pass
3405 02:46:28.670499 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_37 RESULT=pass>
3406 02:46:28.671192 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_37 RESULT=pass
3408 02:46:28.724765 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_37 RESULT=pass>
3409 02:46:28.725455 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_37 RESULT=pass
3411 02:46:28.776800 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_37 RESULT=pass>
3412 02:46:28.777500 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_37 RESULT=pass
3414 02:46:28.834418 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_37 RESULT=pass>
3415 02:46:28.835118 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_37 RESULT=pass
3417 02:46:28.889194 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_37 RESULT=pass>
3418 02:46:28.889889 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_37 RESULT=pass
3420 02:46:28.948667 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_37 RESULT=pass>
3421 02:46:28.949354 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_37 RESULT=pass
3423 02:46:28.999732 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_36 RESULT=pass>
3424 02:46:29.000466 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_36 RESULT=pass
3426 02:46:29.054449 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_36 RESULT=pass>
3427 02:46:29.055168 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_36 RESULT=pass
3429 02:46:29.112100 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_36 RESULT=pass>
3430 02:46:29.112806 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_36 RESULT=pass
3432 02:46:29.168748 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_36 RESULT=pass>
3433 02:46:29.169442 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_36 RESULT=pass
3435 02:46:29.226939 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_36 RESULT=pass>
3436 02:46:29.227634 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_36 RESULT=pass
3438 02:46:29.278115 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_36 RESULT=pass>
3439 02:46:29.278805 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_36 RESULT=pass
3441 02:46:29.331361 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_36 RESULT=pass>
3442 02:46:29.332077 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_36 RESULT=pass
3444 02:46:29.380840 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_35 RESULT=pass>
3445 02:46:29.381533 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_35 RESULT=pass
3447 02:46:29.435799 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_35 RESULT=pass>
3448 02:46:29.436542 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_35 RESULT=pass
3450 02:46:29.482985 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_35 RESULT=pass>
3451 02:46:29.483690 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_35 RESULT=pass
3453 02:46:29.533937 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_35 RESULT=pass>
3454 02:46:29.534650 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_35 RESULT=pass
3456 02:46:29.585618 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_35 RESULT=pass>
3457 02:46:29.586330 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_35 RESULT=pass
3459 02:46:29.638227 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_35 RESULT=pass>
3460 02:46:29.638915 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_35 RESULT=pass
3462 02:46:29.693856 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_35 RESULT=pass>
3463 02:46:29.694545 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_35 RESULT=pass
3465 02:46:29.743445 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_34 RESULT=pass>
3466 02:46:29.744137 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_34 RESULT=pass
3468 02:46:29.801802 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_34 RESULT=pass>
3469 02:46:29.802496 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_34 RESULT=pass
3471 02:46:29.847130 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_34 RESULT=pass>
3472 02:46:29.847813 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_34 RESULT=pass
3474 02:46:29.903295 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_34 RESULT=pass>
3475 02:46:29.904000 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_34 RESULT=pass
3477 02:46:29.958402 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_34 RESULT=pass>
3478 02:46:29.959101 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_34 RESULT=pass
3480 02:46:30.023914 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_34 RESULT=pass>
3481 02:46:30.024641 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_34 RESULT=pass
3483 02:46:30.077545 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_34 RESULT=pass>
3484 02:46:30.078292 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_34 RESULT=pass
3486 02:46:30.122191 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_33 RESULT=pass>
3487 02:46:30.122871 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_33 RESULT=pass
3489 02:46:30.168568 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_33 RESULT=pass>
3490 02:46:30.169237 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_33 RESULT=pass
3492 02:46:30.215950 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_33 RESULT=pass>
3493 02:46:30.216642 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_33 RESULT=pass
3495 02:46:30.264689 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_33 RESULT=pass>
3496 02:46:30.265356 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_33 RESULT=pass
3498 02:46:30.319699 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_33 RESULT=pass>
3499 02:46:30.320487 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_33 RESULT=pass
3501 02:46:30.370958 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_33 RESULT=pass>
3502 02:46:30.371664 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_33 RESULT=pass
3504 02:46:30.422105 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_33 RESULT=pass>
3505 02:46:30.422802 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_33 RESULT=pass
3507 02:46:30.478157 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_32 RESULT=pass>
3508 02:46:30.478862 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_32 RESULT=pass
3510 02:46:30.528487 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_32 RESULT=pass>
3511 02:46:30.529197 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_32 RESULT=pass
3513 02:46:30.585397 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_32 RESULT=pass>
3514 02:46:30.586100 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_32 RESULT=pass
3516 02:46:30.644072 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_32 RESULT=pass>
3517 02:46:30.644760 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_32 RESULT=pass
3519 02:46:30.695152 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_32 RESULT=pass>
3520 02:46:30.695842 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_32 RESULT=pass
3522 02:46:30.752004 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_32 RESULT=pass>
3523 02:46:30.752696 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_32 RESULT=pass
3525 02:46:30.804348 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_32 RESULT=pass>
3526 02:46:30.805046 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_32 RESULT=pass
3528 02:46:30.853974 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_31 RESULT=pass>
3529 02:46:30.854667 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_31 RESULT=pass
3531 02:46:30.903506 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_31 RESULT=pass>
3532 02:46:30.904197 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_31 RESULT=pass
3534 02:46:30.952493 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_31 RESULT=pass>
3535 02:46:30.953179 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_31 RESULT=pass
3537 02:46:31.006265 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_31 RESULT=pass>
3538 02:46:31.006953 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_31 RESULT=pass
3540 02:46:31.051299 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_31 RESULT=pass>
3541 02:46:31.052012 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_31 RESULT=pass
3543 02:46:31.101726 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_31 RESULT=pass>
3544 02:46:31.102448 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_31 RESULT=pass
3546 02:46:31.154784 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_31 RESULT=pass>
3547 02:46:31.155489 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_31 RESULT=pass
3549 02:46:31.204613 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_30 RESULT=pass>
3550 02:46:31.205305 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_30 RESULT=pass
3552 02:46:31.261133 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_30 RESULT=pass>
3553 02:46:31.261822 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_30 RESULT=pass
3555 02:46:31.310184 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_30 RESULT=pass>
3556 02:46:31.310889 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_30 RESULT=pass
3558 02:46:31.367279 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_30 RESULT=pass>
3559 02:46:31.367971 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_30 RESULT=pass
3561 02:46:31.426918 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_30 RESULT=pass>
3562 02:46:31.427608 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_30 RESULT=pass
3564 02:46:31.480640 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_30 RESULT=pass>
3565 02:46:31.481338 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_30 RESULT=pass
3567 02:46:31.534187 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_30 RESULT=pass>
3568 02:46:31.534898 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_30 RESULT=pass
3570 02:46:31.591137 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_29 RESULT=pass>
3571 02:46:31.591837 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_29 RESULT=pass
3573 02:46:31.648506 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_29 RESULT=pass>
3574 02:46:31.649380 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_29 RESULT=pass
3576 02:46:31.705442 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_29 RESULT=pass>
3577 02:46:31.706257 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_29 RESULT=pass
3579 02:46:31.763441 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_29 RESULT=pass>
3580 02:46:31.764152 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_29 RESULT=pass
3582 02:46:31.814923 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_29 RESULT=pass>
3583 02:46:31.815623 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_29 RESULT=pass
3585 02:46:31.861383 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_29 RESULT=pass>
3586 02:46:31.862081 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_29 RESULT=pass
3588 02:46:31.920315 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_29 RESULT=pass>
3589 02:46:31.921009 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_29 RESULT=pass
3591 02:46:31.972203 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_28 RESULT=pass>
3592 02:46:31.972889 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_28 RESULT=pass
3594 02:46:32.025349 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_28 RESULT=pass>
3595 02:46:32.026043 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_28 RESULT=pass
3597 02:46:32.075142 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_28 RESULT=pass>
3598 02:46:32.075827 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_28 RESULT=pass
3600 02:46:32.129920 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_28 RESULT=pass>
3601 02:46:32.130638 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_28 RESULT=pass
3603 02:46:32.194013 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_28 RESULT=pass>
3604 02:46:32.194703 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_28 RESULT=pass
3606 02:46:32.253834 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_28 RESULT=pass>
3607 02:46:32.254521 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_28 RESULT=pass
3609 02:46:32.307478 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_28 RESULT=pass>
3610 02:46:32.308181 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_28 RESULT=pass
3612 02:46:32.361197 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_27 RESULT=pass>
3613 02:46:32.361914 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_27 RESULT=pass
3615 02:46:32.418564 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_27 RESULT=pass>
3616 02:46:32.419265 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_27 RESULT=pass
3618 02:46:32.470624 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_27 RESULT=pass>
3619 02:46:32.471327 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_27 RESULT=pass
3621 02:46:32.529722 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_27 RESULT=pass>
3622 02:46:32.530420 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_27 RESULT=pass
3624 02:46:32.581427 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_27 RESULT=pass>
3625 02:46:32.582127 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_27 RESULT=pass
3627 02:46:32.636066 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_27 RESULT=pass>
3628 02:46:32.636759 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_27 RESULT=pass
3630 02:46:32.691237 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_27 RESULT=pass>
3631 02:46:32.691923 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_27 RESULT=pass
3633 02:46:32.741515 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_26 RESULT=pass>
3634 02:46:32.742207 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_26 RESULT=pass
3636 02:46:32.789616 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_26 RESULT=pass>
3637 02:46:32.790320 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_26 RESULT=pass
3639 02:46:32.844075 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_26 RESULT=skip>
3640 02:46:32.844767 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_26 RESULT=skip
3642 02:46:32.890138 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_26 RESULT=skip>
3643 02:46:32.890834 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_26 RESULT=skip
3645 02:46:32.935627 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_26 RESULT=skip>
3646 02:46:32.936352 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_26 RESULT=skip
3648 02:46:32.989415 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_26 RESULT=pass>
3649 02:46:32.990103 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_26 RESULT=pass
3651 02:46:33.046992 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_26 RESULT=pass>
3652 02:46:33.047680 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_26 RESULT=pass
3654 02:46:33.092465 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_25 RESULT=pass>
3655 02:46:33.093166 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_25 RESULT=pass
3657 02:46:33.144901 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_25 RESULT=pass>
3658 02:46:33.145611 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_25 RESULT=pass
3660 02:46:33.197503 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_25 RESULT=pass>
3661 02:46:33.198193 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_25 RESULT=pass
3663 02:46:33.246381 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_25 RESULT=skip>
3664 02:46:33.247100 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_25 RESULT=skip
3666 02:46:33.296227 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_25 RESULT=skip>
3667 02:46:33.296940 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_25 RESULT=skip
3669 02:46:33.353078 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_25 RESULT=pass>
3670 02:46:33.353774 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_25 RESULT=pass
3672 02:46:33.400169 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_25 RESULT=pass>
3673 02:46:33.400867 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_25 RESULT=pass
3675 02:46:33.453825 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_24 RESULT=pass>
3676 02:46:33.454514 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_24 RESULT=pass
3678 02:46:33.504801 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_24 RESULT=pass>
3679 02:46:33.505498 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_24 RESULT=pass
3681 02:46:33.564813 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_24 RESULT=skip>
3682 02:46:33.565522 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_24 RESULT=skip
3684 02:46:33.615409 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_24 RESULT=skip>
3685 02:46:33.616111 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_24 RESULT=skip
3687 02:46:33.669532 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_24 RESULT=skip>
3688 02:46:33.670238 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_24 RESULT=skip
3690 02:46:33.717640 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_24 RESULT=pass>
3691 02:46:33.718329 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_24 RESULT=pass
3693 02:46:33.763417 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_24 RESULT=pass>
3694 02:46:33.764111 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_24 RESULT=pass
3696 02:46:33.815972 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_23 RESULT=pass>
3697 02:46:33.816716 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_23 RESULT=pass
3699 02:46:33.874396 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_23 RESULT=pass>
3700 02:46:33.875089 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_23 RESULT=pass
3702 02:46:33.931171 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_23 RESULT=skip>
3703 02:46:33.931874 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_23 RESULT=skip
3705 02:46:33.981584 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_23 RESULT=skip>
3706 02:46:33.982284 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_23 RESULT=skip
3708 02:46:34.033805 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_23 RESULT=skip>
3709 02:46:34.034495 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_23 RESULT=skip
3711 02:46:34.088708 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_23 RESULT=pass>
3712 02:46:34.089406 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_23 RESULT=pass
3714 02:46:34.133912 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_23 RESULT=pass>
3715 02:46:34.134607 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_23 RESULT=pass
3717 02:46:34.182586 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_22 RESULT=pass>
3718 02:46:34.183285 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_22 RESULT=pass
3720 02:46:34.229968 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_22 RESULT=pass>
3721 02:46:34.230660 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_22 RESULT=pass
3723 02:46:34.282259 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_22 RESULT=pass>
3724 02:46:34.282951 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_22 RESULT=pass
3726 02:46:34.334879 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_22 RESULT=pass>
3727 02:46:34.335635 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_22 RESULT=pass
3729 02:46:34.380024 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_22 RESULT=pass>
3730 02:46:34.380727 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_22 RESULT=pass
3732 02:46:34.432010 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_22 RESULT=pass>
3733 02:46:34.432715 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_22 RESULT=pass
3735 02:46:34.482836 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_22 RESULT=pass>
3736 02:46:34.483549 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_22 RESULT=pass
3738 02:46:34.529796 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_21 RESULT=pass>
3739 02:46:34.530495 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_21 RESULT=pass
3741 02:46:34.581877 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_21 RESULT=pass>
3742 02:46:34.582583 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_21 RESULT=pass
3744 02:46:34.635291 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_21 RESULT=pass>
3745 02:46:34.636009 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_21 RESULT=pass
3747 02:46:34.689066 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_21 RESULT=pass>
3748 02:46:34.689762 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_21 RESULT=pass
3750 02:46:34.741338 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_21 RESULT=pass>
3751 02:46:34.742026 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_21 RESULT=pass
3753 02:46:34.786852 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_21 RESULT=pass>
3754 02:46:34.787553 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_21 RESULT=pass
3756 02:46:34.845166 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_21 RESULT=pass>
3757 02:46:34.845857 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_21 RESULT=pass
3759 02:46:34.897519 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_20 RESULT=pass>
3760 02:46:34.898205 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_20 RESULT=pass
3762 02:46:34.940360 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_20 RESULT=pass>
3763 02:46:34.941057 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_20 RESULT=pass
3765 02:46:34.985238 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_20 RESULT=pass>
3766 02:46:34.985920 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_20 RESULT=pass
3768 02:46:35.042832 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_20 RESULT=pass>
3769 02:46:35.043530 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_20 RESULT=pass
3771 02:46:35.094625 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_20 RESULT=pass>
3772 02:46:35.095319 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_20 RESULT=pass
3774 02:46:35.147606 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_20 RESULT=pass>
3775 02:46:35.148326 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_20 RESULT=pass
3777 02:46:35.201029 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_20 RESULT=pass>
3778 02:46:35.201737 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_20 RESULT=pass
3780 02:46:35.250787 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_19 RESULT=pass>
3781 02:46:35.251472 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_19 RESULT=pass
3783 02:46:35.296309 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_19 RESULT=pass>
3784 02:46:35.296992 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_19 RESULT=pass
3786 02:46:35.343412 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_19 RESULT=pass>
3787 02:46:35.344089 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_19 RESULT=pass
3789 02:46:35.395569 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_19 RESULT=pass>
3790 02:46:35.396276 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_19 RESULT=pass
3792 02:46:35.440171 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_19 RESULT=pass>
3793 02:46:35.440851 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_19 RESULT=pass
3795 02:46:35.491055 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_19 RESULT=pass>
3796 02:46:35.491772 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_19 RESULT=pass
3798 02:46:35.548547 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_19 RESULT=pass>
3799 02:46:35.549244 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_19 RESULT=pass
3801 02:46:35.596057 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_18 RESULT=pass>
3802 02:46:35.596737 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_18 RESULT=pass
3804 02:46:35.648571 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_18 RESULT=pass>
3805 02:46:35.649264 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_18 RESULT=pass
3807 02:46:35.694673 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_18 RESULT=pass>
3808 02:46:35.695362 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_18 RESULT=pass
3810 02:46:35.749413 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_18 RESULT=pass>
3811 02:46:35.750106 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_18 RESULT=pass
3813 02:46:35.804092 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_18 RESULT=pass>
3814 02:46:35.804797 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_18 RESULT=pass
3816 02:46:35.851568 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_18 RESULT=pass>
3817 02:46:35.852295 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_18 RESULT=pass
3819 02:46:35.903684 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_18 RESULT=pass>
3820 02:46:35.904398 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_18 RESULT=pass
3822 02:46:35.956852 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_17 RESULT=pass>
3823 02:46:35.957548 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_17 RESULT=pass
3825 02:46:36.011928 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_17 RESULT=pass>
3826 02:46:36.012663 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_17 RESULT=pass
3828 02:46:36.065814 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_17 RESULT=pass>
3829 02:46:36.066500 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_17 RESULT=pass
3831 02:46:36.120207 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_17 RESULT=pass>
3832 02:46:36.120900 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_17 RESULT=pass
3834 02:46:36.168307 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_17 RESULT=pass>
3835 02:46:36.169002 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_17 RESULT=pass
3837 02:46:36.221717 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_17 RESULT=pass>
3838 02:46:36.222417 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_17 RESULT=pass
3840 02:46:36.281373 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_17 RESULT=pass>
3841 02:46:36.282060 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_17 RESULT=pass
3843 02:46:36.338060 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_16 RESULT=pass>
3844 02:46:36.338778 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_16 RESULT=pass
3846 02:46:36.393648 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_16 RESULT=pass>
3847 02:46:36.394406 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_16 RESULT=pass
3849 02:46:36.437994 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_16 RESULT=pass>
3850 02:46:36.438769 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_16 RESULT=pass
3852 02:46:36.491456 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_16 RESULT=pass>
3853 02:46:36.492260 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_16 RESULT=pass
3855 02:46:36.538581 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_16 RESULT=pass>
3856 02:46:36.539342 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_16 RESULT=pass
3858 02:46:36.601129 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_16 RESULT=pass>
3859 02:46:36.601902 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_16 RESULT=pass
3861 02:46:36.647562 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_16 RESULT=pass>
3862 02:46:36.648358 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_16 RESULT=pass
3864 02:46:36.697301 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_15 RESULT=pass>
3865 02:46:36.698037 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_15 RESULT=pass
3867 02:46:36.755485 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_15 RESULT=pass>
3868 02:46:36.756465 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_15 RESULT=pass
3870 02:46:36.810287 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_15 RESULT=pass>
3871 02:46:36.811152 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_15 RESULT=pass
3873 02:46:36.863409 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_15 RESULT=pass>
3874 02:46:36.864367 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_15 RESULT=pass
3876 02:46:36.911667 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_15 RESULT=pass>
3877 02:46:36.912492 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_15 RESULT=pass
3879 02:46:36.957813 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_15 RESULT=pass>
3880 02:46:36.958679 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_15 RESULT=pass
3882 02:46:37.005501 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_15 RESULT=pass>
3883 02:46:37.006300 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_15 RESULT=pass
3885 02:46:37.054228 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_14 RESULT=pass>
3886 02:46:37.055120 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_14 RESULT=pass
3888 02:46:37.105886 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_14 RESULT=pass>
3889 02:46:37.106817 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_14 RESULT=pass
3891 02:46:37.154646 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_14 RESULT=pass>
3892 02:46:37.155526 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_14 RESULT=pass
3894 02:46:37.202069 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_14 RESULT=pass>
3895 02:46:37.202945 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_14 RESULT=pass
3897 02:46:37.248460 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_14 RESULT=pass>
3898 02:46:37.249330 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_14 RESULT=pass
3900 02:46:37.299405 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_14 RESULT=pass>
3901 02:46:37.300323 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_14 RESULT=pass
3903 02:46:37.356170 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_14 RESULT=pass>
3904 02:46:37.357006 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_14 RESULT=pass
3906 02:46:37.409275 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_13 RESULT=pass>
3907 02:46:37.410214 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_13 RESULT=pass
3909 02:46:37.461123 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_13 RESULT=pass>
3910 02:46:37.462051 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_13 RESULT=pass
3912 02:46:37.519779 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_13 RESULT=pass>
3913 02:46:37.520634 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_13 RESULT=pass
3915 02:46:37.564087 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_13 RESULT=pass>
3916 02:46:37.565029 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_13 RESULT=pass
3918 02:46:37.612382 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_13 RESULT=pass>
3919 02:46:37.613256 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_13 RESULT=pass
3921 02:46:37.671302 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_13 RESULT=pass>
3922 02:46:37.672115 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_13 RESULT=pass
3924 02:46:37.722406 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_13 RESULT=pass>
3925 02:46:37.723215 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_13 RESULT=pass
3927 02:46:37.774887 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_12 RESULT=pass>
3928 02:46:37.775835 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_12 RESULT=pass
3930 02:46:37.821613 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_12 RESULT=pass>
3931 02:46:37.822541 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_12 RESULT=pass
3933 02:46:37.868767 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_12 RESULT=pass>
3934 02:46:37.869688 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_12 RESULT=pass
3936 02:46:38.143806 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_12 RESULT=pass>
3937 02:46:38.144605 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_12 RESULT=pass>
3938 02:46:38.145224 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_12 RESULT=pass>
3939 02:46:38.145713 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_12 RESULT=pass>
3940 02:46:38.146467 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_12 RESULT=pass
3942 02:46:38.148488 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_12 RESULT=pass
3944 02:46:38.150205 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_12 RESULT=pass
3946 02:46:38.151901 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_12 RESULT=pass
3948 02:46:38.153880 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_11 RESULT=pass>
3949 02:46:38.154775 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_11 RESULT=pass
3951 02:46:38.175868 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_11 RESULT=pass>
3952 02:46:38.176889 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_11 RESULT=pass
3954 02:46:38.231518 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_11 RESULT=pass>
3955 02:46:38.232516 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_11 RESULT=pass
3957 02:46:38.284641 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_11 RESULT=pass>
3958 02:46:38.285533 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_11 RESULT=pass
3960 02:46:38.333379 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_11 RESULT=pass>
3961 02:46:38.334277 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_11 RESULT=pass
3963 02:46:38.379136 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_11 RESULT=pass>
3964 02:46:38.380091 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_11 RESULT=pass
3966 02:46:38.427929 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_11 RESULT=pass>
3967 02:46:38.428855 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_11 RESULT=pass
3969 02:46:38.473095 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_10 RESULT=pass>
3970 02:46:38.474209 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_10 RESULT=pass
3972 02:46:38.520491 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_10 RESULT=pass>
3973 02:46:38.521502 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_10 RESULT=pass
3975 02:46:38.573834 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_10 RESULT=pass>
3976 02:46:38.574719 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_10 RESULT=pass
3978 02:46:38.622625 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_10 RESULT=pass>
3979 02:46:38.623554 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_10 RESULT=pass
3981 02:46:38.673992 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_10 RESULT=pass>
3982 02:46:38.675071 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_10 RESULT=pass
3984 02:46:38.724867 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_10 RESULT=pass>
3985 02:46:38.725797 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_10 RESULT=pass
3987 02:46:38.775922 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_10 RESULT=pass>
3988 02:46:38.776990 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_10 RESULT=pass
3990 02:46:38.827391 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_9 RESULT=pass>
3991 02:46:38.828292 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_9 RESULT=pass
3993 02:46:38.878116 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_9 RESULT=pass>
3994 02:46:38.879099 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_9 RESULT=pass
3996 02:46:38.934383 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_9 RESULT=pass>
3997 02:46:38.935289 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_9 RESULT=pass
3999 02:46:38.988064 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_9 RESULT=pass>
4000 02:46:38.989078 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_9 RESULT=pass
4002 02:46:39.042800 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_9 RESULT=pass>
4003 02:46:39.043691 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_9 RESULT=pass
4005 02:46:39.097010 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_9 RESULT=pass>
4006 02:46:39.098101 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_9 RESULT=pass
4008 02:46:39.154771 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_9 RESULT=pass>
4009 02:46:39.155762 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_9 RESULT=pass
4011 02:46:39.206010 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_8 RESULT=pass>
4012 02:46:39.206886 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_8 RESULT=pass
4014 02:46:39.251165 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_8 RESULT=pass>
4015 02:46:39.252115 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_8 RESULT=pass
4017 02:46:39.307075 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_8 RESULT=pass>
4018 02:46:39.308154 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_8 RESULT=pass
4020 02:46:39.364602 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_8 RESULT=pass>
4021 02:46:39.365568 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_8 RESULT=pass
4023 02:46:39.418908 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_8 RESULT=pass>
4024 02:46:39.419873 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_8 RESULT=pass
4026 02:46:39.469316 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_8 RESULT=pass>
4027 02:46:39.470270 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_8 RESULT=pass
4029 02:46:39.522232 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_8 RESULT=pass>
4030 02:46:39.523129 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_8 RESULT=pass
4032 02:46:39.573060 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_7 RESULT=pass>
4033 02:46:39.573812 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_7 RESULT=pass
4035 02:46:39.619037 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_7 RESULT=pass>
4036 02:46:39.619681 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_7 RESULT=pass
4038 02:46:39.668182 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_7 RESULT=pass>
4039 02:46:39.668794 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_7 RESULT=pass
4041 02:46:39.718478 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_7 RESULT=pass>
4042 02:46:39.719159 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_7 RESULT=pass
4044 02:46:39.770213 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_7 RESULT=pass>
4045 02:46:39.770815 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_7 RESULT=pass
4047 02:46:39.818191 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_7 RESULT=pass>
4048 02:46:39.819230 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_7 RESULT=pass
4050 02:46:39.909985 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_7 RESULT=pass>
4051 02:46:39.910899 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_7 RESULT=pass
4053 02:46:39.959662 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_6 RESULT=pass>
4054 02:46:39.960630 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_6 RESULT=pass
4056 02:46:40.008728 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_6 RESULT=pass>
4057 02:46:40.009644 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_6 RESULT=pass
4059 02:46:40.061858 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_6 RESULT=pass>
4060 02:46:40.062780 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_6 RESULT=pass
4062 02:46:40.119027 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_6 RESULT=pass>
4063 02:46:40.119915 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_6 RESULT=pass
4065 02:46:40.165054 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_6 RESULT=pass>
4066 02:46:40.165947 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_6 RESULT=pass
4068 02:46:40.220681 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_6 RESULT=pass>
4069 02:46:40.221577 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_6 RESULT=pass
4071 02:46:40.276433 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_6 RESULT=pass>
4072 02:46:40.277431 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_6 RESULT=pass
4074 02:46:40.328879 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_5 RESULT=pass>
4075 02:46:40.329826 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_5 RESULT=pass
4077 02:46:40.387399 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_5 RESULT=pass>
4078 02:46:40.388389 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_5 RESULT=pass
4080 02:46:40.440480 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_5 RESULT=pass>
4081 02:46:40.441323 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_5 RESULT=pass
4083 02:46:40.498498 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_5 RESULT=pass>
4084 02:46:40.499452 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_5 RESULT=pass
4086 02:46:40.556461 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_5 RESULT=pass>
4087 02:46:40.557525 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_5 RESULT=pass
4089 02:46:40.615136 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_5 RESULT=pass>
4090 02:46:40.616077 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_5 RESULT=pass
4092 02:46:40.667115 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_5 RESULT=pass>
4093 02:46:40.668085 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_5 RESULT=pass
4095 02:46:40.717977 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_4 RESULT=pass>
4096 02:46:40.718790 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_4 RESULT=pass
4098 02:46:40.762096 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_4 RESULT=pass>
4099 02:46:40.762973 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_4 RESULT=pass
4101 02:46:40.812317 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_4 RESULT=pass>
4102 02:46:40.813204 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_4 RESULT=pass
4104 02:46:40.864306 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_4 RESULT=pass>
4105 02:46:40.865211 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_4 RESULT=pass
4107 02:46:40.919253 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_4 RESULT=pass>
4108 02:46:40.920116 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_4 RESULT=pass
4110 02:46:40.969112 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_4 RESULT=pass>
4111 02:46:40.969991 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_4 RESULT=pass
4113 02:46:41.019554 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_4 RESULT=pass>
4114 02:46:41.020523 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_4 RESULT=pass
4116 02:46:41.064616 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_3 RESULT=pass>
4117 02:46:41.065498 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_3 RESULT=pass
4119 02:46:41.108876 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_3 RESULT=pass>
4120 02:46:41.109818 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_3 RESULT=pass
4122 02:46:41.160884 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_3 RESULT=pass>
4123 02:46:41.161746 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_3 RESULT=pass
4125 02:46:41.211324 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_3 RESULT=pass>
4126 02:46:41.212138 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_3 RESULT=pass
4128 02:46:41.262534 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_3 RESULT=pass>
4129 02:46:41.263349 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_3 RESULT=pass
4131 02:46:41.312154 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_3 RESULT=pass>
4132 02:46:41.312963 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_3 RESULT=pass
4134 02:46:41.356913 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_3 RESULT=pass>
4135 02:46:41.357739 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_3 RESULT=pass
4137 02:46:41.402559 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_2 RESULT=pass>
4138 02:46:41.403367 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_2 RESULT=pass
4140 02:46:41.455239 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_2 RESULT=pass>
4141 02:46:41.456085 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_2 RESULT=pass
4143 02:46:41.501389 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_2 RESULT=pass>
4144 02:46:41.502207 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_2 RESULT=pass
4146 02:46:41.548195 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_2 RESULT=pass>
4147 02:46:41.549002 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_2 RESULT=pass
4149 02:46:41.602064 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_2 RESULT=pass>
4150 02:46:41.602886 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_2 RESULT=pass
4152 02:46:41.647514 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_2 RESULT=pass>
4153 02:46:41.648330 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_2 RESULT=pass
4155 02:46:41.695053 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_2 RESULT=pass>
4156 02:46:41.695845 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_2 RESULT=pass
4158 02:46:41.746174 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_1 RESULT=pass>
4159 02:46:41.746955 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_1 RESULT=pass
4161 02:46:41.792482 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_1 RESULT=pass>
4162 02:46:41.793274 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_1 RESULT=pass
4164 02:46:41.845934 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_1 RESULT=pass>
4165 02:46:41.846731 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_1 RESULT=pass
4167 02:46:41.898636 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_1 RESULT=pass>
4168 02:46:41.899532 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_1 RESULT=pass
4170 02:46:41.950207 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_1 RESULT=pass>
4171 02:46:41.951084 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_1 RESULT=pass
4173 02:46:42.015552 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_1 RESULT=pass>
4174 02:46:42.016401 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_1 RESULT=pass
4176 02:46:42.061148 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_1 RESULT=pass>
4177 02:46:42.061955 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_1 RESULT=pass
4179 02:46:42.115676 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_0 RESULT=pass>
4180 02:46:42.116661 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_0 RESULT=pass
4182 02:46:42.164425 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_0 RESULT=pass>
4183 02:46:42.165328 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_0 RESULT=pass
4185 02:46:42.212649 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_0 RESULT=pass>
4186 02:46:42.213588 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_0 RESULT=pass
4188 02:46:42.263661 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_0 RESULT=pass>
4189 02:46:42.264593 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_0 RESULT=pass
4191 02:46:42.313744 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_0 RESULT=pass>
4192 02:46:42.314553 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_0 RESULT=pass
4194 02:46:42.366230 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_0 RESULT=pass>
4195 02:46:42.367123 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_0 RESULT=pass
4197 02:46:42.415325 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_0 RESULT=pass>
4198 02:46:42.416253 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_0 RESULT=pass
4200 02:46:42.460994 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test RESULT=pass
4202 02:46:42.464115 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test RESULT=pass>
4203 02:46:42.528013 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_5_0_CAPTURE RESULT=skip>
4204 02:46:42.528830 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_5_0_CAPTURE RESULT=skip
4206 02:46:42.575474 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_5_0_CAPTURE RESULT=skip>
4207 02:46:42.576500 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_5_0_CAPTURE RESULT=skip
4209 02:46:42.630459 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_5_0_CAPTURE RESULT=skip>
4210 02:46:42.631343 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_5_0_CAPTURE RESULT=skip
4212 02:46:42.686101 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_5_0_CAPTURE RESULT=skip>
4213 02:46:42.686913 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_5_0_CAPTURE RESULT=skip
4215 02:46:42.731929 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_5_0_CAPTURE RESULT=skip>
4216 02:46:42.732861 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_5_0_CAPTURE RESULT=skip
4218 02:46:42.779683 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_5_0_CAPTURE RESULT=skip>
4219 02:46:42.780597 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_5_0_CAPTURE RESULT=skip
4221 02:46:42.832018 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_5_0_CAPTURE RESULT=skip>
4222 02:46:42.832837 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_5_0_CAPTURE RESULT=skip
4224 02:46:42.875874 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_4_0_CAPTURE RESULT=skip>
4225 02:46:42.876784 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_4_0_CAPTURE RESULT=skip
4227 02:46:42.930175 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_4_0_CAPTURE RESULT=skip>
4228 02:46:42.931049 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_4_0_CAPTURE RESULT=skip
4230 02:46:42.996097 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_4_0_CAPTURE RESULT=skip>
4231 02:46:42.996990 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_4_0_CAPTURE RESULT=skip
4233 02:46:43.052364 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_4_0_CAPTURE RESULT=skip>
4234 02:46:43.053242 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_4_0_CAPTURE RESULT=skip
4236 02:46:43.111342 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_4_0_CAPTURE RESULT=skip>
4237 02:46:43.112224 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_4_0_CAPTURE RESULT=skip
4239 02:46:43.162442 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_4_0_CAPTURE RESULT=skip>
4240 02:46:43.163389 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_4_0_CAPTURE RESULT=skip
4242 02:46:43.216743 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_4_0_CAPTURE RESULT=skip>
4243 02:46:43.217626 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_4_0_CAPTURE RESULT=skip
4245 02:46:43.260250 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_3_0_CAPTURE RESULT=skip>
4246 02:46:43.261192 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_3_0_CAPTURE RESULT=skip
4248 02:46:43.315854 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_3_0_CAPTURE RESULT=skip>
4249 02:46:43.316702 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_3_0_CAPTURE RESULT=skip
4251 02:46:43.370165 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_3_0_CAPTURE RESULT=skip>
4252 02:46:43.371088 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_3_0_CAPTURE RESULT=skip
4254 02:46:43.423756 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_3_0_CAPTURE RESULT=skip>
4255 02:46:43.424778 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_3_0_CAPTURE RESULT=skip
4257 02:46:43.479824 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_3_0_CAPTURE RESULT=skip>
4258 02:46:43.480729 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_3_0_CAPTURE RESULT=skip
4260 02:46:43.534402 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_3_0_CAPTURE RESULT=skip>
4261 02:46:43.535279 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_3_0_CAPTURE RESULT=skip
4263 02:46:43.590536 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_3_0_CAPTURE RESULT=skip>
4264 02:46:43.591419 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_3_0_CAPTURE RESULT=skip
4266 02:46:43.640337 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_2_0_PLAYBACK RESULT=skip>
4267 02:46:43.641218 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_2_0_PLAYBACK RESULT=skip
4269 02:46:43.699020 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_2_0_PLAYBACK RESULT=skip>
4270 02:46:43.699831 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_2_0_PLAYBACK RESULT=skip
4272 02:46:43.750752 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_2_0_PLAYBACK RESULT=skip>
4273 02:46:43.751694 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_2_0_PLAYBACK RESULT=skip
4275 02:46:43.806552 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_2_0_PLAYBACK RESULT=skip>
4276 02:46:43.807358 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_2_0_PLAYBACK RESULT=skip
4278 02:46:43.860375 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_2_0_PLAYBACK RESULT=skip>
4279 02:46:43.861257 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_2_0_PLAYBACK RESULT=skip
4281 02:46:43.919263 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_2_0_PLAYBACK RESULT=skip>
4282 02:46:43.920116 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_2_0_PLAYBACK RESULT=skip
4284 02:46:43.975600 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_2_0_PLAYBACK RESULT=skip>
4285 02:46:43.976447 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_2_0_PLAYBACK RESULT=skip
4287 02:46:44.019241 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_1_0_PLAYBACK RESULT=skip>
4288 02:46:44.020086 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_1_0_PLAYBACK RESULT=skip
4290 02:46:44.065861 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_1_0_PLAYBACK RESULT=skip>
4291 02:46:44.066662 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_1_0_PLAYBACK RESULT=skip
4293 02:46:44.110618 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_1_0_PLAYBACK RESULT=skip>
4294 02:46:44.111427 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_1_0_PLAYBACK RESULT=skip
4296 02:46:44.165893 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_1_0_PLAYBACK RESULT=skip>
4297 02:46:44.166711 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_1_0_PLAYBACK RESULT=skip
4299 02:46:44.219087 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_1_0_PLAYBACK RESULT=skip>
4300 02:46:44.219897 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_1_0_PLAYBACK RESULT=skip
4302 02:46:44.266911 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_1_0_PLAYBACK RESULT=skip>
4303 02:46:44.267718 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_1_0_PLAYBACK RESULT=skip
4305 02:46:44.318949 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_1_0_PLAYBACK RESULT=skip>
4306 02:46:44.319759 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_1_0_PLAYBACK RESULT=skip
4308 02:46:44.371335 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_0_0_PLAYBACK RESULT=skip>
4309 02:46:44.372160 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_0_0_PLAYBACK RESULT=skip
4311 02:46:44.425739 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_0_0_PLAYBACK RESULT=skip>
4312 02:46:44.426559 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_0_0_PLAYBACK RESULT=skip
4314 02:46:44.481003 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_0_0_PLAYBACK RESULT=skip>
4315 02:46:44.481802 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_0_0_PLAYBACK RESULT=skip
4317 02:46:44.533349 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_0_0_PLAYBACK RESULT=skip>
4318 02:46:44.534142 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_0_0_PLAYBACK RESULT=skip
4320 02:46:44.589700 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_0_0_PLAYBACK RESULT=skip>
4321 02:46:44.590510 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_0_0_PLAYBACK RESULT=skip
4323 02:46:44.641591 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_0_0_PLAYBACK RESULT=skip>
4324 02:46:44.642400 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_0_0_PLAYBACK RESULT=skip
4326 02:46:44.695690 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_0_0_PLAYBACK RESULT=skip>
4327 02:46:44.696574 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_0_0_PLAYBACK RESULT=skip
4329 02:46:44.739048 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test RESULT=pass>
4330 02:46:44.739877 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test RESULT=pass
4332 02:46:44.799821 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_playback_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip>
4333 02:46:44.800652 Received signal: <TESTCASE> TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_playback_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip
4335 02:46:44.855107 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_capture_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip>
4336 02:46:44.855905 Received signal: <TESTCASE> TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_capture_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip
4338 02:46:44.913882 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_ni_capture_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip>
4339 02:46:44.914694 Received signal: <TESTCASE> TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_ni_capture_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip
4341 02:46:44.965967 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_ni_playback_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip>
4342 02:46:44.966779 Received signal: <TESTCASE> TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_ni_playback_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip
4344 02:46:45.019098 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_reset_ioctl_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip>
4345 02:46:45.019902 Received signal: <TESTCASE> TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_reset_ioctl_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip
4347 02:46:45.067239 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_test-pcmtest-driver RESULT=pass>
4348 02:46:45.068083 Received signal: <TESTCASE> TEST_CASE_ID=alsa_test-pcmtest-driver RESULT=pass
4350 02:46:45.123761 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_utimer-test_global_wrong_timers_test RESULT=pass>
4351 02:46:45.124619 Received signal: <TESTCASE> TEST_CASE_ID=alsa_utimer-test_global_wrong_timers_test RESULT=pass
4353 02:46:45.178492 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_utimer-test_timer_f_utimer RESULT=fail>
4354 02:46:45.179396 Received signal: <TESTCASE> TEST_CASE_ID=alsa_utimer-test_timer_f_utimer RESULT=fail
4356 02:46:45.218878 Received signal: <TESTCASE> TEST_CASE_ID=alsa_utimer-test RESULT=fail
4358 02:46:45.224196 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_utimer-test RESULT=fail>
4359 02:46:45.224743 + set +x
4360 02:46:45.230132 <LAVA_SIGNAL_ENDRUN 1_kselftest-alsa 932188_1.6.2.4.5>
4361 02:46:45.230649 <LAVA_TEST_RUNNER EXIT>
4362 02:46:45.231348 Received signal: <ENDRUN> 1_kselftest-alsa 932188_1.6.2.4.5
4363 02:46:45.231822 Ending use of test pattern.
4364 02:46:45.232310 Ending test lava.1_kselftest-alsa (932188_1.6.2.4.5), duration 41.46
4366 02:46:45.233927 ok: lava_test_shell seems to have completed
4367 02:46:45.259244 alsa_mixer-test: pass
alsa_mixer-test_event_missing_LCALTA_0: pass
alsa_mixer-test_event_missing_LCALTA_1: pass
alsa_mixer-test_event_missing_LCALTA_10: pass
alsa_mixer-test_event_missing_LCALTA_11: pass
alsa_mixer-test_event_missing_LCALTA_12: pass
alsa_mixer-test_event_missing_LCALTA_13: pass
alsa_mixer-test_event_missing_LCALTA_14: pass
alsa_mixer-test_event_missing_LCALTA_15: pass
alsa_mixer-test_event_missing_LCALTA_16: pass
alsa_mixer-test_event_missing_LCALTA_17: pass
alsa_mixer-test_event_missing_LCALTA_18: pass
alsa_mixer-test_event_missing_LCALTA_19: pass
alsa_mixer-test_event_missing_LCALTA_2: pass
alsa_mixer-test_event_missing_LCALTA_20: pass
alsa_mixer-test_event_missing_LCALTA_21: pass
alsa_mixer-test_event_missing_LCALTA_22: pass
alsa_mixer-test_event_missing_LCALTA_23: pass
alsa_mixer-test_event_missing_LCALTA_24: pass
alsa_mixer-test_event_missing_LCALTA_25: pass
alsa_mixer-test_event_missing_LCALTA_26: pass
alsa_mixer-test_event_missing_LCALTA_27: pass
alsa_mixer-test_event_missing_LCALTA_28: pass
alsa_mixer-test_event_missing_LCALTA_29: pass
alsa_mixer-test_event_missing_LCALTA_3: pass
alsa_mixer-test_event_missing_LCALTA_30: pass
alsa_mixer-test_event_missing_LCALTA_31: pass
alsa_mixer-test_event_missing_LCALTA_32: pass
alsa_mixer-test_event_missing_LCALTA_33: pass
alsa_mixer-test_event_missing_LCALTA_34: pass
alsa_mixer-test_event_missing_LCALTA_35: pass
alsa_mixer-test_event_missing_LCALTA_36: pass
alsa_mixer-test_event_missing_LCALTA_37: pass
alsa_mixer-test_event_missing_LCALTA_38: pass
alsa_mixer-test_event_missing_LCALTA_39: pass
alsa_mixer-test_event_missing_LCALTA_4: pass
alsa_mixer-test_event_missing_LCALTA_40: pass
alsa_mixer-test_event_missing_LCALTA_41: pass
alsa_mixer-test_event_missing_LCALTA_42: pass
alsa_mixer-test_event_missing_LCALTA_43: pass
alsa_mixer-test_event_missing_LCALTA_44: pass
alsa_mixer-test_event_missing_LCALTA_45: pass
alsa_mixer-test_event_missing_LCALTA_46: pass
alsa_mixer-test_event_missing_LCALTA_47: pass
alsa_mixer-test_event_missing_LCALTA_48: pass
alsa_mixer-test_event_missing_LCALTA_49: pass
alsa_mixer-test_event_missing_LCALTA_5: pass
alsa_mixer-test_event_missing_LCALTA_50: pass
alsa_mixer-test_event_missing_LCALTA_51: pass
alsa_mixer-test_event_missing_LCALTA_52: pass
alsa_mixer-test_event_missing_LCALTA_53: pass
alsa_mixer-test_event_missing_LCALTA_54: pass
alsa_mixer-test_event_missing_LCALTA_55: pass
alsa_mixer-test_event_missing_LCALTA_56: pass
alsa_mixer-test_event_missing_LCALTA_57: pass
alsa_mixer-test_event_missing_LCALTA_58: pass
alsa_mixer-test_event_missing_LCALTA_59: pass
alsa_mixer-test_event_missing_LCALTA_6: pass
alsa_mixer-test_event_missing_LCALTA_60: pass
alsa_mixer-test_event_missing_LCALTA_7: pass
alsa_mixer-test_event_missing_LCALTA_8: pass
alsa_mixer-test_event_missing_LCALTA_9: pass
alsa_mixer-test_event_spurious_LCALTA_0: pass
alsa_mixer-test_event_spurious_LCALTA_1: pass
alsa_mixer-test_event_spurious_LCALTA_10: pass
alsa_mixer-test_event_spurious_LCALTA_11: pass
alsa_mixer-test_event_spurious_LCALTA_12: pass
alsa_mixer-test_event_spurious_LCALTA_13: pass
alsa_mixer-test_event_spurious_LCALTA_14: pass
alsa_mixer-test_event_spurious_LCALTA_15: pass
alsa_mixer-test_event_spurious_LCALTA_16: pass
alsa_mixer-test_event_spurious_LCALTA_17: pass
alsa_mixer-test_event_spurious_LCALTA_18: pass
alsa_mixer-test_event_spurious_LCALTA_19: pass
alsa_mixer-test_event_spurious_LCALTA_2: pass
alsa_mixer-test_event_spurious_LCALTA_20: pass
alsa_mixer-test_event_spurious_LCALTA_21: pass
alsa_mixer-test_event_spurious_LCALTA_22: pass
alsa_mixer-test_event_spurious_LCALTA_23: pass
alsa_mixer-test_event_spurious_LCALTA_24: pass
alsa_mixer-test_event_spurious_LCALTA_25: pass
alsa_mixer-test_event_spurious_LCALTA_26: pass
alsa_mixer-test_event_spurious_LCALTA_27: pass
alsa_mixer-test_event_spurious_LCALTA_28: pass
alsa_mixer-test_event_spurious_LCALTA_29: pass
alsa_mixer-test_event_spurious_LCALTA_3: pass
alsa_mixer-test_event_spurious_LCALTA_30: pass
alsa_mixer-test_event_spurious_LCALTA_31: pass
alsa_mixer-test_event_spurious_LCALTA_32: pass
alsa_mixer-test_event_spurious_LCALTA_33: pass
alsa_mixer-test_event_spurious_LCALTA_34: pass
alsa_mixer-test_event_spurious_LCALTA_35: pass
alsa_mixer-test_event_spurious_LCALTA_36: pass
alsa_mixer-test_event_spurious_LCALTA_37: pass
alsa_mixer-test_event_spurious_LCALTA_38: pass
alsa_mixer-test_event_spurious_LCALTA_39: pass
alsa_mixer-test_event_spurious_LCALTA_4: pass
alsa_mixer-test_event_spurious_LCALTA_40: pass
alsa_mixer-test_event_spurious_LCALTA_41: pass
alsa_mixer-test_event_spurious_LCALTA_42: pass
alsa_mixer-test_event_spurious_LCALTA_43: pass
alsa_mixer-test_event_spurious_LCALTA_44: pass
alsa_mixer-test_event_spurious_LCALTA_45: pass
alsa_mixer-test_event_spurious_LCALTA_46: pass
alsa_mixer-test_event_spurious_LCALTA_47: pass
alsa_mixer-test_event_spurious_LCALTA_48: pass
alsa_mixer-test_event_spurious_LCALTA_49: pass
alsa_mixer-test_event_spurious_LCALTA_5: pass
alsa_mixer-test_event_spurious_LCALTA_50: pass
alsa_mixer-test_event_spurious_LCALTA_51: pass
alsa_mixer-test_event_spurious_LCALTA_52: pass
alsa_mixer-test_event_spurious_LCALTA_53: pass
alsa_mixer-test_event_spurious_LCALTA_54: pass
alsa_mixer-test_event_spurious_LCALTA_55: pass
alsa_mixer-test_event_spurious_LCALTA_56: pass
alsa_mixer-test_event_spurious_LCALTA_57: pass
alsa_mixer-test_event_spurious_LCALTA_58: pass
alsa_mixer-test_event_spurious_LCALTA_59: pass
alsa_mixer-test_event_spurious_LCALTA_6: pass
alsa_mixer-test_event_spurious_LCALTA_60: pass
alsa_mixer-test_event_spurious_LCALTA_7: pass
alsa_mixer-test_event_spurious_LCALTA_8: pass
alsa_mixer-test_event_spurious_LCALTA_9: pass
alsa_mixer-test_get_value_LCALTA_0: pass
alsa_mixer-test_get_value_LCALTA_1: pass
alsa_mixer-test_get_value_LCALTA_10: pass
alsa_mixer-test_get_value_LCALTA_11: pass
alsa_mixer-test_get_value_LCALTA_12: pass
alsa_mixer-test_get_value_LCALTA_13: pass
alsa_mixer-test_get_value_LCALTA_14: pass
alsa_mixer-test_get_value_LCALTA_15: pass
alsa_mixer-test_get_value_LCALTA_16: pass
alsa_mixer-test_get_value_LCALTA_17: pass
alsa_mixer-test_get_value_LCALTA_18: pass
alsa_mixer-test_get_value_LCALTA_19: pass
alsa_mixer-test_get_value_LCALTA_2: pass
alsa_mixer-test_get_value_LCALTA_20: pass
alsa_mixer-test_get_value_LCALTA_21: pass
alsa_mixer-test_get_value_LCALTA_22: pass
alsa_mixer-test_get_value_LCALTA_23: pass
alsa_mixer-test_get_value_LCALTA_24: pass
alsa_mixer-test_get_value_LCALTA_25: pass
alsa_mixer-test_get_value_LCALTA_26: pass
alsa_mixer-test_get_value_LCALTA_27: pass
alsa_mixer-test_get_value_LCALTA_28: pass
alsa_mixer-test_get_value_LCALTA_29: pass
alsa_mixer-test_get_value_LCALTA_3: pass
alsa_mixer-test_get_value_LCALTA_30: pass
alsa_mixer-test_get_value_LCALTA_31: pass
alsa_mixer-test_get_value_LCALTA_32: pass
alsa_mixer-test_get_value_LCALTA_33: pass
alsa_mixer-test_get_value_LCALTA_34: pass
alsa_mixer-test_get_value_LCALTA_35: pass
alsa_mixer-test_get_value_LCALTA_36: pass
alsa_mixer-test_get_value_LCALTA_37: pass
alsa_mixer-test_get_value_LCALTA_38: pass
alsa_mixer-test_get_value_LCALTA_39: pass
alsa_mixer-test_get_value_LCALTA_4: pass
alsa_mixer-test_get_value_LCALTA_40: pass
alsa_mixer-test_get_value_LCALTA_41: pass
alsa_mixer-test_get_value_LCALTA_42: pass
alsa_mixer-test_get_value_LCALTA_43: pass
alsa_mixer-test_get_value_LCALTA_44: pass
alsa_mixer-test_get_value_LCALTA_45: pass
alsa_mixer-test_get_value_LCALTA_46: pass
alsa_mixer-test_get_value_LCALTA_47: pass
alsa_mixer-test_get_value_LCALTA_48: pass
alsa_mixer-test_get_value_LCALTA_49: pass
alsa_mixer-test_get_value_LCALTA_5: pass
alsa_mixer-test_get_value_LCALTA_50: pass
alsa_mixer-test_get_value_LCALTA_51: pass
alsa_mixer-test_get_value_LCALTA_52: pass
alsa_mixer-test_get_value_LCALTA_53: pass
alsa_mixer-test_get_value_LCALTA_54: pass
alsa_mixer-test_get_value_LCALTA_55: pass
alsa_mixer-test_get_value_LCALTA_56: pass
alsa_mixer-test_get_value_LCALTA_57: pass
alsa_mixer-test_get_value_LCALTA_58: pass
alsa_mixer-test_get_value_LCALTA_59: pass
alsa_mixer-test_get_value_LCALTA_6: pass
alsa_mixer-test_get_value_LCALTA_60: pass
alsa_mixer-test_get_value_LCALTA_7: pass
alsa_mixer-test_get_value_LCALTA_8: pass
alsa_mixer-test_get_value_LCALTA_9: pass
alsa_mixer-test_name_LCALTA_0: pass
alsa_mixer-test_name_LCALTA_1: pass
alsa_mixer-test_name_LCALTA_10: pass
alsa_mixer-test_name_LCALTA_11: pass
alsa_mixer-test_name_LCALTA_12: pass
alsa_mixer-test_name_LCALTA_13: pass
alsa_mixer-test_name_LCALTA_14: pass
alsa_mixer-test_name_LCALTA_15: pass
alsa_mixer-test_name_LCALTA_16: pass
alsa_mixer-test_name_LCALTA_17: pass
alsa_mixer-test_name_LCALTA_18: pass
alsa_mixer-test_name_LCALTA_19: pass
alsa_mixer-test_name_LCALTA_2: pass
alsa_mixer-test_name_LCALTA_20: pass
alsa_mixer-test_name_LCALTA_21: pass
alsa_mixer-test_name_LCALTA_22: pass
alsa_mixer-test_name_LCALTA_23: pass
alsa_mixer-test_name_LCALTA_24: pass
alsa_mixer-test_name_LCALTA_25: pass
alsa_mixer-test_name_LCALTA_26: pass
alsa_mixer-test_name_LCALTA_27: pass
alsa_mixer-test_name_LCALTA_28: pass
alsa_mixer-test_name_LCALTA_29: pass
alsa_mixer-test_name_LCALTA_3: pass
alsa_mixer-test_name_LCALTA_30: pass
alsa_mixer-test_name_LCALTA_31: pass
alsa_mixer-test_name_LCALTA_32: pass
alsa_mixer-test_name_LCALTA_33: pass
alsa_mixer-test_name_LCALTA_34: pass
alsa_mixer-test_name_LCALTA_35: pass
alsa_mixer-test_name_LCALTA_36: pass
alsa_mixer-test_name_LCALTA_37: pass
alsa_mixer-test_name_LCALTA_38: pass
alsa_mixer-test_name_LCALTA_39: pass
alsa_mixer-test_name_LCALTA_4: pass
alsa_mixer-test_name_LCALTA_40: pass
alsa_mixer-test_name_LCALTA_41: pass
alsa_mixer-test_name_LCALTA_42: pass
alsa_mixer-test_name_LCALTA_43: pass
alsa_mixer-test_name_LCALTA_44: pass
alsa_mixer-test_name_LCALTA_45: pass
alsa_mixer-test_name_LCALTA_46: pass
alsa_mixer-test_name_LCALTA_47: pass
alsa_mixer-test_name_LCALTA_48: pass
alsa_mixer-test_name_LCALTA_49: pass
alsa_mixer-test_name_LCALTA_5: pass
alsa_mixer-test_name_LCALTA_50: pass
alsa_mixer-test_name_LCALTA_51: pass
alsa_mixer-test_name_LCALTA_52: pass
alsa_mixer-test_name_LCALTA_53: pass
alsa_mixer-test_name_LCALTA_54: pass
alsa_mixer-test_name_LCALTA_55: pass
alsa_mixer-test_name_LCALTA_56: pass
alsa_mixer-test_name_LCALTA_57: pass
alsa_mixer-test_name_LCALTA_58: pass
alsa_mixer-test_name_LCALTA_59: pass
alsa_mixer-test_name_LCALTA_6: pass
alsa_mixer-test_name_LCALTA_60: pass
alsa_mixer-test_name_LCALTA_7: pass
alsa_mixer-test_name_LCALTA_8: pass
alsa_mixer-test_name_LCALTA_9: pass
alsa_mixer-test_write_default_LCALTA_0: pass
alsa_mixer-test_write_default_LCALTA_1: pass
alsa_mixer-test_write_default_LCALTA_10: pass
alsa_mixer-test_write_default_LCALTA_11: pass
alsa_mixer-test_write_default_LCALTA_12: pass
alsa_mixer-test_write_default_LCALTA_13: pass
alsa_mixer-test_write_default_LCALTA_14: pass
alsa_mixer-test_write_default_LCALTA_15: pass
alsa_mixer-test_write_default_LCALTA_16: pass
alsa_mixer-test_write_default_LCALTA_17: pass
alsa_mixer-test_write_default_LCALTA_18: pass
alsa_mixer-test_write_default_LCALTA_19: pass
alsa_mixer-test_write_default_LCALTA_2: pass
alsa_mixer-test_write_default_LCALTA_20: pass
alsa_mixer-test_write_default_LCALTA_21: pass
alsa_mixer-test_write_default_LCALTA_22: pass
alsa_mixer-test_write_default_LCALTA_23: skip
alsa_mixer-test_write_default_LCALTA_24: skip
alsa_mixer-test_write_default_LCALTA_25: pass
alsa_mixer-test_write_default_LCALTA_26: skip
alsa_mixer-test_write_default_LCALTA_27: pass
alsa_mixer-test_write_default_LCALTA_28: pass
alsa_mixer-test_write_default_LCALTA_29: pass
alsa_mixer-test_write_default_LCALTA_3: pass
alsa_mixer-test_write_default_LCALTA_30: pass
alsa_mixer-test_write_default_LCALTA_31: pass
alsa_mixer-test_write_default_LCALTA_32: pass
alsa_mixer-test_write_default_LCALTA_33: pass
alsa_mixer-test_write_default_LCALTA_34: pass
alsa_mixer-test_write_default_LCALTA_35: pass
alsa_mixer-test_write_default_LCALTA_36: pass
alsa_mixer-test_write_default_LCALTA_37: pass
alsa_mixer-test_write_default_LCALTA_38: pass
alsa_mixer-test_write_default_LCALTA_39: pass
alsa_mixer-test_write_default_LCALTA_4: pass
alsa_mixer-test_write_default_LCALTA_40: pass
alsa_mixer-test_write_default_LCALTA_41: pass
alsa_mixer-test_write_default_LCALTA_42: pass
alsa_mixer-test_write_default_LCALTA_43: pass
alsa_mixer-test_write_default_LCALTA_44: pass
alsa_mixer-test_write_default_LCALTA_45: pass
alsa_mixer-test_write_default_LCALTA_46: pass
alsa_mixer-test_write_default_LCALTA_47: pass
alsa_mixer-test_write_default_LCALTA_48: pass
alsa_mixer-test_write_default_LCALTA_49: pass
alsa_mixer-test_write_default_LCALTA_5: pass
alsa_mixer-test_write_default_LCALTA_50: pass
alsa_mixer-test_write_default_LCALTA_51: pass
alsa_mixer-test_write_default_LCALTA_52: pass
alsa_mixer-test_write_default_LCALTA_53: pass
alsa_mixer-test_write_default_LCALTA_54: pass
alsa_mixer-test_write_default_LCALTA_55: pass
alsa_mixer-test_write_default_LCALTA_56: pass
alsa_mixer-test_write_default_LCALTA_57: pass
alsa_mixer-test_write_default_LCALTA_58: pass
alsa_mixer-test_write_default_LCALTA_59: pass
alsa_mixer-test_write_default_LCALTA_6: pass
alsa_mixer-test_write_default_LCALTA_60: pass
alsa_mixer-test_write_default_LCALTA_7: pass
alsa_mixer-test_write_default_LCALTA_8: pass
alsa_mixer-test_write_default_LCALTA_9: pass
alsa_mixer-test_write_invalid_LCALTA_0: pass
alsa_mixer-test_write_invalid_LCALTA_1: pass
alsa_mixer-test_write_invalid_LCALTA_10: pass
alsa_mixer-test_write_invalid_LCALTA_11: pass
alsa_mixer-test_write_invalid_LCALTA_12: pass
alsa_mixer-test_write_invalid_LCALTA_13: pass
alsa_mixer-test_write_invalid_LCALTA_14: pass
alsa_mixer-test_write_invalid_LCALTA_15: pass
alsa_mixer-test_write_invalid_LCALTA_16: pass
alsa_mixer-test_write_invalid_LCALTA_17: pass
alsa_mixer-test_write_invalid_LCALTA_18: pass
alsa_mixer-test_write_invalid_LCALTA_19: pass
alsa_mixer-test_write_invalid_LCALTA_2: pass
alsa_mixer-test_write_invalid_LCALTA_20: pass
alsa_mixer-test_write_invalid_LCALTA_21: pass
alsa_mixer-test_write_invalid_LCALTA_22: pass
alsa_mixer-test_write_invalid_LCALTA_23: skip
alsa_mixer-test_write_invalid_LCALTA_24: skip
alsa_mixer-test_write_invalid_LCALTA_25: skip
alsa_mixer-test_write_invalid_LCALTA_26: skip
alsa_mixer-test_write_invalid_LCALTA_27: pass
alsa_mixer-test_write_invalid_LCALTA_28: pass
alsa_mixer-test_write_invalid_LCALTA_29: pass
alsa_mixer-test_write_invalid_LCALTA_3: pass
alsa_mixer-test_write_invalid_LCALTA_30: pass
alsa_mixer-test_write_invalid_LCALTA_31: pass
alsa_mixer-test_write_invalid_LCALTA_32: pass
alsa_mixer-test_write_invalid_LCALTA_33: pass
alsa_mixer-test_write_invalid_LCALTA_34: pass
alsa_mixer-test_write_invalid_LCALTA_35: pass
alsa_mixer-test_write_invalid_LCALTA_36: pass
alsa_mixer-test_write_invalid_LCALTA_37: pass
alsa_mixer-test_write_invalid_LCALTA_38: pass
alsa_mixer-test_write_invalid_LCALTA_39: pass
alsa_mixer-test_write_invalid_LCALTA_4: pass
alsa_mixer-test_write_invalid_LCALTA_40: pass
alsa_mixer-test_write_invalid_LCALTA_41: pass
alsa_mixer-test_write_invalid_LCALTA_42: pass
alsa_mixer-test_write_invalid_LCALTA_43: pass
alsa_mixer-test_write_invalid_LCALTA_44: pass
alsa_mixer-test_write_invalid_LCALTA_45: pass
alsa_mixer-test_write_invalid_LCALTA_46: pass
alsa_mixer-test_write_invalid_LCALTA_47: pass
alsa_mixer-test_write_invalid_LCALTA_48: pass
alsa_mixer-test_write_invalid_LCALTA_49: pass
alsa_mixer-test_write_invalid_LCALTA_5: pass
alsa_mixer-test_write_invalid_LCALTA_50: pass
alsa_mixer-test_write_invalid_LCALTA_51: pass
alsa_mixer-test_write_invalid_LCALTA_52: pass
alsa_mixer-test_write_invalid_LCALTA_53: pass
alsa_mixer-test_write_invalid_LCALTA_54: pass
alsa_mixer-test_write_invalid_LCALTA_55: pass
alsa_mixer-test_write_invalid_LCALTA_56: pass
alsa_mixer-test_write_invalid_LCALTA_57: pass
alsa_mixer-test_write_invalid_LCALTA_58: pass
alsa_mixer-test_write_invalid_LCALTA_59: pass
alsa_mixer-test_write_invalid_LCALTA_6: pass
alsa_mixer-test_write_invalid_LCALTA_60: pass
alsa_mixer-test_write_invalid_LCALTA_7: pass
alsa_mixer-test_write_invalid_LCALTA_8: pass
alsa_mixer-test_write_invalid_LCALTA_9: pass
alsa_mixer-test_write_valid_LCALTA_0: pass
alsa_mixer-test_write_valid_LCALTA_1: pass
alsa_mixer-test_write_valid_LCALTA_10: pass
alsa_mixer-test_write_valid_LCALTA_11: pass
alsa_mixer-test_write_valid_LCALTA_12: pass
alsa_mixer-test_write_valid_LCALTA_13: pass
alsa_mixer-test_write_valid_LCALTA_14: pass
alsa_mixer-test_write_valid_LCALTA_15: pass
alsa_mixer-test_write_valid_LCALTA_16: pass
alsa_mixer-test_write_valid_LCALTA_17: pass
alsa_mixer-test_write_valid_LCALTA_18: pass
alsa_mixer-test_write_valid_LCALTA_19: pass
alsa_mixer-test_write_valid_LCALTA_2: pass
alsa_mixer-test_write_valid_LCALTA_20: pass
alsa_mixer-test_write_valid_LCALTA_21: pass
alsa_mixer-test_write_valid_LCALTA_22: pass
alsa_mixer-test_write_valid_LCALTA_23: skip
alsa_mixer-test_write_valid_LCALTA_24: skip
alsa_mixer-test_write_valid_LCALTA_25: skip
alsa_mixer-test_write_valid_LCALTA_26: skip
alsa_mixer-test_write_valid_LCALTA_27: pass
alsa_mixer-test_write_valid_LCALTA_28: pass
alsa_mixer-test_write_valid_LCALTA_29: pass
alsa_mixer-test_write_valid_LCALTA_3: pass
alsa_mixer-test_write_valid_LCALTA_30: pass
alsa_mixer-test_write_valid_LCALTA_31: pass
alsa_mixer-test_write_valid_LCALTA_32: pass
alsa_mixer-test_write_valid_LCALTA_33: pass
alsa_mixer-test_write_valid_LCALTA_34: pass
alsa_mixer-test_write_valid_LCALTA_35: pass
alsa_mixer-test_write_valid_LCALTA_36: pass
alsa_mixer-test_write_valid_LCALTA_37: pass
alsa_mixer-test_write_valid_LCALTA_38: pass
alsa_mixer-test_write_valid_LCALTA_39: pass
alsa_mixer-test_write_valid_LCALTA_4: pass
alsa_mixer-test_write_valid_LCALTA_40: pass
alsa_mixer-test_write_valid_LCALTA_41: pass
alsa_mixer-test_write_valid_LCALTA_42: pass
alsa_mixer-test_write_valid_LCALTA_43: pass
alsa_mixer-test_write_valid_LCALTA_44: pass
alsa_mixer-test_write_valid_LCALTA_45: pass
alsa_mixer-test_write_valid_LCALTA_46: pass
alsa_mixer-test_write_valid_LCALTA_47: pass
alsa_mixer-test_write_valid_LCALTA_48: pass
alsa_mixer-test_write_valid_LCALTA_49: pass
alsa_mixer-test_write_valid_LCALTA_5: pass
alsa_mixer-test_write_valid_LCALTA_50: pass
alsa_mixer-test_write_valid_LCALTA_51: pass
alsa_mixer-test_write_valid_LCALTA_52: pass
alsa_mixer-test_write_valid_LCALTA_53: pass
alsa_mixer-test_write_valid_LCALTA_54: pass
alsa_mixer-test_write_valid_LCALTA_55: pass
alsa_mixer-test_write_valid_LCALTA_56: pass
alsa_mixer-test_write_valid_LCALTA_57: pass
alsa_mixer-test_write_valid_LCALTA_58: pass
alsa_mixer-test_write_valid_LCALTA_59: pass
alsa_mixer-test_write_valid_LCALTA_6: pass
alsa_mixer-test_write_valid_LCALTA_60: pass
alsa_mixer-test_write_valid_LCALTA_7: pass
alsa_mixer-test_write_valid_LCALTA_8: pass
alsa_mixer-test_write_valid_LCALTA_9: pass
alsa_pcm-test: pass
alsa_pcm-test_default_time1_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time1_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time1_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time1_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time1_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time1_LCALTA_5_0_CAPTURE: skip
alsa_pcm-test_default_time2_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time2_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time2_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time2_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time2_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time2_LCALTA_5_0_CAPTURE: skip
alsa_pcm-test_default_time3_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time3_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time3_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time3_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time3_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time3_LCALTA_5_0_CAPTURE: skip
alsa_pcm-test_default_time4_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time4_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time4_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time4_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time4_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time4_LCALTA_5_0_CAPTURE: skip
alsa_pcm-test_default_time5_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time5_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time5_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time5_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time5_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time5_LCALTA_5_0_CAPTURE: skip
alsa_pcm-test_default_time6_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time6_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time6_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time6_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time6_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time6_LCALTA_5_0_CAPTURE: skip
alsa_pcm-test_default_time7_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time7_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time7_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time7_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time7_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time7_LCALTA_5_0_CAPTURE: skip
alsa_test-pcmtest-driver: pass
alsa_test-pcmtest-driver_pcmtest_capture_Can_t_read_patterns_Probably_module_isn_t_loaded: skip
alsa_test-pcmtest-driver_pcmtest_ni_capture_Can_t_read_patterns_Probably_module_isn_t_loaded: skip
alsa_test-pcmtest-driver_pcmtest_ni_playback_Can_t_read_patterns_Probably_module_isn_t_loaded: skip
alsa_test-pcmtest-driver_pcmtest_playback_Can_t_read_patterns_Probably_module_isn_t_loaded: skip
alsa_test-pcmtest-driver_pcmtest_reset_ioctl_Can_t_read_patterns_Probably_module_isn_t_loaded: skip
alsa_utimer-test: fail
alsa_utimer-test_global_wrong_timers_test: pass
alsa_utimer-test_timer_f_utimer: fail
shardfile-alsa: pass
4368 02:46:45.261121 end: 3.1 lava-test-shell (duration 00:00:42) [common]
4369 02:46:45.261712 end: 3 lava-test-retry (duration 00:00:42) [common]
4370 02:46:45.262297 start: 4 finalize (timeout 00:06:09) [common]
4371 02:46:45.262893 start: 4.1 power-off (timeout 00:00:30) [common]
4372 02:46:45.263910 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
4373 02:46:45.301074 >> OK - accepted request
4374 02:46:45.303180 Returned 0 in 0 seconds
4375 02:46:45.404416 end: 4.1 power-off (duration 00:00:00) [common]
4377 02:46:45.406191 start: 4.2 read-feedback (timeout 00:06:09) [common]
4378 02:46:45.407369 Listened to connection for namespace 'common' for up to 1s
4379 02:46:46.408199 Finalising connection for namespace 'common'
4380 02:46:46.408957 Disconnecting from shell: Finalise
4381 02:46:46.409494 / #
4382 02:46:46.510487 end: 4.2 read-feedback (duration 00:00:01) [common]
4383 02:46:46.511222 end: 4 finalize (duration 00:00:01) [common]
4384 02:46:46.511920 Cleaning after the job
4385 02:46:46.512634 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/932188/tftp-deploy-cpxqodw7/ramdisk
4386 02:46:46.527606 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/932188/tftp-deploy-cpxqodw7/kernel
4387 02:46:46.573753 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/932188/tftp-deploy-cpxqodw7/dtb
4388 02:46:46.574553 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/932188/tftp-deploy-cpxqodw7/nfsrootfs
4389 02:46:46.760697 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/932188/tftp-deploy-cpxqodw7/modules
4390 02:46:46.781245 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/932188
4391 02:46:49.930871 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/932188
4392 02:46:49.931491 Job finished correctly