Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 09:19:04.173636 lava-dispatcher, installed at version: 2024.01
2 09:19:04.174501 start: 0 validate
3 09:19:04.175054 Start time: 2024-11-05 09:19:04.175022+00:00 (UTC)
4 09:19:04.175650 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 09:19:04.176259 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-igt%2F20240313.0%2Farm64%2Frootfs.cpio.gz exists
6 09:19:04.223936 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 09:19:04.225969 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fpending-fixes%2Fv6.12-rc6-192-g566383b19a748%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 09:19:04.260508 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 09:19:04.261190 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fpending-fixes%2Fv6.12-rc6-192-g566383b19a748%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 09:19:04.293490 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 09:19:04.294041 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fpending-fixes%2Fv6.12-rc6-192-g566383b19a748%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
12 09:19:04.333391 validate duration: 0.16
14 09:19:04.334235 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 09:19:04.334579 start: 1.1 download-retry (timeout 00:10:00) [common]
16 09:19:04.334884 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 09:19:04.335474 Not decompressing ramdisk as can be used compressed.
18 09:19:04.335920 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-igt/20240313.0/arm64/rootfs.cpio.gz
19 09:19:04.336229 saving as /var/lib/lava/dispatcher/tmp/939213/tftp-deploy-i__hvijd/ramdisk/rootfs.cpio.gz
20 09:19:04.336496 total size: 47897469 (45 MB)
21 09:19:04.378549 progress 0 % (0 MB)
22 09:19:04.416876 progress 5 % (2 MB)
23 09:19:04.449136 progress 10 % (4 MB)
24 09:19:04.482135 progress 15 % (6 MB)
25 09:19:04.516523 progress 20 % (9 MB)
26 09:19:04.549018 progress 25 % (11 MB)
27 09:19:04.580803 progress 30 % (13 MB)
28 09:19:04.612753 progress 35 % (16 MB)
29 09:19:04.644276 progress 40 % (18 MB)
30 09:19:04.676271 progress 45 % (20 MB)
31 09:19:04.707920 progress 50 % (22 MB)
32 09:19:04.739368 progress 55 % (25 MB)
33 09:19:04.771674 progress 60 % (27 MB)
34 09:19:04.803700 progress 65 % (29 MB)
35 09:19:04.835755 progress 70 % (32 MB)
36 09:19:04.869061 progress 75 % (34 MB)
37 09:19:04.902405 progress 80 % (36 MB)
38 09:19:04.934489 progress 85 % (38 MB)
39 09:19:04.966196 progress 90 % (41 MB)
40 09:19:04.997720 progress 95 % (43 MB)
41 09:19:05.028886 progress 100 % (45 MB)
42 09:19:05.029600 45 MB downloaded in 0.69 s (65.91 MB/s)
43 09:19:05.030140 end: 1.1.1 http-download (duration 00:00:01) [common]
45 09:19:05.031005 end: 1.1 download-retry (duration 00:00:01) [common]
46 09:19:05.031361 start: 1.2 download-retry (timeout 00:09:59) [common]
47 09:19:05.031654 start: 1.2.1 http-download (timeout 00:09:59) [common]
48 09:19:05.032140 downloading http://storage.kernelci.org/next/pending-fixes/v6.12-rc6-192-g566383b19a748/arm64/defconfig/gcc-12/kernel/Image
49 09:19:05.032394 saving as /var/lib/lava/dispatcher/tmp/939213/tftp-deploy-i__hvijd/kernel/Image
50 09:19:05.032601 total size: 45715968 (43 MB)
51 09:19:05.032810 No compression specified
52 09:19:05.072715 progress 0 % (0 MB)
53 09:19:05.102276 progress 5 % (2 MB)
54 09:19:05.131963 progress 10 % (4 MB)
55 09:19:05.160921 progress 15 % (6 MB)
56 09:19:05.189771 progress 20 % (8 MB)
57 09:19:05.218382 progress 25 % (10 MB)
58 09:19:05.246638 progress 30 % (13 MB)
59 09:19:05.275206 progress 35 % (15 MB)
60 09:19:05.303548 progress 40 % (17 MB)
61 09:19:05.331366 progress 45 % (19 MB)
62 09:19:05.359688 progress 50 % (21 MB)
63 09:19:05.387879 progress 55 % (24 MB)
64 09:19:05.417553 progress 60 % (26 MB)
65 09:19:05.447801 progress 65 % (28 MB)
66 09:19:05.478649 progress 70 % (30 MB)
67 09:19:05.507426 progress 75 % (32 MB)
68 09:19:05.536087 progress 80 % (34 MB)
69 09:19:05.564083 progress 85 % (37 MB)
70 09:19:05.592180 progress 90 % (39 MB)
71 09:19:05.619911 progress 95 % (41 MB)
72 09:19:05.647927 progress 100 % (43 MB)
73 09:19:05.648520 43 MB downloaded in 0.62 s (70.79 MB/s)
74 09:19:05.649016 end: 1.2.1 http-download (duration 00:00:01) [common]
76 09:19:05.649829 end: 1.2 download-retry (duration 00:00:01) [common]
77 09:19:05.650102 start: 1.3 download-retry (timeout 00:09:59) [common]
78 09:19:05.650364 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 09:19:05.650835 downloading http://storage.kernelci.org/next/pending-fixes/v6.12-rc6-192-g566383b19a748/arm64/defconfig/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
80 09:19:05.651106 saving as /var/lib/lava/dispatcher/tmp/939213/tftp-deploy-i__hvijd/dtb/meson-g12b-a311d-libretech-cc.dtb
81 09:19:05.651314 total size: 54703 (0 MB)
82 09:19:05.651523 No compression specified
83 09:19:05.690481 progress 59 % (0 MB)
84 09:19:05.691329 progress 100 % (0 MB)
85 09:19:05.691878 0 MB downloaded in 0.04 s (1.29 MB/s)
86 09:19:05.692409 end: 1.3.1 http-download (duration 00:00:00) [common]
88 09:19:05.693229 end: 1.3 download-retry (duration 00:00:00) [common]
89 09:19:05.693492 start: 1.4 download-retry (timeout 00:09:59) [common]
90 09:19:05.693754 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 09:19:05.694218 downloading http://storage.kernelci.org/next/pending-fixes/v6.12-rc6-192-g566383b19a748/arm64/defconfig/gcc-12/modules.tar.xz
92 09:19:05.694463 saving as /var/lib/lava/dispatcher/tmp/939213/tftp-deploy-i__hvijd/modules/modules.tar
93 09:19:05.694668 total size: 11615948 (11 MB)
94 09:19:05.694877 Using unxz to decompress xz
95 09:19:05.734720 progress 0 % (0 MB)
96 09:19:05.800424 progress 5 % (0 MB)
97 09:19:05.874331 progress 10 % (1 MB)
98 09:19:05.971628 progress 15 % (1 MB)
99 09:19:06.063486 progress 20 % (2 MB)
100 09:19:06.143279 progress 25 % (2 MB)
101 09:19:06.218609 progress 30 % (3 MB)
102 09:19:06.297324 progress 35 % (3 MB)
103 09:19:06.370002 progress 40 % (4 MB)
104 09:19:06.446036 progress 45 % (5 MB)
105 09:19:06.530405 progress 50 % (5 MB)
106 09:19:06.607649 progress 55 % (6 MB)
107 09:19:06.692881 progress 60 % (6 MB)
108 09:19:06.773966 progress 65 % (7 MB)
109 09:19:06.854703 progress 70 % (7 MB)
110 09:19:06.932933 progress 75 % (8 MB)
111 09:19:07.016557 progress 80 % (8 MB)
112 09:19:07.097350 progress 85 % (9 MB)
113 09:19:07.180439 progress 90 % (10 MB)
114 09:19:07.253882 progress 95 % (10 MB)
115 09:19:07.332476 progress 100 % (11 MB)
116 09:19:07.344883 11 MB downloaded in 1.65 s (6.71 MB/s)
117 09:19:07.345476 end: 1.4.1 http-download (duration 00:00:02) [common]
119 09:19:07.346291 end: 1.4 download-retry (duration 00:00:02) [common]
120 09:19:07.346562 start: 1.5 prepare-tftp-overlay (timeout 00:09:57) [common]
121 09:19:07.346830 start: 1.5.1 extract-nfsrootfs (timeout 00:09:57) [common]
122 09:19:07.347080 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 09:19:07.347336 start: 1.5.2 lava-overlay (timeout 00:09:57) [common]
124 09:19:07.347935 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/939213/lava-overlay-4a4ccj1v
125 09:19:07.348781 makedir: /var/lib/lava/dispatcher/tmp/939213/lava-overlay-4a4ccj1v/lava-939213/bin
126 09:19:07.349449 makedir: /var/lib/lava/dispatcher/tmp/939213/lava-overlay-4a4ccj1v/lava-939213/tests
127 09:19:07.350070 makedir: /var/lib/lava/dispatcher/tmp/939213/lava-overlay-4a4ccj1v/lava-939213/results
128 09:19:07.350679 Creating /var/lib/lava/dispatcher/tmp/939213/lava-overlay-4a4ccj1v/lava-939213/bin/lava-add-keys
129 09:19:07.351600 Creating /var/lib/lava/dispatcher/tmp/939213/lava-overlay-4a4ccj1v/lava-939213/bin/lava-add-sources
130 09:19:07.352577 Creating /var/lib/lava/dispatcher/tmp/939213/lava-overlay-4a4ccj1v/lava-939213/bin/lava-background-process-start
131 09:19:07.353516 Creating /var/lib/lava/dispatcher/tmp/939213/lava-overlay-4a4ccj1v/lava-939213/bin/lava-background-process-stop
132 09:19:07.354486 Creating /var/lib/lava/dispatcher/tmp/939213/lava-overlay-4a4ccj1v/lava-939213/bin/lava-common-functions
133 09:19:07.355387 Creating /var/lib/lava/dispatcher/tmp/939213/lava-overlay-4a4ccj1v/lava-939213/bin/lava-echo-ipv4
134 09:19:07.356321 Creating /var/lib/lava/dispatcher/tmp/939213/lava-overlay-4a4ccj1v/lava-939213/bin/lava-install-packages
135 09:19:07.357218 Creating /var/lib/lava/dispatcher/tmp/939213/lava-overlay-4a4ccj1v/lava-939213/bin/lava-installed-packages
136 09:19:07.358088 Creating /var/lib/lava/dispatcher/tmp/939213/lava-overlay-4a4ccj1v/lava-939213/bin/lava-os-build
137 09:19:07.358963 Creating /var/lib/lava/dispatcher/tmp/939213/lava-overlay-4a4ccj1v/lava-939213/bin/lava-probe-channel
138 09:19:07.359844 Creating /var/lib/lava/dispatcher/tmp/939213/lava-overlay-4a4ccj1v/lava-939213/bin/lava-probe-ip
139 09:19:07.360871 Creating /var/lib/lava/dispatcher/tmp/939213/lava-overlay-4a4ccj1v/lava-939213/bin/lava-target-ip
140 09:19:07.361767 Creating /var/lib/lava/dispatcher/tmp/939213/lava-overlay-4a4ccj1v/lava-939213/bin/lava-target-mac
141 09:19:07.362650 Creating /var/lib/lava/dispatcher/tmp/939213/lava-overlay-4a4ccj1v/lava-939213/bin/lava-target-storage
142 09:19:07.363538 Creating /var/lib/lava/dispatcher/tmp/939213/lava-overlay-4a4ccj1v/lava-939213/bin/lava-test-case
143 09:19:07.364482 Creating /var/lib/lava/dispatcher/tmp/939213/lava-overlay-4a4ccj1v/lava-939213/bin/lava-test-event
144 09:19:07.365444 Creating /var/lib/lava/dispatcher/tmp/939213/lava-overlay-4a4ccj1v/lava-939213/bin/lava-test-feedback
145 09:19:07.366335 Creating /var/lib/lava/dispatcher/tmp/939213/lava-overlay-4a4ccj1v/lava-939213/bin/lava-test-raise
146 09:19:07.367203 Creating /var/lib/lava/dispatcher/tmp/939213/lava-overlay-4a4ccj1v/lava-939213/bin/lava-test-reference
147 09:19:07.368109 Creating /var/lib/lava/dispatcher/tmp/939213/lava-overlay-4a4ccj1v/lava-939213/bin/lava-test-runner
148 09:19:07.369007 Creating /var/lib/lava/dispatcher/tmp/939213/lava-overlay-4a4ccj1v/lava-939213/bin/lava-test-set
149 09:19:07.369883 Creating /var/lib/lava/dispatcher/tmp/939213/lava-overlay-4a4ccj1v/lava-939213/bin/lava-test-shell
150 09:19:07.370772 Updating /var/lib/lava/dispatcher/tmp/939213/lava-overlay-4a4ccj1v/lava-939213/bin/lava-install-packages (oe)
151 09:19:07.371739 Updating /var/lib/lava/dispatcher/tmp/939213/lava-overlay-4a4ccj1v/lava-939213/bin/lava-installed-packages (oe)
152 09:19:07.372652 Creating /var/lib/lava/dispatcher/tmp/939213/lava-overlay-4a4ccj1v/lava-939213/environment
153 09:19:07.373361 LAVA metadata
154 09:19:07.373841 - LAVA_JOB_ID=939213
155 09:19:07.374267 - LAVA_DISPATCHER_IP=192.168.6.2
156 09:19:07.374926 start: 1.5.2.1 ssh-authorize (timeout 00:09:57) [common]
157 09:19:07.376732 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 09:19:07.377323 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:57) [common]
159 09:19:07.377736 skipped lava-vland-overlay
160 09:19:07.378224 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 09:19:07.378726 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:57) [common]
162 09:19:07.379149 skipped lava-multinode-overlay
163 09:19:07.379631 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 09:19:07.380168 start: 1.5.2.4 test-definition (timeout 00:09:57) [common]
165 09:19:07.380649 Loading test definitions
166 09:19:07.381190 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:57) [common]
167 09:19:07.381623 Using /lava-939213 at stage 0
168 09:19:07.383762 uuid=939213_1.5.2.4.1 testdef=None
169 09:19:07.384243 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 09:19:07.384516 start: 1.5.2.4.2 test-overlay (timeout 00:09:57) [common]
171 09:19:07.386263 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 09:19:07.387072 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:57) [common]
174 09:19:07.389265 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 09:19:07.390105 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:57) [common]
177 09:19:07.392234 runner path: /var/lib/lava/dispatcher/tmp/939213/lava-overlay-4a4ccj1v/lava-939213/0/tests/0_igt-gpu-panfrost test_uuid 939213_1.5.2.4.1
178 09:19:07.392835 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 09:19:07.393658 Creating lava-test-runner.conf files
181 09:19:07.393864 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/939213/lava-overlay-4a4ccj1v/lava-939213/0 for stage 0
182 09:19:07.394206 - 0_igt-gpu-panfrost
183 09:19:07.394559 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 09:19:07.394843 start: 1.5.2.5 compress-overlay (timeout 00:09:57) [common]
185 09:19:07.418468 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 09:19:07.418877 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:57) [common]
187 09:19:07.419143 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 09:19:07.419411 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 09:19:07.419677 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:57) [common]
190 09:19:14.535483 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:07) [common]
191 09:19:14.535958 start: 1.5.4 extract-modules (timeout 00:09:50) [common]
192 09:19:14.536493 extracting modules file /var/lib/lava/dispatcher/tmp/939213/tftp-deploy-i__hvijd/modules/modules.tar to /var/lib/lava/dispatcher/tmp/939213/extract-overlay-ramdisk-ev7dokkw/ramdisk
193 09:19:15.977120 end: 1.5.4 extract-modules (duration 00:00:01) [common]
194 09:19:15.977598 start: 1.5.5 apply-overlay-tftp (timeout 00:09:48) [common]
195 09:19:15.977878 [common] Applying overlay /var/lib/lava/dispatcher/tmp/939213/compress-overlay-5efbyc4f/overlay-1.5.2.5.tar.gz to ramdisk
196 09:19:15.978092 [common] Applying overlay /var/lib/lava/dispatcher/tmp/939213/compress-overlay-5efbyc4f/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/939213/extract-overlay-ramdisk-ev7dokkw/ramdisk
197 09:19:16.008404 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 09:19:16.008822 start: 1.5.6 prepare-kernel (timeout 00:09:48) [common]
199 09:19:16.009093 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:48) [common]
200 09:19:16.009323 Converting downloaded kernel to a uImage
201 09:19:16.009629 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/939213/tftp-deploy-i__hvijd/kernel/Image /var/lib/lava/dispatcher/tmp/939213/tftp-deploy-i__hvijd/kernel/uImage
202 09:19:16.460933 output: Image Name:
203 09:19:16.461341 output: Created: Tue Nov 5 09:19:16 2024
204 09:19:16.461549 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 09:19:16.461753 output: Data Size: 45715968 Bytes = 44644.50 KiB = 43.60 MiB
206 09:19:16.461955 output: Load Address: 01080000
207 09:19:16.462154 output: Entry Point: 01080000
208 09:19:16.462352 output:
209 09:19:16.462680 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
210 09:19:16.462948 end: 1.5.6 prepare-kernel (duration 00:00:00) [common]
211 09:19:16.463214 start: 1.5.7 configure-preseed-file (timeout 00:09:48) [common]
212 09:19:16.463466 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 09:19:16.463722 start: 1.5.8 compress-ramdisk (timeout 00:09:48) [common]
214 09:19:16.463974 Building ramdisk /var/lib/lava/dispatcher/tmp/939213/extract-overlay-ramdisk-ev7dokkw/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/939213/extract-overlay-ramdisk-ev7dokkw/ramdisk
215 09:19:23.487445 >> 502417 blocks
216 09:19:44.004741 Adding RAMdisk u-boot header.
217 09:19:44.005446 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/939213/extract-overlay-ramdisk-ev7dokkw/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/939213/extract-overlay-ramdisk-ev7dokkw/ramdisk.cpio.gz.uboot
218 09:19:44.662111 output: Image Name:
219 09:19:44.662530 output: Created: Tue Nov 5 09:19:44 2024
220 09:19:44.662739 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 09:19:44.662942 output: Data Size: 65716473 Bytes = 64176.24 KiB = 62.67 MiB
222 09:19:44.663140 output: Load Address: 00000000
223 09:19:44.663337 output: Entry Point: 00000000
224 09:19:44.663532 output:
225 09:19:44.664248 rename /var/lib/lava/dispatcher/tmp/939213/extract-overlay-ramdisk-ev7dokkw/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/939213/tftp-deploy-i__hvijd/ramdisk/ramdisk.cpio.gz.uboot
226 09:19:44.665051 end: 1.5.8 compress-ramdisk (duration 00:00:28) [common]
227 09:19:44.665641 end: 1.5 prepare-tftp-overlay (duration 00:00:37) [common]
228 09:19:44.666214 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:20) [common]
229 09:19:44.666713 No LXC device requested
230 09:19:44.667256 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 09:19:44.667810 start: 1.7 deploy-device-env (timeout 00:09:20) [common]
232 09:19:44.668382 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 09:19:44.668834 Checking files for TFTP limit of 4294967296 bytes.
234 09:19:44.671747 end: 1 tftp-deploy (duration 00:00:40) [common]
235 09:19:44.672429 start: 2 uboot-action (timeout 00:05:00) [common]
236 09:19:44.673000 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 09:19:44.673544 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 09:19:44.674114 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 09:19:44.674684 Using kernel file from prepare-kernel: 939213/tftp-deploy-i__hvijd/kernel/uImage
240 09:19:44.675345 substitutions:
241 09:19:44.675792 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 09:19:44.676276 - {DTB_ADDR}: 0x01070000
243 09:19:44.676751 - {DTB}: 939213/tftp-deploy-i__hvijd/dtb/meson-g12b-a311d-libretech-cc.dtb
244 09:19:44.677261 - {INITRD}: 939213/tftp-deploy-i__hvijd/ramdisk/ramdisk.cpio.gz.uboot
245 09:19:44.677756 - {KERNEL_ADDR}: 0x01080000
246 09:19:44.678210 - {KERNEL}: 939213/tftp-deploy-i__hvijd/kernel/uImage
247 09:19:44.678652 - {LAVA_MAC}: None
248 09:19:44.679156 - {PRESEED_CONFIG}: None
249 09:19:44.679602 - {PRESEED_LOCAL}: None
250 09:19:44.680066 - {RAMDISK_ADDR}: 0x08000000
251 09:19:44.680502 - {RAMDISK}: 939213/tftp-deploy-i__hvijd/ramdisk/ramdisk.cpio.gz.uboot
252 09:19:44.680939 - {ROOT_PART}: None
253 09:19:44.681366 - {ROOT}: None
254 09:19:44.681797 - {SERVER_IP}: 192.168.6.2
255 09:19:44.682235 - {TEE_ADDR}: 0x83000000
256 09:19:44.682665 - {TEE}: None
257 09:19:44.683095 Parsed boot commands:
258 09:19:44.683510 - setenv autoload no
259 09:19:44.683939 - setenv initrd_high 0xffffffff
260 09:19:44.684392 - setenv fdt_high 0xffffffff
261 09:19:44.684816 - dhcp
262 09:19:44.685242 - setenv serverip 192.168.6.2
263 09:19:44.685665 - tftpboot 0x01080000 939213/tftp-deploy-i__hvijd/kernel/uImage
264 09:19:44.686091 - tftpboot 0x08000000 939213/tftp-deploy-i__hvijd/ramdisk/ramdisk.cpio.gz.uboot
265 09:19:44.686515 - tftpboot 0x01070000 939213/tftp-deploy-i__hvijd/dtb/meson-g12b-a311d-libretech-cc.dtb
266 09:19:44.686941 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 09:19:44.687374 - bootm 0x01080000 0x08000000 0x01070000
268 09:19:44.687933 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 09:19:44.689592 start: 2.3 connect-device (timeout 00:05:00) [common]
271 09:19:44.690076 [common] connect-device Connecting to device using 'telnet conserv1 3007'
272 09:19:44.706679 Setting prompt string to ['lava-test: # ']
273 09:19:44.708322 end: 2.3 connect-device (duration 00:00:00) [common]
274 09:19:44.708997 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 09:19:44.709580 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 09:19:44.710130 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 09:19:44.711365 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
278 09:19:44.749395 >> OK - accepted request
279 09:19:44.751583 Returned 0 in 0 seconds
280 09:19:44.852606 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
282 09:19:44.854396 end: 2.4.1 reset-device (duration 00:00:00) [common]
283 09:19:44.855008 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
284 09:19:44.855552 Setting prompt string to ['Hit any key to stop autoboot']
285 09:19:44.856109 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 09:19:44.857850 Trying 192.168.56.21...
287 09:19:44.858359 Connected to conserv1.
288 09:19:44.858815 Escape character is '^]'.
289 09:19:44.859255
290 09:19:44.859715 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
291 09:19:44.860214
292 09:19:56.234982 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
293 09:19:56.235683 bl2_stage_init 0x01
294 09:19:56.236232 bl2_stage_init 0x81
295 09:19:56.240595 hw id: 0x0000 - pwm id 0x01
296 09:19:56.241185 bl2_stage_init 0xc1
297 09:19:56.241649 bl2_stage_init 0x02
298 09:19:56.242098
299 09:19:56.246073 L0:00000000
300 09:19:56.246633 L1:20000703
301 09:19:56.247085 L2:00008067
302 09:19:56.247534 L3:14000000
303 09:19:56.248993 B2:00402000
304 09:19:56.249491 B1:e0f83180
305 09:19:56.249934
306 09:19:56.250364 TE: 58124
307 09:19:56.250790
308 09:19:56.260076 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
309 09:19:56.260567
310 09:19:56.261000 Board ID = 1
311 09:19:56.261422 Set A53 clk to 24M
312 09:19:56.261844 Set A73 clk to 24M
313 09:19:56.265880 Set clk81 to 24M
314 09:19:56.266432 A53 clk: 1200 MHz
315 09:19:56.266869 A73 clk: 1200 MHz
316 09:19:56.271394 CLK81: 166.6M
317 09:19:56.271878 smccc: 00012a92
318 09:19:56.277003 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
319 09:19:56.277485 board id: 1
320 09:19:56.285715 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
321 09:19:56.296030 fw parse done
322 09:19:56.301947 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
323 09:19:56.344613 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
324 09:19:56.355504 PIEI prepare done
325 09:19:56.355968 fastboot data load
326 09:19:56.356452 fastboot data verify
327 09:19:56.361214 verify result: 266
328 09:19:56.366738 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
329 09:19:56.367207 LPDDR4 probe
330 09:19:56.367641 ddr clk to 1584MHz
331 09:19:56.374727 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
332 09:19:56.412090
333 09:19:56.412610 dmc_version 0001
334 09:19:56.418650 Check phy result
335 09:19:56.424518 INFO : End of CA training
336 09:19:56.424986 INFO : End of initialization
337 09:19:56.430210 INFO : Training has run successfully!
338 09:19:56.430671 Check phy result
339 09:19:56.435700 INFO : End of initialization
340 09:19:56.436190 INFO : End of read enable training
341 09:19:56.441330 INFO : End of fine write leveling
342 09:19:56.446936 INFO : End of Write leveling coarse delay
343 09:19:56.447393 INFO : Training has run successfully!
344 09:19:56.447827 Check phy result
345 09:19:56.452508 INFO : End of initialization
346 09:19:56.452974 INFO : End of read dq deskew training
347 09:19:56.458195 INFO : End of MPR read delay center optimization
348 09:19:56.463750 INFO : End of write delay center optimization
349 09:19:56.469356 INFO : End of read delay center optimization
350 09:19:56.469824 INFO : End of max read latency training
351 09:19:56.474968 INFO : Training has run successfully!
352 09:19:56.475422 1D training succeed
353 09:19:56.484158 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
354 09:19:56.531746 Check phy result
355 09:19:56.532254 INFO : End of initialization
356 09:19:56.554343 INFO : End of 2D read delay Voltage center optimization
357 09:19:56.574572 INFO : End of 2D read delay Voltage center optimization
358 09:19:56.626619 INFO : End of 2D write delay Voltage center optimization
359 09:19:56.676086 INFO : End of 2D write delay Voltage center optimization
360 09:19:56.681528 INFO : Training has run successfully!
361 09:19:56.681995
362 09:19:56.682435 channel==0
363 09:19:56.687215 RxClkDly_Margin_A0==88 ps 9
364 09:19:56.687682 TxDqDly_Margin_A0==98 ps 10
365 09:19:56.692726 RxClkDly_Margin_A1==88 ps 9
366 09:19:56.693181 TxDqDly_Margin_A1==98 ps 10
367 09:19:56.693616 TrainedVREFDQ_A0==74
368 09:19:56.698347 TrainedVREFDQ_A1==74
369 09:19:56.698808 VrefDac_Margin_A0==24
370 09:19:56.699237 DeviceVref_Margin_A0==40
371 09:19:56.704009 VrefDac_Margin_A1==25
372 09:19:56.704467 DeviceVref_Margin_A1==40
373 09:19:56.704895
374 09:19:56.705328
375 09:19:56.709500 channel==1
376 09:19:56.709957 RxClkDly_Margin_A0==88 ps 9
377 09:19:56.710387 TxDqDly_Margin_A0==98 ps 10
378 09:19:56.715230 RxClkDly_Margin_A1==98 ps 10
379 09:19:56.715684 TxDqDly_Margin_A1==88 ps 9
380 09:19:56.720720 TrainedVREFDQ_A0==77
381 09:19:56.721183 TrainedVREFDQ_A1==77
382 09:19:56.721614 VrefDac_Margin_A0==22
383 09:19:56.726296 DeviceVref_Margin_A0==37
384 09:19:56.726748 VrefDac_Margin_A1==22
385 09:19:56.732034 DeviceVref_Margin_A1==37
386 09:19:56.732493
387 09:19:56.732928 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
388 09:19:56.733356
389 09:19:56.765508 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000019 00000018 00000018 00000016 00000018 00000015 00000018 00000019 00000018 00000019 00000018 0000001a 0000001a 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
390 09:19:56.766053 2D training succeed
391 09:19:56.771334 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
392 09:19:56.776702 auto size-- 65535DDR cs0 size: 2048MB
393 09:19:56.777160 DDR cs1 size: 2048MB
394 09:19:56.782298 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
395 09:19:56.782756 cs0 DataBus test pass
396 09:19:56.787977 cs1 DataBus test pass
397 09:19:56.788479 cs0 AddrBus test pass
398 09:19:56.788909 cs1 AddrBus test pass
399 09:19:56.789332
400 09:19:56.793498 100bdlr_step_size ps== 420
401 09:19:56.793962 result report
402 09:19:56.799245 boot times 0Enable ddr reg access
403 09:19:56.804467 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
404 09:19:56.817965 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
405 09:19:57.391608 0.0;M3 CHK:0;cm4_sp_mode 0
406 09:19:57.392227 MVN_1=0x00000000
407 09:19:57.397071 MVN_2=0x00000000
408 09:19:57.402818 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
409 09:19:57.403312 OPS=0x10
410 09:19:57.403761 ring efuse init
411 09:19:57.404248 chipver efuse init
412 09:19:57.408427 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
413 09:19:57.414013 [0.018961 Inits done]
414 09:19:57.414499 secure task start!
415 09:19:57.414944 high task start!
416 09:19:57.418603 low task start!
417 09:19:57.419093 run into bl31
418 09:19:57.425274 NOTICE: BL31: v1.3(release):4fc40b1
419 09:19:57.433103 NOTICE: BL31: Built : 15:58:17, May 22 2019
420 09:19:57.433598 NOTICE: BL31: G12A normal boot!
421 09:19:57.458457 NOTICE: BL31: BL33 decompress pass
422 09:19:57.464261 ERROR: Error initializing runtime service opteed_fast
423 09:19:58.697040
424 09:19:58.697723
425 09:19:58.705527 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
426 09:19:58.706191
427 09:19:58.706675 Model: Libre Computer AML-A311D-CC Alta
428 09:19:58.914036 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
429 09:19:58.937972 DRAM: 2 GiB (effective 3.8 GiB)
430 09:19:59.080307 Core: 408 devices, 31 uclasses, devicetree: separate
431 09:19:59.086069 WDT: Not starting watchdog@f0d0
432 09:19:59.118329 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
433 09:19:59.130826 Loading Environment from FAT... Card did not respond to voltage select! : -110
434 09:19:59.135800 ** Bad device specification mmc 0 **
435 09:19:59.146114 Card did not respond to voltage select! : -110
436 09:19:59.153789 ** Bad device specification mmc 0 **
437 09:19:59.154289 Couldn't find partition mmc 0
438 09:19:59.162118 Card did not respond to voltage select! : -110
439 09:19:59.167650 ** Bad device specification mmc 0 **
440 09:19:59.168153 Couldn't find partition mmc 0
441 09:19:59.172677 Error: could not access storage.
442 09:20:00.435236 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
443 09:20:00.435934 bl2_stage_init 0x01
444 09:20:00.436520 bl2_stage_init 0x81
445 09:20:00.440735 hw id: 0x0000 - pwm id 0x01
446 09:20:00.441298 bl2_stage_init 0xc1
447 09:20:00.441769 bl2_stage_init 0x02
448 09:20:00.442225
449 09:20:00.446339 L0:00000000
450 09:20:00.446846 L1:20000703
451 09:20:00.447296 L2:00008067
452 09:20:00.447737 L3:14000000
453 09:20:00.451925 B2:00402000
454 09:20:00.452436 B1:e0f83180
455 09:20:00.452880
456 09:20:00.453321 TE: 58124
457 09:20:00.453761
458 09:20:00.457545 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
459 09:20:00.458032
460 09:20:00.458487 Board ID = 1
461 09:20:00.463127 Set A53 clk to 24M
462 09:20:00.463606 Set A73 clk to 24M
463 09:20:00.464085 Set clk81 to 24M
464 09:20:00.468727 A53 clk: 1200 MHz
465 09:20:00.469202 A73 clk: 1200 MHz
466 09:20:00.469642 CLK81: 166.6M
467 09:20:00.470078 smccc: 00012a92
468 09:20:00.474301 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
469 09:20:00.479919 board id: 1
470 09:20:00.485802 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
471 09:20:00.496481 fw parse done
472 09:20:00.502675 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
473 09:20:00.545007 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
474 09:20:00.559150 PIEI prepare done
475 09:20:00.559681 fastboot data load
476 09:20:00.560186 fastboot data verify
477 09:20:00.561605 verify result: 266
478 09:20:00.567322 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
479 09:20:00.567810 LPDDR4 probe
480 09:20:00.568295 ddr clk to 1584MHz
481 09:20:00.575234 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
482 09:20:00.612406
483 09:20:00.612913 dmc_version 0001
484 09:20:00.618161 Check phy result
485 09:20:00.624980 INFO : End of CA training
486 09:20:00.625447 INFO : End of initialization
487 09:20:00.630576 INFO : Training has run successfully!
488 09:20:00.631042 Check phy result
489 09:20:00.636199 INFO : End of initialization
490 09:20:00.636663 INFO : End of read enable training
491 09:20:00.639557 INFO : End of fine write leveling
492 09:20:00.645080 INFO : End of Write leveling coarse delay
493 09:20:00.650790 INFO : Training has run successfully!
494 09:20:00.651256 Check phy result
495 09:20:00.651697 INFO : End of initialization
496 09:20:00.656286 INFO : End of read dq deskew training
497 09:20:00.661893 INFO : End of MPR read delay center optimization
498 09:20:00.662360 INFO : End of write delay center optimization
499 09:20:00.667544 INFO : End of read delay center optimization
500 09:20:00.673090 INFO : End of max read latency training
501 09:20:00.673574 INFO : Training has run successfully!
502 09:20:00.678839 1D training succeed
503 09:20:00.684611 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
504 09:20:00.732278 Check phy result
505 09:20:00.732793 INFO : End of initialization
506 09:20:00.754719 INFO : End of 2D read delay Voltage center optimization
507 09:20:00.774971 INFO : End of 2D read delay Voltage center optimization
508 09:20:00.826983 INFO : End of 2D write delay Voltage center optimization
509 09:20:00.876363 INFO : End of 2D write delay Voltage center optimization
510 09:20:00.881949 INFO : Training has run successfully!
511 09:20:00.882287
512 09:20:00.882526 channel==0
513 09:20:00.887535 RxClkDly_Margin_A0==88 ps 9
514 09:20:00.887959 TxDqDly_Margin_A0==98 ps 10
515 09:20:00.890828 RxClkDly_Margin_A1==88 ps 9
516 09:20:00.891229 TxDqDly_Margin_A1==88 ps 9
517 09:20:00.896344 TrainedVREFDQ_A0==74
518 09:20:00.896630 TrainedVREFDQ_A1==74
519 09:20:00.896843 VrefDac_Margin_A0==25
520 09:20:00.901931 DeviceVref_Margin_A0==40
521 09:20:00.902348 VrefDac_Margin_A1==25
522 09:20:00.907545 DeviceVref_Margin_A1==40
523 09:20:00.907958
524 09:20:00.908301
525 09:20:00.908526 channel==1
526 09:20:00.908724 RxClkDly_Margin_A0==88 ps 9
527 09:20:00.913121 TxDqDly_Margin_A0==88 ps 9
528 09:20:00.913523 RxClkDly_Margin_A1==88 ps 9
529 09:20:00.918821 TxDqDly_Margin_A1==88 ps 9
530 09:20:00.919645 TrainedVREFDQ_A0==75
531 09:20:00.919926 TrainedVREFDQ_A1==77
532 09:20:00.924307 VrefDac_Margin_A0==22
533 09:20:00.924720 DeviceVref_Margin_A0==39
534 09:20:00.929910 VrefDac_Margin_A1==24
535 09:20:00.930309 DeviceVref_Margin_A1==37
536 09:20:00.930539
537 09:20:00.935563 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
538 09:20:00.935885
539 09:20:00.963576 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000017 00000019 00000017 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
540 09:20:00.969139 2D training succeed
541 09:20:00.974828 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
542 09:20:00.975144 auto size-- 65535DDR cs0 size: 2048MB
543 09:20:00.980320 DDR cs1 size: 2048MB
544 09:20:00.980619 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
545 09:20:00.985954 cs0 DataBus test pass
546 09:20:00.986364 cs1 DataBus test pass
547 09:20:00.986675 cs0 AddrBus test pass
548 09:20:00.991548 cs1 AddrBus test pass
549 09:20:00.991829
550 09:20:00.992063 100bdlr_step_size ps== 420
551 09:20:00.992270 result report
552 09:20:00.997156 boot times 0Enable ddr reg access
553 09:20:01.004639 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
554 09:20:01.018097 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
555 09:20:01.591868 0.0;M3 CHK:0;cm4_sp_mode 0
556 09:20:01.592548 MVN_1=0x00000000
557 09:20:01.597380 MVN_2=0x00000000
558 09:20:01.603116 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
559 09:20:01.603638 OPS=0x10
560 09:20:01.604155 ring efuse init
561 09:20:01.604630 chipver efuse init
562 09:20:01.608698 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
563 09:20:01.614298 [0.018961 Inits done]
564 09:20:01.614770 secure task start!
565 09:20:01.615199 high task start!
566 09:20:01.619062 low task start!
567 09:20:01.619521 run into bl31
568 09:20:01.625570 NOTICE: BL31: v1.3(release):4fc40b1
569 09:20:01.633365 NOTICE: BL31: Built : 15:58:17, May 22 2019
570 09:20:01.633834 NOTICE: BL31: G12A normal boot!
571 09:20:01.658752 NOTICE: BL31: BL33 decompress pass
572 09:20:01.664423 ERROR: Error initializing runtime service opteed_fast
573 09:20:02.897324
574 09:20:02.897969
575 09:20:02.905714 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
576 09:20:02.906202
577 09:20:02.906653 Model: Libre Computer AML-A311D-CC Alta
578 09:20:03.114021 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
579 09:20:03.137449 DRAM: 2 GiB (effective 3.8 GiB)
580 09:20:03.280539 Core: 408 devices, 31 uclasses, devicetree: separate
581 09:20:03.286305 WDT: Not starting watchdog@f0d0
582 09:20:03.318582 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
583 09:20:03.331151 Loading Environment from FAT... Card did not respond to voltage select! : -110
584 09:20:03.336047 ** Bad device specification mmc 0 **
585 09:20:03.346339 Card did not respond to voltage select! : -110
586 09:20:03.354011 ** Bad device specification mmc 0 **
587 09:20:03.354485 Couldn't find partition mmc 0
588 09:20:03.362337 Card did not respond to voltage select! : -110
589 09:20:03.367886 ** Bad device specification mmc 0 **
590 09:20:03.368400 Couldn't find partition mmc 0
591 09:20:03.372898 Error: could not access storage.
592 09:20:03.715371 Net: eth0: ethernet@ff3f0000
593 09:20:03.715913 starting USB...
594 09:20:03.967172 Bus usb@ff500000: Register 3000140 NbrPorts 3
595 09:20:03.967737 Starting the controller
596 09:20:03.974126 USB XHCI 1.10
597 09:20:05.686841 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
598 09:20:05.687494 bl2_stage_init 0x01
599 09:20:05.687961 bl2_stage_init 0x81
600 09:20:05.692501 hw id: 0x0000 - pwm id 0x01
601 09:20:05.692984 bl2_stage_init 0xc1
602 09:20:05.693436 bl2_stage_init 0x02
603 09:20:05.693879
604 09:20:05.698026 L0:00000000
605 09:20:05.698519 L1:20000703
606 09:20:05.698967 L2:00008067
607 09:20:05.699406 L3:14000000
608 09:20:05.703629 B2:00402000
609 09:20:05.704128 B1:e0f83180
610 09:20:05.704575
611 09:20:05.705014 TE: 58159
612 09:20:05.705455
613 09:20:05.709215 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
614 09:20:05.709701
615 09:20:05.710148 Board ID = 1
616 09:20:05.714835 Set A53 clk to 24M
617 09:20:05.715307 Set A73 clk to 24M
618 09:20:05.715746 Set clk81 to 24M
619 09:20:05.720520 A53 clk: 1200 MHz
620 09:20:05.720992 A73 clk: 1200 MHz
621 09:20:05.721435 CLK81: 166.6M
622 09:20:05.721871 smccc: 00012ab5
623 09:20:05.726004 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
624 09:20:05.731591 board id: 1
625 09:20:05.737223 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
626 09:20:05.748258 fw parse done
627 09:20:05.754139 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
628 09:20:05.796429 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
629 09:20:05.807667 PIEI prepare done
630 09:20:05.808180 fastboot data load
631 09:20:05.808632 fastboot data verify
632 09:20:05.813297 verify result: 266
633 09:20:05.818885 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
634 09:20:05.819364 LPDDR4 probe
635 09:20:05.819807 ddr clk to 1584MHz
636 09:20:05.826828 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
637 09:20:05.864072
638 09:20:05.864542 dmc_version 0001
639 09:20:05.870775 Check phy result
640 09:20:05.876644 INFO : End of CA training
641 09:20:05.877109 INFO : End of initialization
642 09:20:05.882251 INFO : Training has run successfully!
643 09:20:05.882721 Check phy result
644 09:20:05.887837 INFO : End of initialization
645 09:20:05.888346 INFO : End of read enable training
646 09:20:05.893515 INFO : End of fine write leveling
647 09:20:05.899027 INFO : End of Write leveling coarse delay
648 09:20:05.899490 INFO : Training has run successfully!
649 09:20:05.899932 Check phy result
650 09:20:05.904607 INFO : End of initialization
651 09:20:05.905071 INFO : End of read dq deskew training
652 09:20:05.910254 INFO : End of MPR read delay center optimization
653 09:20:05.915825 INFO : End of write delay center optimization
654 09:20:05.921520 INFO : End of read delay center optimization
655 09:20:05.921988 INFO : End of max read latency training
656 09:20:05.927037 INFO : Training has run successfully!
657 09:20:05.927509 1D training succeed
658 09:20:05.936241 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
659 09:20:05.983802 Check phy result
660 09:20:05.984307 INFO : End of initialization
661 09:20:06.005408 INFO : End of 2D read delay Voltage center optimization
662 09:20:06.025601 INFO : End of 2D read delay Voltage center optimization
663 09:20:06.077446 INFO : End of 2D write delay Voltage center optimization
664 09:20:06.126672 INFO : End of 2D write delay Voltage center optimization
665 09:20:06.132288 INFO : Training has run successfully!
666 09:20:06.132753
667 09:20:06.133198 channel==0
668 09:20:06.137848 RxClkDly_Margin_A0==88 ps 9
669 09:20:06.138315 TxDqDly_Margin_A0==98 ps 10
670 09:20:06.143526 RxClkDly_Margin_A1==88 ps 9
671 09:20:06.144032 TxDqDly_Margin_A1==98 ps 10
672 09:20:06.144497 TrainedVREFDQ_A0==74
673 09:20:06.149027 TrainedVREFDQ_A1==74
674 09:20:06.149517 VrefDac_Margin_A0==25
675 09:20:06.149961 DeviceVref_Margin_A0==40
676 09:20:06.154674 VrefDac_Margin_A1==26
677 09:20:06.155145 DeviceVref_Margin_A1==40
678 09:20:06.155587
679 09:20:06.156054
680 09:20:06.160281 channel==1
681 09:20:06.160750 RxClkDly_Margin_A0==88 ps 9
682 09:20:06.161189 TxDqDly_Margin_A0==88 ps 9
683 09:20:06.165817 RxClkDly_Margin_A1==98 ps 10
684 09:20:06.166288 TxDqDly_Margin_A1==88 ps 9
685 09:20:06.171530 TrainedVREFDQ_A0==77
686 09:20:06.172034 TrainedVREFDQ_A1==77
687 09:20:06.172482 VrefDac_Margin_A0==22
688 09:20:06.177043 DeviceVref_Margin_A0==37
689 09:20:06.177513 VrefDac_Margin_A1==22
690 09:20:06.182619 DeviceVref_Margin_A1==37
691 09:20:06.183087
692 09:20:06.183531 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
693 09:20:06.183970
694 09:20:06.216303 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000018 00000019 00000018 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
695 09:20:06.216840 2D training succeed
696 09:20:06.221856 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
697 09:20:06.227539 auto size-- 65535DDR cs0 size: 2048MB
698 09:20:06.228034 DDR cs1 size: 2048MB
699 09:20:06.233039 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
700 09:20:06.233510 cs0 DataBus test pass
701 09:20:06.238629 cs1 DataBus test pass
702 09:20:06.239099 cs0 AddrBus test pass
703 09:20:06.239540 cs1 AddrBus test pass
704 09:20:06.239976
705 09:20:06.244348 100bdlr_step_size ps== 420
706 09:20:06.244829 result report
707 09:20:06.249964 boot times 0Enable ddr reg access
708 09:20:06.255197 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
709 09:20:06.268605 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
710 09:20:06.841001 0.0;M3 CHK:0;cm4_sp_mode 0
711 09:20:06.841642 MVN_1=0x00000000
712 09:20:06.846297 MVN_2=0x00000000
713 09:20:06.852106 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
714 09:20:06.852666 OPS=0x10
715 09:20:06.853137 ring efuse init
716 09:20:06.853566 chipver efuse init
717 09:20:06.860416 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
718 09:20:06.860901 [0.018960 Inits done]
719 09:20:06.861335 secure task start!
720 09:20:06.867911 high task start!
721 09:20:06.868404 low task start!
722 09:20:06.868827 run into bl31
723 09:20:06.874522 NOTICE: BL31: v1.3(release):4fc40b1
724 09:20:06.881472 NOTICE: BL31: Built : 15:58:17, May 22 2019
725 09:20:06.881942 NOTICE: BL31: G12A normal boot!
726 09:20:06.907650 NOTICE: BL31: BL33 decompress pass
727 09:20:06.913348 ERROR: Error initializing runtime service opteed_fast
728 09:20:08.146220
729 09:20:08.146900
730 09:20:08.154696 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
731 09:20:08.155280
732 09:20:08.155781 Model: Libre Computer AML-A311D-CC Alta
733 09:20:08.363178 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
734 09:20:08.386096 DRAM: 2 GiB (effective 3.8 GiB)
735 09:20:08.529377 Core: 408 devices, 31 uclasses, devicetree: separate
736 09:20:08.534504 WDT: Not starting watchdog@f0d0
737 09:20:08.567713 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
738 09:20:08.580041 Loading Environment from FAT... Card did not respond to voltage select! : -110
739 09:20:08.584666 ** Bad device specification mmc 0 **
740 09:20:08.595363 Card did not respond to voltage select! : -110
741 09:20:08.602626 ** Bad device specification mmc 0 **
742 09:20:08.603137 Couldn't find partition mmc 0
743 09:20:08.611373 Card did not respond to voltage select! : -110
744 09:20:08.616773 ** Bad device specification mmc 0 **
745 09:20:08.617281 Couldn't find partition mmc 0
746 09:20:08.621540 Error: could not access storage.
747 09:20:08.964225 Net: eth0: ethernet@ff3f0000
748 09:20:08.964801 starting USB...
749 09:20:09.216344 Bus usb@ff500000: Register 3000140 NbrPorts 3
750 09:20:09.216906 Starting the controller
751 09:20:09.223303 USB XHCI 1.10
752 09:20:11.385764 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
753 09:20:11.386385 bl2_stage_init 0x01
754 09:20:11.386819 bl2_stage_init 0x81
755 09:20:11.391314 hw id: 0x0000 - pwm id 0x01
756 09:20:11.391823 bl2_stage_init 0xc1
757 09:20:11.392292 bl2_stage_init 0x02
758 09:20:11.392705
759 09:20:11.396941 L0:00000000
760 09:20:11.397460 L1:20000703
761 09:20:11.397877 L2:00008067
762 09:20:11.398280 L3:14000000
763 09:20:11.402580 B2:00402000
764 09:20:11.403079 B1:e0f83180
765 09:20:11.403494
766 09:20:11.403902 TE: 58159
767 09:20:11.404364
768 09:20:11.408195 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
769 09:20:11.408697
770 09:20:11.409114 Board ID = 1
771 09:20:11.413710 Set A53 clk to 24M
772 09:20:11.414203 Set A73 clk to 24M
773 09:20:11.414616 Set clk81 to 24M
774 09:20:11.419346 A53 clk: 1200 MHz
775 09:20:11.419844 A73 clk: 1200 MHz
776 09:20:11.420300 CLK81: 166.6M
777 09:20:11.420706 smccc: 00012ab5
778 09:20:11.424905 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
779 09:20:11.430437 board id: 1
780 09:20:11.436363 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
781 09:20:11.447023 fw parse done
782 09:20:11.453032 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
783 09:20:11.495582 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
784 09:20:11.506494 PIEI prepare done
785 09:20:11.507003 fastboot data load
786 09:20:11.507425 fastboot data verify
787 09:20:11.512183 verify result: 266
788 09:20:11.517847 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
789 09:20:11.518343 LPDDR4 probe
790 09:20:11.518756 ddr clk to 1584MHz
791 09:20:11.525704 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
792 09:20:11.562931
793 09:20:11.563446 dmc_version 0001
794 09:20:11.569664 Check phy result
795 09:20:11.575484 INFO : End of CA training
796 09:20:11.575968 INFO : End of initialization
797 09:20:11.581075 INFO : Training has run successfully!
798 09:20:11.581557 Check phy result
799 09:20:11.586648 INFO : End of initialization
800 09:20:11.587123 INFO : End of read enable training
801 09:20:11.590009 INFO : End of fine write leveling
802 09:20:11.595559 INFO : End of Write leveling coarse delay
803 09:20:11.601092 INFO : Training has run successfully!
804 09:20:11.601575 Check phy result
805 09:20:11.601988 INFO : End of initialization
806 09:20:11.606704 INFO : End of read dq deskew training
807 09:20:11.612334 INFO : End of MPR read delay center optimization
808 09:20:11.612830 INFO : End of write delay center optimization
809 09:20:11.617943 INFO : End of read delay center optimization
810 09:20:11.623506 INFO : End of max read latency training
811 09:20:11.624016 INFO : Training has run successfully!
812 09:20:11.629111 1D training succeed
813 09:20:11.635023 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
814 09:20:11.682585 Check phy result
815 09:20:11.683156 INFO : End of initialization
816 09:20:11.704244 INFO : End of 2D read delay Voltage center optimization
817 09:20:11.724294 INFO : End of 2D read delay Voltage center optimization
818 09:20:11.776294 INFO : End of 2D write delay Voltage center optimization
819 09:20:11.825468 INFO : End of 2D write delay Voltage center optimization
820 09:20:11.830980 INFO : Training has run successfully!
821 09:20:11.831471
822 09:20:11.831922 channel==0
823 09:20:11.836582 RxClkDly_Margin_A0==88 ps 9
824 09:20:11.837082 TxDqDly_Margin_A0==98 ps 10
825 09:20:11.840079 RxClkDly_Margin_A1==88 ps 9
826 09:20:11.840579 TxDqDly_Margin_A1==98 ps 10
827 09:20:11.845617 TrainedVREFDQ_A0==74
828 09:20:11.846101 TrainedVREFDQ_A1==75
829 09:20:11.846538 VrefDac_Margin_A0==25
830 09:20:11.851314 DeviceVref_Margin_A0==40
831 09:20:11.851799 VrefDac_Margin_A1==23
832 09:20:11.856885 DeviceVref_Margin_A1==39
833 09:20:11.857376
834 09:20:11.857813
835 09:20:11.858241 channel==1
836 09:20:11.858664 RxClkDly_Margin_A0==98 ps 10
837 09:20:11.862615 TxDqDly_Margin_A0==98 ps 10
838 09:20:11.863093 RxClkDly_Margin_A1==88 ps 9
839 09:20:11.868332 TxDqDly_Margin_A1==88 ps 9
840 09:20:11.868815 TrainedVREFDQ_A0==77
841 09:20:11.869245 TrainedVREFDQ_A1==77
842 09:20:11.873579 VrefDac_Margin_A0==22
843 09:20:11.874052 DeviceVref_Margin_A0==37
844 09:20:11.879160 VrefDac_Margin_A1==24
845 09:20:11.879629 DeviceVref_Margin_A1==37
846 09:20:11.880091
847 09:20:11.884906 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
848 09:20:11.885384
849 09:20:11.912878 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000018 00000017 00000019 00000018 00000019 00000019 00000018 00000017 00000018 00000017 0000001a 00000018 00000017 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
850 09:20:11.918461 2D training succeed
851 09:20:11.923909 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
852 09:20:11.924413 auto size-- 65535DDR cs0 size: 2048MB
853 09:20:11.929553 DDR cs1 size: 2048MB
854 09:20:11.930029 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
855 09:20:11.935151 cs0 DataBus test pass
856 09:20:11.935622 cs1 DataBus test pass
857 09:20:11.936090 cs0 AddrBus test pass
858 09:20:11.940708 cs1 AddrBus test pass
859 09:20:11.941179
860 09:20:11.941607 100bdlr_step_size ps== 420
861 09:20:11.942043 result report
862 09:20:11.946327 boot times 0Enable ddr reg access
863 09:20:11.953869 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
864 09:20:11.967416 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
865 09:20:12.539409 0.0;M3 CHK:0;cm4_sp_mode 0
866 09:20:12.540068 MVN_1=0x00000000
867 09:20:12.544801 MVN_2=0x00000000
868 09:20:12.550570 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
869 09:20:12.551085 OPS=0x10
870 09:20:12.551545 ring efuse init
871 09:20:12.552104 chipver efuse init
872 09:20:12.556195 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
873 09:20:12.561757 [0.018961 Inits done]
874 09:20:12.562387 secure task start!
875 09:20:12.562942 high task start!
876 09:20:12.566453 low task start!
877 09:20:12.567081 run into bl31
878 09:20:12.573036 NOTICE: BL31: v1.3(release):4fc40b1
879 09:20:12.580849 NOTICE: BL31: Built : 15:58:17, May 22 2019
880 09:20:12.581502 NOTICE: BL31: G12A normal boot!
881 09:20:12.606211 NOTICE: BL31: BL33 decompress pass
882 09:20:12.611846 ERROR: Error initializing runtime service opteed_fast
883 09:20:13.844840
884 09:20:13.845614
885 09:20:13.853196 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
886 09:20:13.853828
887 09:20:13.854389 Model: Libre Computer AML-A311D-CC Alta
888 09:20:14.061644 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
889 09:20:14.085036 DRAM: 2 GiB (effective 3.8 GiB)
890 09:20:14.228064 Core: 408 devices, 31 uclasses, devicetree: separate
891 09:20:14.233873 WDT: Not starting watchdog@f0d0
892 09:20:14.266139 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
893 09:20:14.278694 Loading Environment from FAT... Card did not respond to voltage select! : -110
894 09:20:14.283602 ** Bad device specification mmc 0 **
895 09:20:14.293892 Card did not respond to voltage select! : -110
896 09:20:14.301566 ** Bad device specification mmc 0 **
897 09:20:14.302174 Couldn't find partition mmc 0
898 09:20:14.309892 Card did not respond to voltage select! : -110
899 09:20:14.315390 ** Bad device specification mmc 0 **
900 09:20:14.316010 Couldn't find partition mmc 0
901 09:20:14.319444 Error: could not access storage.
902 09:20:14.662937 Net: eth0: ethernet@ff3f0000
903 09:20:14.663658 starting USB...
904 09:20:14.914859 Bus usb@ff500000: Register 3000140 NbrPorts 3
905 09:20:14.915563 Starting the controller
906 09:20:14.921681 USB XHCI 1.10
907 09:20:16.785161 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
908 09:20:16.785579 bl2_stage_init 0x01
909 09:20:16.785833 bl2_stage_init 0x81
910 09:20:16.790768 hw id: 0x0000 - pwm id 0x01
911 09:20:16.791089 bl2_stage_init 0xc1
912 09:20:16.791308 bl2_stage_init 0x02
913 09:20:16.791515
914 09:20:16.796289 L0:00000000
915 09:20:16.796594 L1:20000703
916 09:20:16.796804 L2:00008067
917 09:20:16.797006 L3:14000000
918 09:20:16.801893 B2:00402000
919 09:20:16.802179 B1:e0f83180
920 09:20:16.802389
921 09:20:16.802590 TE: 58124
922 09:20:16.802797
923 09:20:16.807459 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
924 09:20:16.807868
925 09:20:16.808214 Board ID = 1
926 09:20:16.813075 Set A53 clk to 24M
927 09:20:16.813360 Set A73 clk to 24M
928 09:20:16.813566 Set clk81 to 24M
929 09:20:16.818641 A53 clk: 1200 MHz
930 09:20:16.818922 A73 clk: 1200 MHz
931 09:20:16.819127 CLK81: 166.6M
932 09:20:16.819323 smccc: 00012a91
933 09:20:16.824397 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
934 09:20:16.829905 board id: 1
935 09:20:16.835752 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
936 09:20:16.846483 fw parse done
937 09:20:16.852415 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
938 09:20:16.895085 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
939 09:20:16.905963 PIEI prepare done
940 09:20:16.906509 fastboot data load
941 09:20:16.906953 fastboot data verify
942 09:20:16.911583 verify result: 266
943 09:20:16.917145 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
944 09:20:16.917658 LPDDR4 probe
945 09:20:16.918106 ddr clk to 1584MHz
946 09:20:16.925247 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
947 09:20:16.962516
948 09:20:16.963006 dmc_version 0001
949 09:20:16.969310 Check phy result
950 09:20:16.975155 INFO : End of CA training
951 09:20:16.975633 INFO : End of initialization
952 09:20:16.980638 INFO : Training has run successfully!
953 09:20:16.981149 Check phy result
954 09:20:16.986324 INFO : End of initialization
955 09:20:16.986790 INFO : End of read enable training
956 09:20:16.989715 INFO : End of fine write leveling
957 09:20:16.995071 INFO : End of Write leveling coarse delay
958 09:20:17.000793 INFO : Training has run successfully!
959 09:20:17.001255 Check phy result
960 09:20:17.001666 INFO : End of initialization
961 09:20:17.006215 INFO : End of read dq deskew training
962 09:20:17.011841 INFO : End of MPR read delay center optimization
963 09:20:17.012350 INFO : End of write delay center optimization
964 09:20:17.017466 INFO : End of read delay center optimization
965 09:20:17.023088 INFO : End of max read latency training
966 09:20:17.023544 INFO : Training has run successfully!
967 09:20:17.028546 1D training succeed
968 09:20:17.034539 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
969 09:20:17.082155 Check phy result
970 09:20:17.082651 INFO : End of initialization
971 09:20:17.103070 INFO : End of 2D read delay Voltage center optimization
972 09:20:17.124265 INFO : End of 2D read delay Voltage center optimization
973 09:20:17.176278 INFO : End of 2D write delay Voltage center optimization
974 09:20:17.225721 INFO : End of 2D write delay Voltage center optimization
975 09:20:17.231249 INFO : Training has run successfully!
976 09:20:17.231726
977 09:20:17.232193 channel==0
978 09:20:17.236800 RxClkDly_Margin_A0==88 ps 9
979 09:20:17.237269 TxDqDly_Margin_A0==98 ps 10
980 09:20:17.242400 RxClkDly_Margin_A1==88 ps 9
981 09:20:17.242867 TxDqDly_Margin_A1==88 ps 9
982 09:20:17.243286 TrainedVREFDQ_A0==74
983 09:20:17.248186 TrainedVREFDQ_A1==74
984 09:20:17.248652 VrefDac_Margin_A0==24
985 09:20:17.249068 DeviceVref_Margin_A0==40
986 09:20:17.253608 VrefDac_Margin_A1==25
987 09:20:17.254223 DeviceVref_Margin_A1==40
988 09:20:17.254713
989 09:20:17.255154
990 09:20:17.255663 channel==1
991 09:20:17.259146 RxClkDly_Margin_A0==88 ps 9
992 09:20:17.259645 TxDqDly_Margin_A0==98 ps 10
993 09:20:17.264803 RxClkDly_Margin_A1==88 ps 9
994 09:20:17.265350 TxDqDly_Margin_A1==88 ps 9
995 09:20:17.270411 TrainedVREFDQ_A0==77
996 09:20:17.270876 TrainedVREFDQ_A1==77
997 09:20:17.271271 VrefDac_Margin_A0==22
998 09:20:17.276132 DeviceVref_Margin_A0==37
999 09:20:17.276590 VrefDac_Margin_A1==24
1000 09:20:17.281521 DeviceVref_Margin_A1==37
1001 09:20:17.281965
1002 09:20:17.282362 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
1003 09:20:17.282753
1004 09:20:17.315160 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000017 00000019 00000018 0000001a 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
1005 09:20:17.315746 2D training succeed
1006 09:20:17.320732 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
1007 09:20:17.326425 auto size-- 65535DDR cs0 size: 2048MB
1008 09:20:17.326945 DDR cs1 size: 2048MB
1009 09:20:17.331856 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
1010 09:20:17.332434 cs0 DataBus test pass
1011 09:20:17.337453 cs1 DataBus test pass
1012 09:20:17.337959 cs0 AddrBus test pass
1013 09:20:17.338357 cs1 AddrBus test pass
1014 09:20:17.338746
1015 09:20:17.343073 100bdlr_step_size ps== 420
1016 09:20:17.343611 result report
1017 09:20:17.348648 boot times 0Enable ddr reg access
1018 09:20:17.353936 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
1019 09:20:17.367320 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
1020 09:20:17.941120 0.0;M3 CHK:0;cm4_sp_mode 0
1021 09:20:17.941753 MVN_1=0x00000000
1022 09:20:17.946573 MVN_2=0x00000000
1023 09:20:17.952294 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
1024 09:20:17.952870 OPS=0x10
1025 09:20:17.953352 ring efuse init
1026 09:20:17.953808 chipver efuse init
1027 09:20:17.957856 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
1028 09:20:17.963479 [0.018961 Inits done]
1029 09:20:17.964043 secure task start!
1030 09:20:17.964496 high task start!
1031 09:20:17.968140 low task start!
1032 09:20:17.968681 run into bl31
1033 09:20:17.974712 NOTICE: BL31: v1.3(release):4fc40b1
1034 09:20:17.982489 NOTICE: BL31: Built : 15:58:17, May 22 2019
1035 09:20:17.982966 NOTICE: BL31: G12A normal boot!
1036 09:20:18.007948 NOTICE: BL31: BL33 decompress pass
1037 09:20:18.013564 ERROR: Error initializing runtime service opteed_fast
1038 09:20:19.246613
1039 09:20:19.247127
1040 09:20:19.254954 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
1041 09:20:19.255639
1042 09:20:19.256437 Model: Libre Computer AML-A311D-CC Alta
1043 09:20:19.463446 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
1044 09:20:19.486776 DRAM: 2 GiB (effective 3.8 GiB)
1045 09:20:19.629752 Core: 408 devices, 31 uclasses, devicetree: separate
1046 09:20:19.635597 WDT: Not starting watchdog@f0d0
1047 09:20:19.667889 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
1048 09:20:19.680397 Loading Environment from FAT... Card did not respond to voltage select! : -110
1049 09:20:19.685364 ** Bad device specification mmc 0 **
1050 09:20:19.695668 Card did not respond to voltage select! : -110
1051 09:20:19.703307 ** Bad device specification mmc 0 **
1052 09:20:19.703825 Couldn't find partition mmc 0
1053 09:20:19.711670 Card did not respond to voltage select! : -110
1054 09:20:19.717150 ** Bad device specification mmc 0 **
1055 09:20:19.717663 Couldn't find partition mmc 0
1056 09:20:19.722225 Error: could not access storage.
1057 09:20:20.064641 Net: eth0: ethernet@ff3f0000
1058 09:20:20.065225 starting USB...
1059 09:20:20.316571 Bus usb@ff500000: Register 3000140 NbrPorts 3
1060 09:20:20.317144 Starting the controller
1061 09:20:20.322620 USB XHCI 1.10
1062 09:20:21.877431 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
1063 09:20:21.885777 scanning usb for storage devices... 0 Storage Device(s) found
1065 09:20:21.937438 Hit any key to stop autoboot: 1
1066 09:20:21.938375 end: 2.4.2 bootloader-interrupt (duration 00:00:37) [common]
1067 09:20:21.939001 start: 2.4.3 bootloader-commands (timeout 00:04:23) [common]
1068 09:20:21.939464 Setting prompt string to ['=>']
1069 09:20:21.939934 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:23)
1070 09:20:21.953294 0
1071 09:20:21.954280 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1072 09:20:21.954826 Sending with 10 millisecond of delay
1074 09:20:23.089527 => setenv autoload no
1075 09:20:23.100351 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:22)
1076 09:20:23.105289 setenv autoload no
1077 09:20:23.106050 Sending with 10 millisecond of delay
1079 09:20:24.903784 => setenv initrd_high 0xffffffff
1080 09:20:24.914614 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:20)
1081 09:20:24.915427 setenv initrd_high 0xffffffff
1082 09:20:24.916132 Sending with 10 millisecond of delay
1084 09:20:26.534260 => setenv fdt_high 0xffffffff
1085 09:20:26.545288 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1086 09:20:26.547155 setenv fdt_high 0xffffffff
1087 09:20:26.549191 Sending with 10 millisecond of delay
1089 09:20:26.841223 => dhcp
1090 09:20:26.852042 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1091 09:20:26.852850 dhcp
1092 09:20:26.853285 Speed: 1000, full duplex
1093 09:20:26.853694 BOOTP broadcast 1
1094 09:20:26.859927 DHCP client bound to address 192.168.6.27 (7 ms)
1095 09:20:26.860650 Sending with 10 millisecond of delay
1097 09:20:28.537364 => setenv serverip 192.168.6.2
1098 09:20:28.548173 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:16)
1099 09:20:28.549105 setenv serverip 192.168.6.2
1100 09:20:28.549794 Sending with 10 millisecond of delay
1102 09:20:32.274705 => tftpboot 0x01080000 939213/tftp-deploy-i__hvijd/kernel/uImage
1103 09:20:32.285591 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:12)
1104 09:20:32.286216 tftpboot 0x01080000 939213/tftp-deploy-i__hvijd/kernel/uImage
1105 09:20:32.286511 Speed: 1000, full duplex
1106 09:20:32.286760 Using ethernet@ff3f0000 device
1107 09:20:32.287803 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1108 09:20:32.293286 Filename '939213/tftp-deploy-i__hvijd/kernel/uImage'.
1109 09:20:32.297149 Load address: 0x1080000
1110 09:20:35.087829 Loading: *################################################## 43.6 MiB
1111 09:20:35.088361 15.6 MiB/s
1112 09:20:35.088624 done
1113 09:20:35.092214 Bytes transferred = 45716032 (2b99240 hex)
1114 09:20:35.092754 Sending with 10 millisecond of delay
1116 09:20:39.779916 => tftpboot 0x08000000 939213/tftp-deploy-i__hvijd/ramdisk/ramdisk.cpio.gz.uboot
1117 09:20:39.790762 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:05)
1118 09:20:39.791638 tftpboot 0x08000000 939213/tftp-deploy-i__hvijd/ramdisk/ramdisk.cpio.gz.uboot
1119 09:20:39.792165 Speed: 1000, full duplex
1120 09:20:39.792625 Using ethernet@ff3f0000 device
1121 09:20:39.793405 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1122 09:20:39.805136 Filename '939213/tftp-deploy-i__hvijd/ramdisk/ramdisk.cpio.gz.uboot'.
1123 09:20:39.805568 Load address: 0x8000000
1124 09:20:48.945575 Loading: *#######T ########################################## UDP wrong checksum 0000000f 00001f93
1125 09:20:53.945915 T UDP wrong checksum 0000000f 00001f93
1126 09:20:56.205562 UDP wrong checksum 000000ff 000067fb
1127 09:20:56.246570 UDP wrong checksum 000000ff 0000eced
1128 09:21:03.949777 T T UDP wrong checksum 0000000f 00001f93
1129 09:21:07.425416 UDP wrong checksum 000000ff 0000d89b
1130 09:21:07.471562 UDP wrong checksum 000000ff 0000748e
1131 09:21:13.249164 T UDP wrong checksum 000000ff 00008bf2
1132 09:21:13.261058 UDP wrong checksum 000000ff 000020e5
1133 09:21:23.953503 T T T UDP wrong checksum 0000000f 00001f93
1134 09:21:38.957815 T T
1135 09:21:38.958441 Retry count exceeded; starting again
1137 09:21:38.959825 end: 2.4.3 bootloader-commands (duration 00:01:17) [common]
1140 09:21:38.961713 end: 2.4 uboot-commands (duration 00:01:54) [common]
1142 09:21:38.963065 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
1144 09:21:38.964098 end: 2 uboot-action (duration 00:01:54) [common]
1146 09:21:38.965554 Cleaning after the job
1147 09:21:38.966047 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/939213/tftp-deploy-i__hvijd/ramdisk
1148 09:21:38.967106 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/939213/tftp-deploy-i__hvijd/kernel
1149 09:21:38.995419 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/939213/tftp-deploy-i__hvijd/dtb
1150 09:21:38.996767 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/939213/tftp-deploy-i__hvijd/modules
1151 09:21:39.014109 start: 4.1 power-off (timeout 00:00:30) [common]
1152 09:21:39.014714 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1153 09:21:39.063413 >> OK - accepted request
1154 09:21:39.065448 Returned 0 in 0 seconds
1155 09:21:39.166750 end: 4.1 power-off (duration 00:00:00) [common]
1157 09:21:39.168621 start: 4.2 read-feedback (timeout 00:10:00) [common]
1158 09:21:39.170040 Listened to connection for namespace 'common' for up to 1s
1159 09:21:40.170628 Finalising connection for namespace 'common'
1160 09:21:40.171438 Disconnecting from shell: Finalise
1161 09:21:40.172146 =>
1162 09:21:40.273515 end: 4.2 read-feedback (duration 00:00:01) [common]
1163 09:21:40.274264 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/939213
1164 09:21:41.297975 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/939213
1165 09:21:41.298701 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.