Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 1
- Kernel Warnings: 5
- Errors: 0
- Boot result: PASS
- Kernel Errors: 3
1 09:04:03.881023 lava-dispatcher, installed at version: 2024.01
2 09:04:03.881865 start: 0 validate
3 09:04:03.882427 Start time: 2024-11-05 09:04:03.882391+00:00 (UTC)
4 09:04:03.883089 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 09:04:03.883727 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 09:04:03.928214 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 09:04:03.928827 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fpending-fixes%2Fv6.12-rc6-192-g566383b19a748%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 09:04:03.963296 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 09:04:03.963975 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fpending-fixes%2Fv6.12-rc6-192-g566383b19a748%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 09:04:03.996092 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 09:04:03.996628 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 09:04:04.025021 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 09:04:04.025532 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fpending-fixes%2Fv6.12-rc6-192-g566383b19a748%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
14 09:04:04.059065 validate duration: 0.18
16 09:04:04.060007 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 09:04:04.060377 start: 1.1 download-retry (timeout 00:10:00) [common]
18 09:04:04.060728 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 09:04:04.061352 Not decompressing ramdisk as can be used compressed.
20 09:04:04.061840 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 09:04:04.062137 saving as /var/lib/lava/dispatcher/tmp/939161/tftp-deploy-2ufez62e/ramdisk/initrd.cpio.gz
22 09:04:04.062439 total size: 5628169 (5 MB)
23 09:04:04.100525 progress 0 % (0 MB)
24 09:04:04.106222 progress 5 % (0 MB)
25 09:04:04.113333 progress 10 % (0 MB)
26 09:04:04.118561 progress 15 % (0 MB)
27 09:04:04.123419 progress 20 % (1 MB)
28 09:04:04.127304 progress 25 % (1 MB)
29 09:04:04.131619 progress 30 % (1 MB)
30 09:04:04.136019 progress 35 % (1 MB)
31 09:04:04.139918 progress 40 % (2 MB)
32 09:04:04.143966 progress 45 % (2 MB)
33 09:04:04.147774 progress 50 % (2 MB)
34 09:04:04.152146 progress 55 % (2 MB)
35 09:04:04.156172 progress 60 % (3 MB)
36 09:04:04.159936 progress 65 % (3 MB)
37 09:04:04.164216 progress 70 % (3 MB)
38 09:04:04.167838 progress 75 % (4 MB)
39 09:04:04.172004 progress 80 % (4 MB)
40 09:04:04.176112 progress 85 % (4 MB)
41 09:04:04.180267 progress 90 % (4 MB)
42 09:04:04.184316 progress 95 % (5 MB)
43 09:04:04.187667 progress 100 % (5 MB)
44 09:04:04.188357 5 MB downloaded in 0.13 s (42.63 MB/s)
45 09:04:04.188898 end: 1.1.1 http-download (duration 00:00:00) [common]
47 09:04:04.189798 end: 1.1 download-retry (duration 00:00:00) [common]
48 09:04:04.190104 start: 1.2 download-retry (timeout 00:10:00) [common]
49 09:04:04.190377 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 09:04:04.190857 downloading http://storage.kernelci.org/next/pending-fixes/v6.12-rc6-192-g566383b19a748/arm64/defconfig/gcc-12/kernel/Image
51 09:04:04.191108 saving as /var/lib/lava/dispatcher/tmp/939161/tftp-deploy-2ufez62e/kernel/Image
52 09:04:04.191319 total size: 45715968 (43 MB)
53 09:04:04.191530 No compression specified
54 09:04:04.229985 progress 0 % (0 MB)
55 09:04:04.259574 progress 5 % (2 MB)
56 09:04:04.289539 progress 10 % (4 MB)
57 09:04:04.319498 progress 15 % (6 MB)
58 09:04:04.349584 progress 20 % (8 MB)
59 09:04:04.378896 progress 25 % (10 MB)
60 09:04:04.409271 progress 30 % (13 MB)
61 09:04:04.439244 progress 35 % (15 MB)
62 09:04:04.469167 progress 40 % (17 MB)
63 09:04:04.498345 progress 45 % (19 MB)
64 09:04:04.528280 progress 50 % (21 MB)
65 09:04:04.558013 progress 55 % (24 MB)
66 09:04:04.587485 progress 60 % (26 MB)
67 09:04:04.617072 progress 65 % (28 MB)
68 09:04:04.646878 progress 70 % (30 MB)
69 09:04:04.676436 progress 75 % (32 MB)
70 09:04:04.706050 progress 80 % (34 MB)
71 09:04:04.735243 progress 85 % (37 MB)
72 09:04:04.764466 progress 90 % (39 MB)
73 09:04:04.793690 progress 95 % (41 MB)
74 09:04:04.822605 progress 100 % (43 MB)
75 09:04:04.823168 43 MB downloaded in 0.63 s (69.00 MB/s)
76 09:04:04.823688 end: 1.2.1 http-download (duration 00:00:01) [common]
78 09:04:04.824570 end: 1.2 download-retry (duration 00:00:01) [common]
79 09:04:04.824864 start: 1.3 download-retry (timeout 00:09:59) [common]
80 09:04:04.825140 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 09:04:04.825621 downloading http://storage.kernelci.org/next/pending-fixes/v6.12-rc6-192-g566383b19a748/arm64/defconfig/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
82 09:04:04.825897 saving as /var/lib/lava/dispatcher/tmp/939161/tftp-deploy-2ufez62e/dtb/meson-g12b-a311d-libretech-cc.dtb
83 09:04:04.826121 total size: 54703 (0 MB)
84 09:04:04.826341 No compression specified
85 09:04:04.868806 progress 59 % (0 MB)
86 09:04:04.869686 progress 100 % (0 MB)
87 09:04:04.870274 0 MB downloaded in 0.04 s (1.18 MB/s)
88 09:04:04.870805 end: 1.3.1 http-download (duration 00:00:00) [common]
90 09:04:04.871656 end: 1.3 download-retry (duration 00:00:00) [common]
91 09:04:04.871936 start: 1.4 download-retry (timeout 00:09:59) [common]
92 09:04:04.872248 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 09:04:04.872724 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 09:04:04.872980 saving as /var/lib/lava/dispatcher/tmp/939161/tftp-deploy-2ufez62e/nfsrootfs/full.rootfs.tar
95 09:04:04.873198 total size: 120894716 (115 MB)
96 09:04:04.873416 Using unxz to decompress xz
97 09:04:04.908920 progress 0 % (0 MB)
98 09:04:05.705307 progress 5 % (5 MB)
99 09:04:06.543572 progress 10 % (11 MB)
100 09:04:07.337918 progress 15 % (17 MB)
101 09:04:08.078443 progress 20 % (23 MB)
102 09:04:08.680443 progress 25 % (28 MB)
103 09:04:09.514842 progress 30 % (34 MB)
104 09:04:10.310758 progress 35 % (40 MB)
105 09:04:10.655012 progress 40 % (46 MB)
106 09:04:11.038854 progress 45 % (51 MB)
107 09:04:11.767628 progress 50 % (57 MB)
108 09:04:12.672061 progress 55 % (63 MB)
109 09:04:13.480816 progress 60 % (69 MB)
110 09:04:14.251573 progress 65 % (74 MB)
111 09:04:15.055146 progress 70 % (80 MB)
112 09:04:15.904186 progress 75 % (86 MB)
113 09:04:16.710224 progress 80 % (92 MB)
114 09:04:17.474676 progress 85 % (98 MB)
115 09:04:18.336732 progress 90 % (103 MB)
116 09:04:19.175236 progress 95 % (109 MB)
117 09:04:20.077867 progress 100 % (115 MB)
118 09:04:20.095635 115 MB downloaded in 15.22 s (7.57 MB/s)
119 09:04:20.096708 end: 1.4.1 http-download (duration 00:00:15) [common]
121 09:04:20.098304 end: 1.4 download-retry (duration 00:00:15) [common]
122 09:04:20.098816 start: 1.5 download-retry (timeout 00:09:44) [common]
123 09:04:20.099320 start: 1.5.1 http-download (timeout 00:09:44) [common]
124 09:04:20.100159 downloading http://storage.kernelci.org/next/pending-fixes/v6.12-rc6-192-g566383b19a748/arm64/defconfig/gcc-12/modules.tar.xz
125 09:04:20.100643 saving as /var/lib/lava/dispatcher/tmp/939161/tftp-deploy-2ufez62e/modules/modules.tar
126 09:04:20.101046 total size: 11615948 (11 MB)
127 09:04:20.101458 Using unxz to decompress xz
128 09:04:20.149570 progress 0 % (0 MB)
129 09:04:20.222321 progress 5 % (0 MB)
130 09:04:20.298200 progress 10 % (1 MB)
131 09:04:20.401901 progress 15 % (1 MB)
132 09:04:20.495350 progress 20 % (2 MB)
133 09:04:20.576258 progress 25 % (2 MB)
134 09:04:20.653314 progress 30 % (3 MB)
135 09:04:20.733071 progress 35 % (3 MB)
136 09:04:20.807182 progress 40 % (4 MB)
137 09:04:20.885661 progress 45 % (5 MB)
138 09:04:20.972630 progress 50 % (5 MB)
139 09:04:21.052539 progress 55 % (6 MB)
140 09:04:21.140134 progress 60 % (6 MB)
141 09:04:21.222825 progress 65 % (7 MB)
142 09:04:21.306143 progress 70 % (7 MB)
143 09:04:21.387192 progress 75 % (8 MB)
144 09:04:21.471710 progress 80 % (8 MB)
145 09:04:21.552570 progress 85 % (9 MB)
146 09:04:21.635780 progress 90 % (10 MB)
147 09:04:21.709356 progress 95 % (10 MB)
148 09:04:21.786085 progress 100 % (11 MB)
149 09:04:21.798472 11 MB downloaded in 1.70 s (6.53 MB/s)
150 09:04:21.799051 end: 1.5.1 http-download (duration 00:00:02) [common]
152 09:04:21.799871 end: 1.5 download-retry (duration 00:00:02) [common]
153 09:04:21.800304 start: 1.6 prepare-tftp-overlay (timeout 00:09:42) [common]
154 09:04:21.800829 start: 1.6.1 extract-nfsrootfs (timeout 00:09:42) [common]
155 09:04:39.163399 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/939161/extract-nfsrootfs-1rnnjbw7
156 09:04:39.165449 end: 1.6.1 extract-nfsrootfs (duration 00:00:17) [common]
157 09:04:39.165851 start: 1.6.2 lava-overlay (timeout 00:09:25) [common]
158 09:04:39.166622 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/939161/lava-overlay-_hmre322
159 09:04:39.167148 makedir: /var/lib/lava/dispatcher/tmp/939161/lava-overlay-_hmre322/lava-939161/bin
160 09:04:39.167570 makedir: /var/lib/lava/dispatcher/tmp/939161/lava-overlay-_hmre322/lava-939161/tests
161 09:04:39.167962 makedir: /var/lib/lava/dispatcher/tmp/939161/lava-overlay-_hmre322/lava-939161/results
162 09:04:39.168420 Creating /var/lib/lava/dispatcher/tmp/939161/lava-overlay-_hmre322/lava-939161/bin/lava-add-keys
163 09:04:39.169086 Creating /var/lib/lava/dispatcher/tmp/939161/lava-overlay-_hmre322/lava-939161/bin/lava-add-sources
164 09:04:39.169724 Creating /var/lib/lava/dispatcher/tmp/939161/lava-overlay-_hmre322/lava-939161/bin/lava-background-process-start
165 09:04:39.170285 Creating /var/lib/lava/dispatcher/tmp/939161/lava-overlay-_hmre322/lava-939161/bin/lava-background-process-stop
166 09:04:39.170957 Creating /var/lib/lava/dispatcher/tmp/939161/lava-overlay-_hmre322/lava-939161/bin/lava-common-functions
167 09:04:39.171565 Creating /var/lib/lava/dispatcher/tmp/939161/lava-overlay-_hmre322/lava-939161/bin/lava-echo-ipv4
168 09:04:39.172151 Creating /var/lib/lava/dispatcher/tmp/939161/lava-overlay-_hmre322/lava-939161/bin/lava-install-packages
169 09:04:39.172712 Creating /var/lib/lava/dispatcher/tmp/939161/lava-overlay-_hmre322/lava-939161/bin/lava-installed-packages
170 09:04:39.173279 Creating /var/lib/lava/dispatcher/tmp/939161/lava-overlay-_hmre322/lava-939161/bin/lava-os-build
171 09:04:39.173870 Creating /var/lib/lava/dispatcher/tmp/939161/lava-overlay-_hmre322/lava-939161/bin/lava-probe-channel
172 09:04:39.174450 Creating /var/lib/lava/dispatcher/tmp/939161/lava-overlay-_hmre322/lava-939161/bin/lava-probe-ip
173 09:04:39.175016 Creating /var/lib/lava/dispatcher/tmp/939161/lava-overlay-_hmre322/lava-939161/bin/lava-target-ip
174 09:04:39.175650 Creating /var/lib/lava/dispatcher/tmp/939161/lava-overlay-_hmre322/lava-939161/bin/lava-target-mac
175 09:04:39.176258 Creating /var/lib/lava/dispatcher/tmp/939161/lava-overlay-_hmre322/lava-939161/bin/lava-target-storage
176 09:04:39.176831 Creating /var/lib/lava/dispatcher/tmp/939161/lava-overlay-_hmre322/lava-939161/bin/lava-test-case
177 09:04:39.177383 Creating /var/lib/lava/dispatcher/tmp/939161/lava-overlay-_hmre322/lava-939161/bin/lava-test-event
178 09:04:39.177922 Creating /var/lib/lava/dispatcher/tmp/939161/lava-overlay-_hmre322/lava-939161/bin/lava-test-feedback
179 09:04:39.178467 Creating /var/lib/lava/dispatcher/tmp/939161/lava-overlay-_hmre322/lava-939161/bin/lava-test-raise
180 09:04:39.179010 Creating /var/lib/lava/dispatcher/tmp/939161/lava-overlay-_hmre322/lava-939161/bin/lava-test-reference
181 09:04:39.179560 Creating /var/lib/lava/dispatcher/tmp/939161/lava-overlay-_hmre322/lava-939161/bin/lava-test-runner
182 09:04:39.180147 Creating /var/lib/lava/dispatcher/tmp/939161/lava-overlay-_hmre322/lava-939161/bin/lava-test-set
183 09:04:39.180702 Creating /var/lib/lava/dispatcher/tmp/939161/lava-overlay-_hmre322/lava-939161/bin/lava-test-shell
184 09:04:39.181272 Updating /var/lib/lava/dispatcher/tmp/939161/lava-overlay-_hmre322/lava-939161/bin/lava-add-keys (debian)
185 09:04:39.181863 Updating /var/lib/lava/dispatcher/tmp/939161/lava-overlay-_hmre322/lava-939161/bin/lava-add-sources (debian)
186 09:04:39.182453 Updating /var/lib/lava/dispatcher/tmp/939161/lava-overlay-_hmre322/lava-939161/bin/lava-install-packages (debian)
187 09:04:39.183023 Updating /var/lib/lava/dispatcher/tmp/939161/lava-overlay-_hmre322/lava-939161/bin/lava-installed-packages (debian)
188 09:04:39.183587 Updating /var/lib/lava/dispatcher/tmp/939161/lava-overlay-_hmre322/lava-939161/bin/lava-os-build (debian)
189 09:04:39.184112 Creating /var/lib/lava/dispatcher/tmp/939161/lava-overlay-_hmre322/lava-939161/environment
190 09:04:39.184556 LAVA metadata
191 09:04:39.184861 - LAVA_JOB_ID=939161
192 09:04:39.185098 - LAVA_DISPATCHER_IP=192.168.6.2
193 09:04:39.185502 start: 1.6.2.1 ssh-authorize (timeout 00:09:25) [common]
194 09:04:39.186568 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
195 09:04:39.186941 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:25) [common]
196 09:04:39.187171 skipped lava-vland-overlay
197 09:04:39.187438 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
198 09:04:39.187719 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:25) [common]
199 09:04:39.187961 skipped lava-multinode-overlay
200 09:04:39.188271 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
201 09:04:39.188557 start: 1.6.2.4 test-definition (timeout 00:09:25) [common]
202 09:04:39.188837 Loading test definitions
203 09:04:39.189147 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:25) [common]
204 09:04:39.189391 Using /lava-939161 at stage 0
205 09:04:39.190543 uuid=939161_1.6.2.4.1 testdef=None
206 09:04:39.190894 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
207 09:04:39.191198 start: 1.6.2.4.2 test-overlay (timeout 00:09:25) [common]
208 09:04:39.193020 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
210 09:04:39.193913 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:25) [common]
211 09:04:39.196115 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
213 09:04:39.197066 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:25) [common]
214 09:04:39.199110 runner path: /var/lib/lava/dispatcher/tmp/939161/lava-overlay-_hmre322/lava-939161/0/tests/0_timesync-off test_uuid 939161_1.6.2.4.1
215 09:04:39.199772 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
217 09:04:39.200720 start: 1.6.2.4.5 git-repo-action (timeout 00:09:25) [common]
218 09:04:39.201002 Using /lava-939161 at stage 0
219 09:04:39.201407 Fetching tests from https://github.com/kernelci/test-definitions.git
220 09:04:39.201737 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/939161/lava-overlay-_hmre322/lava-939161/0/tests/1_kselftest-alsa'
221 09:04:42.516164 Running '/usr/bin/git checkout kernelci.org
222 09:04:43.003676 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/939161/lava-overlay-_hmre322/lava-939161/0/tests/1_kselftest-alsa/automated/linux/kselftest/kselftest.yaml
223 09:04:43.005184 uuid=939161_1.6.2.4.5 testdef=None
224 09:04:43.005558 end: 1.6.2.4.5 git-repo-action (duration 00:00:04) [common]
226 09:04:43.006328 start: 1.6.2.4.6 test-overlay (timeout 00:09:21) [common]
227 09:04:43.009321 end: 1.6.2.4.6 test-overlay (duration 00:00:00) [common]
229 09:04:43.010193 start: 1.6.2.4.7 test-install-overlay (timeout 00:09:21) [common]
230 09:04:43.014168 end: 1.6.2.4.7 test-install-overlay (duration 00:00:00) [common]
232 09:04:43.015106 start: 1.6.2.4.8 test-runscript-overlay (timeout 00:09:21) [common]
233 09:04:43.019069 runner path: /var/lib/lava/dispatcher/tmp/939161/lava-overlay-_hmre322/lava-939161/0/tests/1_kselftest-alsa test_uuid 939161_1.6.2.4.5
234 09:04:43.019429 BOARD='meson-g12b-a311d-libretech-cc'
235 09:04:43.019637 BRANCH='next'
236 09:04:43.019838 SKIPFILE='/dev/null'
237 09:04:43.020062 SKIP_INSTALL='True'
238 09:04:43.020266 TESTPROG_URL='http://storage.kernelci.org/next/pending-fixes/v6.12-rc6-192-g566383b19a748/arm64/defconfig/gcc-12/kselftest.tar.xz'
239 09:04:43.020468 TST_CASENAME=''
240 09:04:43.020668 TST_CMDFILES='alsa'
241 09:04:43.021323 end: 1.6.2.4.8 test-runscript-overlay (duration 00:00:00) [common]
243 09:04:43.022213 Creating lava-test-runner.conf files
244 09:04:43.022436 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/939161/lava-overlay-_hmre322/lava-939161/0 for stage 0
245 09:04:43.022850 - 0_timesync-off
246 09:04:43.023110 - 1_kselftest-alsa
247 09:04:43.023478 end: 1.6.2.4 test-definition (duration 00:00:04) [common]
248 09:04:43.023779 start: 1.6.2.5 compress-overlay (timeout 00:09:21) [common]
249 09:05:06.419813 end: 1.6.2.5 compress-overlay (duration 00:00:23) [common]
250 09:05:06.420263 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:08:58) [common]
251 09:05:06.420534 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
252 09:05:06.420809 end: 1.6.2 lava-overlay (duration 00:00:27) [common]
253 09:05:06.421079 start: 1.6.3 extract-overlay-ramdisk (timeout 00:08:58) [common]
254 09:05:07.058743 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:01) [common]
255 09:05:07.059227 start: 1.6.4 extract-modules (timeout 00:08:57) [common]
256 09:05:07.059505 extracting modules file /var/lib/lava/dispatcher/tmp/939161/tftp-deploy-2ufez62e/modules/modules.tar to /var/lib/lava/dispatcher/tmp/939161/extract-nfsrootfs-1rnnjbw7
257 09:05:08.518015 extracting modules file /var/lib/lava/dispatcher/tmp/939161/tftp-deploy-2ufez62e/modules/modules.tar to /var/lib/lava/dispatcher/tmp/939161/extract-overlay-ramdisk-a00qwn0l/ramdisk
258 09:05:10.305784 end: 1.6.4 extract-modules (duration 00:00:03) [common]
259 09:05:10.306283 start: 1.6.5 apply-overlay-tftp (timeout 00:08:54) [common]
260 09:05:10.306580 [common] Applying overlay to NFS
261 09:05:10.306803 [common] Applying overlay /var/lib/lava/dispatcher/tmp/939161/compress-overlay-17vkwrx1/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/939161/extract-nfsrootfs-1rnnjbw7
262 09:05:13.064962 end: 1.6.5 apply-overlay-tftp (duration 00:00:03) [common]
263 09:05:13.065414 start: 1.6.6 prepare-kernel (timeout 00:08:51) [common]
264 09:05:13.065690 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:08:51) [common]
265 09:05:13.065925 Converting downloaded kernel to a uImage
266 09:05:13.066238 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/939161/tftp-deploy-2ufez62e/kernel/Image /var/lib/lava/dispatcher/tmp/939161/tftp-deploy-2ufez62e/kernel/uImage
267 09:05:13.584309 output: Image Name:
268 09:05:13.584739 output: Created: Tue Nov 5 09:05:13 2024
269 09:05:13.584950 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
270 09:05:13.585157 output: Data Size: 45715968 Bytes = 44644.50 KiB = 43.60 MiB
271 09:05:13.585360 output: Load Address: 01080000
272 09:05:13.585562 output: Entry Point: 01080000
273 09:05:13.585761 output:
274 09:05:13.586098 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:01) [common]
275 09:05:13.586368 end: 1.6.6 prepare-kernel (duration 00:00:01) [common]
276 09:05:13.586641 start: 1.6.7 configure-preseed-file (timeout 00:08:50) [common]
277 09:05:13.586900 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
278 09:05:13.587161 start: 1.6.8 compress-ramdisk (timeout 00:08:50) [common]
279 09:05:13.587418 Building ramdisk /var/lib/lava/dispatcher/tmp/939161/extract-overlay-ramdisk-a00qwn0l/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/939161/extract-overlay-ramdisk-a00qwn0l/ramdisk
280 09:05:15.727810 >> 166830 blocks
281 09:05:23.474278 Adding RAMdisk u-boot header.
282 09:05:23.474946 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/939161/extract-overlay-ramdisk-a00qwn0l/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/939161/extract-overlay-ramdisk-a00qwn0l/ramdisk.cpio.gz.uboot
283 09:05:23.773583 output: Image Name:
284 09:05:23.774007 output: Created: Tue Nov 5 09:05:23 2024
285 09:05:23.774222 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
286 09:05:23.774428 output: Data Size: 23432740 Bytes = 22883.54 KiB = 22.35 MiB
287 09:05:23.774632 output: Load Address: 00000000
288 09:05:23.774832 output: Entry Point: 00000000
289 09:05:23.775035 output:
290 09:05:23.775617 rename /var/lib/lava/dispatcher/tmp/939161/extract-overlay-ramdisk-a00qwn0l/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/939161/tftp-deploy-2ufez62e/ramdisk/ramdisk.cpio.gz.uboot
291 09:05:23.776103 end: 1.6.8 compress-ramdisk (duration 00:00:10) [common]
292 09:05:23.776675 end: 1.6 prepare-tftp-overlay (duration 00:01:02) [common]
293 09:05:23.777206 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:40) [common]
294 09:05:23.777661 No LXC device requested
295 09:05:23.778175 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
296 09:05:23.778698 start: 1.8 deploy-device-env (timeout 00:08:40) [common]
297 09:05:23.779298 end: 1.8 deploy-device-env (duration 00:00:00) [common]
298 09:05:23.779729 Checking files for TFTP limit of 4294967296 bytes.
299 09:05:23.782573 end: 1 tftp-deploy (duration 00:01:20) [common]
300 09:05:23.783182 start: 2 uboot-action (timeout 00:05:00) [common]
301 09:05:23.783705 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
302 09:05:23.784241 end: 2.1 uboot-from-media (duration 00:00:00) [common]
303 09:05:23.784753 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
304 09:05:23.785278 Using kernel file from prepare-kernel: 939161/tftp-deploy-2ufez62e/kernel/uImage
305 09:05:23.785904 substitutions:
306 09:05:23.786311 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
307 09:05:23.786714 - {DTB_ADDR}: 0x01070000
308 09:05:23.787109 - {DTB}: 939161/tftp-deploy-2ufez62e/dtb/meson-g12b-a311d-libretech-cc.dtb
309 09:05:23.787510 - {INITRD}: 939161/tftp-deploy-2ufez62e/ramdisk/ramdisk.cpio.gz.uboot
310 09:05:23.787910 - {KERNEL_ADDR}: 0x01080000
311 09:05:23.788339 - {KERNEL}: 939161/tftp-deploy-2ufez62e/kernel/uImage
312 09:05:23.788736 - {LAVA_MAC}: None
313 09:05:23.789169 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/939161/extract-nfsrootfs-1rnnjbw7
314 09:05:23.789569 - {NFS_SERVER_IP}: 192.168.6.2
315 09:05:23.789958 - {PRESEED_CONFIG}: None
316 09:05:23.790350 - {PRESEED_LOCAL}: None
317 09:05:23.790740 - {RAMDISK_ADDR}: 0x08000000
318 09:05:23.791128 - {RAMDISK}: 939161/tftp-deploy-2ufez62e/ramdisk/ramdisk.cpio.gz.uboot
319 09:05:23.791514 - {ROOT_PART}: None
320 09:05:23.791900 - {ROOT}: None
321 09:05:23.792313 - {SERVER_IP}: 192.168.6.2
322 09:05:23.792700 - {TEE_ADDR}: 0x83000000
323 09:05:23.793083 - {TEE}: None
324 09:05:23.793469 Parsed boot commands:
325 09:05:23.793844 - setenv autoload no
326 09:05:23.794227 - setenv initrd_high 0xffffffff
327 09:05:23.794606 - setenv fdt_high 0xffffffff
328 09:05:23.794987 - dhcp
329 09:05:23.795368 - setenv serverip 192.168.6.2
330 09:05:23.795754 - tftpboot 0x01080000 939161/tftp-deploy-2ufez62e/kernel/uImage
331 09:05:23.796202 - tftpboot 0x08000000 939161/tftp-deploy-2ufez62e/ramdisk/ramdisk.cpio.gz.uboot
332 09:05:23.796595 - tftpboot 0x01070000 939161/tftp-deploy-2ufez62e/dtb/meson-g12b-a311d-libretech-cc.dtb
333 09:05:23.796984 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/939161/extract-nfsrootfs-1rnnjbw7,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
334 09:05:23.797383 - bootm 0x01080000 0x08000000 0x01070000
335 09:05:23.797887 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
337 09:05:23.799370 start: 2.3 connect-device (timeout 00:05:00) [common]
338 09:05:23.799792 [common] connect-device Connecting to device using 'telnet conserv1 3007'
339 09:05:23.815245 Setting prompt string to ['lava-test: # ']
340 09:05:23.816923 end: 2.3 connect-device (duration 00:00:00) [common]
341 09:05:23.817557 start: 2.4 uboot-commands (timeout 00:05:00) [common]
342 09:05:23.818219 start: 2.4.1 reset-device (timeout 00:05:00) [common]
343 09:05:23.818888 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
344 09:05:23.820144 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
345 09:05:23.858270 >> OK - accepted request
346 09:05:23.860334 Returned 0 in 0 seconds
347 09:05:23.961523 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
349 09:05:23.963146 end: 2.4.1 reset-device (duration 00:00:00) [common]
350 09:05:23.963698 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
351 09:05:23.964254 Setting prompt string to ['Hit any key to stop autoboot']
352 09:05:23.964704 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
353 09:05:23.966242 Trying 192.168.56.21...
354 09:05:23.966730 Connected to conserv1.
355 09:05:23.967139 Escape character is '^]'.
356 09:05:23.967553
357 09:05:23.968001 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
358 09:05:23.968443
359 09:05:34.738493 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
360 09:05:34.739096 bl2_stage_init 0x01
361 09:05:34.739507 bl2_stage_init 0x81
362 09:05:34.743935 hw id: 0x0000 - pwm id 0x01
363 09:05:34.744513 bl2_stage_init 0xc1
364 09:05:34.744944 bl2_stage_init 0x02
365 09:05:34.745389
366 09:05:34.749514 L0:00000000
367 09:05:34.750032 L1:20000703
368 09:05:34.750449 L2:00008067
369 09:05:34.750850 L3:14000000
370 09:05:34.752338 B2:00402000
371 09:05:34.752814 B1:e0f83180
372 09:05:34.753221
373 09:05:34.753622 TE: 58124
374 09:05:34.754013
375 09:05:34.763383 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
376 09:05:34.763861
377 09:05:34.764295 Board ID = 1
378 09:05:34.764684 Set A53 clk to 24M
379 09:05:34.765068 Set A73 clk to 24M
380 09:05:34.769067 Set clk81 to 24M
381 09:05:34.769385 A53 clk: 1200 MHz
382 09:05:34.769605 A73 clk: 1200 MHz
383 09:05:34.774657 CLK81: 166.6M
384 09:05:34.775002 smccc: 00012a92
385 09:05:34.780287 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
386 09:05:34.780632 board id: 1
387 09:05:34.785822 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
388 09:05:34.799633 fw parse done
389 09:05:34.805154 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
390 09:05:34.847287 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
391 09:05:34.859137 PIEI prepare done
392 09:05:34.859470 fastboot data load
393 09:05:34.859706 fastboot data verify
394 09:05:34.864673 verify result: 266
395 09:05:34.870520 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
396 09:05:34.870871 LPDDR4 probe
397 09:05:34.871115 ddr clk to 1584MHz
398 09:05:34.877479 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
399 09:05:34.915326
400 09:05:34.915703 dmc_version 0001
401 09:05:34.921232 Check phy result
402 09:05:34.928243 INFO : End of CA training
403 09:05:34.928795 INFO : End of initialization
404 09:05:34.933660 INFO : Training has run successfully!
405 09:05:34.934164 Check phy result
406 09:05:34.939265 INFO : End of initialization
407 09:05:34.939768 INFO : End of read enable training
408 09:05:34.944879 INFO : End of fine write leveling
409 09:05:34.950497 INFO : End of Write leveling coarse delay
410 09:05:34.951003 INFO : Training has run successfully!
411 09:05:34.951405 Check phy result
412 09:05:34.956162 INFO : End of initialization
413 09:05:34.956660 INFO : End of read dq deskew training
414 09:05:34.961676 INFO : End of MPR read delay center optimization
415 09:05:34.967320 INFO : End of write delay center optimization
416 09:05:34.972929 INFO : End of read delay center optimization
417 09:05:34.973771 INFO : End of max read latency training
418 09:05:34.978454 INFO : Training has run successfully!
419 09:05:34.979052 1D training succeed
420 09:05:34.987167 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
421 09:05:35.035496 Check phy result
422 09:05:35.036282 INFO : End of initialization
423 09:05:35.056751 INFO : End of 2D read delay Voltage center optimization
424 09:05:35.077179 INFO : End of 2D read delay Voltage center optimization
425 09:05:35.129557 INFO : End of 2D write delay Voltage center optimization
426 09:05:35.179087 INFO : End of 2D write delay Voltage center optimization
427 09:05:35.184610 INFO : Training has run successfully!
428 09:05:35.185267
429 09:05:35.185984 channel==0
430 09:05:35.190309 RxClkDly_Margin_A0==88 ps 9
431 09:05:35.190961 TxDqDly_Margin_A0==98 ps 10
432 09:05:35.193568 RxClkDly_Margin_A1==78 ps 8
433 09:05:35.194216 TxDqDly_Margin_A1==98 ps 10
434 09:05:35.200194 TrainedVREFDQ_A0==74
435 09:05:35.200734 TrainedVREFDQ_A1==74
436 09:05:35.201170 VrefDac_Margin_A0==24
437 09:05:35.204768 DeviceVref_Margin_A0==40
438 09:05:35.205355 VrefDac_Margin_A1==26
439 09:05:35.210365 DeviceVref_Margin_A1==40
440 09:05:35.210925
441 09:05:35.211359
442 09:05:35.211807 channel==1
443 09:05:35.212294 RxClkDly_Margin_A0==98 ps 10
444 09:05:35.213847 TxDqDly_Margin_A0==88 ps 9
445 09:05:35.219286 RxClkDly_Margin_A1==98 ps 10
446 09:05:35.219830 TxDqDly_Margin_A1==88 ps 9
447 09:05:35.220278 TrainedVREFDQ_A0==76
448 09:05:35.224928 TrainedVREFDQ_A1==77
449 09:05:35.225457 VrefDac_Margin_A0==22
450 09:05:35.230555 DeviceVref_Margin_A0==38
451 09:05:35.231040 VrefDac_Margin_A1==24
452 09:05:35.231443 DeviceVref_Margin_A1==37
453 09:05:35.231833
454 09:05:35.236088 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
455 09:05:35.236576
456 09:05:35.269576 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000018 00000019 00000017 00000019 00000018 0000001a 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
457 09:05:35.270182 2D training succeed
458 09:05:35.275207 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
459 09:05:35.280773 auto size-- 65535DDR cs0 size: 2048MB
460 09:05:35.281287 DDR cs1 size: 2048MB
461 09:05:35.286372 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
462 09:05:35.286857 cs0 DataBus test pass
463 09:05:35.287260 cs1 DataBus test pass
464 09:05:35.292092 cs0 AddrBus test pass
465 09:05:35.292606 cs1 AddrBus test pass
466 09:05:35.293005
467 09:05:35.297577 100bdlr_step_size ps== 420
468 09:05:35.298111 result report
469 09:05:35.298522 boot times 0Enable ddr reg access
470 09:05:35.307044 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
471 09:05:35.320064 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
472 09:05:35.892863 0.0;M3 CHK:0;cm4_sp_mode 0
473 09:05:35.893650 MVN_1=0x00000000
474 09:05:35.898385 MVN_2=0x00000000
475 09:05:35.904282 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
476 09:05:35.904928 OPS=0x10
477 09:05:35.905623 ring efuse init
478 09:05:35.906181 chipver efuse init
479 09:05:35.909775 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
480 09:05:35.915357 [0.018961 Inits done]
481 09:05:35.916123 secure task start!
482 09:05:35.916737 high task start!
483 09:05:35.919336 low task start!
484 09:05:35.919842 run into bl31
485 09:05:35.926603 NOTICE: BL31: v1.3(release):4fc40b1
486 09:05:35.933456 NOTICE: BL31: Built : 15:58:17, May 22 2019
487 09:05:35.933947 NOTICE: BL31: G12A normal boot!
488 09:05:35.959701 NOTICE: BL31: BL33 decompress pass
489 09:05:35.964678 ERROR: Error initializing runtime service opteed_fast
490 09:05:37.198418
491 09:05:37.199061
492 09:05:37.206625 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
493 09:05:37.207183
494 09:05:37.207612 Model: Libre Computer AML-A311D-CC Alta
495 09:05:37.417452 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
496 09:05:37.438704 DRAM: 2 GiB (effective 3.8 GiB)
497 09:05:37.582024 Core: 408 devices, 31 uclasses, devicetree: separate
498 09:05:37.587381 WDT: Not starting watchdog@f0d0
499 09:05:37.619650 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
500 09:05:37.632028 Loading Environment from FAT... Card did not respond to voltage select! : -110
501 09:05:37.636984 ** Bad device specification mmc 0 **
502 09:05:37.647596 Card did not respond to voltage select! : -110
503 09:05:37.654984 ** Bad device specification mmc 0 **
504 09:05:37.655506 Couldn't find partition mmc 0
505 09:05:37.663404 Card did not respond to voltage select! : -110
506 09:05:37.668824 ** Bad device specification mmc 0 **
507 09:05:37.669374 Couldn't find partition mmc 0
508 09:05:37.673893 Error: could not access storage.
509 09:05:38.938571 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
510 09:05:38.938976 bl2_stage_init 0x01
511 09:05:38.939221 bl2_stage_init 0x81
512 09:05:38.944218 hw id: 0x0000 - pwm id 0x01
513 09:05:38.944624 bl2_stage_init 0xc1
514 09:05:38.944984 bl2_stage_init 0x02
515 09:05:38.945337
516 09:05:38.949737 L0:00000000
517 09:05:38.950136 L1:20000703
518 09:05:38.950400 L2:00008067
519 09:05:38.950634 L3:14000000
520 09:05:38.952639 B2:00402000
521 09:05:38.953038 B1:e0f83180
522 09:05:38.953394
523 09:05:38.953745 TE: 58124
524 09:05:38.954094
525 09:05:38.963813 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
526 09:05:38.964168
527 09:05:38.964408 Board ID = 1
528 09:05:38.964635 Set A53 clk to 24M
529 09:05:38.964861 Set A73 clk to 24M
530 09:05:38.969874 Set clk81 to 24M
531 09:05:38.970501 A53 clk: 1200 MHz
532 09:05:38.970864 A73 clk: 1200 MHz
533 09:05:38.974999 CLK81: 166.6M
534 09:05:38.975389 smccc: 00012a92
535 09:05:38.980623 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
536 09:05:38.981019 board id: 1
537 09:05:38.989215 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
538 09:05:38.999866 fw parse done
539 09:05:39.005811 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
540 09:05:39.048561 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
541 09:05:39.059519 PIEI prepare done
542 09:05:39.059941 fastboot data load
543 09:05:39.060240 fastboot data verify
544 09:05:39.065086 verify result: 266
545 09:05:39.070661 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
546 09:05:39.070950 LPDDR4 probe
547 09:05:39.071183 ddr clk to 1584MHz
548 09:05:39.078686 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
549 09:05:39.115966
550 09:05:39.116487 dmc_version 0001
551 09:05:39.122692 Check phy result
552 09:05:39.128479 INFO : End of CA training
553 09:05:39.128888 INFO : End of initialization
554 09:05:39.134067 INFO : Training has run successfully!
555 09:05:39.134371 Check phy result
556 09:05:39.139661 INFO : End of initialization
557 09:05:39.139951 INFO : End of read enable training
558 09:05:39.145271 INFO : End of fine write leveling
559 09:05:39.150869 INFO : End of Write leveling coarse delay
560 09:05:39.151160 INFO : Training has run successfully!
561 09:05:39.151395 Check phy result
562 09:05:39.156434 INFO : End of initialization
563 09:05:39.156845 INFO : End of read dq deskew training
564 09:05:39.162055 INFO : End of MPR read delay center optimization
565 09:05:39.167642 INFO : End of write delay center optimization
566 09:05:39.173235 INFO : End of read delay center optimization
567 09:05:39.173524 INFO : End of max read latency training
568 09:05:39.178893 INFO : Training has run successfully!
569 09:05:39.179314 1D training succeed
570 09:05:39.188200 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
571 09:05:39.235779 Check phy result
572 09:05:39.236389 INFO : End of initialization
573 09:05:39.257267 INFO : End of 2D read delay Voltage center optimization
574 09:05:39.277374 INFO : End of 2D read delay Voltage center optimization
575 09:05:39.329298 INFO : End of 2D write delay Voltage center optimization
576 09:05:39.378583 INFO : End of 2D write delay Voltage center optimization
577 09:05:39.384082 INFO : Training has run successfully!
578 09:05:39.384575
579 09:05:39.385040 channel==0
580 09:05:39.389712 RxClkDly_Margin_A0==88 ps 9
581 09:05:39.390204 TxDqDly_Margin_A0==98 ps 10
582 09:05:39.395301 RxClkDly_Margin_A1==88 ps 9
583 09:05:39.395812 TxDqDly_Margin_A1==98 ps 10
584 09:05:39.396332 TrainedVREFDQ_A0==74
585 09:05:39.400867 TrainedVREFDQ_A1==74
586 09:05:39.401366 VrefDac_Margin_A0==25
587 09:05:39.401825 DeviceVref_Margin_A0==40
588 09:05:39.406470 VrefDac_Margin_A1==25
589 09:05:39.406955 DeviceVref_Margin_A1==40
590 09:05:39.407410
591 09:05:39.407862
592 09:05:39.412326 channel==1
593 09:05:39.412924 RxClkDly_Margin_A0==98 ps 10
594 09:05:39.413423 TxDqDly_Margin_A0==98 ps 10
595 09:05:39.417747 RxClkDly_Margin_A1==88 ps 9
596 09:05:39.418324 TxDqDly_Margin_A1==88 ps 9
597 09:05:39.423289 TrainedVREFDQ_A0==77
598 09:05:39.423801 TrainedVREFDQ_A1==77
599 09:05:39.424306 VrefDac_Margin_A0==22
600 09:05:39.428854 DeviceVref_Margin_A0==37
601 09:05:39.429347 VrefDac_Margin_A1==24
602 09:05:39.434476 DeviceVref_Margin_A1==37
603 09:05:39.434970
604 09:05:39.435436 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
605 09:05:39.435894
606 09:05:39.468090 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000018 00000019 00000017 00000019 00000018 0000001a 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
607 09:05:39.468662 2D training succeed
608 09:05:39.473679 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
609 09:05:39.479314 auto size-- 65535DDR cs0 size: 2048MB
610 09:05:39.479839 DDR cs1 size: 2048MB
611 09:05:39.484894 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
612 09:05:39.485401 cs0 DataBus test pass
613 09:05:39.490534 cs1 DataBus test pass
614 09:05:39.491040 cs0 AddrBus test pass
615 09:05:39.491497 cs1 AddrBus test pass
616 09:05:39.491944
617 09:05:39.496141 100bdlr_step_size ps== 420
618 09:05:39.496660 result report
619 09:05:39.501672 boot times 0Enable ddr reg access
620 09:05:39.507046 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
621 09:05:39.520010 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
622 09:05:40.092595 0.0;M3 CHK:0;cm4_sp_mode 0
623 09:05:40.093033 MVN_1=0x00000000
624 09:05:40.097915 MVN_2=0x00000000
625 09:05:40.103701 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
626 09:05:40.104047 OPS=0x10
627 09:05:40.104279 ring efuse init
628 09:05:40.104489 chipver efuse init
629 09:05:40.112143 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
630 09:05:40.112487 [0.018961 Inits done]
631 09:05:40.112707 secure task start!
632 09:05:40.119021 high task start!
633 09:05:40.119331 low task start!
634 09:05:40.119544 run into bl31
635 09:05:40.126231 NOTICE: BL31: v1.3(release):4fc40b1
636 09:05:40.133926 NOTICE: BL31: Built : 15:58:17, May 22 2019
637 09:05:40.134251 NOTICE: BL31: G12A normal boot!
638 09:05:40.159293 NOTICE: BL31: BL33 decompress pass
639 09:05:40.164950 ERROR: Error initializing runtime service opteed_fast
640 09:05:41.398105
641 09:05:41.398548
642 09:05:41.406445 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
643 09:05:41.406924
644 09:05:41.407275 Model: Libre Computer AML-A311D-CC Alta
645 09:05:41.614004 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
646 09:05:41.638248 DRAM: 2 GiB (effective 3.8 GiB)
647 09:05:41.781137 Core: 408 devices, 31 uclasses, devicetree: separate
648 09:05:41.786452 WDT: Not starting watchdog@f0d0
649 09:05:41.819332 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
650 09:05:41.831878 Loading Environment from FAT... Card did not respond to voltage select! : -110
651 09:05:41.835852 ** Bad device specification mmc 0 **
652 09:05:41.847189 Card did not respond to voltage select! : -110
653 09:05:41.854322 ** Bad device specification mmc 0 **
654 09:05:41.854798 Couldn't find partition mmc 0
655 09:05:41.863100 Card did not respond to voltage select! : -110
656 09:05:41.868585 ** Bad device specification mmc 0 **
657 09:05:41.869049 Couldn't find partition mmc 0
658 09:05:41.873158 Error: could not access storage.
659 09:05:42.216334 Net: eth0: ethernet@ff3f0000
660 09:05:42.216926 starting USB...
661 09:05:42.469051 Bus usb@ff500000: Register 3000140 NbrPorts 3
662 09:05:42.469638 Starting the controller
663 09:05:42.475600 USB XHCI 1.10
664 09:05:44.188959 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
665 09:05:44.189618 bl2_stage_init 0x01
666 09:05:44.190057 bl2_stage_init 0x81
667 09:05:44.194539 hw id: 0x0000 - pwm id 0x01
668 09:05:44.195015 bl2_stage_init 0xc1
669 09:05:44.195427 bl2_stage_init 0x02
670 09:05:44.195831
671 09:05:44.200203 L0:00000000
672 09:05:44.200696 L1:20000703
673 09:05:44.201107 L2:00008067
674 09:05:44.201508 L3:14000000
675 09:05:44.205841 B2:00402000
676 09:05:44.206424 B1:e0f83180
677 09:05:44.206843
678 09:05:44.207253 TE: 58167
679 09:05:44.207659
680 09:05:44.211432 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
681 09:05:44.211912
682 09:05:44.212369 Board ID = 1
683 09:05:44.216953 Set A53 clk to 24M
684 09:05:44.217489 Set A73 clk to 24M
685 09:05:44.217901 Set clk81 to 24M
686 09:05:44.222741 A53 clk: 1200 MHz
687 09:05:44.223293 A73 clk: 1200 MHz
688 09:05:44.223710 CLK81: 166.6M
689 09:05:44.224158 smccc: 00012abe
690 09:05:44.228257 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
691 09:05:44.233680 board id: 1
692 09:05:44.238754 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
693 09:05:44.250416 fw parse done
694 09:05:44.256110 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
695 09:05:44.298879 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
696 09:05:44.309811 PIEI prepare done
697 09:05:44.310412 fastboot data load
698 09:05:44.310868 fastboot data verify
699 09:05:44.315479 verify result: 266
700 09:05:44.320944 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
701 09:05:44.321476 LPDDR4 probe
702 09:05:44.321904 ddr clk to 1584MHz
703 09:05:44.328420 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
704 09:05:44.366022
705 09:05:44.366575 dmc_version 0001
706 09:05:44.372295 Check phy result
707 09:05:44.378783 INFO : End of CA training
708 09:05:44.379196 INFO : End of initialization
709 09:05:44.384445 INFO : Training has run successfully!
710 09:05:44.384864 Check phy result
711 09:05:44.389922 INFO : End of initialization
712 09:05:44.390337 INFO : End of read enable training
713 09:05:44.395574 INFO : End of fine write leveling
714 09:05:44.401228 INFO : End of Write leveling coarse delay
715 09:05:44.401640 INFO : Training has run successfully!
716 09:05:44.401894 Check phy result
717 09:05:44.406791 INFO : End of initialization
718 09:05:44.407210 INFO : End of read dq deskew training
719 09:05:44.412487 INFO : End of MPR read delay center optimization
720 09:05:44.417969 INFO : End of write delay center optimization
721 09:05:44.423561 INFO : End of read delay center optimization
722 09:05:44.424016 INFO : End of max read latency training
723 09:05:44.429133 INFO : Training has run successfully!
724 09:05:44.429561 1D training succeed
725 09:05:44.437578 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
726 09:05:44.485125 Check phy result
727 09:05:44.485563 INFO : End of initialization
728 09:05:44.507387 INFO : End of 2D read delay Voltage center optimization
729 09:05:44.527890 INFO : End of 2D read delay Voltage center optimization
730 09:05:44.579467 INFO : End of 2D write delay Voltage center optimization
731 09:05:44.629335 INFO : End of 2D write delay Voltage center optimization
732 09:05:44.634869 INFO : Training has run successfully!
733 09:05:44.635305
734 09:05:44.635573 channel==0
735 09:05:44.640502 RxClkDly_Margin_A0==88 ps 9
736 09:05:44.640919 TxDqDly_Margin_A0==98 ps 10
737 09:05:44.646217 RxClkDly_Margin_A1==88 ps 9
738 09:05:44.646850 TxDqDly_Margin_A1==88 ps 9
739 09:05:44.647323 TrainedVREFDQ_A0==74
740 09:05:44.651661 TrainedVREFDQ_A1==74
741 09:05:44.652308 VrefDac_Margin_A0==25
742 09:05:44.652767 DeviceVref_Margin_A0==40
743 09:05:44.657330 VrefDac_Margin_A1==25
744 09:05:44.657739 DeviceVref_Margin_A1==40
745 09:05:44.658009
746 09:05:44.658264
747 09:05:44.658508 channel==1
748 09:05:44.662887 RxClkDly_Margin_A0==98 ps 10
749 09:05:44.663293 TxDqDly_Margin_A0==98 ps 10
750 09:05:44.668496 RxClkDly_Margin_A1==88 ps 9
751 09:05:44.668935 TxDqDly_Margin_A1==88 ps 9
752 09:05:44.674110 TrainedVREFDQ_A0==77
753 09:05:44.674534 TrainedVREFDQ_A1==77
754 09:05:44.674794 VrefDac_Margin_A0==23
755 09:05:44.679720 DeviceVref_Margin_A0==37
756 09:05:44.680178 VrefDac_Margin_A1==24
757 09:05:44.686347 DeviceVref_Margin_A1==37
758 09:05:44.686760
759 09:05:44.686989 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
760 09:05:44.687194
761 09:05:44.718720 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000018 00000019 00000017 00000019 00000018 0000001a 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000019 00000018 dram_vref_reg_value 0x 0000005f
762 09:05:44.719103 2D training succeed
763 09:05:44.724373 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
764 09:05:44.729940 auto size-- 65535DDR cs0 size: 2048MB
765 09:05:44.730239 DDR cs1 size: 2048MB
766 09:05:44.735724 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
767 09:05:44.736275 cs0 DataBus test pass
768 09:05:44.741319 cs1 DataBus test pass
769 09:05:44.741819 cs0 AddrBus test pass
770 09:05:44.742217 cs1 AddrBus test pass
771 09:05:44.742607
772 09:05:44.746903 100bdlr_step_size ps== 420
773 09:05:44.747407 result report
774 09:05:44.752461 boot times 0Enable ddr reg access
775 09:05:44.756921 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
776 09:05:44.770279 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
777 09:05:45.344749 0.0;M3 CHK:0;cm4_sp_mode 0
778 09:05:45.345361 MVN_1=0x00000000
779 09:05:45.350265 MVN_2=0x00000000
780 09:05:45.356132 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
781 09:05:45.356662 OPS=0x10
782 09:05:45.357099 ring efuse init
783 09:05:45.357516 chipver efuse init
784 09:05:45.361644 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
785 09:05:45.367245 [0.018961 Inits done]
786 09:05:45.367760 secure task start!
787 09:05:45.368236 high task start!
788 09:05:45.371594 low task start!
789 09:05:45.372341 run into bl31
790 09:05:45.378636 NOTICE: BL31: v1.3(release):4fc40b1
791 09:05:45.385552 NOTICE: BL31: Built : 15:58:17, May 22 2019
792 09:05:45.386248 NOTICE: BL31: G12A normal boot!
793 09:05:45.411803 NOTICE: BL31: BL33 decompress pass
794 09:05:45.416647 ERROR: Error initializing runtime service opteed_fast
795 09:05:46.650226
796 09:05:46.650867
797 09:05:46.657713 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
798 09:05:46.658248
799 09:05:46.658662 Model: Libre Computer AML-A311D-CC Alta
800 09:05:46.866783 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
801 09:05:46.889541 DRAM: 2 GiB (effective 3.8 GiB)
802 09:05:47.033587 Core: 408 devices, 31 uclasses, devicetree: separate
803 09:05:47.038779 WDT: Not starting watchdog@f0d0
804 09:05:47.071684 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
805 09:05:47.084088 Loading Environment from FAT... Card did not respond to voltage select! : -110
806 09:05:47.088112 ** Bad device specification mmc 0 **
807 09:05:47.099478 Card did not respond to voltage select! : -110
808 09:05:47.106341 ** Bad device specification mmc 0 **
809 09:05:47.106971 Couldn't find partition mmc 0
810 09:05:47.115257 Card did not respond to voltage select! : -110
811 09:05:47.120823 ** Bad device specification mmc 0 **
812 09:05:47.121406 Couldn't find partition mmc 0
813 09:05:47.125819 Error: could not access storage.
814 09:05:47.467914 Net: eth0: ethernet@ff3f0000
815 09:05:47.468634 starting USB...
816 09:05:47.720189 Bus usb@ff500000: Register 3000140 NbrPorts 3
817 09:05:47.721038 Starting the controller
818 09:05:47.726610 USB XHCI 1.10
819 09:05:49.889538 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
820 09:05:49.890042 bl2_stage_init 0x01
821 09:05:49.890344 bl2_stage_init 0x81
822 09:05:49.894844 hw id: 0x0000 - pwm id 0x01
823 09:05:49.895224 bl2_stage_init 0xc1
824 09:05:49.895512 bl2_stage_init 0x02
825 09:05:49.895791
826 09:05:49.900466 L0:00000000
827 09:05:49.900847 L1:20000703
828 09:05:49.901131 L2:00008067
829 09:05:49.901410 L3:14000000
830 09:05:49.906125 B2:00402000
831 09:05:49.906499 B1:e0f83180
832 09:05:49.906786
833 09:05:49.907072 TE: 58167
834 09:05:49.907361
835 09:05:49.911558 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
836 09:05:49.911929
837 09:05:49.912257 Board ID = 1
838 09:05:49.917433 Set A53 clk to 24M
839 09:05:49.917810 Set A73 clk to 24M
840 09:05:49.918230 Set clk81 to 24M
841 09:05:49.922842 A53 clk: 1200 MHz
842 09:05:49.923200 A73 clk: 1200 MHz
843 09:05:49.923480 CLK81: 166.6M
844 09:05:49.923764 smccc: 00012abc
845 09:05:49.928356 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
846 09:05:49.934051 board id: 1
847 09:05:49.940029 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
848 09:05:49.950690 fw parse done
849 09:05:49.955904 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
850 09:05:49.999073 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
851 09:05:50.010854 PIEI prepare done
852 09:05:50.011346 fastboot data load
853 09:05:50.011751 fastboot data verify
854 09:05:50.015583 verify result: 266
855 09:05:50.021627 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
856 09:05:50.022112 LPDDR4 probe
857 09:05:50.022518 ddr clk to 1584MHz
858 09:05:50.029181 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
859 09:05:50.066379
860 09:05:50.066875 dmc_version 0001
861 09:05:50.073115 Check phy result
862 09:05:50.078918 INFO : End of CA training
863 09:05:50.079391 INFO : End of initialization
864 09:05:50.084457 INFO : Training has run successfully!
865 09:05:50.084922 Check phy result
866 09:05:50.090202 INFO : End of initialization
867 09:05:50.090661 INFO : End of read enable training
868 09:05:50.095655 INFO : End of fine write leveling
869 09:05:50.101274 INFO : End of Write leveling coarse delay
870 09:05:50.101750 INFO : Training has run successfully!
871 09:05:50.102175 Check phy result
872 09:05:50.106890 INFO : End of initialization
873 09:05:50.107358 INFO : End of read dq deskew training
874 09:05:50.112481 INFO : End of MPR read delay center optimization
875 09:05:50.118045 INFO : End of write delay center optimization
876 09:05:50.123667 INFO : End of read delay center optimization
877 09:05:50.124180 INFO : End of max read latency training
878 09:05:50.129201 INFO : Training has run successfully!
879 09:05:50.129663 1D training succeed
880 09:05:50.139244 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
881 09:05:50.186216 Check phy result
882 09:05:50.186823 INFO : End of initialization
883 09:05:50.207102 INFO : End of 2D read delay Voltage center optimization
884 09:05:50.228198 INFO : End of 2D read delay Voltage center optimization
885 09:05:50.280283 INFO : End of 2D write delay Voltage center optimization
886 09:05:50.329577 INFO : End of 2D write delay Voltage center optimization
887 09:05:50.336627 INFO : Training has run successfully!
888 09:05:50.337114
889 09:05:50.337542 channel==0
890 09:05:50.337953 RxClkDly_Margin_A0==88 ps 9
891 09:05:50.342289 TxDqDly_Margin_A0==98 ps 10
892 09:05:50.342766 RxClkDly_Margin_A1==88 ps 9
893 09:05:50.347867 TxDqDly_Margin_A1==98 ps 10
894 09:05:50.348395 TrainedVREFDQ_A0==74
895 09:05:50.348843 TrainedVREFDQ_A1==74
896 09:05:50.353418 VrefDac_Margin_A0==25
897 09:05:50.353928 DeviceVref_Margin_A0==40
898 09:05:50.360072 VrefDac_Margin_A1==25
899 09:05:50.360660 DeviceVref_Margin_A1==40
900 09:05:50.361135
901 09:05:50.361601
902 09:05:50.362008 channel==1
903 09:05:50.364796 RxClkDly_Margin_A0==98 ps 10
904 09:05:50.365263 TxDqDly_Margin_A0==98 ps 10
905 09:05:50.370527 RxClkDly_Margin_A1==88 ps 9
906 09:05:50.371058 TxDqDly_Margin_A1==88 ps 9
907 09:05:50.371460 TrainedVREFDQ_A0==77
908 09:05:50.374083 TrainedVREFDQ_A1==77
909 09:05:50.379226 VrefDac_Margin_A0==22
910 09:05:50.379706 DeviceVref_Margin_A0==37
911 09:05:50.380137 VrefDac_Margin_A1==24
912 09:05:50.384792 DeviceVref_Margin_A1==37
913 09:05:50.385238
914 09:05:50.390332 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
915 09:05:50.390766
916 09:05:50.418266 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000018 00000019 00000017 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
917 09:05:50.418839 2D training succeed
918 09:05:50.423856 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
919 09:05:50.429444 auto size-- 65535DDR cs0 size: 2048MB
920 09:05:50.429893 DDR cs1 size: 2048MB
921 09:05:50.435043 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
922 09:05:50.435478 cs0 DataBus test pass
923 09:05:50.440606 cs1 DataBus test pass
924 09:05:50.441033 cs0 AddrBus test pass
925 09:05:50.441427 cs1 AddrBus test pass
926 09:05:50.446231
927 09:05:50.446657 100bdlr_step_size ps== 420
928 09:05:50.447059 result report
929 09:05:50.451825 boot times 0Enable ddr reg access
930 09:05:50.458015 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
931 09:05:50.471193 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
932 09:05:51.045173 0.0;M3 CHK:0;cm4_sp_mode 0
933 09:05:51.045613 MVN_1=0x00000000
934 09:05:51.050633 MVN_2=0x00000000
935 09:05:51.056402 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
936 09:05:51.056903 OPS=0x10
937 09:05:51.057164 ring efuse init
938 09:05:51.057380 chipver efuse init
939 09:05:51.064624 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
940 09:05:51.065033 [0.018961 Inits done]
941 09:05:51.071268 secure task start!
942 09:05:51.071641 high task start!
943 09:05:51.071903 low task start!
944 09:05:51.072209 run into bl31
945 09:05:51.078808 NOTICE: BL31: v1.3(release):4fc40b1
946 09:05:51.085690 NOTICE: BL31: Built : 15:58:17, May 22 2019
947 09:05:51.086081 NOTICE: BL31: G12A normal boot!
948 09:05:51.112067 NOTICE: BL31: BL33 decompress pass
949 09:05:51.116696 ERROR: Error initializing runtime service opteed_fast
950 09:05:52.350587
951 09:05:52.351009
952 09:05:52.358934 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
953 09:05:52.359401
954 09:05:52.359787 Model: Libre Computer AML-A311D-CC Alta
955 09:05:52.566487 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
956 09:05:52.589887 DRAM: 2 GiB (effective 3.8 GiB)
957 09:05:52.733853 Core: 408 devices, 31 uclasses, devicetree: separate
958 09:05:52.738819 WDT: Not starting watchdog@f0d0
959 09:05:52.772132 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
960 09:05:52.784452 Loading Environment from FAT... Card did not respond to voltage select! : -110
961 09:05:52.788618 ** Bad device specification mmc 0 **
962 09:05:52.799741 Card did not respond to voltage select! : -110
963 09:05:52.806487 ** Bad device specification mmc 0 **
964 09:05:52.807005 Couldn't find partition mmc 0
965 09:05:52.815661 Card did not respond to voltage select! : -110
966 09:05:52.821290 ** Bad device specification mmc 0 **
967 09:05:52.821804 Couldn't find partition mmc 0
968 09:05:52.826273 Error: could not access storage.
969 09:05:53.169730 Net: eth0: ethernet@ff3f0000
970 09:05:53.170339 starting USB...
971 09:05:53.421627 Bus usb@ff500000: Register 3000140 NbrPorts 3
972 09:05:53.422240 Starting the controller
973 09:05:53.428538 USB XHCI 1.10
974 09:05:55.289556 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
975 09:05:55.290201 bl2_stage_init 0x01
976 09:05:55.290677 bl2_stage_init 0x81
977 09:05:55.294622 hw id: 0x0000 - pwm id 0x01
978 09:05:55.295231 bl2_stage_init 0xc1
979 09:05:55.295710 bl2_stage_init 0x02
980 09:05:55.296229
981 09:05:55.300128 L0:00000000
982 09:05:55.300754 L1:20000703
983 09:05:55.301227 L2:00008067
984 09:05:55.301680 L3:14000000
985 09:05:55.302874 B2:00402000
986 09:05:55.303393 B1:e0f83180
987 09:05:55.303851
988 09:05:55.304362 TE: 58159
989 09:05:55.304823
990 09:05:55.314158 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
991 09:05:55.314804
992 09:05:55.315280 Board ID = 1
993 09:05:55.315730 Set A53 clk to 24M
994 09:05:55.316224 Set A73 clk to 24M
995 09:05:55.319923 Set clk81 to 24M
996 09:05:55.320554 A53 clk: 1200 MHz
997 09:05:55.321030 A73 clk: 1200 MHz
998 09:05:55.325383 CLK81: 166.6M
999 09:05:55.325939 smccc: 00012ab5
1000 09:05:55.331078 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
1001 09:05:55.331668 board id: 1
1002 09:05:55.338616 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
1003 09:05:55.350277 fw parse done
1004 09:05:55.356252 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
1005 09:05:55.398776 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
1006 09:05:55.409803 PIEI prepare done
1007 09:05:55.410455 fastboot data load
1008 09:05:55.410907 fastboot data verify
1009 09:05:55.415601 verify result: 266
1010 09:05:55.421275 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
1011 09:05:55.421962 LPDDR4 probe
1012 09:05:55.422418 ddr clk to 1584MHz
1013 09:05:55.428385 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
1014 09:05:55.465506
1015 09:05:55.466200 dmc_version 0001
1016 09:05:55.472234 Check phy result
1017 09:05:55.479005 INFO : End of CA training
1018 09:05:55.479657 INFO : End of initialization
1019 09:05:55.484779 INFO : Training has run successfully!
1020 09:05:55.485436 Check phy result
1021 09:05:55.490272 INFO : End of initialization
1022 09:05:55.490918 INFO : End of read enable training
1023 09:05:55.494480 INFO : End of fine write leveling
1024 09:05:55.499357 INFO : End of Write leveling coarse delay
1025 09:05:55.504699 INFO : Training has run successfully!
1026 09:05:55.505337 Check phy result
1027 09:05:55.505808 INFO : End of initialization
1028 09:05:55.510213 INFO : End of read dq deskew training
1029 09:05:55.514630 INFO : End of MPR read delay center optimization
1030 09:05:55.520388 INFO : End of write delay center optimization
1031 09:05:55.521064 INFO : End of read delay center optimization
1032 09:05:55.525858 INFO : End of max read latency training
1033 09:05:55.531473 INFO : Training has run successfully!
1034 09:05:55.532186 1D training succeed
1035 09:05:55.538441 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
1036 09:05:55.586009 Check phy result
1037 09:05:55.586628 INFO : End of initialization
1038 09:05:55.607736 INFO : End of 2D read delay Voltage center optimization
1039 09:05:55.627099 INFO : End of 2D read delay Voltage center optimization
1040 09:05:55.679165 INFO : End of 2D write delay Voltage center optimization
1041 09:05:55.729470 INFO : End of 2D write delay Voltage center optimization
1042 09:05:55.735126 INFO : Training has run successfully!
1043 09:05:55.735777
1044 09:05:55.736346 channel==0
1045 09:05:55.740606 RxClkDly_Margin_A0==88 ps 9
1046 09:05:55.741190 TxDqDly_Margin_A0==98 ps 10
1047 09:05:55.746199 RxClkDly_Margin_A1==88 ps 9
1048 09:05:55.746776 TxDqDly_Margin_A1==98 ps 10
1049 09:05:55.747247 TrainedVREFDQ_A0==74
1050 09:05:55.751830 TrainedVREFDQ_A1==74
1051 09:05:55.752440 VrefDac_Margin_A0==25
1052 09:05:55.752906 DeviceVref_Margin_A0==40
1053 09:05:55.757365 VrefDac_Margin_A1==25
1054 09:05:55.757934 DeviceVref_Margin_A1==40
1055 09:05:55.758397
1056 09:05:55.758851
1057 09:05:55.763086 channel==1
1058 09:05:55.763651 RxClkDly_Margin_A0==98 ps 10
1059 09:05:55.764160 TxDqDly_Margin_A0==88 ps 9
1060 09:05:55.768578 RxClkDly_Margin_A1==88 ps 9
1061 09:05:55.769109 TxDqDly_Margin_A1==88 ps 9
1062 09:05:55.774122 TrainedVREFDQ_A0==77
1063 09:05:55.774658 TrainedVREFDQ_A1==77
1064 09:05:55.775114 VrefDac_Margin_A0==22
1065 09:05:55.779814 DeviceVref_Margin_A0==37
1066 09:05:55.780380 VrefDac_Margin_A1==24
1067 09:05:55.785364 DeviceVref_Margin_A1==37
1068 09:05:55.785884
1069 09:05:55.786338 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
1070 09:05:55.786790
1071 09:05:55.818958 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000019 00000018 00000019 00000018 0000001a 0000001a 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
1072 09:05:55.819572 2D training succeed
1073 09:05:55.824419 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
1074 09:05:55.830042 auto size-- 65535DDR cs0 size: 2048MB
1075 09:05:55.830551 DDR cs1 size: 2048MB
1076 09:05:55.835691 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
1077 09:05:55.836233 cs0 DataBus test pass
1078 09:05:55.841223 cs1 DataBus test pass
1079 09:05:55.841702 cs0 AddrBus test pass
1080 09:05:55.842149 cs1 AddrBus test pass
1081 09:05:55.842590
1082 09:05:55.846944 100bdlr_step_size ps== 420
1083 09:05:55.847445 result report
1084 09:05:55.852445 boot times 0Enable ddr reg access
1085 09:05:55.857648 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
1086 09:05:55.871191 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
1087 09:05:56.444913 0.0;M3 CHK:0;cm4_sp_mode 0
1088 09:05:56.445575 MVN_1=0x00000000
1089 09:05:56.451195 MVN_2=0x00000000
1090 09:05:56.456051 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
1091 09:05:56.456554 OPS=0x10
1092 09:05:56.457011 ring efuse init
1093 09:05:56.457459 chipver efuse init
1094 09:05:56.464274 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
1095 09:05:56.464790 [0.018961 Inits done]
1096 09:05:56.471857 secure task start!
1097 09:05:56.472390 high task start!
1098 09:05:56.472843 low task start!
1099 09:05:56.473290 run into bl31
1100 09:05:56.478484 NOTICE: BL31: v1.3(release):4fc40b1
1101 09:05:56.485443 NOTICE: BL31: Built : 15:58:17, May 22 2019
1102 09:05:56.485950 NOTICE: BL31: G12A normal boot!
1103 09:05:56.511668 NOTICE: BL31: BL33 decompress pass
1104 09:05:56.517360 ERROR: Error initializing runtime service opteed_fast
1105 09:05:57.750310
1106 09:05:57.750992
1107 09:05:57.758669 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
1108 09:05:57.759237
1109 09:05:57.759713 Model: Libre Computer AML-A311D-CC Alta
1110 09:05:57.967165 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
1111 09:05:57.990536 DRAM: 2 GiB (effective 3.8 GiB)
1112 09:05:58.133515 Core: 408 devices, 31 uclasses, devicetree: separate
1113 09:05:58.139330 WDT: Not starting watchdog@f0d0
1114 09:05:58.171580 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
1115 09:05:58.184096 Loading Environment from FAT... Card did not respond to voltage select! : -110
1116 09:05:58.189002 ** Bad device specification mmc 0 **
1117 09:05:58.199366 Card did not respond to voltage select! : -110
1118 09:05:58.207020 ** Bad device specification mmc 0 **
1119 09:05:58.207351 Couldn't find partition mmc 0
1120 09:05:58.215366 Card did not respond to voltage select! : -110
1121 09:05:58.220872 ** Bad device specification mmc 0 **
1122 09:05:58.221353 Couldn't find partition mmc 0
1123 09:05:58.225939 Error: could not access storage.
1124 09:05:58.568569 Net: eth0: ethernet@ff3f0000
1125 09:05:58.569062 starting USB...
1126 09:05:58.821510 Bus usb@ff500000: Register 3000140 NbrPorts 3
1127 09:05:58.822190 Starting the controller
1128 09:05:58.828292 USB XHCI 1.10
1129 09:06:00.382245 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
1130 09:06:00.390566 scanning usb for storage devices... 0 Storage Device(s) found
1132 09:06:00.442298 Hit any key to stop autoboot: 1
1133 09:06:00.443193 end: 2.4.2 bootloader-interrupt (duration 00:00:36) [common]
1134 09:06:00.443782 start: 2.4.3 bootloader-commands (timeout 00:04:23) [common]
1135 09:06:00.444281 Setting prompt string to ['=>']
1136 09:06:00.444753 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:23)
1137 09:06:00.458642 0
1138 09:06:00.459539 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1139 09:06:00.460056 Sending with 10 millisecond of delay
1141 09:06:01.595279 => setenv autoload no
1142 09:06:01.606220 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:22)
1143 09:06:01.611248 setenv autoload no
1144 09:06:01.612072 Sending with 10 millisecond of delay
1146 09:06:03.409506 => setenv initrd_high 0xffffffff
1147 09:06:03.420392 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:20)
1148 09:06:03.421421 setenv initrd_high 0xffffffff
1149 09:06:03.422172 Sending with 10 millisecond of delay
1151 09:06:05.038649 => setenv fdt_high 0xffffffff
1152 09:06:05.049419 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:19)
1153 09:06:05.050265 setenv fdt_high 0xffffffff
1154 09:06:05.050971 Sending with 10 millisecond of delay
1156 09:06:05.342821 => dhcp
1157 09:06:05.353569 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1158 09:06:05.354428 dhcp
1159 09:06:05.354866 Speed: 1000, full duplex
1160 09:06:05.355276 BOOTP broadcast 1
1161 09:06:05.372398 DHCP client bound to address 192.168.6.27 (19 ms)
1162 09:06:05.373139 Sending with 10 millisecond of delay
1164 09:06:07.049650 => setenv serverip 192.168.6.2
1165 09:06:07.060174 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:17)
1166 09:06:07.060693 setenv serverip 192.168.6.2
1167 09:06:07.061155 Sending with 10 millisecond of delay
1169 09:06:10.784309 => tftpboot 0x01080000 939161/tftp-deploy-2ufez62e/kernel/uImage
1170 09:06:10.795117 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:13)
1171 09:06:10.796038 tftpboot 0x01080000 939161/tftp-deploy-2ufez62e/kernel/uImage
1172 09:06:10.796501 Speed: 1000, full duplex
1173 09:06:10.796923 Using ethernet@ff3f0000 device
1174 09:06:10.797652 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1175 09:06:10.803182 Filename '939161/tftp-deploy-2ufez62e/kernel/uImage'.
1176 09:06:10.807026 Load address: 0x1080000
1177 09:06:13.744513 Loading: *################################################## 43.6 MiB
1178 09:06:13.745153 14.8 MiB/s
1179 09:06:13.745602 done
1180 09:06:13.748338 Bytes transferred = 45716032 (2b99240 hex)
1181 09:06:13.749149 Sending with 10 millisecond of delay
1183 09:06:18.442722 => tftpboot 0x08000000 939161/tftp-deploy-2ufez62e/ramdisk/ramdisk.cpio.gz.uboot
1184 09:06:18.453536 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:05)
1185 09:06:18.454285 tftpboot 0x08000000 939161/tftp-deploy-2ufez62e/ramdisk/ramdisk.cpio.gz.uboot
1186 09:06:18.454802 Speed: 1000, full duplex
1187 09:06:18.455167 Using ethernet@ff3f0000 device
1188 09:06:18.456173 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1189 09:06:18.464907 Filename '939161/tftp-deploy-2ufez62e/ramdisk/ramdisk.cpio.gz.uboot'.
1190 09:06:18.465439 Load address: 0x8000000
1191 09:06:22.480715 Loading: *############## UDP wrong checksum 000000ff 00004bda
1192 09:06:22.490954 UDP wrong checksum 000000ff 0000d8cc
1193 09:06:25.000047 T #################################### 22.3 MiB
1194 09:06:25.007908 3.4 MiB/s
1195 09:06:25.008647 done
1196 09:06:25.009203 Bytes transferred = 23432804 (1658e64 hex)
1197 09:06:25.010056 Sending with 10 millisecond of delay
1199 09:06:30.181177 => tftpboot 0x01070000 939161/tftp-deploy-2ufez62e/dtb/meson-g12b-a311d-libretech-cc.dtb
1200 09:06:30.191871 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:03:54)
1201 09:06:30.192442 tftpboot 0x01070000 939161/tftp-deploy-2ufez62e/dtb/meson-g12b-a311d-libretech-cc.dtb
1202 09:06:30.192708 Speed: 1000, full duplex
1203 09:06:30.192931 Using ethernet@ff3f0000 device
1204 09:06:30.196785 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1205 09:06:30.208997 Filename '939161/tftp-deploy-2ufez62e/dtb/meson-g12b-a311d-libretech-cc.dtb'.
1206 09:06:30.209325 Load address: 0x1070000
1207 09:06:30.224748 Loading: *################################################## 53.4 KiB
1208 09:06:30.225060 3.1 MiB/s
1209 09:06:30.225276 done
1210 09:06:30.231420 Bytes transferred = 54703 (d5af hex)
1211 09:06:30.231940 Sending with 10 millisecond of delay
1213 09:06:43.539833 => setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/939161/extract-nfsrootfs-1rnnjbw7,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
1214 09:06:43.550468 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:03:40)
1215 09:06:43.551054 setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/939161/extract-nfsrootfs-1rnnjbw7,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
1216 09:06:43.551533 Sending with 10 millisecond of delay
1218 09:06:45.906148 => bootm 0x01080000 0x08000000 0x01070000
1219 09:06:45.916750 Setting prompt string to ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1220 09:06:45.917143 bootloader-commands: Wait for prompt ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:03:38)
1221 09:06:45.917762 bootm 0x01080000 0x08000000 0x01070000
1222 09:06:45.918038 ## Booting kernel from Legacy Image at 01080000 ...
1223 09:06:45.921588 Image Name:
1224 09:06:45.927496 Image Type: AArch64 Linux Kernel Image (uncompressed)
1225 09:06:45.928110 Data Size: 45715968 Bytes = 43.6 MiB
1226 09:06:45.932862 Load Address: 01080000
1227 09:06:45.933479 Entry Point: 01080000
1228 09:06:46.127916 Verifying Checksum ... OK
1229 09:06:46.128367 ## Loading init Ramdisk from Legacy Image at 08000000 ...
1230 09:06:46.133267 Image Name:
1231 09:06:46.138807 Image Type: AArch64 Linux RAMDisk Image (uncompressed)
1232 09:06:46.139142 Data Size: 23432740 Bytes = 22.3 MiB
1233 09:06:46.144298 Load Address: 00000000
1234 09:06:46.144653 Entry Point: 00000000
1235 09:06:46.246527 Verifying Checksum ... OK
1236 09:06:46.246960 ## Flattened Device Tree blob at 01070000
1237 09:06:46.251883 Booting using the fdt blob at 0x1070000
1238 09:06:46.252259 Working FDT set to 1070000
1239 09:06:46.256489 Loading Kernel Image
1240 09:06:46.407400 Loading Ramdisk to 7e9a7000, end 7ffffe24 ... OK
1241 09:06:46.415693 Loading Device Tree to 000000007e996000, end 000000007e9a65ae ... OK
1242 09:06:46.416298 Working FDT set to 7e996000
1243 09:06:46.416742
1244 09:06:46.417681 end: 2.4.3 bootloader-commands (duration 00:00:46) [common]
1245 09:06:46.418322 start: 2.4.4 auto-login-action (timeout 00:03:37) [common]
1246 09:06:46.418831 Setting prompt string to ['Linux version [0-9]']
1247 09:06:46.419308 Setting prompt string to ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1248 09:06:46.419784 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:05:00)
1249 09:06:46.420879 Starting kernel ...
1250 09:06:46.421355
1251 09:06:46.456035 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x410fd034]
1252 09:06:46.457102 start: 2.4.4.1 login-action (timeout 00:03:37) [common]
1253 09:06:46.457608 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
1254 09:06:46.458059 Setting prompt string to []
1255 09:06:46.458525 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
1256 09:06:46.458967 Using line separator: #'\n'#
1257 09:06:46.459367 No login prompt set.
1258 09:06:46.459788 Parsing kernel messages
1259 09:06:46.460217 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
1260 09:06:46.460996 [login-action] Waiting for messages, (timeout 00:03:37)
1261 09:06:46.461437 Waiting using forced prompt support (timeout 00:01:49)
1262 09:06:46.472495 [ 0.000000] Linux version 6.12.0-rc6 (KernelCI@build-j363171-arm64-gcc-12-defconfig-zwfbh) (aarch64-linux-gnu-gcc (Debian 12.2.0-14) 12.2.0, GNU ld (GNU Binutils for Debian) 2.40) #1 SMP PREEMPT Tue Nov 5 08:37:01 UTC 2024
1263 09:06:46.478024 [ 0.000000] KASLR disabled due to lack of seed
1264 09:06:46.483644 [ 0.000000] Machine model: Libre Computer AML-A311D-CC Alta
1265 09:06:46.489045 [ 0.000000] efi: UEFI not found.
1266 09:06:46.494600 [ 0.000000] [Firmware Bug]: Kernel image misaligned at boot, please fix your bootloader!
1267 09:06:46.500658 [ 0.000000] Reserved memory: created CMA memory pool at 0x00000000e4c00000, size 256 MiB
1268 09:06:46.511124 [ 0.000000] OF: reserved mem: initialized node linux,cma, compatible id shared-dma-pool
1269 09:06:46.522131 [ 0.000000] OF: reserved mem: 0x00000000e4c00000..0x00000000f4bfffff (262144 KiB) map reusable linux,cma
1270 09:06:46.527602 [ 0.000000] OF: reserved mem: 0x0000000005000000..0x00000000052fffff (3072 KiB) nomap non-reusable secmon@5000000
1271 09:06:46.538706 [ 0.000000] OF: reserved mem: 0x0000000005300000..0x00000000072fffff (32768 KiB) nomap non-reusable secmon@5300000
1272 09:06:46.549663 [ 0.000000] earlycon: meson0 at MMIO 0x00000000ff803000 (options '115200n8')
1273 09:06:46.555218 [ 0.000000] printk: legacy bootconsole [meson0] enabled
1274 09:06:46.560757 [ 0.000000] NUMA: Faking a node at [mem 0x0000000000000000-0x00000000f4e5afff]
1275 09:06:46.566454 [ 0.000000] NODE_DATA(0) allocated [mem 0xe4666a80-0xe46690bf]
1276 09:06:46.567017 [ 0.000000] Zone ranges:
1277 09:06:46.571845 [ 0.000000] DMA [mem 0x0000000000000000-0x00000000f4e5afff]
1278 09:06:46.577368 [ 0.000000] DMA32 empty
1279 09:06:46.577910 [ 0.000000] Normal empty
1280 09:06:46.583002 [ 0.000000] Movable zone start for each node
1281 09:06:46.588247 [ 0.000000] Early memory node ranges
1282 09:06:46.594039 [ 0.000000] node 0: [mem 0x0000000000000000-0x0000000004ffffff]
1283 09:06:46.599213 [ 0.000000] node 0: [mem 0x0000000005000000-0x00000000072fffff]
1284 09:06:46.604908 [ 0.000000] node 0: [mem 0x0000000007300000-0x00000000f4e5afff]
1285 09:06:46.610443 [ 0.000000] Initmem setup node 0 [mem 0x0000000000000000-0x00000000f4e5afff]
1286 09:06:46.637699 [ 0.000000] On node 0, zone DMA: 12709 pages in unavailable ranges
1287 09:06:46.643170 [ 0.000000] psci: probing for conduit method from DT.
1288 09:06:46.643506 [ 0.000000] psci: PSCIv1.0 detected in firmware.
1289 09:06:46.652310 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
1290 09:06:46.652737 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
1291 09:06:46.657982 [ 0.000000] psci: SMC Calling Convention v1.1
1292 09:06:46.663380 [ 0.000000] percpu: Embedded 25 pages/cpu s61656 r8192 d32552 u102400
1293 09:06:46.668915 [ 0.000000] Detected VIPT I-cache on CPU0
1294 09:06:46.674411 [ 0.000000] CPU features: detected: ARM erratum 845719
1295 09:06:46.680023 [ 0.000000] alternatives: applying boot alternatives
1296 09:06:46.701976 [ 0.000000] Kernel command line: console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/939161/extract-nfsrootfs-1rnnjbw7,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp
1297 09:06:46.707440 <6>[ 0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
1298 09:06:46.718508 <6>[ 0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes, linear)
1299 09:06:46.718933 <6>[ 0.000000] Fallback order for Node 0: 0
1300 09:06:46.729573 <6>[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 1003099
1301 09:06:46.730049 <6>[ 0.000000] Policy zone: DMA
1302 09:06:46.735084 <6>[ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
1303 09:06:46.746095 <6>[ 0.000000] software IO TLB: SWIOTLB bounce buffer size adjusted to 3MB
1304 09:06:46.746540 <6>[ 0.000000] software IO TLB: area num 8.
1305 09:06:46.756356 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000dfc00000-0x00000000e0000000] (4MB)
1306 09:06:46.803772 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=6, Nodes=1
1307 09:06:46.809287 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
1308 09:06:46.812874 <6>[ 0.000000] rcu: RCU event tracing is enabled.
1309 09:06:46.818399 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=512 to nr_cpu_ids=6.
1310 09:06:46.823898 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
1311 09:06:46.829405 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
1312 09:06:46.840487 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
1313 09:06:46.846038 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=6
1314 09:06:46.851648 <6>[ 0.000000] RCU Tasks: Setting shift to 3 and lim to 1 rcu_task_cb_adjust=1 rcu_task_cpu_ids=6.
1315 09:06:46.862616 <6>[ 0.000000] RCU Tasks Trace: Setting shift to 3 and lim to 1 rcu_task_cb_adjust=1 rcu_task_cpu_ids=6.
1316 09:06:46.868206 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
1317 09:06:46.873692 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
1318 09:06:46.880030 <6>[ 0.000000] GIC: Using split EOI/Deactivate mode
1319 09:06:46.885460 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
1320 09:06:46.898194 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 24.00MHz (phys).
1321 09:06:46.909231 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x588fe9dc0, max_idle_ns: 440795202592 ns
1322 09:06:46.914909 <6>[ 0.000001] sched_clock: 56 bits at 24MHz, resolution 41ns, wraps every 4398046511097ns
1323 09:06:46.920276 <6>[ 0.008800] Console: colour dummy device 80x25
1324 09:06:46.931277 <6>[ 0.012941] Calibrating delay loop (skipped), value calculated using timer frequency.. 48.00 BogoMIPS (lpj=96000)
1325 09:06:46.936792 <6>[ 0.023294] pid_max: default: 32768 minimum: 301
1326 09:06:46.942316 <6>[ 0.028189] LSM: initializing lsm=capability
1327 09:06:46.947925 <6>[ 0.032731] Mount-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
1328 09:06:46.953322 <6>[ 0.040211] Mountpoint-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
1329 09:06:46.958927 <6>[ 0.050786] rcu: Hierarchical SRCU implementation.
1330 09:06:46.964371 <6>[ 0.053262] rcu: Max phase no-delay instances is 1000.
1331 09:06:46.975461 <6>[ 0.058866] Timer migration: 1 hierarchy levels; 8 children per group; 1 crossnode level
1332 09:06:46.980965 <6>[ 0.071577] EFI services will not be available.
1333 09:06:46.981488 <6>[ 0.072090] smp: Bringing up secondary CPUs ...
1334 09:06:46.986446 <6>[ 0.077153] Detected VIPT I-cache on CPU1
1335 09:06:46.991975 <6>[ 0.077272] CPU1: Booted secondary processor 0x0000000001 [0x410fd034]
1336 09:06:46.997536 <6>[ 0.078617] CPU features: detected: Spectre-v2
1337 09:06:47.003034 <6>[ 0.078632] CPU features: detected: Spectre-v4
1338 09:06:47.008535 <6>[ 0.078637] CPU features: detected: Spectre-BHB
1339 09:06:47.014100 <6>[ 0.078642] CPU features: detected: ARM erratum 858921
1340 09:06:47.019580 <6>[ 0.078650] Detected VIPT I-cache on CPU2
1341 09:06:47.025109 <6>[ 0.078722] arch_timer: Enabling local workaround for ARM erratum 858921
1342 09:06:47.030626 <6>[ 0.078739] arch_timer: CPU2: Trapping CNTVCT access
1343 09:06:47.036205 <6>[ 0.078749] CPU2: Booted secondary processor 0x0000000100 [0x410fd092]
1344 09:06:47.041667 <6>[ 0.079510] Detected VIPT I-cache on CPU3
1345 09:06:47.047732 <6>[ 0.079555] arch_timer: Enabling local workaround for ARM erratum 858921
1346 09:06:47.052702 <6>[ 0.079564] arch_timer: CPU3: Trapping CNTVCT access
1347 09:06:47.058291 <6>[ 0.079572] CPU3: Booted secondary processor 0x0000000101 [0x410fd092]
1348 09:06:47.063853 <6>[ 0.080280] Detected VIPT I-cache on CPU4
1349 09:06:47.069268 <6>[ 0.080326] arch_timer: Enabling local workaround for ARM erratum 858921
1350 09:06:47.074796 <6>[ 0.080336] arch_timer: CPU4: Trapping CNTVCT access
1351 09:06:47.080303 <6>[ 0.080342] CPU4: Booted secondary processor 0x0000000102 [0x410fd092]
1352 09:06:47.085956 <6>[ 0.081117] Detected VIPT I-cache on CPU5
1353 09:06:47.091338 <6>[ 0.081164] arch_timer: Enabling local workaround for ARM erratum 858921
1354 09:06:47.096972 <6>[ 0.081173] arch_timer: CPU5: Trapping CNTVCT access
1355 09:06:47.107910 <6>[ 0.081180] CPU5: Booted secondary processor 0x0000000103 [0x410fd092]
1356 09:06:47.108349 <6>[ 0.081302] smp: Brought up 1 node, 6 CPUs
1357 09:06:47.113425 <6>[ 0.203226] SMP: Total of 6 processors activated.
1358 09:06:47.118994 <6>[ 0.208130] CPU: All CPU(s) started at EL2
1359 09:06:47.124452 <6>[ 0.212475] CPU features: detected: 32-bit EL0 Support
1360 09:06:47.129993 <6>[ 0.217788] CPU features: detected: 32-bit EL1 Support
1361 09:06:47.135520 <6>[ 0.223149] CPU features: detected: CRC32 instructions
1362 09:06:47.141018 <6>[ 0.228543] alternatives: applying system-wide alternatives
1363 09:06:47.159019 <6>[ 0.235721] Memory: 3557436K/4012396K available (17280K kernel code, 4900K rwdata, 11876K rodata, 10432K init, 742K bss, 187796K reserved, 262144K cma-reserved)
1364 09:06:47.159414 <6>[ 0.250083] devtmpfs: initialized
1365 09:06:47.170046 <6>[ 0.259250] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
1366 09:06:47.175615 <6>[ 0.263608] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
1367 09:06:47.181136 <6>[ 0.274402] 21392 pages in range for non-PLT usage
1368 09:06:47.186639 <6>[ 0.274412] 512912 pages in range for PLT usage
1369 09:06:47.192203 <6>[ 0.275967] pinctrl core: initialized pinctrl subsystem
1370 09:06:47.197643 <6>[ 0.288030] DMI not present or invalid.
1371 09:06:47.203170 <6>[ 0.292343] NET: Registered PF_NETLINK/PF_ROUTE protocol family
1372 09:06:47.208703 <6>[ 0.297079] DMA: preallocated 512 KiB GFP_KERNEL pool for atomic allocations
1373 09:06:47.219716 <6>[ 0.303857] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
1374 09:06:47.225394 <6>[ 0.311953] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
1375 09:06:47.230851 <6>[ 0.319436] audit: initializing netlink subsys (disabled)
1376 09:06:47.241900 <5>[ 0.325193] audit: type=2000 audit(0.244:1): state=initialized audit_enabled=0 res=1
1377 09:06:47.247365 <6>[ 0.326674] thermal_sys: Registered thermal governor 'step_wise'
1378 09:06:47.252862 <6>[ 0.332948] thermal_sys: Registered thermal governor 'power_allocator'
1379 09:06:47.258406 <6>[ 0.339204] cpuidle: using governor menu
1380 09:06:47.264085 <6>[ 0.350184] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
1381 09:06:47.269439 <6>[ 0.357117] ASID allocator initialised with 65536 entries
1382 09:06:47.277683 <6>[ 0.364657] Serial: AMBA PL011 UART driver
1383 09:06:47.285476 <6>[ 0.375168] platform ff600000.hdmi-tx: Fixed dependency cycle(s) with /soc/vpu@ff900000
1384 09:06:47.300585 <6>[ 0.390573] platform ff600000.hdmi-tx: Fixed dependency cycle(s) with /soc/vpu@ff900000
1385 09:06:47.311642 <6>[ 0.393239] platform ff900000.vpu: Fixed dependency cycle(s) with /soc/bus@ff600000/hdmi-tx@0
1386 09:06:47.317121 <6>[ 0.406357] platform ff900000.vpu: Fixed dependency cycle(s) with /cvbs-connector
1387 09:06:47.322618 <6>[ 0.409616] platform cvbs-connector: Fixed dependency cycle(s) with /soc/vpu@ff900000
1388 09:06:47.333742 <6>[ 0.418045] platform ff600000.hdmi-tx: Fixed dependency cycle(s) with /hdmi-connector
1389 09:06:47.339176 <6>[ 0.425668] platform hdmi-connector: Fixed dependency cycle(s) with /soc/bus@ff600000/hdmi-tx@0
1390 09:06:47.350207 <6>[ 0.439229] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
1391 09:06:47.355656 <6>[ 0.441485] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
1392 09:06:47.361193 <6>[ 0.447966] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
1393 09:06:47.366718 <6>[ 0.454944] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
1394 09:06:47.377639 <6>[ 0.461413] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
1395 09:06:47.383231 <6>[ 0.468398] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
1396 09:06:47.388775 <6>[ 0.474867] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
1397 09:06:47.394311 <6>[ 0.481852] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
1398 09:06:47.399773 <6>[ 0.489860] ACPI: Interpreter disabled.
1399 09:06:47.405318 <6>[ 0.495267] iommu: Default domain type: Translated
1400 09:06:47.410887 <6>[ 0.497386] iommu: DMA domain TLB invalidation policy: strict mode
1401 09:06:47.416375 <5>[ 0.504070] SCSI subsystem initialized
1402 09:06:47.421939 <6>[ 0.507948] usbcore: registered new interface driver usbfs
1403 09:06:47.427409 <6>[ 0.513443] usbcore: registered new interface driver hub
1404 09:06:47.433047 <6>[ 0.518967] usbcore: registered new device driver usb
1405 09:06:47.438484 <6>[ 0.525229] pps_core: LinuxPPS API ver. 1 registered
1406 09:06:47.444044 <6>[ 0.529380] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
1407 09:06:47.449471 <6>[ 0.538699] PTP clock support registered
1408 09:06:47.455075 <6>[ 0.542938] EDAC MC: Ver: 3.0.0
1409 09:06:47.460529 <6>[ 0.546577] scmi_core: SCMI protocol bus registered
1410 09:06:47.461311 <6>[ 0.552177] FPGA manager framework
1411 09:06:47.466096 <6>[ 0.554961] Advanced Linux Sound Architecture Driver Initialized.
1412 09:06:47.471690 <6>[ 0.561903] vgaarb: loaded
1413 09:06:47.477122 <6>[ 0.564445] clocksource: Switched to clocksource arch_sys_counter
1414 09:06:47.482683 <5>[ 0.570607] VFS: Disk quotas dquot_6.6.0
1415 09:06:47.488182 <6>[ 0.574596] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
1416 09:06:47.493674 <6>[ 0.581806] pnp: PnP ACPI: disabled
1417 09:06:47.499271 <6>[ 0.590369] NET: Registered PF_INET protocol family
1418 09:06:47.504760 <6>[ 0.590622] IP idents hash table entries: 65536 (order: 7, 524288 bytes, linear)
1419 09:06:47.515790 <6>[ 0.600790] tcp_listen_portaddr_hash hash table entries: 2048 (order: 3, 32768 bytes, linear)
1420 09:06:47.521265 <6>[ 0.606793] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
1421 09:06:47.532361 <6>[ 0.614691] TCP established hash table entries: 32768 (order: 6, 262144 bytes, linear)
1422 09:06:47.537841 <6>[ 0.622931] TCP bind hash table entries: 32768 (order: 8, 1048576 bytes, linear)
1423 09:06:47.543346 <6>[ 0.630723] TCP: Hash tables configured (established 32768 bind 32768)
1424 09:06:47.548889 <6>[ 0.637202] UDP hash table entries: 2048 (order: 4, 65536 bytes, linear)
1425 09:06:47.559998 <6>[ 0.644049] UDP-Lite hash table entries: 2048 (order: 4, 65536 bytes, linear)
1426 09:06:47.565476 <6>[ 0.651474] NET: Registered PF_UNIX/PF_LOCAL protocol family
1427 09:06:47.570935 <6>[ 0.657591] RPC: Registered named UNIX socket transport module.
1428 09:06:47.576452 <6>[ 0.663336] RPC: Registered udp transport module.
1429 09:06:47.582049 <6>[ 0.668243] RPC: Registered tcp transport module.
1430 09:06:47.587477 <6>[ 0.673157] RPC: Registered tcp-with-tls transport module.
1431 09:06:47.593042 <6>[ 0.678851] RPC: Registered tcp NFSv4.1 backchannel transport module.
1432 09:06:47.598527 <6>[ 0.685498] PCI: CLS 0 bytes, default 64
1433 09:06:47.598947 <6>[ 0.689763] Unpacking initramfs...
1434 09:06:47.604129 <6>[ 0.695836] kvm [1]: nv: 554 coarse grained trap handlers
1435 09:06:47.609574 <6>[ 0.699177] kvm [1]: IPA Size Limit: 40 bits
1436 09:06:47.615124 <6>[ 0.704794] kvm [1]: vgic interrupt IRQ9
1437 09:06:47.620608 <6>[ 0.707507] kvm [1]: Hyp nVHE mode initialized successfully
1438 09:06:47.626121 <5>[ 0.714558] Initialise system trusted keyrings
1439 09:06:47.631652 <6>[ 0.718139] workingset: timestamp_bits=42 max_order=20 bucket_order=0
1440 09:06:47.637109 <6>[ 0.724824] squashfs: version 4.0 (2009/01/31) Phillip Lougher
1441 09:06:47.642691 <5>[ 0.730876] NFS: Registering the id_resolver key type
1442 09:06:47.648305 <5>[ 0.735902] Key type id_resolver registered
1443 09:06:47.653714 <5>[ 0.740264] Key type id_legacy registered
1444 09:06:47.659229 <6>[ 0.744517] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
1445 09:06:47.664741 <6>[ 0.751389] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
1446 09:06:47.671749 <6>[ 0.759172] 9p: Installing v9fs 9p2000 file system support
1447 09:06:47.709654 <5>[ 0.805317] Key type asymmetric registered
1448 09:06:47.715062 <5>[ 0.805360] Asymmetric key parser 'x509' registered
1449 09:06:47.726347 <6>[ 0.809213] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 245)
1450 09:06:47.726987 <6>[ 0.816737] io scheduler mq-deadline registered
1451 09:06:47.731789 <6>[ 0.821480] io scheduler kyber registered
1452 09:06:47.737359 <6>[ 0.825743] io scheduler bfq registered
1453 09:06:47.743772 <6>[ 0.831621] irq_meson_gpio: 100 to 8 gpio interrupt mux initialized
1454 09:06:47.759878 <6>[ 0.851758] ledtrig-cpu: registered to indicate activity on CPUs
1455 09:06:47.791443 <6>[ 0.883029] soc soc0: Amlogic Meson G12B (A311D) Revision 29:b (10:2) Detected
1456 09:06:47.812019 <6>[ 0.896309] Serial: 8250/16550 driver, 4 ports,<6>[ 0.901008] ff803000.serial: ttyAML0 at MMIO 0xff803000 (irq = 14, base_baud = 1500000) is a meson_uart
1457 09:06:47.817492 <6>[ 0.910628] printk: legacy console [ttyAML0] enabled
1458 09:06:47.823135 <6>[ 0.910628] printk: legacy console [ttyAML0] enabled
1459 09:06:47.828575 <6>[ 0.915433] printk: legacy bootconsole [meson0] disabled
1460 09:06:47.834111 <6>[ 0.915433] printk: legacy bootconsole [meson0] disabled
1461 09:06:47.839652 <6>[ 0.929296] msm_serial: driver initialized
1462 09:06:47.845212 <6>[ 0.931343] SuperH (H)SCI(F) driver initialized
1463 09:06:47.845755 <6>[ 0.935888] STM32 USART driver initialized
1464 09:06:47.850756 <5>[ 0.942094] random: crng init done
1465 09:06:47.857845 <6>[ 0.947554] loop: module loaded
1466 09:06:47.858381 <6>[ 0.948857] megasas: 07.727.03.00-rc1
1467 09:06:47.863455 <6>[ 0.958039] tun: Universal TUN/TAP device driver, 1.6
1468 09:06:47.869076 <6>[ 0.959282] thunder_xcv, ver 1.0
1469 09:06:47.874513 <6>[ 0.961215] thunder_bgx, ver 1.0
1470 09:06:47.875044 <6>[ 0.964673] nicpf, ver 1.0
1471 09:06:47.880124 <6>[ 0.969230] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
1472 09:06:47.885583 <6>[ 0.975054] hns3: Copyright (c) 2017 Huawei Corporation.
1473 09:06:47.891137 <6>[ 0.980641] hclge is initializing
1474 09:06:47.896672 <6>[ 0.984171] e1000: Intel(R) PRO/1000 Network Driver
1475 09:06:47.902132 <6>[ 0.989265] e1000: Copyright (c) 1999-2006 Intel Corporation.
1476 09:06:47.907738 <6>[ 0.995280] e1000e: Intel(R) PRO/1000 Network Driver
1477 09:06:47.913266 <6>[ 1.000445] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
1478 09:06:47.918998 <6>[ 1.006627] igb: Intel(R) Gigabit Ethernet Network Driver
1479 09:06:47.924530 <6>[ 1.012232] igb: Copyright (c) 2007-2014 Intel Corporation.
1480 09:06:47.929948 <6>[ 1.018066] igbvf: Intel(R) Gigabit Virtual Function Network Driver
1481 09:06:47.935450 <6>[ 1.024536] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
1482 09:06:47.941036 <6>[ 1.031293] sky2: driver version 1.30
1483 09:06:47.946466 <6>[ 1.036425] VFIO - User Level meta-driver version: 0.3
1484 09:06:47.952035 <6>[ 1.043887] usbcore: registered new interface driver usb-storage
1485 09:06:47.958146 <6>[ 1.049955] i2c_dev: i2c /dev entries driver
1486 09:06:47.971033 <6>[ 1.061119] sdhci: Secure Digital Host Controller Interface driver
1487 09:06:47.971619 <6>[ 1.061916] sdhci: Copyright(c) Pierre Ossman
1488 09:06:47.980008 <6>[ 1.067634] Synopsys Designware Multimedia Card Interface Driver
1489 09:06:47.985504 <6>[ 1.074181] sdhci-pltfm: SDHCI platform and OF driver helper
1490 09:06:47.991075 <6>[ 1.081800] meson-sm: secure-monitor enabled
1491 09:06:47.996599 <6>[ 1.084308] usbcore: registered new interface driver usbhid
1492 09:06:48.000406 <6>[ 1.088981] usbhid: USB HID core driver
1493 09:06:48.008034 <6>[ 1.103711] NET: Registered PF_PACKET protocol family
1494 09:06:48.013608 <6>[ 1.103802] 9pnet: Installing 9P2000 support
1495 09:06:48.020740 <5>[ 1.107963] Key type dns_resolver registered
1496 09:06:48.028133 <6>[ 1.119632] registered taskstats version 1
1497 09:06:48.028631 <5>[ 1.119785] Loading compiled-in X.509 certificates
1498 09:06:48.035240 <6>[ 1.128489] Demotion targets for Node 0: null
1499 09:06:48.064610 <6>[ 1.160032] dwc3-meson-g12a ffe09000.usb: USB2 ports: 2
1500 09:06:48.069980 <6>[ 1.160071] dwc3-meson-g12a ffe09000.usb: USB3 ports: 1
1501 09:06:48.078913 <4>[ 1.169293] dwc2 ff400000.usb: supply vusb_d not found, using dummy regulator
1502 09:06:48.084403 <4>[ 1.172811] dwc2 ff400000.usb: supply vusb_a not found, using dummy regulator
1503 09:06:48.095691 <6>[ 1.180332] dwc2 ff400000.usb: EPs: 7, dedicated fifos, 712 entries in SPRAM
1504 09:06:48.101148 <6>[ 1.189675] xhci-hcd xhci-hcd.0.auto: xHCI Host Controller
1505 09:06:48.106685 <6>[ 1.193124] xhci-hcd xhci-hcd.0.auto: new USB bus registered, assigned bus number 1
1506 09:06:48.117851 <6>[ 1.201094] xhci-hcd xhci-hcd.0.auto: hcc params 0x0228fe6c hci version 0x110 quirks 0x0000808000000010
1507 09:06:48.123331 <6>[ 1.210631] xhci-hcd xhci-hcd.0.auto: irq 16, io mem 0xff500000
1508 09:06:48.128767 <6>[ 1.216858] xhci-hcd xhci-hcd.0.auto: xHCI Host Controller
1509 09:06:48.139947 <6>[ 1.222479] xhci-hcd xhci-hcd.0.auto: new USB bus registered, assigned bus number 2
1510 09:06:48.145485 <6>[ 1.230364] xhci-hcd xhci-hcd.0.auto: Host supports USB 3.0 SuperSpeed
1511 09:06:48.145936 <6>[ 1.237617] hub 1-0:1.0: USB hub found
1512 09:06:48.151102 <6>[ 1.241131] hub 1-0:1.0: 2 ports detected
1513 09:06:48.162141 <6>[ 1.247173] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
1514 09:06:48.162635 <6>[ 1.254078] hub 2-0:1.0: USB hub found
1515 09:06:48.169404 <6>[ 1.257675] hub 2-0:1.0: 1 port detected
1516 09:06:48.195409 <6>[ 1.288359] meson-gx-mmc ffe05000.mmc: Got CD GPIO
1517 09:06:48.207393 <6>[ 1.299660] meson-gx-mmc ffe07000.mmc: allocated mmc-pwrseq
1518 09:06:48.242579 <6>[ 1.334566] Trying to probe devices needed for running init ...
1519 09:06:48.401199 <6>[ 1.492474] usb 1-1: new high-speed USB device number 2 using xhci-hcd
1520 09:06:48.549744 <6>[ 1.639821] mmc0: new ultra high speed SDR104 SDXC card at address e624
1521 09:06:48.557077 <6>[ 1.642013] mmcblk0: mmc0:e624 SD64G 59.5 GiB
1522 09:06:48.557546 <6>[ 1.647910] mmcblk0: p1
1523 09:06:48.561948 <6>[ 1.655776] Freeing initrd memory: 22880K
1524 09:06:48.590093 <6>[ 1.685447] hub 1-1:1.0: USB hub found
1525 09:06:48.595753 <6>[ 1.685729] hub 1-1:1.0: 4 ports detected
1526 09:06:48.657283 <6>[ 1.748587] usb 2-1: new SuperSpeed USB device number 2 using xhci-hcd
1527 09:06:48.702621 <6>[ 1.798110] hub 2-1:1.0: USB hub found
1528 09:06:48.708356 <6>[ 1.798931] hub 2-1:1.0: 4 ports detected
1529 09:07:00.521029 <6>[ 13.616504] clk: Disabling unused clocks
1530 09:07:00.526468 <6>[ 13.616671] PM: genpd: Disabling unused power domains
1531 09:07:00.534860 <6>[ 13.620363] ALSA device list:
1532 09:07:00.535414 <6>[ 13.623570] No soundcards found.
1533 09:07:00.540201 <6>[ 13.635870] Freeing unused kernel memory: 10432K
1534 09:07:00.546517 <6>[ 13.635967] Run /init as init process
1535 09:07:00.552406 Loading, please wait...
1536 09:07:00.584473 Starting systemd-udevd version 252.22-1~deb12u1
1537 09:07:01.000707 <6>[ 14.094768] mc: Linux media interface: v0.10
1538 09:07:01.007452 <6>[ 14.100831] videodev: Linux video capture interface: v2.00
1539 09:07:01.021438 <6>[ 14.117107] Registered IR keymap rc-empty
1540 09:07:01.032457 <6>[ 14.117237] rc rc0: meson-ir as /devices/platform/soc/ff800000.bus/ff808000.ir/rc/rc0
1541 09:07:01.041381 <6>[ 14.123991] input: meson-ir as /devices/platform/soc/ff800000.bus/ff808000.ir/rc/rc0/input0
1542 09:07:01.046953 <6>[ 14.125623] meson-drm ff900000.vpu: Queued 2 outputs on vpu
1543 09:07:01.052478 <4>[ 14.134043] meson_vdec: module is from the staging directory, the quality is unknown, you have been warned.
1544 09:07:01.058070 <6>[ 14.138298] rc rc0: sw decoder init
1545 09:07:01.063586 <6>[ 14.151956] meson-ir ff808000.ir: receiver initialized
1546 09:07:01.069124 <6>[ 14.159362] meson-vrtc ff8000a8.rtc: registered as rtc0
1547 09:07:01.077592 <6>[ 14.162790] meson-vrtc ff8000a8.rtc: setting system clock to 1970-01-01T00:00:14 UTC (14)
1548 09:07:01.111012 <6>[ 14.201153] meson8b-dwmac ff3f0000.ethernet: IRQ eth_wake_irq not found
1549 09:07:01.116868 <6>[ 14.204075] meson8b-dwmac ff3f0000.ethernet: IRQ eth_lpi not found
1550 09:07:01.125570 <3>[ 14.205343] debugfs: Directory 'ff800280.cec' with parent 'regmap' already present!
1551 09:07:01.131090 <6>[ 14.208877] meson8b-dwmac ff3f0000.ethernet: IRQ sfty not found
1552 09:07:01.136743 <4>[ 14.210158] meson-pwm ff802000.pwm: using obsolete compatible, please consider updating dt
1553 09:07:01.145767 <6>[ 14.231551] meson8b-dwmac ff3f0000.ethernet: PTP uses main clock
1554 09:07:01.151317 <6>[ 14.243258] meson8b-dwmac ff3f0000.ethernet: User ID: 0x11, Synopsys ID: 0x37
1555 09:07:01.156974 <6>[ 14.245083] meson8b-dwmac ff3f0000.ethernet: DWMAC1000
1556 09:07:01.162424 <6>[ 14.245460] panfrost ffe40000.gpu: clock rate = 24000000
1557 09:07:01.173587 <6>[ 14.250510] meson8b-dwmac ff3f0000.ethernet: DMA HW capability register supported
1558 09:07:01.179139 <6>[ 14.250528] meson8b-dwmac ff3f0000.ethernet: RX Checksum Offload Engine supported
1559 09:07:01.190305 <6>[ 14.252809] meson-dw-hdmi ff600000.hdmi-tx: Detected HDMI TX controller v2.01a with HDCP (meson_dw_hdmi_phy)
1560 09:07:01.195822 <3>[ 14.256269] panfrost ffe40000.gpu: error -ENODEV: _opp_set_regulators: no regulator (mali) found
1561 09:07:01.207027 <6>[ 14.257343] meson-dw-hdmi ff600000.hdmi-tx: registered DesignWare HDMI I2C bus driver
1562 09:07:01.212283 <6>[ 14.257964] meson-drm ff900000.vpu: bound ff600000.hdmi-tx (ops meson_dw_hdmi_ops [meson_dw_hdmi])
1563 09:07:01.223382 <3>[ 14.258056] meson-drm ff900000.vpu: DSI transceiver device is disabled
1564 09:07:01.228952 <6>[ 14.258558] [drm] Initialized meson 1.0.0 for ff900000.vpu on minor 0
1565 09:07:01.234494 <6>[ 14.263762] meson8b-dwmac ff3f0000.ethernet: COE Type 2
1566 09:07:01.240101 <6>[ 14.263779] meson8b-dwmac ff3f0000.ethernet: TX Checksum insertion supported
1567 09:07:01.245618 <6>[ 14.263784] meson8b-dwmac ff3f0000.ethernet: Wake-Up On Lan supported
1568 09:07:01.256665 <6>[ 14.271850] meson8b-dwmac ff3f0000.ethernet: Normal descriptors
1569 09:07:01.262319 <6>[ 14.285903] panfrost ffe40000.gpu: mali-g52 id 0x7212 major 0x0 minor 0x0 status 0x0
1570 09:07:01.267976 <6>[ 14.298667] meson8b-dwmac ff3f0000.ethernet: Ring mode enabled
1571 09:07:01.279042 <6>[ 14.307789] panfrost ffe40000.gpu: features: 00000000,00000cf7, issues: 00000000,00000400
1572 09:07:01.290019 <6>[ 14.307803] panfrost ffe40000.gpu: Features: L2:0x07110206 Shader:0x00000000 Tiler:0x00000809 Mem:0x1 MMU:0x00002830 AS:0xff JS:0x7
1573 09:07:01.295575 <6>[ 14.307813] panfrost ffe40000.gpu: shader_present=0x3 l2_present=0x1
1574 09:07:01.301126 <6>[ 14.308149] usbcore: registered new device driver onboard-usb-dev
1575 09:07:01.312397 <6>[ 14.314606] meson8b-dwmac ff3f0000.ethernet: Enable RX Mitigation via HW Watchdog Timer
1576 09:07:01.317780 <6>[ 14.336840] [drm] Initialized panfrost 1.2.0 for ffe40000.gpu on minor 1
1577 09:07:01.322539 <6>[ 14.404059] meson8b-dwmac ff3f0000.ethernet end0: renamed from eth0
1578 09:07:01.501612 <6>[ 14.569262] Console: switching to colour frame buffer device 128x48
1579 09:07:01.506513 <6>[ 14.592541] meson-drm ff900000.vpu: [drm] fb0: mesondrmfb frame buffer device
1580 09:07:01.595731 <6>[ 14.683880] cpufreq: cpufreq_online: CPU2: Running at unlisted initial frequency: 999999 KHz, changing to: 1000000 KHz
1581 09:07:01.742153 <6>[ 14.837571] hub 1-1:1.0: USB hub found
1582 09:07:01.747549 <6>[ 14.837923] hub 1-1:1.0: 4 ports detected
1583 09:07:01.753206 <6>[ 14.843358] onboard-usb-dev 1-1: USB disconnect, device number 2
1584 09:07:02.049340 <6>[ 15.141436] usb 2-1: reset SuperSpeed USB device number 2 using xhci-hcd
1585 09:07:02.184820 <6>[ 15.276495] usb 1-1: new high-speed USB device number 3 using xhci-hcd
1586 09:07:02.382018 <6>[ 15.477545] hub 1-1:1.0: USB hub found
1587 09:07:02.386607 <6>[ 15.477909] hub 1-1:1.0: 4 ports detected
1588 09:07:02.394166 Begin: Loading essential drivers ... done.
1589 09:07:02.399690 Begin: Running /scripts/init-premount ... done.
1590 09:07:02.405244 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
1591 09:07:02.417961 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
1592 09:07:02.418470 Device /sys/class/net/end0 found
1593 09:07:02.418917 done.
1594 09:07:02.439482 Begin: Waiting up to 180 secs for any network device to become available ... done.
1595 09:07:02.480238 IP-Config: end0 hardware address de:ca:d3:e3:c6:63 mtu 1500 DHCP
<6>[ 15.566192] meson8b-dwmac ff3f0000.ethernet end0: Register MEM_TYPE_PAGE_POOL RxQ-0
1596 09:07:02.480885
1597 09:07:02.569309 <6>[ 15.656625] meson8b-dwmac ff3f0000.ethernet end0: PHY [mdio_mux-0.0:00] driver [RTL8211F Gigabit Ethernet] (irq=32)
1598 09:07:02.582651 <6>[ 15.672738] meson8b-dwmac ff3f0000.ethernet end0: No Safety Features support found
1599 09:07:02.588263 <6>[ 15.674938] meson8b-dwmac ff3f0000.ethernet end0: PTP not supported by HW
1600 09:07:02.597471 <6>[ 15.682478] meson8b-dwmac ff3f0000.ethernet end0: configuring for phy/rgmii link mode
1601 09:07:04.569023 IP-Config: no response after 2 secs - giving up
1602 09:07:04.608185 IP-Config: end0 hardware address de:ca:d3:e3:c6:63 mtu 1500 DHCP
1603 09:07:05.551504 <6>[ 18.641062] meson8b-dwmac ff3f0000.ethernet end0: Link is Up - 1Gbps/Full - flow control off
1604 09:07:06.348963 <4>[ 19.444476] rc rc0: two consecutive events of type space
1605 09:07:06.825596 IP-Config: end0 guessed broadcast address 192.168.6.255
1606 09:07:06.830910 IP-Config: end0 complete (dhcp from 192.168.6.1):
1607 09:07:06.836534 address: 192.168.6.27 broadcast: 192.168.6.255 netmask: 255.255.255.0
1608 09:07:06.847657 gateway: 192.168.6.1 dns0 : 10.255.253.1 dns1 : 0.0.0.0
1609 09:07:06.848018 rootserver: 192.168.6.1 rootpath:
1610 09:07:06.851179 filename :
1611 09:07:06.950332 done.
1612 09:07:06.956329 Begin: Running /scripts/nfs-bottom ... done.
1613 09:07:06.968282 Begin: Running /scripts/init-bottom ... done.
1614 09:07:07.315544 <30>[ 20.406594] systemd[1]: System time before build time, advancing clock.
1615 09:07:07.375337 <6>[ 20.470730] NET: Registered PF_INET6 protocol family
1616 09:07:07.380724 <6>[ 20.472557] Segment Routing with IPv6
1617 09:07:07.386038 <6>[ 20.474234] In-situ OAM (IOAM) with IPv6
1618 09:07:07.464071 <30>[ 20.531848] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
1619 09:07:07.469500 <30>[ 20.559213] systemd[1]: Detected architecture arm64.
1620 09:07:07.469953
1621 09:07:07.477252 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
1622 09:07:07.477559
1623 09:07:07.486380 <30>[ 20.578168] systemd[1]: Hostname set to <debian-bookworm-arm64>.
1624 09:07:08.188302 <30>[ 21.278582] systemd[1]: Queued start job for default target graphical.target.
1625 09:07:08.229372 <30>[ 21.318803] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
1626 09:07:08.236848 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
1627 09:07:08.247629 <30>[ 21.337452] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
1628 09:07:08.255876 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
1629 09:07:08.267583 <30>[ 21.357510] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
1630 09:07:08.281043 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
1631 09:07:08.286528 <30>[ 21.377198] systemd[1]: Created slice user.slice - User and Session Slice.
1632 09:07:08.292993 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
1633 09:07:08.304034 <30>[ 21.392722] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
1634 09:07:08.315513 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
1635 09:07:08.326563 <30>[ 21.412661] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
1636 09:07:08.333068 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
1637 09:07:08.355042 <30>[ 21.432646] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
1638 09:07:08.360615 <30>[ 21.446716] systemd[1]: Expecting device dev-ttyAML0.device - /dev/ttyAML0...
1639 09:07:08.368245 Expecting device [0;1;39mdev-ttyAML0.device[0m - /dev/ttyAML0...
1640 09:07:08.379326 <30>[ 21.468547] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
1641 09:07:08.386483 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
1642 09:07:08.402408 <30>[ 21.492564] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
1643 09:07:08.416123 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
1644 09:07:08.421609 <30>[ 21.512595] systemd[1]: Reached target paths.target - Path Units.
1645 09:07:08.430060 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
1646 09:07:08.435607 <30>[ 21.528554] systemd[1]: Reached target remote-fs.target - Remote File Systems.
1647 09:07:08.447403 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
1648 09:07:08.452949 <30>[ 21.544539] systemd[1]: Reached target slices.target - Slice Units.
1649 09:07:08.461011 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
1650 09:07:08.466551 <30>[ 21.560558] systemd[1]: Reached target swap.target - Swaps.
1651 09:07:08.474450 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
1652 09:07:08.486380 <30>[ 21.576578] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
1653 09:07:08.495265 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
1654 09:07:08.510558 <30>[ 21.600748] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
1655 09:07:08.519843 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
1656 09:07:08.531746 <30>[ 21.621874] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
1657 09:07:08.540745 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
1658 09:07:08.551849 <30>[ 21.641405] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
1659 09:07:08.565008 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
1660 09:07:08.570502 <30>[ 21.660898] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
1661 09:07:08.577326 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
1662 09:07:08.588378 <30>[ 21.677470] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
1663 09:07:08.596437 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
1664 09:07:08.608387 <30>[ 21.698530] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
1665 09:07:08.613911 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
1666 09:07:08.628413 <30>[ 21.716791] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
1667 09:07:08.635068 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
1668 09:07:08.674585 <30>[ 21.764700] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
1669 09:07:08.681327 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
1670 09:07:08.693122 <30>[ 21.783153] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
1671 09:07:08.700583 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
1672 09:07:08.717101 <30>[ 21.806945] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
1673 09:07:08.725186 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
1674 09:07:08.742257 <30>[ 21.825184] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
1675 09:07:08.753334 <30>[ 21.840813] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
1676 09:07:08.759163 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
1677 09:07:08.775479 <30>[ 21.865622] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
1678 09:07:08.783377 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
1679 09:07:08.803452 <30>[ 21.893627] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
1680 09:07:08.811089 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
1681 09:07:08.828918 <6>[ 21.918968] device-mapper: ioctl: 4.48.0-ioctl (2023-03-01) initialised: dm-devel@lists.linux.dev
1682 09:07:08.837919 <30>[ 21.919737] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
1683 09:07:08.844842 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
1684 09:07:08.859383 <30>[ 21.949559] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
1685 09:07:08.867698 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
1686 09:07:08.883559 <30>[ 21.973721] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
1687 09:07:08.890914 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
1688 09:07:08.902392 <6>[ 21.998118] fuse: init (API version 7.41)
1689 09:07:08.913482 <30>[ 21.999594] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
1690 09:07:08.917412 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
1691 09:07:08.942949 <30>[ 22.033128] systemd[1]: Starting systemd-journald.service - Journal Service...
1692 09:07:08.949332 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
1693 09:07:08.969987 <30>[ 22.060088] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
1694 09:07:08.977450 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
1695 09:07:08.992250 <30>[ 22.082270] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
1696 09:07:09.001646 Starting [0;1;39msystemd-network-g… units from Kernel command line...
1697 09:07:09.016426 <30>[ 22.106440] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
1698 09:07:09.025143 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
1699 09:07:09.036948 <30>[ 22.126927] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
1700 09:07:09.044906 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
1701 09:07:09.056659 <30>[ 22.146709] systemd[1]: Started systemd-journald.service - Journal Service.
1702 09:07:09.063488 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
1703 09:07:09.075820 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
1704 09:07:09.087128 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
1705 09:07:09.103220 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
1706 09:07:09.119451 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
1707 09:07:09.135717 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
1708 09:07:09.147679 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
1709 09:07:09.163308 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
1710 09:07:09.179680 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
1711 09:07:09.195523 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
1712 09:07:09.211514 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
1713 09:07:09.227491 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
1714 09:07:09.243489 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
1715 09:07:09.259398 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
1716 09:07:09.275771 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
1717 09:07:09.318157 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
1718 09:07:09.328513 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
1719 09:07:09.340193 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
1720 09:07:09.352741 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
1721 09:07:09.366574 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
1722 09:07:09.382243 <46>[ 22.472092] systemd-journald[237]: Received client request to flush runtime journal.
1723 09:07:09.392861 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
1724 09:07:09.411099 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
1725 09:07:09.418498 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
1726 09:07:09.435537 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
1727 09:07:09.451859 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
1728 09:07:09.467458 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
1729 09:07:09.535251 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
1730 09:07:09.586340 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
1731 09:07:09.663694 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
1732 09:07:09.707399 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
1733 09:07:09.727085 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
1734 09:07:09.742248 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
1735 09:07:09.794293 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
1736 09:07:09.808980 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
1737 09:07:10.058309 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
1738 09:07:10.122687 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
1739 09:07:10.143885 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
1740 09:07:10.150306 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
1741 09:07:10.220206 [[0;32m OK [0m] Found device [0;1;39mdev-ttyAML0.device[0m - /dev/ttyAML0.
1742 09:07:10.232748 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
1743 09:07:10.274429 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
1744 09:07:10.295613 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
1745 09:07:10.307362 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
1746 09:07:10.319065 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
1747 09:07:10.334248 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
1748 09:07:10.357953 <46>[ 23.436951] systemd-journald[237]: Oldest entry in /var/log/journal/44a983756b26438995e691b947c527e4/system.journal is older than the configured file retention duration (1month), suggesting rotation.
1749 09:07:10.369458 [[<46>[ 23.449716] systemd-journald[237]: /var/log/journal/44a983756b26438995e691b947c527e4/system.journal: Journal header limits reached or header out-of-date, rotating.
1750 09:07:10.379770 0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
1751 09:07:10.393570 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
1752 09:07:10.410835 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
1753 09:07:10.499375 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
1754 09:07:10.519659 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
1755 09:07:10.529684 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
1756 09:07:10.566600 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
1757 09:07:10.573449 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
1758 09:07:10.578783 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
1759 09:07:10.589680 <5>[ 23.677595] cfg80211: Loading compiled-in X.509 certificates for regulatory database
1760 09:07:10.646091 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
1761 09:07:10.658488 <5>[ 23.748564] Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
1762 09:07:10.664022 <5>[ 23.749423] Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
1763 09:07:10.675223 <4>[ 23.756739] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
1764 09:07:10.675962 <6>[ 23.765389] cfg80211: failed to load regulatory.db
1765 09:07:10.685082 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
1766 09:07:10.736379 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
1767 09:07:10.743687 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
1768 09:07:10.761978 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
1769 09:07:10.776343 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
1770 09:07:10.811070 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
1771 09:07:10.826668 [[0;32m OK [0m] Reached target [0;1;39musb-gadget.…m - Hardware activated USB gadget.
1772 09:07:10.833175 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
1773 09:07:10.886549 Starting [0;1;39malsa-restore.serv…- Save/Restore Sound Card State...
1774 09:07:10.905052 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
1775 09:07:10.917110 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
1776 09:07:10.930507 [[0;32m OK [0m] Finished [0;1;39malsa-restore.serv…m - Save/Restore Sound Card State.
1777 09:07:10.950067 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
1778 09:07:10.960036 [[0;32m OK [0m] Reached target [0;1;39msound.target[0m - Sound Card.
1779 09:07:11.002999 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
1780 09:07:11.024102 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyAM…ice[0m - Serial Getty on ttyAML0.
1781 09:07:11.031301 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
1782 09:07:11.043355 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
1783 09:07:11.055433 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
1784 09:07:11.095394 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
1785 09:07:11.141806 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
1786 09:07:11.228730
1787 09:07:11.229278 Debian GNU/Linux 12 debian-bookworm-arm64 ttyAML0
1788 09:07:11.229598
1789 09:07:11.236124 debian-bookworm-arm64 login: root (automatic login)
1790 09:07:11.236866
1791 09:07:11.372022 Linux debian-bookworm-arm64 6.12.0-rc6 #1 SMP PREEMPT Tue Nov 5 08:37:01 UTC 2024 aarch64
1792 09:07:11.372646
1793 09:07:11.377604 The programs included with the Debian GNU/Linux system are free software;
1794 09:07:11.383145 the exact distribution terms for each program are described in the
1795 09:07:11.388848 individual files in /usr/share/doc/*/copyright.
1796 09:07:11.389402
1797 09:07:11.394215 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
1798 09:07:11.397380 permitted by applicable law.
1799 09:07:12.073489 Matched prompt #10: / #
1801 09:07:12.075028 Setting prompt string to ['/ #']
1802 09:07:12.075598 end: 2.4.4.1 login-action (duration 00:00:26) [common]
1804 09:07:12.077065 end: 2.4.4 auto-login-action (duration 00:00:26) [common]
1805 09:07:12.077609 start: 2.4.5 expect-shell-connection (timeout 00:03:12) [common]
1806 09:07:12.078048 Setting prompt string to ['/ #']
1807 09:07:12.078463 Forcing a shell prompt, looking for ['/ #']
1809 09:07:12.129433 / #
1810 09:07:12.130382 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
1811 09:07:12.130903 Waiting using forced prompt support (timeout 00:02:30)
1812 09:07:12.136310
1813 09:07:12.137387 end: 2.4.5 expect-shell-connection (duration 00:00:00) [common]
1814 09:07:12.138176 start: 2.4.6 export-device-env (timeout 00:03:12) [common]
1815 09:07:12.138801 Sending with 10 millisecond of delay
1817 09:07:17.131608 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/939161/extract-nfsrootfs-1rnnjbw7'
1818 09:07:17.142568 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/939161/extract-nfsrootfs-1rnnjbw7'
1819 09:07:17.143354 Sending with 10 millisecond of delay
1821 09:07:19.242166 / # export NFS_SERVER_IP='192.168.6.2'
1822 09:07:19.253062 export NFS_SERVER_IP='192.168.6.2'
1823 09:07:19.254149 end: 2.4.6 export-device-env (duration 00:00:07) [common]
1824 09:07:19.254756 end: 2.4 uboot-commands (duration 00:01:55) [common]
1825 09:07:19.255474 end: 2 uboot-action (duration 00:01:55) [common]
1826 09:07:19.256145 start: 3 lava-test-retry (timeout 00:06:45) [common]
1827 09:07:19.256733 start: 3.1 lava-test-shell (timeout 00:06:45) [common]
1828 09:07:19.257197 Using namespace: common
1830 09:07:19.358337 / # #
1831 09:07:19.359009 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
1832 09:07:19.363822 #
1833 09:07:19.364381 Using /lava-939161
1835 09:07:19.465116 / # export SHELL=/bin/bash
1836 09:07:19.470294 export SHELL=/bin/bash
1838 09:07:19.571379 / # . /lava-939161/environment
1839 09:07:19.574931 . /lava-939161/environment
1841 09:07:19.680429 / # /lava-939161/bin/lava-test-runner /lava-939161/0
1842 09:07:19.681224 Test shell timeout: 10s (minimum of the action and connection timeout)
1843 09:07:19.684198 /lava-939161/bin/lava-test-runner /lava-939161/0
1844 09:07:19.868208 + export TESTRUN_ID=0_timesync-off
1845 09:07:19.876421 + TESTRUN_ID=0_timesync-off
1846 09:07:19.876973 + cd /lava-939161/0/tests/0_timesync-off
1847 09:07:19.877435 ++ cat uuid
1848 09:07:19.881916 + UUID=939161_1.6.2.4.1
1849 09:07:19.882405 + set +x
1850 09:07:19.889736 <LAVA_SIGNAL_STARTRUN 0_timesync-off 939161_1.6.2.4.1>
1851 09:07:19.890230 + systemctl stop systemd-timesyncd
1852 09:07:19.890966 Received signal: <STARTRUN> 0_timesync-off 939161_1.6.2.4.1
1853 09:07:19.891442 Starting test lava.0_timesync-off (939161_1.6.2.4.1)
1854 09:07:19.892050 Skipping test definition patterns.
1855 09:07:19.926687 + set +x
1856 09:07:19.927304 <LAVA_SIGNAL_ENDRUN 0_timesync-off 939161_1.6.2.4.1>
1857 09:07:19.928060 Received signal: <ENDRUN> 0_timesync-off 939161_1.6.2.4.1
1858 09:07:19.928639 Ending use of test pattern.
1859 09:07:19.929119 Ending test lava.0_timesync-off (939161_1.6.2.4.1), duration 0.04
1861 09:07:20.000972 + export TESTRUN_ID=1_kselftest-alsa
1862 09:07:20.009222 + TESTRUN_ID=1_kselftest-alsa
1863 09:07:20.009761 + cd /lava-939161/0/tests/1_kselftest-alsa
1864 09:07:20.010253 ++ cat uuid
1865 09:07:20.020343 + UUID=939161_1.6.2.4.5
1866 09:07:20.020910 + set +x
1867 09:07:20.025875 <LAVA_SIGNAL_STARTRUN 1_kselftest-alsa 939161_1.6.2.4.5>
1868 09:07:20.026438 + cd ./automated/linux/kselftest/
1869 09:07:20.027185 Received signal: <STARTRUN> 1_kselftest-alsa 939161_1.6.2.4.5
1870 09:07:20.027657 Starting test lava.1_kselftest-alsa (939161_1.6.2.4.5)
1871 09:07:20.028248 Skipping test definition patterns.
1872 09:07:20.054741 + ./kselftest.sh -c alsa -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/next/pending-fixes/v6.12-rc6-192-g566383b19a748/arm64/defconfig/gcc-12/kselftest.tar.xz -L '' -S /dev/null -b meson-g12b-a311d-libretech-cc -g next -e '' -p /opt/kselftests/mainline/ -n 1 -i 1 -E ''
1873 09:07:20.088268 INFO: install_deps skipped
1874 09:07:20.223368 --2024-11-05 09:07:20-- http://storage.kernelci.org/next/pending-fixes/v6.12-rc6-192-g566383b19a748/arm64/defconfig/gcc-12/kselftest.tar.xz
1875 09:07:20.255593 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
1876 09:07:20.391711 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
1877 09:07:20.527474 HTTP request sent, awaiting response... 200 OK
1878 09:07:20.528114 Length: 6925836 (6.6M) [application/octet-stream]
1879 09:07:20.532860 Saving to: 'kselftest_armhf.tar.gz'
1880 09:07:20.533369
1881 09:07:21.922953
kselftest_armhf.tar 0%[ ] 0 --.-KB/s
kselftest_armhf.tar 0%[ ] 49.92K 185KB/s
kselftest_armhf.tar 3%[ ] 218.67K 404KB/s
kselftest_armhf.tar 12%[=> ] 876.79K 1.05MB/s
kselftest_armhf.tar 52%[=========> ] 3.44M 3.18MB/s
kselftest_armhf.tar 99%[==================> ] 6.55M 4.73MB/s
kselftest_armhf.tar 100%[===================>] 6.60M 4.77MB/s in 1.4s
1882 09:07:21.923812
1883 09:07:22.008115 2024-11-05 09:07:21 (4.77 MB/s) - 'kselftest_armhf.tar.gz' saved [6925836/6925836]
1884 09:07:22.008837
1885 09:07:31.484985 skiplist:
1886 09:07:31.485765 ========================================
1887 09:07:31.489544 ========================================
1888 09:07:31.532104 alsa:mixer-test
1889 09:07:31.532785 alsa:pcm-test
1890 09:07:31.533332 alsa:test-pcmtest-driver
1891 09:07:31.535911 alsa:utimer-test
1892 09:07:31.549029 ============== Tests to run ===============
1893 09:07:31.549688 alsa:mixer-test
1894 09:07:31.554770 alsa:pcm-test
1895 09:07:31.555400 alsa:test-pcmtest-driver
1896 09:07:31.555952 alsa:utimer-test
1897 09:07:31.562070 ===========End Tests to run ===============
1898 09:07:31.562699 shardfile-alsa pass
1899 09:07:31.674481 <12>[ 44.767721] kselftest: Running tests in alsa
1900 09:07:31.679711 TAP version 13
1901 09:07:31.689612 1..4
1902 09:07:31.714505 # timeout set to 45
1903 09:07:31.715188 # selftests: alsa: mixer-test
1904 09:07:31.873558 # TAP version 13
1905 09:07:31.874283 # # Card 0/LCALTA - LC-ALTA (LC-ALTA)
1906 09:07:31.878763 # 1..427
1907 09:07:31.879361 # ok 1 get_value.LCALTA.60
1908 09:07:31.879894 # # LCALTA.60 TDMOUT_A SRC SEL
1909 09:07:31.884460 # ok 2 name.LCALTA.60
1910 09:07:31.885063 # ok 3 write_default.LCALTA.60
1911 09:07:31.889851 # ok 4 write_valid.LCALTA.60
1912 09:07:31.890457 # ok 5 write_invalid.LCALTA.60
1913 09:07:31.895362 # ok 6 event_missing.LCALTA.60
1914 09:07:31.895968 # ok 7 event_spurious.LCALTA.60
1915 09:07:31.900975 # ok 8 get_value.LCALTA.59
1916 09:07:31.901589 # # LCALTA.59 TDMOUT_B SRC SEL
1917 09:07:31.906503 # ok 9 name.LCALTA.59
1918 09:07:31.907121 # ok 10 write_default.LCALTA.59
1919 09:07:31.911975 # ok 11 write_valid.LCALTA.59
1920 09:07:31.912618 # ok 12 write_invalid.LCALTA.59
1921 09:07:31.917630 # ok 13 event_missing.LCALTA.59
1922 09:07:31.918230 # ok 14 event_spurious.LCALTA.59
1923 09:07:31.923162 # ok 15 get_value.LCALTA.58
1924 09:07:31.923775 # # LCALTA.58 TDMOUT_C SRC SEL
1925 09:07:31.928701 # ok 16 name.LCALTA.58
1926 09:07:31.929303 # ok 17 write_default.LCALTA.58
1927 09:07:31.934271 # ok 18 write_valid.LCALTA.58
1928 09:07:31.934890 # ok 19 write_invalid.LCALTA.58
1929 09:07:31.939797 # ok 20 event_missing.LCALTA.58
1930 09:07:31.940448 # ok 21 event_spurious.LCALTA.58
1931 09:07:31.945566 # ok 22 get_value.LCALTA.57
1932 09:07:31.946198 # # LCALTA.57 TDMIN_A SRC SEL
1933 09:07:31.946741 # ok 23 name.LCALTA.57
1934 09:07:31.950940 # ok 24 write_default.LCALTA.57
1935 09:07:31.951552 # ok 25 write_valid.LCALTA.57
1936 09:07:31.956465 # ok 26 write_invalid.LCALTA.57
1937 09:07:31.957080 # ok 27 event_missing.LCALTA.57
1938 09:07:31.961944 # ok 28 event_spurious.LCALTA.57
1939 09:07:31.962249 # ok 29 get_value.LCALTA.56
1940 09:07:31.967353 # # LCALTA.56 TDMIN_B SRC SEL
1941 09:07:31.978495 # ok 30 na<3>[ 45.062729] fe.dai-link-5: ASoC: no backend DAIs enabled for fe.dai-link-5, possibly missing ALSA mixer-based routing or UCM profile
1942 09:07:31.978822 me.LCALTA.56
1943 09:07:31.984509 # ok 31 write_default.LCALTA.56
1944 09:07:31.985002 # ok 32 write_valid.LCALTA.56
1945 09:07:31.989714 # ok 33 write_invalid.LCALTA.56
1946 09:07:31.990114 # ok 34 event_missing.LCALTA.56
1947 09:07:31.995946 # ok 35 event_spurious.LCALTA.56
1948 09:07:31.996340 # ok 36 get_value.LCALTA.55
1949 09:07:32.000532 # # LCALTA.55 TDMIN_C SRC SEL
1950 09:07:32.000935 # ok 37 name.LCALTA.55
1951 09:07:32.006094 # ok 38 write_default.LCALTA.55
1952 09:07:32.006467 # ok 39 write_valid.LCALTA.55
1953 09:07:32.011655 # ok 40 write_invalid.LCALTA.55
1954 09:07:32.011962 # ok 41 event_missing.LCALTA.55
1955 09:07:32.017165 # ok 42 event_spurious.LCALTA.55
1956 09:07:32.017444 # ok 43 get_value.LCALTA.54
1957 09:07:32.023268 # # LCALTA.54 ACODEC Left DAC Sel
1958 09:07:32.023588 # ok 44 name.LCALTA.54
1959 09:07:32.028625 # ok 45 write_default.LCALTA.54
1960 09:07:32.028928 # ok 46 write_valid.LCALTA.54
1961 09:07:32.034770 # ok 47 write_invalid.LCALTA.54
1962 09:07:32.035111 # ok 48 event_missing.LCALTA.54
1963 09:07:32.039383 # ok 49 event_spurious.LCALTA.54
1964 09:07:32.039688 # ok 50 get_value.LCALTA.53
1965 09:07:32.045069 # # LCALTA.53 ACODEC Right DAC Sel
1966 09:07:32.045584 # ok 51 name.LCALTA.53
1967 09:07:32.050587 # ok 52 write_default.LCALTA.53
1968 09:07:32.051061 # ok 53 write_valid.LCALTA.53
1969 09:07:32.056139 # ok 54 write_invalid.LCALTA.53
1970 09:07:32.056609 # ok 55 event_missing.LCALTA.53
1971 09:07:32.061639 # ok 56 event_spurious.LCALTA.53
1972 09:07:32.062113 # ok 57 get_value.LCALTA.52
1973 09:07:32.067221 # # LCALTA.52 TOACODEC OUT EN Switch
1974 09:07:32.067700 # ok 58 name.LCALTA.52
1975 09:07:32.072734 # ok 59 write_default.LCALTA.52
1976 09:07:32.073203 # ok 60 write_valid.LCALTA.52
1977 09:07:32.078296 # ok 61 write_invalid.LCALTA.52
1978 09:07:32.078756 # ok 62 event_missing.LCALTA.52
1979 09:07:32.083803 # ok 63 event_spurious.LCALTA.52
1980 09:07:32.084317 # ok 64 get_value.LCALTA.51
1981 09:07:32.089425 # # LCALTA.51 TOACODEC SRC
1982 09:07:32.089906 # ok 65 name.LCALTA.51
1983 09:07:32.094925 # ok 66 write_default.LCALTA.51
1984 09:07:32.095390 # ok 67 write_valid.LCALTA.51
1985 09:07:32.100490 # ok 68 write_invalid.LCALTA.51
1986 09:07:32.100956 # ok 69 event_missing.LCALTA.51
1987 09:07:32.106020 # ok 70 event_spurious.LCALTA.51
1988 09:07:32.106490 # ok 71 get_value.LCALTA.50
1989 09:07:32.111550 # # LCALTA.50 TOHDMITX SPDIF SRC
1990 09:07:32.112062 # ok 72 name.LCALTA.50
1991 09:07:32.112470 # ok 73 write_default.LCALTA.50
1992 09:07:32.117101 # ok 74 write_valid.LCALTA.50
1993 09:07:32.117566 # ok 75 write_invalid.LCALTA.50
1994 09:07:32.122644 # ok 76 event_missing.LCALTA.50
1995 09:07:32.128238 # ok 77 event_spurious.LCALTA.50
1996 09:07:32.128707 # ok 78 get_value.LCALTA.49
1997 09:07:32.129103 # # LCALTA.49 TOHDMITX Switch
1998 09:07:32.133730 # ok 79 name.LCALTA.49
1999 09:07:32.134195 # ok 80 write_default.LCALTA.49
2000 09:07:32.139293 # ok 81 write_valid.LCALTA.49
2001 09:07:32.139759 # ok 82 write_invalid.LCALTA.49
2002 09:07:32.144841 # ok 83 event_missing.LCALTA.49
2003 09:07:32.145315 # ok 84 event_spurious.LCALTA.49
2004 09:07:32.150386 # ok 85 get_value.LCALTA.48
2005 09:07:32.150689 # # LCALTA.48 TOHDMITX I2S SRC
2006 09:07:32.156067 # ok 86 name.LCALTA.48
2007 09:07:32.156497 # ok 87 write_default.LCALTA.48
2008 09:07:32.161697 # ok 88 write_valid.LCALTA.48
2009 09:07:32.165508 # ok 89 write_invalid.LCALTA.48
2010 09:07:32.167296 # ok 90 event_missing.LCALTA.48
2011 09:07:32.167813 # ok 91 event_spurious.LCALTA.48
2012 09:07:32.172601 # ok 92 get_value.LCALTA.47
2013 09:07:32.173149 # # LCALTA.47 TODDR_C SRC SEL
2014 09:07:32.178963 # ok 93 name.LCALTA.47
2015 09:07:32.179606 # ok 94 write_default.LCALTA.47
2016 09:07:32.183734 # ok 95 write_valid.LCALTA.47
2017 09:07:32.184304 # ok 96 write_invalid.LCALTA.47
2018 09:07:32.189337 # ok 97 event_missing.LCALTA.47
2019 09:07:32.189865 # ok 98 event_spurious.LCALTA.47
2020 09:07:32.194757 # ok 99 get_value.LCALTA.46
2021 09:07:32.195299 # # LCALTA.46 TODDR_B SRC SEL
2022 09:07:32.195764 # ok 100 name.LCALTA.46
2023 09:07:32.200300 # ok 101 write_default.LCALTA.46
2024 09:07:32.205831 # ok 102 write_valid.LCALTA.46
2025 09:07:32.206451 # ok 103 write_invalid.LCALTA.46
2026 09:07:32.211358 # ok 104 event_missing.LCALTA.46
2027 09:07:32.211892 # ok 105 event_spurious.LCALTA.46
2028 09:07:32.216936 # ok 106 get_value.LCALTA.45
2029 09:07:32.217555 # # LCALTA.45 TODDR_A SRC SEL
2030 09:07:32.218080 # ok 107 name.LCALTA.45
2031 09:07:32.222508 # ok 108 write_default.LCALTA.45
2032 09:07:32.228051 # ok 109 write_valid.LCALTA.45
2033 09:07:32.228605 # ok 110 write_invalid.LCALTA.45
2034 09:07:32.233666 # ok 111 event_missing.LCALTA.45
2035 09:07:32.234315 # ok 112 event_spurious.LCALTA.45
2036 09:07:32.239267 # ok 113 get_value.LCALTA.44
2037 09:07:32.239799 # # LCALTA.44 FRDDR_C SINK 3 SEL
2038 09:07:32.244601 # ok 114 name.LCALTA.44
2039 09:07:32.244975 # ok 115 write_default.LCALTA.44
2040 09:07:32.250198 # ok 116 write_valid.LCALTA.44
2041 09:07:32.250624 # ok 117 write_invalid.LCALTA.44
2042 09:07:32.255812 # ok 118 event_missing.LCALTA.44
2043 09:07:32.256479 # ok 119 event_spurious.LCALTA.44
2044 09:07:32.261359 # ok 120 get_value.LCALTA.43
2045 09:07:32.261870 # # LCALTA.43 FRDDR_C SINK 2 SEL
2046 09:07:32.267053 # ok 121 name.LCALTA.43
2047 09:07:32.267818 # ok 122 write_default.LCALTA.43
2048 09:07:32.272551 # ok 123 write_valid.LCALTA.43
2049 09:07:32.273252 # ok 124 write_invalid.LCALTA.43
2050 09:07:32.278095 # ok 125 event_missing.LCALTA.43
2051 09:07:32.278772 # ok 126 event_spurious.LCALTA.43
2052 09:07:32.283635 # ok 127 get_value.LCALTA.42
2053 09:07:32.284336 # # LCALTA.42 FRDDR_C SINK 1 SEL
2054 09:07:32.289217 # ok 128 name.LCALTA.42
2055 09:07:32.289852 # ok 129 write_default.LCALTA.42
2056 09:07:32.294680 # ok 130 write_valid.LCALTA.42
2057 09:07:32.295314 # ok 131 write_invalid.LCALTA.42
2058 09:07:32.300394 # ok 132 event_missing.LCALTA.42
2059 09:07:32.301010 # ok 133 event_spurious.LCALTA.42
2060 09:07:32.305782 # ok 134 get_value.LCALTA.41
2061 09:07:32.306418 # # LCALTA.41 FRDDR_C SRC 3 EN Switch
2062 09:07:32.311361 # ok 135 name.LCALTA.41
2063 09:07:32.312034 # ok 136 write_default.LCALTA.41
2064 09:07:32.316905 # ok 137 write_valid.LCALTA.41
2065 09:07:32.317536 # ok 138 write_invalid.LCALTA.41
2066 09:07:32.322488 # ok 139 event_missing.LCALTA.41
2067 09:07:32.323119 # ok 140 event_spurious.LCALTA.41
2068 09:07:32.328012 # ok 141 get_value.LCALTA.40
2069 09:07:32.328695 # # LCALTA.40 FRDDR_C SRC 2 EN Switch
2070 09:07:32.333548 # ok 142 name.LCALTA.40
2071 09:07:32.334235 # ok 143 write_default.LCALTA.40
2072 09:07:32.339066 # ok 144 write_valid.LCALTA.40
2073 09:07:32.339728 # ok 145 write_invalid.LCALTA.40
2074 09:07:32.344659 # ok 146 event_missing.LCALTA.40
2075 09:07:32.345335 # ok 147 event_spurious.LCALTA.40
2076 09:07:32.350219 # ok 148 get_value.LCALTA.39
2077 09:07:32.356066 # # LCALTA.39 FRDDR_C SRC 1 EN Switch
2078 09:07:32.356604 # ok 149 name.LCALTA.39
2079 09:07:32.357013 # ok 150 write_default.LCALTA.39
2080 09:07:32.361302 # ok 151 write_valid.LCALTA.39
2081 09:07:32.361801 # ok 152 write_invalid.LCALTA.39
2082 09:07:32.366725 # ok 153 event_missing.LCALTA.39
2083 09:07:32.372304 # ok 154 event_spurious.LCALTA.39
2084 09:07:32.372837 # ok 155 get_value.LCALTA.38
2085 09:07:32.377844 # # LCALTA.38 FRDDR_B SINK 3 SEL
2086 09:07:32.378371 # ok 156 name.LCALTA.38
2087 09:07:32.378772 # ok 157 write_default.LCALTA.38
2088 09:07:32.383358 # ok 158 write_valid.LCALTA.38
2089 09:07:32.383864 # ok 159 write_invalid.LCALTA.38
2090 09:07:32.388935 # ok 160 event_missing.LCALTA.38
2091 09:07:32.394496 # ok 161 event_spurious.LCALTA.38
2092 09:07:32.395030 # ok 162 get_value.LCALTA.37
2093 09:07:32.400050 # # LCALTA.37 FRDDR_B SINK 2 SEL
2094 09:07:32.400560 # ok 163 name.LCALTA.37
2095 09:07:32.400961 # ok 164 write_default.LCALTA.37
2096 09:07:32.405599 # ok 165 write_valid.LCALTA.37
2097 09:07:32.411130 # ok 166 write_invalid.LCALTA.37
2098 09:07:32.411655 # ok 167 event_missing.LCALTA.37
2099 09:07:32.416675 # ok 168 event_spurious.LCALTA.37
2100 09:07:32.417200 # ok 169 get_value.LCALTA.36
2101 09:07:32.422337 # # LCALTA.36 FRDDR_B SINK 1 SEL
2102 09:07:32.422822 # ok 170 name.LCALTA.36
2103 09:07:32.427809 # ok 171 write_default.LCALTA.36
2104 09:07:32.428427 # ok 172 write_valid.LCALTA.36
2105 09:07:32.433345 # ok 173 write_invalid.LCALTA.36
2106 09:07:32.433849 # ok 174 event_missing.LCALTA.36
2107 09:07:32.438863 # ok 175 event_spurious.LCALTA.36
2108 09:07:32.439379 # ok 176 get_value.LCALTA.35
2109 09:07:32.444452 # # LCALTA.35 FRDDR_B SRC 3 EN Switch
2110 09:07:32.444975 # ok 177 name.LCALTA.35
2111 09:07:32.450006 # ok 178 write_default.LCALTA.35
2112 09:07:32.450554 # ok 179 write_valid.LCALTA.35
2113 09:07:32.455573 # ok 180 write_invalid.LCALTA.35
2114 09:07:32.456339 # ok 181 event_missing.LCALTA.35
2115 09:07:32.461095 # ok 182 event_spurious.LCALTA.35
2116 09:07:32.461740 # ok 183 get_value.LCALTA.34
2117 09:07:32.466647 # # LCALTA.34 FRDDR_B SRC 2 EN Switch
2118 09:07:32.467316 # ok 184 name.LCALTA.34
2119 09:07:32.472420 # ok 185 write_default.LCALTA.34
2120 09:07:32.473178 # ok 186 write_valid.LCALTA.34
2121 09:07:32.477770 # ok 187 write_invalid.LCALTA.34
2122 09:07:32.478435 # ok 188 event_missing.LCALTA.34
2123 09:07:32.483318 # ok 189 event_spurious.LCALTA.34
2124 09:07:32.483812 # ok 190 get_value.LCALTA.33
2125 09:07:32.488813 # # LCALTA.33 FRDDR_B SRC 1 EN Switch
2126 09:07:32.489346 # ok 191 name.LCALTA.33
2127 09:07:32.494328 # ok 192 write_default.LCALTA.33
2128 09:07:32.494824 # ok 193 write_valid.LCALTA.33
2129 09:07:32.499850 # ok 194 write_invalid.LCALTA.33
2130 09:07:32.500368 # ok 195 event_missing.LCALTA.33
2131 09:07:32.505404 # ok 196 event_spurious.LCALTA.33
2132 09:07:32.505890 # ok 197 get_value.LCALTA.32
2133 09:07:32.510923 # # LCALTA.32 FRDDR_A SINK 3 SEL
2134 09:07:32.511409 # ok 198 name.LCALTA.32
2135 09:07:32.516517 # ok 199 write_default.LCALTA.32
2136 09:07:32.517001 # ok 200 write_valid.LCALTA.32
2137 09:07:32.522056 # ok 201 write_invalid.LCALTA.32
2138 09:07:32.522542 # ok 202 event_missing.LCALTA.32
2139 09:07:32.527578 # ok 203 event_spurious.LCALTA.32
2140 09:07:32.528101 # ok 204 get_value.LCALTA.31
2141 09:07:32.533193 # # LCALTA.31 FRDDR_A SINK 2 SEL
2142 09:07:32.533678 # ok 205 name.LCALTA.31
2143 09:07:32.538653 # ok 206 write_default.LCALTA.31
2144 09:07:32.539130 # ok 207 write_valid.LCALTA.31
2145 09:07:32.544308 # ok 208 write_invalid.LCALTA.31
2146 09:07:32.544797 # ok 209 event_missing.LCALTA.31
2147 09:07:32.549785 # ok 210 event_spurious.LCALTA.31
2148 09:07:32.550277 # ok 211 get_value.LCALTA.30
2149 09:07:32.555337 # # LCALTA.30 FRDDR_A SINK 1 SEL
2150 09:07:32.555818 # ok 212 name.LCALTA.30
2151 09:07:32.560849 # ok 213 write_default.LCALTA.30
2152 09:07:32.561335 # ok 214 write_valid.LCALTA.30
2153 09:07:32.566406 # ok 215 write_invalid.LCALTA.30
2154 09:07:32.571971 # ok 216 event_missing.LCALTA.30
2155 09:07:32.572479 # ok 217 event_spurious.LCALTA.30
2156 09:07:32.577486 # ok 218 get_value.LCALTA.29
2157 09:07:32.577965 # # LCALTA.29 FRDDR_A SRC 3 EN Switch
2158 09:07:32.583033 # ok 219 name.LCALTA.29
2159 09:07:32.583511 # ok 220 write_default.LCALTA.29
2160 09:07:32.588604 # ok 221 write_valid.LCALTA.29
2161 09:07:32.589081 # ok 222 write_invalid.LCALTA.29
2162 09:07:32.594205 # ok 223 event_missing.LCALTA.29
2163 09:07:32.594676 # ok 224 event_spurious.LCALTA.29
2164 09:07:32.599671 # ok 225 get_value.LCALTA.28
2165 09:07:32.600171 # # LCALTA.28 FRDDR_A SRC 2 EN Switch
2166 09:07:32.605320 # ok 226 name.LCALTA.28
2167 09:07:32.605806 # ok 227 write_default.LCALTA.28
2168 09:07:32.610789 # ok 228 write_valid.LCALTA.28
2169 09:07:32.611273 # ok 229 write_invalid.LCALTA.28
2170 09:07:32.616317 # ok 230 event_missing.LCALTA.28
2171 09:07:32.616801 # ok 231 event_spurious.LCALTA.28
2172 09:07:32.621897 # ok 232 get_value.LCALTA.27
2173 09:07:32.622373 # # LCALTA.27 FRDDR_A SRC 1 EN Switch
2174 09:07:32.627414 # ok 233 name.LCALTA.27
2175 09:07:32.627902 # ok 234 write_default.LCALTA.27
2176 09:07:32.632987 # ok 235 write_valid.LCALTA.27
2177 09:07:32.633458 # ok 236 write_invalid.LCALTA.27
2178 09:07:32.638530 # ok 237 event_missing.LCALTA.27
2179 09:07:32.638998 # ok 238 event_spurious.LCALTA.27
2180 09:07:32.644096 # ok 239 get_value.LCALTA.26
2181 09:07:32.644574 # # LCALTA.26 ELD
2182 09:07:32.649622 # ok 240 name.LCALTA.26
2183 09:07:32.650094 # # ELD is not writeable
2184 09:07:32.655184 # ok 241 # SKIP write_default.LCALTA.26
2185 09:07:32.655658 # # ELD is not writeable
2186 09:07:32.660760 # ok 242 # SKIP write_valid.LCALTA.26
2187 09:07:32.661392 # # ELD is not writeable
2188 09:07:32.666357 # ok 243 # SKIP write_invalid.LCALTA.26
2189 09:07:32.666838 # ok 244 event_missing.LCALTA.26
2190 09:07:32.671821 # ok 245 event_spurious.LCALTA.26
2191 09:07:32.672325 # ok 246 get_value.LCALTA.25
2192 09:07:32.677425 # # LCALTA.25 IEC958 Playback Default
2193 09:07:32.677897 # ok 247 name.LCALTA.25
2194 09:07:32.682866 # ok 248 write_default.LCALTA.25
2195 09:07:32.683337 # ok 249 # SKIP write_valid.LCALTA.25
2196 09:07:32.688421 # ok 250 # SKIP write_invalid.LCALTA.25
2197 09:07:32.693966 # ok 251 event_missing.LCALTA.25
2198 09:07:32.694439 # ok 252 event_spurious.LCALTA.25
2199 09:07:32.699544 # ok 253 get_value.LCALTA.24
2200 09:07:32.700041 # # LCALTA.24 IEC958 Playback Mask
2201 09:07:32.700456 # ok 254 name.LCALTA.24
2202 09:07:32.705136 # # IEC958 Playback Mask is not writeable
2203 09:07:32.710658 # ok 255 # SKIP write_default.LCALTA.24
2204 09:07:32.711158 # # IEC958 Playback Mask is not writeable
2205 09:07:32.716259 # ok 256 # SKIP write_valid.LCALTA.24
2206 09:07:32.721718 # # IEC958 Playback Mask is not writeable
2207 09:07:32.722210 # ok 257 # SKIP write_invalid.LCALTA.24
2208 09:07:32.727336 # ok 258 event_missing.LCALTA.24
2209 09:07:32.727822 # ok 259 event_spurious.LCALTA.24
2210 09:07:32.732797 # ok 260 get_value.LCALTA.23
2211 09:07:32.733286 # # LCALTA.23 Playback Channel Map
2212 09:07:32.738385 # ok 261 name.LCALTA.23
2213 09:07:32.743954 # # Playback Channel Map is not writeable
2214 09:07:32.744495 # ok 262 # SKIP write_default.LCALTA.23
2215 09:07:32.749479 # # Playback Channel Map is not writeable
2216 09:07:32.749969 # ok 263 # SKIP write_valid.LCALTA.23
2217 09:07:32.755005 # # Playback Channel Map is not writeable
2218 09:07:32.760535 # ok 264 # SKIP write_invalid.LCALTA.23
2219 09:07:32.761005 # ok 265 event_missing.LCALTA.23
2220 09:07:32.766108 # ok 266 event_spurious.LCALTA.23
2221 09:07:32.766576 # ok 267 get_value.LCALTA.22
2222 09:07:32.771634 # # LCALTA.22 TDMOUT_A Gain Enable Switch
2223 09:07:32.772132 # ok 268 name.LCALTA.22
2224 09:07:32.777241 # ok 269 write_default.LCALTA.22
2225 09:07:32.777713 # ok 270 write_valid.LCALTA.22
2226 09:07:32.782726 # ok 271 write_invalid.LCALTA.22
2227 09:07:32.783210 # ok 272 event_missing.LCALTA.22
2228 09:07:32.788354 # ok 273 event_spurious.LCALTA.22
2229 09:07:32.793825 # ok 274 get_value.LCALTA.21
2230 09:07:32.794307 # # LCALTA.21 TDMOUT_A Lane 3 Volume
2231 09:07:32.794722 # ok 275 name.LCALTA.21
2232 09:07:32.799411 # ok 276 write_default.LCALTA.21
2233 09:07:32.804911 # ok 277 write_valid.LCALTA.21
2234 09:07:32.805388 # ok 278 write_invalid.LCALTA.21
2235 09:07:32.810489 # ok 279 event_missing.LCALTA.21
2236 09:07:32.810965 # ok 280 event_spurious.LCALTA.21
2237 09:07:32.816036 # ok 281 get_value.LCALTA.20
2238 09:07:32.816511 # # LCALTA.20 TDMOUT_A Lane 2 Volume
2239 09:07:32.821555 # ok 282 name.LCALTA.20
2240 09:07:32.822029 # ok 283 write_default.LCALTA.20
2241 09:07:32.827089 # ok 284 write_valid.LCALTA.20
2242 09:07:32.827558 # ok 285 write_invalid.LCALTA.20
2243 09:07:32.832653 # ok 286 event_missing.LCALTA.20
2244 09:07:32.833131 # ok 287 event_spurious.LCALTA.20
2245 09:07:32.838224 # ok 288 get_value.LCALTA.19
2246 09:07:32.838699 # # LCALTA.19 TDMOUT_A Lane 1 Volume
2247 09:07:32.843719 # ok 289 name.LCALTA.19
2248 09:07:32.844234 # ok 290 write_default.LCALTA.19
2249 09:07:32.849428 # ok 291 write_valid.LCALTA.19
2250 09:07:32.849900 # ok 292 write_invalid.LCALTA.19
2251 09:07:32.854884 # ok 293 event_missing.LCALTA.19
2252 09:07:32.855361 # ok 294 event_spurious.LCALTA.19
2253 09:07:32.860421 # ok 295 get_value.LCALTA.18
2254 09:07:32.860891 # # LCALTA.18 TDMOUT_A Lane 0 Volume
2255 09:07:32.865917 # ok 296 name.LCALTA.18
2256 09:07:32.866375 # ok 297 write_default.LCALTA.18
2257 09:07:32.871509 # ok 298 write_valid.LCALTA.18
2258 09:07:32.872009 # ok 299 write_invalid.LCALTA.18
2259 09:07:32.877004 # ok 300 event_missing.LCALTA.18
2260 09:07:32.877488 # ok 301 event_spurious.LCALTA.18
2261 09:07:32.882570 # ok 302 get_value.LCALTA.17
2262 09:07:32.888132 # # LCALTA.17 TDMOUT_B Gain Enable Switch
2263 09:07:32.888629 # ok 303 name.LCALTA.17
2264 09:07:32.889042 # ok 304 write_default.LCALTA.17
2265 09:07:32.893694 # ok 305 write_valid.LCALTA.17
2266 09:07:32.899260 # ok 306 write_invalid.LCALTA.17
2267 09:07:32.899760 # ok 307 event_missing.LCALTA.17
2268 09:07:32.904769 # ok 308 event_spurious.LCALTA.17
2269 09:07:32.905262 # ok 309 get_value.LCALTA.16
2270 09:07:32.910369 # # LCALTA.16 TDMOUT_B Lane 3 Volume
2271 09:07:32.910853 # ok 310 name.LCALTA.16
2272 09:07:32.915878 # ok 311 write_default.LCALTA.16
2273 09:07:32.916391 # ok 312 write_valid.LCALTA.16
2274 09:07:32.921434 # ok 313 write_invalid.LCALTA.16
2275 09:07:32.921922 # ok 314 event_missing.LCALTA.16
2276 09:07:32.927020 # ok 315 event_spurious.LCALTA.16
2277 09:07:32.927509 # ok 316 get_value.LCALTA.15
2278 09:07:32.932508 # # LCALTA.15 TDMOUT_B Lane 2 Volume
2279 09:07:32.932985 # ok 317 name.LCALTA.15
2280 09:07:32.938062 # ok 318 write_default.LCALTA.15
2281 09:07:32.938547 # ok 319 write_valid.LCALTA.15
2282 09:07:32.943572 # ok 320 write_invalid.LCALTA.15
2283 09:07:32.944101 # ok 321 event_missing.LCALTA.15
2284 09:07:32.949146 # ok 322 event_spurious.LCALTA.15
2285 09:07:32.949635 # ok 323 get_value.LCALTA.14
2286 09:07:32.954702 # # LCALTA.14 TDMOUT_B Lane 1 Volume
2287 09:07:32.955197 # ok 324 name.LCALTA.14
2288 09:07:32.960292 # ok 325 write_default.LCALTA.14
2289 09:07:32.960785 # ok 326 write_valid.LCALTA.14
2290 09:07:32.965808 # ok 327 write_invalid.LCALTA.14
2291 09:07:32.966306 # ok 328 event_missing.LCALTA.14
2292 09:07:32.971391 # ok 329 event_spurious.LCALTA.14
2293 09:07:32.971886 # ok 330 get_value.LCALTA.13
2294 09:07:32.976863 # # LCALTA.13 TDMOUT_B Lane 0 Volume
2295 09:07:32.977352 # ok 331 name.LCALTA.13
2296 09:07:32.982447 # ok 332 write_default.LCALTA.13
2297 09:07:32.982946 # ok 333 write_valid.LCALTA.13
2298 09:07:32.987966 # ok 334 write_invalid.LCALTA.13
2299 09:07:32.988473 # ok 335 event_missing.LCALTA.13
2300 09:07:32.993530 # ok 336 event_spurious.LCALTA.13
2301 09:07:32.994004 # ok 337 get_value.LCALTA.12
2302 09:07:32.999050 # # LCALTA.12 TDMOUT_C Gain Enable Switch
2303 09:07:32.999531 # ok 338 name.LCALTA.12
2304 09:07:33.004589 # ok 339 write_default.LCALTA.12
2305 09:07:33.010151 # ok 340 write_valid.LCALTA.12
2306 09:07:33.010626 # ok 341 write_invalid.LCALTA.12
2307 09:07:33.015704 # ok 342 event_missing.LCALTA.12
2308 09:07:33.016217 # ok 343 event_spurious.LCALTA.12
2309 09:07:33.021272 # ok 344 get_value.LCALTA.11
2310 09:07:33.021756 # # LCALTA.11 TDMOUT_C Lane 3 Volume
2311 09:07:33.026785 # ok 345 name.LCALTA.11
2312 09:07:33.027269 # ok 346 write_default.LCALTA.11
2313 09:07:33.032438 # ok 347 write_valid.LCALTA.11
2314 09:07:33.032954 # ok 348 write_invalid.LCALTA.11
2315 09:07:33.037952 # ok 349 event_missing.LCALTA.11
2316 09:07:33.038472 # ok 350 event_spurious.LCALTA.11
2317 09:07:33.043495 # ok 351 get_value.LCALTA.10
2318 09:07:33.044054 # # LCALTA.10 TDMOUT_C Lane 2 Volume
2319 09:07:33.049030 # ok 352 name.LCALTA.10
2320 09:07:33.049531 # ok 353 write_default.LCALTA.10
2321 09:07:33.054553 # ok 354 write_valid.LCALTA.10
2322 09:07:33.055057 # ok 355 write_invalid.LCALTA.10
2323 09:07:33.060116 # ok 356 event_missing.LCALTA.10
2324 09:07:33.060640 # ok 357 event_spurious.LCALTA.10
2325 09:07:33.065680 # ok 358 get_value.LCALTA.9
2326 09:07:33.066201 # # LCALTA.9 TDMOUT_C Lane 1 Volume
2327 09:07:33.071207 # ok 359 name.LCALTA.9
2328 09:07:33.071732 # ok 360 write_default.LCALTA.9
2329 09:07:33.076780 # ok 361 write_valid.LCALTA.9
2330 09:07:33.077292 # ok 362 write_invalid.LCALTA.9
2331 09:07:33.082373 # ok 363 event_missing.LCALTA.9
2332 09:07:33.082923 # ok 364 event_spurious.LCALTA.9
2333 09:07:33.087852 # ok 365 get_value.LCALTA.8
2334 09:07:33.088383 # # LCALTA.8 TDMOUT_C Lane 0 Volume
2335 09:07:33.093444 # ok 366 name.LCALTA.8
2336 09:07:33.093916 # ok 367 write_default.LCALTA.8
2337 09:07:33.098911 # ok 368 write_valid.LCALTA.8
2338 09:07:33.099391 # ok 369 write_invalid.LCALTA.8
2339 09:07:33.104439 # ok 370 event_missing.LCALTA.8
2340 09:07:33.104912 # ok 371 event_spurious.LCALTA.8
2341 09:07:33.109995 # ok 372 get_value.LCALTA.7
2342 09:07:33.110466 # # LCALTA.7 ACODEC Unmute Ramp Switch
2343 09:07:33.115521 # ok 373 name.LCALTA.7
2344 09:07:33.116015 # ok 374 write_default.LCALTA.7
2345 09:07:33.121079 # ok 375 write_valid.LCALTA.7
2346 09:07:33.121550 # ok 376 write_invalid.LCALTA.7
2347 09:07:33.126628 # ok 377 event_missing.LCALTA.7
2348 09:07:33.127094 # ok 378 event_spurious.LCALTA.7
2349 09:07:33.132260 # ok 379 get_value.LCALTA.6
2350 09:07:33.132902 # # LCALTA.6 ACODEC Mute Ramp Switch
2351 09:07:33.137721 # ok 380 name.LCALTA.6
2352 09:07:33.138196 # ok 381 write_default.LCALTA.6
2353 09:07:33.143316 # ok 382 write_valid.LCALTA.6
2354 09:07:33.143949 # ok 383 write_invalid.LCALTA.6
2355 09:07:33.148816 # ok 384 event_missing.LCALTA.6
2356 09:07:33.149317 # ok 385 event_spurious.LCALTA.6
2357 09:07:33.154435 # ok 386 get_value.LCALTA.5
2358 09:07:33.154924 # # LCALTA.5 ACODEC Volume Ramp Switch
2359 09:07:33.159923 # ok 387 name.LCALTA.5
2360 09:07:33.160417 # ok 388 write_default.LCALTA.5
2361 09:07:33.165460 # ok 389 write_valid.LCALTA.5
2362 09:07:33.165925 # ok 390 write_invalid.LCALTA.5
2363 09:07:33.171022 # ok 391 event_missing.LCALTA.5
2364 09:07:33.171492 # ok 392 event_spurious.LCALTA.5
2365 09:07:33.176544 # ok 393 get_value.LCALTA.4
2366 09:07:33.177019 # # LCALTA.4 ACODEC Ramp Rate
2367 09:07:33.182092 # ok 394 name.LCALTA.4
2368 09:07:33.182556 # ok 395 write_default.LCALTA.4
2369 09:07:33.187603 # ok 396 write_valid.LCALTA.4
2370 09:07:33.188093 # ok 397 write_invalid.LCALTA.4
2371 09:07:33.193172 # ok 398 event_missing.LCALTA.4
2372 09:07:33.193641 # ok 399 event_spurious.LCALTA.4
2373 09:07:33.198739 # ok 400 get_value.LCALTA.3
2374 09:07:33.199203 # # LCALTA.3 ACODEC Playback Volume
2375 09:07:33.204294 # ok 401 name.LCALTA.3
2376 09:07:33.204759 # ok 402 write_default.LCALTA.3
2377 09:07:33.209796 # ok 403 write_valid.LCALTA.3
2378 09:07:33.210264 # ok 404 write_invalid.LCALTA.3
2379 09:07:33.215405 # ok 405 event_missing.LCALTA.3
2380 09:07:33.215884 # ok 406 event_spurious.LCALTA.3
2381 09:07:33.220947 # ok 407 get_value.LCALTA.2
2382 09:07:33.221429 # # LCALTA.2 ACODEC Playback Switch
2383 09:07:33.226539 # ok 408 name.LCALTA.2
2384 09:07:33.227013 # ok 409 write_default.LCALTA.2
2385 09:07:33.232072 # ok 410 write_valid.LCALTA.2
2386 09:07:33.232546 # ok 411 write_invalid.LCALTA.2
2387 09:07:33.237579 # ok 412 event_missing.LCALTA.2
2388 09:07:33.238052 # ok 413 event_spurious.LCALTA.2
2389 09:07:33.243125 # ok 414 get_value.LCALTA.1
2390 09:07:33.243600 # # LCALTA.1 ACODEC Playback Channel Mode
2391 09:07:33.248671 # ok 415 name.LCALTA.1
2392 09:07:33.249153 # ok 416 write_default.LCALTA.1
2393 09:07:33.254198 # ok 417 write_valid.LCALTA.1
2394 09:07:33.254668 # ok 418 write_invalid.LCALTA.1
2395 09:07:33.259738 # ok 419 event_missing.LCALTA.1
2396 09:07:33.260236 # ok 420 event_spurious.LCALTA.1
2397 09:07:33.265273 # ok 421 get_value.LCALTA.0
2398 09:07:33.265736 # # LCALTA.0 TOACODEC Lane Select
2399 09:07:33.270817 # ok 422 name.LCALTA.0
2400 09:07:33.271282 # ok 423 write_default.LCALTA.0
2401 09:07:33.276413 # ok 424 write_valid.LCALTA.0
2402 09:07:33.276880 # ok 425 write_invalid.LCALTA.0
2403 09:07:33.281937 # ok 426 event_missing.LCALTA.0
2404 09:07:33.282402 # ok 427 event_spurious.LCALTA.0
2405 09:07:33.287457 # # Totals: pass:416 fail:0 xfail:0 xpass:0 skip:11 error:0
2406 09:07:33.292981 ok 1 selftests: alsa: mixer-test
2407 09:07:33.293459 # timeout set to 45
2408 09:07:33.293869 # selftests: alsa: pcm-test
2409 09:07:33.298569 # TAP version 13
2410 09:07:33.299216 # # Card 0/LCALTA - LC-ALTA (LC-ALTA)
2411 09:07:33.304209 # # LCALTA.0 - fe.dai-link-0 (*)
2412 09:07:33.304830 # # LCALTA.0 - fe.dai-link-1 (*)
2413 09:07:33.309699 # # LCALTA.0 - fe.dai-link-2 (*)
2414 09:07:33.310172 # # LCALTA.0 - fe.dai-link-3 (*)
2415 09:07:33.315213 # # LCALTA.0 - fe.dai-link-4 (*)
2416 09:07:33.315684 # # LCALTA.0 - fe.dai-link-5 (*)
2417 09:07:33.320778 # 1..42
2418 09:07:33.326325 # # default.time1.LCALTA.5.0.CAPTURE - 8kHz mono large periods
2419 09:07:33.326803 # ok 1 # SKIP default.time1.LCALTA.5.0.CAPTURE
2420 09:07:33.331876 # # snd_pcm_hw_params: Invalid argument
2421 09:07:33.337425 # # default.time2.LCALTA.5.0.CAPTURE - 8kHz stereo large periods
2422 09:07:33.342937 # ok 2 # SKIP default.time2.LCALTA.5.0.CAPTURE
2423 09:07:33.343407 # # snd_pcm_hw_params: Invalid argument
2424 09:07:33.348496 # # default.time3.LCALTA.5.0.CAPTURE - 44.1kHz stereo large periods
2425 09:07:33.354010 # ok 3 # SKIP default.time3.LCALTA.5.0.CAPTURE
2426 09:07:33.359566 # # snd_pcm_hw_params: Invalid argument
2427 09:07:33.365104 # # default.time4.LCALTA.5.0.CAPTURE - 48kHz stereo small periods
2428 09:07:33.370626 # ok 4 # SKIP default.time4.LCALTA.5.0.CAPTURE
2429 09:07:33.371092 # # snd_pcm_hw_params: Invalid argument
2430 09:07:33.376232 # # default.time5.LCALTA.5.0.CAPTURE - 48kHz stereo large periods
2431 09:07:33.381730 # ok 5 # SKIP default.time5.LCALTA.5.0.CAPTURE
2432 09:07:33.387419 # # snd_pcm_hw_params: Invalid argument
2433 09:07:33.392916 # # default.time6.LCALTA.5.0.CAPTURE - 48kHz 6 channel large periods
2434 09:07:33.398439 # ok 6 # SKIP default.time6.LCALTA.5.0.CAPTURE
2435 09:07:33.398910 # # snd_pcm_hw_params: Invalid argument
2436 09:07:33.403959 # # default.time7.LCALTA.5.0.CAPTURE - 96kHz stereo large periods
2437 09:07:33.409476 # ok 7 # SKIP default.time7.LCALTA.5.0.CAPTURE
2438 09:07:33.415059 # # snd_pcm_hw_params: Invalid argument
2439 09:07:33.420575 # # default.time1.LCALTA.4.0.CAPTURE - 8kHz mono large periods
2440 09:07:33.421046 # ok 8 # SKIP default.time1.LCALTA.4.0.CAPTURE
2441 09:07:33.426141 # # snd_pcm_hw_params: Invalid argument
2442 09:07:33.431697 # # default.time2.LCALTA.4.0.CAPTURE - 8kHz stereo large periods
2443 09:07:33.437285 # ok 9 # SKIP default.time2.LCALTA.4.0.CAPTURE
2444 09:07:33.437770 # # snd_pcm_hw_params: Invalid argument
2445 09:07:33.448389 # # default.time3.LCALTA.4.0.CAPTURE - 44.1kHz stereo large periods
2446 09:07:33.448887 # ok 10 # SKIP default.time3.LCALTA.4.0.CAPTURE
2447 09:07:33.453889 # # snd_pcm_hw_params: Invalid argument
2448 09:07:33.459455 # # default.time4.LCALTA.4.0.CAPTURE - 48kHz stereo small periods
2449 09:07:33.464968 # ok 11 # SKIP default.time4.LCALTA.4.0.CAPTURE
2450 09:07:33.465448 # # snd_pcm_hw_params: Invalid argument
2451 09:07:33.470575 # # default.time5.LCALTA.4.0.CAPTURE - 48kHz stereo large periods
2452 09:07:33.476144 # ok 12 # SKIP default.time5.LCALTA.4.0.CAPTURE
2453 09:07:33.481671 # # snd_pcm_hw_params: Invalid argument
2454 09:07:33.487198 # # default.time6.LCALTA.4.0.CAPTURE - 48kHz 6 channel large periods
2455 09:07:33.492736 # ok 13 # SKIP default.time6.LCALTA.4.0.CAPTURE
2456 09:07:33.493265 # # snd_pcm_hw_params: Invalid argument
2457 09:07:33.498343 # # default.time7.LCALTA.4.0.CAPTURE - 96kHz stereo large periods
2458 09:07:33.503794 # ok 14 # SKIP default.time7.LCALTA.4.0.CAPTURE
2459 09:07:33.509409 # # snd_pcm_hw_params: Invalid argument
2460 09:07:33.514880 # # default.time1.LCALTA.3.0.CAPTURE - 8kHz mono large periods
2461 09:07:33.520442 # ok 15 # SKIP default.time1.LCALTA.3.0.CAPTURE
2462 09:07:33.520912 # # snd_pcm_hw_params: Invalid argument
2463 09:07:33.525932 # # default.time2.LCALTA.3.0.CAPTURE - 8kHz stereo large periods
2464 09:07:33.531537 # ok 16 # SKIP default.time2.LCALTA.3.0.CAPTURE
2465 09:07:33.537074 # # snd_pcm_hw_params: Invalid argument
2466 09:07:33.542631 # # default.time3.LCALTA.3.0.CAPTURE - 44.1kHz stereo large periods
2467 09:07:33.543098 # ok 17 # SKIP default.time3.LCALTA.3.0.CAPTURE
2468 09:07:33.548210 # # snd_pcm_hw_params: Invalid argument
2469 09:07:33.553727 # # default.time4.LCALTA.3.0.CAPTURE - 48kHz stereo small periods
2470 09:07:33.559351 # ok 18 # SKIP default.time4.LCALTA.3.0.CAPTURE
2471 09:07:33.564788 # # snd_pcm_hw_params: Invalid argument
2472 09:07:33.570455 # # default.time5.LCALTA.3.0.CAPTURE - 48kHz stereo large periods
2473 09:07:33.570923 # ok 19 # SKIP default.time5.LCALTA.3.0.CAPTURE
2474 09:07:33.575903 # # snd_pcm_hw_params: Invalid argument
2475 09:07:33.581436 # # default.time6.LCALTA.3.0.CAPTURE - 48kHz 6 channel large periods
2476 09:07:33.586991 # ok 20 # SKIP default.time6.LCALTA.3.0.CAPTURE
2477 09:07:33.592531 # # snd_pcm_hw_params: Invalid argument
2478 09:07:33.598057 # # default.time7.LCALTA.3.0.CAPTURE - 96kHz stereo large periods
2479 09:07:33.598537 # ok 21 # SKIP default.time7.LCALTA.3.0.CAPTURE
2480 09:07:33.603629 # # snd_pcm_hw_params: Invalid argument
2481 09:07:33.609184 # # default.time1.LCALTA.2.0.PLAYBACK - 8kHz mono large periods
2482 09:07:33.614693 # ok 22 # SKIP default.time1.LCALTA.2.0.PLAYBACK
2483 09:07:33.615158 # # snd_pcm_hw_params: Invalid argument
2484 09:07:33.620339 # # default.time2.LCALTA.2.0.PLAYBACK - 8kHz stereo large periods
2485 09:07:33.625805 # ok 23 # SKIP default.time2.LCALTA.2.0.PLAYBACK
2486 09:07:33.631443 # # snd_pcm_hw_params: Invalid argument
2487 09:07:33.636873 # # default.time3.LCALTA.2.0.PLAYBACK - 44.1kHz stereo large periods
2488 09:07:33.642433 # ok 24 # SKIP default.time3.LCALTA.2.0.PLAYBACK
2489 09:07:33.642894 # # snd_pcm_hw_params: Invalid argument
2490 09:07:33.648010 # # default.time4.LCALTA.2.0.PLAYBACK - 48kHz stereo small periods
2491 09:07:33.653540 # ok 25 # SKIP default.time4.LCALTA.2.0.PLAYBACK
2492 09:07:33.659089 # # snd_pcm_hw_params: Invalid argument
2493 09:07:33.664582 # # default.time5.LCALTA.2.0.PLAYBACK - 48kHz stereo large periods
2494 09:07:33.670147 # ok 26 # SKIP default.time5.LCALTA.2.0.PLAYBACK
2495 09:07:33.670618 # # snd_pcm_hw_params: Invalid argument
2496 09:07:33.675767 # # default.time6.LCALTA.2.0.PLAYBACK - 48kHz 6 channel large periods
2497 09:07:33.681342 # ok 27 # SKIP default.time6.LCALTA.2.0.PLAYBACK
2498 09:07:33.686867 # # snd_pcm_hw_params: Invalid argument
2499 09:07:33.692447 # # default.time7.LCALTA.2.0.PLAYBACK - 96kHz stereo large periods
2500 09:07:33.697890 # ok 28 # SKIP default.time7.LCALTA.2.0.PLAYBACK
2501 09:07:33.698356 # # snd_pcm_hw_params: Invalid argument
2502 09:07:33.703485 # # default.time1.LCALTA.1.0.PLAYBACK - 8kHz mono large periods
2503 09:07:33.709008 # ok 29 # SKIP default.time1.LCALTA.1.0.PLAYBACK
2504 09:07:33.714556 # # snd_pcm_hw_params: Invalid argument
2505 09:07:33.720115 # # default.time2.LCALTA.1.0.PLAYBACK - 8kHz stereo large periods
2506 09:07:33.725628 # ok 30 # SKIP default.time2.LCALTA.1.0.PLAYBACK
2507 09:07:33.726090 # # snd_pcm_hw_params: Invalid argument
2508 09:07:33.731158 # # default.time3.LCALTA.1.0.PLAYBACK - 44.1kHz stereo large periods
2509 09:07:33.736679 # ok 31 # SKIP default.time3.LCALTA.1.0.PLAYBACK
2510 09:07:33.742293 # # snd_pcm_hw_params: Invalid argument
2511 09:07:33.747852 # # default.time4.LCALTA.1.0.PLAYBACK - 48kHz stereo small periods
2512 09:07:33.753499 # ok 32 # SKIP default.time4.LCALTA.1.0.PLAYBACK
2513 09:07:33.753966 # # snd_pcm_hw_params: Invalid argument
2514 09:07:33.758924 # # default.time5.LCALTA.1.0.PLAYBACK - 48kHz stereo large periods
2515 09:07:33.764469 # ok 33 # SKIP default.time5.LCALTA.1.0.PLAYBACK
2516 09:07:33.770011 # # snd_pcm_hw_params: Invalid argument
2517 09:07:33.775574 # # default.time6.LCALTA.1.0.PLAYBACK - 48kHz 6 channel large periods
2518 09:07:33.781124 # ok 34 # SKIP default.time6.LCALTA.1.0.PLAYBACK
2519 09:07:33.781595 # # snd_pcm_hw_params: Invalid argument
2520 09:07:33.786716 # # default.time7.LCALTA.1.0.PLAYBACK - 96kHz stereo large periods
2521 09:07:33.792269 # ok 35 # SKIP default.time7.LCALTA.1.0.PLAYBACK
2522 09:07:33.797753 # # snd_pcm_hw_params: Invalid argument
2523 09:07:33.803316 # # default.time1.LCALTA.0.0.PLAYBACK - 8kHz mono large periods
2524 09:07:33.808803 # ok 36 # SKIP default.time1.LCALTA.0.0.PLAYBACK
2525 09:07:33.809274 # # snd_pcm_hw_params: Invalid argument
2526 09:07:33.814416 # # default.time2.LCALTA.0.0.PLAYBACK - 8kHz stereo large periods
2527 09:07:33.819965 # ok 37 # SKIP default.time2.LCALTA.0.0.PLAYBACK
2528 09:07:33.825518 # # snd_pcm_hw_params: Invalid argument
2529 09:07:33.831025 # # default.time3.LCALTA.0.0.PLAYBACK - 44.1kHz stereo large periods
2530 09:07:33.836686 # ok 38 # SKIP default.time3.LCALTA.0.0.PLAYBACK
2531 09:07:33.837156 # # snd_pcm_hw_params: Invalid argument
2532 09:07:33.842259 # # default.time4.LCALTA.0.0.PLAYBACK - 48kHz stereo small periods
2533 09:07:33.848251 # ok 39 # SKIP default.time4.LCALTA.0.0.PLAYBACK
2534 09:07:33.853302 # # snd_pcm_hw_params: Invalid argument
2535 09:07:33.858748 # # default.time5.LCALTA.0.0.PLAYBACK - 48kHz stereo large periods
2536 09:07:33.864373 # ok 40 # SKIP default.time5.LCALTA.0.0.PLAYBACK
2537 09:07:33.864840 # # snd_pcm_hw_params: Invalid argument
2538 09:07:33.869860 # # default.time6.LCALTA.0.0.PLAYBACK - 48kHz 6 channel large periods
2539 09:07:33.875508 # ok 41 # SKIP default.time6.LCALTA.0.0.PLAYBACK
2540 09:07:33.880953 # # snd_pcm_hw_params: Invalid argument
2541 09:07:33.886514 # # default.time7.LCALTA.0.0.PLAYBACK - 96kHz stereo large periods
2542 09:07:33.892069 # ok 42 # SKIP default.time7.LCALTA.0.0.PLAYBACK
2543 09:07:33.892538 # # snd_pcm_hw_params: Invalid argument
2544 09:07:33.897713 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:42 error:0
2545 09:07:33.903163 ok 2 selftests: alsa: pcm-test
2546 09:07:33.903641 # timeout set to 45
2547 09:07:33.908733 # selftests: alsa: test-pcmtest-driver
2548 09:07:33.909200 # TAP version 13
2549 09:07:33.909612 # 1..5
2550 09:07:33.914306 # # Starting 5 tests from 1 test cases.
2551 09:07:33.914774 # # RUN pcmtest.playback ...
2552 09:07:33.919836 # # SKIP Can't read patterns. Probably, module isn't loaded
2553 09:07:33.925391 # # OK pcmtest.playback
2554 09:07:33.930908 # ok 1 pcmtest.playback # SKIP Can't read patterns. Probably, module isn't loaded
2555 09:07:33.936559 # # RUN pcmtest.capture ...
2556 09:07:33.942097 # # SKIP Can't read patterns. Probably, module isn't loaded
2557 09:07:33.947703 # # OK pcmtest.capture
2558 09:07:33.953136 # ok 2 pcmtest.capture # SKIP Can't read patterns. Probably, module isn't loaded
2559 09:07:33.958722 # # RUN pcmtest.ni_capture ...
2560 09:07:33.964270 # # SKIP Can't read patterns. Probably, module isn't loaded
2561 09:07:33.964820 # # OK pcmtest.ni_capture
2562 09:07:33.975308 # ok 3 pcmtest.ni_capture # SKIP Can't read patterns. Probably, module isn't loaded
2563 09:07:33.975847 # # RUN pcmtest.ni_playback ...
2564 09:07:33.980817 # # SKIP Can't read patterns. Probably, module isn't loaded
2565 09:07:33.986407 # # OK pcmtest.ni_playback
2566 09:07:33.991933 # ok 4 pcmtest.ni_playback # SKIP Can't read patterns. Probably, module isn't loaded
2567 09:07:33.997709 # # RUN pcmtest.reset_ioctl ...
2568 09:07:34.003250 # # SKIP Can't read patterns. Probably, module isn't loaded
2569 09:07:34.008625 # # OK pcmtest.reset_ioctl
2570 09:07:34.014205 # ok 5 pcmtest.reset_ioctl # SKIP Can't read patterns. Probably, module isn't loaded
2571 09:07:34.019798 # # PASSED: 5 / 5 tests passed.
2572 09:07:34.025256 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:5 error:0
2573 09:07:34.025909 ok 3 selftests: alsa: test-pcmtest-driver
2574 09:07:34.030877 # timeout set to 45
2575 09:07:34.031535 # selftests: alsa: utimer-test
2576 09:07:34.032205 # TAP version 13
2577 09:07:34.032783 # 1..2
2578 09:07:34.036417 # # Starting 2 tests from 2 test cases.
2579 09:07:34.041854 # # RUN global.wrong_timers_test ...
2580 09:07:34.047436 # # OK global.wrong_timers_test
2581 09:07:34.048070 # ok 1 global.wrong_timers_test
2582 09:07:34.052981 # # RUN timer_f.utimer ...
2583 09:07:34.058594 # # utimer-test.c:55:utimer:Expected ioctl(timer_dev_fd, SNDRV_TIMER_IOCTL_CREATE, self->utimer_info) (-1) == 0 (0)
2584 09:07:34.064069 # # utimer: Test terminated by assertion
2585 09:07:34.069551 # # FAIL timer_f.utimer
2586 09:07:34.070022 # not ok 2 timer_f.utimer
2587 09:07:34.075161 # # FAILED: 1 / 2 tests passed.
2588 09:07:34.082679 # # Totals: pass:1 fail:1 xfail:0 xpass:0 skip:0 error:0
2589 09:07:34.083298 not ok 4 selftests: alsa: utimer-test # exit=1
2590 09:07:34.604724 alsa_mixer-test_get_value_LCALTA_60 pass
2591 09:07:34.610211 alsa_mixer-test_name_LCALTA_60 pass
2592 09:07:34.610864 alsa_mixer-test_write_default_LCALTA_60 pass
2593 09:07:34.615728 alsa_mixer-test_write_valid_LCALTA_60 pass
2594 09:07:34.619195 alsa_mixer-test_write_invalid_LCALTA_60 pass
2595 09:07:34.624747 alsa_mixer-test_event_missing_LCALTA_60 pass
2596 09:07:34.630386 alsa_mixer-test_event_spurious_LCALTA_60 pass
2597 09:07:34.631033 alsa_mixer-test_get_value_LCALTA_59 pass
2598 09:07:34.635783 alsa_mixer-test_name_LCALTA_59 pass
2599 09:07:34.641363 alsa_mixer-test_write_default_LCALTA_59 pass
2600 09:07:34.641974 alsa_mixer-test_write_valid_LCALTA_59 pass
2601 09:07:34.646884 alsa_mixer-test_write_invalid_LCALTA_59 pass
2602 09:07:34.652495 alsa_mixer-test_event_missing_LCALTA_59 pass
2603 09:07:34.653106 alsa_mixer-test_event_spurious_LCALTA_59 pass
2604 09:07:34.658035 alsa_mixer-test_get_value_LCALTA_58 pass
2605 09:07:34.663628 alsa_mixer-test_name_LCALTA_58 pass
2606 09:07:34.664276 alsa_mixer-test_write_default_LCALTA_58 pass
2607 09:07:34.669086 alsa_mixer-test_write_valid_LCALTA_58 pass
2608 09:07:34.674650 alsa_mixer-test_write_invalid_LCALTA_58 pass
2609 09:07:34.680228 alsa_mixer-test_event_missing_LCALTA_58 pass
2610 09:07:34.680851 alsa_mixer-test_event_spurious_LCALTA_58 pass
2611 09:07:34.685757 alsa_mixer-test_get_value_LCALTA_57 pass
2612 09:07:34.691301 alsa_mixer-test_name_LCALTA_57 pass
2613 09:07:34.691921 alsa_mixer-test_write_default_LCALTA_57 pass
2614 09:07:34.696977 alsa_mixer-test_write_valid_LCALTA_57 pass
2615 09:07:34.702399 alsa_mixer-test_write_invalid_LCALTA_57 pass
2616 09:07:34.702902 alsa_mixer-test_event_missing_LCALTA_57 pass
2617 09:07:34.707876 alsa_mixer-test_event_spurious_LCALTA_57 pass
2618 09:07:34.713539 alsa_mixer-test_get_value_LCALTA_56 pass
2619 09:07:34.714177 alsa_mixer-test_name_LCALTA_56 pass
2620 09:07:34.718968 alsa_mixer-test_write_default_LCALTA_56 pass
2621 09:07:34.724636 alsa_mixer-test_write_valid_LCALTA_56 pass
2622 09:07:34.725147 alsa_mixer-test_write_invalid_LCALTA_56 pass
2623 09:07:34.730052 alsa_mixer-test_event_missing_LCALTA_56 pass
2624 09:07:34.735619 alsa_mixer-test_event_spurious_LCALTA_56 pass
2625 09:07:34.741138 alsa_mixer-test_get_value_LCALTA_55 pass
2626 09:07:34.741613 alsa_mixer-test_name_LCALTA_55 pass
2627 09:07:34.746726 alsa_mixer-test_write_default_LCALTA_55 pass
2628 09:07:34.752269 alsa_mixer-test_write_valid_LCALTA_55 pass
2629 09:07:34.752766 alsa_mixer-test_write_invalid_LCALTA_55 pass
2630 09:07:34.757790 alsa_mixer-test_event_missing_LCALTA_55 pass
2631 09:07:34.763343 alsa_mixer-test_event_spurious_LCALTA_55 pass
2632 09:07:34.763859 alsa_mixer-test_get_value_LCALTA_54 pass
2633 09:07:34.768871 alsa_mixer-test_name_LCALTA_54 pass
2634 09:07:34.774549 alsa_mixer-test_write_default_LCALTA_54 pass
2635 09:07:34.775039 alsa_mixer-test_write_valid_LCALTA_54 pass
2636 09:07:34.779972 alsa_mixer-test_write_invalid_LCALTA_54 pass
2637 09:07:34.785694 alsa_mixer-test_event_missing_LCALTA_54 pass
2638 09:07:34.791073 alsa_mixer-test_event_spurious_LCALTA_54 pass
2639 09:07:34.791560 alsa_mixer-test_get_value_LCALTA_53 pass
2640 09:07:34.796599 alsa_mixer-test_name_LCALTA_53 pass
2641 09:07:34.802158 alsa_mixer-test_write_default_LCALTA_53 pass
2642 09:07:34.802641 alsa_mixer-test_write_valid_LCALTA_53 pass
2643 09:07:34.807744 alsa_mixer-test_write_invalid_LCALTA_53 pass
2644 09:07:34.813272 alsa_mixer-test_event_missing_LCALTA_53 pass
2645 09:07:34.813755 alsa_mixer-test_event_spurious_LCALTA_53 pass
2646 09:07:34.818787 alsa_mixer-test_get_value_LCALTA_52 pass
2647 09:07:34.824350 alsa_mixer-test_name_LCALTA_52 pass
2648 09:07:34.824816 alsa_mixer-test_write_default_LCALTA_52 pass
2649 09:07:34.829873 alsa_mixer-test_write_valid_LCALTA_52 pass
2650 09:07:34.835470 alsa_mixer-test_write_invalid_LCALTA_52 pass
2651 09:07:34.835926 alsa_mixer-test_event_missing_LCALTA_52 pass
2652 09:07:34.840985 alsa_mixer-test_event_spurious_LCALTA_52 pass
2653 09:07:34.846710 alsa_mixer-test_get_value_LCALTA_51 pass
2654 09:07:34.847229 alsa_mixer-test_name_LCALTA_51 pass
2655 09:07:34.852657 alsa_mixer-test_write_default_LCALTA_51 pass
2656 09:07:34.857665 alsa_mixer-test_write_valid_LCALTA_51 pass
2657 09:07:34.863167 alsa_mixer-test_write_invalid_LCALTA_51 pass
2658 09:07:34.863637 alsa_mixer-test_event_missing_LCALTA_51 pass
2659 09:07:34.868715 alsa_mixer-test_event_spurious_LCALTA_51 pass
2660 09:07:34.874245 alsa_mixer-test_get_value_LCALTA_50 pass
2661 09:07:34.874714 alsa_mixer-test_name_LCALTA_50 pass
2662 09:07:34.879877 alsa_mixer-test_write_default_LCALTA_50 pass
2663 09:07:34.885415 alsa_mixer-test_write_valid_LCALTA_50 pass
2664 09:07:34.885910 alsa_mixer-test_write_invalid_LCALTA_50 pass
2665 09:07:34.890899 alsa_mixer-test_event_missing_LCALTA_50 pass
2666 09:07:34.896496 alsa_mixer-test_event_spurious_LCALTA_50 pass
2667 09:07:34.896962 alsa_mixer-test_get_value_LCALTA_49 pass
2668 09:07:34.902033 alsa_mixer-test_name_LCALTA_49 pass
2669 09:07:34.907649 alsa_mixer-test_write_default_LCALTA_49 pass
2670 09:07:34.908159 alsa_mixer-test_write_valid_LCALTA_49 pass
2671 09:07:34.913138 alsa_mixer-test_write_invalid_LCALTA_49 pass
2672 09:07:34.918689 alsa_mixer-test_event_missing_LCALTA_49 pass
2673 09:07:34.924310 alsa_mixer-test_event_spurious_LCALTA_49 pass
2674 09:07:34.924795 alsa_mixer-test_get_value_LCALTA_48 pass
2675 09:07:34.929817 alsa_mixer-test_name_LCALTA_48 pass
2676 09:07:34.935279 alsa_mixer-test_write_default_LCALTA_48 pass
2677 09:07:34.935743 alsa_mixer-test_write_valid_LCALTA_48 pass
2678 09:07:34.940855 alsa_mixer-test_write_invalid_LCALTA_48 pass
2679 09:07:34.946408 alsa_mixer-test_event_missing_LCALTA_48 pass
2680 09:07:34.946884 alsa_mixer-test_event_spurious_LCALTA_48 pass
2681 09:07:34.951930 alsa_mixer-test_get_value_LCALTA_47 pass
2682 09:07:34.957510 alsa_mixer-test_name_LCALTA_47 pass
2683 09:07:34.957997 alsa_mixer-test_write_default_LCALTA_47 pass
2684 09:07:34.963017 alsa_mixer-test_write_valid_LCALTA_47 pass
2685 09:07:34.968695 alsa_mixer-test_write_invalid_LCALTA_47 pass
2686 09:07:34.974134 alsa_mixer-test_event_missing_LCALTA_47 pass
2687 09:07:34.974629 alsa_mixer-test_event_spurious_LCALTA_47 pass
2688 09:07:34.979743 alsa_mixer-test_get_value_LCALTA_46 pass
2689 09:07:34.980266 alsa_mixer-test_name_LCALTA_46 pass
2690 09:07:34.985196 alsa_mixer-test_write_default_LCALTA_46 pass
2691 09:07:34.990769 alsa_mixer-test_write_valid_LCALTA_46 pass
2692 09:07:34.996416 alsa_mixer-test_write_invalid_LCALTA_46 pass
2693 09:07:34.996871 alsa_mixer-test_event_missing_LCALTA_46 pass
2694 09:07:35.001824 alsa_mixer-test_event_spurious_LCALTA_46 pass
2695 09:07:35.007409 alsa_mixer-test_get_value_LCALTA_45 pass
2696 09:07:35.007893 alsa_mixer-test_name_LCALTA_45 pass
2697 09:07:35.012908 alsa_mixer-test_write_default_LCALTA_45 pass
2698 09:07:35.018503 alsa_mixer-test_write_valid_LCALTA_45 pass
2699 09:07:35.018956 alsa_mixer-test_write_invalid_LCALTA_45 pass
2700 09:07:35.024053 alsa_mixer-test_event_missing_LCALTA_45 pass
2701 09:07:35.029640 alsa_mixer-test_event_spurious_LCALTA_45 pass
2702 09:07:35.035140 alsa_mixer-test_get_value_LCALTA_44 pass
2703 09:07:35.035605 alsa_mixer-test_name_LCALTA_44 pass
2704 09:07:35.040650 alsa_mixer-test_write_default_LCALTA_44 pass
2705 09:07:35.046198 alsa_mixer-test_write_valid_LCALTA_44 pass
2706 09:07:35.046657 alsa_mixer-test_write_invalid_LCALTA_44 pass
2707 09:07:35.051774 alsa_mixer-test_event_missing_LCALTA_44 pass
2708 09:07:35.057301 alsa_mixer-test_event_spurious_LCALTA_44 pass
2709 09:07:35.057770 alsa_mixer-test_get_value_LCALTA_43 pass
2710 09:07:35.062834 alsa_mixer-test_name_LCALTA_43 pass
2711 09:07:35.068454 alsa_mixer-test_write_default_LCALTA_43 pass
2712 09:07:35.068914 alsa_mixer-test_write_valid_LCALTA_43 pass
2713 09:07:35.073981 alsa_mixer-test_write_invalid_LCALTA_43 pass
2714 09:07:35.079517 alsa_mixer-test_event_missing_LCALTA_43 pass
2715 09:07:35.080018 alsa_mixer-test_event_spurious_LCALTA_43 pass
2716 09:07:35.085032 alsa_mixer-test_get_value_LCALTA_42 pass
2717 09:07:35.090701 alsa_mixer-test_name_LCALTA_42 pass
2718 09:07:35.091181 alsa_mixer-test_write_default_LCALTA_42 pass
2719 09:07:35.096182 alsa_mixer-test_write_valid_LCALTA_42 pass
2720 09:07:35.101684 alsa_mixer-test_write_invalid_LCALTA_42 pass
2721 09:07:35.107303 alsa_mixer-test_event_missing_LCALTA_42 pass
2722 09:07:35.107814 alsa_mixer-test_event_spurious_LCALTA_42 pass
2723 09:07:35.112820 alsa_mixer-test_get_value_LCALTA_41 pass
2724 09:07:35.118332 alsa_mixer-test_name_LCALTA_41 pass
2725 09:07:35.118797 alsa_mixer-test_write_default_LCALTA_41 pass
2726 09:07:35.123863 alsa_mixer-test_write_valid_LCALTA_41 pass
2727 09:07:35.129430 alsa_mixer-test_write_invalid_LCALTA_41 pass
2728 09:07:35.129916 alsa_mixer-test_event_missing_LCALTA_41 pass
2729 09:07:35.134891 alsa_mixer-test_event_spurious_LCALTA_41 pass
2730 09:07:35.140466 alsa_mixer-test_get_value_LCALTA_40 pass
2731 09:07:35.140906 alsa_mixer-test_name_LCALTA_40 pass
2732 09:07:35.146060 alsa_mixer-test_write_default_LCALTA_40 pass
2733 09:07:35.151656 alsa_mixer-test_write_valid_LCALTA_40 pass
2734 09:07:35.152163 alsa_mixer-test_write_invalid_LCALTA_40 pass
2735 09:07:35.157172 alsa_mixer-test_event_missing_LCALTA_40 pass
2736 09:07:35.162641 alsa_mixer-test_event_spurious_LCALTA_40 pass
2737 09:07:35.168190 alsa_mixer-test_get_value_LCALTA_39 pass
2738 09:07:35.168653 alsa_mixer-test_name_LCALTA_39 pass
2739 09:07:35.173784 alsa_mixer-test_write_default_LCALTA_39 pass
2740 09:07:35.179278 alsa_mixer-test_write_valid_LCALTA_39 pass
2741 09:07:35.179729 alsa_mixer-test_write_invalid_LCALTA_39 pass
2742 09:07:35.184822 alsa_mixer-test_event_missing_LCALTA_39 pass
2743 09:07:35.190442 alsa_mixer-test_event_spurious_LCALTA_39 pass
2744 09:07:35.190920 alsa_mixer-test_get_value_LCALTA_38 pass
2745 09:07:35.195950 alsa_mixer-test_name_LCALTA_38 pass
2746 09:07:35.201499 alsa_mixer-test_write_default_LCALTA_38 pass
2747 09:07:35.201959 alsa_mixer-test_write_valid_LCALTA_38 pass
2748 09:07:35.207018 alsa_mixer-test_write_invalid_LCALTA_38 pass
2749 09:07:35.212596 alsa_mixer-test_event_missing_LCALTA_38 pass
2750 09:07:35.218220 alsa_mixer-test_event_spurious_LCALTA_38 pass
2751 09:07:35.218649 alsa_mixer-test_get_value_LCALTA_37 pass
2752 09:07:35.223806 alsa_mixer-test_name_LCALTA_37 pass
2753 09:07:35.229306 alsa_mixer-test_write_default_LCALTA_37 pass
2754 09:07:35.229814 alsa_mixer-test_write_valid_LCALTA_37 pass
2755 09:07:35.234772 alsa_mixer-test_write_invalid_LCALTA_37 pass
2756 09:07:35.240373 alsa_mixer-test_event_missing_LCALTA_37 pass
2757 09:07:35.240895 alsa_mixer-test_event_spurious_LCALTA_37 pass
2758 09:07:35.245946 alsa_mixer-test_get_value_LCALTA_36 pass
2759 09:07:35.251480 alsa_mixer-test_name_LCALTA_36 pass
2760 09:07:35.252169 alsa_mixer-test_write_default_LCALTA_36 pass
2761 09:07:35.256974 alsa_mixer-test_write_valid_LCALTA_36 pass
2762 09:07:35.262544 alsa_mixer-test_write_invalid_LCALTA_36 pass
2763 09:07:35.263174 alsa_mixer-test_event_missing_LCALTA_36 pass
2764 09:07:35.268095 alsa_mixer-test_event_spurious_LCALTA_36 pass
2765 09:07:35.273656 alsa_mixer-test_get_value_LCALTA_35 pass
2766 09:07:35.274240 alsa_mixer-test_name_LCALTA_35 pass
2767 09:07:35.279183 alsa_mixer-test_write_default_LCALTA_35 pass
2768 09:07:35.284713 alsa_mixer-test_write_valid_LCALTA_35 pass
2769 09:07:35.290342 alsa_mixer-test_write_invalid_LCALTA_35 pass
2770 09:07:35.290934 alsa_mixer-test_event_missing_LCALTA_35 pass
2771 09:07:35.295896 alsa_mixer-test_event_spurious_LCALTA_35 pass
2772 09:07:35.301679 alsa_mixer-test_get_value_LCALTA_34 pass
2773 09:07:35.302260 alsa_mixer-test_name_LCALTA_34 pass
2774 09:07:35.306903 alsa_mixer-test_write_default_LCALTA_34 pass
2775 09:07:35.312455 alsa_mixer-test_write_valid_LCALTA_34 pass
2776 09:07:35.313027 alsa_mixer-test_write_invalid_LCALTA_34 pass
2777 09:07:35.317995 alsa_mixer-test_event_missing_LCALTA_34 pass
2778 09:07:35.323554 alsa_mixer-test_event_spurious_LCALTA_34 pass
2779 09:07:35.324165 alsa_mixer-test_get_value_LCALTA_33 pass
2780 09:07:35.329054 alsa_mixer-test_name_LCALTA_33 pass
2781 09:07:35.334695 alsa_mixer-test_write_default_LCALTA_33 pass
2782 09:07:35.335264 alsa_mixer-test_write_valid_LCALTA_33 pass
2783 09:07:35.340225 alsa_mixer-test_write_invalid_LCALTA_33 pass
2784 09:07:35.345734 alsa_mixer-test_event_missing_LCALTA_33 pass
2785 09:07:35.351327 alsa_mixer-test_event_spurious_LCALTA_33 pass
2786 09:07:35.352159 alsa_mixer-test_get_value_LCALTA_32 pass
2787 09:07:35.356844 alsa_mixer-test_name_LCALTA_32 pass
2788 09:07:35.362389 alsa_mixer-test_write_default_LCALTA_32 pass
2789 09:07:35.363004 alsa_mixer-test_write_valid_LCALTA_32 pass
2790 09:07:35.367957 alsa_mixer-test_write_invalid_LCALTA_32 pass
2791 09:07:35.373502 alsa_mixer-test_event_missing_LCALTA_32 pass
2792 09:07:35.374103 alsa_mixer-test_event_spurious_LCALTA_32 pass
2793 09:07:35.379056 alsa_mixer-test_get_value_LCALTA_31 pass
2794 09:07:35.384634 alsa_mixer-test_name_LCALTA_31 pass
2795 09:07:35.385203 alsa_mixer-test_write_default_LCALTA_31 pass
2796 09:07:35.390108 alsa_mixer-test_write_valid_LCALTA_31 pass
2797 09:07:35.395717 alsa_mixer-test_write_invalid_LCALTA_31 pass
2798 09:07:35.401199 alsa_mixer-test_event_missing_LCALTA_31 pass
2799 09:07:35.401775 alsa_mixer-test_event_spurious_LCALTA_31 pass
2800 09:07:35.406775 alsa_mixer-test_get_value_LCALTA_30 pass
2801 09:07:35.407357 alsa_mixer-test_name_LCALTA_30 pass
2802 09:07:35.412323 alsa_mixer-test_write_default_LCALTA_30 pass
2803 09:07:35.417836 alsa_mixer-test_write_valid_LCALTA_30 pass
2804 09:07:35.423407 alsa_mixer-test_write_invalid_LCALTA_30 pass
2805 09:07:35.424046 alsa_mixer-test_event_missing_LCALTA_30 pass
2806 09:07:35.429153 alsa_mixer-test_event_spurious_LCALTA_30 pass
2807 09:07:35.434496 alsa_mixer-test_get_value_LCALTA_29 pass
2808 09:07:35.434981 alsa_mixer-test_name_LCALTA_29 pass
2809 09:07:35.439998 alsa_mixer-test_write_default_LCALTA_29 pass
2810 09:07:35.445634 alsa_mixer-test_write_valid_LCALTA_29 pass
2811 09:07:35.446103 alsa_mixer-test_write_invalid_LCALTA_29 pass
2812 09:07:35.451219 alsa_mixer-test_event_missing_LCALTA_29 pass
2813 09:07:35.456758 alsa_mixer-test_event_spurious_LCALTA_29 pass
2814 09:07:35.462212 alsa_mixer-test_get_value_LCALTA_28 pass
2815 09:07:35.462680 alsa_mixer-test_name_LCALTA_28 pass
2816 09:07:35.467734 alsa_mixer-test_write_default_LCALTA_28 pass
2817 09:07:35.473356 alsa_mixer-test_write_valid_LCALTA_28 pass
2818 09:07:35.473820 alsa_mixer-test_write_invalid_LCALTA_28 pass
2819 09:07:35.478849 alsa_mixer-test_event_missing_LCALTA_28 pass
2820 09:07:35.484388 alsa_mixer-test_event_spurious_LCALTA_28 pass
2821 09:07:35.484875 alsa_mixer-test_get_value_LCALTA_27 pass
2822 09:07:35.490152 alsa_mixer-test_name_LCALTA_27 pass
2823 09:07:35.495612 alsa_mixer-test_write_default_LCALTA_27 pass
2824 09:07:35.496100 alsa_mixer-test_write_valid_LCALTA_27 pass
2825 09:07:35.501151 alsa_mixer-test_write_invalid_LCALTA_27 pass
2826 09:07:35.506740 alsa_mixer-test_event_missing_LCALTA_27 pass
2827 09:07:35.507224 alsa_mixer-test_event_spurious_LCALTA_27 pass
2828 09:07:35.512122 alsa_mixer-test_get_value_LCALTA_26 pass
2829 09:07:35.517760 alsa_mixer-test_name_LCALTA_26 pass
2830 09:07:35.518246 alsa_mixer-test_write_default_LCALTA_26 skip
2831 09:07:35.523332 alsa_mixer-test_write_valid_LCALTA_26 skip
2832 09:07:35.528873 alsa_mixer-test_write_invalid_LCALTA_26 skip
2833 09:07:35.534313 alsa_mixer-test_event_missing_LCALTA_26 pass
2834 09:07:35.534776 alsa_mixer-test_event_spurious_LCALTA_26 pass
2835 09:07:35.539854 alsa_mixer-test_get_value_LCALTA_25 pass
2836 09:07:35.545434 alsa_mixer-test_name_LCALTA_25 pass
2837 09:07:35.545921 alsa_mixer-test_write_default_LCALTA_25 pass
2838 09:07:35.550992 alsa_mixer-test_write_valid_LCALTA_25 skip
2839 09:07:35.556566 alsa_mixer-test_write_invalid_LCALTA_25 skip
2840 09:07:35.557196 alsa_mixer-test_event_missing_LCALTA_25 pass
2841 09:07:35.561995 alsa_mixer-test_event_spurious_LCALTA_25 pass
2842 09:07:35.567578 alsa_mixer-test_get_value_LCALTA_24 pass
2843 09:07:35.568109 alsa_mixer-test_name_LCALTA_24 pass
2844 09:07:35.573130 alsa_mixer-test_write_default_LCALTA_24 skip
2845 09:07:35.578731 alsa_mixer-test_write_valid_LCALTA_24 skip
2846 09:07:35.579205 alsa_mixer-test_write_invalid_LCALTA_24 skip
2847 09:07:35.584225 alsa_mixer-test_event_missing_LCALTA_24 pass
2848 09:07:35.589771 alsa_mixer-test_event_spurious_LCALTA_24 pass
2849 09:07:35.595367 alsa_mixer-test_get_value_LCALTA_23 pass
2850 09:07:35.595826 alsa_mixer-test_name_LCALTA_23 pass
2851 09:07:35.600917 alsa_mixer-test_write_default_LCALTA_23 skip
2852 09:07:35.606434 alsa_mixer-test_write_valid_LCALTA_23 skip
2853 09:07:35.606905 alsa_mixer-test_write_invalid_LCALTA_23 skip
2854 09:07:35.612010 alsa_mixer-test_event_missing_LCALTA_23 pass
2855 09:07:35.617646 alsa_mixer-test_event_spurious_LCALTA_23 pass
2856 09:07:35.618207 alsa_mixer-test_get_value_LCALTA_22 pass
2857 09:07:35.623130 alsa_mixer-test_name_LCALTA_22 pass
2858 09:07:35.628731 alsa_mixer-test_write_default_LCALTA_22 pass
2859 09:07:35.629311 alsa_mixer-test_write_valid_LCALTA_22 pass
2860 09:07:35.634140 alsa_mixer-test_write_invalid_LCALTA_22 pass
2861 09:07:35.639711 alsa_mixer-test_event_missing_LCALTA_22 pass
2862 09:07:35.645240 alsa_mixer-test_event_spurious_LCALTA_22 pass
2863 09:07:35.645723 alsa_mixer-test_get_value_LCALTA_21 pass
2864 09:07:35.650759 alsa_mixer-test_name_LCALTA_21 pass
2865 09:07:35.656318 alsa_mixer-test_write_default_LCALTA_21 pass
2866 09:07:35.656804 alsa_mixer-test_write_valid_LCALTA_21 pass
2867 09:07:35.661923 alsa_mixer-test_write_invalid_LCALTA_21 pass
2868 09:07:35.667564 alsa_mixer-test_event_missing_LCALTA_21 pass
2869 09:07:35.668331 alsa_mixer-test_event_spurious_LCALTA_21 pass
2870 09:07:35.673127 alsa_mixer-test_get_value_LCALTA_20 pass
2871 09:07:35.678608 alsa_mixer-test_name_LCALTA_20 pass
2872 09:07:35.678918 alsa_mixer-test_write_default_LCALTA_20 pass
2873 09:07:35.684117 alsa_mixer-test_write_valid_LCALTA_20 pass
2874 09:07:35.689646 alsa_mixer-test_write_invalid_LCALTA_20 pass
2875 09:07:35.690065 alsa_mixer-test_event_missing_LCALTA_20 pass
2876 09:07:35.695107 alsa_mixer-test_event_spurious_LCALTA_20 pass
2877 09:07:35.700703 alsa_mixer-test_get_value_LCALTA_19 pass
2878 09:07:35.701021 alsa_mixer-test_name_LCALTA_19 pass
2879 09:07:35.706227 alsa_mixer-test_write_default_LCALTA_19 pass
2880 09:07:35.711756 alsa_mixer-test_write_valid_LCALTA_19 pass
2881 09:07:35.717360 alsa_mixer-test_write_invalid_LCALTA_19 pass
2882 09:07:35.717890 alsa_mixer-test_event_missing_LCALTA_19 pass
2883 09:07:35.722817 alsa_mixer-test_event_spurious_LCALTA_19 pass
2884 09:07:35.728466 alsa_mixer-test_get_value_LCALTA_18 pass
2885 09:07:35.729033 alsa_mixer-test_name_LCALTA_18 pass
2886 09:07:35.733967 alsa_mixer-test_write_default_LCALTA_18 pass
2887 09:07:35.739646 alsa_mixer-test_write_valid_LCALTA_18 pass
2888 09:07:35.740190 alsa_mixer-test_write_invalid_LCALTA_18 pass
2889 09:07:35.745278 alsa_mixer-test_event_missing_LCALTA_18 pass
2890 09:07:35.750802 alsa_mixer-test_event_spurious_LCALTA_18 pass
2891 09:07:35.751370 alsa_mixer-test_get_value_LCALTA_17 pass
2892 09:07:35.756237 alsa_mixer-test_name_LCALTA_17 pass
2893 09:07:35.761745 alsa_mixer-test_write_default_LCALTA_17 pass
2894 09:07:35.762342 alsa_mixer-test_write_valid_LCALTA_17 pass
2895 09:07:35.767456 alsa_mixer-test_write_invalid_LCALTA_17 pass
2896 09:07:35.772821 alsa_mixer-test_event_missing_LCALTA_17 pass
2897 09:07:35.778381 alsa_mixer-test_event_spurious_LCALTA_17 pass
2898 09:07:35.778929 alsa_mixer-test_get_value_LCALTA_16 pass
2899 09:07:35.783811 alsa_mixer-test_name_LCALTA_16 pass
2900 09:07:35.789367 alsa_mixer-test_write_default_LCALTA_16 pass
2901 09:07:35.789872 alsa_mixer-test_write_valid_LCALTA_16 pass
2902 09:07:35.794909 alsa_mixer-test_write_invalid_LCALTA_16 pass
2903 09:07:35.800566 alsa_mixer-test_event_missing_LCALTA_16 pass
2904 09:07:35.801128 alsa_mixer-test_event_spurious_LCALTA_16 pass
2905 09:07:35.806089 alsa_mixer-test_get_value_LCALTA_15 pass
2906 09:07:35.811702 alsa_mixer-test_name_LCALTA_15 pass
2907 09:07:35.812268 alsa_mixer-test_write_default_LCALTA_15 pass
2908 09:07:35.817217 alsa_mixer-test_write_valid_LCALTA_15 pass
2909 09:07:35.822789 alsa_mixer-test_write_invalid_LCALTA_15 pass
2910 09:07:35.828329 alsa_mixer-test_event_missing_LCALTA_15 pass
2911 09:07:35.828884 alsa_mixer-test_event_spurious_LCALTA_15 pass
2912 09:07:35.833755 alsa_mixer-test_get_value_LCALTA_14 pass
2913 09:07:35.834306 alsa_mixer-test_name_LCALTA_14 pass
2914 09:07:35.839454 alsa_mixer-test_write_default_LCALTA_14 pass
2915 09:07:35.844912 alsa_mixer-test_write_valid_LCALTA_14 pass
2916 09:07:35.850408 alsa_mixer-test_write_invalid_LCALTA_14 pass
2917 09:07:35.850920 alsa_mixer-test_event_missing_LCALTA_14 pass
2918 09:07:35.856084 alsa_mixer-test_event_spurious_LCALTA_14 pass
2919 09:07:35.861612 alsa_mixer-test_get_value_LCALTA_13 pass
2920 09:07:35.862113 alsa_mixer-test_name_LCALTA_13 pass
2921 09:07:35.867064 alsa_mixer-test_write_default_LCALTA_13 pass
2922 09:07:35.872681 alsa_mixer-test_write_valid_LCALTA_13 pass
2923 09:07:35.873180 alsa_mixer-test_write_invalid_LCALTA_13 pass
2924 09:07:35.878138 alsa_mixer-test_event_missing_LCALTA_13 pass
2925 09:07:35.883660 alsa_mixer-test_event_spurious_LCALTA_13 pass
2926 09:07:35.889227 alsa_mixer-test_get_value_LCALTA_12 pass
2927 09:07:35.889736 alsa_mixer-test_name_LCALTA_12 pass
2928 09:07:35.894947 alsa_mixer-test_write_default_LCALTA_12 pass
2929 09:07:35.900456 alsa_mixer-test_write_valid_LCALTA_12 pass
2930 09:07:35.900959 alsa_mixer-test_write_invalid_LCALTA_12 pass
2931 09:07:35.905953 alsa_mixer-test_event_missing_LCALTA_12 pass
2932 09:07:35.911451 alsa_mixer-test_event_spurious_LCALTA_12 pass
2933 09:07:35.911962 alsa_mixer-test_get_value_LCALTA_11 pass
2934 09:07:35.916982 alsa_mixer-test_name_LCALTA_11 pass
2935 09:07:35.922550 alsa_mixer-test_write_default_LCALTA_11 pass
2936 09:07:35.923053 alsa_mixer-test_write_valid_LCALTA_11 pass
2937 09:07:35.928076 alsa_mixer-test_write_invalid_LCALTA_11 pass
2938 09:07:35.933713 alsa_mixer-test_event_missing_LCALTA_11 pass
2939 09:07:35.934213 alsa_mixer-test_event_spurious_LCALTA_11 pass
2940 09:07:35.939185 alsa_mixer-test_get_value_LCALTA_10 pass
2941 09:07:35.944705 alsa_mixer-test_name_LCALTA_10 pass
2942 09:07:35.945214 alsa_mixer-test_write_default_LCALTA_10 pass
2943 09:07:35.950258 alsa_mixer-test_write_valid_LCALTA_10 pass
2944 09:07:35.955872 alsa_mixer-test_write_invalid_LCALTA_10 pass
2945 09:07:35.961323 alsa_mixer-test_event_missing_LCALTA_10 pass
2946 09:07:35.961823 alsa_mixer-test_event_spurious_LCALTA_10 pass
2947 09:07:35.966926 alsa_mixer-test_get_value_LCALTA_9 pass
2948 09:07:35.972466 alsa_mixer-test_name_LCALTA_9 pass
2949 09:07:35.972978 alsa_mixer-test_write_default_LCALTA_9 pass
2950 09:07:35.978027 alsa_mixer-test_write_valid_LCALTA_9 pass
2951 09:07:35.983665 alsa_mixer-test_write_invalid_LCALTA_9 pass
2952 09:07:35.984215 alsa_mixer-test_event_missing_LCALTA_9 pass
2953 09:07:35.989147 alsa_mixer-test_event_spurious_LCALTA_9 pass
2954 09:07:35.994750 alsa_mixer-test_get_value_LCALTA_8 pass
2955 09:07:35.995329 alsa_mixer-test_name_LCALTA_8 pass
2956 09:07:36.000177 alsa_mixer-test_write_default_LCALTA_8 pass
2957 09:07:36.005696 alsa_mixer-test_write_valid_LCALTA_8 pass
2958 09:07:36.006233 alsa_mixer-test_write_invalid_LCALTA_8 pass
2959 09:07:36.011341 alsa_mixer-test_event_missing_LCALTA_8 pass
2960 09:07:36.016800 alsa_mixer-test_event_spurious_LCALTA_8 pass
2961 09:07:36.017403 alsa_mixer-test_get_value_LCALTA_7 pass
2962 09:07:36.022360 alsa_mixer-test_name_LCALTA_7 pass
2963 09:07:36.028008 alsa_mixer-test_write_default_LCALTA_7 pass
2964 09:07:36.028615 alsa_mixer-test_write_valid_LCALTA_7 pass
2965 09:07:36.033574 alsa_mixer-test_write_invalid_LCALTA_7 pass
2966 09:07:36.039046 alsa_mixer-test_event_missing_LCALTA_7 pass
2967 09:07:36.039541 alsa_mixer-test_event_spurious_LCALTA_7 pass
2968 09:07:36.044684 alsa_mixer-test_get_value_LCALTA_6 pass
2969 09:07:36.050137 alsa_mixer-test_name_LCALTA_6 pass
2970 09:07:36.050610 alsa_mixer-test_write_default_LCALTA_6 pass
2971 09:07:36.055767 alsa_mixer-test_write_valid_LCALTA_6 pass
2972 09:07:36.061190 alsa_mixer-test_write_invalid_LCALTA_6 pass
2973 09:07:36.061681 alsa_mixer-test_event_missing_LCALTA_6 pass
2974 09:07:36.066783 alsa_mixer-test_event_spurious_LCALTA_6 pass
2975 09:07:36.072286 alsa_mixer-test_get_value_LCALTA_5 pass
2976 09:07:36.072770 alsa_mixer-test_name_LCALTA_5 pass
2977 09:07:36.077830 alsa_mixer-test_write_default_LCALTA_5 pass
2978 09:07:36.083391 alsa_mixer-test_write_valid_LCALTA_5 pass
2979 09:07:36.083889 alsa_mixer-test_write_invalid_LCALTA_5 pass
2980 09:07:36.088944 alsa_mixer-test_event_missing_LCALTA_5 pass
2981 09:07:36.094513 alsa_mixer-test_event_spurious_LCALTA_5 pass
2982 09:07:36.094993 alsa_mixer-test_get_value_LCALTA_4 pass
2983 09:07:36.100035 alsa_mixer-test_name_LCALTA_4 pass
2984 09:07:36.105609 alsa_mixer-test_write_default_LCALTA_4 pass
2985 09:07:36.106089 alsa_mixer-test_write_valid_LCALTA_4 pass
2986 09:07:36.111261 alsa_mixer-test_write_invalid_LCALTA_4 pass
2987 09:07:36.116849 alsa_mixer-test_event_missing_LCALTA_4 pass
2988 09:07:36.122263 alsa_mixer-test_event_spurious_LCALTA_4 pass
2989 09:07:36.122737 alsa_mixer-test_get_value_LCALTA_3 pass
2990 09:07:36.127802 alsa_mixer-test_name_LCALTA_3 pass
2991 09:07:36.128306 alsa_mixer-test_write_default_LCALTA_3 pass
2992 09:07:36.133324 alsa_mixer-test_write_valid_LCALTA_3 pass
2993 09:07:36.138853 alsa_mixer-test_write_invalid_LCALTA_3 pass
2994 09:07:36.144431 alsa_mixer-test_event_missing_LCALTA_3 pass
2995 09:07:36.144926 alsa_mixer-test_event_spurious_LCALTA_3 pass
2996 09:07:36.149917 alsa_mixer-test_get_value_LCALTA_2 pass
2997 09:07:36.150397 alsa_mixer-test_name_LCALTA_2 pass
2998 09:07:36.155501 alsa_mixer-test_write_default_LCALTA_2 pass
2999 09:07:36.161016 alsa_mixer-test_write_valid_LCALTA_2 pass
3000 09:07:36.166613 alsa_mixer-test_write_invalid_LCALTA_2 pass
3001 09:07:36.167149 alsa_mixer-test_event_missing_LCALTA_2 pass
3002 09:07:36.172115 alsa_mixer-test_event_spurious_LCALTA_2 pass
3003 09:07:36.177772 alsa_mixer-test_get_value_LCALTA_1 pass
3004 09:07:36.178272 alsa_mixer-test_name_LCALTA_1 pass
3005 09:07:36.183332 alsa_mixer-test_write_default_LCALTA_1 pass
3006 09:07:36.188865 alsa_mixer-test_write_valid_LCALTA_1 pass
3007 09:07:36.189377 alsa_mixer-test_write_invalid_LCALTA_1 pass
3008 09:07:36.194400 alsa_mixer-test_event_missing_LCALTA_1 pass
3009 09:07:36.199903 alsa_mixer-test_event_spurious_LCALTA_1 pass
3010 09:07:36.200418 alsa_mixer-test_get_value_LCALTA_0 pass
3011 09:07:36.205407 alsa_mixer-test_name_LCALTA_0 pass
3012 09:07:36.210967 alsa_mixer-test_write_default_LCALTA_0 pass
3013 09:07:36.211458 alsa_mixer-test_write_valid_LCALTA_0 pass
3014 09:07:36.216499 alsa_mixer-test_write_invalid_LCALTA_0 pass
3015 09:07:36.222068 alsa_mixer-test_event_missing_LCALTA_0 pass
3016 09:07:36.222587 alsa_mixer-test_event_spurious_LCALTA_0 pass
3017 09:07:36.227618 alsa_mixer-test pass
3018 09:07:36.233177 alsa_pcm-test_default_time1_LCALTA_5_0_CAPTURE skip
3019 09:07:36.233674 alsa_pcm-test_default_time2_LCALTA_5_0_CAPTURE skip
3020 09:07:36.238764 alsa_pcm-test_default_time3_LCALTA_5_0_CAPTURE skip
3021 09:07:36.244253 alsa_pcm-test_default_time4_LCALTA_5_0_CAPTURE skip
3022 09:07:36.249811 alsa_pcm-test_default_time5_LCALTA_5_0_CAPTURE skip
3023 09:07:36.255338 alsa_pcm-test_default_time6_LCALTA_5_0_CAPTURE skip
3024 09:07:36.255825 alsa_pcm-test_default_time7_LCALTA_5_0_CAPTURE skip
3025 09:07:36.260914 alsa_pcm-test_default_time1_LCALTA_4_0_CAPTURE skip
3026 09:07:36.266422 alsa_pcm-test_default_time2_LCALTA_4_0_CAPTURE skip
3027 09:07:36.271954 alsa_pcm-test_default_time3_LCALTA_4_0_CAPTURE skip
3028 09:07:36.277506 alsa_pcm-test_default_time4_LCALTA_4_0_CAPTURE skip
3029 09:07:36.283056 alsa_pcm-test_default_time5_LCALTA_4_0_CAPTURE skip
3030 09:07:36.283558 alsa_pcm-test_default_time6_LCALTA_4_0_CAPTURE skip
3031 09:07:36.288657 alsa_pcm-test_default_time7_LCALTA_4_0_CAPTURE skip
3032 09:07:36.294167 alsa_pcm-test_default_time1_LCALTA_3_0_CAPTURE skip
3033 09:07:36.299770 alsa_pcm-test_default_time2_LCALTA_3_0_CAPTURE skip
3034 09:07:36.305248 alsa_pcm-test_default_time3_LCALTA_3_0_CAPTURE skip
3035 09:07:36.310843 alsa_pcm-test_default_time4_LCALTA_3_0_CAPTURE skip
3036 09:07:36.311348 alsa_pcm-test_default_time5_LCALTA_3_0_CAPTURE skip
3037 09:07:36.316389 alsa_pcm-test_default_time6_LCALTA_3_0_CAPTURE skip
3038 09:07:36.321954 alsa_pcm-test_default_time7_LCALTA_3_0_CAPTURE skip
3039 09:07:36.327429 alsa_pcm-test_default_time1_LCALTA_2_0_PLAYBACK skip
3040 09:07:36.333048 alsa_pcm-test_default_time2_LCALTA_2_0_PLAYBACK skip
3041 09:07:36.338664 alsa_pcm-test_default_time3_LCALTA_2_0_PLAYBACK skip
3042 09:07:36.339165 alsa_pcm-test_default_time4_LCALTA_2_0_PLAYBACK skip
3043 09:07:36.344122 alsa_pcm-test_default_time5_LCALTA_2_0_PLAYBACK skip
3044 09:07:36.349679 alsa_pcm-test_default_time6_LCALTA_2_0_PLAYBACK skip
3045 09:07:36.355152 alsa_pcm-test_default_time7_LCALTA_2_0_PLAYBACK skip
3046 09:07:36.360770 alsa_pcm-test_default_time1_LCALTA_1_0_PLAYBACK skip
3047 09:07:36.366266 alsa_pcm-test_default_time2_LCALTA_1_0_PLAYBACK skip
3048 09:07:36.371816 alsa_pcm-test_default_time3_LCALTA_1_0_PLAYBACK skip
3049 09:07:36.372349 alsa_pcm-test_default_time4_LCALTA_1_0_PLAYBACK skip
3050 09:07:36.377329 alsa_pcm-test_default_time5_LCALTA_1_0_PLAYBACK skip
3051 09:07:36.382921 alsa_pcm-test_default_time6_LCALTA_1_0_PLAYBACK skip
3052 09:07:36.388440 alsa_pcm-test_default_time7_LCALTA_1_0_PLAYBACK skip
3053 09:07:36.394029 alsa_pcm-test_default_time1_LCALTA_0_0_PLAYBACK skip
3054 09:07:36.399570 alsa_pcm-test_default_time2_LCALTA_0_0_PLAYBACK skip
3055 09:07:36.400120 alsa_pcm-test_default_time3_LCALTA_0_0_PLAYBACK skip
3056 09:07:36.405103 alsa_pcm-test_default_time4_LCALTA_0_0_PLAYBACK skip
3057 09:07:36.410756 alsa_pcm-test_default_time5_LCALTA_0_0_PLAYBACK skip
3058 09:07:36.416238 alsa_pcm-test_default_time6_LCALTA_0_0_PLAYBACK skip
3059 09:07:36.421794 alsa_pcm-test_default_time7_LCALTA_0_0_PLAYBACK skip
3060 09:07:36.422285 alsa_pcm-test pass
3061 09:07:36.432826 alsa_test-pcmtest-driver_pcmtest_playback_Can_t_read_patterns_Probably_module_isn_t_loaded skip
3062 09:07:36.438351 alsa_test-pcmtest-driver_pcmtest_capture_Can_t_read_patterns_Probably_module_isn_t_loaded skip
3063 09:07:36.449455 alsa_test-pcmtest-driver_pcmtest_ni_capture_Can_t_read_patterns_Probably_module_isn_t_loaded skip
3064 09:07:36.455072 alsa_test-pcmtest-driver_pcmtest_ni_playback_Can_t_read_patterns_Probably_module_isn_t_loaded skip
3065 09:07:36.466121 alsa_test-pcmtest-driver_pcmtest_reset_ioctl_Can_t_read_patterns_Probably_module_isn_t_loaded skip
3066 09:07:36.466639 alsa_test-pcmtest-driver pass
3067 09:07:36.471641 alsa_utimer-test_global_wrong_timers_test pass
3068 09:07:36.477464 alsa_utimer-test_timer_f_utimer fail
3069 09:07:36.478036 alsa_utimer-test fail
3070 09:07:36.482890 + ../../utils/send-to-lava.sh ./output/result.txt
3071 09:07:36.488332 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-alsa RESULT=pass>
3072 09:07:36.489390 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-alsa RESULT=pass
3074 09:07:36.493868 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_60 RESULT=pass>
3075 09:07:36.494685 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_60 RESULT=pass
3077 09:07:36.501836 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_60 RESULT=pass>
3078 09:07:36.502666 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_60 RESULT=pass
3080 09:07:36.518252 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_60 RESULT=pass>
3081 09:07:36.519072 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_60 RESULT=pass
3083 09:07:36.570360 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_60 RESULT=pass>
3084 09:07:36.571250 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_60 RESULT=pass
3086 09:07:36.614898 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_60 RESULT=pass>
3087 09:07:36.615794 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_60 RESULT=pass
3089 09:07:36.667398 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_60 RESULT=pass>
3090 09:07:36.668301 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_60 RESULT=pass
3092 09:07:36.713106 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_60 RESULT=pass>
3093 09:07:36.713931 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_60 RESULT=pass
3095 09:07:36.773073 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_59 RESULT=pass>
3096 09:07:36.774021 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_59 RESULT=pass
3098 09:07:36.821085 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_59 RESULT=pass>
3099 09:07:36.821949 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_59 RESULT=pass
3101 09:07:36.879430 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_59 RESULT=pass>
3102 09:07:36.880328 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_59 RESULT=pass
3104 09:07:36.942106 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_59 RESULT=pass>
3105 09:07:36.942959 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_59 RESULT=pass
3107 09:07:37.004333 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_59 RESULT=pass>
3108 09:07:37.005206 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_59 RESULT=pass
3110 09:07:37.058614 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_59 RESULT=pass>
3111 09:07:37.059488 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_59 RESULT=pass
3113 09:07:37.117117 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_59 RESULT=pass>
3114 09:07:37.117988 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_59 RESULT=pass
3116 09:07:37.171104 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_58 RESULT=pass>
3117 09:07:37.171960 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_58 RESULT=pass
3119 09:07:37.216642 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_58 RESULT=pass>
3120 09:07:37.217593 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_58 RESULT=pass
3122 09:07:37.263468 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_58 RESULT=pass>
3123 09:07:37.264443 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_58 RESULT=pass
3125 09:07:37.312670 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_58 RESULT=pass>
3126 09:07:37.313332 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_58 RESULT=pass
3128 09:07:37.368861 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_58 RESULT=pass>
3129 09:07:37.369596 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_58 RESULT=pass
3131 09:07:37.437394 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_58 RESULT=pass>
3132 09:07:37.438071 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_58 RESULT=pass
3134 09:07:37.492558 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_58 RESULT=pass>
3135 09:07:37.493216 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_58 RESULT=pass
3137 09:07:37.543469 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_57 RESULT=pass>
3138 09:07:37.544139 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_57 RESULT=pass
3140 09:07:37.608419 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_57 RESULT=pass>
3141 09:07:37.609094 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_57 RESULT=pass
3143 09:07:37.655217 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_57 RESULT=pass>
3144 09:07:37.655878 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_57 RESULT=pass
3146 09:07:38.635574 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_57 RESULT=pass>
3147 09:07:38.636267 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_57 RESULT=pass
3149 09:07:38.689067 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_57 RESULT=pass>
3150 09:07:38.689726 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_57 RESULT=pass
3152 09:07:38.742312 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_57 RESULT=pass>
3153 09:07:38.743231 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_57 RESULT=pass
3155 09:07:38.789057 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_57 RESULT=pass>
3156 09:07:38.789975 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_57 RESULT=pass
3158 09:07:38.841064 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_56 RESULT=pass>
3159 09:07:38.841882 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_56 RESULT=pass
3161 09:07:38.903218 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_56 RESULT=pass>
3162 09:07:38.904068 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_56 RESULT=pass
3164 09:07:38.952707 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_56 RESULT=pass>
3165 09:07:38.953501 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_56 RESULT=pass
3167 09:07:38.997023 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_56 RESULT=pass>
3168 09:07:38.997796 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_56 RESULT=pass
3170 09:07:39.045531 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_56 RESULT=pass>
3171 09:07:39.046310 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_56 RESULT=pass
3173 09:07:39.093741 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_56 RESULT=pass>
3174 09:07:39.094515 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_56 RESULT=pass
3176 09:07:39.137634 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_56 RESULT=pass>
3177 09:07:39.138406 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_56 RESULT=pass
3179 09:07:39.194408 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_55 RESULT=pass>
3180 09:07:39.195177 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_55 RESULT=pass
3182 09:07:39.246772 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_55 RESULT=pass>
3183 09:07:39.247582 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_55 RESULT=pass
3185 09:07:39.298013 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_55 RESULT=pass>
3186 09:07:39.298787 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_55 RESULT=pass
3188 09:07:39.347337 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_55 RESULT=pass>
3189 09:07:39.348116 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_55 RESULT=pass
3191 09:07:39.400089 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_55 RESULT=pass>
3192 09:07:39.400879 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_55 RESULT=pass
3194 09:07:39.453078 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_55 RESULT=pass>
3195 09:07:39.453846 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_55 RESULT=pass
3197 09:07:39.503168 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_55 RESULT=pass>
3198 09:07:39.503937 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_55 RESULT=pass
3200 09:07:39.545893 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_54 RESULT=pass>
3201 09:07:39.546654 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_54 RESULT=pass
3203 09:07:39.597859 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_54 RESULT=pass>
3204 09:07:39.598723 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_54 RESULT=pass
3206 09:07:39.648836 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_54 RESULT=pass>
3207 09:07:39.649625 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_54 RESULT=pass
3209 09:07:39.704395 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_54 RESULT=pass>
3210 09:07:39.705156 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_54 RESULT=pass
3212 09:07:39.754577 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_54 RESULT=pass>
3213 09:07:39.755368 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_54 RESULT=pass
3215 09:07:39.811689 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_54 RESULT=pass>
3216 09:07:39.812500 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_54 RESULT=pass
3218 09:07:39.863605 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_54 RESULT=pass>
3219 09:07:39.864430 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_54 RESULT=pass
3221 09:07:39.915216 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_53 RESULT=pass>
3222 09:07:39.916019 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_53 RESULT=pass
3224 09:07:39.963545 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_53 RESULT=pass>
3225 09:07:39.964349 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_53 RESULT=pass
3227 09:07:40.014285 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_53 RESULT=pass>
3228 09:07:40.015048 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_53 RESULT=pass
3230 09:07:40.063474 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_53 RESULT=pass>
3231 09:07:40.064283 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_53 RESULT=pass
3233 09:07:40.115784 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_53 RESULT=pass>
3234 09:07:40.116586 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_53 RESULT=pass
3236 09:07:40.164064 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_53 RESULT=pass>
3237 09:07:40.164840 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_53 RESULT=pass
3239 09:07:40.211799 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_53 RESULT=pass>
3240 09:07:40.212606 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_53 RESULT=pass
3242 09:07:40.262217 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_52 RESULT=pass>
3243 09:07:40.262993 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_52 RESULT=pass
3245 09:07:40.314186 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_52 RESULT=pass>
3246 09:07:40.314982 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_52 RESULT=pass
3248 09:07:40.362370 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_52 RESULT=pass>
3249 09:07:40.363141 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_52 RESULT=pass
3251 09:07:40.415964 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_52 RESULT=pass>
3252 09:07:40.416767 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_52 RESULT=pass
3254 09:07:40.463287 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_52 RESULT=pass>
3255 09:07:40.464093 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_52 RESULT=pass
3257 09:07:40.511524 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_52 RESULT=pass>
3258 09:07:40.512321 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_52 RESULT=pass
3260 09:07:40.559322 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_52 RESULT=pass>
3261 09:07:40.560082 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_52 RESULT=pass
3263 09:07:40.615230 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_51 RESULT=pass>
3264 09:07:40.616034 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_51 RESULT=pass
3266 09:07:40.662193 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_51 RESULT=pass>
3267 09:07:40.662946 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_51 RESULT=pass
3269 09:07:40.711329 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_51 RESULT=pass>
3270 09:07:40.712092 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_51 RESULT=pass
3272 09:07:40.766897 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_51 RESULT=pass>
3273 09:07:40.767740 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_51 RESULT=pass
3275 09:07:40.817554 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_51 RESULT=pass>
3276 09:07:40.818331 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_51 RESULT=pass
3278 09:07:40.871783 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_51 RESULT=pass>
3279 09:07:40.872660 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_51 RESULT=pass
3281 09:07:40.926024 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_51 RESULT=pass>
3282 09:07:40.926907 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_51 RESULT=pass
3284 09:07:40.974204 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_50 RESULT=pass>
3285 09:07:40.974987 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_50 RESULT=pass
3287 09:07:41.024213 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_50 RESULT=pass>
3288 09:07:41.024997 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_50 RESULT=pass
3290 09:07:41.076605 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_50 RESULT=pass>
3291 09:07:41.077485 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_50 RESULT=pass
3293 09:07:41.119953 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_50 RESULT=pass>
3294 09:07:41.120763 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_50 RESULT=pass
3296 09:07:41.171955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_50 RESULT=pass>
3297 09:07:41.172796 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_50 RESULT=pass
3299 09:07:41.223301 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_50 RESULT=pass>
3300 09:07:41.223935 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_50 RESULT=pass
3302 09:07:41.267256 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_50 RESULT=pass>
3303 09:07:41.267879 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_50 RESULT=pass
3305 09:07:41.311579 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_49 RESULT=pass>
3306 09:07:41.312192 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_49 RESULT=pass
3308 09:07:41.365759 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_49 RESULT=pass>
3309 09:07:41.366391 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_49 RESULT=pass
3311 09:07:41.411775 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_49 RESULT=pass>
3312 09:07:41.412711 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_49 RESULT=pass
3314 09:07:41.460461 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_49 RESULT=pass>
3315 09:07:41.461316 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_49 RESULT=pass
3317 09:07:41.520048 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_49 RESULT=pass>
3318 09:07:41.520927 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_49 RESULT=pass
3320 09:07:41.573664 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_49 RESULT=pass>
3321 09:07:41.574265 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_49 RESULT=pass
3323 09:07:41.625911 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_49 RESULT=pass>
3324 09:07:41.626789 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_49 RESULT=pass
3326 09:07:41.671582 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_48 RESULT=pass>
3327 09:07:41.672461 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_48 RESULT=pass
3329 09:07:41.722348 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_48 RESULT=pass>
3330 09:07:41.723112 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_48 RESULT=pass
3332 09:07:41.774684 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_48 RESULT=pass>
3333 09:07:41.775602 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_48 RESULT=pass
3335 09:07:41.817783 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_48 RESULT=pass>
3336 09:07:41.818560 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_48 RESULT=pass
3338 09:07:41.870258 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_48 RESULT=pass>
3339 09:07:41.871093 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_48 RESULT=pass
3341 09:07:41.925407 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_48 RESULT=pass>
3342 09:07:41.926234 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_48 RESULT=pass
3344 09:07:41.976190 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_48 RESULT=pass>
3345 09:07:41.977115 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_48 RESULT=pass
3347 09:07:42.035806 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_47 RESULT=pass>
3348 09:07:42.036654 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_47 RESULT=pass
3350 09:07:42.093985 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_47 RESULT=pass>
3351 09:07:42.094750 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_47 RESULT=pass
3353 09:07:42.140027 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_47 RESULT=pass>
3354 09:07:42.140842 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_47 RESULT=pass
3356 09:07:42.185641 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_47 RESULT=pass>
3357 09:07:42.186448 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_47 RESULT=pass
3359 09:07:42.230635 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_47 RESULT=pass>
3360 09:07:42.231452 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_47 RESULT=pass
3362 09:07:42.290536 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_47 RESULT=pass>
3363 09:07:42.291387 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_47 RESULT=pass
3365 09:07:42.336908 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_47 RESULT=pass>
3366 09:07:42.337711 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_47 RESULT=pass
3368 09:07:42.391718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_46 RESULT=pass>
3369 09:07:42.392590 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_46 RESULT=pass
3371 09:07:42.446867 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_46 RESULT=pass>
3372 09:07:42.447695 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_46 RESULT=pass
3374 09:07:42.494772 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_46 RESULT=pass>
3375 09:07:42.495587 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_46 RESULT=pass
3377 09:07:42.558790 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_46 RESULT=pass>
3378 09:07:42.559555 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_46 RESULT=pass
3380 09:07:42.605156 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_46 RESULT=pass>
3381 09:07:42.605968 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_46 RESULT=pass
3383 09:07:42.665013 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_46 RESULT=pass>
3384 09:07:42.665784 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_46 RESULT=pass
3386 09:07:42.717816 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_46 RESULT=pass>
3387 09:07:42.718661 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_46 RESULT=pass
3389 09:07:42.770620 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_45 RESULT=pass>
3390 09:07:42.771446 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_45 RESULT=pass
3392 09:07:42.816296 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_45 RESULT=pass>
3393 09:07:42.817068 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_45 RESULT=pass
3395 09:07:42.872518 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_45 RESULT=pass>
3396 09:07:42.873329 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_45 RESULT=pass
3398 09:07:42.919411 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_45 RESULT=pass>
3399 09:07:42.920202 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_45 RESULT=pass
3401 09:07:42.976585 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_45 RESULT=pass>
3402 09:07:42.977436 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_45 RESULT=pass
3404 09:07:43.030257 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_45 RESULT=pass>
3405 09:07:43.031087 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_45 RESULT=pass
3407 09:07:43.076783 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_45 RESULT=pass>
3408 09:07:43.077619 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_45 RESULT=pass
3410 09:07:43.128436 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_44 RESULT=pass>
3411 09:07:43.129271 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_44 RESULT=pass
3413 09:07:43.183487 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_44 RESULT=pass>
3414 09:07:43.184341 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_44 RESULT=pass
3416 09:07:43.236186 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_44 RESULT=pass>
3417 09:07:43.237001 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_44 RESULT=pass
3419 09:07:43.288078 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_44 RESULT=pass>
3420 09:07:43.288923 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_44 RESULT=pass
3422 09:07:43.334224 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_44 RESULT=pass>
3423 09:07:43.334981 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_44 RESULT=pass
3425 09:07:43.379671 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_44 RESULT=pass>
3426 09:07:43.380480 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_44 RESULT=pass
3428 09:07:43.434914 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_44 RESULT=pass>
3429 09:07:43.435757 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_44 RESULT=pass
3431 09:07:43.479111 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_43 RESULT=pass>
3432 09:07:43.479881 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_43 RESULT=pass
3434 09:07:43.525994 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_43 RESULT=pass>
3435 09:07:43.526846 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_43 RESULT=pass
3437 09:07:43.584391 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_43 RESULT=pass>
3438 09:07:43.585177 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_43 RESULT=pass
3440 09:07:43.635753 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_43 RESULT=pass>
3441 09:07:43.636656 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_43 RESULT=pass
3443 09:07:43.683957 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_43 RESULT=pass>
3444 09:07:43.684763 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_43 RESULT=pass
3446 09:07:43.739194 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_43 RESULT=pass>
3447 09:07:43.740014 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_43 RESULT=pass
3449 09:07:43.792003 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_43 RESULT=pass>
3450 09:07:43.792877 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_43 RESULT=pass
3452 09:07:43.846169 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_42 RESULT=pass>
3453 09:07:43.847007 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_42 RESULT=pass
3455 09:07:43.905376 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_42 RESULT=pass>
3456 09:07:43.906214 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_42 RESULT=pass
3458 09:07:43.956233 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_42 RESULT=pass>
3459 09:07:43.957019 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_42 RESULT=pass
3461 09:07:44.004360 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_42 RESULT=pass>
3462 09:07:44.005141 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_42 RESULT=pass
3464 09:07:44.048758 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_42 RESULT=pass>
3465 09:07:44.049528 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_42 RESULT=pass
3467 09:07:44.107014 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_42 RESULT=pass>
3468 09:07:44.107773 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_42 RESULT=pass
3470 09:07:44.157199 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_42 RESULT=pass>
3471 09:07:44.157968 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_42 RESULT=pass
3473 09:07:44.212376 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_41 RESULT=pass>
3474 09:07:44.213146 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_41 RESULT=pass
3476 09:07:44.257613 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_41 RESULT=pass>
3477 09:07:44.258426 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_41 RESULT=pass
3479 09:07:44.313836 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_41 RESULT=pass>
3480 09:07:44.314634 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_41 RESULT=pass
3482 09:07:44.364247 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_41 RESULT=pass>
3483 09:07:44.365018 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_41 RESULT=pass
3485 09:07:44.420373 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_41 RESULT=pass>
3486 09:07:44.421144 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_41 RESULT=pass
3488 09:07:44.470948 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_41 RESULT=pass>
3489 09:07:44.471809 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_41 RESULT=pass
3491 09:07:44.521067 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_41 RESULT=pass>
3492 09:07:44.521911 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_41 RESULT=pass
3494 09:07:44.568175 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_40 RESULT=pass>
3495 09:07:44.569003 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_40 RESULT=pass
3497 09:07:44.617193 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_40 RESULT=pass>
3498 09:07:44.618065 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_40 RESULT=pass
3500 09:07:44.672592 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_40 RESULT=pass>
3501 09:07:44.673443 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_40 RESULT=pass
3503 09:07:44.720240 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_40 RESULT=pass>
3504 09:07:44.721060 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_40 RESULT=pass
3506 09:07:44.768205 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_40 RESULT=pass>
3507 09:07:44.769004 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_40 RESULT=pass
3509 09:07:44.810764 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_40 RESULT=pass>
3510 09:07:44.811582 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_40 RESULT=pass
3512 09:07:44.862214 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_40 RESULT=pass>
3513 09:07:44.862999 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_40 RESULT=pass
3515 09:07:44.912423 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_39 RESULT=pass>
3516 09:07:44.913197 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_39 RESULT=pass
3518 09:07:44.961149 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_39 RESULT=pass>
3519 09:07:44.961980 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_39 RESULT=pass
3521 09:07:45.018512 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_39 RESULT=pass>
3522 09:07:45.019303 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_39 RESULT=pass
3524 09:07:45.079490 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_39 RESULT=pass>
3525 09:07:45.080307 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_39 RESULT=pass
3527 09:07:45.142449 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_39 RESULT=pass>
3528 09:07:45.143242 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_39 RESULT=pass
3530 09:07:45.197931 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_39 RESULT=pass>
3531 09:07:45.198715 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_39 RESULT=pass
3533 09:07:45.255731 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_39 RESULT=pass>
3534 09:07:45.256610 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_39 RESULT=pass
3536 09:07:45.309523 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_38 RESULT=pass>
3537 09:07:45.310512 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_38 RESULT=pass
3539 09:07:45.369821 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_38 RESULT=pass>
3540 09:07:45.370746 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_38 RESULT=pass
3542 09:07:45.423191 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_38 RESULT=pass>
3543 09:07:45.424116 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_38 RESULT=pass
3545 09:07:45.468863 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_38 RESULT=pass>
3546 09:07:45.469777 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_38 RESULT=pass
3548 09:07:45.517274 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_38 RESULT=pass>
3549 09:07:45.518199 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_38 RESULT=pass
3551 09:07:45.563462 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_38 RESULT=pass>
3552 09:07:45.564361 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_38 RESULT=pass
3554 09:07:45.618263 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_38 RESULT=pass>
3555 09:07:45.619068 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_38 RESULT=pass
3557 09:07:45.672982 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_37 RESULT=pass>
3558 09:07:45.673781 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_37 RESULT=pass
3560 09:07:45.733399 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_37 RESULT=pass>
3561 09:07:45.734186 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_37 RESULT=pass
3563 09:07:45.781533 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_37 RESULT=pass>
3564 09:07:45.782335 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_37 RESULT=pass
3566 09:07:45.832050 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_37 RESULT=pass>
3567 09:07:45.832909 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_37 RESULT=pass
3569 09:07:45.876376 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_37 RESULT=pass>
3570 09:07:45.877152 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_37 RESULT=pass
3572 09:07:45.928691 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_37 RESULT=pass>
3573 09:07:45.929512 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_37 RESULT=pass
3575 09:07:45.982077 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_37 RESULT=pass>
3576 09:07:45.982934 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_37 RESULT=pass
3578 09:07:46.027081 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_36 RESULT=pass>
3579 09:07:46.027867 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_36 RESULT=pass
3581 09:07:46.080299 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_36 RESULT=pass>
3582 09:07:46.081157 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_36 RESULT=pass
3584 09:07:46.124587 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_36 RESULT=pass>
3585 09:07:46.125359 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_36 RESULT=pass
3587 09:07:46.174577 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_36 RESULT=pass>
3588 09:07:46.175330 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_36 RESULT=pass
3590 09:07:46.224298 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_36 RESULT=pass>
3591 09:07:46.225054 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_36 RESULT=pass
3593 09:07:46.277019 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_36 RESULT=pass>
3594 09:07:46.277805 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_36 RESULT=pass
3596 09:07:46.325630 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_36 RESULT=pass>
3597 09:07:46.326421 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_36 RESULT=pass
3599 09:07:46.373043 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_35 RESULT=pass>
3600 09:07:46.373885 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_35 RESULT=pass
3602 09:07:46.424495 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_35 RESULT=pass>
3603 09:07:46.425331 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_35 RESULT=pass
3605 09:07:46.474616 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_35 RESULT=pass>
3606 09:07:46.475428 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_35 RESULT=pass
3608 09:07:46.528217 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_35 RESULT=pass>
3609 09:07:46.529018 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_35 RESULT=pass
3611 09:07:46.582433 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_35 RESULT=pass>
3612 09:07:46.583284 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_35 RESULT=pass
3614 09:07:46.634933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_35 RESULT=pass>
3615 09:07:46.635748 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_35 RESULT=pass
3617 09:07:46.689980 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_35 RESULT=pass>
3618 09:07:46.690828 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_35 RESULT=pass
3620 09:07:46.737847 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_34 RESULT=pass>
3621 09:07:46.738648 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_34 RESULT=pass
3623 09:07:46.790148 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_34 RESULT=pass>
3624 09:07:46.790941 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_34 RESULT=pass
3626 09:07:46.837644 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_34 RESULT=pass>
3627 09:07:46.838475 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_34 RESULT=pass
3629 09:07:46.890230 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_34 RESULT=pass>
3630 09:07:46.891090 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_34 RESULT=pass
3632 09:07:46.937613 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_34 RESULT=pass>
3633 09:07:46.938477 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_34 RESULT=pass
3635 09:07:46.988319 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_34 RESULT=pass>
3636 09:07:46.989121 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_34 RESULT=pass
3638 09:07:47.034061 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_34 RESULT=pass>
3639 09:07:47.034909 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_34 RESULT=pass
3641 09:07:47.083127 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_33 RESULT=pass>
3642 09:07:47.084046 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_33 RESULT=pass
3644 09:07:47.136445 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_33 RESULT=pass>
3645 09:07:47.137387 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_33 RESULT=pass
3647 09:07:47.186518 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_33 RESULT=pass>
3648 09:07:47.187433 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_33 RESULT=pass
3650 09:07:47.234950 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_33 RESULT=pass>
3651 09:07:47.235804 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_33 RESULT=pass
3653 09:07:47.287040 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_33 RESULT=pass>
3654 09:07:47.287660 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_33 RESULT=pass
3656 09:07:47.335564 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_33 RESULT=pass>
3657 09:07:47.336465 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_33 RESULT=pass
3659 09:07:47.387443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_33 RESULT=pass>
3660 09:07:47.388276 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_33 RESULT=pass
3662 09:07:47.437450 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_32 RESULT=pass>
3663 09:07:47.438255 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_32 RESULT=pass
3665 09:07:47.484529 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_32 RESULT=pass>
3666 09:07:47.485295 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_32 RESULT=pass
3668 09:07:47.540083 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_32 RESULT=pass>
3669 09:07:47.540878 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_32 RESULT=pass
3671 09:07:47.595273 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_32 RESULT=pass>
3672 09:07:47.596087 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_32 RESULT=pass
3674 09:07:47.648423 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_32 RESULT=pass>
3675 09:07:47.649192 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_32 RESULT=pass
3677 09:07:47.701245 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_32 RESULT=pass>
3678 09:07:47.702045 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_32 RESULT=pass
3680 09:07:47.756588 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_32 RESULT=pass>
3681 09:07:47.757387 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_32 RESULT=pass
3683 09:07:47.805235 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_31 RESULT=pass>
3684 09:07:47.805991 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_31 RESULT=pass
3686 09:07:47.858967 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_31 RESULT=pass>
3687 09:07:47.859782 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_31 RESULT=pass
3689 09:07:47.912821 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_31 RESULT=pass>
3690 09:07:47.913644 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_31 RESULT=pass
3692 09:07:47.966669 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_31 RESULT=pass>
3693 09:07:47.967440 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_31 RESULT=pass
3695 09:07:48.012651 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_31 RESULT=pass>
3696 09:07:48.013425 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_31 RESULT=pass
3698 09:07:48.062625 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_31 RESULT=pass>
3699 09:07:48.063390 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_31 RESULT=pass
3701 09:07:48.115776 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_31 RESULT=pass>
3702 09:07:48.116660 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_31 RESULT=pass
3704 09:07:48.164204 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_30 RESULT=pass>
3705 09:07:48.165067 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_30 RESULT=pass
3707 09:07:48.218501 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_30 RESULT=pass>
3708 09:07:48.219372 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_30 RESULT=pass
3710 09:07:48.264763 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_30 RESULT=pass>
3711 09:07:48.265592 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_30 RESULT=pass
3713 09:07:48.323255 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_30 RESULT=pass>
3714 09:07:48.324106 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_30 RESULT=pass
3716 09:07:48.374803 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_30 RESULT=pass>
3717 09:07:48.375657 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_30 RESULT=pass
3719 09:07:48.419773 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_30 RESULT=pass>
3720 09:07:48.420627 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_30 RESULT=pass
3722 09:07:48.467504 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_30 RESULT=pass>
3723 09:07:48.468560 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_30 RESULT=pass
3725 09:07:48.516524 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_29 RESULT=pass>
3726 09:07:48.517423 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_29 RESULT=pass
3728 09:07:48.569468 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_29 RESULT=pass>
3729 09:07:48.570295 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_29 RESULT=pass
3731 09:07:48.633315 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_29 RESULT=pass>
3732 09:07:48.634166 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_29 RESULT=pass
3734 09:07:48.700219 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_29 RESULT=pass>
3735 09:07:48.701046 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_29 RESULT=pass
3737 09:07:48.747442 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_29 RESULT=pass>
3738 09:07:48.748310 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_29 RESULT=pass
3740 09:07:48.795327 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_29 RESULT=pass>
3741 09:07:48.796202 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_29 RESULT=pass
3743 09:07:48.850752 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_29 RESULT=pass>
3744 09:07:48.851614 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_29 RESULT=pass
3746 09:07:48.896509 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_28 RESULT=pass>
3747 09:07:48.897405 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_28 RESULT=pass
3749 09:07:48.945285 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_28 RESULT=pass>
3750 09:07:48.946148 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_28 RESULT=pass
3752 09:07:48.998216 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_28 RESULT=pass>
3753 09:07:48.999227 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_28 RESULT=pass
3755 09:07:49.054829 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_28 RESULT=pass>
3756 09:07:49.055692 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_28 RESULT=pass
3758 09:07:49.101797 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_28 RESULT=pass>
3759 09:07:49.102657 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_28 RESULT=pass
3761 09:07:49.156557 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_28 RESULT=pass>
3762 09:07:49.157412 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_28 RESULT=pass
3764 09:07:49.215126 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_28 RESULT=pass>
3765 09:07:49.216029 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_28 RESULT=pass
3767 09:07:49.264323 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_27 RESULT=pass>
3768 09:07:49.265338 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_27 RESULT=pass
3770 09:07:49.312042 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_27 RESULT=pass>
3771 09:07:49.312971 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_27 RESULT=pass
3773 09:07:49.364799 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_27 RESULT=pass>
3774 09:07:49.365839 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_27 RESULT=pass
3776 09:07:49.416316 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_27 RESULT=pass>
3777 09:07:49.417212 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_27 RESULT=pass
3779 09:07:49.475759 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_27 RESULT=pass>
3780 09:07:49.476677 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_27 RESULT=pass
3782 09:07:49.521845 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_27 RESULT=pass>
3783 09:07:49.522766 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_27 RESULT=pass
3785 09:07:49.588543 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_27 RESULT=pass>
3786 09:07:49.589354 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_27 RESULT=pass
3788 09:07:49.638036 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_26 RESULT=pass>
3789 09:07:49.638893 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_26 RESULT=pass
3791 09:07:49.682730 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_26 RESULT=pass>
3792 09:07:49.683511 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_26 RESULT=pass
3794 09:07:49.729301 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_26 RESULT=skip>
3795 09:07:49.730088 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_26 RESULT=skip
3797 09:07:49.781214 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_26 RESULT=skip>
3798 09:07:49.782002 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_26 RESULT=skip
3800 09:07:49.825491 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_26 RESULT=skip>
3801 09:07:49.826337 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_26 RESULT=skip
3803 09:07:49.876426 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_26 RESULT=pass>
3804 09:07:49.877200 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_26 RESULT=pass
3806 09:07:49.924212 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_26 RESULT=pass>
3807 09:07:49.924996 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_26 RESULT=pass
3809 09:07:49.974422 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_25 RESULT=pass>
3810 09:07:49.975214 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_25 RESULT=pass
3812 09:07:50.034906 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_25 RESULT=pass>
3813 09:07:50.035686 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_25 RESULT=pass
3815 09:07:50.082389 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_25 RESULT=pass>
3816 09:07:50.083190 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_25 RESULT=pass
3818 09:07:50.140397 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_25 RESULT=skip>
3819 09:07:50.141192 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_25 RESULT=skip
3821 09:07:50.185571 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_25 RESULT=skip>
3822 09:07:50.186599 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_25 RESULT=skip
3824 09:07:50.243082 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_25 RESULT=pass>
3825 09:07:50.244060 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_25 RESULT=pass
3827 09:07:50.296963 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_25 RESULT=pass>
3828 09:07:50.297865 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_25 RESULT=pass
3830 09:07:50.348788 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_24 RESULT=pass>
3831 09:07:50.349661 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_24 RESULT=pass
3833 09:07:50.397669 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_24 RESULT=pass>
3834 09:07:50.398561 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_24 RESULT=pass
3836 09:07:50.450895 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_24 RESULT=skip>
3837 09:07:50.451918 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_24 RESULT=skip
3839 09:07:50.500534 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_24 RESULT=skip>
3840 09:07:50.501363 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_24 RESULT=skip
3842 09:07:50.546916 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_24 RESULT=skip>
3843 09:07:50.547751 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_24 RESULT=skip
3845 09:07:50.602742 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_24 RESULT=pass>
3846 09:07:50.603774 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_24 RESULT=pass
3848 09:07:50.660402 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_24 RESULT=pass>
3849 09:07:50.661399 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_24 RESULT=pass
3851 09:07:50.710404 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_23 RESULT=pass>
3852 09:07:50.711420 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_23 RESULT=pass
3854 09:07:50.765755 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_23 RESULT=pass>
3855 09:07:50.766793 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_23 RESULT=pass
3857 09:07:50.813455 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_23 RESULT=skip>
3858 09:07:50.814468 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_23 RESULT=skip
3860 09:07:50.869210 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_23 RESULT=skip>
3861 09:07:50.870260 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_23 RESULT=skip
3863 09:07:50.924537 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_23 RESULT=skip>
3864 09:07:50.925543 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_23 RESULT=skip
3866 09:07:50.980207 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_23 RESULT=pass>
3867 09:07:50.981315 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_23 RESULT=pass
3869 09:07:51.035509 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_23 RESULT=pass>
3870 09:07:51.036580 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_23 RESULT=pass
3872 09:07:51.089431 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_22 RESULT=pass>
3873 09:07:51.090469 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_22 RESULT=pass
3875 09:07:51.140117 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_22 RESULT=pass>
3876 09:07:51.141114 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_22 RESULT=pass
3878 09:07:51.188379 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_22 RESULT=pass>
3879 09:07:51.189151 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_22 RESULT=pass
3881 09:07:51.240678 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_22 RESULT=pass>
3882 09:07:51.241650 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_22 RESULT=pass
3884 09:07:51.292233 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_22 RESULT=pass>
3885 09:07:51.293069 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_22 RESULT=pass
3887 09:07:51.344773 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_22 RESULT=pass>
3888 09:07:51.345783 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_22 RESULT=pass
3890 09:07:51.396637 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_22 RESULT=pass>
3891 09:07:51.397860 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_22 RESULT=pass
3893 09:07:51.443617 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_21 RESULT=pass>
3894 09:07:51.444671 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_21 RESULT=pass
3896 09:07:51.502158 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_21 RESULT=pass>
3897 09:07:51.503170 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_21 RESULT=pass
3899 09:07:51.548212 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_21 RESULT=pass>
3900 09:07:51.549020 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_21 RESULT=pass
3902 09:07:51.597538 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_21 RESULT=pass>
3903 09:07:51.598550 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_21 RESULT=pass
3905 09:07:51.656304 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_21 RESULT=pass>
3906 09:07:51.657334 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_21 RESULT=pass
3908 09:07:51.703056 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_21 RESULT=pass>
3909 09:07:51.704059 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_21 RESULT=pass
3911 09:07:51.751537 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_21 RESULT=pass>
3912 09:07:51.752374 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_21 RESULT=pass
3914 09:07:51.809785 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_20 RESULT=pass>
3915 09:07:51.810818 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_20 RESULT=pass
3917 09:07:51.862840 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_20 RESULT=pass>
3918 09:07:51.863831 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_20 RESULT=pass
3920 09:07:51.918420 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_20 RESULT=pass>
3921 09:07:51.919473 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_20 RESULT=pass
3923 09:07:51.971172 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_20 RESULT=pass>
3924 09:07:51.972222 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_20 RESULT=pass
3926 09:07:52.028803 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_20 RESULT=pass>
3927 09:07:52.029818 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_20 RESULT=pass
3929 09:07:52.082003 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_20 RESULT=pass>
3930 09:07:52.083164 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_20 RESULT=pass
3932 09:07:52.142659 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_20 RESULT=pass>
3933 09:07:52.143480 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_20 RESULT=pass
3935 09:07:52.206585 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_19 RESULT=pass>
3936 09:07:52.207433 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_19 RESULT=pass
3938 09:07:52.258910 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_19 RESULT=pass>
3939 09:07:52.259924 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_19 RESULT=pass
3941 09:07:52.308730 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_19 RESULT=pass>
3942 09:07:52.309620 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_19 RESULT=pass
3944 09:07:52.376989 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_19 RESULT=pass>
3945 09:07:52.377837 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_19 RESULT=pass
3947 09:07:52.431553 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_19 RESULT=pass>
3948 09:07:52.432620 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_19 RESULT=pass
3950 09:07:52.484733 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_19 RESULT=pass>
3951 09:07:52.485687 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_19 RESULT=pass
3953 09:07:52.536516 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_19 RESULT=pass>
3954 09:07:52.537495 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_19 RESULT=pass
3956 09:07:52.592096 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_18 RESULT=pass>
3957 09:07:52.592900 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_18 RESULT=pass
3959 09:07:52.646943 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_18 RESULT=pass>
3960 09:07:52.647757 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_18 RESULT=pass
3962 09:07:52.700902 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_18 RESULT=pass>
3963 09:07:52.701681 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_18 RESULT=pass
3965 09:07:52.745797 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_18 RESULT=pass>
3966 09:07:52.746558 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_18 RESULT=pass
3968 09:07:52.812312 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_18 RESULT=pass>
3969 09:07:52.813143 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_18 RESULT=pass
3971 09:07:52.868984 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_18 RESULT=pass>
3972 09:07:52.869783 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_18 RESULT=pass
3974 09:07:52.919817 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_18 RESULT=pass>
3975 09:07:52.920703 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_18 RESULT=pass
3977 09:07:52.976512 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_17 RESULT=pass>
3978 09:07:52.977306 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_17 RESULT=pass
3980 09:07:53.026603 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_17 RESULT=pass>
3981 09:07:53.027403 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_17 RESULT=pass
3983 09:07:53.085427 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_17 RESULT=pass>
3984 09:07:53.086248 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_17 RESULT=pass
3986 09:07:53.128504 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_17 RESULT=pass>
3987 09:07:53.129323 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_17 RESULT=pass
3989 09:07:53.185156 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_17 RESULT=pass>
3990 09:07:53.185980 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_17 RESULT=pass
3992 09:07:53.234943 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_17 RESULT=pass>
3993 09:07:53.235741 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_17 RESULT=pass
3995 09:07:53.287930 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_17 RESULT=pass>
3996 09:07:53.289123 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_17 RESULT=pass
3998 09:07:53.342131 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_16 RESULT=pass>
3999 09:07:53.343143 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_16 RESULT=pass
4001 09:07:53.393182 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_16 RESULT=pass>
4002 09:07:53.394177 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_16 RESULT=pass
4004 09:07:53.451298 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_16 RESULT=pass>
4005 09:07:53.452384 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_16 RESULT=pass
4007 09:07:53.506666 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_16 RESULT=pass>
4008 09:07:53.507689 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_16 RESULT=pass
4010 09:07:53.558613 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_16 RESULT=pass>
4011 09:07:53.559568 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_16 RESULT=pass
4013 09:07:53.606429 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_16 RESULT=pass>
4014 09:07:53.607447 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_16 RESULT=pass
4016 09:07:53.654715 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_16 RESULT=pass>
4017 09:07:53.655703 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_16 RESULT=pass
4019 09:07:53.704044 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_15 RESULT=pass>
4020 09:07:53.705056 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_15 RESULT=pass
4022 09:07:53.755806 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_15 RESULT=pass>
4023 09:07:53.756655 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_15 RESULT=pass
4025 09:07:53.802393 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_15 RESULT=pass>
4026 09:07:53.803416 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_15 RESULT=pass
4028 09:07:53.856055 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_15 RESULT=pass>
4029 09:07:53.856851 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_15 RESULT=pass
4031 09:07:53.905088 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_15 RESULT=pass>
4032 09:07:53.905939 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_15 RESULT=pass
4034 09:07:53.950385 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_15 RESULT=pass>
4035 09:07:53.951380 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_15 RESULT=pass
4037 09:07:54.007518 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_15 RESULT=pass>
4038 09:07:54.008548 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_15 RESULT=pass
4040 09:07:54.059501 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_14 RESULT=pass>
4041 09:07:54.060512 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_14 RESULT=pass
4043 09:07:54.111507 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_14 RESULT=pass>
4044 09:07:54.112542 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_14 RESULT=pass
4046 09:07:54.159895 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_14 RESULT=pass>
4047 09:07:54.160720 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_14 RESULT=pass
4049 09:07:54.213010 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_14 RESULT=pass>
4050 09:07:54.214000 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_14 RESULT=pass
4052 09:07:54.263024 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_14 RESULT=pass>
4053 09:07:54.264016 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_14 RESULT=pass
4055 09:07:54.324651 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_14 RESULT=pass>
4056 09:07:54.325625 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_14 RESULT=pass
4058 09:07:54.382785 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_14 RESULT=pass>
4059 09:07:54.383744 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_14 RESULT=pass
4061 09:07:54.434833 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_13 RESULT=pass>
4062 09:07:54.435628 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_13 RESULT=pass
4064 09:07:54.487125 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_13 RESULT=pass>
4065 09:07:54.488114 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_13 RESULT=pass
4067 09:07:54.537982 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_13 RESULT=pass>
4068 09:07:54.538961 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_13 RESULT=pass
4070 09:07:54.584935 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_13 RESULT=pass>
4071 09:07:54.585928 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_13 RESULT=pass
4073 09:07:54.640151 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_13 RESULT=pass>
4074 09:07:54.641285 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_13 RESULT=pass
4076 09:07:54.689752 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_13 RESULT=pass>
4077 09:07:54.690583 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_13 RESULT=pass
4079 09:07:54.743940 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_13 RESULT=pass>
4080 09:07:54.744792 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_13 RESULT=pass
4082 09:07:54.794901 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_12 RESULT=pass>
4083 09:07:54.795727 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_12 RESULT=pass
4085 09:07:54.849820 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_12 RESULT=pass>
4086 09:07:54.850861 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_12 RESULT=pass
4088 09:07:54.904652 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_12 RESULT=pass>
4089 09:07:54.905808 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_12 RESULT=pass
4091 09:07:54.962498 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_12 RESULT=pass>
4092 09:07:54.963334 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_12 RESULT=pass
4094 09:07:55.018673 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_12 RESULT=pass>
4095 09:07:55.019472 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_12 RESULT=pass
4097 09:07:55.077357 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_12 RESULT=pass>
4098 09:07:55.078117 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_12 RESULT=pass
4100 09:07:55.128516 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_12 RESULT=pass>
4101 09:07:55.129305 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_12 RESULT=pass
4103 09:07:55.190469 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_11 RESULT=pass>
4104 09:07:55.191310 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_11 RESULT=pass
4106 09:07:55.242442 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_11 RESULT=pass>
4107 09:07:55.243263 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_11 RESULT=pass
4109 09:07:55.298696 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_11 RESULT=pass>
4110 09:07:55.299502 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_11 RESULT=pass
4112 09:07:55.347358 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_11 RESULT=pass>
4113 09:07:55.348204 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_11 RESULT=pass
4115 09:07:55.396979 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_11 RESULT=pass>
4116 09:07:55.397769 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_11 RESULT=pass
4118 09:07:55.447653 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_11 RESULT=pass>
4119 09:07:55.448464 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_11 RESULT=pass
4121 09:07:55.502289 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_11 RESULT=pass>
4122 09:07:55.503048 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_11 RESULT=pass
4124 09:07:55.551311 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_10 RESULT=pass>
4125 09:07:55.552068 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_10 RESULT=pass
4127 09:07:55.597216 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_10 RESULT=pass>
4128 09:07:55.597955 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_10 RESULT=pass
4130 09:07:55.645800 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_10 RESULT=pass>
4131 09:07:55.646555 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_10 RESULT=pass
4133 09:07:55.697784 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_10 RESULT=pass>
4134 09:07:55.698542 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_10 RESULT=pass
4136 09:07:55.751698 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_10 RESULT=pass>
4137 09:07:55.752502 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_10 RESULT=pass
4139 09:07:55.809023 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_10 RESULT=pass>
4140 09:07:55.809788 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_10 RESULT=pass
4142 09:07:55.854667 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_10 RESULT=pass>
4143 09:07:55.855436 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_10 RESULT=pass
4145 09:07:55.911737 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_9 RESULT=pass>
4146 09:07:55.912537 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_9 RESULT=pass
4148 09:07:55.960700 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_9 RESULT=pass>
4149 09:07:55.961523 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_9 RESULT=pass
4151 09:07:56.016823 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_9 RESULT=pass>
4152 09:07:56.017650 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_9 RESULT=pass
4154 09:07:56.063203 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_9 RESULT=pass>
4155 09:07:56.064044 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_9 RESULT=pass
4157 09:07:56.106958 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_9 RESULT=pass>
4158 09:07:56.107765 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_9 RESULT=pass
4160 09:07:56.151920 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_9 RESULT=pass>
4161 09:07:56.152714 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_9 RESULT=pass
4163 09:07:56.205444 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_9 RESULT=pass>
4164 09:07:56.206170 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_9 RESULT=pass
4166 09:07:56.257272 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_8 RESULT=pass>
4167 09:07:56.258020 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_8 RESULT=pass
4169 09:07:56.312502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_8 RESULT=pass>
4170 09:07:56.313237 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_8 RESULT=pass
4172 09:07:56.363013 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_8 RESULT=pass>
4173 09:07:56.363759 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_8 RESULT=pass
4175 09:07:56.413689 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_8 RESULT=pass>
4176 09:07:56.414416 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_8 RESULT=pass
4178 09:07:56.466049 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_8 RESULT=pass>
4179 09:07:56.466807 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_8 RESULT=pass
4181 09:07:56.519531 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_8 RESULT=pass>
4182 09:07:56.520306 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_8 RESULT=pass
4184 09:07:56.565422 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_8 RESULT=pass>
4185 09:07:56.566160 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_8 RESULT=pass
4187 09:07:56.612093 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_7 RESULT=pass>
4188 09:07:56.612827 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_7 RESULT=pass
4190 09:07:56.658081 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_7 RESULT=pass>
4191 09:07:56.658814 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_7 RESULT=pass
4193 09:07:56.710297 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_7 RESULT=pass>
4194 09:07:56.711036 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_7 RESULT=pass
4196 09:07:56.775623 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_7 RESULT=pass>
4197 09:07:56.776398 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_7 RESULT=pass
4199 09:07:56.837615 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_7 RESULT=pass>
4200 09:07:56.838359 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_7 RESULT=pass
4202 09:07:56.891370 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_7 RESULT=pass>
4203 09:07:56.892142 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_7 RESULT=pass
4205 09:07:56.942869 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_7 RESULT=pass>
4206 09:07:56.943646 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_7 RESULT=pass
4208 09:07:56.999647 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_6 RESULT=pass>
4209 09:07:57.000446 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_6 RESULT=pass
4211 09:07:57.045176 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_6 RESULT=pass>
4212 09:07:57.045918 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_6 RESULT=pass
4214 09:07:57.101680 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_6 RESULT=pass>
4215 09:07:57.102508 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_6 RESULT=pass
4217 09:07:57.151005 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_6 RESULT=pass>
4218 09:07:57.152625 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_6 RESULT=pass
4220 09:07:57.213588 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_6 RESULT=pass>
4221 09:07:57.214526 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_6 RESULT=pass
4223 09:07:57.268252 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_6 RESULT=pass>
4224 09:07:57.269211 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_6 RESULT=pass
4226 09:07:57.320993 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_6 RESULT=pass>
4227 09:07:57.321936 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_6 RESULT=pass
4229 09:07:57.375413 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_5 RESULT=pass>
4230 09:07:57.376384 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_5 RESULT=pass
4232 09:07:57.435909 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_5 RESULT=pass>
4233 09:07:57.436907 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_5 RESULT=pass
4235 09:07:57.484419 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_5 RESULT=pass>
4236 09:07:57.485331 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_5 RESULT=pass
4238 09:07:57.544251 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_5 RESULT=pass>
4239 09:07:57.545207 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_5 RESULT=pass
4241 09:07:57.596963 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_5 RESULT=pass>
4242 09:07:57.597911 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_5 RESULT=pass
4244 09:07:57.656740 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_5 RESULT=pass>
4245 09:07:57.657681 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_5 RESULT=pass
4247 09:07:57.715155 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_5 RESULT=pass>
4248 09:07:57.716176 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_5 RESULT=pass
4250 09:07:57.769292 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_4 RESULT=pass>
4251 09:07:57.770290 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_4 RESULT=pass
4253 09:07:57.826844 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_4 RESULT=pass>
4254 09:07:57.827924 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_4 RESULT=pass
4256 09:07:57.880040 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_4 RESULT=pass>
4257 09:07:57.881040 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_4 RESULT=pass
4259 09:07:57.933231 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_4 RESULT=pass>
4260 09:07:57.934576 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_4 RESULT=pass
4262 09:07:57.986878 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_4 RESULT=pass>
4263 09:07:57.987878 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_4 RESULT=pass
4265 09:07:58.033345 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_4 RESULT=pass>
4266 09:07:58.034314 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_4 RESULT=pass
4268 09:07:58.090224 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_4 RESULT=pass>
4269 09:07:58.091184 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_4 RESULT=pass
4271 09:07:58.135288 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_3 RESULT=pass>
4272 09:07:58.136240 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_3 RESULT=pass
4274 09:07:58.193709 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_3 RESULT=pass>
4275 09:07:58.194637 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_3 RESULT=pass
4277 09:07:58.253852 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_3 RESULT=pass>
4278 09:07:58.254799 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_3 RESULT=pass
4280 09:07:58.311262 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_3 RESULT=pass>
4281 09:07:58.312207 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_3 RESULT=pass
4283 09:07:58.365460 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_3 RESULT=pass>
4284 09:07:58.366408 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_3 RESULT=pass
4286 09:07:58.411526 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_3 RESULT=pass>
4287 09:07:58.412527 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_3 RESULT=pass
4289 09:07:58.463029 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_3 RESULT=pass>
4290 09:07:58.463962 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_3 RESULT=pass
4292 09:07:58.507121 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_2 RESULT=pass>
4293 09:07:58.508099 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_2 RESULT=pass
4295 09:07:58.557387 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_2 RESULT=pass>
4296 09:07:58.558337 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_2 RESULT=pass
4298 09:07:58.612336 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_2 RESULT=pass>
4299 09:07:58.613263 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_2 RESULT=pass
4301 09:07:58.664845 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_2 RESULT=pass>
4302 09:07:58.665796 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_2 RESULT=pass
4304 09:07:58.717844 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_2 RESULT=pass>
4305 09:07:58.718832 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_2 RESULT=pass
4307 09:07:58.772063 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_2 RESULT=pass>
4308 09:07:58.773060 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_2 RESULT=pass
4310 09:07:58.834397 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_2 RESULT=pass>
4311 09:07:58.835311 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_2 RESULT=pass
4313 09:07:58.899609 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_1 RESULT=pass>
4314 09:07:58.900600 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_1 RESULT=pass
4316 09:07:58.954639 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_1 RESULT=pass>
4317 09:07:58.955597 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_1 RESULT=pass
4319 09:07:59.012348 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_1 RESULT=pass>
4320 09:07:59.013122 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_1 RESULT=pass
4322 09:07:59.063002 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_1 RESULT=pass>
4323 09:07:59.063781 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_1 RESULT=pass
4325 09:07:59.109856 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_1 RESULT=pass>
4326 09:07:59.110608 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_1 RESULT=pass
4328 09:07:59.165789 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_1 RESULT=pass>
4329 09:07:59.166541 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_1 RESULT=pass
4331 09:07:59.222939 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_1 RESULT=pass>
4332 09:07:59.223694 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_1 RESULT=pass
4334 09:07:59.282344 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_0 RESULT=pass>
4335 09:07:59.283097 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_0 RESULT=pass
4337 09:07:59.330552 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_0 RESULT=pass>
4338 09:07:59.331305 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_0 RESULT=pass
4340 09:07:59.384714 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_0 RESULT=pass>
4341 09:07:59.385473 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_0 RESULT=pass
4343 09:07:59.432688 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_0 RESULT=pass>
4344 09:07:59.433441 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_0 RESULT=pass
4346 09:07:59.489542 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_0 RESULT=pass>
4347 09:07:59.490288 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_0 RESULT=pass
4349 09:07:59.541721 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_0 RESULT=pass>
4350 09:07:59.542463 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_0 RESULT=pass
4352 09:07:59.594323 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_0 RESULT=pass>
4353 09:07:59.595080 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_0 RESULT=pass
4355 09:07:59.641118 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test RESULT=pass
4357 09:07:59.643888 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test RESULT=pass>
4358 09:07:59.701824 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_5_0_CAPTURE RESULT=skip>
4359 09:07:59.702574 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_5_0_CAPTURE RESULT=skip
4361 09:07:59.759801 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_5_0_CAPTURE RESULT=skip>
4362 09:07:59.760576 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_5_0_CAPTURE RESULT=skip
4364 09:07:59.815520 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_5_0_CAPTURE RESULT=skip>
4365 09:07:59.816314 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_5_0_CAPTURE RESULT=skip
4367 09:07:59.864595 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_5_0_CAPTURE RESULT=skip>
4368 09:07:59.865336 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_5_0_CAPTURE RESULT=skip
4370 09:07:59.912195 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_5_0_CAPTURE RESULT=skip>
4371 09:07:59.912989 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_5_0_CAPTURE RESULT=skip
4373 09:07:59.958418 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_5_0_CAPTURE RESULT=skip>
4374 09:07:59.959202 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_5_0_CAPTURE RESULT=skip
4376 09:08:00.015799 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_5_0_CAPTURE RESULT=skip>
4377 09:08:00.016614 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_5_0_CAPTURE RESULT=skip
4379 09:08:00.068973 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_4_0_CAPTURE RESULT=skip>
4380 09:08:00.069747 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_4_0_CAPTURE RESULT=skip
4382 09:08:00.122150 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_4_0_CAPTURE RESULT=skip>
4383 09:08:00.123094 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_4_0_CAPTURE RESULT=skip
4385 09:08:00.175849 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_4_0_CAPTURE RESULT=skip>
4386 09:08:00.176652 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_4_0_CAPTURE RESULT=skip
4388 09:08:00.223583 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_4_0_CAPTURE RESULT=skip>
4389 09:08:00.224407 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_4_0_CAPTURE RESULT=skip
4391 09:08:00.276323 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_4_0_CAPTURE RESULT=skip>
4392 09:08:00.277092 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_4_0_CAPTURE RESULT=skip
4394 09:08:00.322255 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_4_0_CAPTURE RESULT=skip>
4395 09:08:00.323025 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_4_0_CAPTURE RESULT=skip
4397 09:08:00.377813 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_4_0_CAPTURE RESULT=skip>
4398 09:08:00.378596 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_4_0_CAPTURE RESULT=skip
4400 09:08:00.430308 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_3_0_CAPTURE RESULT=skip>
4401 09:08:00.431084 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_3_0_CAPTURE RESULT=skip
4403 09:08:00.478441 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_3_0_CAPTURE RESULT=skip>
4404 09:08:00.479191 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_3_0_CAPTURE RESULT=skip
4406 09:08:00.523534 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_3_0_CAPTURE RESULT=skip>
4407 09:08:00.524322 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_3_0_CAPTURE RESULT=skip
4409 09:08:00.578960 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_3_0_CAPTURE RESULT=skip>
4410 09:08:00.579728 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_3_0_CAPTURE RESULT=skip
4412 09:08:00.623755 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_3_0_CAPTURE RESULT=skip>
4413 09:08:00.624550 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_3_0_CAPTURE RESULT=skip
4415 09:08:00.670791 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_3_0_CAPTURE RESULT=skip>
4416 09:08:00.671561 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_3_0_CAPTURE RESULT=skip
4418 09:08:00.731695 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_3_0_CAPTURE RESULT=skip>
4419 09:08:00.732495 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_3_0_CAPTURE RESULT=skip
4421 09:08:00.786001 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_2_0_PLAYBACK RESULT=skip>
4422 09:08:00.786779 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_2_0_PLAYBACK RESULT=skip
4424 09:08:00.844108 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_2_0_PLAYBACK RESULT=skip>
4425 09:08:00.844992 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_2_0_PLAYBACK RESULT=skip
4427 09:08:00.900951 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_2_0_PLAYBACK RESULT=skip>
4428 09:08:00.902144 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_2_0_PLAYBACK RESULT=skip
4430 09:08:00.952768 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_2_0_PLAYBACK RESULT=skip>
4431 09:08:00.953689 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_2_0_PLAYBACK RESULT=skip
4433 09:08:01.006804 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_2_0_PLAYBACK RESULT=skip>
4434 09:08:01.007650 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_2_0_PLAYBACK RESULT=skip
4436 09:08:01.056222 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_2_0_PLAYBACK RESULT=skip>
4437 09:08:01.057060 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_2_0_PLAYBACK RESULT=skip
4439 09:08:01.101386 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_2_0_PLAYBACK RESULT=skip>
4440 09:08:01.102243 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_2_0_PLAYBACK RESULT=skip
4442 09:08:01.154120 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_1_0_PLAYBACK RESULT=skip>
4443 09:08:01.154972 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_1_0_PLAYBACK RESULT=skip
4445 09:08:01.205275 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_1_0_PLAYBACK RESULT=skip>
4446 09:08:01.206095 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_1_0_PLAYBACK RESULT=skip
4448 09:08:01.264154 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_1_0_PLAYBACK RESULT=skip>
4449 09:08:01.265206 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_1_0_PLAYBACK RESULT=skip
4451 09:08:01.317070 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_1_0_PLAYBACK RESULT=skip>
4452 09:08:01.317922 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_1_0_PLAYBACK RESULT=skip
4454 09:08:01.371504 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_1_0_PLAYBACK RESULT=skip>
4455 09:08:01.372460 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_1_0_PLAYBACK RESULT=skip
4457 09:08:01.429486 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_1_0_PLAYBACK RESULT=skip>
4458 09:08:01.430475 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_1_0_PLAYBACK RESULT=skip
4460 09:08:01.488802 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_1_0_PLAYBACK RESULT=skip>
4461 09:08:01.489747 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_1_0_PLAYBACK RESULT=skip
4463 09:08:01.538827 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_0_0_PLAYBACK RESULT=skip>
4464 09:08:01.539697 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_0_0_PLAYBACK RESULT=skip
4466 09:08:01.601587 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_0_0_PLAYBACK RESULT=skip>
4467 09:08:01.602539 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_0_0_PLAYBACK RESULT=skip
4469 09:08:01.656752 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_0_0_PLAYBACK RESULT=skip>
4470 09:08:01.657652 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_0_0_PLAYBACK RESULT=skip
4472 09:08:01.718209 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_0_0_PLAYBACK RESULT=skip>
4473 09:08:01.719158 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_0_0_PLAYBACK RESULT=skip
4475 09:08:01.776940 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_0_0_PLAYBACK RESULT=skip>
4476 09:08:01.777797 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_0_0_PLAYBACK RESULT=skip
4478 09:08:01.828159 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_0_0_PLAYBACK RESULT=skip>
4479 09:08:01.829110 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_0_0_PLAYBACK RESULT=skip
4481 09:08:01.880407 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_0_0_PLAYBACK RESULT=skip>
4482 09:08:01.881355 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_0_0_PLAYBACK RESULT=skip
4484 09:08:01.933370 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test RESULT=pass>
4485 09:08:01.934267 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test RESULT=pass
4487 09:08:01.995548 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_playback_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip>
4488 09:08:01.996510 Received signal: <TESTCASE> TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_playback_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip
4490 09:08:02.045569 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_capture_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip>
4491 09:08:02.046526 Received signal: <TESTCASE> TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_capture_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip
4493 09:08:02.100508 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_ni_capture_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip>
4494 09:08:02.101494 Received signal: <TESTCASE> TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_ni_capture_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip
4496 09:08:02.147544 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_ni_playback_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip>
4497 09:08:02.148371 Received signal: <TESTCASE> TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_ni_playback_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip
4499 09:08:02.208261 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_reset_ioctl_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip>
4500 09:08:02.208937 Received signal: <TESTCASE> TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_reset_ioctl_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip
4502 09:08:02.256698 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_test-pcmtest-driver RESULT=pass>
4503 09:08:02.257373 Received signal: <TESTCASE> TEST_CASE_ID=alsa_test-pcmtest-driver RESULT=pass
4505 09:08:02.309718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_utimer-test_global_wrong_timers_test RESULT=pass>
4506 09:08:02.310358 Received signal: <TESTCASE> TEST_CASE_ID=alsa_utimer-test_global_wrong_timers_test RESULT=pass
4508 09:08:02.364061 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_utimer-test_timer_f_utimer RESULT=fail>
4509 09:08:02.364697 Received signal: <TESTCASE> TEST_CASE_ID=alsa_utimer-test_timer_f_utimer RESULT=fail
4511 09:08:02.416157 Received signal: <TESTCASE> TEST_CASE_ID=alsa_utimer-test RESULT=fail
4513 09:08:02.421134 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_utimer-test RESULT=fail>
4514 09:08:02.421475 + set +x
4515 09:08:02.427140 <LAVA_SIGNAL_ENDRUN 1_kselftest-alsa 939161_1.6.2.4.5>
4516 09:08:02.427497 <LAVA_TEST_RUNNER EXIT>
4517 09:08:02.427948 Received signal: <ENDRUN> 1_kselftest-alsa 939161_1.6.2.4.5
4518 09:08:02.428268 Ending use of test pattern.
4519 09:08:02.428495 Ending test lava.1_kselftest-alsa (939161_1.6.2.4.5), duration 42.40
4521 09:08:02.429340 ok: lava_test_shell seems to have completed
4522 09:08:02.441042 alsa_mixer-test: pass
alsa_mixer-test_event_missing_LCALTA_0: pass
alsa_mixer-test_event_missing_LCALTA_1: pass
alsa_mixer-test_event_missing_LCALTA_10: pass
alsa_mixer-test_event_missing_LCALTA_11: pass
alsa_mixer-test_event_missing_LCALTA_12: pass
alsa_mixer-test_event_missing_LCALTA_13: pass
alsa_mixer-test_event_missing_LCALTA_14: pass
alsa_mixer-test_event_missing_LCALTA_15: pass
alsa_mixer-test_event_missing_LCALTA_16: pass
alsa_mixer-test_event_missing_LCALTA_17: pass
alsa_mixer-test_event_missing_LCALTA_18: pass
alsa_mixer-test_event_missing_LCALTA_19: pass
alsa_mixer-test_event_missing_LCALTA_2: pass
alsa_mixer-test_event_missing_LCALTA_20: pass
alsa_mixer-test_event_missing_LCALTA_21: pass
alsa_mixer-test_event_missing_LCALTA_22: pass
alsa_mixer-test_event_missing_LCALTA_23: pass
alsa_mixer-test_event_missing_LCALTA_24: pass
alsa_mixer-test_event_missing_LCALTA_25: pass
alsa_mixer-test_event_missing_LCALTA_26: pass
alsa_mixer-test_event_missing_LCALTA_27: pass
alsa_mixer-test_event_missing_LCALTA_28: pass
alsa_mixer-test_event_missing_LCALTA_29: pass
alsa_mixer-test_event_missing_LCALTA_3: pass
alsa_mixer-test_event_missing_LCALTA_30: pass
alsa_mixer-test_event_missing_LCALTA_31: pass
alsa_mixer-test_event_missing_LCALTA_32: pass
alsa_mixer-test_event_missing_LCALTA_33: pass
alsa_mixer-test_event_missing_LCALTA_34: pass
alsa_mixer-test_event_missing_LCALTA_35: pass
alsa_mixer-test_event_missing_LCALTA_36: pass
alsa_mixer-test_event_missing_LCALTA_37: pass
alsa_mixer-test_event_missing_LCALTA_38: pass
alsa_mixer-test_event_missing_LCALTA_39: pass
alsa_mixer-test_event_missing_LCALTA_4: pass
alsa_mixer-test_event_missing_LCALTA_40: pass
alsa_mixer-test_event_missing_LCALTA_41: pass
alsa_mixer-test_event_missing_LCALTA_42: pass
alsa_mixer-test_event_missing_LCALTA_43: pass
alsa_mixer-test_event_missing_LCALTA_44: pass
alsa_mixer-test_event_missing_LCALTA_45: pass
alsa_mixer-test_event_missing_LCALTA_46: pass
alsa_mixer-test_event_missing_LCALTA_47: pass
alsa_mixer-test_event_missing_LCALTA_48: pass
alsa_mixer-test_event_missing_LCALTA_49: pass
alsa_mixer-test_event_missing_LCALTA_5: pass
alsa_mixer-test_event_missing_LCALTA_50: pass
alsa_mixer-test_event_missing_LCALTA_51: pass
alsa_mixer-test_event_missing_LCALTA_52: pass
alsa_mixer-test_event_missing_LCALTA_53: pass
alsa_mixer-test_event_missing_LCALTA_54: pass
alsa_mixer-test_event_missing_LCALTA_55: pass
alsa_mixer-test_event_missing_LCALTA_56: pass
alsa_mixer-test_event_missing_LCALTA_57: pass
alsa_mixer-test_event_missing_LCALTA_58: pass
alsa_mixer-test_event_missing_LCALTA_59: pass
alsa_mixer-test_event_missing_LCALTA_6: pass
alsa_mixer-test_event_missing_LCALTA_60: pass
alsa_mixer-test_event_missing_LCALTA_7: pass
alsa_mixer-test_event_missing_LCALTA_8: pass
alsa_mixer-test_event_missing_LCALTA_9: pass
alsa_mixer-test_event_spurious_LCALTA_0: pass
alsa_mixer-test_event_spurious_LCALTA_1: pass
alsa_mixer-test_event_spurious_LCALTA_10: pass
alsa_mixer-test_event_spurious_LCALTA_11: pass
alsa_mixer-test_event_spurious_LCALTA_12: pass
alsa_mixer-test_event_spurious_LCALTA_13: pass
alsa_mixer-test_event_spurious_LCALTA_14: pass
alsa_mixer-test_event_spurious_LCALTA_15: pass
alsa_mixer-test_event_spurious_LCALTA_16: pass
alsa_mixer-test_event_spurious_LCALTA_17: pass
alsa_mixer-test_event_spurious_LCALTA_18: pass
alsa_mixer-test_event_spurious_LCALTA_19: pass
alsa_mixer-test_event_spurious_LCALTA_2: pass
alsa_mixer-test_event_spurious_LCALTA_20: pass
alsa_mixer-test_event_spurious_LCALTA_21: pass
alsa_mixer-test_event_spurious_LCALTA_22: pass
alsa_mixer-test_event_spurious_LCALTA_23: pass
alsa_mixer-test_event_spurious_LCALTA_24: pass
alsa_mixer-test_event_spurious_LCALTA_25: pass
alsa_mixer-test_event_spurious_LCALTA_26: pass
alsa_mixer-test_event_spurious_LCALTA_27: pass
alsa_mixer-test_event_spurious_LCALTA_28: pass
alsa_mixer-test_event_spurious_LCALTA_29: pass
alsa_mixer-test_event_spurious_LCALTA_3: pass
alsa_mixer-test_event_spurious_LCALTA_30: pass
alsa_mixer-test_event_spurious_LCALTA_31: pass
alsa_mixer-test_event_spurious_LCALTA_32: pass
alsa_mixer-test_event_spurious_LCALTA_33: pass
alsa_mixer-test_event_spurious_LCALTA_34: pass
alsa_mixer-test_event_spurious_LCALTA_35: pass
alsa_mixer-test_event_spurious_LCALTA_36: pass
alsa_mixer-test_event_spurious_LCALTA_37: pass
alsa_mixer-test_event_spurious_LCALTA_38: pass
alsa_mixer-test_event_spurious_LCALTA_39: pass
alsa_mixer-test_event_spurious_LCALTA_4: pass
alsa_mixer-test_event_spurious_LCALTA_40: pass
alsa_mixer-test_event_spurious_LCALTA_41: pass
alsa_mixer-test_event_spurious_LCALTA_42: pass
alsa_mixer-test_event_spurious_LCALTA_43: pass
alsa_mixer-test_event_spurious_LCALTA_44: pass
alsa_mixer-test_event_spurious_LCALTA_45: pass
alsa_mixer-test_event_spurious_LCALTA_46: pass
alsa_mixer-test_event_spurious_LCALTA_47: pass
alsa_mixer-test_event_spurious_LCALTA_48: pass
alsa_mixer-test_event_spurious_LCALTA_49: pass
alsa_mixer-test_event_spurious_LCALTA_5: pass
alsa_mixer-test_event_spurious_LCALTA_50: pass
alsa_mixer-test_event_spurious_LCALTA_51: pass
alsa_mixer-test_event_spurious_LCALTA_52: pass
alsa_mixer-test_event_spurious_LCALTA_53: pass
alsa_mixer-test_event_spurious_LCALTA_54: pass
alsa_mixer-test_event_spurious_LCALTA_55: pass
alsa_mixer-test_event_spurious_LCALTA_56: pass
alsa_mixer-test_event_spurious_LCALTA_57: pass
alsa_mixer-test_event_spurious_LCALTA_58: pass
alsa_mixer-test_event_spurious_LCALTA_59: pass
alsa_mixer-test_event_spurious_LCALTA_6: pass
alsa_mixer-test_event_spurious_LCALTA_60: pass
alsa_mixer-test_event_spurious_LCALTA_7: pass
alsa_mixer-test_event_spurious_LCALTA_8: pass
alsa_mixer-test_event_spurious_LCALTA_9: pass
alsa_mixer-test_get_value_LCALTA_0: pass
alsa_mixer-test_get_value_LCALTA_1: pass
alsa_mixer-test_get_value_LCALTA_10: pass
alsa_mixer-test_get_value_LCALTA_11: pass
alsa_mixer-test_get_value_LCALTA_12: pass
alsa_mixer-test_get_value_LCALTA_13: pass
alsa_mixer-test_get_value_LCALTA_14: pass
alsa_mixer-test_get_value_LCALTA_15: pass
alsa_mixer-test_get_value_LCALTA_16: pass
alsa_mixer-test_get_value_LCALTA_17: pass
alsa_mixer-test_get_value_LCALTA_18: pass
alsa_mixer-test_get_value_LCALTA_19: pass
alsa_mixer-test_get_value_LCALTA_2: pass
alsa_mixer-test_get_value_LCALTA_20: pass
alsa_mixer-test_get_value_LCALTA_21: pass
alsa_mixer-test_get_value_LCALTA_22: pass
alsa_mixer-test_get_value_LCALTA_23: pass
alsa_mixer-test_get_value_LCALTA_24: pass
alsa_mixer-test_get_value_LCALTA_25: pass
alsa_mixer-test_get_value_LCALTA_26: pass
alsa_mixer-test_get_value_LCALTA_27: pass
alsa_mixer-test_get_value_LCALTA_28: pass
alsa_mixer-test_get_value_LCALTA_29: pass
alsa_mixer-test_get_value_LCALTA_3: pass
alsa_mixer-test_get_value_LCALTA_30: pass
alsa_mixer-test_get_value_LCALTA_31: pass
alsa_mixer-test_get_value_LCALTA_32: pass
alsa_mixer-test_get_value_LCALTA_33: pass
alsa_mixer-test_get_value_LCALTA_34: pass
alsa_mixer-test_get_value_LCALTA_35: pass
alsa_mixer-test_get_value_LCALTA_36: pass
alsa_mixer-test_get_value_LCALTA_37: pass
alsa_mixer-test_get_value_LCALTA_38: pass
alsa_mixer-test_get_value_LCALTA_39: pass
alsa_mixer-test_get_value_LCALTA_4: pass
alsa_mixer-test_get_value_LCALTA_40: pass
alsa_mixer-test_get_value_LCALTA_41: pass
alsa_mixer-test_get_value_LCALTA_42: pass
alsa_mixer-test_get_value_LCALTA_43: pass
alsa_mixer-test_get_value_LCALTA_44: pass
alsa_mixer-test_get_value_LCALTA_45: pass
alsa_mixer-test_get_value_LCALTA_46: pass
alsa_mixer-test_get_value_LCALTA_47: pass
alsa_mixer-test_get_value_LCALTA_48: pass
alsa_mixer-test_get_value_LCALTA_49: pass
alsa_mixer-test_get_value_LCALTA_5: pass
alsa_mixer-test_get_value_LCALTA_50: pass
alsa_mixer-test_get_value_LCALTA_51: pass
alsa_mixer-test_get_value_LCALTA_52: pass
alsa_mixer-test_get_value_LCALTA_53: pass
alsa_mixer-test_get_value_LCALTA_54: pass
alsa_mixer-test_get_value_LCALTA_55: pass
alsa_mixer-test_get_value_LCALTA_56: pass
alsa_mixer-test_get_value_LCALTA_57: pass
alsa_mixer-test_get_value_LCALTA_58: pass
alsa_mixer-test_get_value_LCALTA_59: pass
alsa_mixer-test_get_value_LCALTA_6: pass
alsa_mixer-test_get_value_LCALTA_60: pass
alsa_mixer-test_get_value_LCALTA_7: pass
alsa_mixer-test_get_value_LCALTA_8: pass
alsa_mixer-test_get_value_LCALTA_9: pass
alsa_mixer-test_name_LCALTA_0: pass
alsa_mixer-test_name_LCALTA_1: pass
alsa_mixer-test_name_LCALTA_10: pass
alsa_mixer-test_name_LCALTA_11: pass
alsa_mixer-test_name_LCALTA_12: pass
alsa_mixer-test_name_LCALTA_13: pass
alsa_mixer-test_name_LCALTA_14: pass
alsa_mixer-test_name_LCALTA_15: pass
alsa_mixer-test_name_LCALTA_16: pass
alsa_mixer-test_name_LCALTA_17: pass
alsa_mixer-test_name_LCALTA_18: pass
alsa_mixer-test_name_LCALTA_19: pass
alsa_mixer-test_name_LCALTA_2: pass
alsa_mixer-test_name_LCALTA_20: pass
alsa_mixer-test_name_LCALTA_21: pass
alsa_mixer-test_name_LCALTA_22: pass
alsa_mixer-test_name_LCALTA_23: pass
alsa_mixer-test_name_LCALTA_24: pass
alsa_mixer-test_name_LCALTA_25: pass
alsa_mixer-test_name_LCALTA_26: pass
alsa_mixer-test_name_LCALTA_27: pass
alsa_mixer-test_name_LCALTA_28: pass
alsa_mixer-test_name_LCALTA_29: pass
alsa_mixer-test_name_LCALTA_3: pass
alsa_mixer-test_name_LCALTA_30: pass
alsa_mixer-test_name_LCALTA_31: pass
alsa_mixer-test_name_LCALTA_32: pass
alsa_mixer-test_name_LCALTA_33: pass
alsa_mixer-test_name_LCALTA_34: pass
alsa_mixer-test_name_LCALTA_35: pass
alsa_mixer-test_name_LCALTA_36: pass
alsa_mixer-test_name_LCALTA_37: pass
alsa_mixer-test_name_LCALTA_38: pass
alsa_mixer-test_name_LCALTA_39: pass
alsa_mixer-test_name_LCALTA_4: pass
alsa_mixer-test_name_LCALTA_40: pass
alsa_mixer-test_name_LCALTA_41: pass
alsa_mixer-test_name_LCALTA_42: pass
alsa_mixer-test_name_LCALTA_43: pass
alsa_mixer-test_name_LCALTA_44: pass
alsa_mixer-test_name_LCALTA_45: pass
alsa_mixer-test_name_LCALTA_46: pass
alsa_mixer-test_name_LCALTA_47: pass
alsa_mixer-test_name_LCALTA_48: pass
alsa_mixer-test_name_LCALTA_49: pass
alsa_mixer-test_name_LCALTA_5: pass
alsa_mixer-test_name_LCALTA_50: pass
alsa_mixer-test_name_LCALTA_51: pass
alsa_mixer-test_name_LCALTA_52: pass
alsa_mixer-test_name_LCALTA_53: pass
alsa_mixer-test_name_LCALTA_54: pass
alsa_mixer-test_name_LCALTA_55: pass
alsa_mixer-test_name_LCALTA_56: pass
alsa_mixer-test_name_LCALTA_57: pass
alsa_mixer-test_name_LCALTA_58: pass
alsa_mixer-test_name_LCALTA_59: pass
alsa_mixer-test_name_LCALTA_6: pass
alsa_mixer-test_name_LCALTA_60: pass
alsa_mixer-test_name_LCALTA_7: pass
alsa_mixer-test_name_LCALTA_8: pass
alsa_mixer-test_name_LCALTA_9: pass
alsa_mixer-test_write_default_LCALTA_0: pass
alsa_mixer-test_write_default_LCALTA_1: pass
alsa_mixer-test_write_default_LCALTA_10: pass
alsa_mixer-test_write_default_LCALTA_11: pass
alsa_mixer-test_write_default_LCALTA_12: pass
alsa_mixer-test_write_default_LCALTA_13: pass
alsa_mixer-test_write_default_LCALTA_14: pass
alsa_mixer-test_write_default_LCALTA_15: pass
alsa_mixer-test_write_default_LCALTA_16: pass
alsa_mixer-test_write_default_LCALTA_17: pass
alsa_mixer-test_write_default_LCALTA_18: pass
alsa_mixer-test_write_default_LCALTA_19: pass
alsa_mixer-test_write_default_LCALTA_2: pass
alsa_mixer-test_write_default_LCALTA_20: pass
alsa_mixer-test_write_default_LCALTA_21: pass
alsa_mixer-test_write_default_LCALTA_22: pass
alsa_mixer-test_write_default_LCALTA_23: skip
alsa_mixer-test_write_default_LCALTA_24: skip
alsa_mixer-test_write_default_LCALTA_25: pass
alsa_mixer-test_write_default_LCALTA_26: skip
alsa_mixer-test_write_default_LCALTA_27: pass
alsa_mixer-test_write_default_LCALTA_28: pass
alsa_mixer-test_write_default_LCALTA_29: pass
alsa_mixer-test_write_default_LCALTA_3: pass
alsa_mixer-test_write_default_LCALTA_30: pass
alsa_mixer-test_write_default_LCALTA_31: pass
alsa_mixer-test_write_default_LCALTA_32: pass
alsa_mixer-test_write_default_LCALTA_33: pass
alsa_mixer-test_write_default_LCALTA_34: pass
alsa_mixer-test_write_default_LCALTA_35: pass
alsa_mixer-test_write_default_LCALTA_36: pass
alsa_mixer-test_write_default_LCALTA_37: pass
alsa_mixer-test_write_default_LCALTA_38: pass
alsa_mixer-test_write_default_LCALTA_39: pass
alsa_mixer-test_write_default_LCALTA_4: pass
alsa_mixer-test_write_default_LCALTA_40: pass
alsa_mixer-test_write_default_LCALTA_41: pass
alsa_mixer-test_write_default_LCALTA_42: pass
alsa_mixer-test_write_default_LCALTA_43: pass
alsa_mixer-test_write_default_LCALTA_44: pass
alsa_mixer-test_write_default_LCALTA_45: pass
alsa_mixer-test_write_default_LCALTA_46: pass
alsa_mixer-test_write_default_LCALTA_47: pass
alsa_mixer-test_write_default_LCALTA_48: pass
alsa_mixer-test_write_default_LCALTA_49: pass
alsa_mixer-test_write_default_LCALTA_5: pass
alsa_mixer-test_write_default_LCALTA_50: pass
alsa_mixer-test_write_default_LCALTA_51: pass
alsa_mixer-test_write_default_LCALTA_52: pass
alsa_mixer-test_write_default_LCALTA_53: pass
alsa_mixer-test_write_default_LCALTA_54: pass
alsa_mixer-test_write_default_LCALTA_55: pass
alsa_mixer-test_write_default_LCALTA_56: pass
alsa_mixer-test_write_default_LCALTA_57: pass
alsa_mixer-test_write_default_LCALTA_58: pass
alsa_mixer-test_write_default_LCALTA_59: pass
alsa_mixer-test_write_default_LCALTA_6: pass
alsa_mixer-test_write_default_LCALTA_60: pass
alsa_mixer-test_write_default_LCALTA_7: pass
alsa_mixer-test_write_default_LCALTA_8: pass
alsa_mixer-test_write_default_LCALTA_9: pass
alsa_mixer-test_write_invalid_LCALTA_0: pass
alsa_mixer-test_write_invalid_LCALTA_1: pass
alsa_mixer-test_write_invalid_LCALTA_10: pass
alsa_mixer-test_write_invalid_LCALTA_11: pass
alsa_mixer-test_write_invalid_LCALTA_12: pass
alsa_mixer-test_write_invalid_LCALTA_13: pass
alsa_mixer-test_write_invalid_LCALTA_14: pass
alsa_mixer-test_write_invalid_LCALTA_15: pass
alsa_mixer-test_write_invalid_LCALTA_16: pass
alsa_mixer-test_write_invalid_LCALTA_17: pass
alsa_mixer-test_write_invalid_LCALTA_18: pass
alsa_mixer-test_write_invalid_LCALTA_19: pass
alsa_mixer-test_write_invalid_LCALTA_2: pass
alsa_mixer-test_write_invalid_LCALTA_20: pass
alsa_mixer-test_write_invalid_LCALTA_21: pass
alsa_mixer-test_write_invalid_LCALTA_22: pass
alsa_mixer-test_write_invalid_LCALTA_23: skip
alsa_mixer-test_write_invalid_LCALTA_24: skip
alsa_mixer-test_write_invalid_LCALTA_25: skip
alsa_mixer-test_write_invalid_LCALTA_26: skip
alsa_mixer-test_write_invalid_LCALTA_27: pass
alsa_mixer-test_write_invalid_LCALTA_28: pass
alsa_mixer-test_write_invalid_LCALTA_29: pass
alsa_mixer-test_write_invalid_LCALTA_3: pass
alsa_mixer-test_write_invalid_LCALTA_30: pass
alsa_mixer-test_write_invalid_LCALTA_31: pass
alsa_mixer-test_write_invalid_LCALTA_32: pass
alsa_mixer-test_write_invalid_LCALTA_33: pass
alsa_mixer-test_write_invalid_LCALTA_34: pass
alsa_mixer-test_write_invalid_LCALTA_35: pass
alsa_mixer-test_write_invalid_LCALTA_36: pass
alsa_mixer-test_write_invalid_LCALTA_37: pass
alsa_mixer-test_write_invalid_LCALTA_38: pass
alsa_mixer-test_write_invalid_LCALTA_39: pass
alsa_mixer-test_write_invalid_LCALTA_4: pass
alsa_mixer-test_write_invalid_LCALTA_40: pass
alsa_mixer-test_write_invalid_LCALTA_41: pass
alsa_mixer-test_write_invalid_LCALTA_42: pass
alsa_mixer-test_write_invalid_LCALTA_43: pass
alsa_mixer-test_write_invalid_LCALTA_44: pass
alsa_mixer-test_write_invalid_LCALTA_45: pass
alsa_mixer-test_write_invalid_LCALTA_46: pass
alsa_mixer-test_write_invalid_LCALTA_47: pass
alsa_mixer-test_write_invalid_LCALTA_48: pass
alsa_mixer-test_write_invalid_LCALTA_49: pass
alsa_mixer-test_write_invalid_LCALTA_5: pass
alsa_mixer-test_write_invalid_LCALTA_50: pass
alsa_mixer-test_write_invalid_LCALTA_51: pass
alsa_mixer-test_write_invalid_LCALTA_52: pass
alsa_mixer-test_write_invalid_LCALTA_53: pass
alsa_mixer-test_write_invalid_LCALTA_54: pass
alsa_mixer-test_write_invalid_LCALTA_55: pass
alsa_mixer-test_write_invalid_LCALTA_56: pass
alsa_mixer-test_write_invalid_LCALTA_57: pass
alsa_mixer-test_write_invalid_LCALTA_58: pass
alsa_mixer-test_write_invalid_LCALTA_59: pass
alsa_mixer-test_write_invalid_LCALTA_6: pass
alsa_mixer-test_write_invalid_LCALTA_60: pass
alsa_mixer-test_write_invalid_LCALTA_7: pass
alsa_mixer-test_write_invalid_LCALTA_8: pass
alsa_mixer-test_write_invalid_LCALTA_9: pass
alsa_mixer-test_write_valid_LCALTA_0: pass
alsa_mixer-test_write_valid_LCALTA_1: pass
alsa_mixer-test_write_valid_LCALTA_10: pass
alsa_mixer-test_write_valid_LCALTA_11: pass
alsa_mixer-test_write_valid_LCALTA_12: pass
alsa_mixer-test_write_valid_LCALTA_13: pass
alsa_mixer-test_write_valid_LCALTA_14: pass
alsa_mixer-test_write_valid_LCALTA_15: pass
alsa_mixer-test_write_valid_LCALTA_16: pass
alsa_mixer-test_write_valid_LCALTA_17: pass
alsa_mixer-test_write_valid_LCALTA_18: pass
alsa_mixer-test_write_valid_LCALTA_19: pass
alsa_mixer-test_write_valid_LCALTA_2: pass
alsa_mixer-test_write_valid_LCALTA_20: pass
alsa_mixer-test_write_valid_LCALTA_21: pass
alsa_mixer-test_write_valid_LCALTA_22: pass
alsa_mixer-test_write_valid_LCALTA_23: skip
alsa_mixer-test_write_valid_LCALTA_24: skip
alsa_mixer-test_write_valid_LCALTA_25: skip
alsa_mixer-test_write_valid_LCALTA_26: skip
alsa_mixer-test_write_valid_LCALTA_27: pass
alsa_mixer-test_write_valid_LCALTA_28: pass
alsa_mixer-test_write_valid_LCALTA_29: pass
alsa_mixer-test_write_valid_LCALTA_3: pass
alsa_mixer-test_write_valid_LCALTA_30: pass
alsa_mixer-test_write_valid_LCALTA_31: pass
alsa_mixer-test_write_valid_LCALTA_32: pass
alsa_mixer-test_write_valid_LCALTA_33: pass
alsa_mixer-test_write_valid_LCALTA_34: pass
alsa_mixer-test_write_valid_LCALTA_35: pass
alsa_mixer-test_write_valid_LCALTA_36: pass
alsa_mixer-test_write_valid_LCALTA_37: pass
alsa_mixer-test_write_valid_LCALTA_38: pass
alsa_mixer-test_write_valid_LCALTA_39: pass
alsa_mixer-test_write_valid_LCALTA_4: pass
alsa_mixer-test_write_valid_LCALTA_40: pass
alsa_mixer-test_write_valid_LCALTA_41: pass
alsa_mixer-test_write_valid_LCALTA_42: pass
alsa_mixer-test_write_valid_LCALTA_43: pass
alsa_mixer-test_write_valid_LCALTA_44: pass
alsa_mixer-test_write_valid_LCALTA_45: pass
alsa_mixer-test_write_valid_LCALTA_46: pass
alsa_mixer-test_write_valid_LCALTA_47: pass
alsa_mixer-test_write_valid_LCALTA_48: pass
alsa_mixer-test_write_valid_LCALTA_49: pass
alsa_mixer-test_write_valid_LCALTA_5: pass
alsa_mixer-test_write_valid_LCALTA_50: pass
alsa_mixer-test_write_valid_LCALTA_51: pass
alsa_mixer-test_write_valid_LCALTA_52: pass
alsa_mixer-test_write_valid_LCALTA_53: pass
alsa_mixer-test_write_valid_LCALTA_54: pass
alsa_mixer-test_write_valid_LCALTA_55: pass
alsa_mixer-test_write_valid_LCALTA_56: pass
alsa_mixer-test_write_valid_LCALTA_57: pass
alsa_mixer-test_write_valid_LCALTA_58: pass
alsa_mixer-test_write_valid_LCALTA_59: pass
alsa_mixer-test_write_valid_LCALTA_6: pass
alsa_mixer-test_write_valid_LCALTA_60: pass
alsa_mixer-test_write_valid_LCALTA_7: pass
alsa_mixer-test_write_valid_LCALTA_8: pass
alsa_mixer-test_write_valid_LCALTA_9: pass
alsa_pcm-test: pass
alsa_pcm-test_default_time1_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time1_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time1_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time1_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time1_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time1_LCALTA_5_0_CAPTURE: skip
alsa_pcm-test_default_time2_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time2_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time2_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time2_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time2_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time2_LCALTA_5_0_CAPTURE: skip
alsa_pcm-test_default_time3_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time3_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time3_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time3_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time3_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time3_LCALTA_5_0_CAPTURE: skip
alsa_pcm-test_default_time4_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time4_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time4_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time4_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time4_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time4_LCALTA_5_0_CAPTURE: skip
alsa_pcm-test_default_time5_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time5_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time5_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time5_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time5_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time5_LCALTA_5_0_CAPTURE: skip
alsa_pcm-test_default_time6_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time6_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time6_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time6_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time6_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time6_LCALTA_5_0_CAPTURE: skip
alsa_pcm-test_default_time7_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time7_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time7_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time7_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time7_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time7_LCALTA_5_0_CAPTURE: skip
alsa_test-pcmtest-driver: pass
alsa_test-pcmtest-driver_pcmtest_capture_Can_t_read_patterns_Probably_module_isn_t_loaded: skip
alsa_test-pcmtest-driver_pcmtest_ni_capture_Can_t_read_patterns_Probably_module_isn_t_loaded: skip
alsa_test-pcmtest-driver_pcmtest_ni_playback_Can_t_read_patterns_Probably_module_isn_t_loaded: skip
alsa_test-pcmtest-driver_pcmtest_playback_Can_t_read_patterns_Probably_module_isn_t_loaded: skip
alsa_test-pcmtest-driver_pcmtest_reset_ioctl_Can_t_read_patterns_Probably_module_isn_t_loaded: skip
alsa_utimer-test: fail
alsa_utimer-test_global_wrong_timers_test: pass
alsa_utimer-test_timer_f_utimer: fail
shardfile-alsa: pass
4523 09:08:02.442087 end: 3.1 lava-test-shell (duration 00:00:43) [common]
4524 09:08:02.442420 end: 3 lava-test-retry (duration 00:00:43) [common]
4525 09:08:02.442742 start: 4 finalize (timeout 00:06:02) [common]
4526 09:08:02.443096 start: 4.1 power-off (timeout 00:00:30) [common]
4527 09:08:02.443618 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
4528 09:08:02.477124 >> OK - accepted request
4529 09:08:02.479339 Returned 0 in 0 seconds
4530 09:08:02.580286 end: 4.1 power-off (duration 00:00:00) [common]
4532 09:08:02.581393 start: 4.2 read-feedback (timeout 00:06:01) [common]
4533 09:08:02.582083 Listened to connection for namespace 'common' for up to 1s
4534 09:08:03.582982 Finalising connection for namespace 'common'
4535 09:08:03.583504 Disconnecting from shell: Finalise
4536 09:08:03.583809 / #
4537 09:08:03.684505 end: 4.2 read-feedback (duration 00:00:01) [common]
4538 09:08:03.685024 end: 4 finalize (duration 00:00:01) [common]
4539 09:08:03.685423 Cleaning after the job
4540 09:08:03.685813 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/939161/tftp-deploy-2ufez62e/ramdisk
4541 09:08:03.690599 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/939161/tftp-deploy-2ufez62e/kernel
4542 09:08:03.705981 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/939161/tftp-deploy-2ufez62e/dtb
4543 09:08:03.706936 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/939161/tftp-deploy-2ufez62e/nfsrootfs
4544 09:08:03.741990 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/939161/tftp-deploy-2ufez62e/modules
4545 09:08:03.749619 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/939161
4546 09:08:07.944188 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/939161
4547 09:08:07.944757 Job finished correctly