Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 09:15:44.100802 lava-dispatcher, installed at version: 2024.01
2 09:15:44.101602 start: 0 validate
3 09:15:44.102063 Start time: 2024-11-05 09:15:44.102034+00:00 (UTC)
4 09:15:44.102616 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 09:15:44.103160 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-gst-fluster%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 09:15:44.138192 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 09:15:44.138741 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fpending-fixes%2Fv6.12-rc6-192-g566383b19a748%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 09:15:44.168520 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 09:15:44.169311 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fpending-fixes%2Fv6.12-rc6-192-g566383b19a748%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 09:15:44.199503 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 09:15:44.200034 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-gst-fluster%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 09:15:44.229607 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 09:15:44.230116 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fpending-fixes%2Fv6.12-rc6-192-g566383b19a748%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
14 09:15:44.266753 validate duration: 0.16
16 09:15:44.267728 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 09:15:44.268101 start: 1.1 download-retry (timeout 00:10:00) [common]
18 09:15:44.268494 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 09:15:44.269123 Not decompressing ramdisk as can be used compressed.
20 09:15:44.269594 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-gst-fluster/20240313.0/arm64/initrd.cpio.gz
21 09:15:44.269896 saving as /var/lib/lava/dispatcher/tmp/939177/tftp-deploy-vnuf9uja/ramdisk/initrd.cpio.gz
22 09:15:44.270206 total size: 5628140 (5 MB)
23 09:15:44.306454 progress 0 % (0 MB)
24 09:15:44.310838 progress 5 % (0 MB)
25 09:15:44.315637 progress 10 % (0 MB)
26 09:15:44.319538 progress 15 % (0 MB)
27 09:15:44.324211 progress 20 % (1 MB)
28 09:15:44.328540 progress 25 % (1 MB)
29 09:15:44.332920 progress 30 % (1 MB)
30 09:15:44.337254 progress 35 % (1 MB)
31 09:15:44.340993 progress 40 % (2 MB)
32 09:15:44.345057 progress 45 % (2 MB)
33 09:15:44.348701 progress 50 % (2 MB)
34 09:15:44.352764 progress 55 % (2 MB)
35 09:15:44.356763 progress 60 % (3 MB)
36 09:15:44.360393 progress 65 % (3 MB)
37 09:15:44.364475 progress 70 % (3 MB)
38 09:15:44.368290 progress 75 % (4 MB)
39 09:15:44.372786 progress 80 % (4 MB)
40 09:15:44.376743 progress 85 % (4 MB)
41 09:15:44.381183 progress 90 % (4 MB)
42 09:15:44.385294 progress 95 % (5 MB)
43 09:15:44.388802 progress 100 % (5 MB)
44 09:15:44.389501 5 MB downloaded in 0.12 s (45.00 MB/s)
45 09:15:44.390074 end: 1.1.1 http-download (duration 00:00:00) [common]
47 09:15:44.390990 end: 1.1 download-retry (duration 00:00:00) [common]
48 09:15:44.391357 start: 1.2 download-retry (timeout 00:10:00) [common]
49 09:15:44.391684 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 09:15:44.392233 downloading http://storage.kernelci.org/next/pending-fixes/v6.12-rc6-192-g566383b19a748/arm64/defconfig/gcc-12/kernel/Image
51 09:15:44.392519 saving as /var/lib/lava/dispatcher/tmp/939177/tftp-deploy-vnuf9uja/kernel/Image
52 09:15:44.392748 total size: 45715968 (43 MB)
53 09:15:44.392995 No compression specified
54 09:15:44.426785 progress 0 % (0 MB)
55 09:15:44.462892 progress 5 % (2 MB)
56 09:15:44.498153 progress 10 % (4 MB)
57 09:15:44.533678 progress 15 % (6 MB)
58 09:15:44.568816 progress 20 % (8 MB)
59 09:15:44.603720 progress 25 % (10 MB)
60 09:15:44.638328 progress 30 % (13 MB)
61 09:15:44.673549 progress 35 % (15 MB)
62 09:15:44.708663 progress 40 % (17 MB)
63 09:15:44.742719 progress 45 % (19 MB)
64 09:15:44.777860 progress 50 % (21 MB)
65 09:15:44.812537 progress 55 % (24 MB)
66 09:15:44.848025 progress 60 % (26 MB)
67 09:15:44.882545 progress 65 % (28 MB)
68 09:15:44.917319 progress 70 % (30 MB)
69 09:15:44.952419 progress 75 % (32 MB)
70 09:15:44.986925 progress 80 % (34 MB)
71 09:15:45.021510 progress 85 % (37 MB)
72 09:15:45.055659 progress 90 % (39 MB)
73 09:15:45.090035 progress 95 % (41 MB)
74 09:15:45.123744 progress 100 % (43 MB)
75 09:15:45.124401 43 MB downloaded in 0.73 s (59.59 MB/s)
76 09:15:45.124949 end: 1.2.1 http-download (duration 00:00:01) [common]
78 09:15:45.126021 end: 1.2 download-retry (duration 00:00:01) [common]
79 09:15:45.126371 start: 1.3 download-retry (timeout 00:09:59) [common]
80 09:15:45.126698 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 09:15:45.127249 downloading http://storage.kernelci.org/next/pending-fixes/v6.12-rc6-192-g566383b19a748/arm64/defconfig/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
82 09:15:45.127596 saving as /var/lib/lava/dispatcher/tmp/939177/tftp-deploy-vnuf9uja/dtb/meson-g12b-a311d-libretech-cc.dtb
83 09:15:45.127852 total size: 54703 (0 MB)
84 09:15:45.128139 No compression specified
85 09:15:45.166343 progress 59 % (0 MB)
86 09:15:45.167232 progress 100 % (0 MB)
87 09:15:45.167832 0 MB downloaded in 0.04 s (1.31 MB/s)
88 09:15:45.168433 end: 1.3.1 http-download (duration 00:00:00) [common]
90 09:15:45.169366 end: 1.3 download-retry (duration 00:00:00) [common]
91 09:15:45.169687 start: 1.4 download-retry (timeout 00:09:59) [common]
92 09:15:45.169997 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 09:15:45.170494 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-gst-fluster/20240313.0/arm64/full.rootfs.tar.xz
94 09:15:45.170780 saving as /var/lib/lava/dispatcher/tmp/939177/tftp-deploy-vnuf9uja/nfsrootfs/full.rootfs.tar
95 09:15:45.171032 total size: 474398908 (452 MB)
96 09:15:45.171288 Using unxz to decompress xz
97 09:15:45.203816 progress 0 % (0 MB)
98 09:15:46.306698 progress 5 % (22 MB)
99 09:15:47.810908 progress 10 % (45 MB)
100 09:15:48.279312 progress 15 % (67 MB)
101 09:15:49.182602 progress 20 % (90 MB)
102 09:15:49.750454 progress 25 % (113 MB)
103 09:15:50.168770 progress 30 % (135 MB)
104 09:15:50.791757 progress 35 % (158 MB)
105 09:15:51.787475 progress 40 % (181 MB)
106 09:15:52.616200 progress 45 % (203 MB)
107 09:15:53.166220 progress 50 % (226 MB)
108 09:15:53.827160 progress 55 % (248 MB)
109 09:15:55.066173 progress 60 % (271 MB)
110 09:15:56.528562 progress 65 % (294 MB)
111 09:15:58.181982 progress 70 % (316 MB)
112 09:16:01.380229 progress 75 % (339 MB)
113 09:16:03.820115 progress 80 % (361 MB)
114 09:16:06.716910 progress 85 % (384 MB)
115 09:16:09.866771 progress 90 % (407 MB)
116 09:16:13.063337 progress 95 % (429 MB)
117 09:16:16.236030 progress 100 % (452 MB)
118 09:16:16.250043 452 MB downloaded in 31.08 s (14.56 MB/s)
119 09:16:16.250954 end: 1.4.1 http-download (duration 00:00:31) [common]
121 09:16:16.252692 end: 1.4 download-retry (duration 00:00:31) [common]
122 09:16:16.253285 start: 1.5 download-retry (timeout 00:09:28) [common]
123 09:16:16.253807 start: 1.5.1 http-download (timeout 00:09:28) [common]
124 09:16:16.254584 downloading http://storage.kernelci.org/next/pending-fixes/v6.12-rc6-192-g566383b19a748/arm64/defconfig/gcc-12/modules.tar.xz
125 09:16:16.255035 saving as /var/lib/lava/dispatcher/tmp/939177/tftp-deploy-vnuf9uja/modules/modules.tar
126 09:16:16.255438 total size: 11615948 (11 MB)
127 09:16:16.255852 Using unxz to decompress xz
128 09:16:16.303016 progress 0 % (0 MB)
129 09:16:16.371803 progress 5 % (0 MB)
130 09:16:16.449018 progress 10 % (1 MB)
131 09:16:16.548745 progress 15 % (1 MB)
132 09:16:16.644459 progress 20 % (2 MB)
133 09:16:16.725849 progress 25 % (2 MB)
134 09:16:16.803870 progress 30 % (3 MB)
135 09:16:16.884911 progress 35 % (3 MB)
136 09:16:16.959216 progress 40 % (4 MB)
137 09:16:17.036861 progress 45 % (5 MB)
138 09:16:17.123430 progress 50 % (5 MB)
139 09:16:17.203304 progress 55 % (6 MB)
140 09:16:17.290735 progress 60 % (6 MB)
141 09:16:17.373104 progress 65 % (7 MB)
142 09:16:17.454759 progress 70 % (7 MB)
143 09:16:17.533986 progress 75 % (8 MB)
144 09:16:17.618613 progress 80 % (8 MB)
145 09:16:17.699115 progress 85 % (9 MB)
146 09:16:17.782601 progress 90 % (10 MB)
147 09:16:17.856499 progress 95 % (10 MB)
148 09:16:17.933567 progress 100 % (11 MB)
149 09:16:17.947034 11 MB downloaded in 1.69 s (6.55 MB/s)
150 09:16:17.948049 end: 1.5.1 http-download (duration 00:00:02) [common]
152 09:16:17.950139 end: 1.5 download-retry (duration 00:00:02) [common]
153 09:16:17.950731 start: 1.6 prepare-tftp-overlay (timeout 00:09:26) [common]
154 09:16:17.951395 start: 1.6.1 extract-nfsrootfs (timeout 00:09:26) [common]
155 09:16:34.547773 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/939177/extract-nfsrootfs-rr91m4uv
156 09:16:34.548414 end: 1.6.1 extract-nfsrootfs (duration 00:00:17) [common]
157 09:16:34.548703 start: 1.6.2 lava-overlay (timeout 00:09:10) [common]
158 09:16:34.549320 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/939177/lava-overlay-ja7qjvcz
159 09:16:34.549746 makedir: /var/lib/lava/dispatcher/tmp/939177/lava-overlay-ja7qjvcz/lava-939177/bin
160 09:16:34.550068 makedir: /var/lib/lava/dispatcher/tmp/939177/lava-overlay-ja7qjvcz/lava-939177/tests
161 09:16:34.550382 makedir: /var/lib/lava/dispatcher/tmp/939177/lava-overlay-ja7qjvcz/lava-939177/results
162 09:16:34.550716 Creating /var/lib/lava/dispatcher/tmp/939177/lava-overlay-ja7qjvcz/lava-939177/bin/lava-add-keys
163 09:16:34.551279 Creating /var/lib/lava/dispatcher/tmp/939177/lava-overlay-ja7qjvcz/lava-939177/bin/lava-add-sources
164 09:16:34.551809 Creating /var/lib/lava/dispatcher/tmp/939177/lava-overlay-ja7qjvcz/lava-939177/bin/lava-background-process-start
165 09:16:34.552333 Creating /var/lib/lava/dispatcher/tmp/939177/lava-overlay-ja7qjvcz/lava-939177/bin/lava-background-process-stop
166 09:16:34.552858 Creating /var/lib/lava/dispatcher/tmp/939177/lava-overlay-ja7qjvcz/lava-939177/bin/lava-common-functions
167 09:16:34.553343 Creating /var/lib/lava/dispatcher/tmp/939177/lava-overlay-ja7qjvcz/lava-939177/bin/lava-echo-ipv4
168 09:16:34.553811 Creating /var/lib/lava/dispatcher/tmp/939177/lava-overlay-ja7qjvcz/lava-939177/bin/lava-install-packages
169 09:16:34.554288 Creating /var/lib/lava/dispatcher/tmp/939177/lava-overlay-ja7qjvcz/lava-939177/bin/lava-installed-packages
170 09:16:34.554777 Creating /var/lib/lava/dispatcher/tmp/939177/lava-overlay-ja7qjvcz/lava-939177/bin/lava-os-build
171 09:16:34.555281 Creating /var/lib/lava/dispatcher/tmp/939177/lava-overlay-ja7qjvcz/lava-939177/bin/lava-probe-channel
172 09:16:34.555757 Creating /var/lib/lava/dispatcher/tmp/939177/lava-overlay-ja7qjvcz/lava-939177/bin/lava-probe-ip
173 09:16:34.556256 Creating /var/lib/lava/dispatcher/tmp/939177/lava-overlay-ja7qjvcz/lava-939177/bin/lava-target-ip
174 09:16:34.556727 Creating /var/lib/lava/dispatcher/tmp/939177/lava-overlay-ja7qjvcz/lava-939177/bin/lava-target-mac
175 09:16:34.557193 Creating /var/lib/lava/dispatcher/tmp/939177/lava-overlay-ja7qjvcz/lava-939177/bin/lava-target-storage
176 09:16:34.557664 Creating /var/lib/lava/dispatcher/tmp/939177/lava-overlay-ja7qjvcz/lava-939177/bin/lava-test-case
177 09:16:34.558130 Creating /var/lib/lava/dispatcher/tmp/939177/lava-overlay-ja7qjvcz/lava-939177/bin/lava-test-event
178 09:16:34.558609 Creating /var/lib/lava/dispatcher/tmp/939177/lava-overlay-ja7qjvcz/lava-939177/bin/lava-test-feedback
179 09:16:34.559101 Creating /var/lib/lava/dispatcher/tmp/939177/lava-overlay-ja7qjvcz/lava-939177/bin/lava-test-raise
180 09:16:34.559643 Creating /var/lib/lava/dispatcher/tmp/939177/lava-overlay-ja7qjvcz/lava-939177/bin/lava-test-reference
181 09:16:34.560152 Creating /var/lib/lava/dispatcher/tmp/939177/lava-overlay-ja7qjvcz/lava-939177/bin/lava-test-runner
182 09:16:34.560637 Creating /var/lib/lava/dispatcher/tmp/939177/lava-overlay-ja7qjvcz/lava-939177/bin/lava-test-set
183 09:16:34.561102 Creating /var/lib/lava/dispatcher/tmp/939177/lava-overlay-ja7qjvcz/lava-939177/bin/lava-test-shell
184 09:16:34.561572 Updating /var/lib/lava/dispatcher/tmp/939177/lava-overlay-ja7qjvcz/lava-939177/bin/lava-install-packages (oe)
185 09:16:34.562096 Updating /var/lib/lava/dispatcher/tmp/939177/lava-overlay-ja7qjvcz/lava-939177/bin/lava-installed-packages (oe)
186 09:16:34.562528 Creating /var/lib/lava/dispatcher/tmp/939177/lava-overlay-ja7qjvcz/lava-939177/environment
187 09:16:34.562886 LAVA metadata
188 09:16:34.563141 - LAVA_JOB_ID=939177
189 09:16:34.563356 - LAVA_DISPATCHER_IP=192.168.6.2
190 09:16:34.563708 start: 1.6.2.1 ssh-authorize (timeout 00:09:10) [common]
191 09:16:34.564668 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
192 09:16:34.564973 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:10) [common]
193 09:16:34.565179 skipped lava-vland-overlay
194 09:16:34.565421 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
195 09:16:34.565675 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:10) [common]
196 09:16:34.565892 skipped lava-multinode-overlay
197 09:16:34.566132 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
198 09:16:34.566381 start: 1.6.2.4 test-definition (timeout 00:09:10) [common]
199 09:16:34.566626 Loading test definitions
200 09:16:34.566898 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:10) [common]
201 09:16:34.567116 Using /lava-939177 at stage 0
202 09:16:34.568272 uuid=939177_1.6.2.4.1 testdef=None
203 09:16:34.568577 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
204 09:16:34.568836 start: 1.6.2.4.2 test-overlay (timeout 00:09:10) [common]
205 09:16:34.570533 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
207 09:16:34.571317 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:10) [common]
208 09:16:34.573441 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
210 09:16:34.574265 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:10) [common]
211 09:16:34.576306 runner path: /var/lib/lava/dispatcher/tmp/939177/lava-overlay-ja7qjvcz/lava-939177/0/tests/0_v4l2-decoder-conformance-h264 test_uuid 939177_1.6.2.4.1
212 09:16:34.576879 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
214 09:16:34.577641 Creating lava-test-runner.conf files
215 09:16:34.577842 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/939177/lava-overlay-ja7qjvcz/lava-939177/0 for stage 0
216 09:16:34.578179 - 0_v4l2-decoder-conformance-h264
217 09:16:34.578513 end: 1.6.2.4 test-definition (duration 00:00:00) [common]
218 09:16:34.578784 start: 1.6.2.5 compress-overlay (timeout 00:09:10) [common]
219 09:16:34.600053 end: 1.6.2.5 compress-overlay (duration 00:00:00) [common]
220 09:16:34.600417 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:09:10) [common]
221 09:16:34.600673 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
222 09:16:34.600936 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
223 09:16:34.601196 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:10) [common]
224 09:16:35.216013 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:01) [common]
225 09:16:35.216590 start: 1.6.4 extract-modules (timeout 00:09:09) [common]
226 09:16:35.216901 extracting modules file /var/lib/lava/dispatcher/tmp/939177/tftp-deploy-vnuf9uja/modules/modules.tar to /var/lib/lava/dispatcher/tmp/939177/extract-nfsrootfs-rr91m4uv
227 09:16:36.860777 extracting modules file /var/lib/lava/dispatcher/tmp/939177/tftp-deploy-vnuf9uja/modules/modules.tar to /var/lib/lava/dispatcher/tmp/939177/extract-overlay-ramdisk-23b7z_ht/ramdisk
228 09:16:38.550040 end: 1.6.4 extract-modules (duration 00:00:03) [common]
229 09:16:38.550625 start: 1.6.5 apply-overlay-tftp (timeout 00:09:06) [common]
230 09:16:38.550963 [common] Applying overlay to NFS
231 09:16:38.551227 [common] Applying overlay /var/lib/lava/dispatcher/tmp/939177/compress-overlay-d0yzq3n5/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/939177/extract-nfsrootfs-rr91m4uv
232 09:16:38.586854 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
233 09:16:38.587364 start: 1.6.6 prepare-kernel (timeout 00:09:06) [common]
234 09:16:38.587697 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:09:06) [common]
235 09:16:38.587977 Converting downloaded kernel to a uImage
236 09:16:38.588408 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/939177/tftp-deploy-vnuf9uja/kernel/Image /var/lib/lava/dispatcher/tmp/939177/tftp-deploy-vnuf9uja/kernel/uImage
237 09:16:39.099505 output: Image Name:
238 09:16:39.099928 output: Created: Tue Nov 5 09:16:38 2024
239 09:16:39.100178 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
240 09:16:39.100385 output: Data Size: 45715968 Bytes = 44644.50 KiB = 43.60 MiB
241 09:16:39.100587 output: Load Address: 01080000
242 09:16:39.100787 output: Entry Point: 01080000
243 09:16:39.100983 output:
244 09:16:39.101314 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:01) [common]
245 09:16:39.101579 end: 1.6.6 prepare-kernel (duration 00:00:01) [common]
246 09:16:39.101847 start: 1.6.7 configure-preseed-file (timeout 00:09:05) [common]
247 09:16:39.102101 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
248 09:16:39.102355 start: 1.6.8 compress-ramdisk (timeout 00:09:05) [common]
249 09:16:39.102609 Building ramdisk /var/lib/lava/dispatcher/tmp/939177/extract-overlay-ramdisk-23b7z_ht/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/939177/extract-overlay-ramdisk-23b7z_ht/ramdisk
250 09:16:41.258143 >> 166830 blocks
251 09:16:49.966137 Adding RAMdisk u-boot header.
252 09:16:49.966583 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/939177/extract-overlay-ramdisk-23b7z_ht/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/939177/extract-overlay-ramdisk-23b7z_ht/ramdisk.cpio.gz.uboot
253 09:16:50.218930 output: Image Name:
254 09:16:50.219355 output: Created: Tue Nov 5 09:16:49 2024
255 09:16:50.219570 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
256 09:16:50.219778 output: Data Size: 23432315 Bytes = 22883.12 KiB = 22.35 MiB
257 09:16:50.220017 output: Load Address: 00000000
258 09:16:50.220467 output: Entry Point: 00000000
259 09:16:50.220908 output:
260 09:16:50.221989 rename /var/lib/lava/dispatcher/tmp/939177/extract-overlay-ramdisk-23b7z_ht/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/939177/tftp-deploy-vnuf9uja/ramdisk/ramdisk.cpio.gz.uboot
261 09:16:50.222754 end: 1.6.8 compress-ramdisk (duration 00:00:11) [common]
262 09:16:50.223351 end: 1.6 prepare-tftp-overlay (duration 00:00:32) [common]
263 09:16:50.223929 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:54) [common]
264 09:16:50.224482 No LXC device requested
265 09:16:50.225041 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
266 09:16:50.225605 start: 1.8 deploy-device-env (timeout 00:08:54) [common]
267 09:16:50.226147 end: 1.8 deploy-device-env (duration 00:00:00) [common]
268 09:16:50.226603 Checking files for TFTP limit of 4294967296 bytes.
269 09:16:50.229609 end: 1 tftp-deploy (duration 00:01:06) [common]
270 09:16:50.230236 start: 2 uboot-action (timeout 00:05:00) [common]
271 09:16:50.230810 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
272 09:16:50.231359 end: 2.1 uboot-from-media (duration 00:00:00) [common]
273 09:16:50.231912 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
274 09:16:50.232526 Using kernel file from prepare-kernel: 939177/tftp-deploy-vnuf9uja/kernel/uImage
275 09:16:50.233216 substitutions:
276 09:16:50.233663 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
277 09:16:50.234104 - {DTB_ADDR}: 0x01070000
278 09:16:50.234544 - {DTB}: 939177/tftp-deploy-vnuf9uja/dtb/meson-g12b-a311d-libretech-cc.dtb
279 09:16:50.234984 - {INITRD}: 939177/tftp-deploy-vnuf9uja/ramdisk/ramdisk.cpio.gz.uboot
280 09:16:50.235422 - {KERNEL_ADDR}: 0x01080000
281 09:16:50.235853 - {KERNEL}: 939177/tftp-deploy-vnuf9uja/kernel/uImage
282 09:16:50.236328 - {LAVA_MAC}: None
283 09:16:50.236805 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/939177/extract-nfsrootfs-rr91m4uv
284 09:16:50.237247 - {NFS_SERVER_IP}: 192.168.6.2
285 09:16:50.237681 - {PRESEED_CONFIG}: None
286 09:16:50.238113 - {PRESEED_LOCAL}: None
287 09:16:50.238543 - {RAMDISK_ADDR}: 0x08000000
288 09:16:50.238968 - {RAMDISK}: 939177/tftp-deploy-vnuf9uja/ramdisk/ramdisk.cpio.gz.uboot
289 09:16:50.239397 - {ROOT_PART}: None
290 09:16:50.239825 - {ROOT}: None
291 09:16:50.240316 - {SERVER_IP}: 192.168.6.2
292 09:16:50.240751 - {TEE_ADDR}: 0x83000000
293 09:16:50.241176 - {TEE}: None
294 09:16:50.241603 Parsed boot commands:
295 09:16:50.242020 - setenv autoload no
296 09:16:50.242446 - setenv initrd_high 0xffffffff
297 09:16:50.242876 - setenv fdt_high 0xffffffff
298 09:16:50.243300 - dhcp
299 09:16:50.243723 - setenv serverip 192.168.6.2
300 09:16:50.244180 - tftpboot 0x01080000 939177/tftp-deploy-vnuf9uja/kernel/uImage
301 09:16:50.244612 - tftpboot 0x08000000 939177/tftp-deploy-vnuf9uja/ramdisk/ramdisk.cpio.gz.uboot
302 09:16:50.245039 - tftpboot 0x01070000 939177/tftp-deploy-vnuf9uja/dtb/meson-g12b-a311d-libretech-cc.dtb
303 09:16:50.245465 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/939177/extract-nfsrootfs-rr91m4uv,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
304 09:16:50.245908 - bootm 0x01080000 0x08000000 0x01070000
305 09:16:50.246449 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
307 09:16:50.248105 start: 2.3 connect-device (timeout 00:05:00) [common]
308 09:16:50.248570 [common] connect-device Connecting to device using 'telnet conserv1 3007'
309 09:16:50.263857 Setting prompt string to ['lava-test: # ']
310 09:16:50.265478 end: 2.3 connect-device (duration 00:00:00) [common]
311 09:16:50.266112 start: 2.4 uboot-commands (timeout 00:05:00) [common]
312 09:16:50.266782 start: 2.4.1 reset-device (timeout 00:05:00) [common]
313 09:16:50.267444 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
314 09:16:50.268726 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
315 09:16:50.306854 >> OK - accepted request
316 09:16:50.308992 Returned 0 in 0 seconds
317 09:16:50.409850 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
319 09:16:50.411542 end: 2.4.1 reset-device (duration 00:00:00) [common]
320 09:16:50.412184 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
321 09:16:50.412750 Setting prompt string to ['Hit any key to stop autoboot']
322 09:16:50.413252 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
323 09:16:50.414902 Trying 192.168.56.21...
324 09:16:50.415425 Connected to conserv1.
325 09:16:50.415881 Escape character is '^]'.
326 09:16:50.416392
327 09:16:50.416844 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
328 09:16:50.417311
329 09:17:02.113792 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
330 09:17:02.114191 bl2_stage_init 0x01
331 09:17:02.114438 bl2_stage_init 0x81
332 09:17:02.119330 hw id: 0x0000 - pwm id 0x01
333 09:17:02.119622 bl2_stage_init 0xc1
334 09:17:02.119848 bl2_stage_init 0x02
335 09:17:02.120108
336 09:17:02.124933 L0:00000000
337 09:17:02.125194 L1:20000703
338 09:17:02.125415 L2:00008067
339 09:17:02.125626 L3:14000000
340 09:17:02.130645 B2:00402000
341 09:17:02.130921 B1:e0f83180
342 09:17:02.131150
343 09:17:02.131369 TE: 58124
344 09:17:02.131585
345 09:17:02.136465 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
346 09:17:02.137006
347 09:17:02.137483 Board ID = 1
348 09:17:02.141960 Set A53 clk to 24M
349 09:17:02.142484 Set A73 clk to 24M
350 09:17:02.142925 Set clk81 to 24M
351 09:17:02.147485 A53 clk: 1200 MHz
352 09:17:02.148021 A73 clk: 1200 MHz
353 09:17:02.148465 CLK81: 166.6M
354 09:17:02.148894 smccc: 00012a92
355 09:17:02.153169 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
356 09:17:02.158715 board id: 1
357 09:17:02.164727 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
358 09:17:02.175240 fw parse done
359 09:17:02.181061 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
360 09:17:02.223691 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
361 09:17:02.234669 PIEI prepare done
362 09:17:02.235238 fastboot data load
363 09:17:02.235686 fastboot data verify
364 09:17:02.240335 verify result: 266
365 09:17:02.245867 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
366 09:17:02.246447 LPDDR4 probe
367 09:17:02.246891 ddr clk to 1584MHz
368 09:17:02.253855 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
369 09:17:02.291080
370 09:17:02.291664 dmc_version 0001
371 09:17:02.297798 Check phy result
372 09:17:02.303644 INFO : End of CA training
373 09:17:02.304275 INFO : End of initialization
374 09:17:02.309311 INFO : Training has run successfully!
375 09:17:02.309889 Check phy result
376 09:17:02.314827 INFO : End of initialization
377 09:17:02.315420 INFO : End of read enable training
378 09:17:02.320391 INFO : End of fine write leveling
379 09:17:02.326029 INFO : End of Write leveling coarse delay
380 09:17:02.326627 INFO : Training has run successfully!
381 09:17:02.327077 Check phy result
382 09:17:02.331564 INFO : End of initialization
383 09:17:02.332175 INFO : End of read dq deskew training
384 09:17:02.337281 INFO : End of MPR read delay center optimization
385 09:17:02.342822 INFO : End of write delay center optimization
386 09:17:02.348416 INFO : End of read delay center optimization
387 09:17:02.348989 INFO : End of max read latency training
388 09:17:02.354059 INFO : Training has run successfully!
389 09:17:02.354631 1D training succeed
390 09:17:02.363284 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
391 09:17:02.410896 Check phy result
392 09:17:02.411602 INFO : End of initialization
393 09:17:02.432596 INFO : End of 2D read delay Voltage center optimization
394 09:17:02.452830 INFO : End of 2D read delay Voltage center optimization
395 09:17:02.504851 INFO : End of 2D write delay Voltage center optimization
396 09:17:02.554226 INFO : End of 2D write delay Voltage center optimization
397 09:17:02.559711 INFO : Training has run successfully!
398 09:17:02.560130
399 09:17:02.560384 channel==0
400 09:17:02.565303 RxClkDly_Margin_A0==88 ps 9
401 09:17:02.565682 TxDqDly_Margin_A0==98 ps 10
402 09:17:02.570875 RxClkDly_Margin_A1==88 ps 9
403 09:17:02.571248 TxDqDly_Margin_A1==88 ps 9
404 09:17:02.571725 TrainedVREFDQ_A0==74
405 09:17:02.576639 TrainedVREFDQ_A1==74
406 09:17:02.577210 VrefDac_Margin_A0==25
407 09:17:02.577675 DeviceVref_Margin_A0==40
408 09:17:02.582231 VrefDac_Margin_A1==25
409 09:17:02.582827 DeviceVref_Margin_A1==40
410 09:17:02.583290
411 09:17:02.583739
412 09:17:02.584247 channel==1
413 09:17:02.587628 RxClkDly_Margin_A0==98 ps 10
414 09:17:02.588300 TxDqDly_Margin_A0==98 ps 10
415 09:17:02.593444 RxClkDly_Margin_A1==98 ps 10
416 09:17:02.594036 TxDqDly_Margin_A1==88 ps 9
417 09:17:02.599005 TrainedVREFDQ_A0==77
418 09:17:02.599597 TrainedVREFDQ_A1==77
419 09:17:02.600093 VrefDac_Margin_A0==22
420 09:17:02.604591 DeviceVref_Margin_A0==37
421 09:17:02.605173 VrefDac_Margin_A1==22
422 09:17:02.610219 DeviceVref_Margin_A1==37
423 09:17:02.610830
424 09:17:02.611308 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
425 09:17:02.611766
426 09:17:02.643811 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000018 00000015 00000018 00000019 00000018 00000019 00000018 0000001a 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
427 09:17:02.644626 2D training succeed
428 09:17:02.649423 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
429 09:17:02.655018 auto size-- 65535DDR cs0 size: 2048MB
430 09:17:02.655610 DDR cs1 size: 2048MB
431 09:17:02.660729 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
432 09:17:02.661356 cs0 DataBus test pass
433 09:17:02.666212 cs1 DataBus test pass
434 09:17:02.666812 cs0 AddrBus test pass
435 09:17:02.667287 cs1 AddrBus test pass
436 09:17:02.667741
437 09:17:02.671825 100bdlr_step_size ps== 420
438 09:17:02.672433 result report
439 09:17:02.677392 boot times 0Enable ddr reg access
440 09:17:02.682796 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
441 09:17:02.696340 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
442 09:17:03.269754 0.0;M3 CHK:0;cm4_sp_mode 0
443 09:17:03.270446 MVN_1=0x00000000
444 09:17:03.275449 MVN_2=0x00000000
445 09:17:03.281160 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
446 09:17:03.281748 OPS=0x10
447 09:17:03.282218 ring efuse init
448 09:17:03.282673 chipver efuse init
449 09:17:03.286653 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
450 09:17:03.292381 [0.018961 Inits done]
451 09:17:03.292975 secure task start!
452 09:17:03.293447 high task start!
453 09:17:03.296776 low task start!
454 09:17:03.297344 run into bl31
455 09:17:03.303509 NOTICE: BL31: v1.3(release):4fc40b1
456 09:17:03.310473 NOTICE: BL31: Built : 15:58:17, May 22 2019
457 09:17:03.311058 NOTICE: BL31: G12A normal boot!
458 09:17:03.336662 NOTICE: BL31: BL33 decompress pass
459 09:17:03.342551 ERROR: Error initializing runtime service opteed_fast
460 09:17:04.574969
461 09:17:04.575372
462 09:17:04.583489 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
463 09:17:04.583833
464 09:17:04.584140 Model: Libre Computer AML-A311D-CC Alta
465 09:17:04.791823 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
466 09:17:04.815271 DRAM: 2 GiB (effective 3.8 GiB)
467 09:17:04.958296 Core: 408 devices, 31 uclasses, devicetree: separate
468 09:17:04.964090 WDT: Not starting watchdog@f0d0
469 09:17:04.996678 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
470 09:17:05.008954 Loading Environment from FAT... Card did not respond to voltage select! : -110
471 09:17:05.014054 ** Bad device specification mmc 0 **
472 09:17:05.024203 Card did not respond to voltage select! : -110
473 09:17:05.030929 ** Bad device specification mmc 0 **
474 09:17:05.031263 Couldn't find partition mmc 0
475 09:17:05.040223 Card did not respond to voltage select! : -110
476 09:17:05.045641 ** Bad device specification mmc 0 **
477 09:17:05.045975 Couldn't find partition mmc 0
478 09:17:05.050836 Error: could not access storage.
479 09:17:06.314142 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.�!,K��х��}���с0x01
480 09:17:06.314792 bl2_stage_init 0x81
481 09:17:06.319708 hw id: 0x0000 - pwm id 0x01
482 09:17:06.320279 bl2_stage_init 0xc1
483 09:17:06.320736 bl2_stage_init 0x02
484 09:17:06.321181
485 09:17:06.325428 L0:00000000
486 09:17:06.326509 L1:20000703
487 09:17:06.327356 L2:00008067
488 09:17:06.328242 L3:14000000
489 09:17:06.329039 B2:00402000
490 09:17:06.330967 B1:e0f83180
491 09:17:06.331842
492 09:17:06.332693 TE: 58150
493 09:17:06.333553
494 09:17:06.336547 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
495 09:17:06.337489
496 09:17:06.338013 Board ID = 1
497 09:17:06.342218 Set A53 clk to 24M
498 09:17:06.343309 Set A73 clk to 24M
499 09:17:06.343780 Set clk81 to 24M
500 09:17:06.347670 A53 clk: 1200 MHz
501 09:17:06.348213 A73 clk: 1200 MHz
502 09:17:06.348675 CLK81: 166.6M
503 09:17:06.349111 smccc: 00012aac
504 09:17:06.353299 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
505 09:17:06.358880 board id: 1
506 09:17:06.364750 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
507 09:17:06.375312 fw parse done
508 09:17:06.380406 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
509 09:17:06.424044 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
510 09:17:06.434863 PIEI prepare done
511 09:17:06.435408 fastboot data load
512 09:17:06.435875 fastboot data verify
513 09:17:06.440582 verify result: 266
514 09:17:06.446149 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
515 09:17:06.446727 LPDDR4 probe
516 09:17:06.447217 ddr clk to 1584MHz
517 09:17:06.454149 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
518 09:17:06.491384
519 09:17:06.492053 dmc_version 0001
520 09:17:06.498093 Check phy result
521 09:17:06.503975 INFO : End of CA training
522 09:17:06.504595 INFO : End of initialization
523 09:17:06.509584 INFO : Training has run successfully!
524 09:17:06.510164 Check phy result
525 09:17:06.515124 INFO : End of initialization
526 09:17:06.515700 INFO : End of read enable training
527 09:17:06.520961 INFO : End of fine write leveling
528 09:17:06.526307 INFO : End of Write leveling coarse delay
529 09:17:06.526836 INFO : Training has run successfully!
530 09:17:06.527296 Check phy result
531 09:17:06.531915 INFO : End of initialization
532 09:17:06.532480 INFO : End of read dq deskew training
533 09:17:06.537581 INFO : End of MPR read delay center optimization
534 09:17:06.543119 INFO : End of write delay center optimization
535 09:17:06.548869 INFO : End of read delay center optimization
536 09:17:06.549455 INFO : End of max read latency training
537 09:17:06.554356 INFO : Training has run successfully!
538 09:17:06.554935 1D training succeed
539 09:17:06.563512 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
540 09:17:06.610420 Check phy result
541 09:17:06.611030 INFO : End of initialization
542 09:17:06.632735 INFO : End of 2D read delay Voltage center optimization
543 09:17:06.653128 INFO : End of 2D read delay Voltage center optimization
544 09:17:06.704785 INFO : End of 2D write delay Voltage center optimization
545 09:17:06.753995 INFO : End of 2D write delay Voltage center optimization
546 09:17:06.759631 INFO : Training has run successfully!
547 09:17:06.760280
548 09:17:06.760815 channel==0
549 09:17:06.765157 RxClkDly_Margin_A0==88 ps 9
550 09:17:06.765756 TxDqDly_Margin_A0==98 ps 10
551 09:17:06.770898 RxClkDly_Margin_A1==88 ps 9
552 09:17:06.771484 TxDqDly_Margin_A1==88 ps 9
553 09:17:06.772015 TrainedVREFDQ_A0==74
554 09:17:06.776338 TrainedVREFDQ_A1==74
555 09:17:06.776928 VrefDac_Margin_A0==25
556 09:17:06.777419 DeviceVref_Margin_A0==40
557 09:17:06.781970 VrefDac_Margin_A1==25
558 09:17:06.782572 DeviceVref_Margin_A1==40
559 09:17:06.783065
560 09:17:06.783545
561 09:17:06.784056 channel==1
562 09:17:06.787731 RxClkDly_Margin_A0==98 ps 10
563 09:17:06.788356 TxDqDly_Margin_A0==98 ps 10
564 09:17:06.793277 RxClkDly_Margin_A1==98 ps 10
565 09:17:06.793855 TxDqDly_Margin_A1==88 ps 9
566 09:17:06.798745 TrainedVREFDQ_A0==77
567 09:17:06.799285 TrainedVREFDQ_A1==77
568 09:17:06.799698 VrefDac_Margin_A0==22
569 09:17:06.804392 DeviceVref_Margin_A0==37
570 09:17:06.805050 VrefDac_Margin_A1==24
571 09:17:06.809857 DeviceVref_Margin_A1==37
572 09:17:06.810376
573 09:17:06.810787 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
574 09:17:06.811185
575 09:17:06.843499 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000019 00000018 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
576 09:17:06.844221 2D training succeed
577 09:17:06.849160 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
578 09:17:06.854685 auto size-- 65535DDR cs0 size: 2048MB
579 09:17:06.855246 DDR cs1 size: 2048MB
580 09:17:06.860360 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
581 09:17:06.860900 cs0 DataBus test pass
582 09:17:06.865859 cs1 DataBus test pass
583 09:17:06.866376 cs0 AddrBus test pass
584 09:17:06.866776 cs1 AddrBus test pass
585 09:17:06.867174
586 09:17:06.871556 100bdlr_step_size ps== 420
587 09:17:06.872093 result report
588 09:17:06.877169 boot times 0Enable ddr reg access
589 09:17:06.882409 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
590 09:17:06.895006 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
591 09:17:07.468164 0.0;M3 CHK:0;cm4_sp_mode 0
592 09:17:07.468799 MVN_1=0x00000000
593 09:17:07.473430 MVN_2=0x00000000
594 09:17:07.479250 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
595 09:17:07.479778 OPS=0x10
596 09:17:07.480241 ring efuse init
597 09:17:07.480640 chipver efuse init
598 09:17:07.487620 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
599 09:17:07.488185 [0.018960 Inits done]
600 09:17:07.488595 secure task start!
601 09:17:07.495035 high task start!
602 09:17:07.495559 low task start!
603 09:17:07.495959 run into bl31
604 09:17:07.501718 NOTICE: BL31: v1.3(release):4fc40b1
605 09:17:07.509493 NOTICE: BL31: Built : 15:58:17, May 22 2019
606 09:17:07.510050 NOTICE: BL31: G12A normal boot!
607 09:17:07.534962 NOTICE: BL31: BL33 decompress pass
608 09:17:07.540576 ERROR: Error initializing runtime service opteed_fast
609 09:17:08.773510
610 09:17:08.773972
611 09:17:08.782052 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
612 09:17:08.782735
613 09:17:08.783267 Model: Libre Computer AML-A311D-CC Alta
614 09:17:08.990522 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
615 09:17:09.013078 DRAM: 2 GiB (effective 3.8 GiB)
616 09:17:09.156936 Core: 408 devices, 31 uclasses, devicetree: separate
617 09:17:09.162615 WDT: Not starting watchdog@f0d0
618 09:17:09.194849 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
619 09:17:09.207392 Loading Environment from FAT... Card did not respond to voltage select! : -110
620 09:17:09.212348 ** Bad device specification mmc 0 **
621 09:17:09.222635 Card did not respond to voltage select! : -110
622 09:17:09.230338 ** Bad device specification mmc 0 **
623 09:17:09.230850 Couldn't find partition mmc 0
624 09:17:09.238723 Card did not respond to voltage select! : -110
625 09:17:09.244123 ** Bad device specification mmc 0 **
626 09:17:09.244633 Couldn't find partition mmc 0
627 09:17:09.249221 Error: could not access storage.
628 09:17:09.592718 Net: eth0: ethernet@ff3f0000
629 09:17:09.593365 starting USB...
630 09:17:09.844631 Bus usb@ff500000: Register 3000140 NbrPorts 3
631 09:17:09.845264 Starting the controller
632 09:17:09.851537 USB XHCI 1.10
633 09:17:11.485588 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
634 09:17:11.486265 bl2_stage_init 0x01
635 09:17:11.486737 bl2_stage_init 0x81
636 09:17:11.491130 hw id: 0x0000 - pwm id 0x01
637 09:17:11.491638 bl2_stage_init 0xc1
638 09:17:11.492147 bl2_stage_init 0x02
639 09:17:11.492599
640 09:17:11.496698 L0:00000000
641 09:17:11.497209 L1:20000703
642 09:17:11.497661 L2:00008067
643 09:17:11.498108 L3:14000000
644 09:17:11.502378 B2:00402000
645 09:17:11.502867 B1:e0f83180
646 09:17:11.503318
647 09:17:11.503764 TE: 58159
648 09:17:11.504253
649 09:17:11.507911 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
650 09:17:11.508435
651 09:17:11.508897 Board ID = 1
652 09:17:11.513545 Set A53 clk to 24M
653 09:17:11.514041 Set A73 clk to 24M
654 09:17:11.514489 Set clk81 to 24M
655 09:17:11.519109 A53 clk: 1200 MHz
656 09:17:11.519587 A73 clk: 1200 MHz
657 09:17:11.520072 CLK81: 166.6M
658 09:17:11.520518 smccc: 00012ab5
659 09:17:11.524703 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
660 09:17:11.530368 board id: 1
661 09:17:11.535299 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
662 09:17:11.546849 fw parse done
663 09:17:11.551836 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
664 09:17:11.594545 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
665 09:17:11.606384 PIEI prepare done
666 09:17:11.606884 fastboot data load
667 09:17:11.607335 fastboot data verify
668 09:17:11.611961 verify result: 266
669 09:17:11.617585 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
670 09:17:11.618074 LPDDR4 probe
671 09:17:11.618523 ddr clk to 1584MHz
672 09:17:11.625582 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
673 09:17:11.662877
674 09:17:11.663384 dmc_version 0001
675 09:17:11.669547 Check phy result
676 09:17:11.675450 INFO : End of CA training
677 09:17:11.675933 INFO : End of initialization
678 09:17:11.680962 INFO : Training has run successfully!
679 09:17:11.681453 Check phy result
680 09:17:11.686583 INFO : End of initialization
681 09:17:11.687068 INFO : End of read enable training
682 09:17:11.692242 INFO : End of fine write leveling
683 09:17:11.697796 INFO : End of Write leveling coarse delay
684 09:17:11.698285 INFO : Training has run successfully!
685 09:17:11.698737 Check phy result
686 09:17:11.703465 INFO : End of initialization
687 09:17:11.703949 INFO : End of read dq deskew training
688 09:17:11.709004 INFO : End of MPR read delay center optimization
689 09:17:11.714572 INFO : End of write delay center optimization
690 09:17:11.720209 INFO : End of read delay center optimization
691 09:17:11.720691 INFO : End of max read latency training
692 09:17:11.725771 INFO : Training has run successfully!
693 09:17:11.726265 1D training succeed
694 09:17:11.734941 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
695 09:17:11.782750 Check phy result
696 09:17:11.783403 INFO : End of initialization
697 09:17:11.805160 INFO : End of 2D read delay Voltage center optimization
698 09:17:11.825204 INFO : End of 2D read delay Voltage center optimization
699 09:17:11.877185 INFO : End of 2D write delay Voltage center optimization
700 09:17:11.926310 INFO : End of 2D write delay Voltage center optimization
701 09:17:11.931793 INFO : Training has run successfully!
702 09:17:11.932339
703 09:17:11.932799 channel==0
704 09:17:11.937481 RxClkDly_Margin_A0==88 ps 9
705 09:17:11.937969 TxDqDly_Margin_A0==98 ps 10
706 09:17:11.943009 RxClkDly_Margin_A1==88 ps 9
707 09:17:11.943494 TxDqDly_Margin_A1==98 ps 10
708 09:17:11.943946 TrainedVREFDQ_A0==74
709 09:17:11.948603 TrainedVREFDQ_A1==74
710 09:17:11.949094 VrefDac_Margin_A0==24
711 09:17:11.949541 DeviceVref_Margin_A0==40
712 09:17:11.954224 VrefDac_Margin_A1==24
713 09:17:11.954704 DeviceVref_Margin_A1==40
714 09:17:11.955150
715 09:17:11.955596
716 09:17:11.959811 channel==1
717 09:17:11.960325 RxClkDly_Margin_A0==98 ps 10
718 09:17:11.960773 TxDqDly_Margin_A0==98 ps 10
719 09:17:11.965475 RxClkDly_Margin_A1==98 ps 10
720 09:17:11.965972 TxDqDly_Margin_A1==88 ps 9
721 09:17:11.971008 TrainedVREFDQ_A0==77
722 09:17:11.971496 TrainedVREFDQ_A1==77
723 09:17:11.971944 VrefDac_Margin_A0==22
724 09:17:11.976592 DeviceVref_Margin_A0==37
725 09:17:11.977067 VrefDac_Margin_A1==22
726 09:17:11.982223 DeviceVref_Margin_A1==37
727 09:17:11.982702
728 09:17:11.983149 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
729 09:17:11.987806
730 09:17:12.015837 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000017 00000018 00000018 00000017 00000017 00000016 00000017 00000015 00000017 00000018 00000017 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
731 09:17:12.016431 2D training succeed
732 09:17:12.021477 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
733 09:17:12.027010 auto size-- 65535DDR cs0 size: 2048MB
734 09:17:12.027503 DDR cs1 size: 2048MB
735 09:17:12.032624 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
736 09:17:12.033109 cs0 DataBus test pass
737 09:17:12.038233 cs1 DataBus test pass
738 09:17:12.038712 cs0 AddrBus test pass
739 09:17:12.039160 cs1 AddrBus test pass
740 09:17:12.039597
741 09:17:12.043833 100bdlr_step_size ps== 420
742 09:17:12.044371 result report
743 09:17:12.049506 boot times 0Enable ddr reg access
744 09:17:12.054861 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
745 09:17:12.068313 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
746 09:17:12.640289 0.0;M3 CHK:0;cm4_sp_mode 0
747 09:17:12.640953 MVN_1=0x00000000
748 09:17:12.645822 MVN_2=0x00000000
749 09:17:12.651585 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
750 09:17:12.652237 OPS=0x10
751 09:17:12.652697 ring efuse init
752 09:17:12.653141 chipver efuse init
753 09:17:12.657166 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
754 09:17:12.662760 [0.018961 Inits done]
755 09:17:12.663310 secure task start!
756 09:17:12.663763 high task start!
757 09:17:12.666378 low task start!
758 09:17:12.666920 run into bl31
759 09:17:12.674031 NOTICE: BL31: v1.3(release):4fc40b1
760 09:17:12.681873 NOTICE: BL31: Built : 15:58:17, May 22 2019
761 09:17:12.682496 NOTICE: BL31: G12A normal boot!
762 09:17:12.707328 NOTICE: BL31: BL33 decompress pass
763 09:17:12.711936 ERROR: Error initializing runtime service opteed_fast
764 09:17:13.945868
765 09:17:13.946549
766 09:17:13.954103 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
767 09:17:13.954606
768 09:17:13.955073 Model: Libre Computer AML-A311D-CC Alta
769 09:17:14.162638 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
770 09:17:14.186008 DRAM: 2 GiB (effective 3.8 GiB)
771 09:17:14.329095 Core: 408 devices, 31 uclasses, devicetree: separate
772 09:17:14.333897 WDT: Not starting watchdog@f0d0
773 09:17:14.367146 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
774 09:17:14.379591 Loading Environment from FAT... Card did not respond to voltage select! : -110
775 09:17:14.383650 ** Bad device specification mmc 0 **
776 09:17:14.394880 Card did not respond to voltage select! : -110
777 09:17:14.402580 ** Bad device specification mmc 0 **
778 09:17:14.403069 Couldn't find partition mmc 0
779 09:17:14.410857 Card did not respond to voltage select! : -110
780 09:17:14.416386 ** Bad device specification mmc 0 **
781 09:17:14.416874 Couldn't find partition mmc 0
782 09:17:14.420490 Error: could not access storage.
783 09:17:14.764046 Net: eth0: ethernet@ff3f0000
784 09:17:14.764619 starting USB...
785 09:17:15.016795 Bus usb@ff500000: Register 3000140 NbrPorts 3
786 09:17:15.017467 Starting the controller
787 09:17:15.023736 USB XHCI 1.10
788 09:17:17.184337 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
789 09:17:17.185002 bl2_stage_init 0x01
790 09:17:17.185511 bl2_stage_init 0x81
791 09:17:17.189829 hw id: 0x0000 - pwm id 0x01
792 09:17:17.190150 bl2_stage_init 0xc1
793 09:17:17.190376 bl2_stage_init 0x02
794 09:17:17.190587
795 09:17:17.195448 L0:00000000
796 09:17:17.195764 L1:20000703
797 09:17:17.196039 L2:00008067
798 09:17:17.196454 L3:14000000
799 09:17:17.201984 B2:00402000
800 09:17:17.202535 B1:e0f83180
801 09:17:17.203017
802 09:17:17.203470 TE: 58159
803 09:17:17.203916
804 09:17:17.206763 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
805 09:17:17.207317
806 09:17:17.207781 Board ID = 1
807 09:17:17.212360 Set A53 clk to 24M
808 09:17:17.212906 Set A73 clk to 24M
809 09:17:17.213368 Set clk81 to 24M
810 09:17:17.217965 A53 clk: 1200 MHz
811 09:17:17.218512 A73 clk: 1200 MHz
812 09:17:17.218974 CLK81: 166.6M
813 09:17:17.219418 smccc: 00012ab4
814 09:17:17.223739 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
815 09:17:17.229215 board id: 1
816 09:17:17.234145 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
817 09:17:17.245743 fw parse done
818 09:17:17.250747 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
819 09:17:17.294304 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
820 09:17:17.305093 PIEI prepare done
821 09:17:17.305655 fastboot data load
822 09:17:17.306129 fastboot data verify
823 09:17:17.310785 verify result: 266
824 09:17:17.316389 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
825 09:17:17.316949 LPDDR4 probe
826 09:17:17.317415 ddr clk to 1584MHz
827 09:17:17.324517 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
828 09:17:17.361640
829 09:17:17.362221 dmc_version 0001
830 09:17:17.367346 Check phy result
831 09:17:17.374179 INFO : End of CA training
832 09:17:17.374742 INFO : End of initialization
833 09:17:17.379759 INFO : Training has run successfully!
834 09:17:17.380357 Check phy result
835 09:17:17.385366 INFO : End of initialization
836 09:17:17.385932 INFO : End of read enable training
837 09:17:17.390937 INFO : End of fine write leveling
838 09:17:17.396566 INFO : End of Write leveling coarse delay
839 09:17:17.397131 INFO : Training has run successfully!
840 09:17:17.397604 Check phy result
841 09:17:17.402198 INFO : End of initialization
842 09:17:17.402752 INFO : End of read dq deskew training
843 09:17:17.407788 INFO : End of MPR read delay center optimization
844 09:17:17.413385 INFO : End of write delay center optimization
845 09:17:17.418966 INFO : End of read delay center optimization
846 09:17:17.419518 INFO : End of max read latency training
847 09:17:17.424566 INFO : Training has run successfully!
848 09:17:17.425153 1D training succeed
849 09:17:17.433701 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
850 09:17:17.480394 Check phy result
851 09:17:17.480989 INFO : End of initialization
852 09:17:17.502029 INFO : End of 2D read delay Voltage center optimization
853 09:17:17.522087 INFO : End of 2D read delay Voltage center optimization
854 09:17:17.574065 INFO : End of 2D write delay Voltage center optimization
855 09:17:17.624204 INFO : End of 2D write delay Voltage center optimization
856 09:17:17.629740 INFO : Training has run successfully!
857 09:17:17.630277
858 09:17:17.630740 channel==0
859 09:17:17.635422 RxClkDly_Margin_A0==88 ps 9
860 09:17:17.635963 TxDqDly_Margin_A0==98 ps 10
861 09:17:17.640937 RxClkDly_Margin_A1==88 ps 9
862 09:17:17.641469 TxDqDly_Margin_A1==98 ps 10
863 09:17:17.641950 TrainedVREFDQ_A0==74
864 09:17:17.646611 TrainedVREFDQ_A1==75
865 09:17:17.647176 VrefDac_Margin_A0==25
866 09:17:17.647609 DeviceVref_Margin_A0==40
867 09:17:17.652310 VrefDac_Margin_A1==25
868 09:17:17.652870 DeviceVref_Margin_A1==39
869 09:17:17.653329
870 09:17:17.653791
871 09:17:17.657779 channel==1
872 09:17:17.658309 RxClkDly_Margin_A0==98 ps 10
873 09:17:17.658740 TxDqDly_Margin_A0==98 ps 10
874 09:17:17.663350 RxClkDly_Margin_A1==88 ps 9
875 09:17:17.663851 TxDqDly_Margin_A1==98 ps 10
876 09:17:17.668860 TrainedVREFDQ_A0==77
877 09:17:17.669365 TrainedVREFDQ_A1==78
878 09:17:17.669800 VrefDac_Margin_A0==22
879 09:17:17.674492 DeviceVref_Margin_A0==37
880 09:17:17.674991 VrefDac_Margin_A1==24
881 09:17:17.680119 DeviceVref_Margin_A1==36
882 09:17:17.680685
883 09:17:17.681125 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
884 09:17:17.685709
885 09:17:17.713671 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000017 00000016 00000017 00000015 00000018 00000018 00000017 00000019 00000018 0000001a 00000019 00000018 00000017 00000018 00000017 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
886 09:17:17.714239 2D training succeed
887 09:17:17.719352 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
888 09:17:17.724862 auto size-- 65535DDR cs0 size: 2048MB
889 09:17:17.725361 DDR cs1 size: 2048MB
890 09:17:17.730581 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
891 09:17:17.731137 cs0 DataBus test pass
892 09:17:17.736240 cs1 DataBus test pass
893 09:17:17.736779 cs0 AddrBus test pass
894 09:17:17.737224 cs1 AddrBus test pass
895 09:17:17.737659
896 09:17:17.741753 100bdlr_step_size ps== 420
897 09:17:17.742295 result report
898 09:17:17.747414 boot times 0Enable ddr reg access
899 09:17:17.752795 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
900 09:17:17.766239 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
901 09:17:18.338239 0.0;M3 CHK:0;cm4_sp_mode 0
902 09:17:18.338892 MVN_1=0x00000000
903 09:17:18.343758 MVN_2=0x00000000
904 09:17:18.349569 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
905 09:17:18.350133 OPS=0x10
906 09:17:18.350611 ring efuse init
907 09:17:18.351066 chipver efuse init
908 09:17:18.355090 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
909 09:17:18.360738 [0.018961 Inits done]
910 09:17:18.361297 secure task start!
911 09:17:18.361762 high task start!
912 09:17:18.365310 low task start!
913 09:17:18.365849 run into bl31
914 09:17:18.371908 NOTICE: BL31: v1.3(release):4fc40b1
915 09:17:18.379682 NOTICE: BL31: Built : 15:58:17, May 22 2019
916 09:17:18.380269 NOTICE: BL31: G12A normal boot!
917 09:17:18.405157 NOTICE: BL31: BL33 decompress pass
918 09:17:18.410856 ERROR: Error initializing runtime service opteed_fast
919 09:17:19.643758
920 09:17:19.644468
921 09:17:19.652116 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
922 09:17:19.652657
923 09:17:19.653123 Model: Libre Computer AML-A311D-CC Alta
924 09:17:19.860525 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
925 09:17:19.883951 DRAM: 2 GiB (effective 3.8 GiB)
926 09:17:20.026884 Core: 408 devices, 31 uclasses, devicetree: separate
927 09:17:20.032824 WDT: Not starting watchdog@f0d0
928 09:17:20.065012 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
929 09:17:20.077429 Loading Environment from FAT... Card did not respond to voltage select! : -110
930 09:17:20.082444 ** Bad device specification mmc 0 **
931 09:17:20.092792 Card did not respond to voltage select! : -110
932 09:17:20.100430 ** Bad device specification mmc 0 **
933 09:17:20.100951 Couldn't find partition mmc 0
934 09:17:20.108792 Card did not respond to voltage select! : -110
935 09:17:20.114284 ** Bad device specification mmc 0 **
936 09:17:20.114801 Couldn't find partition mmc 0
937 09:17:20.119346 Error: could not access storage.
938 09:17:20.461711 Net: eth0: ethernet@ff3f0000
939 09:17:20.462123 starting USB...
940 09:17:20.713471 Bus usb@ff500000: Register 3000140 NbrPorts 3
941 09:17:20.714049 Starting the controller
942 09:17:20.720438 USB XHCI 1.10
943 09:17:22.274531 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
944 09:17:22.283115 scanning usb for storage devices... 0 Storage Device(s) found
946 09:17:22.334338 Hit any key to stop autoboot: 1
947 09:17:22.335077 end: 2.4.2 bootloader-interrupt (duration 00:00:32) [common]
948 09:17:22.335450 start: 2.4.3 bootloader-commands (timeout 00:04:28) [common]
949 09:17:22.335715 Setting prompt string to ['=>']
950 09:17:22.335974 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:28)
951 09:17:22.350434 0
952 09:17:22.351059 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
953 09:17:22.351354 Sending with 10 millisecond of delay
955 09:17:23.485351 => setenv autoload no
956 09:17:23.495927 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:27)
957 09:17:23.498520 setenv autoload no
958 09:17:23.499000 Sending with 10 millisecond of delay
960 09:17:25.295392 => setenv initrd_high 0xffffffff
961 09:17:25.306391 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:25)
962 09:17:25.307435 setenv initrd_high 0xffffffff
963 09:17:25.308338 Sending with 10 millisecond of delay
965 09:17:26.925257 => setenv fdt_high 0xffffffff
966 09:17:26.936222 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:23)
967 09:17:26.937252 setenv fdt_high 0xffffffff
968 09:17:26.938126 Sending with 10 millisecond of delay
970 09:17:27.230345 => dhcp
971 09:17:27.241333 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:23)
972 09:17:27.242389 dhcp
973 09:17:27.242964 Speed: 1000, full duplex
974 09:17:27.243498 BOOTP broadcast 1
975 09:17:27.253037 DHCP client bound to address 192.168.6.27 (11 ms)
976 09:17:27.253956 Sending with 10 millisecond of delay
978 09:17:28.930967 => setenv serverip 192.168.6.2
979 09:17:28.942023 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:21)
980 09:17:28.943260 setenv serverip 192.168.6.2
981 09:17:28.944110 Sending with 10 millisecond of delay
983 09:17:32.669983 => tftpboot 0x01080000 939177/tftp-deploy-vnuf9uja/kernel/uImage
984 09:17:32.680879 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
985 09:17:32.681823 tftpboot 0x01080000 939177/tftp-deploy-vnuf9uja/kernel/uImage
986 09:17:32.682310 Speed: 1000, full duplex
987 09:17:32.682767 Using ethernet@ff3f0000 device
988 09:17:32.684024 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
989 09:17:32.689567 Filename '939177/tftp-deploy-vnuf9uja/kernel/uImage'.
990 09:17:32.693441 Load address: 0x1080000
991 09:17:35.584772 Loading: *################################################## 43.6 MiB
992 09:17:35.585457 15.1 MiB/s
993 09:17:35.585951 done
994 09:17:35.589337 Bytes transferred = 45716032 (2b99240 hex)
995 09:17:35.590297 Sending with 10 millisecond of delay
997 09:17:40.278528 => tftpboot 0x08000000 939177/tftp-deploy-vnuf9uja/ramdisk/ramdisk.cpio.gz.uboot
998 09:17:40.289367 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:10)
999 09:17:40.290245 tftpboot 0x08000000 939177/tftp-deploy-vnuf9uja/ramdisk/ramdisk.cpio.gz.uboot
1000 09:17:40.290733 Speed: 1000, full duplex
1001 09:17:40.291188 Using ethernet@ff3f0000 device
1002 09:17:40.292317 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1003 09:17:40.304108 Filename '939177/tftp-deploy-vnuf9uja/ramdisk/ramdisk.cpio.gz.uboot'.
1004 09:17:40.304673 Load address: 0x8000000
1005 09:17:47.299792 Loading: *#####################T ############################ UDP wrong checksum 00000005 00006ee8
1006 09:17:52.300494 T UDP wrong checksum 00000005 00006ee8
1007 09:17:57.505888 T UDP wrong checksum 000000ff 00001f81
1008 09:17:57.555859 UDP wrong checksum 000000ff 0000b873
1009 09:18:02.303948 T UDP wrong checksum 00000005 00006ee8
1010 09:18:22.307645 T T T T UDP wrong checksum 00000005 00006ee8
1011 09:18:31.857928 T UDP wrong checksum 000000ff 00003d88
1012 09:18:31.948307 UDP wrong checksum 000000ff 0000d07a
1013 09:18:37.311118 T
1014 09:18:37.311793 Retry count exceeded; starting again
1016 09:18:37.313371 end: 2.4.3 bootloader-commands (duration 00:01:15) [common]
1019 09:18:37.315414 end: 2.4 uboot-commands (duration 00:01:47) [common]
1021 09:18:37.316987 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
1023 09:18:37.318123 end: 2 uboot-action (duration 00:01:47) [common]
1025 09:18:37.319807 Cleaning after the job
1026 09:18:37.320454 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/939177/tftp-deploy-vnuf9uja/ramdisk
1027 09:18:37.321816 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/939177/tftp-deploy-vnuf9uja/kernel
1028 09:18:37.368948 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/939177/tftp-deploy-vnuf9uja/dtb
1029 09:18:37.369724 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/939177/tftp-deploy-vnuf9uja/nfsrootfs
1030 09:18:37.431246 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/939177/tftp-deploy-vnuf9uja/modules
1031 09:18:37.449222 start: 4.1 power-off (timeout 00:00:30) [common]
1032 09:18:37.449877 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1033 09:18:37.485189 >> OK - accepted request
1034 09:18:37.487520 Returned 0 in 0 seconds
1035 09:18:37.588330 end: 4.1 power-off (duration 00:00:00) [common]
1037 09:18:37.589346 start: 4.2 read-feedback (timeout 00:10:00) [common]
1038 09:18:37.589989 Listened to connection for namespace 'common' for up to 1s
1039 09:18:38.590035 Finalising connection for namespace 'common'
1040 09:18:38.590787 Disconnecting from shell: Finalise
1041 09:18:38.591355 =>
1042 09:18:38.692391 end: 4.2 read-feedback (duration 00:00:01) [common]
1043 09:18:38.693018 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/939177
1044 09:18:41.551228 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/939177
1045 09:18:41.551878 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.