Boot log: meson-sm1-s905d3-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 23:51:12.659658 lava-dispatcher, installed at version: 2024.01
2 23:51:12.660478 start: 0 validate
3 23:51:12.660945 Start time: 2024-11-05 23:51:12.660914+00:00 (UTC)
4 23:51:12.661494 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 23:51:12.662029 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-igt%2F20240313.0%2Farm64%2Frootfs.cpio.gz exists
6 23:51:12.702181 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 23:51:12.702714 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fpending-fixes%2Fv6.12-rc6-237-g47f01a19a6ee2%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 23:51:12.735919 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 23:51:12.736620 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fpending-fixes%2Fv6.12-rc6-237-g47f01a19a6ee2%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-sm1-s905d3-libretech-cc.dtb exists
10 23:51:12.765738 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 23:51:12.766213 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fpending-fixes%2Fv6.12-rc6-237-g47f01a19a6ee2%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
12 23:51:12.810284 validate duration: 0.15
14 23:51:12.811131 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 23:51:12.811441 start: 1.1 download-retry (timeout 00:10:00) [common]
16 23:51:12.811730 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 23:51:12.812322 Not decompressing ramdisk as can be used compressed.
18 23:51:12.812751 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-igt/20240313.0/arm64/rootfs.cpio.gz
19 23:51:12.813008 saving as /var/lib/lava/dispatcher/tmp/943308/tftp-deploy-l2zn3scx/ramdisk/rootfs.cpio.gz
20 23:51:12.813268 total size: 47897469 (45 MB)
21 23:51:12.848074 progress 0 % (0 MB)
22 23:51:12.879172 progress 5 % (2 MB)
23 23:51:12.909173 progress 10 % (4 MB)
24 23:51:12.939120 progress 15 % (6 MB)
25 23:51:12.968966 progress 20 % (9 MB)
26 23:51:12.998858 progress 25 % (11 MB)
27 23:51:13.028775 progress 30 % (13 MB)
28 23:51:13.058700 progress 35 % (16 MB)
29 23:51:13.088781 progress 40 % (18 MB)
30 23:51:13.118602 progress 45 % (20 MB)
31 23:51:13.148466 progress 50 % (22 MB)
32 23:51:13.178401 progress 55 % (25 MB)
33 23:51:13.209020 progress 60 % (27 MB)
34 23:51:13.238885 progress 65 % (29 MB)
35 23:51:13.268772 progress 70 % (32 MB)
36 23:51:13.298629 progress 75 % (34 MB)
37 23:51:13.328478 progress 80 % (36 MB)
38 23:51:13.358287 progress 85 % (38 MB)
39 23:51:13.388252 progress 90 % (41 MB)
40 23:51:13.418021 progress 95 % (43 MB)
41 23:51:13.447421 progress 100 % (45 MB)
42 23:51:13.448184 45 MB downloaded in 0.63 s (71.95 MB/s)
43 23:51:13.448766 end: 1.1.1 http-download (duration 00:00:01) [common]
45 23:51:13.449676 end: 1.1 download-retry (duration 00:00:01) [common]
46 23:51:13.449992 start: 1.2 download-retry (timeout 00:09:59) [common]
47 23:51:13.450280 start: 1.2.1 http-download (timeout 00:09:59) [common]
48 23:51:13.450772 downloading http://storage.kernelci.org/next/pending-fixes/v6.12-rc6-237-g47f01a19a6ee2/arm64/defconfig/gcc-12/kernel/Image
49 23:51:13.451032 saving as /var/lib/lava/dispatcher/tmp/943308/tftp-deploy-l2zn3scx/kernel/Image
50 23:51:13.451249 total size: 45715968 (43 MB)
51 23:51:13.451469 No compression specified
52 23:51:13.494263 progress 0 % (0 MB)
53 23:51:13.522270 progress 5 % (2 MB)
54 23:51:13.550500 progress 10 % (4 MB)
55 23:51:13.578551 progress 15 % (6 MB)
56 23:51:13.606670 progress 20 % (8 MB)
57 23:51:13.634116 progress 25 % (10 MB)
58 23:51:13.662297 progress 30 % (13 MB)
59 23:51:13.690381 progress 35 % (15 MB)
60 23:51:13.718630 progress 40 % (17 MB)
61 23:51:13.746393 progress 45 % (19 MB)
62 23:51:13.774430 progress 50 % (21 MB)
63 23:51:13.802838 progress 55 % (24 MB)
64 23:51:13.831129 progress 60 % (26 MB)
65 23:51:13.858912 progress 65 % (28 MB)
66 23:51:13.887132 progress 70 % (30 MB)
67 23:51:13.915325 progress 75 % (32 MB)
68 23:51:13.943262 progress 80 % (34 MB)
69 23:51:13.970855 progress 85 % (37 MB)
70 23:51:13.998956 progress 90 % (39 MB)
71 23:51:14.026952 progress 95 % (41 MB)
72 23:51:14.054006 progress 100 % (43 MB)
73 23:51:14.054541 43 MB downloaded in 0.60 s (72.27 MB/s)
74 23:51:14.055021 end: 1.2.1 http-download (duration 00:00:01) [common]
76 23:51:14.055827 end: 1.2 download-retry (duration 00:00:01) [common]
77 23:51:14.056136 start: 1.3 download-retry (timeout 00:09:59) [common]
78 23:51:14.056403 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 23:51:14.056877 downloading http://storage.kernelci.org/next/pending-fixes/v6.12-rc6-237-g47f01a19a6ee2/arm64/defconfig/gcc-12/dtbs/amlogic/meson-sm1-s905d3-libretech-cc.dtb
80 23:51:14.057152 saving as /var/lib/lava/dispatcher/tmp/943308/tftp-deploy-l2zn3scx/dtb/meson-sm1-s905d3-libretech-cc.dtb
81 23:51:14.057357 total size: 53209 (0 MB)
82 23:51:14.057562 No compression specified
83 23:51:14.092750 progress 61 % (0 MB)
84 23:51:14.093598 progress 100 % (0 MB)
85 23:51:14.094146 0 MB downloaded in 0.04 s (1.38 MB/s)
86 23:51:14.094603 end: 1.3.1 http-download (duration 00:00:00) [common]
88 23:51:14.095400 end: 1.3 download-retry (duration 00:00:00) [common]
89 23:51:14.095659 start: 1.4 download-retry (timeout 00:09:59) [common]
90 23:51:14.095921 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 23:51:14.096405 downloading http://storage.kernelci.org/next/pending-fixes/v6.12-rc6-237-g47f01a19a6ee2/arm64/defconfig/gcc-12/modules.tar.xz
92 23:51:14.096647 saving as /var/lib/lava/dispatcher/tmp/943308/tftp-deploy-l2zn3scx/modules/modules.tar
93 23:51:14.096850 total size: 11614632 (11 MB)
94 23:51:14.097058 Using unxz to decompress xz
95 23:51:14.132076 progress 0 % (0 MB)
96 23:51:14.198080 progress 5 % (0 MB)
97 23:51:14.271737 progress 10 % (1 MB)
98 23:51:14.366764 progress 15 % (1 MB)
99 23:51:14.458062 progress 20 % (2 MB)
100 23:51:14.537228 progress 25 % (2 MB)
101 23:51:14.612445 progress 30 % (3 MB)
102 23:51:14.691006 progress 35 % (3 MB)
103 23:51:14.763819 progress 40 % (4 MB)
104 23:51:14.840262 progress 45 % (5 MB)
105 23:51:14.924106 progress 50 % (5 MB)
106 23:51:15.000588 progress 55 % (6 MB)
107 23:51:15.085001 progress 60 % (6 MB)
108 23:51:15.164993 progress 65 % (7 MB)
109 23:51:15.244809 progress 70 % (7 MB)
110 23:51:15.322479 progress 75 % (8 MB)
111 23:51:15.405264 progress 80 % (8 MB)
112 23:51:15.484616 progress 85 % (9 MB)
113 23:51:15.567022 progress 90 % (10 MB)
114 23:51:15.639898 progress 95 % (10 MB)
115 23:51:15.715939 progress 100 % (11 MB)
116 23:51:15.727813 11 MB downloaded in 1.63 s (6.79 MB/s)
117 23:51:15.728734 end: 1.4.1 http-download (duration 00:00:02) [common]
119 23:51:15.730326 end: 1.4 download-retry (duration 00:00:02) [common]
120 23:51:15.730848 start: 1.5 prepare-tftp-overlay (timeout 00:09:57) [common]
121 23:51:15.731365 start: 1.5.1 extract-nfsrootfs (timeout 00:09:57) [common]
122 23:51:15.731851 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 23:51:15.732386 start: 1.5.2 lava-overlay (timeout 00:09:57) [common]
124 23:51:15.733364 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/943308/lava-overlay-2ohi7czk
125 23:51:15.734196 makedir: /var/lib/lava/dispatcher/tmp/943308/lava-overlay-2ohi7czk/lava-943308/bin
126 23:51:15.734857 makedir: /var/lib/lava/dispatcher/tmp/943308/lava-overlay-2ohi7czk/lava-943308/tests
127 23:51:15.735468 makedir: /var/lib/lava/dispatcher/tmp/943308/lava-overlay-2ohi7czk/lava-943308/results
128 23:51:15.736108 Creating /var/lib/lava/dispatcher/tmp/943308/lava-overlay-2ohi7czk/lava-943308/bin/lava-add-keys
129 23:51:15.737066 Creating /var/lib/lava/dispatcher/tmp/943308/lava-overlay-2ohi7czk/lava-943308/bin/lava-add-sources
130 23:51:15.738031 Creating /var/lib/lava/dispatcher/tmp/943308/lava-overlay-2ohi7czk/lava-943308/bin/lava-background-process-start
131 23:51:15.738963 Creating /var/lib/lava/dispatcher/tmp/943308/lava-overlay-2ohi7czk/lava-943308/bin/lava-background-process-stop
132 23:51:15.739940 Creating /var/lib/lava/dispatcher/tmp/943308/lava-overlay-2ohi7czk/lava-943308/bin/lava-common-functions
133 23:51:15.740897 Creating /var/lib/lava/dispatcher/tmp/943308/lava-overlay-2ohi7czk/lava-943308/bin/lava-echo-ipv4
134 23:51:15.741786 Creating /var/lib/lava/dispatcher/tmp/943308/lava-overlay-2ohi7czk/lava-943308/bin/lava-install-packages
135 23:51:15.742662 Creating /var/lib/lava/dispatcher/tmp/943308/lava-overlay-2ohi7czk/lava-943308/bin/lava-installed-packages
136 23:51:15.743532 Creating /var/lib/lava/dispatcher/tmp/943308/lava-overlay-2ohi7czk/lava-943308/bin/lava-os-build
137 23:51:15.744447 Creating /var/lib/lava/dispatcher/tmp/943308/lava-overlay-2ohi7czk/lava-943308/bin/lava-probe-channel
138 23:51:15.745338 Creating /var/lib/lava/dispatcher/tmp/943308/lava-overlay-2ohi7czk/lava-943308/bin/lava-probe-ip
139 23:51:15.746217 Creating /var/lib/lava/dispatcher/tmp/943308/lava-overlay-2ohi7czk/lava-943308/bin/lava-target-ip
140 23:51:15.747084 Creating /var/lib/lava/dispatcher/tmp/943308/lava-overlay-2ohi7czk/lava-943308/bin/lava-target-mac
141 23:51:15.747953 Creating /var/lib/lava/dispatcher/tmp/943308/lava-overlay-2ohi7czk/lava-943308/bin/lava-target-storage
142 23:51:15.748978 Creating /var/lib/lava/dispatcher/tmp/943308/lava-overlay-2ohi7czk/lava-943308/bin/lava-test-case
143 23:51:15.749924 Creating /var/lib/lava/dispatcher/tmp/943308/lava-overlay-2ohi7czk/lava-943308/bin/lava-test-event
144 23:51:15.750835 Creating /var/lib/lava/dispatcher/tmp/943308/lava-overlay-2ohi7czk/lava-943308/bin/lava-test-feedback
145 23:51:15.751712 Creating /var/lib/lava/dispatcher/tmp/943308/lava-overlay-2ohi7czk/lava-943308/bin/lava-test-raise
146 23:51:15.752633 Creating /var/lib/lava/dispatcher/tmp/943308/lava-overlay-2ohi7czk/lava-943308/bin/lava-test-reference
147 23:51:15.753511 Creating /var/lib/lava/dispatcher/tmp/943308/lava-overlay-2ohi7czk/lava-943308/bin/lava-test-runner
148 23:51:15.754385 Creating /var/lib/lava/dispatcher/tmp/943308/lava-overlay-2ohi7czk/lava-943308/bin/lava-test-set
149 23:51:15.755354 Creating /var/lib/lava/dispatcher/tmp/943308/lava-overlay-2ohi7czk/lava-943308/bin/lava-test-shell
150 23:51:15.756317 Updating /var/lib/lava/dispatcher/tmp/943308/lava-overlay-2ohi7czk/lava-943308/bin/lava-install-packages (oe)
151 23:51:15.757280 Updating /var/lib/lava/dispatcher/tmp/943308/lava-overlay-2ohi7czk/lava-943308/bin/lava-installed-packages (oe)
152 23:51:15.758090 Creating /var/lib/lava/dispatcher/tmp/943308/lava-overlay-2ohi7czk/lava-943308/environment
153 23:51:15.758790 LAVA metadata
154 23:51:15.759272 - LAVA_JOB_ID=943308
155 23:51:15.759696 - LAVA_DISPATCHER_IP=192.168.6.2
156 23:51:15.760384 start: 1.5.2.1 ssh-authorize (timeout 00:09:57) [common]
157 23:51:15.762133 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 23:51:15.762734 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:57) [common]
159 23:51:15.763144 skipped lava-vland-overlay
160 23:51:15.763622 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 23:51:15.764155 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:57) [common]
162 23:51:15.764579 skipped lava-multinode-overlay
163 23:51:15.765053 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 23:51:15.765544 start: 1.5.2.4 test-definition (timeout 00:09:57) [common]
165 23:51:15.766010 Loading test definitions
166 23:51:15.766542 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:57) [common]
167 23:51:15.766974 Using /lava-943308 at stage 0
168 23:51:15.768685 uuid=943308_1.5.2.4.1 testdef=None
169 23:51:15.769018 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 23:51:15.769305 start: 1.5.2.4.2 test-overlay (timeout 00:09:57) [common]
171 23:51:15.771021 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 23:51:15.771833 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:57) [common]
174 23:51:15.774008 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 23:51:15.774877 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:57) [common]
177 23:51:15.776985 runner path: /var/lib/lava/dispatcher/tmp/943308/lava-overlay-2ohi7czk/lava-943308/0/tests/0_igt-gpu-panfrost test_uuid 943308_1.5.2.4.1
178 23:51:15.777583 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 23:51:15.778403 Creating lava-test-runner.conf files
181 23:51:15.778610 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/943308/lava-overlay-2ohi7czk/lava-943308/0 for stage 0
182 23:51:15.778943 - 0_igt-gpu-panfrost
183 23:51:15.779295 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 23:51:15.779579 start: 1.5.2.5 compress-overlay (timeout 00:09:57) [common]
185 23:51:15.803183 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 23:51:15.803603 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:57) [common]
187 23:51:15.803871 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 23:51:15.804171 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 23:51:15.804440 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:57) [common]
190 23:51:22.858581 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:07) [common]
191 23:51:22.859047 start: 1.5.4 extract-modules (timeout 00:09:50) [common]
192 23:51:22.859291 extracting modules file /var/lib/lava/dispatcher/tmp/943308/tftp-deploy-l2zn3scx/modules/modules.tar to /var/lib/lava/dispatcher/tmp/943308/extract-overlay-ramdisk-e8rw6xu_/ramdisk
193 23:51:24.261194 end: 1.5.4 extract-modules (duration 00:00:01) [common]
194 23:51:24.261683 start: 1.5.5 apply-overlay-tftp (timeout 00:09:49) [common]
195 23:51:24.261960 [common] Applying overlay /var/lib/lava/dispatcher/tmp/943308/compress-overlay-9hpqjbk1/overlay-1.5.2.5.tar.gz to ramdisk
196 23:51:24.262173 [common] Applying overlay /var/lib/lava/dispatcher/tmp/943308/compress-overlay-9hpqjbk1/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/943308/extract-overlay-ramdisk-e8rw6xu_/ramdisk
197 23:51:24.292553 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 23:51:24.292994 start: 1.5.6 prepare-kernel (timeout 00:09:49) [common]
199 23:51:24.293266 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:49) [common]
200 23:51:24.293495 Converting downloaded kernel to a uImage
201 23:51:24.293799 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/943308/tftp-deploy-l2zn3scx/kernel/Image /var/lib/lava/dispatcher/tmp/943308/tftp-deploy-l2zn3scx/kernel/uImage
202 23:51:24.789957 output: Image Name:
203 23:51:24.790366 output: Created: Tue Nov 5 23:51:24 2024
204 23:51:24.790573 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 23:51:24.790777 output: Data Size: 45715968 Bytes = 44644.50 KiB = 43.60 MiB
206 23:51:24.790978 output: Load Address: 01080000
207 23:51:24.791175 output: Entry Point: 01080000
208 23:51:24.791372 output:
209 23:51:24.791701 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
210 23:51:24.791963 end: 1.5.6 prepare-kernel (duration 00:00:00) [common]
211 23:51:24.792278 start: 1.5.7 configure-preseed-file (timeout 00:09:48) [common]
212 23:51:24.792533 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 23:51:24.792790 start: 1.5.8 compress-ramdisk (timeout 00:09:48) [common]
214 23:51:24.793043 Building ramdisk /var/lib/lava/dispatcher/tmp/943308/extract-overlay-ramdisk-e8rw6xu_/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/943308/extract-overlay-ramdisk-e8rw6xu_/ramdisk
215 23:51:31.604412 >> 502418 blocks
216 23:51:52.174900 Adding RAMdisk u-boot header.
217 23:51:52.175631 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/943308/extract-overlay-ramdisk-e8rw6xu_/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/943308/extract-overlay-ramdisk-e8rw6xu_/ramdisk.cpio.gz.uboot
218 23:51:52.866913 output: Image Name:
219 23:51:52.867420 output: Created: Tue Nov 5 23:51:52 2024
220 23:51:52.867676 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 23:51:52.867921 output: Data Size: 65714079 Bytes = 64173.91 KiB = 62.67 MiB
222 23:51:52.868468 output: Load Address: 00000000
223 23:51:52.868983 output: Entry Point: 00000000
224 23:51:52.869503 output:
225 23:51:52.870672 rename /var/lib/lava/dispatcher/tmp/943308/extract-overlay-ramdisk-e8rw6xu_/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/943308/tftp-deploy-l2zn3scx/ramdisk/ramdisk.cpio.gz.uboot
226 23:51:52.871570 end: 1.5.8 compress-ramdisk (duration 00:00:28) [common]
227 23:51:52.872310 end: 1.5 prepare-tftp-overlay (duration 00:00:37) [common]
228 23:51:52.872987 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:20) [common]
229 23:51:52.873558 No LXC device requested
230 23:51:52.874191 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 23:51:52.874847 start: 1.7 deploy-device-env (timeout 00:09:20) [common]
232 23:51:52.875467 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 23:51:52.876012 Checking files for TFTP limit of 4294967296 bytes.
234 23:51:52.879494 end: 1 tftp-deploy (duration 00:00:40) [common]
235 23:51:52.880293 start: 2 uboot-action (timeout 00:05:00) [common]
236 23:51:52.880986 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 23:51:52.881623 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 23:51:52.882259 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 23:51:52.882925 Using kernel file from prepare-kernel: 943308/tftp-deploy-l2zn3scx/kernel/uImage
240 23:51:52.883709 substitutions:
241 23:51:52.884288 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 23:51:52.884800 - {DTB_ADDR}: 0x01070000
243 23:51:52.885305 - {DTB}: 943308/tftp-deploy-l2zn3scx/dtb/meson-sm1-s905d3-libretech-cc.dtb
244 23:51:52.885809 - {INITRD}: 943308/tftp-deploy-l2zn3scx/ramdisk/ramdisk.cpio.gz.uboot
245 23:51:52.886312 - {KERNEL_ADDR}: 0x01080000
246 23:51:52.886811 - {KERNEL}: 943308/tftp-deploy-l2zn3scx/kernel/uImage
247 23:51:52.887311 - {LAVA_MAC}: None
248 23:51:52.887860 - {PRESEED_CONFIG}: None
249 23:51:52.888407 - {PRESEED_LOCAL}: None
250 23:51:52.888916 - {RAMDISK_ADDR}: 0x08000000
251 23:51:52.889422 - {RAMDISK}: 943308/tftp-deploy-l2zn3scx/ramdisk/ramdisk.cpio.gz.uboot
252 23:51:52.889941 - {ROOT_PART}: None
253 23:51:52.890447 - {ROOT}: None
254 23:51:52.890955 - {SERVER_IP}: 192.168.6.2
255 23:51:52.891464 - {TEE_ADDR}: 0x83000000
256 23:51:52.891966 - {TEE}: None
257 23:51:52.892502 Parsed boot commands:
258 23:51:52.892990 - setenv autoload no
259 23:51:52.893494 - setenv initrd_high 0xffffffff
260 23:51:52.893997 - setenv fdt_high 0xffffffff
261 23:51:52.894499 - dhcp
262 23:51:52.894997 - setenv serverip 192.168.6.2
263 23:51:52.895499 - tftpboot 0x01080000 943308/tftp-deploy-l2zn3scx/kernel/uImage
264 23:51:52.896060 - tftpboot 0x08000000 943308/tftp-deploy-l2zn3scx/ramdisk/ramdisk.cpio.gz.uboot
265 23:51:52.896590 - tftpboot 0x01070000 943308/tftp-deploy-l2zn3scx/dtb/meson-sm1-s905d3-libretech-cc.dtb
266 23:51:52.897098 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 23:51:52.897612 - bootm 0x01080000 0x08000000 0x01070000
268 23:51:52.898262 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 23:51:52.900197 start: 2.3 connect-device (timeout 00:05:00) [common]
271 23:51:52.900776 [common] connect-device Connecting to device using 'telnet conserv1 3008'
272 23:51:52.916295 Setting prompt string to ['lava-test: # ']
273 23:51:52.918252 end: 2.3 connect-device (duration 00:00:00) [common]
274 23:51:52.919039 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 23:51:52.919748 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 23:51:52.920454 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 23:51:52.921879 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=solitude-01'
278 23:51:52.958944 >> OK - accepted request
279 23:51:52.961106 Returned 0 in 0 seconds
280 23:51:53.062483 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
282 23:51:53.064645 end: 2.4.1 reset-device (duration 00:00:00) [common]
283 23:51:53.065368 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
284 23:51:53.066005 Setting prompt string to ['Hit any key to stop autoboot']
285 23:51:53.066576 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 23:51:53.068680 Trying 192.168.56.21...
287 23:51:53.069307 Connected to conserv1.
288 23:51:53.069827 Escape character is '^]'.
289 23:51:53.070356
290 23:51:53.070896 ser2net port telnet,3008 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.3.3:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
291 23:51:53.071433
292 23:51:59.578839 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
293 23:51:59.579652 bl2_stage_init 0x01
294 23:51:59.580246 bl2_stage_init 0x81
295 23:51:59.584455 hw id: 0x0000 - pwm id 0x01
296 23:51:59.585049 bl2_stage_init 0xc1
297 23:51:59.588851 bl2_stage_init 0x02
298 23:51:59.589421
299 23:51:59.589945 L0:00000000
300 23:51:59.590455 L1:00000703
301 23:51:59.590954 L2:00008067
302 23:51:59.594448 L3:15000000
303 23:51:59.594974 S1:00000000
304 23:51:59.595476 B2:20282000
305 23:51:59.595975 B1:a0f83180
306 23:51:59.596497
307 23:51:59.596995 TE: 73010
308 23:51:59.597494
309 23:51:59.605668 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
310 23:51:59.606213
311 23:51:59.606718 Board ID = 1
312 23:51:59.607213 Set cpu clk to 24M
313 23:51:59.607697 Set clk81 to 24M
314 23:51:59.609258 Use GP1_pll as DSU clk.
315 23:51:59.614772 DSU clk: 1200 Mhz
316 23:51:59.615298 CPU clk: 1200 MHz
317 23:51:59.615802 Set clk81 to 166.6M
318 23:51:59.620397 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
319 23:51:59.620926 board id: 1
320 23:51:59.629784 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
321 23:51:59.641462 fw parse done
322 23:51:59.647415 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
323 23:51:59.690026 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
324 23:51:59.700862 PIEI prepare done
325 23:51:59.701386 fastboot data load
326 23:51:59.701892 fastboot data verify
327 23:51:59.706477 verify result: 266
328 23:51:59.712088 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
329 23:51:59.712634 LPDDR4 probe
330 23:51:59.713143 ddr clk to 1584MHz
331 23:51:59.720097 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
332 23:51:59.757295
333 23:51:59.757866 dmc_version 0001
334 23:51:59.764046 Check phy result
335 23:51:59.769958 INFO : End of CA training
336 23:51:59.770497 INFO : End of initialization
337 23:51:59.775501 INFO : Training has run successfully!
338 23:51:59.776053 Check phy result
339 23:51:59.781101 INFO : End of initialization
340 23:51:59.781648 INFO : End of read enable training
341 23:51:59.786701 INFO : End of fine write leveling
342 23:51:59.792296 INFO : End of Write leveling coarse delay
343 23:51:59.792825 INFO : Training has run successfully!
344 23:51:59.793327 Check phy result
345 23:51:59.797976 INFO : End of initialization
346 23:51:59.798528 INFO : End of read dq deskew training
347 23:51:59.803494 INFO : End of MPR read delay center optimization
348 23:51:59.809078 INFO : End of write delay center optimization
349 23:51:59.814703 INFO : End of read delay center optimization
350 23:51:59.815254 INFO : End of max read latency training
351 23:51:59.820305 INFO : Training has run successfully!
352 23:51:59.820828 1D training succeed
353 23:51:59.829487 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
354 23:51:59.877051 Check phy result
355 23:51:59.877591 INFO : End of initialization
356 23:51:59.899469 INFO : End of 2D read delay Voltage center optimization
357 23:51:59.918608 INFO : End of 2D read delay Voltage center optimization
358 23:51:59.970451 INFO : End of 2D write delay Voltage center optimization
359 23:52:00.019686 INFO : End of 2D write delay Voltage center optimization
360 23:52:00.025252 INFO : Training has run successfully!
361 23:52:00.025780
362 23:52:00.026282 channel==0
363 23:52:00.030834 RxClkDly_Margin_A0==88 ps 9
364 23:52:00.031363 TxDqDly_Margin_A0==98 ps 10
365 23:52:00.036433 RxClkDly_Margin_A1==88 ps 9
366 23:52:00.036958 TxDqDly_Margin_A1==98 ps 10
367 23:52:00.037462 TrainedVREFDQ_A0==74
368 23:52:00.042041 TrainedVREFDQ_A1==75
369 23:52:00.042566 VrefDac_Margin_A0==24
370 23:52:00.043063 DeviceVref_Margin_A0==40
371 23:52:00.047640 VrefDac_Margin_A1==23
372 23:52:00.048188 DeviceVref_Margin_A1==39
373 23:52:00.048677
374 23:52:00.049177
375 23:52:00.053242 channel==1
376 23:52:00.053758 RxClkDly_Margin_A0==88 ps 9
377 23:52:00.054261 TxDqDly_Margin_A0==98 ps 10
378 23:52:00.058822 RxClkDly_Margin_A1==88 ps 9
379 23:52:00.059354 TxDqDly_Margin_A1==88 ps 9
380 23:52:00.064443 TrainedVREFDQ_A0==78
381 23:52:00.064967 TrainedVREFDQ_A1==75
382 23:52:00.065470 VrefDac_Margin_A0==22
383 23:52:00.070046 DeviceVref_Margin_A0==36
384 23:52:00.070560 VrefDac_Margin_A1==23
385 23:52:00.075627 DeviceVref_Margin_A1==39
386 23:52:00.076167
387 23:52:00.076673 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
388 23:52:00.077173
389 23:52:00.109260 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000018 00000017 00000018 00000018 00000017 00000018 00000015 00000018 00000014 00000015 00000017 00000018 00000019 00000018 00000018 0000001c 00000018 00000016 00000017 dram_vref_reg_value 0x 00000061
390 23:52:00.109869 2D training succeed
391 23:52:00.114818 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
392 23:52:00.120432 auto size-- 65535DDR cs0 size: 2048MB
393 23:52:00.120951 DDR cs1 size: 2048MB
394 23:52:00.126041 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
395 23:52:00.126570 cs0 DataBus test pass
396 23:52:00.131635 cs1 DataBus test pass
397 23:52:00.132194 cs0 AddrBus test pass
398 23:52:00.132701 cs1 AddrBus test pass
399 23:52:00.133198
400 23:52:00.137243 100bdlr_step_size ps== 478
401 23:52:00.137780 result report
402 23:52:00.142832 boot times 0Enable ddr reg access
403 23:52:00.148179 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
404 23:52:00.161925 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
405 23:52:00.817254 bl2z: ptr: 05129330, size: 00001e40
406 23:52:00.825121 0.0;M3 CHK:0;cm4_sp_mode 0
407 23:52:00.825687 MVN_1=0x00000000
408 23:52:00.826198 MVN_2=0x00000000
409 23:52:00.836626 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
410 23:52:00.837172 OPS=0x04
411 23:52:00.837685 ring efuse init
412 23:52:00.842254 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
413 23:52:00.842783 [0.017319 Inits done]
414 23:52:00.843285 secure task start!
415 23:52:00.850121 high task start!
416 23:52:00.850652 low task start!
417 23:52:00.851141 run into bl31
418 23:52:00.858656 NOTICE: BL31: v1.3(release):4fc40b1
419 23:52:00.866474 NOTICE: BL31: Built : 15:57:33, May 22 2019
420 23:52:00.867007 NOTICE: BL31: G12A normal boot!
421 23:52:00.882051 NOTICE: BL31: BL33 decompress pass
422 23:52:00.887679 ERROR: Error initializing runtime service opteed_fast
423 23:52:02.134310 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
424 23:52:02.134971 bl2_stage_init 0x01
425 23:52:02.135510 bl2_stage_init 0x81
426 23:52:02.139872 hw id: 0x0000 - pwm id 0x01
427 23:52:02.140460 bl2_stage_init 0xc1
428 23:52:02.145486 bl2_stage_init 0x02
429 23:52:02.146035
430 23:52:02.146569 L0:00000000
431 23:52:02.147081 L1:00000703
432 23:52:02.147589 L2:00008067
433 23:52:02.148120 L3:15000000
434 23:52:02.151505 S1:00000000
435 23:52:02.152079 B2:20282000
436 23:52:02.152609 B1:a0f83180
437 23:52:02.153118
438 23:52:02.153623 TE: 68349
439 23:52:02.154128
440 23:52:02.157116 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
441 23:52:02.157650
442 23:52:02.162714 Board ID = 1
443 23:52:02.163250 Set cpu clk to 24M
444 23:52:02.163760 Set clk81 to 24M
445 23:52:02.168315 Use GP1_pll as DSU clk.
446 23:52:02.168853 DSU clk: 1200 Mhz
447 23:52:02.169364 CPU clk: 1200 MHz
448 23:52:02.169867 Set clk81 to 166.6M
449 23:52:02.179501 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
450 23:52:02.180065 board id: 1
451 23:52:02.186298 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
452 23:52:02.196930 fw parse done
453 23:52:02.202881 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
454 23:52:02.245644 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
455 23:52:02.256501 PIEI prepare done
456 23:52:02.257043 fastboot data load
457 23:52:02.257557 fastboot data verify
458 23:52:02.262066 verify result: 266
459 23:52:02.267702 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
460 23:52:02.268283 LPDDR4 probe
461 23:52:02.268807 ddr clk to 1584MHz
462 23:52:03.636319 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c00 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
463 23:52:03.637098 bl2_stage_init 0x01
464 23:52:03.637670 bl2_stage_init 0x81
465 23:52:03.641912 hw id: 0x0000 - pwm id 0x01
466 23:52:03.642494 bl2_stage_init 0xc1
467 23:52:03.647504 bl2_stage_init 0x02
468 23:52:03.648156
469 23:52:03.648664 L0:00000000
470 23:52:03.649161 L1:00000703
471 23:52:03.649657 L2:00008067
472 23:52:03.650143 L3:15000000
473 23:52:03.653097 S1:00000000
474 23:52:03.653647 B2:20282000
475 23:52:03.654143 B1:a0f83180
476 23:52:03.654626
477 23:52:03.655119 TE: 70600
478 23:52:03.655598
479 23:52:03.658691 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
480 23:52:03.659221
481 23:52:03.664277 Board ID = 1
482 23:52:03.664790 Set cpu clk to 24M
483 23:52:03.665284 Set clk81 to 24M
484 23:52:03.669878 Use GP1_pll as DSU clk.
485 23:52:03.670392 DSU clk: 1200 Mhz
486 23:52:03.670887 CPU clk: 1200 MHz
487 23:52:03.675466 Set clk81 to 166.6M
488 23:52:03.681064 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
489 23:52:03.681582 board id: 1
490 23:52:03.688253 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
491 23:52:03.699208 fw parse done
492 23:52:03.705135 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
493 23:52:03.748689 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
494 23:52:03.759440 PIEI prepare done
495 23:52:03.760049 fastboot data load
496 23:52:03.760561 fastboot data verify
497 23:52:03.765035 verify result: 266
498 23:52:03.770630 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
499 23:52:03.771154 LPDDR4 probe
500 23:52:03.771653 ddr clk to 1584MHz
501 23:52:03.778592 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
502 23:52:03.816343
503 23:52:03.816917 dmc_version 0001
504 23:52:03.823361 Check phy result
505 23:52:03.829343 INFO : End of CA training
506 23:52:03.829871 INFO : End of initialization
507 23:52:03.834961 INFO : Training has run successfully!
508 23:52:03.835555 Check phy result
509 23:52:03.840583 INFO : End of initialization
510 23:52:03.841133 INFO : End of read enable training
511 23:52:03.846138 INFO : End of fine write leveling
512 23:52:03.851736 INFO : End of Write leveling coarse delay
513 23:52:03.852307 INFO : Training has run successfully!
514 23:52:03.852825 Check phy result
515 23:52:03.857345 INFO : End of initialization
516 23:52:03.857887 INFO : End of read dq deskew training
517 23:52:03.862947 INFO : End of MPR read delay center optimization
518 23:52:03.868539 INFO : End of write delay center optimization
519 23:52:03.874154 INFO : End of read delay center optimization
520 23:52:03.874704 INFO : End of max read latency training
521 23:52:03.879762 INFO : Training has run successfully!
522 23:52:03.880345 1D training succeed
523 23:52:03.888944 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
524 23:52:03.937185 Check phy result
525 23:52:03.937724 INFO : End of initialization
526 23:52:03.964626 INFO : End of 2D read delay Voltage center optimization
527 23:52:03.988752 INFO : End of 2D read delay Voltage center optimization
528 23:52:04.045382 INFO : End of 2D write delay Voltage center optimization
529 23:52:04.099379 INFO : End of 2D write delay Voltage center optimization
530 23:52:04.104974 INFO : Training has run successfully!
531 23:52:04.105524
532 23:52:04.106057 channel==0
533 23:52:04.110593 RxClkDly_Margin_A0==78 ps 8
534 23:52:04.111133 TxDqDly_Margin_A0==98 ps 10
535 23:52:04.116218 RxClkDly_Margin_A1==78 ps 8
536 23:52:04.116759 TxDqDly_Margin_A1==98 ps 10
537 23:52:04.117275 TrainedVREFDQ_A0==74
538 23:52:04.121774 TrainedVREFDQ_A1==75
539 23:52:04.122314 VrefDac_Margin_A0==23
540 23:52:04.122825 DeviceVref_Margin_A0==40
541 23:52:04.127372 VrefDac_Margin_A1==23
542 23:52:04.127910 DeviceVref_Margin_A1==39
543 23:52:04.128468
544 23:52:04.128981
545 23:52:04.132970 channel==1
546 23:52:04.133503 RxClkDly_Margin_A0==88 ps 9
547 23:52:04.134015 TxDqDly_Margin_A0==98 ps 10
548 23:52:04.138553 RxClkDly_Margin_A1==78 ps 8
549 23:52:04.139078 TxDqDly_Margin_A1==88 ps 9
550 23:52:04.144192 TrainedVREFDQ_A0==78
551 23:52:04.144738 TrainedVREFDQ_A1==78
552 23:52:04.145254 VrefDac_Margin_A0==22
553 23:52:04.149772 DeviceVref_Margin_A0==36
554 23:52:04.150321 VrefDac_Margin_A1==22
555 23:52:04.155385 DeviceVref_Margin_A1==36
556 23:52:04.155932
557 23:52:04.156502 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
558 23:52:04.157025
559 23:52:04.188974 soc_vref_reg_value 0x 00000019 00000018 00000018 00000016 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000017 00000018 00000018 00000018 00000017 00000018 00000015 00000017 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001c 00000018 00000016 00000017 dram_vref_reg_value 0x 00000061
560 23:52:04.189571 2D training succeed
561 23:52:04.194564 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
562 23:52:04.200200 auto size-- 65535DDR cs0 size: 2048MB
563 23:52:04.200731 DDR cs1 size: 2048MB
564 23:52:04.205769 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
565 23:52:04.206319 cs0 DataBus test pass
566 23:52:04.211383 cs1 DataBus test pass
567 23:52:04.211912 cs0 AddrBus test pass
568 23:52:04.212472 cs1 AddrBus test pass
569 23:52:04.212979
570 23:52:04.216965 100bdlr_step_size ps== 471
571 23:52:04.217513 result report
572 23:52:04.222555 boot times 0Enable ddr reg access
573 23:52:04.227843 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
574 23:52:04.241704 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
575 23:52:04.902535 bl2z: ptr: 05129330, size: 00001e40
576 23:52:04.911132 0.0;M3 CHK:0;cm4_sp_mode 0
577 23:52:04.911718 MVN_1=0x00000000
578 23:52:04.912288 MVN_2=0x00000000
579 23:52:04.922708 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
580 23:52:04.923268 OPS=0x04
581 23:52:04.923787 ring efuse init
582 23:52:04.928305 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
583 23:52:04.928858 [0.017354 Inits done]
584 23:52:04.929372 secure task start!
585 23:52:04.936434 high task start!
586 23:52:04.936964 low task start!
587 23:52:04.937475 run into bl31
588 23:52:04.944921 NOTICE: BL31: v1.3(release):4fc40b1
589 23:52:04.952760 NOTICE: BL31: Built : 15:57:33, May 22 2019
590 23:52:04.953310 NOTICE: BL31: G12A normal boot!
591 23:52:04.968382 NOTICE: BL31: BL33 decompress pass
592 23:52:04.974101 ERROR: Error initializing runtime service opteed_fast
593 23:52:06.338592 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
594 23:52:06.339266 bl2_stage_init 0x01
595 23:52:06.339819 bl2_stage_init 0x81
596 23:52:06.344166 hw id: 0x0000 - pwm id 0x01
597 23:52:06.344733 bl2_stage_init 0xc1
598 23:52:06.349869 bl2_stage_init 0x02
599 23:52:06.350415
600 23:52:06.350931 L0:00000000
601 23:52:06.351439 L1:00000703
602 23:52:06.351944 L2:00008067
603 23:52:06.352514 L3:15000000
604 23:52:06.355473 S1:00000000
605 23:52:06.356041 B2:20282000
606 23:52:06.356567 B1:a0f83180
607 23:52:06.357071
608 23:52:06.357579 TE: 72533
609 23:52:06.358083
610 23:52:06.361005 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
611 23:52:06.361552
612 23:52:06.366657 Board ID = 1
613 23:52:06.367185 Set cpu clk to 24M
614 23:52:06.367705 Set clk81 to 24M
615 23:52:06.370132 Use GP1_pll as DSU clk.
616 23:52:06.370678 DSU clk: 1200 Mhz
617 23:52:06.375652 CPU clk: 1200 MHz
618 23:52:06.376239 Set clk81 to 166.6M
619 23:52:06.381186 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
620 23:52:06.381738 board id: 1
621 23:52:06.390521 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
622 23:52:06.401180 fw parse done
623 23:52:06.407192 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
624 23:52:06.449905 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
625 23:52:06.460744 PIEI prepare done
626 23:52:06.461302 fastboot data load
627 23:52:06.461834 fastboot data verify
628 23:52:06.466328 verify result: 266
629 23:52:06.471962 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
630 23:52:06.472551 LPDDR4 probe
631 23:52:06.473070 ddr clk to 1584MHz
632 23:52:06.479945 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
633 23:52:06.517234
634 23:52:06.517815 dmc_version 0001
635 23:52:06.523925 Check phy result
636 23:52:06.529799 INFO : End of CA training
637 23:52:06.530340 INFO : End of initialization
638 23:52:06.535434 INFO : Training has run successfully!
639 23:52:06.535965 Check phy result
640 23:52:06.541002 INFO : End of initialization
641 23:52:06.541543 INFO : End of read enable training
642 23:52:06.546607 INFO : End of fine write leveling
643 23:52:06.552237 INFO : End of Write leveling coarse delay
644 23:52:06.552779 INFO : Training has run successfully!
645 23:52:06.553293 Check phy result
646 23:52:06.557834 INFO : End of initialization
647 23:52:06.558372 INFO : End of read dq deskew training
648 23:52:06.563405 INFO : End of MPR read delay center optimization
649 23:52:06.568950 INFO : End of write delay center optimization
650 23:52:06.574586 INFO : End of read delay center optimization
651 23:52:06.575125 INFO : End of max read latency training
652 23:52:06.580238 INFO : Training has run successfully!
653 23:52:06.580775 1D training succeed
654 23:52:06.589388 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
655 23:52:06.636887 Check phy result
656 23:52:06.637443 INFO : End of initialization
657 23:52:06.659270 INFO : End of 2D read delay Voltage center optimization
658 23:52:06.678416 INFO : End of 2D read delay Voltage center optimization
659 23:52:06.730329 INFO : End of 2D write delay Voltage center optimization
660 23:52:06.779439 INFO : End of 2D write delay Voltage center optimization
661 23:52:06.785040 INFO : Training has run successfully!
662 23:52:06.785614
663 23:52:06.786162 channel==0
664 23:52:06.790631 RxClkDly_Margin_A0==78 ps 8
665 23:52:06.791186 TxDqDly_Margin_A0==98 ps 10
666 23:52:06.793934 RxClkDly_Margin_A1==69 ps 7
667 23:52:06.794475 TxDqDly_Margin_A1==98 ps 10
668 23:52:06.799458 TrainedVREFDQ_A0==74
669 23:52:06.800028 TrainedVREFDQ_A1==75
670 23:52:06.805078 VrefDac_Margin_A0==23
671 23:52:06.805619 DeviceVref_Margin_A0==40
672 23:52:06.806134 VrefDac_Margin_A1==23
673 23:52:06.810692 DeviceVref_Margin_A1==39
674 23:52:06.811243
675 23:52:06.811756
676 23:52:06.812311 channel==1
677 23:52:06.812820 RxClkDly_Margin_A0==78 ps 8
678 23:52:06.816244 TxDqDly_Margin_A0==98 ps 10
679 23:52:06.816788 RxClkDly_Margin_A1==78 ps 8
680 23:52:06.821934 TxDqDly_Margin_A1==88 ps 9
681 23:52:06.822473 TrainedVREFDQ_A0==78
682 23:52:06.822985 TrainedVREFDQ_A1==77
683 23:52:06.827476 VrefDac_Margin_A0==22
684 23:52:06.828042 DeviceVref_Margin_A0==36
685 23:52:06.833073 VrefDac_Margin_A1==22
686 23:52:06.833622 DeviceVref_Margin_A1==37
687 23:52:06.834143
688 23:52:06.838682 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
689 23:52:06.839227
690 23:52:06.866691 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000017 00000017 00000018 00000018 00000017 00000018 00000015 00000018 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001c 00000017 00000016 00000017 dram_vref_reg_value 0x 00000061
691 23:52:06.872280 2D training succeed
692 23:52:06.877948 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
693 23:52:06.878500 auto size-- 65535DDR cs0 size: 2048MB
694 23:52:06.883477 DDR cs1 size: 2048MB
695 23:52:06.884065 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
696 23:52:06.889061 cs0 DataBus test pass
697 23:52:06.889600 cs1 DataBus test pass
698 23:52:06.890112 cs0 AddrBus test pass
699 23:52:06.894685 cs1 AddrBus test pass
700 23:52:06.895213
701 23:52:06.895740 100bdlr_step_size ps== 478
702 23:52:06.896286 result report
703 23:52:06.900271 boot times 0Enable ddr reg access
704 23:52:06.907885 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
705 23:52:06.921725 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
706 23:52:07.575686 bl2z: ptr: 05129330, size: 00001e40
707 23:52:07.582180 0.0;M3 CHK:0;cm4_sp_mode 0
708 23:52:07.582749 MVN_1=0x00000000
709 23:52:07.583267 MVN_2=0x00000000
710 23:52:07.593700 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
711 23:52:07.594290 OPS=0x04
712 23:52:07.594825 ring efuse init
713 23:52:07.599301 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
714 23:52:07.599877 [0.017310 Inits done]
715 23:52:07.600436 secure task start!
716 23:52:07.606882 high task start!
717 23:52:07.607488 low task start!
718 23:52:07.608046 run into bl31
719 23:52:07.615446 NOTICE: BL31: v1.3(release):4fc40b1
720 23:52:07.623229 NOTICE: BL31: Built : 15:57:33, May 22 2019
721 23:52:07.623785 NOTICE: BL31: G12A normal boot!
722 23:52:07.638780 NOTICE: BL31: BL33 decompress pass
723 23:52:07.644452 ERROR: Error initializing runtime service opteed_fast
724 23:52:08.438608
725 23:52:08.439282
726 23:52:08.443934 U-Boot 2024.01-rc4+ (Dec 14 2023 - 02:26:00 -0500) Libre Computer AML-S905D3-CC
727 23:52:08.444522
728 23:52:08.447437 Model: Libre Computer AML-S905D3-CC Solitude
729 23:52:08.594252 SoC: Amlogic Meson SM1 (S905D3) Revision 2b:c (4:2)
730 23:52:08.609644 DRAM: 2 GiB (effective 3.8 GiB)
731 23:52:08.710559 Core: 406 devices, 33 uclasses, devicetree: separate
732 23:52:08.716495 WDT: Not starting watchdog@f0d0
733 23:52:08.741551 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
734 23:52:08.753789 Loading Environment from FAT... Card did not respond to voltage select! : -110
735 23:52:08.758775 ** Bad device specification mmc 0 **
736 23:52:08.768847 Card did not respond to voltage select! : -110
737 23:52:08.776503 ** Bad device specification mmc 0 **
738 23:52:08.777093 Couldn't find partition mmc 0
739 23:52:08.784797 Card did not respond to voltage select! : -110
740 23:52:08.790380 ** Bad device specification mmc 0 **
741 23:52:08.790950 Couldn't find partition mmc 0
742 23:52:08.795462 Error: could not access storage.
743 23:52:09.091811 Net: eth0: ethernet@ff3f0000
744 23:52:09.092394 starting USB...
745 23:52:09.336541 Bus usb@ff500000: Register 3000140 NbrPorts 3
746 23:52:09.337086 Starting the controller
747 23:52:09.343528 USB XHCI 1.10
748 23:52:10.897316 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
749 23:52:10.905667 scanning usb for storage devices... 0 Storage Device(s) found
751 23:52:10.957369 Hit any key to stop autoboot: 1
752 23:52:10.958414 end: 2.4.2 bootloader-interrupt (duration 00:00:18) [common]
753 23:52:10.959161 start: 2.4.3 bootloader-commands (timeout 00:04:42) [common]
754 23:52:10.959709 Setting prompt string to ['=>']
755 23:52:10.960304 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:42)
756 23:52:10.971725 0
757 23:52:10.972789 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
759 23:52:11.074155 => setenv autoload no
760 23:52:11.075169 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:42)
761 23:52:11.080942 setenv autoload no
763 23:52:11.182570 => setenv initrd_high 0xffffffff
764 23:52:11.183529 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:42)
765 23:52:11.187784 setenv initrd_high 0xffffffff
767 23:52:11.289416 => setenv fdt_high 0xffffffff
768 23:52:11.290359 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:42)
769 23:52:11.294617 setenv fdt_high 0xffffffff
771 23:52:11.396234 => dhcp
772 23:52:11.397171 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
773 23:52:11.401220 dhcp
774 23:52:12.307143 ethernet@ff3f0000 Waiting for PHY auto negotiation to complete.. done
775 23:52:12.307757 Speed: 1000, full duplex
776 23:52:12.308331 BOOTP broadcast 1
777 23:52:12.319546 DHCP client bound to address 192.168.6.21 (12 ms)
779 23:52:12.421180 => setenv serverip 192.168.6.2
780 23:52:12.422142 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
781 23:52:12.426673 setenv serverip 192.168.6.2
783 23:52:12.528269 => tftpboot 0x01080000 943308/tftp-deploy-l2zn3scx/kernel/uImage
784 23:52:12.529086 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
785 23:52:12.536665 tftpboot 0x01080000 943308/tftp-deploy-l2zn3scx/kernel/uImage
786 23:52:12.537263 Speed: 1000, full duplex
787 23:52:12.537737 Using ethernet@ff3f0000 device
788 23:52:12.542198 TFTP from server 192.168.6.2; our IP address is 192.168.6.21
789 23:52:12.547737 Filename '943308/tftp-deploy-l2zn3scx/kernel/uImage'.
790 23:52:12.551658 Load address: 0x1080000
791 23:52:15.375126 Loading: *################################################## 43.6 MiB
792 23:52:15.375543 15.4 MiB/s
793 23:52:15.375765 done
794 23:52:15.379705 Bytes transferred = 45716032 (2b99240 hex)
796 23:52:15.481455 => tftpboot 0x08000000 943308/tftp-deploy-l2zn3scx/ramdisk/ramdisk.cpio.gz.uboot
797 23:52:15.482226 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:37)
798 23:52:15.489097 tftpboot 0x08000000 943308/tftp-deploy-l2zn3scx/ramdisk/ramdisk.cpio.gz.uboot
799 23:52:15.489634 Speed: 1000, full duplex
800 23:52:15.490075 Using ethernet@ff3f0000 device
801 23:52:15.494622 TFTP from server 192.168.6.2; our IP address is 192.168.6.21
802 23:52:15.504428 Filename '943308/tftp-deploy-l2zn3scx/ramdisk/ramdisk.cpio.gz.uboot'.
803 23:52:15.504963 Load address: 0x8000000
804 23:52:25.773253 Loading: *##########################T ####################### UDP wrong checksum 0000000f 0000d02d
805 23:52:30.774038 T UDP wrong checksum 0000000f 0000d02d
806 23:52:40.776344 T T UDP wrong checksum 0000000f 0000d02d
807 23:53:00.781047 T T T T UDP wrong checksum 0000000f 0000d02d
808 23:53:15.784995 T T
809 23:53:15.785673 Retry count exceeded; starting again
811 23:53:15.787216 end: 2.4.3 bootloader-commands (duration 00:01:05) [common]
814 23:53:15.789419 end: 2.4 uboot-commands (duration 00:01:23) [common]
816 23:53:15.790965 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
818 23:53:15.792196 end: 2 uboot-action (duration 00:01:23) [common]
820 23:53:15.793870 Cleaning after the job
821 23:53:15.794460 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/943308/tftp-deploy-l2zn3scx/ramdisk
822 23:53:15.795868 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/943308/tftp-deploy-l2zn3scx/kernel
823 23:53:15.842941 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/943308/tftp-deploy-l2zn3scx/dtb
824 23:53:15.843670 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/943308/tftp-deploy-l2zn3scx/modules
825 23:53:15.861728 start: 4.1 power-off (timeout 00:00:30) [common]
826 23:53:15.862329 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=solitude-01'
827 23:53:15.894831 >> OK - accepted request
828 23:53:15.897102 Returned 0 in 0 seconds
829 23:53:15.998129 end: 4.1 power-off (duration 00:00:00) [common]
831 23:53:15.999066 start: 4.2 read-feedback (timeout 00:10:00) [common]
832 23:53:15.999698 Listened to connection for namespace 'common' for up to 1s
833 23:53:17.000050 Finalising connection for namespace 'common'
834 23:53:17.000799 Disconnecting from shell: Finalise
835 23:53:17.001358 =>
836 23:53:17.102411 end: 4.2 read-feedback (duration 00:00:01) [common]
837 23:53:17.103112 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/943308
838 23:53:17.736910 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/943308
839 23:53:17.737541 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.