Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 1
- Kernel Warnings: 8
- Errors: 0
- Boot result: PASS
- Kernel Errors: 6
1 23:36:32.060261 lava-dispatcher, installed at version: 2024.01
2 23:36:32.061189 start: 0 validate
3 23:36:32.061722 Start time: 2024-11-05 23:36:32.061689+00:00 (UTC)
4 23:36:32.062333 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 23:36:32.062966 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 23:36:32.103845 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 23:36:32.104500 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fpending-fixes%2Fv6.12-rc6-237-g47f01a19a6ee2%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 23:36:32.139283 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 23:36:32.139951 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fpending-fixes%2Fv6.12-rc6-237-g47f01a19a6ee2%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 23:36:32.174059 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 23:36:32.174565 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 23:36:32.211839 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 23:36:32.212401 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fpending-fixes%2Fv6.12-rc6-237-g47f01a19a6ee2%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
14 23:36:32.253904 validate duration: 0.19
16 23:36:32.255470 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 23:36:32.256111 start: 1.1 download-retry (timeout 00:10:00) [common]
18 23:36:32.256727 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 23:36:32.257811 Not decompressing ramdisk as can be used compressed.
20 23:36:32.258648 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 23:36:32.259172 saving as /var/lib/lava/dispatcher/tmp/943265/tftp-deploy-ni9yk04u/ramdisk/initrd.cpio.gz
22 23:36:32.259661 total size: 5628169 (5 MB)
23 23:36:32.301910 progress 0 % (0 MB)
24 23:36:32.307158 progress 5 % (0 MB)
25 23:36:32.317293 progress 10 % (0 MB)
26 23:36:32.325469 progress 15 % (0 MB)
27 23:36:32.330827 progress 20 % (1 MB)
28 23:36:32.335386 progress 25 % (1 MB)
29 23:36:32.340463 progress 30 % (1 MB)
30 23:36:32.345586 progress 35 % (1 MB)
31 23:36:32.350137 progress 40 % (2 MB)
32 23:36:32.355122 progress 45 % (2 MB)
33 23:36:32.359581 progress 50 % (2 MB)
34 23:36:32.364705 progress 55 % (2 MB)
35 23:36:32.369727 progress 60 % (3 MB)
36 23:36:32.374419 progress 65 % (3 MB)
37 23:36:32.379550 progress 70 % (3 MB)
38 23:36:32.384311 progress 75 % (4 MB)
39 23:36:32.389533 progress 80 % (4 MB)
40 23:36:32.394241 progress 85 % (4 MB)
41 23:36:32.399543 progress 90 % (4 MB)
42 23:36:32.404698 progress 95 % (5 MB)
43 23:36:32.408898 progress 100 % (5 MB)
44 23:36:32.409788 5 MB downloaded in 0.15 s (35.76 MB/s)
45 23:36:32.410479 end: 1.1.1 http-download (duration 00:00:00) [common]
47 23:36:32.411613 end: 1.1 download-retry (duration 00:00:00) [common]
48 23:36:32.412011 start: 1.2 download-retry (timeout 00:10:00) [common]
49 23:36:32.412369 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 23:36:32.412988 downloading http://storage.kernelci.org/next/pending-fixes/v6.12-rc6-237-g47f01a19a6ee2/arm64/defconfig/gcc-12/kernel/Image
51 23:36:32.413309 saving as /var/lib/lava/dispatcher/tmp/943265/tftp-deploy-ni9yk04u/kernel/Image
52 23:36:32.413568 total size: 45715968 (43 MB)
53 23:36:32.413831 No compression specified
54 23:36:32.453899 progress 0 % (0 MB)
55 23:36:32.483508 progress 5 % (2 MB)
56 23:36:32.513145 progress 10 % (4 MB)
57 23:36:32.543728 progress 15 % (6 MB)
58 23:36:32.573752 progress 20 % (8 MB)
59 23:36:32.603372 progress 25 % (10 MB)
60 23:36:32.633083 progress 30 % (13 MB)
61 23:36:32.663190 progress 35 % (15 MB)
62 23:36:32.693073 progress 40 % (17 MB)
63 23:36:32.722443 progress 45 % (19 MB)
64 23:36:32.752087 progress 50 % (21 MB)
65 23:36:32.781909 progress 55 % (24 MB)
66 23:36:32.811682 progress 60 % (26 MB)
67 23:36:32.841610 progress 65 % (28 MB)
68 23:36:32.871638 progress 70 % (30 MB)
69 23:36:32.902790 progress 75 % (32 MB)
70 23:36:32.933301 progress 80 % (34 MB)
71 23:36:32.962206 progress 85 % (37 MB)
72 23:36:32.991779 progress 90 % (39 MB)
73 23:36:33.021122 progress 95 % (41 MB)
74 23:36:33.049779 progress 100 % (43 MB)
75 23:36:33.050333 43 MB downloaded in 0.64 s (68.47 MB/s)
76 23:36:33.050806 end: 1.2.1 http-download (duration 00:00:01) [common]
78 23:36:33.051629 end: 1.2 download-retry (duration 00:00:01) [common]
79 23:36:33.051899 start: 1.3 download-retry (timeout 00:09:59) [common]
80 23:36:33.052193 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 23:36:33.052670 downloading http://storage.kernelci.org/next/pending-fixes/v6.12-rc6-237-g47f01a19a6ee2/arm64/defconfig/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
82 23:36:33.052941 saving as /var/lib/lava/dispatcher/tmp/943265/tftp-deploy-ni9yk04u/dtb/meson-g12b-a311d-libretech-cc.dtb
83 23:36:33.053147 total size: 54703 (0 MB)
84 23:36:33.053357 No compression specified
85 23:36:33.091605 progress 59 % (0 MB)
86 23:36:33.092478 progress 100 % (0 MB)
87 23:36:33.093035 0 MB downloaded in 0.04 s (1.31 MB/s)
88 23:36:33.093520 end: 1.3.1 http-download (duration 00:00:00) [common]
90 23:36:33.094338 end: 1.3 download-retry (duration 00:00:00) [common]
91 23:36:33.094601 start: 1.4 download-retry (timeout 00:09:59) [common]
92 23:36:33.094869 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 23:36:33.095329 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 23:36:33.095569 saving as /var/lib/lava/dispatcher/tmp/943265/tftp-deploy-ni9yk04u/nfsrootfs/full.rootfs.tar
95 23:36:33.095775 total size: 120894716 (115 MB)
96 23:36:33.096006 Using unxz to decompress xz
97 23:36:33.130563 progress 0 % (0 MB)
98 23:36:33.922446 progress 5 % (5 MB)
99 23:36:34.769440 progress 10 % (11 MB)
100 23:36:35.561685 progress 15 % (17 MB)
101 23:36:36.299147 progress 20 % (23 MB)
102 23:36:36.898778 progress 25 % (28 MB)
103 23:36:37.723459 progress 30 % (34 MB)
104 23:36:38.515274 progress 35 % (40 MB)
105 23:36:38.863302 progress 40 % (46 MB)
106 23:36:39.244351 progress 45 % (51 MB)
107 23:36:39.991469 progress 50 % (57 MB)
108 23:36:40.912315 progress 55 % (63 MB)
109 23:36:41.691332 progress 60 % (69 MB)
110 23:36:42.449976 progress 65 % (74 MB)
111 23:36:43.229848 progress 70 % (80 MB)
112 23:36:44.055977 progress 75 % (86 MB)
113 23:36:44.845733 progress 80 % (92 MB)
114 23:36:45.603762 progress 85 % (98 MB)
115 23:36:46.457122 progress 90 % (103 MB)
116 23:36:47.241354 progress 95 % (109 MB)
117 23:36:48.077585 progress 100 % (115 MB)
118 23:36:48.090054 115 MB downloaded in 14.99 s (7.69 MB/s)
119 23:36:48.090638 end: 1.4.1 http-download (duration 00:00:15) [common]
121 23:36:48.091460 end: 1.4 download-retry (duration 00:00:15) [common]
122 23:36:48.091724 start: 1.5 download-retry (timeout 00:09:44) [common]
123 23:36:48.092016 start: 1.5.1 http-download (timeout 00:09:44) [common]
124 23:36:48.093001 downloading http://storage.kernelci.org/next/pending-fixes/v6.12-rc6-237-g47f01a19a6ee2/arm64/defconfig/gcc-12/modules.tar.xz
125 23:36:48.093515 saving as /var/lib/lava/dispatcher/tmp/943265/tftp-deploy-ni9yk04u/modules/modules.tar
126 23:36:48.093963 total size: 11614632 (11 MB)
127 23:36:48.094419 Using unxz to decompress xz
128 23:36:48.142492 progress 0 % (0 MB)
129 23:36:48.209174 progress 5 % (0 MB)
130 23:36:48.282891 progress 10 % (1 MB)
131 23:36:48.378123 progress 15 % (1 MB)
132 23:36:48.469862 progress 20 % (2 MB)
133 23:36:48.549107 progress 25 % (2 MB)
134 23:36:48.624488 progress 30 % (3 MB)
135 23:36:48.702829 progress 35 % (3 MB)
136 23:36:48.775334 progress 40 % (4 MB)
137 23:36:48.851165 progress 45 % (5 MB)
138 23:36:48.935087 progress 50 % (5 MB)
139 23:36:49.011836 progress 55 % (6 MB)
140 23:36:49.096601 progress 60 % (6 MB)
141 23:36:49.178982 progress 65 % (7 MB)
142 23:36:49.259303 progress 70 % (7 MB)
143 23:36:49.340847 progress 75 % (8 MB)
144 23:36:49.423379 progress 80 % (8 MB)
145 23:36:49.502391 progress 85 % (9 MB)
146 23:36:49.584097 progress 90 % (10 MB)
147 23:36:49.656468 progress 95 % (10 MB)
148 23:36:49.731965 progress 100 % (11 MB)
149 23:36:49.743745 11 MB downloaded in 1.65 s (6.71 MB/s)
150 23:36:49.744717 end: 1.5.1 http-download (duration 00:00:02) [common]
152 23:36:49.746479 end: 1.5 download-retry (duration 00:00:02) [common]
153 23:36:49.747041 start: 1.6 prepare-tftp-overlay (timeout 00:09:43) [common]
154 23:36:49.747604 start: 1.6.1 extract-nfsrootfs (timeout 00:09:43) [common]
155 23:37:06.441950 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/943265/extract-nfsrootfs-4cipzu_g
156 23:37:06.442562 end: 1.6.1 extract-nfsrootfs (duration 00:00:17) [common]
157 23:37:06.442848 start: 1.6.2 lava-overlay (timeout 00:09:26) [common]
158 23:37:06.443467 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/943265/lava-overlay-eyuwy691
159 23:37:06.443910 makedir: /var/lib/lava/dispatcher/tmp/943265/lava-overlay-eyuwy691/lava-943265/bin
160 23:37:06.444282 makedir: /var/lib/lava/dispatcher/tmp/943265/lava-overlay-eyuwy691/lava-943265/tests
161 23:37:06.444608 makedir: /var/lib/lava/dispatcher/tmp/943265/lava-overlay-eyuwy691/lava-943265/results
162 23:37:06.444959 Creating /var/lib/lava/dispatcher/tmp/943265/lava-overlay-eyuwy691/lava-943265/bin/lava-add-keys
163 23:37:06.445518 Creating /var/lib/lava/dispatcher/tmp/943265/lava-overlay-eyuwy691/lava-943265/bin/lava-add-sources
164 23:37:06.446063 Creating /var/lib/lava/dispatcher/tmp/943265/lava-overlay-eyuwy691/lava-943265/bin/lava-background-process-start
165 23:37:06.446650 Creating /var/lib/lava/dispatcher/tmp/943265/lava-overlay-eyuwy691/lava-943265/bin/lava-background-process-stop
166 23:37:06.447354 Creating /var/lib/lava/dispatcher/tmp/943265/lava-overlay-eyuwy691/lava-943265/bin/lava-common-functions
167 23:37:06.447898 Creating /var/lib/lava/dispatcher/tmp/943265/lava-overlay-eyuwy691/lava-943265/bin/lava-echo-ipv4
168 23:37:06.448461 Creating /var/lib/lava/dispatcher/tmp/943265/lava-overlay-eyuwy691/lava-943265/bin/lava-install-packages
169 23:37:06.448977 Creating /var/lib/lava/dispatcher/tmp/943265/lava-overlay-eyuwy691/lava-943265/bin/lava-installed-packages
170 23:37:06.449475 Creating /var/lib/lava/dispatcher/tmp/943265/lava-overlay-eyuwy691/lava-943265/bin/lava-os-build
171 23:37:06.449964 Creating /var/lib/lava/dispatcher/tmp/943265/lava-overlay-eyuwy691/lava-943265/bin/lava-probe-channel
172 23:37:06.450478 Creating /var/lib/lava/dispatcher/tmp/943265/lava-overlay-eyuwy691/lava-943265/bin/lava-probe-ip
173 23:37:06.451011 Creating /var/lib/lava/dispatcher/tmp/943265/lava-overlay-eyuwy691/lava-943265/bin/lava-target-ip
174 23:37:06.451530 Creating /var/lib/lava/dispatcher/tmp/943265/lava-overlay-eyuwy691/lava-943265/bin/lava-target-mac
175 23:37:06.452048 Creating /var/lib/lava/dispatcher/tmp/943265/lava-overlay-eyuwy691/lava-943265/bin/lava-target-storage
176 23:37:06.452578 Creating /var/lib/lava/dispatcher/tmp/943265/lava-overlay-eyuwy691/lava-943265/bin/lava-test-case
177 23:37:06.453085 Creating /var/lib/lava/dispatcher/tmp/943265/lava-overlay-eyuwy691/lava-943265/bin/lava-test-event
178 23:37:06.453578 Creating /var/lib/lava/dispatcher/tmp/943265/lava-overlay-eyuwy691/lava-943265/bin/lava-test-feedback
179 23:37:06.454076 Creating /var/lib/lava/dispatcher/tmp/943265/lava-overlay-eyuwy691/lava-943265/bin/lava-test-raise
180 23:37:06.454560 Creating /var/lib/lava/dispatcher/tmp/943265/lava-overlay-eyuwy691/lava-943265/bin/lava-test-reference
181 23:37:06.455062 Creating /var/lib/lava/dispatcher/tmp/943265/lava-overlay-eyuwy691/lava-943265/bin/lava-test-runner
182 23:37:06.455618 Creating /var/lib/lava/dispatcher/tmp/943265/lava-overlay-eyuwy691/lava-943265/bin/lava-test-set
183 23:37:06.456179 Creating /var/lib/lava/dispatcher/tmp/943265/lava-overlay-eyuwy691/lava-943265/bin/lava-test-shell
184 23:37:06.456706 Updating /var/lib/lava/dispatcher/tmp/943265/lava-overlay-eyuwy691/lava-943265/bin/lava-add-keys (debian)
185 23:37:06.457244 Updating /var/lib/lava/dispatcher/tmp/943265/lava-overlay-eyuwy691/lava-943265/bin/lava-add-sources (debian)
186 23:37:06.457756 Updating /var/lib/lava/dispatcher/tmp/943265/lava-overlay-eyuwy691/lava-943265/bin/lava-install-packages (debian)
187 23:37:06.458273 Updating /var/lib/lava/dispatcher/tmp/943265/lava-overlay-eyuwy691/lava-943265/bin/lava-installed-packages (debian)
188 23:37:06.458813 Updating /var/lib/lava/dispatcher/tmp/943265/lava-overlay-eyuwy691/lava-943265/bin/lava-os-build (debian)
189 23:37:06.459293 Creating /var/lib/lava/dispatcher/tmp/943265/lava-overlay-eyuwy691/lava-943265/environment
190 23:37:06.459701 LAVA metadata
191 23:37:06.459970 - LAVA_JOB_ID=943265
192 23:37:06.460211 - LAVA_DISPATCHER_IP=192.168.6.2
193 23:37:06.460602 start: 1.6.2.1 ssh-authorize (timeout 00:09:26) [common]
194 23:37:06.461694 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
195 23:37:06.462033 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:26) [common]
196 23:37:06.462240 skipped lava-vland-overlay
197 23:37:06.462479 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
198 23:37:06.462730 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:26) [common]
199 23:37:06.462948 skipped lava-multinode-overlay
200 23:37:06.463189 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
201 23:37:06.463436 start: 1.6.2.4 test-definition (timeout 00:09:26) [common]
202 23:37:06.463683 Loading test definitions
203 23:37:06.463954 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:26) [common]
204 23:37:06.464205 Using /lava-943265 at stage 0
205 23:37:06.465308 uuid=943265_1.6.2.4.1 testdef=None
206 23:37:06.465616 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
207 23:37:06.465875 start: 1.6.2.4.2 test-overlay (timeout 00:09:26) [common]
208 23:37:06.467437 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
210 23:37:06.468251 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:26) [common]
211 23:37:06.470185 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
213 23:37:06.471028 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:26) [common]
214 23:37:06.473182 runner path: /var/lib/lava/dispatcher/tmp/943265/lava-overlay-eyuwy691/lava-943265/0/tests/0_timesync-off test_uuid 943265_1.6.2.4.1
215 23:37:06.473994 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
217 23:37:06.474934 start: 1.6.2.4.5 git-repo-action (timeout 00:09:26) [common]
218 23:37:06.475172 Using /lava-943265 at stage 0
219 23:37:06.475565 Fetching tests from https://github.com/kernelci/test-definitions.git
220 23:37:06.475882 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/943265/lava-overlay-eyuwy691/lava-943265/0/tests/1_kselftest-alsa'
221 23:37:10.237912 Running '/usr/bin/git checkout kernelci.org
222 23:37:10.471489 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/943265/lava-overlay-eyuwy691/lava-943265/0/tests/1_kselftest-alsa/automated/linux/kselftest/kselftest.yaml
223 23:37:10.472938 uuid=943265_1.6.2.4.5 testdef=None
224 23:37:10.473285 end: 1.6.2.4.5 git-repo-action (duration 00:00:04) [common]
226 23:37:10.474029 start: 1.6.2.4.6 test-overlay (timeout 00:09:22) [common]
227 23:37:10.476842 end: 1.6.2.4.6 test-overlay (duration 00:00:00) [common]
229 23:37:10.477655 start: 1.6.2.4.7 test-install-overlay (timeout 00:09:22) [common]
230 23:37:10.483052 end: 1.6.2.4.7 test-install-overlay (duration 00:00:00) [common]
232 23:37:10.484878 start: 1.6.2.4.8 test-runscript-overlay (timeout 00:09:22) [common]
233 23:37:10.491815 runner path: /var/lib/lava/dispatcher/tmp/943265/lava-overlay-eyuwy691/lava-943265/0/tests/1_kselftest-alsa test_uuid 943265_1.6.2.4.5
234 23:37:10.492361 BOARD='meson-g12b-a311d-libretech-cc'
235 23:37:10.492767 BRANCH='next'
236 23:37:10.493157 SKIPFILE='/dev/null'
237 23:37:10.493548 SKIP_INSTALL='True'
238 23:37:10.493937 TESTPROG_URL='http://storage.kernelci.org/next/pending-fixes/v6.12-rc6-237-g47f01a19a6ee2/arm64/defconfig/gcc-12/kselftest.tar.xz'
239 23:37:10.494335 TST_CASENAME=''
240 23:37:10.494722 TST_CMDFILES='alsa'
241 23:37:10.495682 end: 1.6.2.4.8 test-runscript-overlay (duration 00:00:00) [common]
243 23:37:10.497244 Creating lava-test-runner.conf files
244 23:37:10.497640 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/943265/lava-overlay-eyuwy691/lava-943265/0 for stage 0
245 23:37:10.498292 - 0_timesync-off
246 23:37:10.498738 - 1_kselftest-alsa
247 23:37:10.499352 end: 1.6.2.4 test-definition (duration 00:00:04) [common]
248 23:37:10.499876 start: 1.6.2.5 compress-overlay (timeout 00:09:22) [common]
249 23:37:33.583776 end: 1.6.2.5 compress-overlay (duration 00:00:23) [common]
250 23:37:33.584241 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:08:59) [common]
251 23:37:33.584532 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
252 23:37:33.584831 end: 1.6.2 lava-overlay (duration 00:00:27) [common]
253 23:37:33.585116 start: 1.6.3 extract-overlay-ramdisk (timeout 00:08:59) [common]
254 23:37:34.211663 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:01) [common]
255 23:37:34.212148 start: 1.6.4 extract-modules (timeout 00:08:58) [common]
256 23:37:34.212428 extracting modules file /var/lib/lava/dispatcher/tmp/943265/tftp-deploy-ni9yk04u/modules/modules.tar to /var/lib/lava/dispatcher/tmp/943265/extract-nfsrootfs-4cipzu_g
257 23:37:35.580433 extracting modules file /var/lib/lava/dispatcher/tmp/943265/tftp-deploy-ni9yk04u/modules/modules.tar to /var/lib/lava/dispatcher/tmp/943265/extract-overlay-ramdisk-dw1jpsv0/ramdisk
258 23:37:37.062336 end: 1.6.4 extract-modules (duration 00:00:03) [common]
259 23:37:37.062815 start: 1.6.5 apply-overlay-tftp (timeout 00:08:55) [common]
260 23:37:37.063064 [common] Applying overlay to NFS
261 23:37:37.063270 [common] Applying overlay /var/lib/lava/dispatcher/tmp/943265/compress-overlay-3jx7kr5f/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/943265/extract-nfsrootfs-4cipzu_g
262 23:37:39.796808 end: 1.6.5 apply-overlay-tftp (duration 00:00:03) [common]
263 23:37:39.797259 start: 1.6.6 prepare-kernel (timeout 00:08:52) [common]
264 23:37:39.797528 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:08:52) [common]
265 23:37:39.797757 Converting downloaded kernel to a uImage
266 23:37:39.798063 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/943265/tftp-deploy-ni9yk04u/kernel/Image /var/lib/lava/dispatcher/tmp/943265/tftp-deploy-ni9yk04u/kernel/uImage
267 23:37:40.251830 output: Image Name:
268 23:37:40.252282 output: Created: Tue Nov 5 23:37:39 2024
269 23:37:40.252489 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
270 23:37:40.252692 output: Data Size: 45715968 Bytes = 44644.50 KiB = 43.60 MiB
271 23:37:40.252890 output: Load Address: 01080000
272 23:37:40.253086 output: Entry Point: 01080000
273 23:37:40.253283 output:
274 23:37:40.253614 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
275 23:37:40.253875 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
276 23:37:40.254139 start: 1.6.7 configure-preseed-file (timeout 00:08:52) [common]
277 23:37:40.254387 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
278 23:37:40.254640 start: 1.6.8 compress-ramdisk (timeout 00:08:52) [common]
279 23:37:40.254868 Building ramdisk /var/lib/lava/dispatcher/tmp/943265/extract-overlay-ramdisk-dw1jpsv0/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/943265/extract-overlay-ramdisk-dw1jpsv0/ramdisk
280 23:37:42.624321 >> 166830 blocks
281 23:37:50.382707 Adding RAMdisk u-boot header.
282 23:37:50.383419 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/943265/extract-overlay-ramdisk-dw1jpsv0/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/943265/extract-overlay-ramdisk-dw1jpsv0/ramdisk.cpio.gz.uboot
283 23:37:50.631623 output: Image Name:
284 23:37:50.632290 output: Created: Tue Nov 5 23:37:50 2024
285 23:37:50.632756 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
286 23:37:50.633206 output: Data Size: 23435192 Bytes = 22885.93 KiB = 22.35 MiB
287 23:37:50.633651 output: Load Address: 00000000
288 23:37:50.634088 output: Entry Point: 00000000
289 23:37:50.634524 output:
290 23:37:50.635621 rename /var/lib/lava/dispatcher/tmp/943265/extract-overlay-ramdisk-dw1jpsv0/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/943265/tftp-deploy-ni9yk04u/ramdisk/ramdisk.cpio.gz.uboot
291 23:37:50.636435 end: 1.6.8 compress-ramdisk (duration 00:00:10) [common]
292 23:37:50.637039 end: 1.6 prepare-tftp-overlay (duration 00:01:01) [common]
293 23:37:50.637615 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:42) [common]
294 23:37:50.638117 No LXC device requested
295 23:37:50.638676 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
296 23:37:50.639249 start: 1.8 deploy-device-env (timeout 00:08:42) [common]
297 23:37:50.639802 end: 1.8 deploy-device-env (duration 00:00:00) [common]
298 23:37:50.640307 Checking files for TFTP limit of 4294967296 bytes.
299 23:37:50.643196 end: 1 tftp-deploy (duration 00:01:18) [common]
300 23:37:50.643816 start: 2 uboot-action (timeout 00:05:00) [common]
301 23:37:50.644433 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
302 23:37:50.644985 end: 2.1 uboot-from-media (duration 00:00:00) [common]
303 23:37:50.645540 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
304 23:37:50.646089 Using kernel file from prepare-kernel: 943265/tftp-deploy-ni9yk04u/kernel/uImage
305 23:37:50.646767 substitutions:
306 23:37:50.647217 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
307 23:37:50.647659 - {DTB_ADDR}: 0x01070000
308 23:37:50.648139 - {DTB}: 943265/tftp-deploy-ni9yk04u/dtb/meson-g12b-a311d-libretech-cc.dtb
309 23:37:50.648586 - {INITRD}: 943265/tftp-deploy-ni9yk04u/ramdisk/ramdisk.cpio.gz.uboot
310 23:37:50.649025 - {KERNEL_ADDR}: 0x01080000
311 23:37:50.649457 - {KERNEL}: 943265/tftp-deploy-ni9yk04u/kernel/uImage
312 23:37:50.649888 - {LAVA_MAC}: None
313 23:37:50.650336 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/943265/extract-nfsrootfs-4cipzu_g
314 23:37:50.650768 - {NFS_SERVER_IP}: 192.168.6.2
315 23:37:50.651192 - {PRESEED_CONFIG}: None
316 23:37:50.651622 - {PRESEED_LOCAL}: None
317 23:37:50.652106 - {RAMDISK_ADDR}: 0x08000000
318 23:37:50.652547 - {RAMDISK}: 943265/tftp-deploy-ni9yk04u/ramdisk/ramdisk.cpio.gz.uboot
319 23:37:50.652977 - {ROOT_PART}: None
320 23:37:50.653405 - {ROOT}: None
321 23:37:50.653828 - {SERVER_IP}: 192.168.6.2
322 23:37:50.654248 - {TEE_ADDR}: 0x83000000
323 23:37:50.654670 - {TEE}: None
324 23:37:50.655094 Parsed boot commands:
325 23:37:50.655507 - setenv autoload no
326 23:37:50.655930 - setenv initrd_high 0xffffffff
327 23:37:50.656407 - setenv fdt_high 0xffffffff
328 23:37:50.656832 - dhcp
329 23:37:50.657253 - setenv serverip 192.168.6.2
330 23:37:50.657677 - tftpboot 0x01080000 943265/tftp-deploy-ni9yk04u/kernel/uImage
331 23:37:50.658103 - tftpboot 0x08000000 943265/tftp-deploy-ni9yk04u/ramdisk/ramdisk.cpio.gz.uboot
332 23:37:50.658530 - tftpboot 0x01070000 943265/tftp-deploy-ni9yk04u/dtb/meson-g12b-a311d-libretech-cc.dtb
333 23:37:50.658952 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/943265/extract-nfsrootfs-4cipzu_g,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
334 23:37:50.659388 - bootm 0x01080000 0x08000000 0x01070000
335 23:37:50.659931 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
337 23:37:50.661582 start: 2.3 connect-device (timeout 00:05:00) [common]
338 23:37:50.662042 [common] connect-device Connecting to device using 'telnet conserv1 3007'
339 23:37:50.675951 Setting prompt string to ['lava-test: # ']
340 23:37:50.678083 end: 2.3 connect-device (duration 00:00:00) [common]
341 23:37:50.678936 start: 2.4 uboot-commands (timeout 00:05:00) [common]
342 23:37:50.679646 start: 2.4.1 reset-device (timeout 00:05:00) [common]
343 23:37:50.680267 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
344 23:37:50.681685 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
345 23:37:50.718612 >> OK - accepted request
346 23:37:50.720777 Returned 0 in 0 seconds
347 23:37:50.822031 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
349 23:37:50.823922 end: 2.4.1 reset-device (duration 00:00:00) [common]
350 23:37:50.824635 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
351 23:37:50.825235 Setting prompt string to ['Hit any key to stop autoboot']
352 23:37:50.825753 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
353 23:37:50.827600 Trying 192.168.56.21...
354 23:37:50.828201 Connected to conserv1.
355 23:37:50.828722 Escape character is '^]'.
356 23:37:50.829220
357 23:37:50.829695 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
358 23:37:50.830183
359 23:38:01.563813 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
360 23:38:01.564499 bl2_stage_init 0x01
361 23:38:01.565004 bl2_stage_init 0x81
362 23:38:01.569380 hw id: 0x0000 - pwm id 0x01
363 23:38:01.569972 bl2_stage_init 0xc1
364 23:38:01.570458 bl2_stage_init 0x02
365 23:38:01.570889
366 23:38:01.574792 L0:00000000
367 23:38:01.575328 L1:20000703
368 23:38:01.575770 L2:00008067
369 23:38:01.576260 L3:14000000
370 23:38:01.580486 B2:00402000
371 23:38:01.580950 B1:e0f83180
372 23:38:01.581401
373 23:38:01.581831 TE: 58167
374 23:38:01.582258
375 23:38:01.586082 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
376 23:38:01.586544
377 23:38:01.586973 Board ID = 1
378 23:38:01.591681 Set A53 clk to 24M
379 23:38:01.592171 Set A73 clk to 24M
380 23:38:01.592602 Set clk81 to 24M
381 23:38:01.597395 A53 clk: 1200 MHz
382 23:38:01.597856 A73 clk: 1200 MHz
383 23:38:01.598284 CLK81: 166.6M
384 23:38:01.598708 smccc: 00012abe
385 23:38:01.602859 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
386 23:38:01.608736 board id: 1
387 23:38:01.614404 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
388 23:38:01.624922 fw parse done
389 23:38:01.630947 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
390 23:38:01.673520 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
391 23:38:01.684397 PIEI prepare done
392 23:38:01.684845 fastboot data load
393 23:38:01.685275 fastboot data verify
394 23:38:01.690058 verify result: 266
395 23:38:01.695664 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
396 23:38:01.696210 LPDDR4 probe
397 23:38:01.696661 ddr clk to 1584MHz
398 23:38:01.702709 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
399 23:38:01.740866
400 23:38:01.741337 dmc_version 0001
401 23:38:01.747563 Check phy result
402 23:38:01.753447 INFO : End of CA training
403 23:38:01.753909 INFO : End of initialization
404 23:38:01.759028 INFO : Training has run successfully!
405 23:38:01.759491 Check phy result
406 23:38:01.764636 INFO : End of initialization
407 23:38:01.765134 INFO : End of read enable training
408 23:38:01.770276 INFO : End of fine write leveling
409 23:38:01.775845 INFO : End of Write leveling coarse delay
410 23:38:01.776339 INFO : Training has run successfully!
411 23:38:01.776783 Check phy result
412 23:38:01.781395 INFO : End of initialization
413 23:38:01.781855 INFO : End of read dq deskew training
414 23:38:01.787086 INFO : End of MPR read delay center optimization
415 23:38:01.792697 INFO : End of write delay center optimization
416 23:38:01.798288 INFO : End of read delay center optimization
417 23:38:01.798789 INFO : End of max read latency training
418 23:38:01.803906 INFO : Training has run successfully!
419 23:38:01.804405 1D training succeed
420 23:38:01.813074 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
421 23:38:01.860626 Check phy result
422 23:38:01.861090 INFO : End of initialization
423 23:38:01.882459 INFO : End of 2D read delay Voltage center optimization
424 23:38:01.902589 INFO : End of 2D read delay Voltage center optimization
425 23:38:01.954628 INFO : End of 2D write delay Voltage center optimization
426 23:38:02.004064 INFO : End of 2D write delay Voltage center optimization
427 23:38:02.009521 INFO : Training has run successfully!
428 23:38:02.009984
429 23:38:02.010430 channel==0
430 23:38:02.015217 RxClkDly_Margin_A0==88 ps 9
431 23:38:02.015676 TxDqDly_Margin_A0==98 ps 10
432 23:38:02.020731 RxClkDly_Margin_A1==88 ps 9
433 23:38:02.021191 TxDqDly_Margin_A1==88 ps 9
434 23:38:02.021634 TrainedVREFDQ_A0==74
435 23:38:02.026469 TrainedVREFDQ_A1==74
436 23:38:02.026933 VrefDac_Margin_A0==25
437 23:38:02.027372 DeviceVref_Margin_A0==40
438 23:38:02.032029 VrefDac_Margin_A1==25
439 23:38:02.032492 DeviceVref_Margin_A1==40
440 23:38:02.032932
441 23:38:02.033370
442 23:38:02.033805 channel==1
443 23:38:02.037627 RxClkDly_Margin_A0==98 ps 10
444 23:38:02.038090 TxDqDly_Margin_A0==98 ps 10
445 23:38:02.043133 RxClkDly_Margin_A1==88 ps 9
446 23:38:02.043595 TxDqDly_Margin_A1==88 ps 9
447 23:38:02.048814 TrainedVREFDQ_A0==76
448 23:38:02.049283 TrainedVREFDQ_A1==77
449 23:38:02.049725 VrefDac_Margin_A0==22
450 23:38:02.054496 DeviceVref_Margin_A0==38
451 23:38:02.054998 VrefDac_Margin_A1==24
452 23:38:02.060017 DeviceVref_Margin_A1==37
453 23:38:02.060478
454 23:38:02.060920 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
455 23:38:02.061357
456 23:38:02.093490 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000017 00000018 00000018 00000019 00000018 0000001a 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
457 23:38:02.094041 2D training succeed
458 23:38:02.099077 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
459 23:38:02.104672 auto size-- 65535DDR cs0 size: 2048MB
460 23:38:02.105135 DDR cs1 size: 2048MB
461 23:38:02.110279 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
462 23:38:02.110739 cs0 DataBus test pass
463 23:38:02.115884 cs1 DataBus test pass
464 23:38:02.116387 cs0 AddrBus test pass
465 23:38:02.116831 cs1 AddrBus test pass
466 23:38:02.117266
467 23:38:02.121472 100bdlr_step_size ps== 420
468 23:38:02.121945 result report
469 23:38:02.127054 boot times 0Enable ddr reg access
470 23:38:02.132345 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
471 23:38:02.145841 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
472 23:38:02.719527 0.0;M3 CHK:0;cm4_sp_mode 0
473 23:38:02.720117 MVN_1=0x00000000
474 23:38:02.724986 MVN_2=0x00000000
475 23:38:02.730740 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
476 23:38:02.731207 OPS=0x10
477 23:38:02.731653 ring efuse init
478 23:38:02.732121 chipver efuse init
479 23:38:02.738989 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
480 23:38:02.739498 [0.018961 Inits done]
481 23:38:02.746554 secure task start!
482 23:38:02.747029 high task start!
483 23:38:02.747479 low task start!
484 23:38:02.747918 run into bl31
485 23:38:02.753215 NOTICE: BL31: v1.3(release):4fc40b1
486 23:38:02.760994 NOTICE: BL31: Built : 15:58:17, May 22 2019
487 23:38:02.761461 NOTICE: BL31: G12A normal boot!
488 23:38:02.786438 NOTICE: BL31: BL33 decompress pass
489 23:38:02.792073 ERROR: Error initializing runtime service opteed_fast
490 23:38:04.024942
491 23:38:04.025481
492 23:38:04.033355 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
493 23:38:04.033833
494 23:38:04.034280 Model: Libre Computer AML-A311D-CC Alta
495 23:38:04.241770 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
496 23:38:04.265134 DRAM: 2 GiB (effective 3.8 GiB)
497 23:38:04.408118 Core: 408 devices, 31 uclasses, devicetree: separate
498 23:38:04.414021 WDT: Not starting watchdog@f0d0
499 23:38:04.446236 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
500 23:38:04.458724 Loading Environment from FAT... Card did not respond to voltage select! : -110
501 23:38:04.463728 ** Bad device specification mmc 0 **
502 23:38:04.474053 Card did not respond to voltage select! : -110
503 23:38:04.481735 ** Bad device specification mmc 0 **
504 23:38:04.482205 Couldn't find partition mmc 0
505 23:38:04.490025 Card did not respond to voltage select! : -110
506 23:38:04.495656 ** Bad device specification mmc 0 **
507 23:38:04.496183 Couldn't find partition mmc 0
508 23:38:04.500615 Error: could not access storage.
509 23:38:05.763857 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
510 23:38:05.764489 bl2_stage_init 0x01
511 23:38:05.764951 bl2_stage_init 0x81
512 23:38:05.769398 hw id: 0x0000 - pwm id 0x01
513 23:38:05.769871 bl2_stage_init 0xc1
514 23:38:05.770318 bl2_stage_init 0x02
515 23:38:05.770755
516 23:38:05.775013 L0:00000000
517 23:38:05.775475 L1:20000703
518 23:38:05.775915 L2:00008067
519 23:38:05.776396 L3:14000000
520 23:38:05.777890 B2:00402000
521 23:38:05.778356 B1:e0f83180
522 23:38:05.778798
523 23:38:05.779235 TE: 58124
524 23:38:05.779672
525 23:38:05.789008 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
526 23:38:05.789482
527 23:38:05.789930 Board ID = 1
528 23:38:05.790367 Set A53 clk to 24M
529 23:38:05.790803 Set A73 clk to 24M
530 23:38:05.794605 Set clk81 to 24M
531 23:38:05.795068 A53 clk: 1200 MHz
532 23:38:05.795505 A73 clk: 1200 MHz
533 23:38:05.800199 CLK81: 166.6M
534 23:38:05.800663 smccc: 00012a91
535 23:38:05.805841 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
536 23:38:05.806309 board id: 1
537 23:38:05.811409 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
538 23:38:05.825137 fw parse done
539 23:38:05.831097 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
540 23:38:05.873781 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
541 23:38:05.884623 PIEI prepare done
542 23:38:05.885087 fastboot data load
543 23:38:05.885533 fastboot data verify
544 23:38:05.890336 verify result: 266
545 23:38:05.895920 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
546 23:38:05.896433 LPDDR4 probe
547 23:38:05.896875 ddr clk to 1584MHz
548 23:38:05.903867 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
549 23:38:05.941115
550 23:38:05.941579 dmc_version 0001
551 23:38:05.947872 Check phy result
552 23:38:05.953683 INFO : End of CA training
553 23:38:05.954143 INFO : End of initialization
554 23:38:05.959293 INFO : Training has run successfully!
555 23:38:05.959760 Check phy result
556 23:38:05.964931 INFO : End of initialization
557 23:38:05.965395 INFO : End of read enable training
558 23:38:05.970468 INFO : End of fine write leveling
559 23:38:05.976058 INFO : End of Write leveling coarse delay
560 23:38:05.976522 INFO : Training has run successfully!
561 23:38:05.976962 Check phy result
562 23:38:05.981670 INFO : End of initialization
563 23:38:05.982132 INFO : End of read dq deskew training
564 23:38:05.987287 INFO : End of MPR read delay center optimization
565 23:38:05.992936 INFO : End of write delay center optimization
566 23:38:05.998482 INFO : End of read delay center optimization
567 23:38:05.998942 INFO : End of max read latency training
568 23:38:06.004070 INFO : Training has run successfully!
569 23:38:06.004530 1D training succeed
570 23:38:06.013254 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
571 23:38:06.060901 Check phy result
572 23:38:06.061364 INFO : End of initialization
573 23:38:06.082567 INFO : End of 2D read delay Voltage center optimization
574 23:38:06.102797 INFO : End of 2D read delay Voltage center optimization
575 23:38:06.154866 INFO : End of 2D write delay Voltage center optimization
576 23:38:06.204232 INFO : End of 2D write delay Voltage center optimization
577 23:38:06.209860 INFO : Training has run successfully!
578 23:38:06.210358
579 23:38:06.210806 channel==0
580 23:38:06.215380 RxClkDly_Margin_A0==88 ps 9
581 23:38:06.215846 TxDqDly_Margin_A0==98 ps 10
582 23:38:06.221011 RxClkDly_Margin_A1==88 ps 9
583 23:38:06.221480 TxDqDly_Margin_A1==98 ps 10
584 23:38:06.221928 TrainedVREFDQ_A0==74
585 23:38:06.226657 TrainedVREFDQ_A1==74
586 23:38:06.227132 VrefDac_Margin_A0==25
587 23:38:06.227575 DeviceVref_Margin_A0==40
588 23:38:06.232229 VrefDac_Margin_A1==25
589 23:38:06.232693 DeviceVref_Margin_A1==40
590 23:38:06.233131
591 23:38:06.233567
592 23:38:06.237840 channel==1
593 23:38:06.238304 RxClkDly_Margin_A0==98 ps 10
594 23:38:06.238744 TxDqDly_Margin_A0==88 ps 9
595 23:38:06.243417 RxClkDly_Margin_A1==98 ps 10
596 23:38:06.243880 TxDqDly_Margin_A1==98 ps 10
597 23:38:06.249022 TrainedVREFDQ_A0==77
598 23:38:06.249494 TrainedVREFDQ_A1==77
599 23:38:06.249940 VrefDac_Margin_A0==22
600 23:38:06.254593 DeviceVref_Margin_A0==37
601 23:38:06.255053 VrefDac_Margin_A1==22
602 23:38:06.260228 DeviceVref_Margin_A1==37
603 23:38:06.260696
604 23:38:06.261141 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
605 23:38:06.265842
606 23:38:06.293849 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000017 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
607 23:38:06.294379 2D training succeed
608 23:38:06.299373 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
609 23:38:06.305020 auto size-- 65535DDR cs0 size: 2048MB
610 23:38:06.305498 DDR cs1 size: 2048MB
611 23:38:06.310605 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
612 23:38:06.311083 cs0 DataBus test pass
613 23:38:06.316222 cs1 DataBus test pass
614 23:38:06.316693 cs0 AddrBus test pass
615 23:38:06.317134 cs1 AddrBus test pass
616 23:38:06.317567
617 23:38:06.321850 100bdlr_step_size ps== 420
618 23:38:06.322330 result report
619 23:38:06.327379 boot times 0Enable ddr reg access
620 23:38:06.332823 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
621 23:38:06.346319 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
622 23:38:06.919937 0.0;M3 CHK:0;cm4_sp_mode 0
623 23:38:06.920506 MVN_1=0x00000000
624 23:38:06.925504 MVN_2=0x00000000
625 23:38:06.931267 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
626 23:38:06.931793 OPS=0x10
627 23:38:06.932314 ring efuse init
628 23:38:06.932801 chipver efuse init
629 23:38:06.939550 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
630 23:38:06.940093 [0.018961 Inits done]
631 23:38:06.940532 secure task start!
632 23:38:06.947091 high task start!
633 23:38:06.947556 low task start!
634 23:38:06.948015 run into bl31
635 23:38:06.953682 NOTICE: BL31: v1.3(release):4fc40b1
636 23:38:06.961493 NOTICE: BL31: Built : 15:58:17, May 22 2019
637 23:38:06.961967 NOTICE: BL31: G12A normal boot!
638 23:38:06.986867 NOTICE: BL31: BL33 decompress pass
639 23:38:06.992528 ERROR: Error initializing runtime service opteed_fast
640 23:38:08.225806
641 23:38:08.226452
642 23:38:08.234081 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
643 23:38:08.234635
644 23:38:08.235097 Model: Libre Computer AML-A311D-CC Alta
645 23:38:08.442568 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
646 23:38:08.465857 DRAM: 2 GiB (effective 3.8 GiB)
647 23:38:08.608876 Core: 408 devices, 31 uclasses, devicetree: separate
648 23:38:08.614644 WDT: Not starting watchdog@f0d0
649 23:38:08.646832 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
650 23:38:08.659380 Loading Environment from FAT... Card did not respond to voltage select! : -110
651 23:38:08.664552 ** Bad device specification mmc 0 **
652 23:38:08.674647 Card did not respond to voltage select! : -110
653 23:38:08.682497 ** Bad device specification mmc 0 **
654 23:38:08.683016 Couldn't find partition mmc 0
655 23:38:08.690683 Card did not respond to voltage select! : -110
656 23:38:08.696319 ** Bad device specification mmc 0 **
657 23:38:08.696883 Couldn't find partition mmc 0
658 23:38:08.701344 Error: could not access storage.
659 23:38:09.044843 Net: eth0: ethernet@ff3f0000
660 23:38:09.045388 starting USB...
661 23:38:09.296642 Bus usb@ff500000: Register 3000140 NbrPorts 3
662 23:38:09.297285 Starting the controller
663 23:38:09.303764 USB XHCI 1.10
664 23:38:11.014338 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
665 23:38:11.015018 bl2_stage_init 0x01
666 23:38:11.015497 bl2_stage_init 0x81
667 23:38:11.019934 hw id: 0x0000 - pwm id 0x01
668 23:38:11.020518 bl2_stage_init 0xc1
669 23:38:11.021000 bl2_stage_init 0x02
670 23:38:11.021529
671 23:38:11.026091 L0:00000000
672 23:38:11.026770 L1:20000703
673 23:38:11.027290 L2:00008067
674 23:38:11.027785 L3:14000000
675 23:38:11.031381 B2:00402000
676 23:38:11.032005 B1:e0f83180
677 23:38:11.032529
678 23:38:11.033389 TE: 58159
679 23:38:11.033898
680 23:38:11.037100 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
681 23:38:11.037700
682 23:38:11.038159 Board ID = 1
683 23:38:11.042362 Set A53 clk to 24M
684 23:38:11.042897 Set A73 clk to 24M
685 23:38:11.043323 Set clk81 to 24M
686 23:38:11.047889 A53 clk: 1200 MHz
687 23:38:11.048413 A73 clk: 1200 MHz
688 23:38:11.048848 CLK81: 166.6M
689 23:38:11.049313 smccc: 00012ab5
690 23:38:11.053526 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
691 23:38:11.059133 board id: 1
692 23:38:11.065048 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
693 23:38:11.075691 fw parse done
694 23:38:11.081644 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
695 23:38:11.124231 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
696 23:38:11.135146 PIEI prepare done
697 23:38:11.135786 fastboot data load
698 23:38:11.136377 fastboot data verify
699 23:38:11.140910 verify result: 266
700 23:38:11.146405 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
701 23:38:11.147054 LPDDR4 probe
702 23:38:11.147470 ddr clk to 1584MHz
703 23:38:11.154250 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
704 23:38:11.191576
705 23:38:11.191998 dmc_version 0001
706 23:38:11.198181 Check phy result
707 23:38:11.204244 INFO : End of CA training
708 23:38:11.204795 INFO : End of initialization
709 23:38:11.209799 INFO : Training has run successfully!
710 23:38:11.210332 Check phy result
711 23:38:11.215398 INFO : End of initialization
712 23:38:11.215950 INFO : End of read enable training
713 23:38:11.218726 INFO : End of fine write leveling
714 23:38:11.224277 INFO : End of Write leveling coarse delay
715 23:38:11.229833 INFO : Training has run successfully!
716 23:38:11.230367 Check phy result
717 23:38:11.230834 INFO : End of initialization
718 23:38:11.235469 INFO : End of read dq deskew training
719 23:38:11.241088 INFO : End of MPR read delay center optimization
720 23:38:11.241616 INFO : End of write delay center optimization
721 23:38:11.246703 INFO : End of read delay center optimization
722 23:38:11.252270 INFO : End of max read latency training
723 23:38:11.252796 INFO : Training has run successfully!
724 23:38:11.257830 1D training succeed
725 23:38:11.263945 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
726 23:38:11.311365 Check phy result
727 23:38:11.311914 INFO : End of initialization
728 23:38:11.332977 INFO : End of 2D read delay Voltage center optimization
729 23:38:11.353040 INFO : End of 2D read delay Voltage center optimization
730 23:38:11.405056 INFO : End of 2D write delay Voltage center optimization
731 23:38:11.454303 INFO : End of 2D write delay Voltage center optimization
732 23:38:11.459918 INFO : Training has run successfully!
733 23:38:11.460498
734 23:38:11.460966 channel==0
735 23:38:11.465406 RxClkDly_Margin_A0==88 ps 9
736 23:38:11.465933 TxDqDly_Margin_A0==98 ps 10
737 23:38:11.471050 RxClkDly_Margin_A1==88 ps 9
738 23:38:11.471583 TxDqDly_Margin_A1==98 ps 10
739 23:38:11.472085 TrainedVREFDQ_A0==74
740 23:38:11.476537 TrainedVREFDQ_A1==74
741 23:38:11.477107 VrefDac_Margin_A0==25
742 23:38:11.477565 DeviceVref_Margin_A0==40
743 23:38:11.482232 VrefDac_Margin_A1==25
744 23:38:11.482767 DeviceVref_Margin_A1==40
745 23:38:11.483220
746 23:38:11.483664
747 23:38:11.487899 channel==1
748 23:38:11.488461 RxClkDly_Margin_A0==88 ps 9
749 23:38:11.488919 TxDqDly_Margin_A0==88 ps 9
750 23:38:11.493413 RxClkDly_Margin_A1==98 ps 10
751 23:38:11.493952 TxDqDly_Margin_A1==98 ps 10
752 23:38:11.499026 TrainedVREFDQ_A0==77
753 23:38:11.499558 TrainedVREFDQ_A1==78
754 23:38:11.500053 VrefDac_Margin_A0==22
755 23:38:11.504600 DeviceVref_Margin_A0==37
756 23:38:11.505120 VrefDac_Margin_A1==22
757 23:38:11.510100 DeviceVref_Margin_A1==36
758 23:38:11.510624
759 23:38:11.511083 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
760 23:38:11.511529
761 23:38:11.543789 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000019 00000017 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 0000001a 00000018 00000018 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
762 23:38:11.544425 2D training succeed
763 23:38:11.549340 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
764 23:38:11.554928 auto size-- 65535DDR cs0 size: 2048MB
765 23:38:11.555452 DDR cs1 size: 2048MB
766 23:38:11.560528 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
767 23:38:11.561049 cs0 DataBus test pass
768 23:38:11.566127 cs1 DataBus test pass
769 23:38:11.566640 cs0 AddrBus test pass
770 23:38:11.567091 cs1 AddrBus test pass
771 23:38:11.567533
772 23:38:11.571850 100bdlr_step_size ps== 420
773 23:38:11.572421 result report
774 23:38:11.577345 boot times 0Enable ddr reg access
775 23:38:11.582688 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
776 23:38:11.596099 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
777 23:38:12.167859 0.0;M3 CHK:0;cm4_sp_mode 0
778 23:38:12.168284 MVN_1=0x00000000
779 23:38:12.173432 MVN_2=0x00000000
780 23:38:12.179153 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
781 23:38:12.179432 OPS=0x10
782 23:38:12.179637 ring efuse init
783 23:38:12.179834 chipver efuse init
784 23:38:12.184743 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
785 23:38:12.190332 [0.018960 Inits done]
786 23:38:12.190592 secure task start!
787 23:38:12.190792 high task start!
788 23:38:12.194908 low task start!
789 23:38:12.195160 run into bl31
790 23:38:12.201673 NOTICE: BL31: v1.3(release):4fc40b1
791 23:38:12.209408 NOTICE: BL31: Built : 15:58:17, May 22 2019
792 23:38:12.209719 NOTICE: BL31: G12A normal boot!
793 23:38:12.234874 NOTICE: BL31: BL33 decompress pass
794 23:38:12.240551 ERROR: Error initializing runtime service opteed_fast
795 23:38:13.473546
796 23:38:13.474205
797 23:38:13.482120 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
798 23:38:13.482699
799 23:38:13.483158 Model: Libre Computer AML-A311D-CC Alta
800 23:38:13.690328 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
801 23:38:13.713814 DRAM: 2 GiB (effective 3.8 GiB)
802 23:38:13.856749 Core: 408 devices, 31 uclasses, devicetree: separate
803 23:38:13.862680 WDT: Not starting watchdog@f0d0
804 23:38:13.894911 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
805 23:38:13.907316 Loading Environment from FAT... Card did not respond to voltage select! : -110
806 23:38:13.912341 ** Bad device specification mmc 0 **
807 23:38:13.922651 Card did not respond to voltage select! : -110
808 23:38:13.930311 ** Bad device specification mmc 0 **
809 23:38:13.930838 Couldn't find partition mmc 0
810 23:38:13.938660 Card did not respond to voltage select! : -110
811 23:38:13.944230 ** Bad device specification mmc 0 **
812 23:38:13.944744 Couldn't find partition mmc 0
813 23:38:13.949257 Error: could not access storage.
814 23:38:14.292798 Net: eth0: ethernet@ff3f0000
815 23:38:14.293425 starting USB...
816 23:38:14.544620 Bus usb@ff500000: Register 3000140 NbrPorts 3
817 23:38:14.545249 Starting the controller
818 23:38:14.551630 USB XHCI 1.10
819 23:38:16.714753 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.�!,K��х��}���с0x01
820 23:38:16.715461 bl2_stage_init 0x81
821 23:38:16.720263 hw id: 0x0000 - pwm id 0x01
822 23:38:16.720803 bl2_stage_init 0xc1
823 23:38:16.721261 bl2_stage_init 0x02
824 23:38:16.721711
825 23:38:16.725863 L0:00000000
826 23:38:16.726398 L1:20000703
827 23:38:16.726852 L2:00008067
828 23:38:16.727294 L3:14000000
829 23:38:16.727733 B2:00402000
830 23:38:16.731479 B1:e0f83180
831 23:38:16.732041
832 23:38:16.732512 TE: 58150
833 23:38:16.732973
834 23:38:16.736978 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
835 23:38:16.737498
836 23:38:16.737952 Board ID = 1
837 23:38:16.742644 Set A53 clk to 24M
838 23:38:16.743166 Set A73 clk to 24M
839 23:38:16.743613 Set clk81 to 24M
840 23:38:16.748250 A53 clk: 1200 MHz
841 23:38:16.748772 A73 clk: 1200 MHz
842 23:38:16.749223 CLK81: 166.6M
843 23:38:16.749666 smccc: 00012aab
844 23:38:16.753834 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
845 23:38:16.759426 board id: 1
846 23:38:16.765284 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
847 23:38:16.775815 fw parse done
848 23:38:16.781932 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
849 23:38:16.824297 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
850 23:38:16.835227 PIEI prepare done
851 23:38:16.835789 fastboot data load
852 23:38:16.836297 fastboot data verify
853 23:38:16.840851 verify result: 266
854 23:38:16.846515 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
855 23:38:16.847023 LPDDR4 probe
856 23:38:16.847469 ddr clk to 1584MHz
857 23:38:16.854462 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
858 23:38:16.891726
859 23:38:16.892342 dmc_version 0001
860 23:38:16.898374 Check phy result
861 23:38:16.904277 INFO : End of CA training
862 23:38:16.904792 INFO : End of initialization
863 23:38:16.909843 INFO : Training has run successfully!
864 23:38:16.910364 Check phy result
865 23:38:16.915545 INFO : End of initialization
866 23:38:16.916122 INFO : End of read enable training
867 23:38:16.921039 INFO : End of fine write leveling
868 23:38:16.926596 INFO : End of Write leveling coarse delay
869 23:38:16.927108 INFO : Training has run successfully!
870 23:38:16.927557 Check phy result
871 23:38:16.932263 INFO : End of initialization
872 23:38:16.932789 INFO : End of read dq deskew training
873 23:38:16.937854 INFO : End of MPR read delay center optimization
874 23:38:16.943562 INFO : End of write delay center optimization
875 23:38:16.949047 INFO : End of read delay center optimization
876 23:38:16.949571 INFO : End of max read latency training
877 23:38:16.954505 INFO : Training has run successfully!
878 23:38:16.954829 1D training succeed
879 23:38:16.963765 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
880 23:38:17.011437 Check phy result
881 23:38:17.012041 INFO : End of initialization
882 23:38:17.033084 INFO : End of 2D read delay Voltage center optimization
883 23:38:17.053173 INFO : End of 2D read delay Voltage center optimization
884 23:38:17.105053 INFO : End of 2D write delay Voltage center optimization
885 23:38:17.154289 INFO : End of 2D write delay Voltage center optimization
886 23:38:17.159875 INFO : Training has run successfully!
887 23:38:17.160491
888 23:38:17.160957 channel==0
889 23:38:17.165468 RxClkDly_Margin_A0==88 ps 9
890 23:38:17.165994 TxDqDly_Margin_A0==98 ps 10
891 23:38:17.171085 RxClkDly_Margin_A1==88 ps 9
892 23:38:17.171605 TxDqDly_Margin_A1==98 ps 10
893 23:38:17.172122 TrainedVREFDQ_A0==74
894 23:38:17.176700 TrainedVREFDQ_A1==74
895 23:38:17.177236 VrefDac_Margin_A0==25
896 23:38:17.177690 DeviceVref_Margin_A0==40
897 23:38:17.182253 VrefDac_Margin_A1==25
898 23:38:17.182774 DeviceVref_Margin_A1==40
899 23:38:17.183207
900 23:38:17.183637
901 23:38:17.187855 channel==1
902 23:38:17.188387 RxClkDly_Margin_A0==98 ps 10
903 23:38:17.188819 TxDqDly_Margin_A0==98 ps 10
904 23:38:17.193463 RxClkDly_Margin_A1==88 ps 9
905 23:38:17.193971 TxDqDly_Margin_A1==88 ps 9
906 23:38:17.199053 TrainedVREFDQ_A0==77
907 23:38:17.199609 TrainedVREFDQ_A1==77
908 23:38:17.200091 VrefDac_Margin_A0==22
909 23:38:17.204655 DeviceVref_Margin_A0==37
910 23:38:17.205166 VrefDac_Margin_A1==24
911 23:38:17.210254 DeviceVref_Margin_A1==37
912 23:38:17.210759
913 23:38:17.211196 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
914 23:38:17.211624
915 23:38:17.243821 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000016 00000018 00000018 00000018 00000019 00000018 0000001a 0000001a 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
916 23:38:17.244433 2D training succeed
917 23:38:17.249461 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
918 23:38:17.255044 auto size-- 65535DDR cs0 size: 2048MB
919 23:38:17.255549 DDR cs1 size: 2048MB
920 23:38:17.260638 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
921 23:38:17.261130 cs0 DataBus test pass
922 23:38:17.266249 cs1 DataBus test pass
923 23:38:17.266749 cs0 AddrBus test pass
924 23:38:17.267180 cs1 AddrBus test pass
925 23:38:17.267608
926 23:38:17.271825 100bdlr_step_size ps== 420
927 23:38:17.272370 result report
928 23:38:17.277456 boot times 0Enable ddr reg access
929 23:38:17.282774 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
930 23:38:17.296254 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
931 23:38:17.868154 0.0;M3 CHK:0;cm4_sp_mode 0
932 23:38:17.868585 MVN_1=0x00000000
933 23:38:17.873569 MVN_2=0x00000000
934 23:38:17.879428 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
935 23:38:17.879720 OPS=0x10
936 23:38:17.879954 ring efuse init
937 23:38:17.880218 chipver efuse init
938 23:38:17.884933 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
939 23:38:17.890516 [0.018961 Inits done]
940 23:38:17.890800 secure task start!
941 23:38:17.891035 high task start!
942 23:38:17.895098 low task start!
943 23:38:17.895374 run into bl31
944 23:38:17.901769 NOTICE: BL31: v1.3(release):4fc40b1
945 23:38:17.909584 NOTICE: BL31: Built : 15:58:17, May 22 2019
946 23:38:17.909886 NOTICE: BL31: G12A normal boot!
947 23:38:17.935527 NOTICE: BL31: BL33 decompress pass
948 23:38:17.941365 ERROR: Error initializing runtime service opteed_fast
949 23:38:19.174318
950 23:38:19.175044
951 23:38:19.182803 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
952 23:38:19.183399
953 23:38:19.183915 Model: Libre Computer AML-A311D-CC Alta
954 23:38:19.391100 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
955 23:38:19.414418 DRAM: 2 GiB (effective 3.8 GiB)
956 23:38:19.557411 Core: 408 devices, 31 uclasses, devicetree: separate
957 23:38:19.563249 WDT: Not starting watchdog@f0d0
958 23:38:19.595531 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
959 23:38:19.608104 Loading Environment from FAT... Card did not respond to voltage select! : -110
960 23:38:19.612951 ** Bad device specification mmc 0 **
961 23:38:19.623312 Card did not respond to voltage select! : -110
962 23:38:19.630944 ** Bad device specification mmc 0 **
963 23:38:19.631434 Couldn't find partition mmc 0
964 23:38:19.639282 Card did not respond to voltage select! : -110
965 23:38:19.644787 ** Bad device specification mmc 0 **
966 23:38:19.645261 Couldn't find partition mmc 0
967 23:38:19.649871 Error: could not access storage.
968 23:38:19.993358 Net: eth0: ethernet@ff3f0000
969 23:38:19.993957 starting USB...
970 23:38:20.245151 Bus usb@ff500000: Register 3000140 NbrPorts 3
971 23:38:20.245711 Starting the controller
972 23:38:20.252187 USB XHCI 1.10
973 23:38:21.806246 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
974 23:38:21.814511 scanning usb for storage devices... 0 Storage Device(s) found
976 23:38:21.866301 Hit any key to stop autoboot: 1
977 23:38:21.867134 end: 2.4.2 bootloader-interrupt (duration 00:00:31) [common]
978 23:38:21.867731 start: 2.4.3 bootloader-commands (timeout 00:04:29) [common]
979 23:38:21.868256 Setting prompt string to ['=>']
980 23:38:21.868751 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:29)
981 23:38:21.882142 0
982 23:38:21.883050 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
983 23:38:21.883541 Sending with 10 millisecond of delay
985 23:38:23.018508 => setenv autoload no
986 23:38:23.029315 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:28)
987 23:38:23.034357 setenv autoload no
988 23:38:23.035092 Sending with 10 millisecond of delay
990 23:38:24.832367 => setenv initrd_high 0xffffffff
991 23:38:24.843163 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:26)
992 23:38:24.844099 setenv initrd_high 0xffffffff
993 23:38:24.844820 Sending with 10 millisecond of delay
995 23:38:26.461497 => setenv fdt_high 0xffffffff
996 23:38:26.472268 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:24)
997 23:38:26.473053 setenv fdt_high 0xffffffff
998 23:38:26.473749 Sending with 10 millisecond of delay
1000 23:38:26.765555 => dhcp
1001 23:38:26.776345 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:24)
1002 23:38:26.777145 dhcp
1003 23:38:26.777581 Speed: 1000, full duplex
1004 23:38:26.777996 BOOTP broadcast 1
1005 23:38:26.784443 DHCP client bound to address 192.168.6.27 (8 ms)
1006 23:38:26.785131 Sending with 10 millisecond of delay
1008 23:38:28.461816 => setenv serverip 192.168.6.2
1009 23:38:28.472608 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:22)
1010 23:38:28.473488 setenv serverip 192.168.6.2
1011 23:38:28.474176 Sending with 10 millisecond of delay
1013 23:38:32.197301 => tftpboot 0x01080000 943265/tftp-deploy-ni9yk04u/kernel/uImage
1014 23:38:32.208118 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1015 23:38:32.208972 tftpboot 0x01080000 943265/tftp-deploy-ni9yk04u/kernel/uImage
1016 23:38:32.209419 Speed: 1000, full duplex
1017 23:38:32.209830 Using ethernet@ff3f0000 device
1018 23:38:32.210949 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1019 23:38:32.216498 Filename '943265/tftp-deploy-ni9yk04u/kernel/uImage'.
1020 23:38:32.220395 Load address: 0x1080000
1021 23:38:34.990899 Loading: *################################################## 43.6 MiB
1022 23:38:34.991529 15.7 MiB/s
1023 23:38:34.991958 done
1024 23:38:34.995207 Bytes transferred = 45716032 (2b99240 hex)
1025 23:38:34.996021 Sending with 10 millisecond of delay
1027 23:38:39.683043 => tftpboot 0x08000000 943265/tftp-deploy-ni9yk04u/ramdisk/ramdisk.cpio.gz.uboot
1028 23:38:39.693823 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:11)
1029 23:38:39.694650 tftpboot 0x08000000 943265/tftp-deploy-ni9yk04u/ramdisk/ramdisk.cpio.gz.uboot
1030 23:38:39.695094 Speed: 1000, full duplex
1031 23:38:39.695508 Using ethernet@ff3f0000 device
1032 23:38:39.697182 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1033 23:38:39.705765 Filename '943265/tftp-deploy-ni9yk04u/ramdisk/ramdisk.cpio.gz.uboot'.
1034 23:38:39.706274 Load address: 0x8000000
1035 23:38:42.231665 Loading: *##################### UDP wrong checksum 000000ff 00004b0f
1036 23:38:42.268721 UDP wrong checksum 000000ff 0000d601
1037 23:38:46.369161 T ############################# 22.3 MiB
1038 23:38:46.369782 3.4 MiB/s
1039 23:38:46.370214 done
1040 23:38:46.373388 Bytes transferred = 23435256 (16597f8 hex)
1041 23:38:46.374115 Sending with 10 millisecond of delay
1043 23:38:51.540935 => tftpboot 0x01070000 943265/tftp-deploy-ni9yk04u/dtb/meson-g12b-a311d-libretech-cc.dtb
1044 23:38:51.551682 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:03:59)
1045 23:38:51.552489 tftpboot 0x01070000 943265/tftp-deploy-ni9yk04u/dtb/meson-g12b-a311d-libretech-cc.dtb
1046 23:38:51.552944 Speed: 1000, full duplex
1047 23:38:51.553352 Using ethernet@ff3f0000 device
1048 23:38:51.556616 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1049 23:38:51.564130 Filename '943265/tftp-deploy-ni9yk04u/dtb/meson-g12b-a311d-libretech-cc.dtb'.
1050 23:38:51.575335 Load address: 0x1070000
1051 23:38:51.584355 Loading: *################################################## 53.4 KiB
1052 23:38:51.584797 2.9 MiB/s
1053 23:38:51.585210 done
1054 23:38:51.591829 Bytes transferred = 54703 (d5af hex)
1055 23:38:51.592547 Sending with 10 millisecond of delay
1057 23:39:04.884495 => setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/943265/extract-nfsrootfs-4cipzu_g,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
1058 23:39:04.895285 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:03:46)
1059 23:39:04.896173 setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/943265/extract-nfsrootfs-4cipzu_g,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
1060 23:39:04.896882 Sending with 10 millisecond of delay
1062 23:39:07.235678 => bootm 0x01080000 0x08000000 0x01070000
1063 23:39:07.246514 Setting prompt string to ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1064 23:39:07.247023 bootloader-commands: Wait for prompt ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:03:43)
1065 23:39:07.248043 bootm 0x01080000 0x08000000 0x01070000
1066 23:39:07.248484 ## Booting kernel from Legacy Image at 01080000 ...
1067 23:39:07.251336 Image Name:
1068 23:39:07.256868 Image Type: AArch64 Linux Kernel Image (uncompressed)
1069 23:39:07.257320 Data Size: 45715968 Bytes = 43.6 MiB
1070 23:39:07.262407 Load Address: 01080000
1071 23:39:07.262838 Entry Point: 01080000
1072 23:39:07.457733 Verifying Checksum ... OK
1073 23:39:07.458175 ## Loading init Ramdisk from Legacy Image at 08000000 ...
1074 23:39:07.463130 Image Name:
1075 23:39:07.468458 Image Type: AArch64 Linux RAMDisk Image (uncompressed)
1076 23:39:07.468885 Data Size: 23435192 Bytes = 22.3 MiB
1077 23:39:07.470841 Load Address: 00000000
1078 23:39:07.478101 Entry Point: 00000000
1079 23:39:07.576307 Verifying Checksum ... OK
1080 23:39:07.576753 ## Flattened Device Tree blob at 01070000
1081 23:39:07.581814 Booting using the fdt blob at 0x1070000
1082 23:39:07.582256 Working FDT set to 1070000
1083 23:39:07.586199 Loading Kernel Image
1084 23:39:07.630763 Loading Ramdisk to 7e9a6000, end 7ffff7b8 ... OK
1085 23:39:07.639137 Loading Device Tree to 000000007e995000, end 000000007e9a55ae ... OK
1086 23:39:07.639582 Working FDT set to 7e995000
1087 23:39:07.640034
1088 23:39:07.640927 end: 2.4.3 bootloader-commands (duration 00:00:46) [common]
1089 23:39:07.641510 start: 2.4.4 auto-login-action (timeout 00:03:43) [common]
1090 23:39:07.641983 Setting prompt string to ['Linux version [0-9]']
1091 23:39:07.642432 Setting prompt string to ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1092 23:39:07.642895 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:05:00)
1093 23:39:07.643923 Starting kernel ...
1094 23:39:07.644417
1095 23:39:07.679482 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x410fd034]
1096 23:39:07.680358 start: 2.4.4.1 login-action (timeout 00:03:43) [common]
1097 23:39:07.680864 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
1098 23:39:07.681317 Setting prompt string to []
1099 23:39:07.681800 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
1100 23:39:07.682248 Using line separator: #'\n'#
1101 23:39:07.682651 No login prompt set.
1102 23:39:07.683090 Parsing kernel messages
1103 23:39:07.683484 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
1104 23:39:07.684307 [login-action] Waiting for messages, (timeout 00:03:43)
1105 23:39:07.684827 Waiting using forced prompt support (timeout 00:01:51)
1106 23:39:07.696032 [ 0.000000] Linux version 6.12.0-rc6 (KernelCI@build-j364108-arm64-gcc-12-defconfig-2glsp) (aarch64-linux-gnu-gcc (Debian 12.2.0-14) 12.2.0, GNU ld (GNU Binutils for Debian) 2.40) #1 SMP PREEMPT Tue Nov 5 23:01:29 UTC 2024
1107 23:39:07.701548 [ 0.000000] KASLR disabled due to lack of seed
1108 23:39:07.707055 [ 0.000000] Machine model: Libre Computer AML-A311D-CC Alta
1109 23:39:07.712594 [ 0.000000] efi: UEFI not found.
1110 23:39:07.718129 [ 0.000000] [Firmware Bug]: Kernel image misaligned at boot, please fix your bootloader!
1111 23:39:07.723628 [ 0.000000] Reserved memory: created CMA memory pool at 0x00000000e4c00000, size 256 MiB
1112 23:39:07.734657 [ 0.000000] OF: reserved mem: initialized node linux,cma, compatible id shared-dma-pool
1113 23:39:07.745616 [ 0.000000] OF: reserved mem: 0x00000000e4c00000..0x00000000f4bfffff (262144 KiB) map reusable linux,cma
1114 23:39:07.751197 [ 0.000000] OF: reserved mem: 0x0000000005000000..0x00000000052fffff (3072 KiB) nomap non-reusable secmon@5000000
1115 23:39:07.762200 [ 0.000000] OF: reserved mem: 0x0000000005300000..0x00000000072fffff (32768 KiB) nomap non-reusable secmon@5300000
1116 23:39:07.773272 [ 0.000000] earlycon: meson0 at MMIO 0x00000000ff803000 (options '115200n8')
1117 23:39:07.778706 [ 0.000000] printk: legacy bootconsole [meson0] enabled
1118 23:39:07.784250 [ 0.000000] NUMA: Faking a node at [mem 0x0000000000000000-0x00000000f4e5afff]
1119 23:39:07.789748 [ 0.000000] NODE_DATA(0) allocated [mem 0xe4666a80-0xe46690bf]
1120 23:39:07.790173 [ 0.000000] Zone ranges:
1121 23:39:07.795365 [ 0.000000] DMA [mem 0x0000000000000000-0x00000000f4e5afff]
1122 23:39:07.800790 [ 0.000000] DMA32 empty
1123 23:39:07.801216 [ 0.000000] Normal empty
1124 23:39:07.806405 [ 0.000000] Movable zone start for each node
1125 23:39:07.811891 [ 0.000000] Early memory node ranges
1126 23:39:07.817417 [ 0.000000] node 0: [mem 0x0000000000000000-0x0000000004ffffff]
1127 23:39:07.822880 [ 0.000000] node 0: [mem 0x0000000005000000-0x00000000072fffff]
1128 23:39:07.828387 [ 0.000000] node 0: [mem 0x0000000007300000-0x00000000f4e5afff]
1129 23:39:07.833900 [ 0.000000] Initmem setup node 0 [mem 0x0000000000000000-0x00000000f4e5afff]
1130 23:39:07.861275 [ 0.000000] On node 0, zone DMA: 12709 pages in unavailable ranges
1131 23:39:07.866794 [ 0.000000] psci: probing for conduit method from DT.
1132 23:39:07.867221 [ 0.000000] psci: PSCIv1.0 detected in firmware.
1133 23:39:07.872399 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
1134 23:39:07.877805 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
1135 23:39:07.883418 [ 0.000000] psci: SMC Calling Convention v1.1
1136 23:39:07.888861 [ 0.000000] percpu: Embedded 25 pages/cpu s61656 r8192 d32552 u102400
1137 23:39:07.894382 [ 0.000000] Detected VIPT I-cache on CPU0
1138 23:39:07.899914 [ 0.000000] CPU features: detected: ARM erratum 845719
1139 23:39:07.905444 [ 0.000000] alternatives: applying boot alternatives
1140 23:39:07.921969 [ 0.000000] Kernel command line: console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/943265/extract-nfsrootfs-4cipzu_g,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp
1141 23:39:07.933036 <6>[ 0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
1142 23:39:07.938548 <6>[ 0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes, linear)
1143 23:39:07.944067 <6>[ 0.000000] Fallback order for Node 0: 0
1144 23:39:07.949593 <6>[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 1003099
1145 23:39:07.955103 <6>[ 0.000000] Policy zone: DMA
1146 23:39:07.960623 <6>[ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
1147 23:39:07.966169 <6>[ 0.000000] software IO TLB: SWIOTLB bounce buffer size adjusted to 3MB
1148 23:39:07.971664 <6>[ 0.000000] software IO TLB: area num 8.
1149 23:39:07.980701 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000dfc00000-0x00000000e0000000] (4MB)
1150 23:39:08.027264 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=6, Nodes=1
1151 23:39:08.032792 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
1152 23:39:08.036435 <6>[ 0.000000] rcu: RCU event tracing is enabled.
1153 23:39:08.041937 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=512 to nr_cpu_ids=6.
1154 23:39:08.047444 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
1155 23:39:08.052973 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
1156 23:39:08.064024 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
1157 23:39:08.069541 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=6
1158 23:39:08.075057 <6>[ 0.000000] RCU Tasks: Setting shift to 3 and lim to 1 rcu_task_cb_adjust=1 rcu_task_cpu_ids=6.
1159 23:39:08.086083 <6>[ 0.000000] RCU Tasks Trace: Setting shift to 3 and lim to 1 rcu_task_cb_adjust=1 rcu_task_cpu_ids=6.
1160 23:39:08.091610 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
1161 23:39:08.097142 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
1162 23:39:08.102667 <6>[ 0.000000] GIC: Using split EOI/Deactivate mode
1163 23:39:08.108912 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
1164 23:39:08.121584 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 24.00MHz (phys).
1165 23:39:08.132621 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x588fe9dc0, max_idle_ns: 440795202592 ns
1166 23:39:08.138156 <6>[ 0.000001] sched_clock: 56 bits at 24MHz, resolution 41ns, wraps every 4398046511097ns
1167 23:39:08.143660 <6>[ 0.008797] Console: colour dummy device 80x25
1168 23:39:08.154702 <6>[ 0.012940] Calibrating delay loop (skipped), value calculated using timer frequency.. 48.00 BogoMIPS (lpj=96000)
1169 23:39:08.160283 <6>[ 0.023294] pid_max: default: 32768 minimum: 301
1170 23:39:08.165745 <6>[ 0.028190] LSM: initializing lsm=capability
1171 23:39:08.171308 <6>[ 0.032730] Mount-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
1172 23:39:08.176799 <6>[ 0.040211] Mountpoint-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
1173 23:39:08.182298 <6>[ 0.052297] rcu: Hierarchical SRCU implementation.
1174 23:39:08.187836 <6>[ 0.053215] rcu: Max phase no-delay instances is 1000.
1175 23:39:08.198860 <6>[ 0.058882] Timer migration: 1 hierarchy levels; 8 children per group; 1 crossnode level
1176 23:39:08.207294 <6>[ 0.071587] EFI services will not be available.
1177 23:39:08.207730 <6>[ 0.075239] smp: Bringing up secondary CPUs ...
1178 23:39:08.219557 <6>[ 0.077132] Detected VIPT I-cache on CPU1
1179 23:39:08.225072 <6>[ 0.077252] CPU1: Booted secondary processor 0x0000000001 [0x410fd034]
1180 23:39:08.230589 <6>[ 0.078583] CPU features: detected: Spectre-v2
1181 23:39:08.239631 <6>[ 0.078599] CPU features: detected: Spectre-v4
1182 23:39:08.240087 <6>[ 0.078604] CPU features: detected: Spectre-BHB
1183 23:39:08.245163 <6>[ 0.078609] CPU features: detected: ARM erratum 858921
1184 23:39:08.250680 <6>[ 0.078617] Detected VIPT I-cache on CPU2
1185 23:39:08.259735 <6>[ 0.078688] arch_timer: Enabling local workaround for ARM erratum 858921
1186 23:39:08.265251 <6>[ 0.078705] arch_timer: CPU2: Trapping CNTVCT access
1187 23:39:08.270773 <6>[ 0.078715] CPU2: Booted secondary processor 0x0000000100 [0x410fd092]
1188 23:39:08.276321 <6>[ 0.083589] Detected VIPT I-cache on CPU3
1189 23:39:08.281810 <6>[ 0.083634] arch_timer: Enabling local workaround for ARM erratum 858921
1190 23:39:08.287452 <6>[ 0.083643] arch_timer: CPU3: Trapping CNTVCT access
1191 23:39:08.292861 <6>[ 0.083650] CPU3: Booted secondary processor 0x0000000101 [0x410fd092]
1192 23:39:08.298443 <6>[ 0.087629] Detected VIPT I-cache on CPU4
1193 23:39:08.303887 <6>[ 0.087676] arch_timer: Enabling local workaround for ARM erratum 858921
1194 23:39:08.309477 <6>[ 0.087685] arch_timer: CPU4: Trapping CNTVCT access
1195 23:39:08.314942 <6>[ 0.087692] CPU4: Booted secondary processor 0x0000000102 [0x410fd092]
1196 23:39:08.320432 <6>[ 0.091624] Detected VIPT I-cache on CPU5
1197 23:39:08.325973 <6>[ 0.091672] arch_timer: Enabling local workaround for ARM erratum 858921
1198 23:39:08.331509 <6>[ 0.091681] arch_timer: CPU5: Trapping CNTVCT access
1199 23:39:08.337014 <6>[ 0.091688] CPU5: Booted secondary processor 0x0000000103 [0x410fd092]
1200 23:39:08.342518 <6>[ 0.091802] smp: Brought up 1 node, 6 CPUs
1201 23:39:08.348058 <6>[ 0.213028] SMP: Total of 6 processors activated.
1202 23:39:08.353578 <6>[ 0.217934] CPU: All CPU(s) started at EL2
1203 23:39:08.359091 <6>[ 0.222284] CPU features: detected: 32-bit EL0 Support
1204 23:39:08.364597 <6>[ 0.227595] CPU features: detected: 32-bit EL1 Support
1205 23:39:08.370122 <6>[ 0.232941] CPU features: detected: CRC32 instructions
1206 23:39:08.375654 <6>[ 0.238343] alternatives: applying system-wide alternatives
1207 23:39:08.386701 <6>[ 0.245517] Memory: 3557432K/4012396K available (17280K kernel code, 4900K rwdata, 11876K rodata, 10432K init, 742K bss, 187800K reserved, 262144K cma-reserved)
1208 23:39:08.393571 <6>[ 0.259878] devtmpfs: initialized
1209 23:39:08.404614 <6>[ 0.269024] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
1210 23:39:08.410112 <6>[ 0.273377] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
1211 23:39:08.415616 <6>[ 0.284180] 21392 pages in range for non-PLT usage
1212 23:39:08.421166 <6>[ 0.284190] 512912 pages in range for PLT usage
1213 23:39:08.426676 <6>[ 0.285741] pinctrl core: initialized pinctrl subsystem
1214 23:39:08.432216 <6>[ 0.297814] DMI not present or invalid.
1215 23:39:08.437730 <6>[ 0.302116] NET: Registered PF_NETLINK/PF_ROUTE protocol family
1216 23:39:08.443241 <6>[ 0.306851] DMA: preallocated 512 KiB GFP_KERNEL pool for atomic allocations
1217 23:39:08.454349 <6>[ 0.313633] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
1218 23:39:08.459820 <6>[ 0.321731] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
1219 23:39:08.465355 <6>[ 0.329207] audit: initializing netlink subsys (disabled)
1220 23:39:08.470854 <5>[ 0.334941] audit: type=2000 audit(0.256:1): state=initialized audit_enabled=0 res=1
1221 23:39:08.481885 <6>[ 0.336351] thermal_sys: Registered thermal governor 'step_wise'
1222 23:39:08.487488 <6>[ 0.342714] thermal_sys: Registered thermal governor 'power_allocator'
1223 23:39:08.492930 <6>[ 0.348977] cpuidle: using governor menu
1224 23:39:08.498458 <6>[ 0.360024] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
1225 23:39:08.503943 <6>[ 0.366892] ASID allocator initialised with 65536 entries
1226 23:39:08.512204 <6>[ 0.374449] Serial: AMBA PL011 UART driver
1227 23:39:08.518567 <6>[ 0.384958] platform ff600000.hdmi-tx: Fixed dependency cycle(s) with /soc/vpu@ff900000
1228 23:39:08.533642 <6>[ 0.400382] platform ff600000.hdmi-tx: Fixed dependency cycle(s) with /soc/vpu@ff900000
1229 23:39:08.544678 <6>[ 0.403046] platform ff900000.vpu: Fixed dependency cycle(s) with /soc/bus@ff600000/hdmi-tx@0
1230 23:39:08.550187 <6>[ 0.416187] platform ff900000.vpu: Fixed dependency cycle(s) with /cvbs-connector
1231 23:39:08.555700 <6>[ 0.419424] platform cvbs-connector: Fixed dependency cycle(s) with /soc/vpu@ff900000
1232 23:39:08.566760 <6>[ 0.427854] platform ff600000.hdmi-tx: Fixed dependency cycle(s) with /hdmi-connector
1233 23:39:08.572279 <6>[ 0.435475] platform hdmi-connector: Fixed dependency cycle(s) with /soc/bus@ff600000/hdmi-tx@0
1234 23:39:08.583352 <6>[ 0.449056] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
1235 23:39:08.588825 <6>[ 0.451292] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
1236 23:39:08.594358 <6>[ 0.457772] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
1237 23:39:08.599867 <6>[ 0.464750] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
1238 23:39:08.610923 <6>[ 0.471219] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
1239 23:39:08.616521 <6>[ 0.478204] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
1240 23:39:08.621968 <6>[ 0.484674] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
1241 23:39:08.627502 <6>[ 0.491659] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
1242 23:39:08.633015 <6>[ 0.499649] ACPI: Interpreter disabled.
1243 23:39:08.638558 <6>[ 0.505070] iommu: Default domain type: Translated
1244 23:39:08.644056 <6>[ 0.507193] iommu: DMA domain TLB invalidation policy: strict mode
1245 23:39:08.649559 <5>[ 0.513870] SCSI subsystem initialized
1246 23:39:08.655061 <6>[ 0.517751] usbcore: registered new interface driver usbfs
1247 23:39:08.660589 <6>[ 0.523251] usbcore: registered new interface driver hub
1248 23:39:08.666122 <6>[ 0.528774] usbcore: registered new device driver usb
1249 23:39:08.671624 <6>[ 0.535032] pps_core: LinuxPPS API ver. 1 registered
1250 23:39:08.677162 <6>[ 0.539186] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
1251 23:39:08.682670 <6>[ 0.548505] PTP clock support registered
1252 23:39:08.688223 <6>[ 0.552743] EDAC MC: Ver: 3.0.0
1253 23:39:08.693728 <6>[ 0.556379] scmi_core: SCMI protocol bus registered
1254 23:39:08.694161 <6>[ 0.561993] FPGA manager framework
1255 23:39:08.699258 <6>[ 0.564770] Advanced Linux Sound Architecture Driver Initialized.
1256 23:39:08.704744 <6>[ 0.571709] vgaarb: loaded
1257 23:39:08.710286 <6>[ 0.574249] clocksource: Switched to clocksource arch_sys_counter
1258 23:39:08.715794 <5>[ 0.580415] VFS: Disk quotas dquot_6.6.0
1259 23:39:08.721389 <6>[ 0.584398] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
1260 23:39:08.726838 <6>[ 0.591793] pnp: PnP ACPI: disabled
1261 23:39:08.732387 <6>[ 0.600085] NET: Registered PF_INET protocol family
1262 23:39:08.737894 <6>[ 0.600435] IP idents hash table entries: 65536 (order: 7, 524288 bytes, linear)
1263 23:39:08.748919 <6>[ 0.610602] tcp_listen_portaddr_hash hash table entries: 2048 (order: 3, 32768 bytes, linear)
1264 23:39:08.754492 <6>[ 0.616605] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
1265 23:39:08.765543 <6>[ 0.624497] TCP established hash table entries: 32768 (order: 6, 262144 bytes, linear)
1266 23:39:08.771006 <6>[ 0.632736] TCP bind hash table entries: 32768 (order: 8, 1048576 bytes, linear)
1267 23:39:08.776519 <6>[ 0.640527] TCP: Hash tables configured (established 32768 bind 32768)
1268 23:39:08.782044 <6>[ 0.647008] UDP hash table entries: 2048 (order: 4, 65536 bytes, linear)
1269 23:39:08.793075 <6>[ 0.653859] UDP-Lite hash table entries: 2048 (order: 4, 65536 bytes, linear)
1270 23:39:08.798557 <6>[ 0.661280] NET: Registered PF_UNIX/PF_LOCAL protocol family
1271 23:39:08.804087 <6>[ 0.667403] RPC: Registered named UNIX socket transport module.
1272 23:39:08.809641 <6>[ 0.673144] RPC: Registered udp transport module.
1273 23:39:08.815211 <6>[ 0.678049] RPC: Registered tcp transport module.
1274 23:39:08.820671 <6>[ 0.682963] RPC: Registered tcp-with-tls transport module.
1275 23:39:08.826204 <6>[ 0.688656] RPC: Registered tcp NFSv4.1 backchannel transport module.
1276 23:39:08.831724 <6>[ 0.695305] PCI: CLS 0 bytes, default 64
1277 23:39:08.832179 <6>[ 0.699697] Unpacking initramfs...
1278 23:39:08.837229 <6>[ 0.705710] kvm [1]: nv: 554 coarse grained trap handlers
1279 23:39:08.842769 <6>[ 0.708960] kvm [1]: IPA Size Limit: 40 bits
1280 23:39:08.848277 <6>[ 0.714599] kvm [1]: vgic interrupt IRQ9
1281 23:39:08.853809 <6>[ 0.717314] kvm [1]: Hyp nVHE mode initialized successfully
1282 23:39:08.859293 <5>[ 0.724421] Initialise system trusted keyrings
1283 23:39:08.864853 <6>[ 0.727878] workingset: timestamp_bits=42 max_order=20 bucket_order=0
1284 23:39:08.870408 <6>[ 0.734609] squashfs: version 4.0 (2009/01/31) Phillip Lougher
1285 23:39:08.875880 <5>[ 0.740596] NFS: Registering the id_resolver key type
1286 23:39:08.881408 <5>[ 0.745691] Key type id_resolver registered
1287 23:39:08.886913 <5>[ 0.750067] Key type id_legacy registered
1288 23:39:08.892535 <6>[ 0.754306] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
1289 23:39:08.897942 <6>[ 0.761194] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
1290 23:39:08.905370 <6>[ 0.769001] 9p: Installing v9fs 9p2000 file system support
1291 23:39:08.943418 <5>[ 0.815631] Key type asymmetric registered
1292 23:39:08.948893 <5>[ 0.815674] Asymmetric key parser 'x509' registered
1293 23:39:08.959931 <6>[ 0.819532] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 245)
1294 23:39:08.960394 <6>[ 0.827052] io scheduler mq-deadline registered
1295 23:39:08.965547 <6>[ 0.831800] io scheduler kyber registered
1296 23:39:08.970964 <6>[ 0.836061] io scheduler bfq registered
1297 23:39:08.977419 <6>[ 0.843961] irq_meson_gpio: 100 to 8 gpio interrupt mux initialized
1298 23:39:08.993611 <6>[ 0.862120] ledtrig-cpu: registered to indicate activity on CPUs
1299 23:39:09.025973 <6>[ 0.893249] soc soc0: Amlogic Meson G12B (A311D) Revision 29:b (10:2) Detected
1300 23:39:09.045319 <6>[ 0.906321] Serial: 8250/16550 driver, 4 ports<6>[ 0.910943] ff803000.serial: ttyAML0 at MMIO 0xff803000 (irq = 14, base_baud = 1500000) is a meson_uart
1301 23:39:09.050841 <6>[ 0.920571] printk: legacy console [ttyAML0] enabled
1302 23:39:09.056415 <6>[ 0.920571] printk: legacy console [ttyAML0] enabled
1303 23:39:09.061964 <6>[ 0.925372] printk: legacy bootconsole [meson0] disabled
1304 23:39:09.067582 <6>[ 0.925372] printk: legacy bootconsole [meson0] disabled
1305 23:39:09.073031 <6>[ 0.937233] msm_serial: driver initialized
1306 23:39:09.078612 <6>[ 0.941393] SuperH (H)SCI(F) driver initialized
1307 23:39:09.079039 <6>[ 0.945825] STM32 USART driver initialized
1308 23:39:09.084161 <5>[ 0.952003] random: crng init done
1309 23:39:09.091127 <6>[ 0.957550] loop: module loaded
1310 23:39:09.091550 <6>[ 0.958846] megasas: 07.727.03.00-rc1
1311 23:39:09.096710 <6>[ 0.967879] tun: Universal TUN/TAP device driver, 1.6
1312 23:39:09.102233 <6>[ 0.969067] thunder_xcv, ver 1.0
1313 23:39:09.107756 <6>[ 0.971071] thunder_bgx, ver 1.0
1314 23:39:09.108213 <6>[ 0.974516] nicpf, ver 1.0
1315 23:39:09.113339 <6>[ 0.979107] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
1316 23:39:09.118870 <6>[ 0.984904] hns3: Copyright (c) 2017 Huawei Corporation.
1317 23:39:09.124441 <6>[ 0.990491] hclge is initializing
1318 23:39:09.129959 <6>[ 0.994019] e1000: Intel(R) PRO/1000 Network Driver
1319 23:39:09.135591 <6>[ 0.999115] e1000: Copyright (c) 1999-2006 Intel Corporation.
1320 23:39:09.141069 <6>[ 1.005135] e1000e: Intel(R) PRO/1000 Network Driver
1321 23:39:09.146619 <6>[ 1.010290] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
1322 23:39:09.152180 <6>[ 1.016477] igb: Intel(R) Gigabit Ethernet Network Driver
1323 23:39:09.157714 <6>[ 1.022079] igb: Copyright (c) 2007-2014 Intel Corporation.
1324 23:39:09.163224 <6>[ 1.027926] igbvf: Intel(R) Gigabit Virtual Function Network Driver
1325 23:39:09.168785 <6>[ 1.034385] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
1326 23:39:09.174327 <6>[ 1.041143] sky2: driver version 1.30
1327 23:39:09.179870 <6>[ 1.046226] VFIO - User Level meta-driver version: 0.3
1328 23:39:09.185440 <6>[ 1.053777] usbcore: registered new interface driver usb-storage
1329 23:39:09.191457 <6>[ 1.059822] i2c_dev: i2c /dev entries driver
1330 23:39:09.204240 <6>[ 1.070928] sdhci: Secure Digital Host Controller Interface driver
1331 23:39:09.204676 <6>[ 1.071731] sdhci: Copyright(c) Pierre Ossman
1332 23:39:09.215337 <6>[ 1.077443] Synopsys Designware Multimedia Card Interface Driver
1333 23:39:09.220851 <6>[ 1.083973] sdhci-pltfm: SDHCI platform and OF driver helper
1334 23:39:09.221284 <6>[ 1.091643] meson-sm: secure-monitor enabled
1335 23:39:09.233747 <6>[ 1.094137] usbcore: registered new interface driver usbhid
1336 23:39:09.234180 <6>[ 1.098788] usbhid: USB HID core driver
1337 23:39:09.241266 <6>[ 1.113503] NET: Registered PF_PACKET protocol family
1338 23:39:09.246805 <6>[ 1.113599] 9pnet: Installing 9P2000 support
1339 23:39:09.253869 <5>[ 1.117747] Key type dns_resolver registered
1340 23:39:09.259458 <6>[ 1.129309] registered taskstats version 1
1341 23:39:09.264969 <5>[ 1.129470] Loading compiled-in X.509 certificates
1342 23:39:09.268659 <6>[ 1.138081] Demotion targets for Node 0: null
1343 23:39:09.297594 <6>[ 1.169826] dwc3-meson-g12a ffe09000.usb: USB2 ports: 2
1344 23:39:09.303135 <6>[ 1.169866] dwc3-meson-g12a ffe09000.usb: USB3 ports: 1
1345 23:39:09.314227 <4>[ 1.179075] dwc2 ff400000.usb: supply vusb_d not found, using dummy regulator
1346 23:39:09.319785 <4>[ 1.182618] dwc2 ff400000.usb: supply vusb_a not found, using dummy regulator
1347 23:39:09.325347 <6>[ 1.190144] dwc2 ff400000.usb: EPs: 7, dedicated fifos, 712 entries in SPRAM
1348 23:39:09.330879 <6>[ 1.199447] xhci-hcd xhci-hcd.0.auto: xHCI Host Controller
1349 23:39:09.341980 <6>[ 1.202910] xhci-hcd xhci-hcd.0.auto: new USB bus registered, assigned bus number 1
1350 23:39:09.353062 <6>[ 1.210889] xhci-hcd xhci-hcd.0.auto: hcc params 0x0228fe6c hci version 0x110 quirks 0x0000808000000010
1351 23:39:09.358597 <6>[ 1.220436] xhci-hcd xhci-hcd.0.auto: irq 16, io mem 0xff500000
1352 23:39:09.364228 <6>[ 1.226648] xhci-hcd xhci-hcd.0.auto: xHCI Host Controller
1353 23:39:09.369739 <6>[ 1.232274] xhci-hcd xhci-hcd.0.auto: new USB bus registered, assigned bus number 2
1354 23:39:09.375244 <6>[ 1.240160] xhci-hcd xhci-hcd.0.auto: Host supports USB 3.0 SuperSpeed
1355 23:39:09.380792 <6>[ 1.247409] hub 1-0:1.0: USB hub found
1356 23:39:09.386335 <6>[ 1.250934] hub 1-0:1.0: 2 ports detected
1357 23:39:09.391873 <6>[ 1.256969] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
1358 23:39:09.397476 <6>[ 1.263911] hub 2-0:1.0: USB hub found
1359 23:39:09.402555 <6>[ 1.267476] hub 2-0:1.0: 1 port detected
1360 23:39:09.428266 <6>[ 1.297926] meson-gx-mmc ffe05000.mmc: Got CD GPIO
1361 23:39:09.440309 <6>[ 1.309194] meson-gx-mmc ffe07000.mmc: allocated mmc-pwrseq
1362 23:39:09.473179 <6>[ 1.341721] Trying to probe devices needed for running init ...
1363 23:39:09.638357 <6>[ 1.506282] usb 1-1: new high-speed USB device number 2 using xhci-hcd
1364 23:39:09.782917 <6>[ 1.649597] mmc0: new ultra high speed SDR104 SDXC card at address e624
1365 23:39:09.789128 <6>[ 1.651612] mmcblk0: mmc0:e624 SD64G 59.5 GiB
1366 23:39:09.789573 <6>[ 1.657674] mmcblk0: p1
1367 23:39:09.799119 <6>[ 1.669577] Freeing initrd memory: 22884K
1368 23:39:09.823058 <6>[ 1.695243] hub 1-1:1.0: USB hub found
1369 23:39:09.828801 <6>[ 1.695568] hub 1-1:1.0: 4 ports detected
1370 23:39:09.898449 <6>[ 1.766389] usb 2-1: new SuperSpeed USB device number 2 using xhci-hcd
1371 23:39:09.935713 <6>[ 1.807910] hub 2-1:1.0: USB hub found
1372 23:39:09.941443 <6>[ 1.808732] hub 2-1:1.0: 4 ports detected
1373 23:39:21.742547 <6>[ 13.614308] clk: Disabling unused clocks
1374 23:39:21.747815 <6>[ 13.614477] PM: genpd: Disabling unused power domains
1375 23:39:21.756418 <6>[ 13.618168] ALSA device list:
1376 23:39:21.756873 <6>[ 13.621371] No soundcards found.
1377 23:39:21.761927 <6>[ 13.633727] Freeing unused kernel memory: 10432K
1378 23:39:21.767899 <6>[ 13.633826] Run /init as init process
1379 23:39:21.773769 Loading, please wait...
1380 23:39:21.811527 Starting systemd-udevd version 252.22-1~deb12u1
1381 23:39:22.237636 <6>[ 14.109423] mc: Linux media interface: v0.10
1382 23:39:22.245198 <6>[ 14.113823] videodev: Linux video capture interface: v2.00
1383 23:39:22.283304 <4>[ 14.149780] meson_vdec: module is from the staging directory, the quality is unknown, you have been warned.
1384 23:39:22.292673 <4>[ 14.155993] meson-pwm ff802000.pwm: using obsolete compatible, please consider updating dt
1385 23:39:22.302899 <6>[ 14.171731] meson-drm ff900000.vpu: Queued 2 outputs on vpu
1386 23:39:22.324484 <6>[ 14.196571] panfrost ffe40000.gpu: clock rate = 24000000
1387 23:39:22.335436 <3>[ 14.196665] panfrost ffe40000.gpu: error -ENODEV: _opp_set_regulators: no regulator (mali) found
1388 23:39:22.341069 <6>[ 14.196835] meson-vrtc ff8000a8.rtc: registered as rtc0
1389 23:39:22.352145 <6>[ 14.198328] meson-dw-hdmi ff600000.hdmi-tx: Detected HDMI TX controller v2.01a with HDCP (meson_dw_hdmi_phy)
1390 23:39:22.357666 <6>[ 14.199491] meson-dw-hdmi ff600000.hdmi-tx: registered DesignWare HDMI I2C bus driver
1391 23:39:22.368802 <6>[ 14.200069] meson-drm ff900000.vpu: bound ff600000.hdmi-tx (ops meson_dw_hdmi_ops [meson_dw_hdmi])
1392 23:39:22.374335 <3>[ 14.200162] meson-drm ff900000.vpu: DSI transceiver device is disabled
1393 23:39:22.379866 <6>[ 14.207173] meson8b-dwmac ff3f0000.ethernet: IRQ eth_wake_irq not found
1394 23:39:22.390983 <6>[ 14.212680] meson-vrtc ff8000a8.rtc: setting system clock to 1970-01-01T00:00:14 UTC (14)
1395 23:39:22.396463 <6>[ 14.215593] [drm] Initialized meson 1.0.0 for ff900000.vpu on minor 0
1396 23:39:22.407514 <6>[ 14.217058] panfrost ffe40000.gpu: mali-g52 id 0x7212 major 0x0 minor 0x0 status 0x0
1397 23:39:22.413073 <6>[ 14.217072] panfrost ffe40000.gpu: features: 00000000,00000cf7, issues: 00000000,00000400
1398 23:39:22.424190 <6>[ 14.217080] panfrost ffe40000.gpu: Features: L2:0x07110206 Shader:0x00000000 Tiler:0x00000809 Mem:0x1 MMU:0x00002830 AS:0xff JS:0x7
1399 23:39:22.435254 <6>[ 14.217089] panfrost ffe40000.gpu: shader_present=0x3 l2_present=0x1
1400 23:39:22.440793 <6>[ 14.221142] meson8b-dwmac ff3f0000.ethernet: IRQ eth_lpi not found
1401 23:39:22.446410 <3>[ 14.223016] debugfs: Directory 'ff800280.cec' with parent 'regmap' already present!
1402 23:39:22.451906 <6>[ 14.316416] meson8b-dwmac ff3f0000.ethernet: IRQ sfty not found
1403 23:39:22.459902 <6>[ 14.323571] meson8b-dwmac ff3f0000.ethernet: PTP uses main clock
1404 23:39:22.646747 <6>[ 14.329562] meson8b-dwmac ff3f0000.ethernet: User ID: 0x11, Synopsys ID: 0x37
1405 23:39:22.652309 <6>[ 14.329580] meson8b-dwmac ff3f0000.ethernet: DWMAC1000
1406 23:39:22.661305 <6>[ 14.329586] meson8b-dwmac ff3f0000.ethernet: DMA HW capability register supported
1407 23:39:22.666830 <6>[ 14.329590] meson8b-dwmac ff3f0000.ethernet: RX Checksum Offload Engine supported
1408 23:39:22.672455 <6>[ 14.329595] meson8b-dwmac ff3f0000.ethernet: COE Type 2
1409 23:39:22.681405 <6>[ 14.329600] meson8b-dwmac ff3f0000.ethernet: TX Checksum insertion supported
1410 23:39:22.686934 <6>[ 14.329604] meson8b-dwmac ff3f0000.ethernet: Wake-Up On Lan supported
1411 23:39:22.692490 <6>[ 14.331375] usbcore: registered new device driver onboard-usb-dev
1412 23:39:22.698034 <6>[ 14.334478] meson8b-dwmac ff3f0000.ethernet: Normal descriptors
1413 23:39:22.703581 <6>[ 14.334490] meson8b-dwmac ff3f0000.ethernet: Ring mode enabled
1414 23:39:22.714693 <6>[ 14.334495] meson8b-dwmac ff3f0000.ethernet: Enable RX Mitigation via HW Watchdog Timer
1415 23:39:22.720264 <6>[ 14.334508] [drm] Initialized panfrost 1.2.0 for ffe40000.gpu on minor 1
1416 23:39:22.725769 <6>[ 14.341542] Registered IR keymap rc-empty
1417 23:39:22.731297 <6>[ 14.341688] rc rc0: meson-ir as /devices/platform/soc/ff800000.bus/ff808000.ir/rc/rc0
1418 23:39:22.742416 <6>[ 14.341812] input: meson-ir as /devices/platform/soc/ff800000.bus/ff808000.ir/rc/rc0/input0
1419 23:39:22.742858 <6>[ 14.344992] rc rc0: sw decoder init
1420 23:39:22.747926 <6>[ 14.345040] meson-ir ff808000.ir: receiver initialized
1421 23:39:22.753504 <6>[ 14.377511] meson8b-dwmac ff3f0000.ethernet end0: renamed from eth0
1422 23:39:22.764604 <6>[ 14.377709] cpufreq: cpufreq_online: CPU2: Running at unlisted initial frequency: 999999 KHz, changing to: 1000000 KHz
1423 23:39:22.775702 <6>[ 14.491042] Console: switching to colour frame buffer device 128x48
1424 23:39:22.781393 <6>[ 14.643135] meson-drm ff900000.vpu: [drm] fb0: mesondrmfb frame buffer device
1425 23:39:23.007076 <6>[ 14.879243] hub 1-1:1.0: USB hub found
1426 23:39:23.011782 <6>[ 14.879539] hub 1-1:1.0: 4 ports detected
1427 23:39:23.155572 <4>[ 15.022271] xhci-hcd xhci-hcd.0.auto: USB core suspending port 1-1 not in U0/U1/U2
1428 23:39:23.161114 <3>[ 15.024633] onboard-usb-dev 1-1: Failed to suspend device, error -32
1429 23:39:23.167143 <3>[ 15.031068] onboard-usb-dev 1-1: can't set config #1, error -71
1430 23:39:23.183636 <4>[ 15.050275] xhci-hcd xhci-hcd.0.auto: USB core suspending port 1-1 not in U0/U1/U2
1431 23:39:23.189118 <6>[ 15.052601] onboard-usb-dev 1-1: USB disconnect, device number 2
1432 23:39:23.195262 <3>[ 15.052647] onboard-usb-dev 1-1: Failed to suspend device, error -32
1433 23:39:23.441455 <6>[ 15.310303] usb 1-1: new high-speed USB device number 3 using xhci-hcd
1434 23:39:23.615200 <6>[ 15.487387] hub 1-1:1.0: USB hub found
1435 23:39:23.620907 <6>[ 15.487713] hub 1-1:1.0: 4 ports detected
1436 23:39:23.627541 Begin: Loading essential drivers ... done.
1437 23:39:23.633100 Begin: Running /scripts/init-premount ... done.
1438 23:39:23.638645 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
1439 23:39:23.652070 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
1440 23:39:23.652522 Device /sys/class/net/end0 found
1441 23:39:23.652956 done.
1442 23:39:23.661946 Begin: Waiting up to 180 secs for any network device to become available ... done.
1443 23:39:23.729291 IP-Config: end0 hardware address de:ca:d3:e3:c6:63 mtu 1500 DHCP
<6>[ 15.591404] meson8b-dwmac ff3f0000.ethernet end0: Register MEM_TYPE_PAGE_POOL RxQ-0
1444 23:39:23.730041
1445 23:39:23.779450 <6>[ 15.647229] usb 2-1: reset SuperSpeed USB device number 2 using xhci-hcd
1446 23:39:23.794297 <6>[ 15.658356] meson8b-dwmac ff3f0000.ethernet end0: PHY [mdio_mux-0.0:00] driver [RTL8211F Gigabit Ethernet] (irq=32)
1447 23:39:23.808443 <6>[ 15.675106] meson8b-dwmac ff3f0000.ethernet end0: No Safety Features support found
1448 23:39:23.813954 <6>[ 15.677295] meson8b-dwmac ff3f0000.ethernet end0: PTP not supported by HW
1449 23:39:23.823260 <6>[ 15.684632] meson8b-dwmac ff3f0000.ethernet end0: configuring for phy/rgmii link mode
1450 23:39:24.035446 <6>[ 15.903202] usb 2-1: reset SuperSpeed USB device number 2 using xhci-hcd
1451 23:39:25.214192 <4>[ 17.086257] rc rc0: two consecutive events of type space
1452 23:39:25.842349 IP-Config: no response after 2 secs - giving up
1453 23:39:25.905319 IP-Config: end0 hardware address de:ca:d3:e3:c6:63 mtu 1500 DHCP
1454 23:39:26.785852 <6>[ 18.651883] meson8b-dwmac ff3f0000.ethernet end0: Link is Up - 1Gbps/Full - flow control off
1455 23:39:28.113201 IP-Config: end0 guessed broadcast address 192.168.6.255
1456 23:39:28.118514 IP-Config: end0 complete (dhcp from 192.168.6.1):
1457 23:39:28.124057 address: 192.168.6.27 broadcast: 192.168.6.255 netmask: 255.255.255.0
1458 23:39:28.135139 gateway: 192.168.6.1 dns0 : 10.255.253.1 dns1 : 0.0.0.0
1459 23:39:28.135594 rootserver: 192.168.6.1 rootpath:
1460 23:39:28.138538 filename :
1461 23:39:28.236625 done.
1462 23:39:28.242506 Begin: Running /scripts/nfs-bottom ... done.
1463 23:39:28.256888 Begin: Running /scripts/init-bottom ... done.
1464 23:39:28.587895 <30>[ 20.455708] systemd[1]: System time before build time, advancing clock.
1465 23:39:28.647312 <6>[ 20.519549] NET: Registered PF_INET6 protocol family
1466 23:39:28.652793 <6>[ 20.521054] Segment Routing with IPv6
1467 23:39:28.658053 <6>[ 20.523075] In-situ OAM (IOAM) with IPv6
1468 23:39:28.733792 <30>[ 20.578335] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
1469 23:39:28.739356 <30>[ 20.605806] systemd[1]: Detected architecture arm64.
1470 23:39:28.739823
1471 23:39:28.746755 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
1472 23:39:28.747204
1473 23:39:28.759565 <30>[ 20.628001] systemd[1]: Hostname set to <debian-bookworm-arm64>.
1474 23:39:29.486830 <30>[ 21.354000] systemd[1]: Queued start job for default target graphical.target.
1475 23:39:29.529928 <30>[ 21.396624] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
1476 23:39:29.537970 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
1477 23:39:29.548541 <30>[ 21.415258] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
1478 23:39:29.557034 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
1479 23:39:29.568742 <30>[ 21.435351] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
1480 23:39:29.582170 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
1481 23:39:29.587788 <30>[ 21.455034] systemd[1]: Created slice user.slice - User and Session Slice.
1482 23:39:29.594120 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
1483 23:39:29.605089 <30>[ 21.470533] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
1484 23:39:29.616544 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
1485 23:39:29.628178 <30>[ 21.490454] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
1486 23:39:29.634326 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
1487 23:39:29.657732 <30>[ 21.510444] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
1488 23:39:29.662049 <30>[ 21.524506] systemd[1]: Expecting device dev-ttyAML0.device - /dev/ttyAML0...
1489 23:39:29.676420 Expecting device [0;1;39mdev-ttyAML0.device[0m - /dev/ttyAML0...
1490 23:39:29.681037 <30>[ 21.546344] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
1491 23:39:29.695366 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
1492 23:39:29.703667 <30>[ 21.570364] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
1493 23:39:29.717533 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
1494 23:39:29.723076 <30>[ 21.590400] systemd[1]: Reached target paths.target - Path Units.
1495 23:39:29.731576 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
1496 23:39:29.736980 <30>[ 21.606353] systemd[1]: Reached target remote-fs.target - Remote File Systems.
1497 23:39:29.748926 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
1498 23:39:29.754404 <30>[ 21.622347] systemd[1]: Reached target slices.target - Slice Units.
1499 23:39:29.760327 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
1500 23:39:29.772481 <30>[ 21.638358] systemd[1]: Reached target swap.target - Swaps.
1501 23:39:29.775222 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
1502 23:39:29.787818 <30>[ 21.654381] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
1503 23:39:29.796300 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
1504 23:39:29.812548 <30>[ 21.678536] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
1505 23:39:29.822483 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
1506 23:39:29.833823 <30>[ 21.700380] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
1507 23:39:29.841696 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
1508 23:39:29.856563 <30>[ 21.723279] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
1509 23:39:29.865607 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
1510 23:39:29.876719 <30>[ 21.742716] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
1511 23:39:29.883321 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
1512 23:39:29.896579 <30>[ 21.763296] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
1513 23:39:29.905738 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
1514 23:39:29.918319 <30>[ 21.785033] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
1515 23:39:29.923874 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
1516 23:39:29.938365 <30>[ 21.802584] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
1517 23:39:29.943790 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
1518 23:39:29.983810 <30>[ 21.850461] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
1519 23:39:29.990291 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
1520 23:39:30.002333 <30>[ 21.868976] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
1521 23:39:30.009828 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
1522 23:39:30.022221 <30>[ 21.888902] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
1523 23:39:30.030104 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
1524 23:39:30.047900 <30>[ 21.906644] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
1525 23:39:30.053517 <30>[ 21.919729] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
1526 23:39:30.062729 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
1527 23:39:30.082558 <30>[ 21.949198] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
1528 23:39:30.090126 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
1529 23:39:30.102600 <30>[ 21.969246] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
1530 23:39:30.110143 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
1531 23:39:30.122577 <30>[ 21.989256] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
1532 23:39:30.138546 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel <6>[ 21.997427] device-mapper: ioctl: 4.48.0-ioctl (2023-03-01) initialised: dm-devel@lists.linux.dev
1533 23:39:30.139235 Module drm...
1534 23:39:30.150924 <30>[ 22.017574] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
1535 23:39:30.159179 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
1536 23:39:30.170354 <30>[ 22.037009] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
1537 23:39:30.177578 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
1538 23:39:30.190520 <30>[ 22.057216] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
1539 23:39:30.196068 <6>[ 22.060190] fuse: init (API version 7.41)
1540 23:39:30.199606 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
1541 23:39:30.216533 <30>[ 22.083100] systemd[1]: Starting systemd-journald.service - Journal Service...
1542 23:39:30.221878 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
1543 23:39:30.238077 <30>[ 22.104759] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
1544 23:39:30.244758 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
1545 23:39:30.257823 <30>[ 22.124461] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
1546 23:39:30.266766 Starting [0;1;39msystemd-network-g… units from Kernel command line...
1547 23:39:30.283066 <30>[ 22.149772] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
1548 23:39:30.290910 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
1549 23:39:30.308739 <30>[ 22.175459] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
1550 23:39:30.315885 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
1551 23:39:30.330225 <30>[ 22.196859] systemd[1]: Started systemd-journald.service - Journal Service.
1552 23:39:30.336066 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
1553 23:39:30.348727 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
1554 23:39:30.364624 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
1555 23:39:30.376260 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
1556 23:39:30.388565 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
1557 23:39:30.400835 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
1558 23:39:30.412833 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
1559 23:39:30.424573 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
1560 23:39:30.436854 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
1561 23:39:30.456662 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
1562 23:39:30.468905 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
1563 23:39:30.480639 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
1564 23:39:30.492585 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
1565 23:39:30.504639 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
1566 23:39:30.517131 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
1567 23:39:30.574589 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
1568 23:39:30.581141 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
1569 23:39:30.594023 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
1570 23:39:30.605509 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
1571 23:39:30.620275 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
1572 23:39:30.632564 <46>[ 22.499065] systemd-journald[229]: Received client request to flush runtime journal.
1573 23:39:30.639690 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
1574 23:39:30.661271 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
1575 23:39:30.672639 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
1576 23:39:30.688621 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
1577 23:39:30.701051 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
1578 23:39:30.712925 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
1579 23:39:30.781056 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
1580 23:39:30.812047 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
1581 23:39:30.947797 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
1582 23:39:30.971925 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
1583 23:39:30.978385 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
1584 23:39:30.995559 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
1585 23:39:31.034669 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
1586 23:39:31.047536 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
1587 23:39:31.284500 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
1588 23:39:31.292925 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
1589 23:39:31.339507 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
1590 23:39:31.357026 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
1591 23:39:31.370118 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
1592 23:39:31.413782 [[0;32m OK [0m] Found device [0;1;39mdev-ttyAML0.device[0m - /dev/ttyAML0.
1593 23:39:31.451442 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
1594 23:39:31.519306 <5>[ 23.386015] cfg80211: Loading compiled-in X.509 certificates for regulatory database
1595 23:39:31.554964 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
1596 23:39:31.560401 <5>[ 23.429822] Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
1597 23:39:31.567006 <5>[ 23.430546] Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
1598 23:39:31.578052 <4>[ 23.438993] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
1599 23:39:31.582299 <6>[ 23.447019] cfg80211: failed to load regulatory.db
1600 23:39:31.598434 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
1601 23:39:31.620699 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanu<46>[ 23.475646] systemd-journald[229]: Oldest entry in /var/log/journal/44a983756b26438995e691b947c527e4/system.journal is older than the configured file retention duration (1month), suggesting rotation.
1602 23:39:31.638913 <46>[ 23.491404] systemd-journald[229]: /var/log/journal/44a983756b26438995e691b947c527e4/system.journal: Journal header limits reached or header out-of-date, rotating.
1603 23:39:31.639458 p of Temporary Directories.
1604 23:39:31.648400 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
1605 23:39:31.670737 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
1606 23:39:31.759965 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
1607 23:39:31.776422 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
1608 23:39:31.825457 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
1609 23:39:31.840076 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
1610 23:39:31.847055 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
1611 23:39:31.887873 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
1612 23:39:31.894388 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
1613 23:39:31.902906 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
1614 23:39:31.954856 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
1615 23:39:31.972892 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
1616 23:39:32.005823 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
1617 23:39:32.013040 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
1618 23:39:32.056130 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
1619 23:39:32.068210 [[0;32m OK [0m] Reached target [0;1;39musb-gadget.…m - Hardware activated USB gadget.
1620 23:39:32.084207 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
1621 23:39:32.138901 Starting [0;1;39malsa-restore.serv…- Save/Restore Sound Card State...
1622 23:39:32.144976 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
1623 23:39:32.155601 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
1624 23:39:32.175357 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
1625 23:39:32.196425 [[0;32m OK [0m] Finished [0;1;39malsa-restore.serv…m - Save/Restore Sound Card State.
1626 23:39:32.207646 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
1627 23:39:32.226079 [[0;32m OK [0m] Reached target [0;1;39msound.target[0m - Sound Card.
1628 23:39:32.283023 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
1629 23:39:32.295759 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyAM…ice[0m - Serial Getty on ttyAML0.
1630 23:39:32.302827 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
1631 23:39:32.309212 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
1632 23:39:32.328837 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
1633 23:39:32.340023 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
1634 23:39:32.403905 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
1635 23:39:32.453567 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
1636 23:39:32.538364
1637 23:39:32.539007 Debian GNU/Linux 12 debian-bookworm-arm64 ttyAML0
1638 23:39:32.539511
1639 23:39:32.545506 debian-bookworm-arm64 login: root (automatic login)
1640 23:39:32.546067
1641 23:39:32.699350 Linux debian-bookworm-arm64 6.12.0-rc6 #1 SMP PREEMPT Tue Nov 5 23:01:29 UTC 2024 aarch64
1642 23:39:32.700043
1643 23:39:32.705010 The programs included with the Debian GNU/Linux system are free software;
1644 23:39:32.710461 the exact distribution terms for each program are described in the
1645 23:39:32.715938 individual files in /usr/share/doc/*/copyright.
1646 23:39:32.716495
1647 23:39:32.721602 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
1648 23:39:32.724839 permitted by applicable law.
1649 23:39:33.434177 Matched prompt #10: / #
1651 23:39:33.435882 Setting prompt string to ['/ #']
1652 23:39:33.436578 end: 2.4.4.1 login-action (duration 00:00:26) [common]
1654 23:39:33.438117 end: 2.4.4 auto-login-action (duration 00:00:26) [common]
1655 23:39:33.438721 start: 2.4.5 expect-shell-connection (timeout 00:03:17) [common]
1656 23:39:33.439215 Setting prompt string to ['/ #']
1657 23:39:33.439678 Forcing a shell prompt, looking for ['/ #']
1659 23:39:33.490769 / #
1660 23:39:33.491437 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
1661 23:39:33.491945 Waiting using forced prompt support (timeout 00:02:30)
1662 23:39:33.496749
1663 23:39:33.497649 end: 2.4.5 expect-shell-connection (duration 00:00:00) [common]
1664 23:39:33.498296 start: 2.4.6 export-device-env (timeout 00:03:17) [common]
1665 23:39:33.498842 Sending with 10 millisecond of delay
1667 23:39:38.487103 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/943265/extract-nfsrootfs-4cipzu_g'
1668 23:39:38.498099 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/943265/extract-nfsrootfs-4cipzu_g'
1669 23:39:38.498922 Sending with 10 millisecond of delay
1671 23:39:40.596961 / # export NFS_SERVER_IP='192.168.6.2'
1672 23:39:40.607900 export NFS_SERVER_IP='192.168.6.2'
1673 23:39:40.608858 end: 2.4.6 export-device-env (duration 00:00:07) [common]
1674 23:39:40.609499 end: 2.4 uboot-commands (duration 00:01:50) [common]
1675 23:39:40.610137 end: 2 uboot-action (duration 00:01:50) [common]
1676 23:39:40.610760 start: 3 lava-test-retry (timeout 00:06:52) [common]
1677 23:39:40.611394 start: 3.1 lava-test-shell (timeout 00:06:52) [common]
1678 23:39:40.611928 Using namespace: common
1680 23:39:40.713224 / # #
1681 23:39:40.713981 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
1682 23:39:40.718784 #
1683 23:39:40.719604 Using /lava-943265
1685 23:39:40.820859 / # export SHELL=/bin/bash
1686 23:39:40.826425 export SHELL=/bin/bash
1688 23:39:40.927938 / # . /lava-943265/environment
1689 23:39:40.932818 . /lava-943265/environment
1691 23:39:41.037609 / # /lava-943265/bin/lava-test-runner /lava-943265/0
1692 23:39:41.038437 Test shell timeout: 10s (minimum of the action and connection timeout)
1693 23:39:41.041508 /lava-943265/bin/lava-test-runner /lava-943265/0
1694 23:39:41.232337 + export TESTRUN_ID=0_timesync-off
1695 23:39:41.239173 + TESTRUN_ID=0_timesync-off
1696 23:39:41.239730 + cd /lava-943265/0/tests/0_timesync-off
1697 23:39:41.240355 ++ cat uuid
1698 23:39:41.245079 + UUID=943265_1.6.2.4.1
1699 23:39:41.245636 + set +x
1700 23:39:41.252633 <LAVA_SIGNAL_STARTRUN 0_timesync-off 943265_1.6.2.4.1>
1701 23:39:41.253182 + systemctl stop systemd-timesyncd
1702 23:39:41.253996 Received signal: <STARTRUN> 0_timesync-off 943265_1.6.2.4.1
1703 23:39:41.254497 Starting test lava.0_timesync-off (943265_1.6.2.4.1)
1704 23:39:41.255153 Skipping test definition patterns.
1705 23:39:41.306841 + set +x
1706 23:39:41.307488 <LAVA_SIGNAL_ENDRUN 0_timesync-off 943265_1.6.2.4.1>
1707 23:39:41.308236 Received signal: <ENDRUN> 0_timesync-off 943265_1.6.2.4.1
1708 23:39:41.308879 Ending use of test pattern.
1709 23:39:41.309458 Ending test lava.0_timesync-off (943265_1.6.2.4.1), duration 0.05
1711 23:39:41.391755 + export TESTRUN_ID=1_kselftest-alsa
1712 23:39:41.399243 + TESTRUN_ID=1_kselftest-alsa
1713 23:39:41.399859 + cd /lava-943265/0/tests/1_kselftest-alsa
1714 23:39:41.400440 ++ cat uuid
1715 23:39:41.409127 + UUID=943265_1.6.2.4.5
1716 23:39:41.409688 + set +x
1717 23:39:41.414695 <LAVA_SIGNAL_STARTRUN 1_kselftest-alsa 943265_1.6.2.4.5>
1718 23:39:41.415246 + cd ./automated/linux/kselftest/
1719 23:39:41.416040 Received signal: <STARTRUN> 1_kselftest-alsa 943265_1.6.2.4.5
1720 23:39:41.416522 Starting test lava.1_kselftest-alsa (943265_1.6.2.4.5)
1721 23:39:41.417049 Skipping test definition patterns.
1722 23:39:41.442445 + ./kselftest.sh -c alsa -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/next/pending-fixes/v6.12-rc6-237-g47f01a19a6ee2/arm64/defconfig/gcc-12/kselftest.tar.xz -L '' -S /dev/null -b meson-g12b-a311d-libretech-cc -g next -e '' -p /opt/kselftests/mainline/ -n 1 -i 1 -E ''
1723 23:39:41.481868 INFO: install_deps skipped
1724 23:39:41.595596 --2024-11-05 23:39:41-- http://storage.kernelci.org/next/pending-fixes/v6.12-rc6-237-g47f01a19a6ee2/arm64/defconfig/gcc-12/kselftest.tar.xz
1725 23:39:41.616740 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
1726 23:39:41.752447 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
1727 23:39:41.887238 HTTP request sent, awaiting response... 200 OK
1728 23:39:41.887859 Length: 6930112 (6.6M) [application/octet-stream]
1729 23:39:41.892763 Saving to: 'kselftest_armhf.tar.gz'
1730 23:39:41.893322
1731 23:39:43.281080
kselftest_armhf.tar 0%[ ] 0 --.-KB/s
kselftest_armhf.tar 0%[ ] 49.92K 185KB/s
kselftest_armhf.tar 3%[ ] 218.67K 403KB/s
kselftest_armhf.tar 13%[=> ] 893.67K 1.08MB/s
kselftest_armhf.tar 53%[=========> ] 3.51M 3.24MB/s
kselftest_armhf.tar 99%[==================> ] 6.54M 4.74MB/s
kselftest_armhf.tar 100%[===================>] 6.61M 4.78MB/s in 1.4s
1732 23:39:43.281868
1733 23:39:43.367231 2024-11-05 23:39:43 (4.78 MB/s) - 'kselftest_armhf.tar.gz' saved [6930112/6930112]
1734 23:39:43.367936
1735 23:39:52.653207 skiplist:
1736 23:39:52.653865 ========================================
1737 23:39:52.658815 ========================================
1738 23:39:52.696251 alsa:mixer-test
1739 23:39:52.696784 alsa:pcm-test
1740 23:39:52.697231 alsa:test-pcmtest-driver
1741 23:39:52.700402 alsa:utimer-test
1742 23:39:52.711560 ============== Tests to run ===============
1743 23:39:52.712108 alsa:mixer-test
1744 23:39:52.717026 alsa:pcm-test
1745 23:39:52.717527 alsa:test-pcmtest-driver
1746 23:39:52.717970 alsa:utimer-test
1747 23:39:52.725314 ===========End Tests to run ===============
1748 23:39:52.725820 shardfile-alsa pass
1749 23:39:52.845876 <12>[ 44.715757] kselftest: Running tests in alsa
1750 23:39:52.853522 TAP version 13
1751 23:39:52.863508 1..4
1752 23:39:52.884627 # timeout set to 45
1753 23:39:52.885188 # selftests: alsa: mixer-test
1754 23:39:53.045807 # TAP version 13
1755 23:39:53.046453 # # Card 0/LCALTA - LC-ALTA (LC-ALTA)
1756 23:39:53.051027 # 1..427
1757 23:39:53.051551 # ok 1 get_value.LCALTA.60
1758 23:39:53.052044 # # LCALTA.60 TDMOUT_A SRC SEL
1759 23:39:53.056425 # ok 2 name.LCALTA.60
1760 23:39:53.056965 # ok 3 write_default.LCALTA.60
1761 23:39:53.061921 # ok 4 write_valid.LCALTA.60
1762 23:39:53.062444 # ok 5 write_invalid.LCALTA.60
1763 23:39:53.067391 # ok 6 event_missing.LCALTA.60
1764 23:39:53.067914 # ok 7 event_spurious.LCALTA.60
1765 23:39:53.072968 # ok 8 get_value.LCALTA.59
1766 23:39:53.073486 # # LCALTA.59 TDMOUT_B SRC SEL
1767 23:39:53.078523 # ok 9 name.LCALTA.59
1768 23:39:53.079046 # ok 10 write_default.LCALTA.59
1769 23:39:53.084151 # ok 11 write_valid.LCALTA.59
1770 23:39:53.084704 # ok 12 write_invalid.LCALTA.59
1771 23:39:53.089688 # ok 13 event_missing.LCALTA.59
1772 23:39:53.090224 # ok 14 event_spurious.LCALTA.59
1773 23:39:53.095199 # ok 15 get_value.LCALTA.58
1774 23:39:53.095730 # # LCALTA.58 TDMOUT_C SRC SEL
1775 23:39:53.100680 # ok 16 name.LCALTA.58
1776 23:39:53.101207 # ok 17 write_default.LCALTA.58
1777 23:39:53.106223 # ok 18 write_valid.LCALTA.58
1778 23:39:53.106742 # ok 19 write_invalid.LCALTA.58
1779 23:39:53.111870 # ok 20 event_missing.LCALTA.58
1780 23:39:53.112428 # ok 21 event_spurious.LCALTA.58
1781 23:39:53.117421 # ok 22 get_value.LCALTA.57
1782 23:39:53.117939 # # LCALTA.57 TDMIN_A SRC SEL
1783 23:39:53.118378 # ok 23 name.LCALTA.57
1784 23:39:53.122943 # ok 24 write_default.LCALTA.57
1785 23:39:53.123449 # ok 25 write_valid.LCALTA.57
1786 23:39:53.128467 # ok 26 write_invalid.LCALTA.57
1787 23:39:53.128965 # ok 27 event_missing.LCALTA.57
1788 23:39:53.133913 # ok 28 event_spurious.LCALTA.57
1789 23:39:53.134418 # ok 29 get_value.LCALTA.56
1790 23:39:53.139538 # # LCALTA.56 TDMIN_B SRC SEL
1791 23:39:53.140110 # ok 30 name.LCALTA.56
1792 23:39:53.145026 # ok 31 write_default.LCALTA.56
1793 23:39:53.145538 # ok 32 write_valid.LCALTA.56
1794 23:39:53.150684 # ok 33 write_invalid.LCALTA.56
1795 23:39:53.151194 # ok 34 event_missing.LCALTA.56
1796 23:39:53.156232 # ok 35 event_spurious.LCALTA.56
1797 23:39:53.167260 # ok 36 get_value<3>[ 45.027105] fe.dai-link-5: ASoC: no backend DAIs enabled for fe.dai-link-5, possibly missing ALSA mixer-based routing or UCM profile
1798 23:39:53.167807 .LCALTA.55
1799 23:39:53.172737 # # LCALTA.55 TDMIN_C SRC SEL
1800 23:39:53.173245 # ok 37 name.LCALTA.55
1801 23:39:53.178283 # ok 38 write_default.LCALTA.55
1802 23:39:53.178801 # ok 39 write_valid.LCALTA.55
1803 23:39:53.183823 # ok 40 write_invalid.LCALTA.55
1804 23:39:53.184373 # ok 41 event_missing.LCALTA.55
1805 23:39:53.189378 # ok 42 event_spurious.LCALTA.55
1806 23:39:53.189882 # ok 43 get_value.LCALTA.54
1807 23:39:53.194883 # # LCALTA.54 ACODEC Left DAC Sel
1808 23:39:53.195396 # ok 44 name.LCALTA.54
1809 23:39:53.200470 # ok 45 write_default.LCALTA.54
1810 23:39:53.200977 # ok 46 write_valid.LCALTA.54
1811 23:39:53.206009 # ok 47 write_invalid.LCALTA.54
1812 23:39:53.206508 # ok 48 event_missing.LCALTA.54
1813 23:39:53.211585 # ok 49 event_spurious.LCALTA.54
1814 23:39:53.212123 # ok 50 get_value.LCALTA.53
1815 23:39:53.217119 # # LCALTA.53 ACODEC Right DAC Sel
1816 23:39:53.217634 # ok 51 name.LCALTA.53
1817 23:39:53.222654 # ok 52 write_default.LCALTA.53
1818 23:39:53.223150 # ok 53 write_valid.LCALTA.53
1819 23:39:53.228227 # ok 54 write_invalid.LCALTA.53
1820 23:39:53.228734 # ok 55 event_missing.LCALTA.53
1821 23:39:53.233729 # ok 56 event_spurious.LCALTA.53
1822 23:39:53.234228 # ok 57 get_value.LCALTA.52
1823 23:39:53.239274 # # LCALTA.52 TOACODEC OUT EN Switch
1824 23:39:53.239773 # ok 58 name.LCALTA.52
1825 23:39:53.244838 # ok 59 write_default.LCALTA.52
1826 23:39:53.245347 # ok 60 write_valid.LCALTA.52
1827 23:39:53.250353 # ok 61 write_invalid.LCALTA.52
1828 23:39:53.250850 # ok 62 event_missing.LCALTA.52
1829 23:39:53.255913 # ok 63 event_spurious.LCALTA.52
1830 23:39:53.256443 # ok 64 get_value.LCALTA.51
1831 23:39:53.261476 # # LCALTA.51 TOACODEC SRC
1832 23:39:53.261972 # ok 65 name.LCALTA.51
1833 23:39:53.266998 # ok 66 write_default.LCALTA.51
1834 23:39:53.267505 # ok 67 write_valid.LCALTA.51
1835 23:39:53.272631 # ok 68 write_invalid.LCALTA.51
1836 23:39:53.273153 # ok 69 event_missing.LCALTA.51
1837 23:39:53.278132 # ok 70 event_spurious.LCALTA.51
1838 23:39:53.278644 # ok 71 get_value.LCALTA.50
1839 23:39:53.283668 # # LCALTA.50 TOHDMITX SPDIF SRC
1840 23:39:53.284236 # ok 72 name.LCALTA.50
1841 23:39:53.284680 # ok 73 write_default.LCALTA.50
1842 23:39:53.289234 # ok 74 write_valid.LCALTA.50
1843 23:39:53.289753 # ok 75 write_invalid.LCALTA.50
1844 23:39:53.294751 # ok 76 event_missing.LCALTA.50
1845 23:39:53.300321 # ok 77 event_spurious.LCALTA.50
1846 23:39:53.300844 # ok 78 get_value.LCALTA.49
1847 23:39:53.301286 # # LCALTA.49 TOHDMITX Switch
1848 23:39:53.305856 # ok 79 name.LCALTA.49
1849 23:39:53.306371 # ok 80 write_default.LCALTA.49
1850 23:39:53.311393 # ok 81 write_valid.LCALTA.49
1851 23:39:53.311919 # ok 82 write_invalid.LCALTA.49
1852 23:39:53.316956 # ok 83 event_missing.LCALTA.49
1853 23:39:53.317471 # ok 84 event_spurious.LCALTA.49
1854 23:39:53.322489 # ok 85 get_value.LCALTA.48
1855 23:39:53.322995 # # LCALTA.48 TOHDMITX I2S SRC
1856 23:39:53.328041 # ok 86 name.LCALTA.48
1857 23:39:53.328548 # ok 87 write_default.LCALTA.48
1858 23:39:53.333635 # ok 88 write_valid.LCALTA.48
1859 23:39:53.334142 # ok 89 write_invalid.LCALTA.48
1860 23:39:53.339121 # ok 90 event_missing.LCALTA.48
1861 23:39:53.339624 # ok 91 event_spurious.LCALTA.48
1862 23:39:53.344677 # ok 92 get_value.LCALTA.47
1863 23:39:53.345191 # # LCALTA.47 TODDR_C SRC SEL
1864 23:39:53.350243 # ok 93 name.LCALTA.47
1865 23:39:53.350760 # ok 94 write_default.LCALTA.47
1866 23:39:53.355746 # ok 95 write_valid.LCALTA.47
1867 23:39:53.356285 # ok 96 write_invalid.LCALTA.47
1868 23:39:53.361299 # ok 97 event_missing.LCALTA.47
1869 23:39:53.361799 # ok 98 event_spurious.LCALTA.47
1870 23:39:53.366868 # ok 99 get_value.LCALTA.46
1871 23:39:53.367369 # # LCALTA.46 TODDR_B SRC SEL
1872 23:39:53.367805 # ok 100 name.LCALTA.46
1873 23:39:53.372381 # ok 101 write_default.LCALTA.46
1874 23:39:53.377961 # ok 102 write_valid.LCALTA.46
1875 23:39:53.378466 # ok 103 write_invalid.LCALTA.46
1876 23:39:53.383509 # ok 104 event_missing.LCALTA.46
1877 23:39:53.384051 # ok 105 event_spurious.LCALTA.46
1878 23:39:53.389056 # ok 106 get_value.LCALTA.45
1879 23:39:53.389565 # # LCALTA.45 TODDR_A SRC SEL
1880 23:39:53.389996 # ok 107 name.LCALTA.45
1881 23:39:53.394637 # ok 108 write_default.LCALTA.45
1882 23:39:53.400150 # ok 109 write_valid.LCALTA.45
1883 23:39:53.400664 # ok 110 write_invalid.LCALTA.45
1884 23:39:53.405680 # ok 111 event_missing.LCALTA.45
1885 23:39:53.406180 # ok 112 event_spurious.LCALTA.45
1886 23:39:53.411220 # ok 113 get_value.LCALTA.44
1887 23:39:53.411715 # # LCALTA.44 FRDDR_C SINK 3 SEL
1888 23:39:53.416761 # ok 114 name.LCALTA.44
1889 23:39:53.417261 # ok 115 write_default.LCALTA.44
1890 23:39:53.422313 # ok 116 write_valid.LCALTA.44
1891 23:39:53.422809 # ok 117 write_invalid.LCALTA.44
1892 23:39:53.427866 # ok 118 event_missing.LCALTA.44
1893 23:39:53.428393 # ok 119 event_spurious.LCALTA.44
1894 23:39:53.433387 # ok 120 get_value.LCALTA.43
1895 23:39:53.433873 # # LCALTA.43 FRDDR_C SINK 2 SEL
1896 23:39:53.438953 # ok 121 name.LCALTA.43
1897 23:39:53.439462 # ok 122 write_default.LCALTA.43
1898 23:39:53.444502 # ok 123 write_valid.LCALTA.43
1899 23:39:53.444993 # ok 124 write_invalid.LCALTA.43
1900 23:39:53.450048 # ok 125 event_missing.LCALTA.43
1901 23:39:53.450538 # ok 126 event_spurious.LCALTA.43
1902 23:39:53.455631 # ok 127 get_value.LCALTA.42
1903 23:39:53.456152 # # LCALTA.42 FRDDR_C SINK 1 SEL
1904 23:39:53.461148 # ok 128 name.LCALTA.42
1905 23:39:53.461635 # ok 129 write_default.LCALTA.42
1906 23:39:53.466672 # ok 130 write_valid.LCALTA.42
1907 23:39:53.467156 # ok 131 write_invalid.LCALTA.42
1908 23:39:53.472265 # ok 132 event_missing.LCALTA.42
1909 23:39:53.472754 # ok 133 event_spurious.LCALTA.42
1910 23:39:53.477772 # ok 134 get_value.LCALTA.41
1911 23:39:53.478262 # # LCALTA.41 FRDDR_C SRC 3 EN Switch
1912 23:39:53.483337 # ok 135 name.LCALTA.41
1913 23:39:53.483828 # ok 136 write_default.LCALTA.41
1914 23:39:53.488857 # ok 137 write_valid.LCALTA.41
1915 23:39:53.489350 # ok 138 write_invalid.LCALTA.41
1916 23:39:53.494411 # ok 139 event_missing.LCALTA.41
1917 23:39:53.494912 # ok 140 event_spurious.LCALTA.41
1918 23:39:53.499977 # ok 141 get_value.LCALTA.40
1919 23:39:53.500503 # # LCALTA.40 FRDDR_C SRC 2 EN Switch
1920 23:39:53.505522 # ok 142 name.LCALTA.40
1921 23:39:53.506011 # ok 143 write_default.LCALTA.40
1922 23:39:53.511053 # ok 144 write_valid.LCALTA.40
1923 23:39:53.511551 # ok 145 write_invalid.LCALTA.40
1924 23:39:53.516643 # ok 146 event_missing.LCALTA.40
1925 23:39:53.517139 # ok 147 event_spurious.LCALTA.40
1926 23:39:53.522155 # ok 148 get_value.LCALTA.39
1927 23:39:53.527688 # # LCALTA.39 FRDDR_C SRC 1 EN Switch
1928 23:39:53.528223 # ok 149 name.LCALTA.39
1929 23:39:53.528662 # ok 150 write_default.LCALTA.39
1930 23:39:53.533260 # ok 151 write_valid.LCALTA.39
1931 23:39:53.533756 # ok 152 write_invalid.LCALTA.39
1932 23:39:53.538782 # ok 153 event_missing.LCALTA.39
1933 23:39:53.544337 # ok 154 event_spurious.LCALTA.39
1934 23:39:53.544831 # ok 155 get_value.LCALTA.38
1935 23:39:53.549873 # # LCALTA.38 FRDDR_B SINK 3 SEL
1936 23:39:53.550369 # ok 156 name.LCALTA.38
1937 23:39:53.550806 # ok 157 write_default.LCALTA.38
1938 23:39:53.555402 # ok 158 write_valid.LCALTA.38
1939 23:39:53.555900 # ok 159 write_invalid.LCALTA.38
1940 23:39:53.560983 # ok 160 event_missing.LCALTA.38
1941 23:39:53.566499 # ok 161 event_spurious.LCALTA.38
1942 23:39:53.566990 # ok 162 get_value.LCALTA.37
1943 23:39:53.572086 # # LCALTA.37 FRDDR_B SINK 2 SEL
1944 23:39:53.572585 # ok 163 name.LCALTA.37
1945 23:39:53.573022 # ok 164 write_default.LCALTA.37
1946 23:39:53.577622 # ok 165 write_valid.LCALTA.37
1947 23:39:53.583148 # ok 166 write_invalid.LCALTA.37
1948 23:39:53.583647 # ok 167 event_missing.LCALTA.37
1949 23:39:53.588692 # ok 168 event_spurious.LCALTA.37
1950 23:39:53.589190 # ok 169 get_value.LCALTA.36
1951 23:39:53.594239 # # LCALTA.36 FRDDR_B SINK 1 SEL
1952 23:39:53.594741 # ok 170 name.LCALTA.36
1953 23:39:53.599802 # ok 171 write_default.LCALTA.36
1954 23:39:53.600342 # ok 172 write_valid.LCALTA.36
1955 23:39:53.605352 # ok 173 write_invalid.LCALTA.36
1956 23:39:53.605851 # ok 174 event_missing.LCALTA.36
1957 23:39:53.610915 # ok 175 event_spurious.LCALTA.36
1958 23:39:53.611418 # ok 176 get_value.LCALTA.35
1959 23:39:53.616451 # # LCALTA.35 FRDDR_B SRC 3 EN Switch
1960 23:39:53.616945 # ok 177 name.LCALTA.35
1961 23:39:53.622013 # ok 178 write_default.LCALTA.35
1962 23:39:53.622507 # ok 179 write_valid.LCALTA.35
1963 23:39:53.627554 # ok 180 write_invalid.LCALTA.35
1964 23:39:53.628077 # ok 181 event_missing.LCALTA.35
1965 23:39:53.633089 # ok 182 event_spurious.LCALTA.35
1966 23:39:53.633586 # ok 183 get_value.LCALTA.34
1967 23:39:53.638661 # # LCALTA.34 FRDDR_B SRC 2 EN Switch
1968 23:39:53.639161 # ok 184 name.LCALTA.34
1969 23:39:53.644227 # ok 185 write_default.LCALTA.34
1970 23:39:53.644734 # ok 186 write_valid.LCALTA.34
1971 23:39:53.649721 # ok 187 write_invalid.LCALTA.34
1972 23:39:53.650222 # ok 188 event_missing.LCALTA.34
1973 23:39:53.655291 # ok 189 event_spurious.LCALTA.34
1974 23:39:53.655800 # ok 190 get_value.LCALTA.33
1975 23:39:53.660838 # # LCALTA.33 FRDDR_B SRC 1 EN Switch
1976 23:39:53.661347 # ok 191 name.LCALTA.33
1977 23:39:53.666398 # ok 192 write_default.LCALTA.33
1978 23:39:53.666903 # ok 193 write_valid.LCALTA.33
1979 23:39:53.671928 # ok 194 write_invalid.LCALTA.33
1980 23:39:53.672466 # ok 195 event_missing.LCALTA.33
1981 23:39:53.677468 # ok 196 event_spurious.LCALTA.33
1982 23:39:53.677978 # ok 197 get_value.LCALTA.32
1983 23:39:53.683044 # # LCALTA.32 FRDDR_A SINK 3 SEL
1984 23:39:53.683557 # ok 198 name.LCALTA.32
1985 23:39:53.688576 # ok 199 write_default.LCALTA.32
1986 23:39:53.689086 # ok 200 write_valid.LCALTA.32
1987 23:39:53.694123 # ok 201 write_invalid.LCALTA.32
1988 23:39:53.694629 # ok 202 event_missing.LCALTA.32
1989 23:39:53.699678 # ok 203 event_spurious.LCALTA.32
1990 23:39:53.700220 # ok 204 get_value.LCALTA.31
1991 23:39:53.705191 # # LCALTA.31 FRDDR_A SINK 2 SEL
1992 23:39:53.705692 # ok 205 name.LCALTA.31
1993 23:39:53.710757 # ok 206 write_default.LCALTA.31
1994 23:39:53.711265 # ok 207 write_valid.LCALTA.31
1995 23:39:53.716310 # ok 208 write_invalid.LCALTA.31
1996 23:39:53.716830 # ok 209 event_missing.LCALTA.31
1997 23:39:53.721848 # ok 210 event_spurious.LCALTA.31
1998 23:39:53.722361 # ok 211 get_value.LCALTA.30
1999 23:39:53.727412 # # LCALTA.30 FRDDR_A SINK 1 SEL
2000 23:39:53.727926 # ok 212 name.LCALTA.30
2001 23:39:53.732966 # ok 213 write_default.LCALTA.30
2002 23:39:53.733496 # ok 214 write_valid.LCALTA.30
2003 23:39:53.738510 # ok 215 write_invalid.LCALTA.30
2004 23:39:53.744094 # ok 216 event_missing.LCALTA.30
2005 23:39:53.744623 # ok 217 event_spurious.LCALTA.30
2006 23:39:53.749615 # ok 218 get_value.LCALTA.29
2007 23:39:53.750134 # # LCALTA.29 FRDDR_A SRC 3 EN Switch
2008 23:39:53.755165 # ok 219 name.LCALTA.29
2009 23:39:53.755682 # ok 220 write_default.LCALTA.29
2010 23:39:53.760684 # ok 221 write_valid.LCALTA.29
2011 23:39:53.761204 # ok 222 write_invalid.LCALTA.29
2012 23:39:53.766256 # ok 223 event_missing.LCALTA.29
2013 23:39:53.766778 # ok 224 event_spurious.LCALTA.29
2014 23:39:53.771785 # ok 225 get_value.LCALTA.28
2015 23:39:53.772329 # # LCALTA.28 FRDDR_A SRC 2 EN Switch
2016 23:39:53.777337 # ok 226 name.LCALTA.28
2017 23:39:53.777859 # ok 227 write_default.LCALTA.28
2018 23:39:53.782878 # ok 228 write_valid.LCALTA.28
2019 23:39:53.783396 # ok 229 write_invalid.LCALTA.28
2020 23:39:53.788406 # ok 230 event_missing.LCALTA.28
2021 23:39:53.788923 # ok 231 event_spurious.LCALTA.28
2022 23:39:53.793969 # ok 232 get_value.LCALTA.27
2023 23:39:53.794491 # # LCALTA.27 FRDDR_A SRC 1 EN Switch
2024 23:39:53.799524 # ok 233 name.LCALTA.27
2025 23:39:53.800081 # ok 234 write_default.LCALTA.27
2026 23:39:53.805064 # ok 235 write_valid.LCALTA.27
2027 23:39:53.805576 # ok 236 write_invalid.LCALTA.27
2028 23:39:53.810605 # ok 237 event_missing.LCALTA.27
2029 23:39:53.811110 # ok 238 event_spurious.LCALTA.27
2030 23:39:53.816181 # ok 239 get_value.LCALTA.26
2031 23:39:53.816693 # # LCALTA.26 ELD
2032 23:39:53.821721 # ok 240 name.LCALTA.26
2033 23:39:53.822238 # # ELD is not writeable
2034 23:39:53.827224 # ok 241 # SKIP write_default.LCALTA.26
2035 23:39:53.827728 # # ELD is not writeable
2036 23:39:53.832777 # ok 242 # SKIP write_valid.LCALTA.26
2037 23:39:53.833284 # # ELD is not writeable
2038 23:39:53.838344 # ok 243 # SKIP write_invalid.LCALTA.26
2039 23:39:53.838851 # ok 244 event_missing.LCALTA.26
2040 23:39:53.843884 # ok 245 event_spurious.LCALTA.26
2041 23:39:53.844429 # ok 246 get_value.LCALTA.25
2042 23:39:53.849460 # # LCALTA.25 IEC958 Playback Default
2043 23:39:53.849986 # ok 247 name.LCALTA.25
2044 23:39:53.855015 # ok 248 write_default.LCALTA.25
2045 23:39:53.855555 # ok 249 # SKIP write_valid.LCALTA.25
2046 23:39:53.860569 # ok 250 # SKIP write_invalid.LCALTA.25
2047 23:39:53.866118 # ok 251 event_missing.LCALTA.25
2048 23:39:53.866658 # ok 252 event_spurious.LCALTA.25
2049 23:39:53.871650 # ok 253 get_value.LCALTA.24
2050 23:39:53.872228 # # LCALTA.24 IEC958 Playback Mask
2051 23:39:53.872685 # ok 254 name.LCALTA.24
2052 23:39:53.877175 # # IEC958 Playback Mask is not writeable
2053 23:39:53.882739 # ok 255 # SKIP write_default.LCALTA.24
2054 23:39:53.883283 # # IEC958 Playback Mask is not writeable
2055 23:39:53.888291 # ok 256 # SKIP write_valid.LCALTA.24
2056 23:39:53.893822 # # IEC958 Playback Mask is not writeable
2057 23:39:53.894362 # ok 257 # SKIP write_invalid.LCALTA.24
2058 23:39:53.899373 # ok 258 event_missing.LCALTA.24
2059 23:39:53.899917 # ok 259 event_spurious.LCALTA.24
2060 23:39:53.904916 # ok 260 get_value.LCALTA.23
2061 23:39:53.905445 # # LCALTA.23 Playback Channel Map
2062 23:39:53.910493 # ok 261 name.LCALTA.23
2063 23:39:53.916043 # # Playback Channel Map is not writeable
2064 23:39:53.916586 # ok 262 # SKIP write_default.LCALTA.23
2065 23:39:53.921567 # # Playback Channel Map is not writeable
2066 23:39:53.922108 # ok 263 # SKIP write_valid.LCALTA.23
2067 23:39:53.927112 # # Playback Channel Map is not writeable
2068 23:39:53.932636 # ok 264 # SKIP write_invalid.LCALTA.23
2069 23:39:53.933183 # ok 265 event_missing.LCALTA.23
2070 23:39:53.938195 # ok 266 event_spurious.LCALTA.23
2071 23:39:53.938743 # ok 267 get_value.LCALTA.22
2072 23:39:53.943745 # # LCALTA.22 TDMOUT_A Gain Enable Switch
2073 23:39:53.944348 # ok 268 name.LCALTA.22
2074 23:39:53.949315 # ok 269 write_default.LCALTA.22
2075 23:39:53.949857 # ok 270 write_valid.LCALTA.22
2076 23:39:53.954848 # ok 271 write_invalid.LCALTA.22
2077 23:39:53.955377 # ok 272 event_missing.LCALTA.22
2078 23:39:53.960389 # ok 273 event_spurious.LCALTA.22
2079 23:39:53.965906 # ok 274 get_value.LCALTA.21
2080 23:39:53.966439 # # LCALTA.21 TDMOUT_A Lane 3 Volume
2081 23:39:53.966889 # ok 275 name.LCALTA.21
2082 23:39:53.971489 # ok 276 write_default.LCALTA.21
2083 23:39:53.977024 # ok 277 write_valid.LCALTA.21
2084 23:39:53.977548 # ok 278 write_invalid.LCALTA.21
2085 23:39:53.982549 # ok 279 event_missing.LCALTA.21
2086 23:39:53.983061 # ok 280 event_spurious.LCALTA.21
2087 23:39:53.988107 # ok 281 get_value.LCALTA.20
2088 23:39:53.988610 # # LCALTA.20 TDMOUT_A Lane 2 Volume
2089 23:39:53.993652 # ok 282 name.LCALTA.20
2090 23:39:53.994164 # ok 283 write_default.LCALTA.20
2091 23:39:53.999195 # ok 284 write_valid.LCALTA.20
2092 23:39:53.999705 # ok 285 write_invalid.LCALTA.20
2093 23:39:54.004715 # ok 286 event_missing.LCALTA.20
2094 23:39:54.005226 # ok 287 event_spurious.LCALTA.20
2095 23:39:54.010284 # ok 288 get_value.LCALTA.19
2096 23:39:54.010793 # # LCALTA.19 TDMOUT_A Lane 1 Volume
2097 23:39:54.015841 # ok 289 name.LCALTA.19
2098 23:39:54.016382 # ok 290 write_default.LCALTA.19
2099 23:39:54.021378 # ok 291 write_valid.LCALTA.19
2100 23:39:54.021891 # ok 292 write_invalid.LCALTA.19
2101 23:39:54.026919 # ok 293 event_missing.LCALTA.19
2102 23:39:54.027423 # ok 294 event_spurious.LCALTA.19
2103 23:39:54.032464 # ok 295 get_value.LCALTA.18
2104 23:39:54.032975 # # LCALTA.18 TDMOUT_A Lane 0 Volume
2105 23:39:54.038002 # ok 296 name.LCALTA.18
2106 23:39:54.038514 # ok 297 write_default.LCALTA.18
2107 23:39:54.043566 # ok 298 write_valid.LCALTA.18
2108 23:39:54.044109 # ok 299 write_invalid.LCALTA.18
2109 23:39:54.049126 # ok 300 event_missing.LCALTA.18
2110 23:39:54.049641 # ok 301 event_spurious.LCALTA.18
2111 23:39:54.054663 # ok 302 get_value.LCALTA.17
2112 23:39:54.060241 # # LCALTA.17 TDMOUT_B Gain Enable Switch
2113 23:39:54.060762 # ok 303 name.LCALTA.17
2114 23:39:54.061214 # ok 304 write_default.LCALTA.17
2115 23:39:54.065766 # ok 305 write_valid.LCALTA.17
2116 23:39:54.071294 # ok 306 write_invalid.LCALTA.17
2117 23:39:54.071809 # ok 307 event_missing.LCALTA.17
2118 23:39:54.076868 # ok 308 event_spurious.LCALTA.17
2119 23:39:54.077396 # ok 309 get_value.LCALTA.16
2120 23:39:54.082414 # # LCALTA.16 TDMOUT_B Lane 3 Volume
2121 23:39:54.082948 # ok 310 name.LCALTA.16
2122 23:39:54.087959 # ok 311 write_default.LCALTA.16
2123 23:39:54.088520 # ok 312 write_valid.LCALTA.16
2124 23:39:54.093478 # ok 313 write_invalid.LCALTA.16
2125 23:39:54.094004 # ok 314 event_missing.LCALTA.16
2126 23:39:54.099022 # ok 315 event_spurious.LCALTA.16
2127 23:39:54.099551 # ok 316 get_value.LCALTA.15
2128 23:39:54.104582 # # LCALTA.15 TDMOUT_B Lane 2 Volume
2129 23:39:54.105111 # ok 317 name.LCALTA.15
2130 23:39:54.110155 # ok 318 write_default.LCALTA.15
2131 23:39:54.110681 # ok 319 write_valid.LCALTA.15
2132 23:39:54.115776 # ok 320 write_invalid.LCALTA.15
2133 23:39:54.116337 # ok 321 event_missing.LCALTA.15
2134 23:39:54.121248 # ok 322 event_spurious.LCALTA.15
2135 23:39:54.121775 # ok 323 get_value.LCALTA.14
2136 23:39:54.126814 # # LCALTA.14 TDMOUT_B Lane 1 Volume
2137 23:39:54.127347 # ok 324 name.LCALTA.14
2138 23:39:54.132311 # ok 325 write_default.LCALTA.14
2139 23:39:54.132845 # ok 326 write_valid.LCALTA.14
2140 23:39:54.137891 # ok 327 write_invalid.LCALTA.14
2141 23:39:54.138411 # ok 328 event_missing.LCALTA.14
2142 23:39:54.143384 # ok 329 event_spurious.LCALTA.14
2143 23:39:54.143905 # ok 330 get_value.LCALTA.13
2144 23:39:54.148979 # # LCALTA.13 TDMOUT_B Lane 0 Volume
2145 23:39:54.149508 # ok 331 name.LCALTA.13
2146 23:39:54.154512 # ok 332 write_default.LCALTA.13
2147 23:39:54.155021 # ok 333 write_valid.LCALTA.13
2148 23:39:54.160053 # ok 334 write_invalid.LCALTA.13
2149 23:39:54.160559 # ok 335 event_missing.LCALTA.13
2150 23:39:54.165576 # ok 336 event_spurious.LCALTA.13
2151 23:39:54.166085 # ok 337 get_value.LCALTA.12
2152 23:39:54.171139 # # LCALTA.12 TDMOUT_C Gain Enable Switch
2153 23:39:54.171647 # ok 338 name.LCALTA.12
2154 23:39:54.176758 # ok 339 write_default.LCALTA.12
2155 23:39:54.182202 # ok 340 write_valid.LCALTA.12
2156 23:39:54.182711 # ok 341 write_invalid.LCALTA.12
2157 23:39:54.187790 # ok 342 event_missing.LCALTA.12
2158 23:39:54.188328 # ok 343 event_spurious.LCALTA.12
2159 23:39:54.193323 # ok 344 get_value.LCALTA.11
2160 23:39:54.193829 # # LCALTA.11 TDMOUT_C Lane 3 Volume
2161 23:39:54.198872 # ok 345 name.LCALTA.11
2162 23:39:54.199386 # ok 346 write_default.LCALTA.11
2163 23:39:54.204426 # ok 347 write_valid.LCALTA.11
2164 23:39:54.204947 # ok 348 write_invalid.LCALTA.11
2165 23:39:54.209990 # ok 349 event_missing.LCALTA.11
2166 23:39:54.210507 # ok 350 event_spurious.LCALTA.11
2167 23:39:54.215504 # ok 351 get_value.LCALTA.10
2168 23:39:54.216168 # # LCALTA.10 TDMOUT_C Lane 2 Volume
2169 23:39:54.221074 # ok 352 name.LCALTA.10
2170 23:39:54.221595 # ok 353 write_default.LCALTA.10
2171 23:39:54.226621 # ok 354 write_valid.LCALTA.10
2172 23:39:54.227134 # ok 355 write_invalid.LCALTA.10
2173 23:39:54.232180 # ok 356 event_missing.LCALTA.10
2174 23:39:54.232704 # ok 357 event_spurious.LCALTA.10
2175 23:39:54.237773 # ok 358 get_value.LCALTA.9
2176 23:39:54.238296 # # LCALTA.9 TDMOUT_C Lane 1 Volume
2177 23:39:54.243262 # ok 359 name.LCALTA.9
2178 23:39:54.243779 # ok 360 write_default.LCALTA.9
2179 23:39:54.248820 # ok 361 write_valid.LCALTA.9
2180 23:39:54.249334 # ok 362 write_invalid.LCALTA.9
2181 23:39:54.254338 # ok 363 event_missing.LCALTA.9
2182 23:39:54.254850 # ok 364 event_spurious.LCALTA.9
2183 23:39:54.259872 # ok 365 get_value.LCALTA.8
2184 23:39:54.260414 # # LCALTA.8 TDMOUT_C Lane 0 Volume
2185 23:39:54.265434 # ok 366 name.LCALTA.8
2186 23:39:54.265941 # ok 367 write_default.LCALTA.8
2187 23:39:54.270969 # ok 368 write_valid.LCALTA.8
2188 23:39:54.271478 # ok 369 write_invalid.LCALTA.8
2189 23:39:54.276521 # ok 370 event_missing.LCALTA.8
2190 23:39:54.277033 # ok 371 event_spurious.LCALTA.8
2191 23:39:54.282065 # ok 372 get_value.LCALTA.7
2192 23:39:54.282569 # # LCALTA.7 ACODEC Unmute Ramp Switch
2193 23:39:54.287615 # ok 373 name.LCALTA.7
2194 23:39:54.288159 # ok 374 write_default.LCALTA.7
2195 23:39:54.293154 # ok 375 write_valid.LCALTA.7
2196 23:39:54.293662 # ok 376 write_invalid.LCALTA.7
2197 23:39:54.298772 # ok 377 event_missing.LCALTA.7
2198 23:39:54.299279 # ok 378 event_spurious.LCALTA.7
2199 23:39:54.304263 # ok 379 get_value.LCALTA.6
2200 23:39:54.304774 # # LCALTA.6 ACODEC Mute Ramp Switch
2201 23:39:54.309820 # ok 380 name.LCALTA.6
2202 23:39:54.310330 # ok 381 write_default.LCALTA.6
2203 23:39:54.315350 # ok 382 write_valid.LCALTA.6
2204 23:39:54.315859 # ok 383 write_invalid.LCALTA.6
2205 23:39:54.320901 # ok 384 event_missing.LCALTA.6
2206 23:39:54.321415 # ok 385 event_spurious.LCALTA.6
2207 23:39:54.326441 # ok 386 get_value.LCALTA.5
2208 23:39:54.326948 # # LCALTA.5 ACODEC Volume Ramp Switch
2209 23:39:54.331971 # ok 387 name.LCALTA.5
2210 23:39:54.332515 # ok 388 write_default.LCALTA.5
2211 23:39:54.337531 # ok 389 write_valid.LCALTA.5
2212 23:39:54.338042 # ok 390 write_invalid.LCALTA.5
2213 23:39:54.343075 # ok 391 event_missing.LCALTA.5
2214 23:39:54.343583 # ok 392 event_spurious.LCALTA.5
2215 23:39:54.348642 # ok 393 get_value.LCALTA.4
2216 23:39:54.349149 # # LCALTA.4 ACODEC Ramp Rate
2217 23:39:54.354166 # ok 394 name.LCALTA.4
2218 23:39:54.354677 # ok 395 write_default.LCALTA.4
2219 23:39:54.359798 # ok 396 write_valid.LCALTA.4
2220 23:39:54.360350 # ok 397 write_invalid.LCALTA.4
2221 23:39:54.365295 # ok 398 event_missing.LCALTA.4
2222 23:39:54.365818 # ok 399 event_spurious.LCALTA.4
2223 23:39:54.370890 # ok 400 get_value.LCALTA.3
2224 23:39:54.371482 # # LCALTA.3 ACODEC Playback Volume
2225 23:39:54.376387 # ok 401 name.LCALTA.3
2226 23:39:54.376940 # ok 402 write_default.LCALTA.3
2227 23:39:54.381922 # ok 403 write_valid.LCALTA.3
2228 23:39:54.382457 # ok 404 write_invalid.LCALTA.3
2229 23:39:54.387472 # ok 405 event_missing.LCALTA.3
2230 23:39:54.388039 # ok 406 event_spurious.LCALTA.3
2231 23:39:54.393026 # ok 407 get_value.LCALTA.2
2232 23:39:54.393563 # # LCALTA.2 ACODEC Playback Switch
2233 23:39:54.398571 # ok 408 name.LCALTA.2
2234 23:39:54.399097 # ok 409 write_default.LCALTA.2
2235 23:39:54.404147 # ok 410 write_valid.LCALTA.2
2236 23:39:54.404689 # ok 411 write_invalid.LCALTA.2
2237 23:39:54.409678 # ok 412 event_missing.LCALTA.2
2238 23:39:54.410210 # ok 413 event_spurious.LCALTA.2
2239 23:39:54.415208 # ok 414 get_value.LCALTA.1
2240 23:39:54.415742 # # LCALTA.1 ACODEC Playback Channel Mode
2241 23:39:54.420799 # ok 415 name.LCALTA.1
2242 23:39:54.421316 # ok 416 write_default.LCALTA.1
2243 23:39:54.426289 # ok 417 write_valid.LCALTA.1
2244 23:39:54.426800 # ok 418 write_invalid.LCALTA.1
2245 23:39:54.431837 # ok 419 event_missing.LCALTA.1
2246 23:39:54.432392 # ok 420 event_spurious.LCALTA.1
2247 23:39:54.437391 # ok 421 get_value.LCALTA.0
2248 23:39:54.437917 # # LCALTA.0 TOACODEC Lane Select
2249 23:39:54.442935 # ok 422 name.LCALTA.0
2250 23:39:54.443456 # ok 423 write_default.LCALTA.0
2251 23:39:54.448476 # ok 424 write_valid.LCALTA.0
2252 23:39:54.448996 # ok 425 write_invalid.LCALTA.0
2253 23:39:54.454041 # ok 426 event_missing.LCALTA.0
2254 23:39:54.454569 # ok 427 event_spurious.LCALTA.0
2255 23:39:54.459558 # # Totals: pass:416 fail:0 xfail:0 xpass:0 skip:11 error:0
2256 23:39:54.465123 ok 1 selftests: alsa: mixer-test
2257 23:39:54.465642 # timeout set to 45
2258 23:39:54.466094 # selftests: alsa: pcm-test
2259 23:39:54.470691 # TAP version 13
2260 23:39:54.471205 # # Card 0/LCALTA - LC-ALTA (LC-ALTA)
2261 23:39:54.476483 # # LCALTA.0 - fe.dai-link-0 (*)
2262 23:39:54.477189 # # LCALTA.0 - fe.dai-link-1 (*)
2263 23:39:54.481875 # # LCALTA.0 - fe.dai-link-2 (*)
2264 23:39:54.482417 # # LCALTA.0 - fe.dai-link-3 (*)
2265 23:39:54.487328 # # LCALTA.0 - fe.dai-link-4 (*)
2266 23:39:54.487854 # # LCALTA.0 - fe.dai-link-5 (*)
2267 23:39:54.492902 # 1..42
2268 23:39:54.498400 # # default.time1.LCALTA.5.0.CAPTURE - 8kHz mono large periods
2269 23:39:54.499066 # ok 1 # SKIP default.time1.LCALTA.5.0.CAPTURE
2270 23:39:54.503959 # # snd_pcm_hw_params: Invalid argument
2271 23:39:54.509497 # # default.time2.LCALTA.5.0.CAPTURE - 8kHz stereo large periods
2272 23:39:54.515055 # ok 2 # SKIP default.time2.LCALTA.5.0.CAPTURE
2273 23:39:54.515698 # # snd_pcm_hw_params: Invalid argument
2274 23:39:54.520584 # # default.time3.LCALTA.5.0.CAPTURE - 44.1kHz stereo large periods
2275 23:39:54.526147 # ok 3 # SKIP default.time3.LCALTA.5.0.CAPTURE
2276 23:39:54.531707 # # snd_pcm_hw_params: Invalid argument
2277 23:39:54.537231 # # default.time4.LCALTA.5.0.CAPTURE - 48kHz stereo small periods
2278 23:39:54.542815 # ok 4 # SKIP default.time4.LCALTA.5.0.CAPTURE
2279 23:39:54.543487 # # snd_pcm_hw_params: Invalid argument
2280 23:39:54.548355 # # default.time5.LCALTA.5.0.CAPTURE - 48kHz stereo large periods
2281 23:39:54.553868 # ok 5 # SKIP default.time5.LCALTA.5.0.CAPTURE
2282 23:39:54.559423 # # snd_pcm_hw_params: Invalid argument
2283 23:39:54.564945 # # default.time6.LCALTA.5.0.CAPTURE - 48kHz 6 channel large periods
2284 23:39:54.570481 # ok 6 # SKIP default.time6.LCALTA.5.0.CAPTURE
2285 23:39:54.571136 # # snd_pcm_hw_params: Invalid argument
2286 23:39:54.576093 # # default.time7.LCALTA.5.0.CAPTURE - 96kHz stereo large periods
2287 23:39:54.581635 # ok 7 # SKIP default.time7.LCALTA.5.0.CAPTURE
2288 23:39:54.587168 # # snd_pcm_hw_params: Invalid argument
2289 23:39:54.592711 # # default.time1.LCALTA.4.0.CAPTURE - 8kHz mono large periods
2290 23:39:54.593384 # ok 8 # SKIP default.time1.LCALTA.4.0.CAPTURE
2291 23:39:54.598264 # # snd_pcm_hw_params: Invalid argument
2292 23:39:54.603820 # # default.time2.LCALTA.4.0.CAPTURE - 8kHz stereo large periods
2293 23:39:54.609348 # ok 9 # SKIP default.time2.LCALTA.4.0.CAPTURE
2294 23:39:54.610021 # # snd_pcm_hw_params: Invalid argument
2295 23:39:54.620401 # # default.time3.LCALTA.4.0.CAPTURE - 44.1kHz stereo large periods
2296 23:39:54.621119 # ok 10 # SKIP default.time3.LCALTA.4.0.CAPTURE
2297 23:39:54.626022 # # snd_pcm_hw_params: Invalid argument
2298 23:39:54.631548 # # default.time4.LCALTA.4.0.CAPTURE - 48kHz stereo small periods
2299 23:39:54.637111 # ok 11 # SKIP default.time4.LCALTA.4.0.CAPTURE
2300 23:39:54.637792 # # snd_pcm_hw_params: Invalid argument
2301 23:39:54.642648 # # default.time5.LCALTA.4.0.CAPTURE - 48kHz stereo large periods
2302 23:39:54.648271 # ok 12 # SKIP default.time5.LCALTA.4.0.CAPTURE
2303 23:39:54.653747 # # snd_pcm_hw_params: Invalid argument
2304 23:39:54.659301 # # default.time6.LCALTA.4.0.CAPTURE - 48kHz 6 channel large periods
2305 23:39:54.664866 # ok 13 # SKIP default.time6.LCALTA.4.0.CAPTURE
2306 23:39:54.665537 # # snd_pcm_hw_params: Invalid argument
2307 23:39:54.670377 # # default.time7.LCALTA.4.0.CAPTURE - 96kHz stereo large periods
2308 23:39:54.675913 # ok 14 # SKIP default.time7.LCALTA.4.0.CAPTURE
2309 23:39:54.681481 # # snd_pcm_hw_params: Invalid argument
2310 23:39:54.687010 # # default.time1.LCALTA.3.0.CAPTURE - 8kHz mono large periods
2311 23:39:54.692546 # ok 15 # SKIP default.time1.LCALTA.3.0.CAPTURE
2312 23:39:54.693216 # # snd_pcm_hw_params: Invalid argument
2313 23:39:54.698117 # # default.time2.LCALTA.3.0.CAPTURE - 8kHz stereo large periods
2314 23:39:54.703636 # ok 16 # SKIP default.time2.LCALTA.3.0.CAPTURE
2315 23:39:54.709193 # # snd_pcm_hw_params: Invalid argument
2316 23:39:54.714728 # # default.time3.LCALTA.3.0.CAPTURE - 44.1kHz stereo large periods
2317 23:39:54.715368 # ok 17 # SKIP default.time3.LCALTA.3.0.CAPTURE
2318 23:39:54.720323 # # snd_pcm_hw_params: Invalid argument
2319 23:39:54.725849 # # default.time4.LCALTA.3.0.CAPTURE - 48kHz stereo small periods
2320 23:39:54.731384 # ok 18 # SKIP default.time4.LCALTA.3.0.CAPTURE
2321 23:39:54.736907 # # snd_pcm_hw_params: Invalid argument
2322 23:39:54.742466 # # default.time5.LCALTA.3.0.CAPTURE - 48kHz stereo large periods
2323 23:39:54.743105 # ok 19 # SKIP default.time5.LCALTA.3.0.CAPTURE
2324 23:39:54.748031 # # snd_pcm_hw_params: Invalid argument
2325 23:39:54.753572 # # default.time6.LCALTA.3.0.CAPTURE - 48kHz 6 channel large periods
2326 23:39:54.759095 # ok 20 # SKIP default.time6.LCALTA.3.0.CAPTURE
2327 23:39:54.764609 # # snd_pcm_hw_params: Invalid argument
2328 23:39:54.770180 # # default.time7.LCALTA.3.0.CAPTURE - 96kHz stereo large periods
2329 23:39:54.770823 # ok 21 # SKIP default.time7.LCALTA.3.0.CAPTURE
2330 23:39:54.775743 # # snd_pcm_hw_params: Invalid argument
2331 23:39:54.781286 # # default.time1.LCALTA.2.0.PLAYBACK - 8kHz mono large periods
2332 23:39:54.786865 # ok 22 # SKIP default.time1.LCALTA.2.0.PLAYBACK
2333 23:39:54.787515 # # snd_pcm_hw_params: Invalid argument
2334 23:39:54.792371 # # default.time2.LCALTA.2.0.PLAYBACK - 8kHz stereo large periods
2335 23:39:54.797904 # ok 23 # SKIP default.time2.LCALTA.2.0.PLAYBACK
2336 23:39:54.803478 # # snd_pcm_hw_params: Invalid argument
2337 23:39:54.809014 # # default.time3.LCALTA.2.0.PLAYBACK - 44.1kHz stereo large periods
2338 23:39:54.814572 # ok 24 # SKIP default.time3.LCALTA.2.0.PLAYBACK
2339 23:39:54.815212 # # snd_pcm_hw_params: Invalid argument
2340 23:39:54.820147 # # default.time4.LCALTA.2.0.PLAYBACK - 48kHz stereo small periods
2341 23:39:54.825671 # ok 25 # SKIP default.time4.LCALTA.2.0.PLAYBACK
2342 23:39:54.831227 # # snd_pcm_hw_params: Invalid argument
2343 23:39:54.836779 # # default.time5.LCALTA.2.0.PLAYBACK - 48kHz stereo large periods
2344 23:39:54.842317 # ok 26 # SKIP default.time5.LCALTA.2.0.PLAYBACK
2345 23:39:54.842983 # # snd_pcm_hw_params: Invalid argument
2346 23:39:54.847886 # # default.time6.LCALTA.2.0.PLAYBACK - 48kHz 6 channel large periods
2347 23:39:54.853409 # ok 27 # SKIP default.time6.LCALTA.2.0.PLAYBACK
2348 23:39:54.858961 # # snd_pcm_hw_params: Invalid argument
2349 23:39:54.864493 # # default.time7.LCALTA.2.0.PLAYBACK - 96kHz stereo large periods
2350 23:39:54.870033 # ok 28 # SKIP default.time7.LCALTA.2.0.PLAYBACK
2351 23:39:54.870685 # # snd_pcm_hw_params: Invalid argument
2352 23:39:54.875575 # # default.time1.LCALTA.1.0.PLAYBACK - 8kHz mono large periods
2353 23:39:54.881135 # ok 29 # SKIP default.time1.LCALTA.1.0.PLAYBACK
2354 23:39:54.886665 # # snd_pcm_hw_params: Invalid argument
2355 23:39:54.892294 # # default.time2.LCALTA.1.0.PLAYBACK - 8kHz stereo large periods
2356 23:39:54.897760 # ok 30 # SKIP default.time2.LCALTA.1.0.PLAYBACK
2357 23:39:54.898412 # # snd_pcm_hw_params: Invalid argument
2358 23:39:54.903315 # # default.time3.LCALTA.1.0.PLAYBACK - 44.1kHz stereo large periods
2359 23:39:54.908866 # ok 31 # SKIP default.time3.LCALTA.1.0.PLAYBACK
2360 23:39:54.914406 # # snd_pcm_hw_params: Invalid argument
2361 23:39:54.919947 # # default.time4.LCALTA.1.0.PLAYBACK - 48kHz stereo small periods
2362 23:39:54.925531 # ok 32 # SKIP default.time4.LCALTA.1.0.PLAYBACK
2363 23:39:54.926207 # # snd_pcm_hw_params: Invalid argument
2364 23:39:54.931057 # # default.time5.LCALTA.1.0.PLAYBACK - 48kHz stereo large periods
2365 23:39:54.936605 # ok 33 # SKIP default.time5.LCALTA.1.0.PLAYBACK
2366 23:39:54.942130 # # snd_pcm_hw_params: Invalid argument
2367 23:39:54.947706 # # default.time6.LCALTA.1.0.PLAYBACK - 48kHz 6 channel large periods
2368 23:39:54.953257 # ok 34 # SKIP default.time6.LCALTA.1.0.PLAYBACK
2369 23:39:54.953923 # # snd_pcm_hw_params: Invalid argument
2370 23:39:54.958786 # # default.time7.LCALTA.1.0.PLAYBACK - 96kHz stereo large periods
2371 23:39:54.964354 # ok 35 # SKIP default.time7.LCALTA.1.0.PLAYBACK
2372 23:39:54.969884 # # snd_pcm_hw_params: Invalid argument
2373 23:39:54.975419 # # default.time1.LCALTA.0.0.PLAYBACK - 8kHz mono large periods
2374 23:39:54.980962 # ok 36 # SKIP default.time1.LCALTA.0.0.PLAYBACK
2375 23:39:54.981602 # # snd_pcm_hw_params: Invalid argument
2376 23:39:54.986522 # # default.time2.LCALTA.0.0.PLAYBACK - 8kHz stereo large periods
2377 23:39:54.992091 # ok 37 # SKIP default.time2.LCALTA.0.0.PLAYBACK
2378 23:39:54.997614 # # snd_pcm_hw_params: Invalid argument
2379 23:39:55.003148 # # default.time3.LCALTA.0.0.PLAYBACK - 44.1kHz stereo large periods
2380 23:39:55.008766 # ok 38 # SKIP default.time3.LCALTA.0.0.PLAYBACK
2381 23:39:55.009472 # # snd_pcm_hw_params: Invalid argument
2382 23:39:55.014258 # # default.time4.LCALTA.0.0.PLAYBACK - 48kHz stereo small periods
2383 23:39:55.019796 # ok 39 # SKIP default.time4.LCALTA.0.0.PLAYBACK
2384 23:39:55.025333 # # snd_pcm_hw_params: Invalid argument
2385 23:39:55.030901 # # default.time5.LCALTA.0.0.PLAYBACK - 48kHz stereo large periods
2386 23:39:55.036428 # ok 40 # SKIP default.time5.LCALTA.0.0.PLAYBACK
2387 23:39:55.037091 # # snd_pcm_hw_params: Invalid argument
2388 23:39:55.041980 # # default.time6.LCALTA.0.0.PLAYBACK - 48kHz 6 channel large periods
2389 23:39:55.047526 # ok 41 # SKIP default.time6.LCALTA.0.0.PLAYBACK
2390 23:39:55.053061 # # snd_pcm_hw_params: Invalid argument
2391 23:39:55.058587 # # default.time7.LCALTA.0.0.PLAYBACK - 96kHz stereo large periods
2392 23:39:55.064189 # ok 42 # SKIP default.time7.LCALTA.0.0.PLAYBACK
2393 23:39:55.064817 # # snd_pcm_hw_params: Invalid argument
2394 23:39:55.069695 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:42 error:0
2395 23:39:55.075301 ok 2 selftests: alsa: pcm-test
2396 23:39:55.075931 # timeout set to 45
2397 23:39:55.080821 # selftests: alsa: test-pcmtest-driver
2398 23:39:55.081453 # TAP version 13
2399 23:39:55.081988 # 1..5
2400 23:39:55.086360 # # Starting 5 tests from 1 test cases.
2401 23:39:55.087012 # # RUN pcmtest.playback ...
2402 23:39:55.091857 # # SKIP Can't read patterns. Probably, module isn't loaded
2403 23:39:55.097451 # # OK pcmtest.playback
2404 23:39:55.103012 # ok 1 pcmtest.playback # SKIP Can't read patterns. Probably, module isn't loaded
2405 23:39:55.108525 # # RUN pcmtest.capture ...
2406 23:39:55.114070 # # SKIP Can't read patterns. Probably, module isn't loaded
2407 23:39:55.119638 # # OK pcmtest.capture
2408 23:39:55.125165 # ok 2 pcmtest.capture # SKIP Can't read patterns. Probably, module isn't loaded
2409 23:39:55.130716 # # RUN pcmtest.ni_capture ...
2410 23:39:55.136321 # # SKIP Can't read patterns. Probably, module isn't loaded
2411 23:39:55.136985 # # OK pcmtest.ni_capture
2412 23:39:55.147315 # ok 3 pcmtest.ni_capture # SKIP Can't read patterns. Probably, module isn't loaded
2413 23:39:55.148051 # # RUN pcmtest.ni_playback ...
2414 23:39:55.152924 # # SKIP Can't read patterns. Probably, module isn't loaded
2415 23:39:55.158479 # # OK pcmtest.ni_playback
2416 23:39:55.164052 # ok 4 pcmtest.ni_playback # SKIP Can't read patterns. Probably, module isn't loaded
2417 23:39:55.169562 # # RUN pcmtest.reset_ioctl ...
2418 23:39:55.175117 # # SKIP Can't read patterns. Probably, module isn't loaded
2419 23:39:55.180643 # # OK pcmtest.reset_ioctl
2420 23:39:55.186201 # ok 5 pcmtest.reset_ioctl # SKIP Can't read patterns. Probably, module isn't loaded
2421 23:39:55.191731 # # PASSED: 5 / 5 tests passed.
2422 23:39:55.197302 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:5 error:0
2423 23:39:55.197951 ok 3 selftests: alsa: test-pcmtest-driver
2424 23:39:55.202840 # timeout set to 45
2425 23:39:55.203491 # selftests: alsa: utimer-test
2426 23:39:55.204070 # TAP version 13
2427 23:39:55.204616 # 1..2
2428 23:39:55.208404 # # Starting 2 tests from 2 test cases.
2429 23:39:55.213974 # # RUN global.wrong_timers_test ...
2430 23:39:55.219476 # # OK global.wrong_timers_test
2431 23:39:55.220155 # ok 1 global.wrong_timers_test
2432 23:39:55.225033 # # RUN timer_f.utimer ...
2433 23:39:55.230564 # # utimer-test.c:55:utimer:Expected ioctl(timer_dev_fd, SNDRV_TIMER_IOCTL_CREATE, self->utimer_info) (-1) == 0 (0)
2434 23:39:55.236128 # # utimer: Test terminated by assertion
2435 23:39:55.241678 # # FAIL timer_f.utimer
2436 23:39:55.242324 # not ok 2 timer_f.utimer
2437 23:39:55.247212 # # FAILED: 1 / 2 tests passed.
2438 23:39:55.254635 # # Totals: pass:1 fail:1 xfail:0 xpass:0 skip:0 error:0
2439 23:39:55.255292 not ok 4 selftests: alsa: utimer-test # exit=1
2440 23:39:55.758113 alsa_mixer-test_get_value_LCALTA_60 pass
2441 23:39:55.763422 alsa_mixer-test_name_LCALTA_60 pass
2442 23:39:55.764077 alsa_mixer-test_write_default_LCALTA_60 pass
2443 23:39:55.768959 alsa_mixer-test_write_valid_LCALTA_60 pass
2444 23:39:55.774508 alsa_mixer-test_write_invalid_LCALTA_60 pass
2445 23:39:55.780074 alsa_mixer-test_event_missing_LCALTA_60 pass
2446 23:39:55.780687 alsa_mixer-test_event_spurious_LCALTA_60 pass
2447 23:39:55.785608 alsa_mixer-test_get_value_LCALTA_59 pass
2448 23:39:55.791135 alsa_mixer-test_name_LCALTA_59 pass
2449 23:39:55.791731 alsa_mixer-test_write_default_LCALTA_59 pass
2450 23:39:55.796684 alsa_mixer-test_write_valid_LCALTA_59 pass
2451 23:39:55.802239 alsa_mixer-test_write_invalid_LCALTA_59 pass
2452 23:39:55.802848 alsa_mixer-test_event_missing_LCALTA_59 pass
2453 23:39:55.807875 alsa_mixer-test_event_spurious_LCALTA_59 pass
2454 23:39:55.813323 alsa_mixer-test_get_value_LCALTA_58 pass
2455 23:39:55.813918 alsa_mixer-test_name_LCALTA_58 pass
2456 23:39:55.818885 alsa_mixer-test_write_default_LCALTA_58 pass
2457 23:39:55.824418 alsa_mixer-test_write_valid_LCALTA_58 pass
2458 23:39:55.825070 alsa_mixer-test_write_invalid_LCALTA_58 pass
2459 23:39:55.829974 alsa_mixer-test_event_missing_LCALTA_58 pass
2460 23:39:55.835511 alsa_mixer-test_event_spurious_LCALTA_58 pass
2461 23:39:55.841073 alsa_mixer-test_get_value_LCALTA_57 pass
2462 23:39:55.841664 alsa_mixer-test_name_LCALTA_57 pass
2463 23:39:55.846799 alsa_mixer-test_write_default_LCALTA_57 pass
2464 23:39:55.852358 alsa_mixer-test_write_valid_LCALTA_57 pass
2465 23:39:55.852985 alsa_mixer-test_write_invalid_LCALTA_57 pass
2466 23:39:55.857861 alsa_mixer-test_event_missing_LCALTA_57 pass
2467 23:39:55.863403 alsa_mixer-test_event_spurious_LCALTA_57 pass
2468 23:39:55.864068 alsa_mixer-test_get_value_LCALTA_56 pass
2469 23:39:55.869039 alsa_mixer-test_name_LCALTA_56 pass
2470 23:39:55.874515 alsa_mixer-test_write_default_LCALTA_56 pass
2471 23:39:55.875130 alsa_mixer-test_write_valid_LCALTA_56 pass
2472 23:39:55.880067 alsa_mixer-test_write_invalid_LCALTA_56 pass
2473 23:39:55.885583 alsa_mixer-test_event_missing_LCALTA_56 pass
2474 23:39:55.891140 alsa_mixer-test_event_spurious_LCALTA_56 pass
2475 23:39:55.891763 alsa_mixer-test_get_value_LCALTA_55 pass
2476 23:39:55.896696 alsa_mixer-test_name_LCALTA_55 pass
2477 23:39:55.902236 alsa_mixer-test_write_default_LCALTA_55 pass
2478 23:39:55.902856 alsa_mixer-test_write_valid_LCALTA_55 pass
2479 23:39:55.907775 alsa_mixer-test_write_invalid_LCALTA_55 pass
2480 23:39:55.913316 alsa_mixer-test_event_missing_LCALTA_55 pass
2481 23:39:55.913928 alsa_mixer-test_event_spurious_LCALTA_55 pass
2482 23:39:55.918889 alsa_mixer-test_get_value_LCALTA_54 pass
2483 23:39:55.924399 alsa_mixer-test_name_LCALTA_54 pass
2484 23:39:55.925026 alsa_mixer-test_write_default_LCALTA_54 pass
2485 23:39:55.930036 alsa_mixer-test_write_valid_LCALTA_54 pass
2486 23:39:55.935501 alsa_mixer-test_write_invalid_LCALTA_54 pass
2487 23:39:55.936154 alsa_mixer-test_event_missing_LCALTA_54 pass
2488 23:39:55.941053 alsa_mixer-test_event_spurious_LCALTA_54 pass
2489 23:39:55.946639 alsa_mixer-test_get_value_LCALTA_53 pass
2490 23:39:55.947282 alsa_mixer-test_name_LCALTA_53 pass
2491 23:39:55.952267 alsa_mixer-test_write_default_LCALTA_53 pass
2492 23:39:55.957682 alsa_mixer-test_write_valid_LCALTA_53 pass
2493 23:39:55.963233 alsa_mixer-test_write_invalid_LCALTA_53 pass
2494 23:39:55.963836 alsa_mixer-test_event_missing_LCALTA_53 pass
2495 23:39:55.968760 alsa_mixer-test_event_spurious_LCALTA_53 pass
2496 23:39:55.974305 alsa_mixer-test_get_value_LCALTA_52 pass
2497 23:39:55.974908 alsa_mixer-test_name_LCALTA_52 pass
2498 23:39:55.979877 alsa_mixer-test_write_default_LCALTA_52 pass
2499 23:39:55.985444 alsa_mixer-test_write_valid_LCALTA_52 pass
2500 23:39:55.986075 alsa_mixer-test_write_invalid_LCALTA_52 pass
2501 23:39:55.991031 alsa_mixer-test_event_missing_LCALTA_52 pass
2502 23:39:55.996499 alsa_mixer-test_event_spurious_LCALTA_52 pass
2503 23:39:55.997124 alsa_mixer-test_get_value_LCALTA_51 pass
2504 23:39:56.002135 alsa_mixer-test_name_LCALTA_51 pass
2505 23:39:56.007616 alsa_mixer-test_write_default_LCALTA_51 pass
2506 23:39:56.008276 alsa_mixer-test_write_valid_LCALTA_51 pass
2507 23:39:56.013171 alsa_mixer-test_write_invalid_LCALTA_51 pass
2508 23:39:56.018700 alsa_mixer-test_event_missing_LCALTA_51 pass
2509 23:39:56.024315 alsa_mixer-test_event_spurious_LCALTA_51 pass
2510 23:39:56.024942 alsa_mixer-test_get_value_LCALTA_50 pass
2511 23:39:56.029800 alsa_mixer-test_name_LCALTA_50 pass
2512 23:39:56.035357 alsa_mixer-test_write_default_LCALTA_50 pass
2513 23:39:56.035973 alsa_mixer-test_write_valid_LCALTA_50 pass
2514 23:39:56.040900 alsa_mixer-test_write_invalid_LCALTA_50 pass
2515 23:39:56.046446 alsa_mixer-test_event_missing_LCALTA_50 pass
2516 23:39:56.047071 alsa_mixer-test_event_spurious_LCALTA_50 pass
2517 23:39:56.052077 alsa_mixer-test_get_value_LCALTA_49 pass
2518 23:39:56.057544 alsa_mixer-test_name_LCALTA_49 pass
2519 23:39:56.058156 alsa_mixer-test_write_default_LCALTA_49 pass
2520 23:39:56.063099 alsa_mixer-test_write_valid_LCALTA_49 pass
2521 23:39:56.068613 alsa_mixer-test_write_invalid_LCALTA_49 pass
2522 23:39:56.074074 alsa_mixer-test_event_missing_LCALTA_49 pass
2523 23:39:56.074663 alsa_mixer-test_event_spurious_LCALTA_49 pass
2524 23:39:56.079611 alsa_mixer-test_get_value_LCALTA_48 pass
2525 23:39:56.080211 alsa_mixer-test_name_LCALTA_48 pass
2526 23:39:56.085163 alsa_mixer-test_write_default_LCALTA_48 pass
2527 23:39:56.090688 alsa_mixer-test_write_valid_LCALTA_48 pass
2528 23:39:56.096249 alsa_mixer-test_write_invalid_LCALTA_48 pass
2529 23:39:56.096834 alsa_mixer-test_event_missing_LCALTA_48 pass
2530 23:39:56.101808 alsa_mixer-test_event_spurious_LCALTA_48 pass
2531 23:39:56.107331 alsa_mixer-test_get_value_LCALTA_47 pass
2532 23:39:56.107915 alsa_mixer-test_name_LCALTA_47 pass
2533 23:39:56.112930 alsa_mixer-test_write_default_LCALTA_47 pass
2534 23:39:56.118455 alsa_mixer-test_write_valid_LCALTA_47 pass
2535 23:39:56.119023 alsa_mixer-test_write_invalid_LCALTA_47 pass
2536 23:39:56.123997 alsa_mixer-test_event_missing_LCALTA_47 pass
2537 23:39:56.129529 alsa_mixer-test_event_spurious_LCALTA_47 pass
2538 23:39:56.135029 alsa_mixer-test_get_value_LCALTA_46 pass
2539 23:39:56.135599 alsa_mixer-test_name_LCALTA_46 pass
2540 23:39:56.140601 alsa_mixer-test_write_default_LCALTA_46 pass
2541 23:39:56.146172 alsa_mixer-test_write_valid_LCALTA_46 pass
2542 23:39:56.146749 alsa_mixer-test_write_invalid_LCALTA_46 pass
2543 23:39:56.151738 alsa_mixer-test_event_missing_LCALTA_46 pass
2544 23:39:56.157299 alsa_mixer-test_event_spurious_LCALTA_46 pass
2545 23:39:56.157887 alsa_mixer-test_get_value_LCALTA_45 pass
2546 23:39:56.162858 alsa_mixer-test_name_LCALTA_45 pass
2547 23:39:56.168373 alsa_mixer-test_write_default_LCALTA_45 pass
2548 23:39:56.168943 alsa_mixer-test_write_valid_LCALTA_45 pass
2549 23:39:56.173947 alsa_mixer-test_write_invalid_LCALTA_45 pass
2550 23:39:56.179428 alsa_mixer-test_event_missing_LCALTA_45 pass
2551 23:39:56.180052 alsa_mixer-test_event_spurious_LCALTA_45 pass
2552 23:39:56.184999 alsa_mixer-test_get_value_LCALTA_44 pass
2553 23:39:56.190561 alsa_mixer-test_name_LCALTA_44 pass
2554 23:39:56.191146 alsa_mixer-test_write_default_LCALTA_44 pass
2555 23:39:56.196162 alsa_mixer-test_write_valid_LCALTA_44 pass
2556 23:39:56.201675 alsa_mixer-test_write_invalid_LCALTA_44 pass
2557 23:39:56.207260 alsa_mixer-test_event_missing_LCALTA_44 pass
2558 23:39:56.207845 alsa_mixer-test_event_spurious_LCALTA_44 pass
2559 23:39:56.212757 alsa_mixer-test_get_value_LCALTA_43 pass
2560 23:39:56.218303 alsa_mixer-test_name_LCALTA_43 pass
2561 23:39:56.218889 alsa_mixer-test_write_default_LCALTA_43 pass
2562 23:39:56.223777 alsa_mixer-test_write_valid_LCALTA_43 pass
2563 23:39:56.229373 alsa_mixer-test_write_invalid_LCALTA_43 pass
2564 23:39:56.229955 alsa_mixer-test_event_missing_LCALTA_43 pass
2565 23:39:56.234935 alsa_mixer-test_event_spurious_LCALTA_43 pass
2566 23:39:56.240523 alsa_mixer-test_get_value_LCALTA_42 pass
2567 23:39:56.241091 alsa_mixer-test_name_LCALTA_42 pass
2568 23:39:56.246027 alsa_mixer-test_write_default_LCALTA_42 pass
2569 23:39:56.251569 alsa_mixer-test_write_valid_LCALTA_42 pass
2570 23:39:56.252192 alsa_mixer-test_write_invalid_LCALTA_42 pass
2571 23:39:56.257168 alsa_mixer-test_event_missing_LCALTA_42 pass
2572 23:39:56.262641 alsa_mixer-test_event_spurious_LCALTA_42 pass
2573 23:39:56.268224 alsa_mixer-test_get_value_LCALTA_41 pass
2574 23:39:56.268807 alsa_mixer-test_name_LCALTA_41 pass
2575 23:39:56.273753 alsa_mixer-test_write_default_LCALTA_41 pass
2576 23:39:56.279280 alsa_mixer-test_write_valid_LCALTA_41 pass
2577 23:39:56.279864 alsa_mixer-test_write_invalid_LCALTA_41 pass
2578 23:39:56.284833 alsa_mixer-test_event_missing_LCALTA_41 pass
2579 23:39:56.290382 alsa_mixer-test_event_spurious_LCALTA_41 pass
2580 23:39:56.290967 alsa_mixer-test_get_value_LCALTA_40 pass
2581 23:39:56.295941 alsa_mixer-test_name_LCALTA_40 pass
2582 23:39:56.301466 alsa_mixer-test_write_default_LCALTA_40 pass
2583 23:39:56.302058 alsa_mixer-test_write_valid_LCALTA_40 pass
2584 23:39:56.306998 alsa_mixer-test_write_invalid_LCALTA_40 pass
2585 23:39:56.312576 alsa_mixer-test_event_missing_LCALTA_40 pass
2586 23:39:56.318111 alsa_mixer-test_event_spurious_LCALTA_40 pass
2587 23:39:56.318700 alsa_mixer-test_get_value_LCALTA_39 pass
2588 23:39:56.323657 alsa_mixer-test_name_LCALTA_39 pass
2589 23:39:56.329218 alsa_mixer-test_write_default_LCALTA_39 pass
2590 23:39:56.329788 alsa_mixer-test_write_valid_LCALTA_39 pass
2591 23:39:56.334743 alsa_mixer-test_write_invalid_LCALTA_39 pass
2592 23:39:56.340312 alsa_mixer-test_event_missing_LCALTA_39 pass
2593 23:39:56.340879 alsa_mixer-test_event_spurious_LCALTA_39 pass
2594 23:39:56.345838 alsa_mixer-test_get_value_LCALTA_38 pass
2595 23:39:56.351383 alsa_mixer-test_name_LCALTA_38 pass
2596 23:39:56.351955 alsa_mixer-test_write_default_LCALTA_38 pass
2597 23:39:56.356951 alsa_mixer-test_write_valid_LCALTA_38 pass
2598 23:39:56.362485 alsa_mixer-test_write_invalid_LCALTA_38 pass
2599 23:39:56.363055 alsa_mixer-test_event_missing_LCALTA_38 pass
2600 23:39:56.368069 alsa_mixer-test_event_spurious_LCALTA_38 pass
2601 23:39:56.373590 alsa_mixer-test_get_value_LCALTA_37 pass
2602 23:39:56.374177 alsa_mixer-test_name_LCALTA_37 pass
2603 23:39:56.379115 alsa_mixer-test_write_default_LCALTA_37 pass
2604 23:39:56.384697 alsa_mixer-test_write_valid_LCALTA_37 pass
2605 23:39:56.390225 alsa_mixer-test_write_invalid_LCALTA_37 pass
2606 23:39:56.390794 alsa_mixer-test_event_missing_LCALTA_37 pass
2607 23:39:56.395766 alsa_mixer-test_event_spurious_LCALTA_37 pass
2608 23:39:56.401330 alsa_mixer-test_get_value_LCALTA_36 pass
2609 23:39:56.401897 alsa_mixer-test_name_LCALTA_36 pass
2610 23:39:56.406844 alsa_mixer-test_write_default_LCALTA_36 pass
2611 23:39:56.412400 alsa_mixer-test_write_valid_LCALTA_36 pass
2612 23:39:56.412965 alsa_mixer-test_write_invalid_LCALTA_36 pass
2613 23:39:56.417972 alsa_mixer-test_event_missing_LCALTA_36 pass
2614 23:39:56.423486 alsa_mixer-test_event_spurious_LCALTA_36 pass
2615 23:39:56.424082 alsa_mixer-test_get_value_LCALTA_35 pass
2616 23:39:56.429029 alsa_mixer-test_name_LCALTA_35 pass
2617 23:39:56.434586 alsa_mixer-test_write_default_LCALTA_35 pass
2618 23:39:56.435150 alsa_mixer-test_write_valid_LCALTA_35 pass
2619 23:39:56.440235 alsa_mixer-test_write_invalid_LCALTA_35 pass
2620 23:39:56.445707 alsa_mixer-test_event_missing_LCALTA_35 pass
2621 23:39:56.451253 alsa_mixer-test_event_spurious_LCALTA_35 pass
2622 23:39:56.451823 alsa_mixer-test_get_value_LCALTA_34 pass
2623 23:39:56.456781 alsa_mixer-test_name_LCALTA_34 pass
2624 23:39:56.462314 alsa_mixer-test_write_default_LCALTA_34 pass
2625 23:39:56.462887 alsa_mixer-test_write_valid_LCALTA_34 pass
2626 23:39:56.467868 alsa_mixer-test_write_invalid_LCALTA_34 pass
2627 23:39:56.473431 alsa_mixer-test_event_missing_LCALTA_34 pass
2628 23:39:56.474032 alsa_mixer-test_event_spurious_LCALTA_34 pass
2629 23:39:56.478973 alsa_mixer-test_get_value_LCALTA_33 pass
2630 23:39:56.484524 alsa_mixer-test_name_LCALTA_33 pass
2631 23:39:56.485111 alsa_mixer-test_write_default_LCALTA_33 pass
2632 23:39:56.490048 alsa_mixer-test_write_valid_LCALTA_33 pass
2633 23:39:56.495601 alsa_mixer-test_write_invalid_LCALTA_33 pass
2634 23:39:56.501168 alsa_mixer-test_event_missing_LCALTA_33 pass
2635 23:39:56.501762 alsa_mixer-test_event_spurious_LCALTA_33 pass
2636 23:39:56.506723 alsa_mixer-test_get_value_LCALTA_32 pass
2637 23:39:56.507302 alsa_mixer-test_name_LCALTA_32 pass
2638 23:39:56.512244 alsa_mixer-test_write_default_LCALTA_32 pass
2639 23:39:56.517841 alsa_mixer-test_write_valid_LCALTA_32 pass
2640 23:39:56.523361 alsa_mixer-test_write_invalid_LCALTA_32 pass
2641 23:39:56.523943 alsa_mixer-test_event_missing_LCALTA_32 pass
2642 23:39:56.528888 alsa_mixer-test_event_spurious_LCALTA_32 pass
2643 23:39:56.534448 alsa_mixer-test_get_value_LCALTA_31 pass
2644 23:39:56.535037 alsa_mixer-test_name_LCALTA_31 pass
2645 23:39:56.539975 alsa_mixer-test_write_default_LCALTA_31 pass
2646 23:39:56.545534 alsa_mixer-test_write_valid_LCALTA_31 pass
2647 23:39:56.546115 alsa_mixer-test_write_invalid_LCALTA_31 pass
2648 23:39:56.551068 alsa_mixer-test_event_missing_LCALTA_31 pass
2649 23:39:56.556616 alsa_mixer-test_event_spurious_LCALTA_31 pass
2650 23:39:56.562172 alsa_mixer-test_get_value_LCALTA_30 pass
2651 23:39:56.562759 alsa_mixer-test_name_LCALTA_30 pass
2652 23:39:56.567699 alsa_mixer-test_write_default_LCALTA_30 pass
2653 23:39:56.573258 alsa_mixer-test_write_valid_LCALTA_30 pass
2654 23:39:56.573843 alsa_mixer-test_write_invalid_LCALTA_30 pass
2655 23:39:56.578811 alsa_mixer-test_event_missing_LCALTA_30 pass
2656 23:39:56.584374 alsa_mixer-test_event_spurious_LCALTA_30 pass
2657 23:39:56.584964 alsa_mixer-test_get_value_LCALTA_29 pass
2658 23:39:56.589897 alsa_mixer-test_name_LCALTA_29 pass
2659 23:39:56.595461 alsa_mixer-test_write_default_LCALTA_29 pass
2660 23:39:56.596097 alsa_mixer-test_write_valid_LCALTA_29 pass
2661 23:39:56.600962 alsa_mixer-test_write_invalid_LCALTA_29 pass
2662 23:39:56.606518 alsa_mixer-test_event_missing_LCALTA_29 pass
2663 23:39:56.607092 alsa_mixer-test_event_spurious_LCALTA_29 pass
2664 23:39:56.612108 alsa_mixer-test_get_value_LCALTA_28 pass
2665 23:39:56.617637 alsa_mixer-test_name_LCALTA_28 pass
2666 23:39:56.618225 alsa_mixer-test_write_default_LCALTA_28 pass
2667 23:39:56.623186 alsa_mixer-test_write_valid_LCALTA_28 pass
2668 23:39:56.628757 alsa_mixer-test_write_invalid_LCALTA_28 pass
2669 23:39:56.634276 alsa_mixer-test_event_missing_LCALTA_28 pass
2670 23:39:56.634861 alsa_mixer-test_event_spurious_LCALTA_28 pass
2671 23:39:56.639795 alsa_mixer-test_get_value_LCALTA_27 pass
2672 23:39:56.645379 alsa_mixer-test_name_LCALTA_27 pass
2673 23:39:56.645968 alsa_mixer-test_write_default_LCALTA_27 pass
2674 23:39:56.650911 alsa_mixer-test_write_valid_LCALTA_27 pass
2675 23:39:56.656502 alsa_mixer-test_write_invalid_LCALTA_27 pass
2676 23:39:56.657104 alsa_mixer-test_event_missing_LCALTA_27 pass
2677 23:39:56.662101 alsa_mixer-test_event_spurious_LCALTA_27 pass
2678 23:39:56.667545 alsa_mixer-test_get_value_LCALTA_26 pass
2679 23:39:56.668138 alsa_mixer-test_name_LCALTA_26 pass
2680 23:39:56.673111 alsa_mixer-test_write_default_LCALTA_26 skip
2681 23:39:56.678665 alsa_mixer-test_write_valid_LCALTA_26 skip
2682 23:39:56.679259 alsa_mixer-test_write_invalid_LCALTA_26 skip
2683 23:39:56.684227 alsa_mixer-test_event_missing_LCALTA_26 pass
2684 23:39:56.689745 alsa_mixer-test_event_spurious_LCALTA_26 pass
2685 23:39:56.695298 alsa_mixer-test_get_value_LCALTA_25 pass
2686 23:39:56.695882 alsa_mixer-test_name_LCALTA_25 pass
2687 23:39:56.700840 alsa_mixer-test_write_default_LCALTA_25 pass
2688 23:39:56.706450 alsa_mixer-test_write_valid_LCALTA_25 skip
2689 23:39:56.707020 alsa_mixer-test_write_invalid_LCALTA_25 skip
2690 23:39:56.712055 alsa_mixer-test_event_missing_LCALTA_25 pass
2691 23:39:56.717475 alsa_mixer-test_event_spurious_LCALTA_25 pass
2692 23:39:56.718050 alsa_mixer-test_get_value_LCALTA_24 pass
2693 23:39:56.723077 alsa_mixer-test_name_LCALTA_24 pass
2694 23:39:56.728564 alsa_mixer-test_write_default_LCALTA_24 skip
2695 23:39:56.729163 alsa_mixer-test_write_valid_LCALTA_24 skip
2696 23:39:56.734133 alsa_mixer-test_write_invalid_LCALTA_24 skip
2697 23:39:56.739677 alsa_mixer-test_event_missing_LCALTA_24 pass
2698 23:39:56.745214 alsa_mixer-test_event_spurious_LCALTA_24 pass
2699 23:39:56.745788 alsa_mixer-test_get_value_LCALTA_23 pass
2700 23:39:56.750758 alsa_mixer-test_name_LCALTA_23 pass
2701 23:39:56.756308 alsa_mixer-test_write_default_LCALTA_23 skip
2702 23:39:56.756877 alsa_mixer-test_write_valid_LCALTA_23 skip
2703 23:39:56.761851 alsa_mixer-test_write_invalid_LCALTA_23 skip
2704 23:39:56.767386 alsa_mixer-test_event_missing_LCALTA_23 pass
2705 23:39:56.767975 alsa_mixer-test_event_spurious_LCALTA_23 pass
2706 23:39:56.773034 alsa_mixer-test_get_value_LCALTA_22 pass
2707 23:39:56.778505 alsa_mixer-test_name_LCALTA_22 pass
2708 23:39:56.779104 alsa_mixer-test_write_default_LCALTA_22 pass
2709 23:39:56.784086 alsa_mixer-test_write_valid_LCALTA_22 pass
2710 23:39:56.789596 alsa_mixer-test_write_invalid_LCALTA_22 pass
2711 23:39:56.790187 alsa_mixer-test_event_missing_LCALTA_22 pass
2712 23:39:56.795132 alsa_mixer-test_event_spurious_LCALTA_22 pass
2713 23:39:56.800858 alsa_mixer-test_get_value_LCALTA_21 pass
2714 23:39:56.801468 alsa_mixer-test_name_LCALTA_21 pass
2715 23:39:56.806232 alsa_mixer-test_write_default_LCALTA_21 pass
2716 23:39:56.811774 alsa_mixer-test_write_valid_LCALTA_21 pass
2717 23:39:56.817332 alsa_mixer-test_write_invalid_LCALTA_21 pass
2718 23:39:56.817918 alsa_mixer-test_event_missing_LCALTA_21 pass
2719 23:39:56.822871 alsa_mixer-test_event_spurious_LCALTA_21 pass
2720 23:39:56.828413 alsa_mixer-test_get_value_LCALTA_20 pass
2721 23:39:56.829014 alsa_mixer-test_name_LCALTA_20 pass
2722 23:39:56.834048 alsa_mixer-test_write_default_LCALTA_20 pass
2723 23:39:56.839505 alsa_mixer-test_write_valid_LCALTA_20 pass
2724 23:39:56.840116 alsa_mixer-test_write_invalid_LCALTA_20 pass
2725 23:39:56.845063 alsa_mixer-test_event_missing_LCALTA_20 pass
2726 23:39:56.850595 alsa_mixer-test_event_spurious_LCALTA_20 pass
2727 23:39:56.851182 alsa_mixer-test_get_value_LCALTA_19 pass
2728 23:39:56.856201 alsa_mixer-test_name_LCALTA_19 pass
2729 23:39:56.861695 alsa_mixer-test_write_default_LCALTA_19 pass
2730 23:39:56.862311 alsa_mixer-test_write_valid_LCALTA_19 pass
2731 23:39:56.867247 alsa_mixer-test_write_invalid_LCALTA_19 pass
2732 23:39:56.872778 alsa_mixer-test_event_missing_LCALTA_19 pass
2733 23:39:56.878333 alsa_mixer-test_event_spurious_LCALTA_19 pass
2734 23:39:56.878927 alsa_mixer-test_get_value_LCALTA_18 pass
2735 23:39:56.883887 alsa_mixer-test_name_LCALTA_18 pass
2736 23:39:56.889420 alsa_mixer-test_write_default_LCALTA_18 pass
2737 23:39:56.890028 alsa_mixer-test_write_valid_LCALTA_18 pass
2738 23:39:56.895022 alsa_mixer-test_write_invalid_LCALTA_18 pass
2739 23:39:56.900525 alsa_mixer-test_event_missing_LCALTA_18 pass
2740 23:39:56.901121 alsa_mixer-test_event_spurious_LCALTA_18 pass
2741 23:39:56.906074 alsa_mixer-test_get_value_LCALTA_17 pass
2742 23:39:56.911604 alsa_mixer-test_name_LCALTA_17 pass
2743 23:39:56.912223 alsa_mixer-test_write_default_LCALTA_17 pass
2744 23:39:56.917159 alsa_mixer-test_write_valid_LCALTA_17 pass
2745 23:39:56.922695 alsa_mixer-test_write_invalid_LCALTA_17 pass
2746 23:39:56.928248 alsa_mixer-test_event_missing_LCALTA_17 pass
2747 23:39:56.928842 alsa_mixer-test_event_spurious_LCALTA_17 pass
2748 23:39:56.933776 alsa_mixer-test_get_value_LCALTA_16 pass
2749 23:39:56.934355 alsa_mixer-test_name_LCALTA_16 pass
2750 23:39:56.939321 alsa_mixer-test_write_default_LCALTA_16 pass
2751 23:39:56.944887 alsa_mixer-test_write_valid_LCALTA_16 pass
2752 23:39:56.950512 alsa_mixer-test_write_invalid_LCALTA_16 pass
2753 23:39:56.951159 alsa_mixer-test_event_missing_LCALTA_16 pass
2754 23:39:56.956178 alsa_mixer-test_event_spurious_LCALTA_16 pass
2755 23:39:56.961596 alsa_mixer-test_get_value_LCALTA_15 pass
2756 23:39:56.962184 alsa_mixer-test_name_LCALTA_15 pass
2757 23:39:56.967094 alsa_mixer-test_write_default_LCALTA_15 pass
2758 23:39:56.972623 alsa_mixer-test_write_valid_LCALTA_15 pass
2759 23:39:56.973188 alsa_mixer-test_write_invalid_LCALTA_15 pass
2760 23:39:56.978158 alsa_mixer-test_event_missing_LCALTA_15 pass
2761 23:39:56.983800 alsa_mixer-test_event_spurious_LCALTA_15 pass
2762 23:39:56.989307 alsa_mixer-test_get_value_LCALTA_14 pass
2763 23:39:56.989883 alsa_mixer-test_name_LCALTA_14 pass
2764 23:39:56.994826 alsa_mixer-test_write_default_LCALTA_14 pass
2765 23:39:57.000360 alsa_mixer-test_write_valid_LCALTA_14 pass
2766 23:39:57.000945 alsa_mixer-test_write_invalid_LCALTA_14 pass
2767 23:39:57.005911 alsa_mixer-test_event_missing_LCALTA_14 pass
2768 23:39:57.011456 alsa_mixer-test_event_spurious_LCALTA_14 pass
2769 23:39:57.012074 alsa_mixer-test_get_value_LCALTA_13 pass
2770 23:39:57.017080 alsa_mixer-test_name_LCALTA_13 pass
2771 23:39:57.022555 alsa_mixer-test_write_default_LCALTA_13 pass
2772 23:39:57.023167 alsa_mixer-test_write_valid_LCALTA_13 pass
2773 23:39:57.028105 alsa_mixer-test_write_invalid_LCALTA_13 pass
2774 23:39:57.033631 alsa_mixer-test_event_missing_LCALTA_13 pass
2775 23:39:57.034213 alsa_mixer-test_event_spurious_LCALTA_13 pass
2776 23:39:57.039173 alsa_mixer-test_get_value_LCALTA_12 pass
2777 23:39:57.044707 alsa_mixer-test_name_LCALTA_12 pass
2778 23:39:57.045293 alsa_mixer-test_write_default_LCALTA_12 pass
2779 23:39:57.050286 alsa_mixer-test_write_valid_LCALTA_12 pass
2780 23:39:57.055816 alsa_mixer-test_write_invalid_LCALTA_12 pass
2781 23:39:57.061372 alsa_mixer-test_event_missing_LCALTA_12 pass
2782 23:39:57.061975 alsa_mixer-test_event_spurious_LCALTA_12 pass
2783 23:39:57.066930 alsa_mixer-test_get_value_LCALTA_11 pass
2784 23:39:57.072445 alsa_mixer-test_name_LCALTA_11 pass
2785 23:39:57.073036 alsa_mixer-test_write_default_LCALTA_11 pass
2786 23:39:57.078050 alsa_mixer-test_write_valid_LCALTA_11 pass
2787 23:39:57.083516 alsa_mixer-test_write_invalid_LCALTA_11 pass
2788 23:39:57.084116 alsa_mixer-test_event_missing_LCALTA_11 pass
2789 23:39:57.089110 alsa_mixer-test_event_spurious_LCALTA_11 pass
2790 23:39:57.094646 alsa_mixer-test_get_value_LCALTA_10 pass
2791 23:39:57.095238 alsa_mixer-test_name_LCALTA_10 pass
2792 23:39:57.100231 alsa_mixer-test_write_default_LCALTA_10 pass
2793 23:39:57.105722 alsa_mixer-test_write_valid_LCALTA_10 pass
2794 23:39:57.106327 alsa_mixer-test_write_invalid_LCALTA_10 pass
2795 23:39:57.111273 alsa_mixer-test_event_missing_LCALTA_10 pass
2796 23:39:57.116834 alsa_mixer-test_event_spurious_LCALTA_10 pass
2797 23:39:57.122385 alsa_mixer-test_get_value_LCALTA_9 pass
2798 23:39:57.122955 alsa_mixer-test_name_LCALTA_9 pass
2799 23:39:57.127922 alsa_mixer-test_write_default_LCALTA_9 pass
2800 23:39:57.133480 alsa_mixer-test_write_valid_LCALTA_9 pass
2801 23:39:57.134077 alsa_mixer-test_write_invalid_LCALTA_9 pass
2802 23:39:57.139023 alsa_mixer-test_event_missing_LCALTA_9 pass
2803 23:39:57.144597 alsa_mixer-test_event_spurious_LCALTA_9 pass
2804 23:39:57.145169 alsa_mixer-test_get_value_LCALTA_8 pass
2805 23:39:57.150123 alsa_mixer-test_name_LCALTA_8 pass
2806 23:39:57.155656 alsa_mixer-test_write_default_LCALTA_8 pass
2807 23:39:57.156249 alsa_mixer-test_write_valid_LCALTA_8 pass
2808 23:39:57.161207 alsa_mixer-test_write_invalid_LCALTA_8 pass
2809 23:39:57.166770 alsa_mixer-test_event_missing_LCALTA_8 pass
2810 23:39:57.167358 alsa_mixer-test_event_spurious_LCALTA_8 pass
2811 23:39:57.172362 alsa_mixer-test_get_value_LCALTA_7 pass
2812 23:39:57.177839 alsa_mixer-test_name_LCALTA_7 pass
2813 23:39:57.178427 alsa_mixer-test_write_default_LCALTA_7 pass
2814 23:39:57.183390 alsa_mixer-test_write_valid_LCALTA_7 pass
2815 23:39:57.188961 alsa_mixer-test_write_invalid_LCALTA_7 pass
2816 23:39:57.189558 alsa_mixer-test_event_missing_LCALTA_7 pass
2817 23:39:57.194507 alsa_mixer-test_event_spurious_LCALTA_7 pass
2818 23:39:57.200083 alsa_mixer-test_get_value_LCALTA_6 pass
2819 23:39:57.200661 alsa_mixer-test_name_LCALTA_6 pass
2820 23:39:57.205590 alsa_mixer-test_write_default_LCALTA_6 pass
2821 23:39:57.211113 alsa_mixer-test_write_valid_LCALTA_6 pass
2822 23:39:57.211685 alsa_mixer-test_write_invalid_LCALTA_6 pass
2823 23:39:57.216670 alsa_mixer-test_event_missing_LCALTA_6 pass
2824 23:39:57.222215 alsa_mixer-test_event_spurious_LCALTA_6 pass
2825 23:39:57.222786 alsa_mixer-test_get_value_LCALTA_5 pass
2826 23:39:57.227763 alsa_mixer-test_name_LCALTA_5 pass
2827 23:39:57.233329 alsa_mixer-test_write_default_LCALTA_5 pass
2828 23:39:57.233954 alsa_mixer-test_write_valid_LCALTA_5 pass
2829 23:39:57.238841 alsa_mixer-test_write_invalid_LCALTA_5 pass
2830 23:39:57.244386 alsa_mixer-test_event_missing_LCALTA_5 pass
2831 23:39:57.244955 alsa_mixer-test_event_spurious_LCALTA_5 pass
2832 23:39:57.249966 alsa_mixer-test_get_value_LCALTA_4 pass
2833 23:39:57.255516 alsa_mixer-test_name_LCALTA_4 pass
2834 23:39:57.256120 alsa_mixer-test_write_default_LCALTA_4 pass
2835 23:39:57.261061 alsa_mixer-test_write_valid_LCALTA_4 pass
2836 23:39:57.266595 alsa_mixer-test_write_invalid_LCALTA_4 pass
2837 23:39:57.267153 alsa_mixer-test_event_missing_LCALTA_4 pass
2838 23:39:57.272189 alsa_mixer-test_event_spurious_LCALTA_4 pass
2839 23:39:57.277700 alsa_mixer-test_get_value_LCALTA_3 pass
2840 23:39:57.278278 alsa_mixer-test_name_LCALTA_3 pass
2841 23:39:57.283218 alsa_mixer-test_write_default_LCALTA_3 pass
2842 23:39:57.288781 alsa_mixer-test_write_valid_LCALTA_3 pass
2843 23:39:57.289354 alsa_mixer-test_write_invalid_LCALTA_3 pass
2844 23:39:57.294313 alsa_mixer-test_event_missing_LCALTA_3 pass
2845 23:39:57.299849 alsa_mixer-test_event_spurious_LCALTA_3 pass
2846 23:39:57.300445 alsa_mixer-test_get_value_LCALTA_2 pass
2847 23:39:57.305409 alsa_mixer-test_name_LCALTA_2 pass
2848 23:39:57.310969 alsa_mixer-test_write_default_LCALTA_2 pass
2849 23:39:57.311533 alsa_mixer-test_write_valid_LCALTA_2 pass
2850 23:39:57.316501 alsa_mixer-test_write_invalid_LCALTA_2 pass
2851 23:39:57.322082 alsa_mixer-test_event_missing_LCALTA_2 pass
2852 23:39:57.327615 alsa_mixer-test_event_spurious_LCALTA_2 pass
2853 23:39:57.328252 alsa_mixer-test_get_value_LCALTA_1 pass
2854 23:39:57.333163 alsa_mixer-test_name_LCALTA_1 pass
2855 23:39:57.333773 alsa_mixer-test_write_default_LCALTA_1 pass
2856 23:39:57.338713 alsa_mixer-test_write_valid_LCALTA_1 pass
2857 23:39:57.344288 alsa_mixer-test_write_invalid_LCALTA_1 pass
2858 23:39:57.349917 alsa_mixer-test_event_missing_LCALTA_1 pass
2859 23:39:57.350496 alsa_mixer-test_event_spurious_LCALTA_1 pass
2860 23:39:57.355341 alsa_mixer-test_get_value_LCALTA_0 pass
2861 23:39:57.355908 alsa_mixer-test_name_LCALTA_0 pass
2862 23:39:57.360889 alsa_mixer-test_write_default_LCALTA_0 pass
2863 23:39:57.366437 alsa_mixer-test_write_valid_LCALTA_0 pass
2864 23:39:57.372038 alsa_mixer-test_write_invalid_LCALTA_0 pass
2865 23:39:57.372626 alsa_mixer-test_event_missing_LCALTA_0 pass
2866 23:39:57.377532 alsa_mixer-test_event_spurious_LCALTA_0 pass
2867 23:39:57.378100 alsa_mixer-test pass
2868 23:39:57.383118 alsa_pcm-test_default_time1_LCALTA_5_0_CAPTURE skip
2869 23:39:57.388652 alsa_pcm-test_default_time2_LCALTA_5_0_CAPTURE skip
2870 23:39:57.394170 alsa_pcm-test_default_time3_LCALTA_5_0_CAPTURE skip
2871 23:39:57.399740 alsa_pcm-test_default_time4_LCALTA_5_0_CAPTURE skip
2872 23:39:57.400368 alsa_pcm-test_default_time5_LCALTA_5_0_CAPTURE skip
2873 23:39:57.405255 alsa_pcm-test_default_time6_LCALTA_5_0_CAPTURE skip
2874 23:39:57.410810 alsa_pcm-test_default_time7_LCALTA_5_0_CAPTURE skip
2875 23:39:57.416383 alsa_pcm-test_default_time1_LCALTA_4_0_CAPTURE skip
2876 23:39:57.421911 alsa_pcm-test_default_time2_LCALTA_4_0_CAPTURE skip
2877 23:39:57.427454 alsa_pcm-test_default_time3_LCALTA_4_0_CAPTURE skip
2878 23:39:57.428145 alsa_pcm-test_default_time4_LCALTA_4_0_CAPTURE skip
2879 23:39:57.433022 alsa_pcm-test_default_time5_LCALTA_4_0_CAPTURE skip
2880 23:39:57.438553 alsa_pcm-test_default_time6_LCALTA_4_0_CAPTURE skip
2881 23:39:57.444189 alsa_pcm-test_default_time7_LCALTA_4_0_CAPTURE skip
2882 23:39:57.449705 alsa_pcm-test_default_time1_LCALTA_3_0_CAPTURE skip
2883 23:39:57.455244 alsa_pcm-test_default_time2_LCALTA_3_0_CAPTURE skip
2884 23:39:57.455842 alsa_pcm-test_default_time3_LCALTA_3_0_CAPTURE skip
2885 23:39:57.460749 alsa_pcm-test_default_time4_LCALTA_3_0_CAPTURE skip
2886 23:39:57.466384 alsa_pcm-test_default_time5_LCALTA_3_0_CAPTURE skip
2887 23:39:57.471919 alsa_pcm-test_default_time6_LCALTA_3_0_CAPTURE skip
2888 23:39:57.477467 alsa_pcm-test_default_time7_LCALTA_3_0_CAPTURE skip
2889 23:39:57.482997 alsa_pcm-test_default_time1_LCALTA_2_0_PLAYBACK skip
2890 23:39:57.483538 alsa_pcm-test_default_time2_LCALTA_2_0_PLAYBACK skip
2891 23:39:57.488579 alsa_pcm-test_default_time3_LCALTA_2_0_PLAYBACK skip
2892 23:39:57.494119 alsa_pcm-test_default_time4_LCALTA_2_0_PLAYBACK skip
2893 23:39:57.499626 alsa_pcm-test_default_time5_LCALTA_2_0_PLAYBACK skip
2894 23:39:57.505213 alsa_pcm-test_default_time6_LCALTA_2_0_PLAYBACK skip
2895 23:39:57.510746 alsa_pcm-test_default_time7_LCALTA_2_0_PLAYBACK skip
2896 23:39:57.511295 alsa_pcm-test_default_time1_LCALTA_1_0_PLAYBACK skip
2897 23:39:57.516301 alsa_pcm-test_default_time2_LCALTA_1_0_PLAYBACK skip
2898 23:39:57.521821 alsa_pcm-test_default_time3_LCALTA_1_0_PLAYBACK skip
2899 23:39:57.527372 alsa_pcm-test_default_time4_LCALTA_1_0_PLAYBACK skip
2900 23:39:57.532954 alsa_pcm-test_default_time5_LCALTA_1_0_PLAYBACK skip
2901 23:39:57.538470 alsa_pcm-test_default_time6_LCALTA_1_0_PLAYBACK skip
2902 23:39:57.544011 alsa_pcm-test_default_time7_LCALTA_1_0_PLAYBACK skip
2903 23:39:57.544571 alsa_pcm-test_default_time1_LCALTA_0_0_PLAYBACK skip
2904 23:39:57.549541 alsa_pcm-test_default_time2_LCALTA_0_0_PLAYBACK skip
2905 23:39:57.555152 alsa_pcm-test_default_time3_LCALTA_0_0_PLAYBACK skip
2906 23:39:57.560636 alsa_pcm-test_default_time4_LCALTA_0_0_PLAYBACK skip
2907 23:39:57.566202 alsa_pcm-test_default_time5_LCALTA_0_0_PLAYBACK skip
2908 23:39:57.571872 alsa_pcm-test_default_time6_LCALTA_0_0_PLAYBACK skip
2909 23:39:57.572507 alsa_pcm-test_default_time7_LCALTA_0_0_PLAYBACK skip
2910 23:39:57.577249 alsa_pcm-test pass
2911 23:39:57.582851 alsa_test-pcmtest-driver_pcmtest_playback_Can_t_read_patterns_Probably_module_isn_t_loaded skip
2912 23:39:57.593884 alsa_test-pcmtest-driver_pcmtest_capture_Can_t_read_patterns_Probably_module_isn_t_loaded skip
2913 23:39:57.599464 alsa_test-pcmtest-driver_pcmtest_ni_capture_Can_t_read_patterns_Probably_module_isn_t_loaded skip
2914 23:39:57.610507 alsa_test-pcmtest-driver_pcmtest_ni_playback_Can_t_read_patterns_Probably_module_isn_t_loaded skip
2915 23:39:57.616149 alsa_test-pcmtest-driver_pcmtest_reset_ioctl_Can_t_read_patterns_Probably_module_isn_t_loaded skip
2916 23:39:57.621664 alsa_test-pcmtest-driver pass
2917 23:39:57.627215 alsa_utimer-test_global_wrong_timers_test pass
2918 23:39:57.627760 alsa_utimer-test_timer_f_utimer fail
2919 23:39:57.632739 alsa_utimer-test fail
2920 23:39:57.633280 + ../../utils/send-to-lava.sh ./output/result.txt
2921 23:39:57.638280 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-alsa RESULT=pass>
2922 23:39:57.639305 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-alsa RESULT=pass
2924 23:39:57.649357 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_60 RESULT=pass>
2925 23:39:57.650224 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_60 RESULT=pass
2927 23:39:57.655193 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_60 RESULT=pass>
2928 23:39:57.656039 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_60 RESULT=pass
2930 23:39:57.683363 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_60 RESULT=pass>
2931 23:39:57.684217 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_60 RESULT=pass
2933 23:39:57.733452 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_60 RESULT=pass>
2934 23:39:57.734318 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_60 RESULT=pass
2936 23:39:57.778940 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_60 RESULT=pass>
2937 23:39:57.779853 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_60 RESULT=pass
2939 23:39:57.834665 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_60 RESULT=pass>
2940 23:39:57.835552 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_60 RESULT=pass
2942 23:39:57.892726 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_60 RESULT=pass>
2943 23:39:57.893605 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_60 RESULT=pass
2945 23:39:57.954212 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_59 RESULT=pass>
2946 23:39:57.955091 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_59 RESULT=pass
2948 23:39:58.010478 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_59 RESULT=pass>
2949 23:39:58.011371 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_59 RESULT=pass
2951 23:39:58.063673 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_59 RESULT=pass>
2952 23:39:58.064597 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_59 RESULT=pass
2954 23:39:58.124303 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_59 RESULT=pass>
2955 23:39:58.125167 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_59 RESULT=pass
2957 23:39:58.167635 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_59 RESULT=pass>
2958 23:39:58.168554 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_59 RESULT=pass
2960 23:39:58.217066 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_59 RESULT=pass>
2961 23:39:58.217957 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_59 RESULT=pass
2963 23:39:58.266809 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_59 RESULT=pass>
2964 23:39:58.267673 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_59 RESULT=pass
2966 23:39:58.315819 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_58 RESULT=pass>
2967 23:39:58.316722 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_58 RESULT=pass
2969 23:39:58.372289 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_58 RESULT=pass>
2970 23:39:58.373164 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_58 RESULT=pass
2972 23:39:58.421287 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_58 RESULT=pass>
2973 23:39:58.422134 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_58 RESULT=pass
2975 23:39:58.471699 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_58 RESULT=pass>
2976 23:39:58.472641 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_58 RESULT=pass
2978 23:39:58.523809 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_58 RESULT=pass>
2979 23:39:58.524742 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_58 RESULT=pass
2981 23:39:58.575713 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_58 RESULT=pass>
2982 23:39:58.576617 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_58 RESULT=pass
2984 23:39:58.634760 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_58 RESULT=pass>
2985 23:39:58.635652 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_58 RESULT=pass
2987 23:39:58.684398 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_57 RESULT=pass>
2988 23:39:58.685264 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_57 RESULT=pass
2990 23:39:58.736684 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_57 RESULT=pass>
2991 23:39:58.737549 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_57 RESULT=pass
2993 23:39:58.787434 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_57 RESULT=pass>
2994 23:39:58.788322 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_57 RESULT=pass
2996 23:39:58.845128 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_57 RESULT=pass>
2997 23:39:58.845996 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_57 RESULT=pass
2999 23:39:58.895578 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_57 RESULT=pass>
3000 23:39:58.896459 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_57 RESULT=pass
3002 23:39:58.948273 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_57 RESULT=pass>
3003 23:39:58.949126 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_57 RESULT=pass
3005 23:39:59.009633 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_57 RESULT=pass>
3006 23:39:59.010508 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_57 RESULT=pass
3008 23:39:59.053260 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_56 RESULT=pass>
3009 23:39:59.054115 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_56 RESULT=pass
3011 23:39:59.105450 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_56 RESULT=pass>
3012 23:39:59.106362 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_56 RESULT=pass
3014 23:39:59.153924 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_56 RESULT=pass>
3015 23:39:59.154769 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_56 RESULT=pass
3017 23:39:59.208984 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_56 RESULT=pass>
3018 23:39:59.209884 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_56 RESULT=pass
3020 23:39:59.260832 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_56 RESULT=pass>
3021 23:39:59.261687 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_56 RESULT=pass
3023 23:39:59.309148 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_56 RESULT=pass>
3024 23:39:59.310349 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_56 RESULT=pass
3026 23:39:59.362546 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_56 RESULT=pass>
3027 23:39:59.363483 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_56 RESULT=pass
3029 23:39:59.419242 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_55 RESULT=pass>
3030 23:39:59.420151 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_55 RESULT=pass
3032 23:39:59.472613 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_55 RESULT=pass>
3033 23:39:59.473502 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_55 RESULT=pass
3035 23:39:59.525196 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_55 RESULT=pass>
3036 23:39:59.526073 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_55 RESULT=pass
3038 23:39:59.582083 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_55 RESULT=pass>
3039 23:39:59.582968 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_55 RESULT=pass
3041 23:39:59.633510 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_55 RESULT=pass>
3042 23:39:59.634382 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_55 RESULT=pass
3044 23:39:59.698216 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_55 RESULT=pass>
3045 23:39:59.699098 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_55 RESULT=pass
3047 23:39:59.749667 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_55 RESULT=pass>
3048 23:39:59.750540 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_55 RESULT=pass
3050 23:39:59.800772 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_54 RESULT=pass>
3051 23:39:59.801674 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_54 RESULT=pass
3053 23:39:59.858182 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_54 RESULT=pass>
3054 23:39:59.859020 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_54 RESULT=pass
3056 23:39:59.916615 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_54 RESULT=pass>
3057 23:39:59.917497 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_54 RESULT=pass
3059 23:39:59.968134 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_54 RESULT=pass>
3060 23:39:59.969200 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_54 RESULT=pass
3062 23:40:00.020942 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_54 RESULT=pass>
3063 23:40:00.021847 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_54 RESULT=pass
3065 23:40:00.067027 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_54 RESULT=pass>
3066 23:40:00.067923 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_54 RESULT=pass
3068 23:40:00.120300 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_54 RESULT=pass>
3069 23:40:00.121377 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_54 RESULT=pass
3071 23:40:00.184789 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_53 RESULT=pass>
3072 23:40:00.185811 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_53 RESULT=pass
3074 23:40:00.235533 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_53 RESULT=pass>
3075 23:40:00.236478 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_53 RESULT=pass
3077 23:40:00.293435 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_53 RESULT=pass>
3078 23:40:00.294348 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_53 RESULT=pass
3080 23:40:00.348432 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_53 RESULT=pass>
3081 23:40:00.349354 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_53 RESULT=pass
3083 23:40:00.412661 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_53 RESULT=pass>
3084 23:40:00.413637 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_53 RESULT=pass
3086 23:40:00.464387 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_53 RESULT=pass>
3087 23:40:00.465292 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_53 RESULT=pass
3089 23:40:00.514711 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_53 RESULT=pass>
3090 23:40:00.515578 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_53 RESULT=pass
3092 23:40:00.564781 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_52 RESULT=pass>
3093 23:40:00.565644 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_52 RESULT=pass
3095 23:40:00.616418 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_52 RESULT=pass>
3096 23:40:00.617257 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_52 RESULT=pass
3098 23:40:00.674837 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_52 RESULT=pass>
3099 23:40:00.675698 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_52 RESULT=pass
3101 23:40:00.731132 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_52 RESULT=pass>
3102 23:40:00.732015 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_52 RESULT=pass
3104 23:40:00.783668 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_52 RESULT=pass>
3105 23:40:00.784577 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_52 RESULT=pass
3107 23:40:00.839861 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_52 RESULT=pass>
3108 23:40:00.840738 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_52 RESULT=pass
3110 23:40:00.890476 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_52 RESULT=pass>
3111 23:40:00.891375 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_52 RESULT=pass
3113 23:40:00.947583 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_51 RESULT=pass>
3114 23:40:00.948465 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_51 RESULT=pass
3116 23:40:00.997586 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_51 RESULT=pass>
3117 23:40:00.998424 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_51 RESULT=pass
3119 23:40:01.056632 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_51 RESULT=pass>
3120 23:40:01.057502 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_51 RESULT=pass
3122 23:40:01.112813 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_51 RESULT=pass>
3123 23:40:01.113842 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_51 RESULT=pass
3125 23:40:01.175672 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_51 RESULT=pass>
3126 23:40:01.176766 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_51 RESULT=pass
3128 23:40:01.233700 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_51 RESULT=pass>
3129 23:40:01.234693 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_51 RESULT=pass
3131 23:40:01.282983 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_51 RESULT=pass>
3132 23:40:01.283913 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_51 RESULT=pass
3134 23:40:01.336275 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_50 RESULT=pass>
3135 23:40:01.337222 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_50 RESULT=pass
3137 23:40:01.381256 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_50 RESULT=pass>
3138 23:40:01.382133 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_50 RESULT=pass
3140 23:40:01.431885 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_50 RESULT=pass>
3141 23:40:01.432872 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_50 RESULT=pass
3143 23:40:01.488349 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_50 RESULT=pass>
3144 23:40:01.489240 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_50 RESULT=pass
3146 23:40:01.543881 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_50 RESULT=pass>
3147 23:40:01.544932 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_50 RESULT=pass
3149 23:40:01.598939 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_50 RESULT=pass>
3150 23:40:01.599889 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_50 RESULT=pass
3152 23:40:01.650963 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_50 RESULT=pass>
3153 23:40:01.651844 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_50 RESULT=pass
3155 23:40:01.705228 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_49 RESULT=pass>
3156 23:40:01.706181 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_49 RESULT=pass
3158 23:40:01.762833 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_49 RESULT=pass>
3159 23:40:01.763700 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_49 RESULT=pass
3161 23:40:01.807090 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_49 RESULT=pass>
3162 23:40:01.807954 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_49 RESULT=pass
3164 23:40:01.866392 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_49 RESULT=pass>
3165 23:40:01.867269 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_49 RESULT=pass
3167 23:40:01.919912 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_49 RESULT=pass>
3168 23:40:01.920866 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_49 RESULT=pass
3170 23:40:01.973521 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_49 RESULT=pass>
3171 23:40:01.974457 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_49 RESULT=pass
3173 23:40:02.025008 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_49 RESULT=pass>
3174 23:40:02.025932 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_49 RESULT=pass
3176 23:40:02.077214 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_48 RESULT=pass>
3177 23:40:02.078105 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_48 RESULT=pass
3179 23:40:02.126696 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_48 RESULT=pass>
3180 23:40:02.127563 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_48 RESULT=pass
3182 23:40:02.184016 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_48 RESULT=pass>
3183 23:40:02.185008 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_48 RESULT=pass
3185 23:40:02.235163 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_48 RESULT=pass>
3186 23:40:02.236096 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_48 RESULT=pass
3188 23:40:02.287202 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_48 RESULT=pass>
3189 23:40:02.288063 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_48 RESULT=pass
3191 23:40:02.344428 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_48 RESULT=pass>
3192 23:40:02.345270 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_48 RESULT=pass
3194 23:40:02.389704 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_48 RESULT=pass>
3195 23:40:02.390541 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_48 RESULT=pass
3197 23:40:02.434623 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_47 RESULT=pass>
3198 23:40:02.435450 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_47 RESULT=pass
3200 23:40:02.496381 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_47 RESULT=pass>
3201 23:40:02.497230 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_47 RESULT=pass
3203 23:40:02.554595 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_47 RESULT=pass>
3204 23:40:02.555419 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_47 RESULT=pass
3206 23:40:02.606140 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_47 RESULT=pass>
3207 23:40:02.606939 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_47 RESULT=pass
3209 23:40:02.663693 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_47 RESULT=pass>
3210 23:40:02.664559 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_47 RESULT=pass
3212 23:40:02.718738 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_47 RESULT=pass>
3213 23:40:02.719543 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_47 RESULT=pass
3215 23:40:02.769470 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_47 RESULT=pass>
3216 23:40:02.770329 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_47 RESULT=pass
3218 23:40:02.815439 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_46 RESULT=pass>
3219 23:40:02.816327 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_46 RESULT=pass
3221 23:40:02.871532 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_46 RESULT=pass>
3222 23:40:02.872393 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_46 RESULT=pass
3224 23:40:02.921428 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_46 RESULT=pass>
3225 23:40:02.922244 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_46 RESULT=pass
3227 23:40:02.980378 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_46 RESULT=pass>
3228 23:40:02.981323 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_46 RESULT=pass
3230 23:40:03.025567 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_46 RESULT=pass>
3231 23:40:03.026414 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_46 RESULT=pass
3233 23:40:03.082210 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_46 RESULT=pass>
3234 23:40:03.083329 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_46 RESULT=pass
3236 23:40:03.128812 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_46 RESULT=pass>
3237 23:40:03.129934 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_46 RESULT=pass
3239 23:40:03.176231 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_45 RESULT=pass>
3240 23:40:03.177171 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_45 RESULT=pass
3242 23:40:03.236138 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_45 RESULT=pass>
3243 23:40:03.237007 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_45 RESULT=pass
3245 23:40:03.294274 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_45 RESULT=pass>
3246 23:40:03.295111 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_45 RESULT=pass
3248 23:40:03.347101 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_45 RESULT=pass>
3249 23:40:03.347963 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_45 RESULT=pass
3251 23:40:03.399302 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_45 RESULT=pass>
3252 23:40:03.400146 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_45 RESULT=pass
3254 23:40:03.455085 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_45 RESULT=pass>
3255 23:40:03.455938 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_45 RESULT=pass
3257 23:40:03.505968 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_45 RESULT=pass>
3258 23:40:03.506909 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_45 RESULT=pass
3260 23:40:03.551558 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_44 RESULT=pass>
3261 23:40:03.552749 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_44 RESULT=pass
3263 23:40:03.601153 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_44 RESULT=pass>
3264 23:40:03.602101 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_44 RESULT=pass
3266 23:40:03.654893 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_44 RESULT=pass>
3267 23:40:03.655807 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_44 RESULT=pass
3269 23:40:03.702212 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_44 RESULT=pass>
3270 23:40:03.703123 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_44 RESULT=pass
3272 23:40:03.748021 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_44 RESULT=pass>
3273 23:40:03.748920 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_44 RESULT=pass
3275 23:40:03.799898 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_44 RESULT=pass>
3276 23:40:03.800818 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_44 RESULT=pass
3278 23:40:03.851630 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_44 RESULT=pass>
3279 23:40:03.852506 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_44 RESULT=pass
3281 23:40:03.902549 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_43 RESULT=pass>
3282 23:40:03.903529 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_43 RESULT=pass
3284 23:40:03.956836 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_43 RESULT=pass>
3285 23:40:03.957730 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_43 RESULT=pass
3287 23:40:04.002763 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_43 RESULT=pass>
3288 23:40:04.003343 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_43 RESULT=pass
3290 23:40:04.048579 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_43 RESULT=pass>
3291 23:40:04.049183 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_43 RESULT=pass
3293 23:40:04.096296 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_43 RESULT=pass>
3294 23:40:04.097184 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_43 RESULT=pass
3296 23:40:04.142537 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_43 RESULT=pass>
3297 23:40:04.143424 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_43 RESULT=pass
3299 23:40:04.191226 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_43 RESULT=pass>
3300 23:40:04.192097 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_43 RESULT=pass
3302 23:40:04.234822 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_42 RESULT=pass>
3303 23:40:04.235628 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_42 RESULT=pass
3305 23:40:04.283289 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_42 RESULT=pass>
3306 23:40:04.284141 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_42 RESULT=pass
3308 23:40:04.329292 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_42 RESULT=pass>
3309 23:40:04.330142 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_42 RESULT=pass
3311 23:40:04.377245 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_42 RESULT=pass>
3312 23:40:04.378087 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_42 RESULT=pass
3314 23:40:04.445589 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_42 RESULT=pass>
3315 23:40:04.446476 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_42 RESULT=pass
3317 23:40:04.501997 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_42 RESULT=pass>
3318 23:40:04.502975 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_42 RESULT=pass
3320 23:40:04.570877 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_42 RESULT=pass>
3321 23:40:04.571791 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_42 RESULT=pass
3323 23:40:04.628955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_41 RESULT=pass>
3324 23:40:04.629835 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_41 RESULT=pass
3326 23:40:04.677116 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_41 RESULT=pass>
3327 23:40:04.678043 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_41 RESULT=pass
3329 23:40:04.737753 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_41 RESULT=pass>
3330 23:40:04.738666 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_41 RESULT=pass
3332 23:40:04.795514 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_41 RESULT=pass>
3333 23:40:04.796610 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_41 RESULT=pass
3335 23:40:04.859574 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_41 RESULT=pass>
3336 23:40:04.860476 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_41 RESULT=pass
3338 23:40:04.931787 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_41 RESULT=pass>
3339 23:40:04.932917 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_41 RESULT=pass
3341 23:40:04.991681 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_41 RESULT=pass>
3342 23:40:04.992613 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_41 RESULT=pass
3344 23:40:05.047219 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_40 RESULT=pass>
3345 23:40:05.048095 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_40 RESULT=pass
3347 23:40:05.106307 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_40 RESULT=pass>
3348 23:40:05.107112 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_40 RESULT=pass
3350 23:40:05.157901 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_40 RESULT=pass>
3351 23:40:05.158778 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_40 RESULT=pass
3353 23:40:05.219649 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_40 RESULT=pass>
3354 23:40:05.220324 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_40 RESULT=pass
3356 23:40:05.274307 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_40 RESULT=pass>
3357 23:40:05.275218 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_40 RESULT=pass
3359 23:40:05.326726 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_40 RESULT=pass>
3360 23:40:05.327710 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_40 RESULT=pass
3362 23:40:05.387495 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_40 RESULT=pass>
3363 23:40:05.388532 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_40 RESULT=pass
3365 23:40:05.445639 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_39 RESULT=pass>
3366 23:40:05.446531 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_39 RESULT=pass
3368 23:40:05.539156 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_39 RESULT=pass>
3369 23:40:05.540275 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_39 RESULT=pass
3371 23:40:05.607791 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_39 RESULT=pass>
3372 23:40:05.608523 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_39 RESULT=pass
3374 23:40:05.661552 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_39 RESULT=pass>
3375 23:40:05.662265 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_39 RESULT=pass
3377 23:40:05.725410 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_39 RESULT=pass>
3378 23:40:05.726135 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_39 RESULT=pass
3380 23:40:05.794359 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_39 RESULT=pass>
3381 23:40:05.795335 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_39 RESULT=pass
3383 23:40:05.861679 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_39 RESULT=pass>
3384 23:40:05.862649 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_39 RESULT=pass
3386 23:40:05.926234 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_38 RESULT=pass>
3387 23:40:05.926972 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_38 RESULT=pass
3389 23:40:05.993149 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_38 RESULT=pass>
3390 23:40:05.993830 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_38 RESULT=pass
3392 23:40:06.070314 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_38 RESULT=pass>
3393 23:40:06.071280 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_38 RESULT=pass
3395 23:40:06.148904 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_38 RESULT=pass>
3396 23:40:06.149873 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_38 RESULT=pass
3398 23:40:06.213835 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_38 RESULT=pass>
3399 23:40:06.214764 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_38 RESULT=pass
3401 23:40:06.268492 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_38 RESULT=pass>
3402 23:40:06.269388 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_38 RESULT=pass
3404 23:40:06.314438 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_38 RESULT=pass>
3405 23:40:06.315313 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_38 RESULT=pass
3407 23:40:06.367597 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_37 RESULT=pass>
3408 23:40:06.368460 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_37 RESULT=pass
3410 23:40:06.426552 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_37 RESULT=pass>
3411 23:40:06.427438 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_37 RESULT=pass
3413 23:40:06.477778 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_37 RESULT=pass>
3414 23:40:06.478692 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_37 RESULT=pass
3416 23:40:06.528658 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_37 RESULT=pass>
3417 23:40:06.529530 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_37 RESULT=pass
3419 23:40:06.580739 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_37 RESULT=pass>
3420 23:40:06.581615 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_37 RESULT=pass
3422 23:40:06.630160 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_37 RESULT=pass>
3423 23:40:06.631069 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_37 RESULT=pass
3425 23:40:06.680492 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_37 RESULT=pass>
3426 23:40:06.681399 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_37 RESULT=pass
3428 23:40:06.730383 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_36 RESULT=pass>
3429 23:40:06.731277 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_36 RESULT=pass
3431 23:40:06.777279 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_36 RESULT=pass>
3432 23:40:06.778198 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_36 RESULT=pass
3434 23:40:06.824027 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_36 RESULT=pass>
3435 23:40:06.824906 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_36 RESULT=pass
3437 23:40:06.872530 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_36 RESULT=pass>
3438 23:40:06.873426 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_36 RESULT=pass
3440 23:40:06.926693 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_36 RESULT=pass>
3441 23:40:06.927580 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_36 RESULT=pass
3443 23:40:06.980177 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_36 RESULT=pass>
3444 23:40:06.981044 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_36 RESULT=pass
3446 23:40:07.034332 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_36 RESULT=pass>
3447 23:40:07.035223 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_36 RESULT=pass
3449 23:40:07.083758 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_35 RESULT=pass>
3450 23:40:07.084687 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_35 RESULT=pass
3452 23:40:07.130131 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_35 RESULT=pass>
3453 23:40:07.131006 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_35 RESULT=pass
3455 23:40:07.186183 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_35 RESULT=pass>
3456 23:40:07.187057 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_35 RESULT=pass
3458 23:40:07.238461 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_35 RESULT=pass>
3459 23:40:07.239395 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_35 RESULT=pass
3461 23:40:07.284107 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_35 RESULT=pass>
3462 23:40:07.285062 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_35 RESULT=pass
3464 23:40:07.340506 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_35 RESULT=pass>
3465 23:40:07.341508 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_35 RESULT=pass
3467 23:40:07.394511 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_35 RESULT=pass>
3468 23:40:07.395482 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_35 RESULT=pass
3470 23:40:07.437748 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_34 RESULT=pass>
3471 23:40:07.439190 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_34 RESULT=pass
3473 23:40:07.490240 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_34 RESULT=pass>
3474 23:40:07.491103 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_34 RESULT=pass
3476 23:40:07.537837 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_34 RESULT=pass>
3477 23:40:07.538710 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_34 RESULT=pass
3479 23:40:07.590191 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_34 RESULT=pass>
3480 23:40:07.591182 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_34 RESULT=pass
3482 23:40:07.641450 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_34 RESULT=pass>
3483 23:40:07.642323 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_34 RESULT=pass
3485 23:40:07.697843 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_34 RESULT=pass>
3486 23:40:07.698705 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_34 RESULT=pass
3488 23:40:07.749509 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_34 RESULT=pass>
3489 23:40:07.750388 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_34 RESULT=pass
3491 23:40:07.800498 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_33 RESULT=pass>
3492 23:40:07.801341 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_33 RESULT=pass
3494 23:40:07.853362 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_33 RESULT=pass>
3495 23:40:07.854411 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_33 RESULT=pass
3497 23:40:07.901870 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_33 RESULT=pass>
3498 23:40:07.902866 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_33 RESULT=pass
3500 23:40:07.950336 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_33 RESULT=pass>
3501 23:40:07.951252 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_33 RESULT=pass
3503 23:40:07.995724 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_33 RESULT=pass>
3504 23:40:07.996731 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_33 RESULT=pass
3506 23:40:08.049153 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_33 RESULT=pass>
3507 23:40:08.050121 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_33 RESULT=pass
3509 23:40:08.101658 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_33 RESULT=pass>
3510 23:40:08.102634 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_33 RESULT=pass
3512 23:40:08.157185 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_32 RESULT=pass>
3513 23:40:08.158111 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_32 RESULT=pass
3515 23:40:08.201741 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_32 RESULT=pass>
3516 23:40:08.202694 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_32 RESULT=pass
3518 23:40:08.247756 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_32 RESULT=pass>
3519 23:40:08.248770 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_32 RESULT=pass
3521 23:40:08.295342 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_32 RESULT=pass>
3522 23:40:08.296246 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_32 RESULT=pass
3524 23:40:08.352714 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_32 RESULT=pass>
3525 23:40:08.353680 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_32 RESULT=pass
3527 23:40:08.407147 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_32 RESULT=pass>
3528 23:40:08.408321 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_32 RESULT=pass
3530 23:40:08.454424 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_32 RESULT=pass>
3531 23:40:08.455336 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_32 RESULT=pass
3533 23:40:08.501078 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_31 RESULT=pass>
3534 23:40:08.501956 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_31 RESULT=pass
3536 23:40:08.556700 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_31 RESULT=pass>
3537 23:40:08.557678 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_31 RESULT=pass
3539 23:40:08.611839 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_31 RESULT=pass>
3540 23:40:08.612796 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_31 RESULT=pass
3542 23:40:08.663335 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_31 RESULT=pass>
3543 23:40:08.664225 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_31 RESULT=pass
3545 23:40:08.724184 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_31 RESULT=pass>
3546 23:40:08.725079 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_31 RESULT=pass
3548 23:40:08.775814 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_31 RESULT=pass>
3549 23:40:08.776711 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_31 RESULT=pass
3551 23:40:08.828397 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_31 RESULT=pass>
3552 23:40:08.829453 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_31 RESULT=pass
3554 23:40:08.877434 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_30 RESULT=pass>
3555 23:40:08.878417 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_30 RESULT=pass
3557 23:40:08.935866 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_30 RESULT=pass>
3558 23:40:08.937015 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_30 RESULT=pass
3560 23:40:08.988120 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_30 RESULT=pass>
3561 23:40:08.989185 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_30 RESULT=pass
3563 23:40:09.045294 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_30 RESULT=pass>
3564 23:40:09.046212 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_30 RESULT=pass
3566 23:40:09.098598 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_30 RESULT=pass>
3567 23:40:09.099584 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_30 RESULT=pass
3569 23:40:09.152451 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_30 RESULT=pass>
3570 23:40:09.153374 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_30 RESULT=pass
3572 23:40:09.198877 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_30 RESULT=pass>
3573 23:40:09.199875 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_30 RESULT=pass
3575 23:40:09.251304 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_29 RESULT=pass>
3576 23:40:09.252228 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_29 RESULT=pass
3578 23:40:09.299284 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_29 RESULT=pass>
3579 23:40:09.300242 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_29 RESULT=pass
3581 23:40:09.353496 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_29 RESULT=pass>
3582 23:40:09.354428 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_29 RESULT=pass
3584 23:40:09.406020 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_29 RESULT=pass>
3585 23:40:09.406936 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_29 RESULT=pass
3587 23:40:09.462859 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_29 RESULT=pass>
3588 23:40:09.463757 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_29 RESULT=pass
3590 23:40:09.516332 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_29 RESULT=pass>
3591 23:40:09.517167 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_29 RESULT=pass
3593 23:40:09.565605 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_29 RESULT=pass>
3594 23:40:09.566512 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_29 RESULT=pass
3596 23:40:09.753804 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_28 RESULT=pass>
3597 23:40:09.754729 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_28 RESULT=pass
3599 23:40:09.806210 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_28 RESULT=pass>
3600 23:40:09.807109 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_28 RESULT=pass
3602 23:40:09.855280 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_28 RESULT=pass>
3603 23:40:09.856368 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_28 RESULT=pass
3605 23:40:09.900450 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_28 RESULT=pass>
3606 23:40:09.901307 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_28 RESULT=pass
3608 23:40:09.952562 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_28 RESULT=pass>
3609 23:40:09.953437 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_28 RESULT=pass
3611 23:40:09.998568 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_28 RESULT=pass>
3612 23:40:09.999431 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_28 RESULT=pass
3614 23:40:10.047833 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_28 RESULT=pass>
3615 23:40:10.048746 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_28 RESULT=pass
3617 23:40:10.095885 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_27 RESULT=pass>
3618 23:40:10.096777 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_27 RESULT=pass
3620 23:40:10.144970 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_27 RESULT=pass>
3621 23:40:10.145869 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_27 RESULT=pass
3623 23:40:10.205396 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_27 RESULT=pass>
3624 23:40:10.206298 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_27 RESULT=pass
3626 23:40:10.250377 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_27 RESULT=pass>
3627 23:40:10.251217 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_27 RESULT=pass
3629 23:40:10.307419 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_27 RESULT=pass>
3630 23:40:10.308326 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_27 RESULT=pass
3632 23:40:10.363251 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_27 RESULT=pass>
3633 23:40:10.364099 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_27 RESULT=pass
3635 23:40:10.412872 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_27 RESULT=pass>
3636 23:40:10.413766 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_27 RESULT=pass
3638 23:40:10.465383 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_26 RESULT=pass>
3639 23:40:10.466275 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_26 RESULT=pass
3641 23:40:10.520278 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_26 RESULT=pass>
3642 23:40:10.521267 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_26 RESULT=pass
3644 23:40:10.576861 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_26 RESULT=skip>
3645 23:40:10.577726 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_26 RESULT=skip
3647 23:40:10.630755 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_26 RESULT=skip>
3648 23:40:10.631681 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_26 RESULT=skip
3650 23:40:10.681173 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_26 RESULT=skip>
3651 23:40:10.682009 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_26 RESULT=skip
3653 23:40:10.726911 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_26 RESULT=pass>
3654 23:40:10.727738 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_26 RESULT=pass
3656 23:40:10.785786 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_26 RESULT=pass>
3657 23:40:10.786639 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_26 RESULT=pass
3659 23:40:10.836466 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_25 RESULT=pass>
3660 23:40:10.837356 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_25 RESULT=pass
3662 23:40:10.888153 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_25 RESULT=pass>
3663 23:40:10.889098 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_25 RESULT=pass
3665 23:40:10.941914 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_25 RESULT=pass>
3666 23:40:10.942792 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_25 RESULT=pass
3668 23:40:10.995147 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_25 RESULT=skip>
3669 23:40:10.996070 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_25 RESULT=skip
3671 23:40:11.053296 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_25 RESULT=skip>
3672 23:40:11.054173 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_25 RESULT=skip
3674 23:40:11.102718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_25 RESULT=pass>
3675 23:40:11.103531 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_25 RESULT=pass
3677 23:40:11.156861 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_25 RESULT=pass>
3678 23:40:11.157720 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_25 RESULT=pass
3680 23:40:11.214230 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_24 RESULT=pass>
3681 23:40:11.215100 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_24 RESULT=pass
3683 23:40:11.267917 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_24 RESULT=pass>
3684 23:40:11.268855 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_24 RESULT=pass
3686 23:40:11.328424 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_24 RESULT=skip>
3687 23:40:11.329245 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_24 RESULT=skip
3689 23:40:11.375142 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_24 RESULT=skip>
3690 23:40:11.376049 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_24 RESULT=skip
3692 23:40:11.434491 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_24 RESULT=skip>
3693 23:40:11.435322 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_24 RESULT=skip
3695 23:40:11.477997 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_24 RESULT=pass>
3696 23:40:11.478840 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_24 RESULT=pass
3698 23:40:11.534211 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_24 RESULT=pass>
3699 23:40:11.535037 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_24 RESULT=pass
3701 23:40:11.579692 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_23 RESULT=pass>
3702 23:40:11.580530 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_23 RESULT=pass
3704 23:40:11.630197 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_23 RESULT=pass>
3705 23:40:11.630978 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_23 RESULT=pass
3707 23:40:11.686597 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_23 RESULT=skip>
3708 23:40:11.687497 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_23 RESULT=skip
3710 23:40:11.745194 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_23 RESULT=skip>
3711 23:40:11.746030 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_23 RESULT=skip
3713 23:40:11.804614 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_23 RESULT=skip>
3714 23:40:11.805472 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_23 RESULT=skip
3716 23:40:11.859735 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_23 RESULT=pass>
3717 23:40:11.860623 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_23 RESULT=pass
3719 23:40:11.921168 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_23 RESULT=pass>
3720 23:40:11.922060 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_23 RESULT=pass
3722 23:40:11.965971 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_22 RESULT=pass>
3723 23:40:11.966777 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_22 RESULT=pass
3725 23:40:12.012913 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_22 RESULT=pass>
3726 23:40:12.013772 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_22 RESULT=pass
3728 23:40:12.070773 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_22 RESULT=pass>
3729 23:40:12.071580 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_22 RESULT=pass
3731 23:40:12.123685 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_22 RESULT=pass>
3732 23:40:12.124491 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_22 RESULT=pass
3734 23:40:12.176144 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_22 RESULT=pass>
3735 23:40:12.176933 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_22 RESULT=pass
3737 23:40:12.233242 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_22 RESULT=pass>
3738 23:40:12.234014 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_22 RESULT=pass
3740 23:40:12.290747 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_22 RESULT=pass>
3741 23:40:12.291552 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_22 RESULT=pass
3743 23:40:12.340883 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_21 RESULT=pass>
3744 23:40:12.341674 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_21 RESULT=pass
3746 23:40:12.390662 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_21 RESULT=pass>
3747 23:40:12.391442 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_21 RESULT=pass
3749 23:40:12.448758 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_21 RESULT=pass>
3750 23:40:12.449579 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_21 RESULT=pass
3752 23:40:12.500111 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_21 RESULT=pass>
3753 23:40:12.500927 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_21 RESULT=pass
3755 23:40:12.551858 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_21 RESULT=pass>
3756 23:40:12.552736 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_21 RESULT=pass
3758 23:40:12.602646 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_21 RESULT=pass>
3759 23:40:12.603490 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_21 RESULT=pass
3761 23:40:12.660305 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_21 RESULT=pass>
3762 23:40:12.661134 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_21 RESULT=pass
3764 23:40:12.710708 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_20 RESULT=pass>
3765 23:40:12.711490 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_20 RESULT=pass
3767 23:40:12.754378 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_20 RESULT=pass>
3768 23:40:12.755189 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_20 RESULT=pass
3770 23:40:12.802874 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_20 RESULT=pass>
3771 23:40:12.803657 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_20 RESULT=pass
3773 23:40:12.846419 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_20 RESULT=pass>
3774 23:40:12.847478 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_20 RESULT=pass
3776 23:40:12.898522 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_20 RESULT=pass>
3777 23:40:12.899319 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_20 RESULT=pass
3779 23:40:12.945115 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_20 RESULT=pass>
3780 23:40:12.945923 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_20 RESULT=pass
3782 23:40:12.999752 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_20 RESULT=pass>
3783 23:40:13.000641 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_20 RESULT=pass
3785 23:40:13.056768 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_19 RESULT=pass>
3786 23:40:13.057557 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_19 RESULT=pass
3788 23:40:13.102706 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_19 RESULT=pass>
3789 23:40:13.103514 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_19 RESULT=pass
3791 23:40:13.156398 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_19 RESULT=pass>
3792 23:40:13.157175 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_19 RESULT=pass
3794 23:40:13.206459 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_19 RESULT=pass>
3795 23:40:13.207257 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_19 RESULT=pass
3797 23:40:13.260292 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_19 RESULT=pass>
3798 23:40:13.261090 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_19 RESULT=pass
3800 23:40:13.310930 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_19 RESULT=pass>
3801 23:40:13.311696 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_19 RESULT=pass
3803 23:40:13.362122 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_19 RESULT=pass>
3804 23:40:13.362907 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_19 RESULT=pass
3806 23:40:13.406180 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_18 RESULT=pass>
3807 23:40:13.406929 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_18 RESULT=pass
3809 23:40:13.463794 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_18 RESULT=pass>
3810 23:40:13.464607 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_18 RESULT=pass
3812 23:40:13.515665 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_18 RESULT=pass>
3813 23:40:13.516492 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_18 RESULT=pass
3815 23:40:13.559974 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_18 RESULT=pass>
3816 23:40:13.560739 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_18 RESULT=pass
3818 23:40:13.609511 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_18 RESULT=pass>
3819 23:40:13.610302 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_18 RESULT=pass
3821 23:40:13.659077 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_18 RESULT=pass>
3822 23:40:13.659830 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_18 RESULT=pass
3824 23:40:13.710353 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_18 RESULT=pass>
3825 23:40:13.711095 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_18 RESULT=pass
3827 23:40:13.768900 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_17 RESULT=pass>
3828 23:40:13.769592 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_17 RESULT=pass
3830 23:40:13.821221 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_17 RESULT=pass>
3831 23:40:13.821982 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_17 RESULT=pass
3833 23:40:13.868104 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_17 RESULT=pass>
3834 23:40:13.868895 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_17 RESULT=pass
3836 23:40:13.920477 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_17 RESULT=pass>
3837 23:40:13.921224 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_17 RESULT=pass
3839 23:40:13.971145 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_17 RESULT=pass>
3840 23:40:13.971836 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_17 RESULT=pass
3842 23:40:14.018820 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_17 RESULT=pass>
3843 23:40:14.019549 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_17 RESULT=pass
3845 23:40:14.070093 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_17 RESULT=pass>
3846 23:40:14.070970 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_17 RESULT=pass
3848 23:40:14.119870 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_16 RESULT=pass>
3849 23:40:14.120740 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_16 RESULT=pass
3851 23:40:14.164609 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_16 RESULT=pass>
3852 23:40:14.165461 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_16 RESULT=pass
3854 23:40:14.209968 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_16 RESULT=pass>
3855 23:40:14.210891 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_16 RESULT=pass
3857 23:40:14.266517 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_16 RESULT=pass>
3858 23:40:14.267458 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_16 RESULT=pass
3860 23:40:14.325658 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_16 RESULT=pass>
3861 23:40:14.326503 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_16 RESULT=pass
3863 23:40:14.374367 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_16 RESULT=pass>
3864 23:40:14.375219 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_16 RESULT=pass
3866 23:40:14.420962 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_16 RESULT=pass>
3867 23:40:14.421983 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_16 RESULT=pass
3869 23:40:14.468779 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_15 RESULT=pass>
3870 23:40:14.469695 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_15 RESULT=pass
3872 23:40:14.519212 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_15 RESULT=pass>
3873 23:40:14.520088 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_15 RESULT=pass
3875 23:40:14.566753 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_15 RESULT=pass>
3876 23:40:14.567801 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_15 RESULT=pass
3878 23:40:14.611707 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_15 RESULT=pass>
3879 23:40:14.612586 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_15 RESULT=pass
3881 23:40:14.669456 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_15 RESULT=pass>
3882 23:40:14.670315 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_15 RESULT=pass
3884 23:40:14.713603 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_15 RESULT=pass>
3885 23:40:14.714453 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_15 RESULT=pass
3887 23:40:14.772111 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_15 RESULT=pass>
3888 23:40:14.772970 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_15 RESULT=pass
3890 23:40:14.821690 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_14 RESULT=pass>
3891 23:40:14.822533 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_14 RESULT=pass
3893 23:40:14.875775 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_14 RESULT=pass>
3894 23:40:14.876691 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_14 RESULT=pass
3896 23:40:14.939231 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_14 RESULT=pass>
3897 23:40:14.940117 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_14 RESULT=pass
3899 23:40:14.985401 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_14 RESULT=pass>
3900 23:40:14.986254 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_14 RESULT=pass
3902 23:40:15.039282 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_14 RESULT=pass>
3903 23:40:15.040130 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_14 RESULT=pass
3905 23:40:15.096391 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_14 RESULT=pass>
3906 23:40:15.097246 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_14 RESULT=pass
3908 23:40:15.152726 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_14 RESULT=pass>
3909 23:40:15.153565 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_14 RESULT=pass
3911 23:40:15.206051 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_13 RESULT=pass>
3912 23:40:15.206891 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_13 RESULT=pass
3914 23:40:15.257970 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_13 RESULT=pass>
3915 23:40:15.258836 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_13 RESULT=pass
3917 23:40:15.304708 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_13 RESULT=pass>
3918 23:40:15.305549 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_13 RESULT=pass
3920 23:40:15.349004 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_13 RESULT=pass>
3921 23:40:15.349835 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_13 RESULT=pass
3923 23:40:15.401197 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_13 RESULT=pass>
3924 23:40:15.402152 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_13 RESULT=pass
3926 23:40:15.456908 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_13 RESULT=pass>
3927 23:40:15.457755 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_13 RESULT=pass
3929 23:40:15.502910 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_13 RESULT=pass>
3930 23:40:15.503737 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_13 RESULT=pass
3932 23:40:15.554652 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_12 RESULT=pass>
3933 23:40:15.555790 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_12 RESULT=pass
3935 23:40:15.609414 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_12 RESULT=pass>
3936 23:40:15.610267 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_12 RESULT=pass
3938 23:40:15.658510 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_12 RESULT=pass>
3939 23:40:15.659371 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_12 RESULT=pass
3941 23:40:15.710867 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_12 RESULT=pass>
3942 23:40:15.711708 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_12 RESULT=pass
3944 23:40:15.765654 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_12 RESULT=pass>
3945 23:40:15.766495 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_12 RESULT=pass
3947 23:40:15.817381 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_12 RESULT=pass>
3948 23:40:15.818242 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_12 RESULT=pass
3950 23:40:15.873669 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_12 RESULT=pass>
3951 23:40:15.874512 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_12 RESULT=pass
3953 23:40:15.922873 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_11 RESULT=pass>
3954 23:40:15.923726 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_11 RESULT=pass
3956 23:40:15.973849 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_11 RESULT=pass>
3957 23:40:15.974702 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_11 RESULT=pass
3959 23:40:16.026475 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_11 RESULT=pass>
3960 23:40:16.027290 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_11 RESULT=pass
3962 23:40:16.079282 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_11 RESULT=pass>
3963 23:40:16.080277 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_11 RESULT=pass
3965 23:40:16.128452 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_11 RESULT=pass>
3966 23:40:16.129277 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_11 RESULT=pass
3968 23:40:16.188636 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_11 RESULT=pass>
3969 23:40:16.189470 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_11 RESULT=pass
3971 23:40:16.240343 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_11 RESULT=pass>
3972 23:40:16.241168 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_11 RESULT=pass
3974 23:40:16.286905 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_10 RESULT=pass>
3975 23:40:16.287739 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_10 RESULT=pass
3977 23:40:16.340667 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_10 RESULT=pass>
3978 23:40:16.341479 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_10 RESULT=pass
3980 23:40:16.382242 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_10 RESULT=pass>
3981 23:40:16.383065 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_10 RESULT=pass
3983 23:40:16.442197 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_10 RESULT=pass>
3984 23:40:16.443036 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_10 RESULT=pass
3986 23:40:16.489435 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_10 RESULT=pass>
3987 23:40:16.490260 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_10 RESULT=pass
3989 23:40:16.542270 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_10 RESULT=pass>
3990 23:40:16.543069 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_10 RESULT=pass
3992 23:40:16.603356 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_10 RESULT=pass>
3993 23:40:16.604179 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_10 RESULT=pass
3995 23:40:16.659066 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_9 RESULT=pass>
3996 23:40:16.659875 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_9 RESULT=pass
3998 23:40:16.709873 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_9 RESULT=pass>
3999 23:40:16.710699 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_9 RESULT=pass
4001 23:40:16.769788 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_9 RESULT=pass>
4002 23:40:16.770619 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_9 RESULT=pass
4004 23:40:16.815802 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_9 RESULT=pass>
4005 23:40:16.816664 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_9 RESULT=pass
4007 23:40:16.870604 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_9 RESULT=pass>
4008 23:40:16.871441 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_9 RESULT=pass
4010 23:40:16.921045 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_9 RESULT=pass>
4011 23:40:16.921943 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_9 RESULT=pass
4013 23:40:16.980452 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_9 RESULT=pass>
4014 23:40:16.981286 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_9 RESULT=pass
4016 23:40:17.031941 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_8 RESULT=pass>
4017 23:40:17.032815 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_8 RESULT=pass
4019 23:40:17.079568 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_8 RESULT=pass>
4020 23:40:17.080419 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_8 RESULT=pass
4022 23:40:17.125810 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_8 RESULT=pass>
4023 23:40:17.126628 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_8 RESULT=pass
4025 23:40:17.173052 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_8 RESULT=pass>
4026 23:40:17.173878 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_8 RESULT=pass
4028 23:40:17.226035 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_8 RESULT=pass>
4029 23:40:17.226847 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_8 RESULT=pass
4031 23:40:17.279133 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_8 RESULT=pass>
4032 23:40:17.279957 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_8 RESULT=pass
4034 23:40:17.334000 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_8 RESULT=pass>
4035 23:40:17.334801 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_8 RESULT=pass
4037 23:40:17.388090 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_7 RESULT=pass>
4038 23:40:17.388902 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_7 RESULT=pass
4040 23:40:17.432762 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_7 RESULT=pass>
4041 23:40:17.433598 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_7 RESULT=pass
4043 23:40:17.481354 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_7 RESULT=pass>
4044 23:40:17.482176 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_7 RESULT=pass
4046 23:40:17.527184 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_7 RESULT=pass>
4047 23:40:17.528082 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_7 RESULT=pass
4049 23:40:17.574193 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_7 RESULT=pass>
4050 23:40:17.575019 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_7 RESULT=pass
4052 23:40:17.632748 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_7 RESULT=pass>
4053 23:40:17.633570 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_7 RESULT=pass
4055 23:40:17.692254 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_7 RESULT=pass>
4056 23:40:17.693075 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_7 RESULT=pass
4058 23:40:17.737361 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_6 RESULT=pass>
4059 23:40:17.738149 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_6 RESULT=pass
4061 23:40:17.787026 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_6 RESULT=pass>
4062 23:40:17.787853 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_6 RESULT=pass
4064 23:40:17.833264 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_6 RESULT=pass>
4065 23:40:17.834100 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_6 RESULT=pass
4067 23:40:17.888749 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_6 RESULT=pass>
4068 23:40:17.889652 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_6 RESULT=pass
4070 23:40:17.934716 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_6 RESULT=pass>
4071 23:40:17.935537 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_6 RESULT=pass
4073 23:40:17.981102 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_6 RESULT=pass>
4074 23:40:17.981923 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_6 RESULT=pass
4076 23:40:18.028473 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_6 RESULT=pass>
4077 23:40:18.029339 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_6 RESULT=pass
4079 23:40:18.074510 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_5 RESULT=pass>
4080 23:40:18.075328 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_5 RESULT=pass
4082 23:40:18.120901 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_5 RESULT=pass>
4083 23:40:18.121790 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_5 RESULT=pass
4085 23:40:18.168226 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_5 RESULT=pass>
4086 23:40:18.169039 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_5 RESULT=pass
4088 23:40:18.223199 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_5 RESULT=pass>
4089 23:40:18.224097 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_5 RESULT=pass
4091 23:40:18.276568 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_5 RESULT=pass>
4092 23:40:18.277398 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_5 RESULT=pass
4094 23:40:18.327710 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_5 RESULT=pass>
4095 23:40:18.328708 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_5 RESULT=pass
4097 23:40:18.381960 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_5 RESULT=pass>
4098 23:40:18.382923 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_5 RESULT=pass
4100 23:40:18.431816 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_4 RESULT=pass>
4101 23:40:18.432725 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_4 RESULT=pass
4103 23:40:18.483374 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_4 RESULT=pass>
4104 23:40:18.484285 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_4 RESULT=pass
4106 23:40:18.529644 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_4 RESULT=pass>
4107 23:40:18.530508 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_4 RESULT=pass
4109 23:40:18.583911 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_4 RESULT=pass>
4110 23:40:18.584843 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_4 RESULT=pass
4112 23:40:18.633962 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_4 RESULT=pass>
4113 23:40:18.634915 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_4 RESULT=pass
4115 23:40:18.689164 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_4 RESULT=pass>
4116 23:40:18.690130 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_4 RESULT=pass
4118 23:40:18.738277 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_4 RESULT=pass>
4119 23:40:18.739131 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_4 RESULT=pass
4121 23:40:18.781803 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_3 RESULT=pass>
4122 23:40:18.782695 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_3 RESULT=pass
4124 23:40:18.827574 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_3 RESULT=pass>
4125 23:40:18.828501 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_3 RESULT=pass
4127 23:40:18.888639 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_3 RESULT=pass>
4128 23:40:18.889526 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_3 RESULT=pass
4130 23:40:18.931619 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_3 RESULT=pass>
4131 23:40:18.932515 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_3 RESULT=pass
4133 23:40:18.988787 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_3 RESULT=pass>
4134 23:40:18.989699 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_3 RESULT=pass
4136 23:40:19.045858 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_3 RESULT=pass>
4137 23:40:19.046709 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_3 RESULT=pass
4139 23:40:19.095743 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_3 RESULT=pass>
4140 23:40:19.096664 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_3 RESULT=pass
4142 23:40:19.149650 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_2 RESULT=pass>
4143 23:40:19.150540 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_2 RESULT=pass
4145 23:40:19.202080 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_2 RESULT=pass>
4146 23:40:19.203045 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_2 RESULT=pass
4148 23:40:19.253358 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_2 RESULT=pass>
4149 23:40:19.254196 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_2 RESULT=pass
4151 23:40:19.301369 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_2 RESULT=pass>
4152 23:40:19.302259 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_2 RESULT=pass
4154 23:40:19.353218 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_2 RESULT=pass>
4155 23:40:19.354141 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_2 RESULT=pass
4157 23:40:19.398215 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_2 RESULT=pass>
4158 23:40:19.399202 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_2 RESULT=pass
4160 23:40:19.454613 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_2 RESULT=pass>
4161 23:40:19.455494 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_2 RESULT=pass
4163 23:40:19.508275 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_1 RESULT=pass>
4164 23:40:19.509300 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_1 RESULT=pass
4166 23:40:19.553432 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_1 RESULT=pass>
4167 23:40:19.554295 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_1 RESULT=pass
4169 23:40:19.606032 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_1 RESULT=pass>
4170 23:40:19.606934 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_1 RESULT=pass
4172 23:40:19.661860 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_1 RESULT=pass>
4173 23:40:19.662767 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_1 RESULT=pass
4175 23:40:19.711098 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_1 RESULT=pass>
4176 23:40:19.711975 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_1 RESULT=pass
4178 23:40:19.763320 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_1 RESULT=pass>
4179 23:40:19.764180 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_1 RESULT=pass
4181 23:40:19.816206 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_1 RESULT=pass>
4182 23:40:19.817092 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_1 RESULT=pass
4184 23:40:19.869756 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_0 RESULT=pass>
4185 23:40:19.870654 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_0 RESULT=pass
4187 23:40:19.914718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_0 RESULT=pass>
4188 23:40:19.915596 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_0 RESULT=pass
4190 23:40:19.967883 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_0 RESULT=pass>
4191 23:40:19.968759 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_0 RESULT=pass
4193 23:40:20.025249 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_0 RESULT=pass>
4194 23:40:20.026118 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_0 RESULT=pass
4196 23:40:20.069418 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_0 RESULT=pass>
4197 23:40:20.070251 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_0 RESULT=pass
4199 23:40:20.119831 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_0 RESULT=pass>
4200 23:40:20.120718 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_0 RESULT=pass
4202 23:40:20.171594 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_0 RESULT=pass>
4203 23:40:20.172477 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_0 RESULT=pass
4205 23:40:20.212280 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test RESULT=pass
4207 23:40:20.215178 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test RESULT=pass>
4208 23:40:20.263103 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_5_0_CAPTURE RESULT=skip>
4209 23:40:20.263917 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_5_0_CAPTURE RESULT=skip
4211 23:40:20.309487 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_5_0_CAPTURE RESULT=skip>
4212 23:40:20.310335 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_5_0_CAPTURE RESULT=skip
4214 23:40:20.361861 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_5_0_CAPTURE RESULT=skip>
4215 23:40:20.362725 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_5_0_CAPTURE RESULT=skip
4217 23:40:20.414527 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_5_0_CAPTURE RESULT=skip>
4218 23:40:20.415540 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_5_0_CAPTURE RESULT=skip
4220 23:40:20.459806 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_5_0_CAPTURE RESULT=skip>
4221 23:40:20.460718 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_5_0_CAPTURE RESULT=skip
4223 23:40:20.521385 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_5_0_CAPTURE RESULT=skip>
4224 23:40:20.522296 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_5_0_CAPTURE RESULT=skip
4226 23:40:20.567484 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_5_0_CAPTURE RESULT=skip>
4227 23:40:20.568356 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_5_0_CAPTURE RESULT=skip
4229 23:40:20.618705 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_4_0_CAPTURE RESULT=skip>
4230 23:40:20.619567 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_4_0_CAPTURE RESULT=skip
4232 23:40:20.665380 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_4_0_CAPTURE RESULT=skip>
4233 23:40:20.666269 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_4_0_CAPTURE RESULT=skip
4235 23:40:20.717416 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_4_0_CAPTURE RESULT=skip>
4236 23:40:20.718335 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_4_0_CAPTURE RESULT=skip
4238 23:40:20.764786 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_4_0_CAPTURE RESULT=skip>
4239 23:40:20.765658 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_4_0_CAPTURE RESULT=skip
4241 23:40:20.816112 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_4_0_CAPTURE RESULT=skip>
4242 23:40:20.817016 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_4_0_CAPTURE RESULT=skip
4244 23:40:20.867690 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_4_0_CAPTURE RESULT=skip>
4245 23:40:20.868578 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_4_0_CAPTURE RESULT=skip
4247 23:40:20.919724 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_4_0_CAPTURE RESULT=skip>
4248 23:40:20.920749 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_4_0_CAPTURE RESULT=skip
4250 23:40:20.972670 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_3_0_CAPTURE RESULT=skip>
4251 23:40:20.973540 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_3_0_CAPTURE RESULT=skip
4253 23:40:21.016604 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_3_0_CAPTURE RESULT=skip>
4254 23:40:21.017510 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_3_0_CAPTURE RESULT=skip
4256 23:40:21.069892 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_3_0_CAPTURE RESULT=skip>
4257 23:40:21.070803 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_3_0_CAPTURE RESULT=skip
4259 23:40:21.117681 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_3_0_CAPTURE RESULT=skip>
4260 23:40:21.118602 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_3_0_CAPTURE RESULT=skip
4262 23:40:21.172729 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_3_0_CAPTURE RESULT=skip>
4263 23:40:21.173599 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_3_0_CAPTURE RESULT=skip
4265 23:40:21.219800 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_3_0_CAPTURE RESULT=skip>
4266 23:40:21.220854 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_3_0_CAPTURE RESULT=skip
4268 23:40:21.271051 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_3_0_CAPTURE RESULT=skip>
4269 23:40:21.271898 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_3_0_CAPTURE RESULT=skip
4271 23:40:21.323451 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_2_0_PLAYBACK RESULT=skip>
4272 23:40:21.324411 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_2_0_PLAYBACK RESULT=skip
4274 23:40:21.374912 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_2_0_PLAYBACK RESULT=skip>
4275 23:40:21.375841 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_2_0_PLAYBACK RESULT=skip
4277 23:40:21.430411 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_2_0_PLAYBACK RESULT=skip>
4278 23:40:21.431088 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_2_0_PLAYBACK RESULT=skip
4280 23:40:21.486935 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_2_0_PLAYBACK RESULT=skip>
4281 23:40:21.487882 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_2_0_PLAYBACK RESULT=skip
4283 23:40:21.531635 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_2_0_PLAYBACK RESULT=skip>
4284 23:40:21.532609 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_2_0_PLAYBACK RESULT=skip
4286 23:40:21.584246 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_2_0_PLAYBACK RESULT=skip>
4287 23:40:21.585189 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_2_0_PLAYBACK RESULT=skip
4289 23:40:21.635539 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_2_0_PLAYBACK RESULT=skip>
4290 23:40:21.636494 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_2_0_PLAYBACK RESULT=skip
4292 23:40:21.696101 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_1_0_PLAYBACK RESULT=skip>
4293 23:40:21.696985 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_1_0_PLAYBACK RESULT=skip
4295 23:40:21.746674 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_1_0_PLAYBACK RESULT=skip>
4296 23:40:21.747560 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_1_0_PLAYBACK RESULT=skip
4298 23:40:21.804004 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_1_0_PLAYBACK RESULT=skip>
4299 23:40:21.804943 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_1_0_PLAYBACK RESULT=skip
4301 23:40:21.849026 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_1_0_PLAYBACK RESULT=skip>
4302 23:40:21.849914 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_1_0_PLAYBACK RESULT=skip
4304 23:40:21.897429 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_1_0_PLAYBACK RESULT=skip>
4305 23:40:21.898291 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_1_0_PLAYBACK RESULT=skip
4307 23:40:21.944286 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_1_0_PLAYBACK RESULT=skip>
4308 23:40:21.945201 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_1_0_PLAYBACK RESULT=skip
4310 23:40:21.990253 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_1_0_PLAYBACK RESULT=skip>
4311 23:40:21.991083 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_1_0_PLAYBACK RESULT=skip
4313 23:40:22.036051 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_0_0_PLAYBACK RESULT=skip>
4314 23:40:22.036965 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_0_0_PLAYBACK RESULT=skip
4316 23:40:22.095417 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_0_0_PLAYBACK RESULT=skip>
4317 23:40:22.096318 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_0_0_PLAYBACK RESULT=skip
4319 23:40:22.147261 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_0_0_PLAYBACK RESULT=skip>
4320 23:40:22.148110 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_0_0_PLAYBACK RESULT=skip
4322 23:40:22.195304 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_0_0_PLAYBACK RESULT=skip>
4323 23:40:22.196154 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_0_0_PLAYBACK RESULT=skip
4325 23:40:22.239285 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_0_0_PLAYBACK RESULT=skip>
4326 23:40:22.240175 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_0_0_PLAYBACK RESULT=skip
4328 23:40:22.288407 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_0_0_PLAYBACK RESULT=skip>
4329 23:40:22.289294 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_0_0_PLAYBACK RESULT=skip
4331 23:40:22.343574 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_0_0_PLAYBACK RESULT=skip>
4332 23:40:22.344510 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_0_0_PLAYBACK RESULT=skip
4334 23:40:22.388804 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test RESULT=pass>
4335 23:40:22.389634 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test RESULT=pass
4337 23:40:22.452589 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_playback_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip>
4338 23:40:22.453408 Received signal: <TESTCASE> TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_playback_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip
4340 23:40:22.497954 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_capture_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip>
4341 23:40:22.498791 Received signal: <TESTCASE> TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_capture_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip
4343 23:40:22.544302 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_ni_capture_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip>
4344 23:40:22.545194 Received signal: <TESTCASE> TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_ni_capture_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip
4346 23:40:22.590874 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_ni_playback_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip>
4347 23:40:22.591731 Received signal: <TESTCASE> TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_ni_playback_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip
4349 23:40:22.646827 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_reset_ioctl_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip>
4350 23:40:22.647653 Received signal: <TESTCASE> TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_reset_ioctl_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip
4352 23:40:22.693476 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_test-pcmtest-driver RESULT=pass>
4353 23:40:22.694370 Received signal: <TESTCASE> TEST_CASE_ID=alsa_test-pcmtest-driver RESULT=pass
4355 23:40:22.740701 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_utimer-test_global_wrong_timers_test RESULT=pass>
4356 23:40:22.741577 Received signal: <TESTCASE> TEST_CASE_ID=alsa_utimer-test_global_wrong_timers_test RESULT=pass
4358 23:40:22.789051 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_utimer-test_timer_f_utimer RESULT=fail>
4359 23:40:22.789917 Received signal: <TESTCASE> TEST_CASE_ID=alsa_utimer-test_timer_f_utimer RESULT=fail
4361 23:40:22.831844 Received signal: <TESTCASE> TEST_CASE_ID=alsa_utimer-test RESULT=fail
4363 23:40:22.837076 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_utimer-test RESULT=fail>
4364 23:40:22.837592 + set +x
4365 23:40:22.843058 <LAVA_SIGNAL_ENDRUN 1_kselftest-alsa 943265_1.6.2.4.5>
4366 23:40:22.843540 <LAVA_TEST_RUNNER EXIT>
4367 23:40:22.844232 Received signal: <ENDRUN> 1_kselftest-alsa 943265_1.6.2.4.5
4368 23:40:22.844717 Ending use of test pattern.
4369 23:40:22.845151 Ending test lava.1_kselftest-alsa (943265_1.6.2.4.5), duration 41.43
4371 23:40:22.846807 ok: lava_test_shell seems to have completed
4372 23:40:22.871820 alsa_mixer-test: pass
alsa_mixer-test_event_missing_LCALTA_0: pass
alsa_mixer-test_event_missing_LCALTA_1: pass
alsa_mixer-test_event_missing_LCALTA_10: pass
alsa_mixer-test_event_missing_LCALTA_11: pass
alsa_mixer-test_event_missing_LCALTA_12: pass
alsa_mixer-test_event_missing_LCALTA_13: pass
alsa_mixer-test_event_missing_LCALTA_14: pass
alsa_mixer-test_event_missing_LCALTA_15: pass
alsa_mixer-test_event_missing_LCALTA_16: pass
alsa_mixer-test_event_missing_LCALTA_17: pass
alsa_mixer-test_event_missing_LCALTA_18: pass
alsa_mixer-test_event_missing_LCALTA_19: pass
alsa_mixer-test_event_missing_LCALTA_2: pass
alsa_mixer-test_event_missing_LCALTA_20: pass
alsa_mixer-test_event_missing_LCALTA_21: pass
alsa_mixer-test_event_missing_LCALTA_22: pass
alsa_mixer-test_event_missing_LCALTA_23: pass
alsa_mixer-test_event_missing_LCALTA_24: pass
alsa_mixer-test_event_missing_LCALTA_25: pass
alsa_mixer-test_event_missing_LCALTA_26: pass
alsa_mixer-test_event_missing_LCALTA_27: pass
alsa_mixer-test_event_missing_LCALTA_28: pass
alsa_mixer-test_event_missing_LCALTA_29: pass
alsa_mixer-test_event_missing_LCALTA_3: pass
alsa_mixer-test_event_missing_LCALTA_30: pass
alsa_mixer-test_event_missing_LCALTA_31: pass
alsa_mixer-test_event_missing_LCALTA_32: pass
alsa_mixer-test_event_missing_LCALTA_33: pass
alsa_mixer-test_event_missing_LCALTA_34: pass
alsa_mixer-test_event_missing_LCALTA_35: pass
alsa_mixer-test_event_missing_LCALTA_36: pass
alsa_mixer-test_event_missing_LCALTA_37: pass
alsa_mixer-test_event_missing_LCALTA_38: pass
alsa_mixer-test_event_missing_LCALTA_39: pass
alsa_mixer-test_event_missing_LCALTA_4: pass
alsa_mixer-test_event_missing_LCALTA_40: pass
alsa_mixer-test_event_missing_LCALTA_41: pass
alsa_mixer-test_event_missing_LCALTA_42: pass
alsa_mixer-test_event_missing_LCALTA_43: pass
alsa_mixer-test_event_missing_LCALTA_44: pass
alsa_mixer-test_event_missing_LCALTA_45: pass
alsa_mixer-test_event_missing_LCALTA_46: pass
alsa_mixer-test_event_missing_LCALTA_47: pass
alsa_mixer-test_event_missing_LCALTA_48: pass
alsa_mixer-test_event_missing_LCALTA_49: pass
alsa_mixer-test_event_missing_LCALTA_5: pass
alsa_mixer-test_event_missing_LCALTA_50: pass
alsa_mixer-test_event_missing_LCALTA_51: pass
alsa_mixer-test_event_missing_LCALTA_52: pass
alsa_mixer-test_event_missing_LCALTA_53: pass
alsa_mixer-test_event_missing_LCALTA_54: pass
alsa_mixer-test_event_missing_LCALTA_55: pass
alsa_mixer-test_event_missing_LCALTA_56: pass
alsa_mixer-test_event_missing_LCALTA_57: pass
alsa_mixer-test_event_missing_LCALTA_58: pass
alsa_mixer-test_event_missing_LCALTA_59: pass
alsa_mixer-test_event_missing_LCALTA_6: pass
alsa_mixer-test_event_missing_LCALTA_60: pass
alsa_mixer-test_event_missing_LCALTA_7: pass
alsa_mixer-test_event_missing_LCALTA_8: pass
alsa_mixer-test_event_missing_LCALTA_9: pass
alsa_mixer-test_event_spurious_LCALTA_0: pass
alsa_mixer-test_event_spurious_LCALTA_1: pass
alsa_mixer-test_event_spurious_LCALTA_10: pass
alsa_mixer-test_event_spurious_LCALTA_11: pass
alsa_mixer-test_event_spurious_LCALTA_12: pass
alsa_mixer-test_event_spurious_LCALTA_13: pass
alsa_mixer-test_event_spurious_LCALTA_14: pass
alsa_mixer-test_event_spurious_LCALTA_15: pass
alsa_mixer-test_event_spurious_LCALTA_16: pass
alsa_mixer-test_event_spurious_LCALTA_17: pass
alsa_mixer-test_event_spurious_LCALTA_18: pass
alsa_mixer-test_event_spurious_LCALTA_19: pass
alsa_mixer-test_event_spurious_LCALTA_2: pass
alsa_mixer-test_event_spurious_LCALTA_20: pass
alsa_mixer-test_event_spurious_LCALTA_21: pass
alsa_mixer-test_event_spurious_LCALTA_22: pass
alsa_mixer-test_event_spurious_LCALTA_23: pass
alsa_mixer-test_event_spurious_LCALTA_24: pass
alsa_mixer-test_event_spurious_LCALTA_25: pass
alsa_mixer-test_event_spurious_LCALTA_26: pass
alsa_mixer-test_event_spurious_LCALTA_27: pass
alsa_mixer-test_event_spurious_LCALTA_28: pass
alsa_mixer-test_event_spurious_LCALTA_29: pass
alsa_mixer-test_event_spurious_LCALTA_3: pass
alsa_mixer-test_event_spurious_LCALTA_30: pass
alsa_mixer-test_event_spurious_LCALTA_31: pass
alsa_mixer-test_event_spurious_LCALTA_32: pass
alsa_mixer-test_event_spurious_LCALTA_33: pass
alsa_mixer-test_event_spurious_LCALTA_34: pass
alsa_mixer-test_event_spurious_LCALTA_35: pass
alsa_mixer-test_event_spurious_LCALTA_36: pass
alsa_mixer-test_event_spurious_LCALTA_37: pass
alsa_mixer-test_event_spurious_LCALTA_38: pass
alsa_mixer-test_event_spurious_LCALTA_39: pass
alsa_mixer-test_event_spurious_LCALTA_4: pass
alsa_mixer-test_event_spurious_LCALTA_40: pass
alsa_mixer-test_event_spurious_LCALTA_41: pass
alsa_mixer-test_event_spurious_LCALTA_42: pass
alsa_mixer-test_event_spurious_LCALTA_43: pass
alsa_mixer-test_event_spurious_LCALTA_44: pass
alsa_mixer-test_event_spurious_LCALTA_45: pass
alsa_mixer-test_event_spurious_LCALTA_46: pass
alsa_mixer-test_event_spurious_LCALTA_47: pass
alsa_mixer-test_event_spurious_LCALTA_48: pass
alsa_mixer-test_event_spurious_LCALTA_49: pass
alsa_mixer-test_event_spurious_LCALTA_5: pass
alsa_mixer-test_event_spurious_LCALTA_50: pass
alsa_mixer-test_event_spurious_LCALTA_51: pass
alsa_mixer-test_event_spurious_LCALTA_52: pass
alsa_mixer-test_event_spurious_LCALTA_53: pass
alsa_mixer-test_event_spurious_LCALTA_54: pass
alsa_mixer-test_event_spurious_LCALTA_55: pass
alsa_mixer-test_event_spurious_LCALTA_56: pass
alsa_mixer-test_event_spurious_LCALTA_57: pass
alsa_mixer-test_event_spurious_LCALTA_58: pass
alsa_mixer-test_event_spurious_LCALTA_59: pass
alsa_mixer-test_event_spurious_LCALTA_6: pass
alsa_mixer-test_event_spurious_LCALTA_60: pass
alsa_mixer-test_event_spurious_LCALTA_7: pass
alsa_mixer-test_event_spurious_LCALTA_8: pass
alsa_mixer-test_event_spurious_LCALTA_9: pass
alsa_mixer-test_get_value_LCALTA_0: pass
alsa_mixer-test_get_value_LCALTA_1: pass
alsa_mixer-test_get_value_LCALTA_10: pass
alsa_mixer-test_get_value_LCALTA_11: pass
alsa_mixer-test_get_value_LCALTA_12: pass
alsa_mixer-test_get_value_LCALTA_13: pass
alsa_mixer-test_get_value_LCALTA_14: pass
alsa_mixer-test_get_value_LCALTA_15: pass
alsa_mixer-test_get_value_LCALTA_16: pass
alsa_mixer-test_get_value_LCALTA_17: pass
alsa_mixer-test_get_value_LCALTA_18: pass
alsa_mixer-test_get_value_LCALTA_19: pass
alsa_mixer-test_get_value_LCALTA_2: pass
alsa_mixer-test_get_value_LCALTA_20: pass
alsa_mixer-test_get_value_LCALTA_21: pass
alsa_mixer-test_get_value_LCALTA_22: pass
alsa_mixer-test_get_value_LCALTA_23: pass
alsa_mixer-test_get_value_LCALTA_24: pass
alsa_mixer-test_get_value_LCALTA_25: pass
alsa_mixer-test_get_value_LCALTA_26: pass
alsa_mixer-test_get_value_LCALTA_27: pass
alsa_mixer-test_get_value_LCALTA_28: pass
alsa_mixer-test_get_value_LCALTA_29: pass
alsa_mixer-test_get_value_LCALTA_3: pass
alsa_mixer-test_get_value_LCALTA_30: pass
alsa_mixer-test_get_value_LCALTA_31: pass
alsa_mixer-test_get_value_LCALTA_32: pass
alsa_mixer-test_get_value_LCALTA_33: pass
alsa_mixer-test_get_value_LCALTA_34: pass
alsa_mixer-test_get_value_LCALTA_35: pass
alsa_mixer-test_get_value_LCALTA_36: pass
alsa_mixer-test_get_value_LCALTA_37: pass
alsa_mixer-test_get_value_LCALTA_38: pass
alsa_mixer-test_get_value_LCALTA_39: pass
alsa_mixer-test_get_value_LCALTA_4: pass
alsa_mixer-test_get_value_LCALTA_40: pass
alsa_mixer-test_get_value_LCALTA_41: pass
alsa_mixer-test_get_value_LCALTA_42: pass
alsa_mixer-test_get_value_LCALTA_43: pass
alsa_mixer-test_get_value_LCALTA_44: pass
alsa_mixer-test_get_value_LCALTA_45: pass
alsa_mixer-test_get_value_LCALTA_46: pass
alsa_mixer-test_get_value_LCALTA_47: pass
alsa_mixer-test_get_value_LCALTA_48: pass
alsa_mixer-test_get_value_LCALTA_49: pass
alsa_mixer-test_get_value_LCALTA_5: pass
alsa_mixer-test_get_value_LCALTA_50: pass
alsa_mixer-test_get_value_LCALTA_51: pass
alsa_mixer-test_get_value_LCALTA_52: pass
alsa_mixer-test_get_value_LCALTA_53: pass
alsa_mixer-test_get_value_LCALTA_54: pass
alsa_mixer-test_get_value_LCALTA_55: pass
alsa_mixer-test_get_value_LCALTA_56: pass
alsa_mixer-test_get_value_LCALTA_57: pass
alsa_mixer-test_get_value_LCALTA_58: pass
alsa_mixer-test_get_value_LCALTA_59: pass
alsa_mixer-test_get_value_LCALTA_6: pass
alsa_mixer-test_get_value_LCALTA_60: pass
alsa_mixer-test_get_value_LCALTA_7: pass
alsa_mixer-test_get_value_LCALTA_8: pass
alsa_mixer-test_get_value_LCALTA_9: pass
alsa_mixer-test_name_LCALTA_0: pass
alsa_mixer-test_name_LCALTA_1: pass
alsa_mixer-test_name_LCALTA_10: pass
alsa_mixer-test_name_LCALTA_11: pass
alsa_mixer-test_name_LCALTA_12: pass
alsa_mixer-test_name_LCALTA_13: pass
alsa_mixer-test_name_LCALTA_14: pass
alsa_mixer-test_name_LCALTA_15: pass
alsa_mixer-test_name_LCALTA_16: pass
alsa_mixer-test_name_LCALTA_17: pass
alsa_mixer-test_name_LCALTA_18: pass
alsa_mixer-test_name_LCALTA_19: pass
alsa_mixer-test_name_LCALTA_2: pass
alsa_mixer-test_name_LCALTA_20: pass
alsa_mixer-test_name_LCALTA_21: pass
alsa_mixer-test_name_LCALTA_22: pass
alsa_mixer-test_name_LCALTA_23: pass
alsa_mixer-test_name_LCALTA_24: pass
alsa_mixer-test_name_LCALTA_25: pass
alsa_mixer-test_name_LCALTA_26: pass
alsa_mixer-test_name_LCALTA_27: pass
alsa_mixer-test_name_LCALTA_28: pass
alsa_mixer-test_name_LCALTA_29: pass
alsa_mixer-test_name_LCALTA_3: pass
alsa_mixer-test_name_LCALTA_30: pass
alsa_mixer-test_name_LCALTA_31: pass
alsa_mixer-test_name_LCALTA_32: pass
alsa_mixer-test_name_LCALTA_33: pass
alsa_mixer-test_name_LCALTA_34: pass
alsa_mixer-test_name_LCALTA_35: pass
alsa_mixer-test_name_LCALTA_36: pass
alsa_mixer-test_name_LCALTA_37: pass
alsa_mixer-test_name_LCALTA_38: pass
alsa_mixer-test_name_LCALTA_39: pass
alsa_mixer-test_name_LCALTA_4: pass
alsa_mixer-test_name_LCALTA_40: pass
alsa_mixer-test_name_LCALTA_41: pass
alsa_mixer-test_name_LCALTA_42: pass
alsa_mixer-test_name_LCALTA_43: pass
alsa_mixer-test_name_LCALTA_44: pass
alsa_mixer-test_name_LCALTA_45: pass
alsa_mixer-test_name_LCALTA_46: pass
alsa_mixer-test_name_LCALTA_47: pass
alsa_mixer-test_name_LCALTA_48: pass
alsa_mixer-test_name_LCALTA_49: pass
alsa_mixer-test_name_LCALTA_5: pass
alsa_mixer-test_name_LCALTA_50: pass
alsa_mixer-test_name_LCALTA_51: pass
alsa_mixer-test_name_LCALTA_52: pass
alsa_mixer-test_name_LCALTA_53: pass
alsa_mixer-test_name_LCALTA_54: pass
alsa_mixer-test_name_LCALTA_55: pass
alsa_mixer-test_name_LCALTA_56: pass
alsa_mixer-test_name_LCALTA_57: pass
alsa_mixer-test_name_LCALTA_58: pass
alsa_mixer-test_name_LCALTA_59: pass
alsa_mixer-test_name_LCALTA_6: pass
alsa_mixer-test_name_LCALTA_60: pass
alsa_mixer-test_name_LCALTA_7: pass
alsa_mixer-test_name_LCALTA_8: pass
alsa_mixer-test_name_LCALTA_9: pass
alsa_mixer-test_write_default_LCALTA_0: pass
alsa_mixer-test_write_default_LCALTA_1: pass
alsa_mixer-test_write_default_LCALTA_10: pass
alsa_mixer-test_write_default_LCALTA_11: pass
alsa_mixer-test_write_default_LCALTA_12: pass
alsa_mixer-test_write_default_LCALTA_13: pass
alsa_mixer-test_write_default_LCALTA_14: pass
alsa_mixer-test_write_default_LCALTA_15: pass
alsa_mixer-test_write_default_LCALTA_16: pass
alsa_mixer-test_write_default_LCALTA_17: pass
alsa_mixer-test_write_default_LCALTA_18: pass
alsa_mixer-test_write_default_LCALTA_19: pass
alsa_mixer-test_write_default_LCALTA_2: pass
alsa_mixer-test_write_default_LCALTA_20: pass
alsa_mixer-test_write_default_LCALTA_21: pass
alsa_mixer-test_write_default_LCALTA_22: pass
alsa_mixer-test_write_default_LCALTA_23: skip
alsa_mixer-test_write_default_LCALTA_24: skip
alsa_mixer-test_write_default_LCALTA_25: pass
alsa_mixer-test_write_default_LCALTA_26: skip
alsa_mixer-test_write_default_LCALTA_27: pass
alsa_mixer-test_write_default_LCALTA_28: pass
alsa_mixer-test_write_default_LCALTA_29: pass
alsa_mixer-test_write_default_LCALTA_3: pass
alsa_mixer-test_write_default_LCALTA_30: pass
alsa_mixer-test_write_default_LCALTA_31: pass
alsa_mixer-test_write_default_LCALTA_32: pass
alsa_mixer-test_write_default_LCALTA_33: pass
alsa_mixer-test_write_default_LCALTA_34: pass
alsa_mixer-test_write_default_LCALTA_35: pass
alsa_mixer-test_write_default_LCALTA_36: pass
alsa_mixer-test_write_default_LCALTA_37: pass
alsa_mixer-test_write_default_LCALTA_38: pass
alsa_mixer-test_write_default_LCALTA_39: pass
alsa_mixer-test_write_default_LCALTA_4: pass
alsa_mixer-test_write_default_LCALTA_40: pass
alsa_mixer-test_write_default_LCALTA_41: pass
alsa_mixer-test_write_default_LCALTA_42: pass
alsa_mixer-test_write_default_LCALTA_43: pass
alsa_mixer-test_write_default_LCALTA_44: pass
alsa_mixer-test_write_default_LCALTA_45: pass
alsa_mixer-test_write_default_LCALTA_46: pass
alsa_mixer-test_write_default_LCALTA_47: pass
alsa_mixer-test_write_default_LCALTA_48: pass
alsa_mixer-test_write_default_LCALTA_49: pass
alsa_mixer-test_write_default_LCALTA_5: pass
alsa_mixer-test_write_default_LCALTA_50: pass
alsa_mixer-test_write_default_LCALTA_51: pass
alsa_mixer-test_write_default_LCALTA_52: pass
alsa_mixer-test_write_default_LCALTA_53: pass
alsa_mixer-test_write_default_LCALTA_54: pass
alsa_mixer-test_write_default_LCALTA_55: pass
alsa_mixer-test_write_default_LCALTA_56: pass
alsa_mixer-test_write_default_LCALTA_57: pass
alsa_mixer-test_write_default_LCALTA_58: pass
alsa_mixer-test_write_default_LCALTA_59: pass
alsa_mixer-test_write_default_LCALTA_6: pass
alsa_mixer-test_write_default_LCALTA_60: pass
alsa_mixer-test_write_default_LCALTA_7: pass
alsa_mixer-test_write_default_LCALTA_8: pass
alsa_mixer-test_write_default_LCALTA_9: pass
alsa_mixer-test_write_invalid_LCALTA_0: pass
alsa_mixer-test_write_invalid_LCALTA_1: pass
alsa_mixer-test_write_invalid_LCALTA_10: pass
alsa_mixer-test_write_invalid_LCALTA_11: pass
alsa_mixer-test_write_invalid_LCALTA_12: pass
alsa_mixer-test_write_invalid_LCALTA_13: pass
alsa_mixer-test_write_invalid_LCALTA_14: pass
alsa_mixer-test_write_invalid_LCALTA_15: pass
alsa_mixer-test_write_invalid_LCALTA_16: pass
alsa_mixer-test_write_invalid_LCALTA_17: pass
alsa_mixer-test_write_invalid_LCALTA_18: pass
alsa_mixer-test_write_invalid_LCALTA_19: pass
alsa_mixer-test_write_invalid_LCALTA_2: pass
alsa_mixer-test_write_invalid_LCALTA_20: pass
alsa_mixer-test_write_invalid_LCALTA_21: pass
alsa_mixer-test_write_invalid_LCALTA_22: pass
alsa_mixer-test_write_invalid_LCALTA_23: skip
alsa_mixer-test_write_invalid_LCALTA_24: skip
alsa_mixer-test_write_invalid_LCALTA_25: skip
alsa_mixer-test_write_invalid_LCALTA_26: skip
alsa_mixer-test_write_invalid_LCALTA_27: pass
alsa_mixer-test_write_invalid_LCALTA_28: pass
alsa_mixer-test_write_invalid_LCALTA_29: pass
alsa_mixer-test_write_invalid_LCALTA_3: pass
alsa_mixer-test_write_invalid_LCALTA_30: pass
alsa_mixer-test_write_invalid_LCALTA_31: pass
alsa_mixer-test_write_invalid_LCALTA_32: pass
alsa_mixer-test_write_invalid_LCALTA_33: pass
alsa_mixer-test_write_invalid_LCALTA_34: pass
alsa_mixer-test_write_invalid_LCALTA_35: pass
alsa_mixer-test_write_invalid_LCALTA_36: pass
alsa_mixer-test_write_invalid_LCALTA_37: pass
alsa_mixer-test_write_invalid_LCALTA_38: pass
alsa_mixer-test_write_invalid_LCALTA_39: pass
alsa_mixer-test_write_invalid_LCALTA_4: pass
alsa_mixer-test_write_invalid_LCALTA_40: pass
alsa_mixer-test_write_invalid_LCALTA_41: pass
alsa_mixer-test_write_invalid_LCALTA_42: pass
alsa_mixer-test_write_invalid_LCALTA_43: pass
alsa_mixer-test_write_invalid_LCALTA_44: pass
alsa_mixer-test_write_invalid_LCALTA_45: pass
alsa_mixer-test_write_invalid_LCALTA_46: pass
alsa_mixer-test_write_invalid_LCALTA_47: pass
alsa_mixer-test_write_invalid_LCALTA_48: pass
alsa_mixer-test_write_invalid_LCALTA_49: pass
alsa_mixer-test_write_invalid_LCALTA_5: pass
alsa_mixer-test_write_invalid_LCALTA_50: pass
alsa_mixer-test_write_invalid_LCALTA_51: pass
alsa_mixer-test_write_invalid_LCALTA_52: pass
alsa_mixer-test_write_invalid_LCALTA_53: pass
alsa_mixer-test_write_invalid_LCALTA_54: pass
alsa_mixer-test_write_invalid_LCALTA_55: pass
alsa_mixer-test_write_invalid_LCALTA_56: pass
alsa_mixer-test_write_invalid_LCALTA_57: pass
alsa_mixer-test_write_invalid_LCALTA_58: pass
alsa_mixer-test_write_invalid_LCALTA_59: pass
alsa_mixer-test_write_invalid_LCALTA_6: pass
alsa_mixer-test_write_invalid_LCALTA_60: pass
alsa_mixer-test_write_invalid_LCALTA_7: pass
alsa_mixer-test_write_invalid_LCALTA_8: pass
alsa_mixer-test_write_invalid_LCALTA_9: pass
alsa_mixer-test_write_valid_LCALTA_0: pass
alsa_mixer-test_write_valid_LCALTA_1: pass
alsa_mixer-test_write_valid_LCALTA_10: pass
alsa_mixer-test_write_valid_LCALTA_11: pass
alsa_mixer-test_write_valid_LCALTA_12: pass
alsa_mixer-test_write_valid_LCALTA_13: pass
alsa_mixer-test_write_valid_LCALTA_14: pass
alsa_mixer-test_write_valid_LCALTA_15: pass
alsa_mixer-test_write_valid_LCALTA_16: pass
alsa_mixer-test_write_valid_LCALTA_17: pass
alsa_mixer-test_write_valid_LCALTA_18: pass
alsa_mixer-test_write_valid_LCALTA_19: pass
alsa_mixer-test_write_valid_LCALTA_2: pass
alsa_mixer-test_write_valid_LCALTA_20: pass
alsa_mixer-test_write_valid_LCALTA_21: pass
alsa_mixer-test_write_valid_LCALTA_22: pass
alsa_mixer-test_write_valid_LCALTA_23: skip
alsa_mixer-test_write_valid_LCALTA_24: skip
alsa_mixer-test_write_valid_LCALTA_25: skip
alsa_mixer-test_write_valid_LCALTA_26: skip
alsa_mixer-test_write_valid_LCALTA_27: pass
alsa_mixer-test_write_valid_LCALTA_28: pass
alsa_mixer-test_write_valid_LCALTA_29: pass
alsa_mixer-test_write_valid_LCALTA_3: pass
alsa_mixer-test_write_valid_LCALTA_30: pass
alsa_mixer-test_write_valid_LCALTA_31: pass
alsa_mixer-test_write_valid_LCALTA_32: pass
alsa_mixer-test_write_valid_LCALTA_33: pass
alsa_mixer-test_write_valid_LCALTA_34: pass
alsa_mixer-test_write_valid_LCALTA_35: pass
alsa_mixer-test_write_valid_LCALTA_36: pass
alsa_mixer-test_write_valid_LCALTA_37: pass
alsa_mixer-test_write_valid_LCALTA_38: pass
alsa_mixer-test_write_valid_LCALTA_39: pass
alsa_mixer-test_write_valid_LCALTA_4: pass
alsa_mixer-test_write_valid_LCALTA_40: pass
alsa_mixer-test_write_valid_LCALTA_41: pass
alsa_mixer-test_write_valid_LCALTA_42: pass
alsa_mixer-test_write_valid_LCALTA_43: pass
alsa_mixer-test_write_valid_LCALTA_44: pass
alsa_mixer-test_write_valid_LCALTA_45: pass
alsa_mixer-test_write_valid_LCALTA_46: pass
alsa_mixer-test_write_valid_LCALTA_47: pass
alsa_mixer-test_write_valid_LCALTA_48: pass
alsa_mixer-test_write_valid_LCALTA_49: pass
alsa_mixer-test_write_valid_LCALTA_5: pass
alsa_mixer-test_write_valid_LCALTA_50: pass
alsa_mixer-test_write_valid_LCALTA_51: pass
alsa_mixer-test_write_valid_LCALTA_52: pass
alsa_mixer-test_write_valid_LCALTA_53: pass
alsa_mixer-test_write_valid_LCALTA_54: pass
alsa_mixer-test_write_valid_LCALTA_55: pass
alsa_mixer-test_write_valid_LCALTA_56: pass
alsa_mixer-test_write_valid_LCALTA_57: pass
alsa_mixer-test_write_valid_LCALTA_58: pass
alsa_mixer-test_write_valid_LCALTA_59: pass
alsa_mixer-test_write_valid_LCALTA_6: pass
alsa_mixer-test_write_valid_LCALTA_60: pass
alsa_mixer-test_write_valid_LCALTA_7: pass
alsa_mixer-test_write_valid_LCALTA_8: pass
alsa_mixer-test_write_valid_LCALTA_9: pass
alsa_pcm-test: pass
alsa_pcm-test_default_time1_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time1_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time1_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time1_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time1_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time1_LCALTA_5_0_CAPTURE: skip
alsa_pcm-test_default_time2_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time2_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time2_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time2_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time2_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time2_LCALTA_5_0_CAPTURE: skip
alsa_pcm-test_default_time3_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time3_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time3_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time3_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time3_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time3_LCALTA_5_0_CAPTURE: skip
alsa_pcm-test_default_time4_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time4_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time4_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time4_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time4_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time4_LCALTA_5_0_CAPTURE: skip
alsa_pcm-test_default_time5_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time5_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time5_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time5_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time5_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time5_LCALTA_5_0_CAPTURE: skip
alsa_pcm-test_default_time6_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time6_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time6_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time6_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time6_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time6_LCALTA_5_0_CAPTURE: skip
alsa_pcm-test_default_time7_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time7_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time7_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time7_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time7_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time7_LCALTA_5_0_CAPTURE: skip
alsa_test-pcmtest-driver: pass
alsa_test-pcmtest-driver_pcmtest_capture_Can_t_read_patterns_Probably_module_isn_t_loaded: skip
alsa_test-pcmtest-driver_pcmtest_ni_capture_Can_t_read_patterns_Probably_module_isn_t_loaded: skip
alsa_test-pcmtest-driver_pcmtest_ni_playback_Can_t_read_patterns_Probably_module_isn_t_loaded: skip
alsa_test-pcmtest-driver_pcmtest_playback_Can_t_read_patterns_Probably_module_isn_t_loaded: skip
alsa_test-pcmtest-driver_pcmtest_reset_ioctl_Can_t_read_patterns_Probably_module_isn_t_loaded: skip
alsa_utimer-test: fail
alsa_utimer-test_global_wrong_timers_test: pass
alsa_utimer-test_timer_f_utimer: fail
shardfile-alsa: pass
4373 23:40:22.873768 end: 3.1 lava-test-shell (duration 00:00:42) [common]
4374 23:40:22.874391 end: 3 lava-test-retry (duration 00:00:42) [common]
4375 23:40:22.874998 start: 4 finalize (timeout 00:06:09) [common]
4376 23:40:22.875616 start: 4.1 power-off (timeout 00:00:30) [common]
4377 23:40:22.876684 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
4378 23:40:22.910755 >> OK - accepted request
4379 23:40:22.912948 Returned 0 in 0 seconds
4380 23:40:23.014138 end: 4.1 power-off (duration 00:00:00) [common]
4382 23:40:23.015933 start: 4.2 read-feedback (timeout 00:06:09) [common]
4383 23:40:23.017186 Listened to connection for namespace 'common' for up to 1s
4384 23:40:24.017269 Finalising connection for namespace 'common'
4385 23:40:24.017978 Disconnecting from shell: Finalise
4386 23:40:24.018510 / #
4387 23:40:24.119481 end: 4.2 read-feedback (duration 00:00:01) [common]
4388 23:40:24.120270 end: 4 finalize (duration 00:00:01) [common]
4389 23:40:24.121053 Cleaning after the job
4390 23:40:24.121724 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/943265/tftp-deploy-ni9yk04u/ramdisk
4391 23:40:24.137411 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/943265/tftp-deploy-ni9yk04u/kernel
4392 23:40:24.181498 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/943265/tftp-deploy-ni9yk04u/dtb
4393 23:40:24.182486 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/943265/tftp-deploy-ni9yk04u/nfsrootfs
4394 23:40:24.350760 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/943265/tftp-deploy-ni9yk04u/modules
4395 23:40:24.371862 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/943265
4396 23:40:28.568967 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/943265
4397 23:40:28.569566 Job finished correctly