Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 23:26:11.331775 lava-dispatcher, installed at version: 2024.01
2 23:26:11.332557 start: 0 validate
3 23:26:11.333022 Start time: 2024-11-05 23:26:11.332992+00:00 (UTC)
4 23:26:11.333571 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 23:26:11.334104 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-gst-fluster%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 23:26:11.371663 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 23:26:11.372221 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fpending-fixes%2Fv6.12-rc6-237-g47f01a19a6ee2%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 23:26:11.402210 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 23:26:11.402834 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fpending-fixes%2Fv6.12-rc6-237-g47f01a19a6ee2%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 23:26:11.435049 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 23:26:11.435555 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-gst-fluster%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 23:26:11.469232 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 23:26:11.469771 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fpending-fixes%2Fv6.12-rc6-237-g47f01a19a6ee2%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
14 23:26:11.508712 validate duration: 0.18
16 23:26:11.509598 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 23:26:11.509945 start: 1.1 download-retry (timeout 00:10:00) [common]
18 23:26:11.510292 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 23:26:11.510981 Not decompressing ramdisk as can be used compressed.
20 23:26:11.511459 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-gst-fluster/20240313.0/arm64/initrd.cpio.gz
21 23:26:11.511769 saving as /var/lib/lava/dispatcher/tmp/943216/tftp-deploy-0b9nxwej/ramdisk/initrd.cpio.gz
22 23:26:11.512086 total size: 5628140 (5 MB)
23 23:26:11.549642 progress 0 % (0 MB)
24 23:26:11.553835 progress 5 % (0 MB)
25 23:26:11.558227 progress 10 % (0 MB)
26 23:26:11.562034 progress 15 % (0 MB)
27 23:26:11.566261 progress 20 % (1 MB)
28 23:26:11.570063 progress 25 % (1 MB)
29 23:26:11.574289 progress 30 % (1 MB)
30 23:26:11.578487 progress 35 % (1 MB)
31 23:26:11.582198 progress 40 % (2 MB)
32 23:26:11.586288 progress 45 % (2 MB)
33 23:26:11.590092 progress 50 % (2 MB)
34 23:26:11.594220 progress 55 % (2 MB)
35 23:26:11.598399 progress 60 % (3 MB)
36 23:26:11.602078 progress 65 % (3 MB)
37 23:26:11.606233 progress 70 % (3 MB)
38 23:26:11.609899 progress 75 % (4 MB)
39 23:26:11.614090 progress 80 % (4 MB)
40 23:26:11.617776 progress 85 % (4 MB)
41 23:26:11.621824 progress 90 % (4 MB)
42 23:26:11.625771 progress 95 % (5 MB)
43 23:26:11.629088 progress 100 % (5 MB)
44 23:26:11.629747 5 MB downloaded in 0.12 s (45.63 MB/s)
45 23:26:11.630338 end: 1.1.1 http-download (duration 00:00:00) [common]
47 23:26:11.631283 end: 1.1 download-retry (duration 00:00:00) [common]
48 23:26:11.631598 start: 1.2 download-retry (timeout 00:10:00) [common]
49 23:26:11.631886 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 23:26:11.632409 downloading http://storage.kernelci.org/next/pending-fixes/v6.12-rc6-237-g47f01a19a6ee2/arm64/defconfig/gcc-12/kernel/Image
51 23:26:11.632678 saving as /var/lib/lava/dispatcher/tmp/943216/tftp-deploy-0b9nxwej/kernel/Image
52 23:26:11.632899 total size: 45715968 (43 MB)
53 23:26:11.633118 No compression specified
54 23:26:11.674514 progress 0 % (0 MB)
55 23:26:11.703312 progress 5 % (2 MB)
56 23:26:11.732009 progress 10 % (4 MB)
57 23:26:11.761043 progress 15 % (6 MB)
58 23:26:11.789700 progress 20 % (8 MB)
59 23:26:11.817661 progress 25 % (10 MB)
60 23:26:11.846729 progress 30 % (13 MB)
61 23:26:11.875261 progress 35 % (15 MB)
62 23:26:11.907605 progress 40 % (17 MB)
63 23:26:11.938304 progress 45 % (19 MB)
64 23:26:11.970241 progress 50 % (21 MB)
65 23:26:12.000109 progress 55 % (24 MB)
66 23:26:12.029571 progress 60 % (26 MB)
67 23:26:12.059134 progress 65 % (28 MB)
68 23:26:12.088822 progress 70 % (30 MB)
69 23:26:12.118027 progress 75 % (32 MB)
70 23:26:12.147853 progress 80 % (34 MB)
71 23:26:12.180429 progress 85 % (37 MB)
72 23:26:12.210212 progress 90 % (39 MB)
73 23:26:12.239747 progress 95 % (41 MB)
74 23:26:12.268481 progress 100 % (43 MB)
75 23:26:12.269097 43 MB downloaded in 0.64 s (68.53 MB/s)
76 23:26:12.269592 end: 1.2.1 http-download (duration 00:00:01) [common]
78 23:26:12.270441 end: 1.2 download-retry (duration 00:00:01) [common]
79 23:26:12.270725 start: 1.3 download-retry (timeout 00:09:59) [common]
80 23:26:12.270998 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 23:26:12.271513 downloading http://storage.kernelci.org/next/pending-fixes/v6.12-rc6-237-g47f01a19a6ee2/arm64/defconfig/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
82 23:26:12.271849 saving as /var/lib/lava/dispatcher/tmp/943216/tftp-deploy-0b9nxwej/dtb/meson-g12b-a311d-libretech-cc.dtb
83 23:26:12.272107 total size: 54703 (0 MB)
84 23:26:12.272333 No compression specified
85 23:26:12.318855 progress 59 % (0 MB)
86 23:26:12.319771 progress 100 % (0 MB)
87 23:26:12.320444 0 MB downloaded in 0.05 s (1.08 MB/s)
88 23:26:12.320997 end: 1.3.1 http-download (duration 00:00:00) [common]
90 23:26:12.321844 end: 1.3 download-retry (duration 00:00:00) [common]
91 23:26:12.322119 start: 1.4 download-retry (timeout 00:09:59) [common]
92 23:26:12.322392 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 23:26:12.323131 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-gst-fluster/20240313.0/arm64/full.rootfs.tar.xz
94 23:26:12.323454 saving as /var/lib/lava/dispatcher/tmp/943216/tftp-deploy-0b9nxwej/nfsrootfs/full.rootfs.tar
95 23:26:12.323686 total size: 474398908 (452 MB)
96 23:26:12.323916 Using unxz to decompress xz
97 23:26:12.368827 progress 0 % (0 MB)
98 23:26:13.522692 progress 5 % (22 MB)
99 23:26:14.998549 progress 10 % (45 MB)
100 23:26:15.509065 progress 15 % (67 MB)
101 23:26:16.425106 progress 20 % (90 MB)
102 23:26:16.968947 progress 25 % (113 MB)
103 23:26:17.360358 progress 30 % (135 MB)
104 23:26:18.076026 progress 35 % (158 MB)
105 23:26:18.949230 progress 40 % (181 MB)
106 23:26:19.685947 progress 45 % (203 MB)
107 23:26:20.258118 progress 50 % (226 MB)
108 23:26:20.925032 progress 55 % (248 MB)
109 23:26:22.145835 progress 60 % (271 MB)
110 23:26:23.612384 progress 65 % (294 MB)
111 23:26:25.207392 progress 70 % (316 MB)
112 23:26:28.283679 progress 75 % (339 MB)
113 23:26:30.760518 progress 80 % (361 MB)
114 23:26:33.653522 progress 85 % (384 MB)
115 23:26:36.880932 progress 90 % (407 MB)
116 23:26:40.083297 progress 95 % (429 MB)
117 23:26:43.310929 progress 100 % (452 MB)
118 23:26:43.324017 452 MB downloaded in 31.00 s (14.59 MB/s)
119 23:26:43.325002 end: 1.4.1 http-download (duration 00:00:31) [common]
121 23:26:43.326808 end: 1.4 download-retry (duration 00:00:31) [common]
122 23:26:43.327397 start: 1.5 download-retry (timeout 00:09:28) [common]
123 23:26:43.328007 start: 1.5.1 http-download (timeout 00:09:28) [common]
124 23:26:43.328886 downloading http://storage.kernelci.org/next/pending-fixes/v6.12-rc6-237-g47f01a19a6ee2/arm64/defconfig/gcc-12/modules.tar.xz
125 23:26:43.329395 saving as /var/lib/lava/dispatcher/tmp/943216/tftp-deploy-0b9nxwej/modules/modules.tar
126 23:26:43.329854 total size: 11614632 (11 MB)
127 23:26:43.330326 Using unxz to decompress xz
128 23:26:43.374977 progress 0 % (0 MB)
129 23:26:43.442125 progress 5 % (0 MB)
130 23:26:43.516442 progress 10 % (1 MB)
131 23:26:43.614957 progress 15 % (1 MB)
132 23:26:43.707344 progress 20 % (2 MB)
133 23:26:43.787752 progress 25 % (2 MB)
134 23:26:43.863474 progress 30 % (3 MB)
135 23:26:43.942149 progress 35 % (3 MB)
136 23:26:44.014659 progress 40 % (4 MB)
137 23:26:44.090732 progress 45 % (5 MB)
138 23:26:44.175938 progress 50 % (5 MB)
139 23:26:44.254024 progress 55 % (6 MB)
140 23:26:44.341228 progress 60 % (6 MB)
141 23:26:44.425583 progress 65 % (7 MB)
142 23:26:44.510202 progress 70 % (7 MB)
143 23:26:44.590740 progress 75 % (8 MB)
144 23:26:44.677536 progress 80 % (8 MB)
145 23:26:44.762723 progress 85 % (9 MB)
146 23:26:44.848217 progress 90 % (10 MB)
147 23:26:44.923148 progress 95 % (10 MB)
148 23:26:45.000851 progress 100 % (11 MB)
149 23:26:45.013409 11 MB downloaded in 1.68 s (6.58 MB/s)
150 23:26:45.014342 end: 1.5.1 http-download (duration 00:00:02) [common]
152 23:26:45.016064 end: 1.5 download-retry (duration 00:00:02) [common]
153 23:26:45.016609 start: 1.6 prepare-tftp-overlay (timeout 00:09:26) [common]
154 23:26:45.017128 start: 1.6.1 extract-nfsrootfs (timeout 00:09:26) [common]
155 23:27:00.321105 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/943216/extract-nfsrootfs-sw6ei2s2
156 23:27:00.321695 end: 1.6.1 extract-nfsrootfs (duration 00:00:15) [common]
157 23:27:00.322023 start: 1.6.2 lava-overlay (timeout 00:09:11) [common]
158 23:27:00.322734 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/943216/lava-overlay-8zdpj8ax
159 23:27:00.323285 makedir: /var/lib/lava/dispatcher/tmp/943216/lava-overlay-8zdpj8ax/lava-943216/bin
160 23:27:00.323713 makedir: /var/lib/lava/dispatcher/tmp/943216/lava-overlay-8zdpj8ax/lava-943216/tests
161 23:27:00.324142 makedir: /var/lib/lava/dispatcher/tmp/943216/lava-overlay-8zdpj8ax/lava-943216/results
162 23:27:00.324497 Creating /var/lib/lava/dispatcher/tmp/943216/lava-overlay-8zdpj8ax/lava-943216/bin/lava-add-keys
163 23:27:00.325128 Creating /var/lib/lava/dispatcher/tmp/943216/lava-overlay-8zdpj8ax/lava-943216/bin/lava-add-sources
164 23:27:00.325761 Creating /var/lib/lava/dispatcher/tmp/943216/lava-overlay-8zdpj8ax/lava-943216/bin/lava-background-process-start
165 23:27:00.326319 Creating /var/lib/lava/dispatcher/tmp/943216/lava-overlay-8zdpj8ax/lava-943216/bin/lava-background-process-stop
166 23:27:00.327363 Creating /var/lib/lava/dispatcher/tmp/943216/lava-overlay-8zdpj8ax/lava-943216/bin/lava-common-functions
167 23:27:00.327970 Creating /var/lib/lava/dispatcher/tmp/943216/lava-overlay-8zdpj8ax/lava-943216/bin/lava-echo-ipv4
168 23:27:00.329313 Creating /var/lib/lava/dispatcher/tmp/943216/lava-overlay-8zdpj8ax/lava-943216/bin/lava-install-packages
169 23:27:00.330101 Creating /var/lib/lava/dispatcher/tmp/943216/lava-overlay-8zdpj8ax/lava-943216/bin/lava-installed-packages
170 23:27:00.330603 Creating /var/lib/lava/dispatcher/tmp/943216/lava-overlay-8zdpj8ax/lava-943216/bin/lava-os-build
171 23:27:00.331105 Creating /var/lib/lava/dispatcher/tmp/943216/lava-overlay-8zdpj8ax/lava-943216/bin/lava-probe-channel
172 23:27:00.331594 Creating /var/lib/lava/dispatcher/tmp/943216/lava-overlay-8zdpj8ax/lava-943216/bin/lava-probe-ip
173 23:27:00.332181 Creating /var/lib/lava/dispatcher/tmp/943216/lava-overlay-8zdpj8ax/lava-943216/bin/lava-target-ip
174 23:27:00.332676 Creating /var/lib/lava/dispatcher/tmp/943216/lava-overlay-8zdpj8ax/lava-943216/bin/lava-target-mac
175 23:27:00.333159 Creating /var/lib/lava/dispatcher/tmp/943216/lava-overlay-8zdpj8ax/lava-943216/bin/lava-target-storage
176 23:27:00.333660 Creating /var/lib/lava/dispatcher/tmp/943216/lava-overlay-8zdpj8ax/lava-943216/bin/lava-test-case
177 23:27:00.334163 Creating /var/lib/lava/dispatcher/tmp/943216/lava-overlay-8zdpj8ax/lava-943216/bin/lava-test-event
178 23:27:00.334675 Creating /var/lib/lava/dispatcher/tmp/943216/lava-overlay-8zdpj8ax/lava-943216/bin/lava-test-feedback
179 23:27:00.335161 Creating /var/lib/lava/dispatcher/tmp/943216/lava-overlay-8zdpj8ax/lava-943216/bin/lava-test-raise
180 23:27:00.335657 Creating /var/lib/lava/dispatcher/tmp/943216/lava-overlay-8zdpj8ax/lava-943216/bin/lava-test-reference
181 23:27:00.336183 Creating /var/lib/lava/dispatcher/tmp/943216/lava-overlay-8zdpj8ax/lava-943216/bin/lava-test-runner
182 23:27:00.336697 Creating /var/lib/lava/dispatcher/tmp/943216/lava-overlay-8zdpj8ax/lava-943216/bin/lava-test-set
183 23:27:00.337184 Creating /var/lib/lava/dispatcher/tmp/943216/lava-overlay-8zdpj8ax/lava-943216/bin/lava-test-shell
184 23:27:00.337679 Updating /var/lib/lava/dispatcher/tmp/943216/lava-overlay-8zdpj8ax/lava-943216/bin/lava-install-packages (oe)
185 23:27:00.338204 Updating /var/lib/lava/dispatcher/tmp/943216/lava-overlay-8zdpj8ax/lava-943216/bin/lava-installed-packages (oe)
186 23:27:00.338645 Creating /var/lib/lava/dispatcher/tmp/943216/lava-overlay-8zdpj8ax/lava-943216/environment
187 23:27:00.339008 LAVA metadata
188 23:27:00.339263 - LAVA_JOB_ID=943216
189 23:27:00.339476 - LAVA_DISPATCHER_IP=192.168.6.2
190 23:27:00.339840 start: 1.6.2.1 ssh-authorize (timeout 00:09:11) [common]
191 23:27:00.340847 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
192 23:27:00.341160 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:11) [common]
193 23:27:00.341369 skipped lava-vland-overlay
194 23:27:00.341609 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
195 23:27:00.341860 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:11) [common]
196 23:27:00.342075 skipped lava-multinode-overlay
197 23:27:00.342313 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
198 23:27:00.342564 start: 1.6.2.4 test-definition (timeout 00:09:11) [common]
199 23:27:00.342811 Loading test definitions
200 23:27:00.343089 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:11) [common]
201 23:27:00.343308 Using /lava-943216 at stage 0
202 23:27:00.344525 uuid=943216_1.6.2.4.1 testdef=None
203 23:27:00.344833 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
204 23:27:00.345096 start: 1.6.2.4.2 test-overlay (timeout 00:09:11) [common]
205 23:27:00.346851 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
207 23:27:00.347643 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:11) [common]
208 23:27:00.349827 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
210 23:27:00.350654 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:11) [common]
211 23:27:00.352756 runner path: /var/lib/lava/dispatcher/tmp/943216/lava-overlay-8zdpj8ax/lava-943216/0/tests/0_v4l2-decoder-conformance-vp9 test_uuid 943216_1.6.2.4.1
212 23:27:00.353333 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
214 23:27:00.354086 Creating lava-test-runner.conf files
215 23:27:00.354287 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/943216/lava-overlay-8zdpj8ax/lava-943216/0 for stage 0
216 23:27:00.354626 - 0_v4l2-decoder-conformance-vp9
217 23:27:00.354964 end: 1.6.2.4 test-definition (duration 00:00:00) [common]
218 23:27:00.355231 start: 1.6.2.5 compress-overlay (timeout 00:09:11) [common]
219 23:27:00.377098 end: 1.6.2.5 compress-overlay (duration 00:00:00) [common]
220 23:27:00.377491 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:09:11) [common]
221 23:27:00.377750 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
222 23:27:00.378016 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
223 23:27:00.378279 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:11) [common]
224 23:27:01.009821 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:01) [common]
225 23:27:01.010276 start: 1.6.4 extract-modules (timeout 00:09:10) [common]
226 23:27:01.010527 extracting modules file /var/lib/lava/dispatcher/tmp/943216/tftp-deploy-0b9nxwej/modules/modules.tar to /var/lib/lava/dispatcher/tmp/943216/extract-nfsrootfs-sw6ei2s2
227 23:27:02.697384 extracting modules file /var/lib/lava/dispatcher/tmp/943216/tftp-deploy-0b9nxwej/modules/modules.tar to /var/lib/lava/dispatcher/tmp/943216/extract-overlay-ramdisk-1xhq0rkc/ramdisk
228 23:27:04.121491 end: 1.6.4 extract-modules (duration 00:00:03) [common]
229 23:27:04.122004 start: 1.6.5 apply-overlay-tftp (timeout 00:09:07) [common]
230 23:27:04.122299 [common] Applying overlay to NFS
231 23:27:04.122520 [common] Applying overlay /var/lib/lava/dispatcher/tmp/943216/compress-overlay-_fb_pkbo/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/943216/extract-nfsrootfs-sw6ei2s2
232 23:27:04.153311 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
233 23:27:04.153791 start: 1.6.6 prepare-kernel (timeout 00:09:07) [common]
234 23:27:04.154071 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:09:07) [common]
235 23:27:04.154312 Converting downloaded kernel to a uImage
236 23:27:04.154634 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/943216/tftp-deploy-0b9nxwej/kernel/Image /var/lib/lava/dispatcher/tmp/943216/tftp-deploy-0b9nxwej/kernel/uImage
237 23:27:04.699005 output: Image Name:
238 23:27:04.699536 output: Created: Tue Nov 5 23:27:04 2024
239 23:27:04.699797 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
240 23:27:04.700115 output: Data Size: 45715968 Bytes = 44644.50 KiB = 43.60 MiB
241 23:27:04.700383 output: Load Address: 01080000
242 23:27:04.700631 output: Entry Point: 01080000
243 23:27:04.700876 output:
244 23:27:04.701294 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:01) [common]
245 23:27:04.701645 end: 1.6.6 prepare-kernel (duration 00:00:01) [common]
246 23:27:04.702006 start: 1.6.7 configure-preseed-file (timeout 00:09:07) [common]
247 23:27:04.702337 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
248 23:27:04.702665 start: 1.6.8 compress-ramdisk (timeout 00:09:07) [common]
249 23:27:04.702990 Building ramdisk /var/lib/lava/dispatcher/tmp/943216/extract-overlay-ramdisk-1xhq0rkc/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/943216/extract-overlay-ramdisk-1xhq0rkc/ramdisk
250 23:27:07.223521 >> 166830 blocks
251 23:27:14.967077 Adding RAMdisk u-boot header.
252 23:27:14.967790 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/943216/extract-overlay-ramdisk-1xhq0rkc/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/943216/extract-overlay-ramdisk-1xhq0rkc/ramdisk.cpio.gz.uboot
253 23:27:15.210912 output: Image Name:
254 23:27:15.211342 output: Created: Tue Nov 5 23:27:14 2024
255 23:27:15.211555 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
256 23:27:15.211762 output: Data Size: 23434321 Bytes = 22885.08 KiB = 22.35 MiB
257 23:27:15.211965 output: Load Address: 00000000
258 23:27:15.212375 output: Entry Point: 00000000
259 23:27:15.212773 output:
260 23:27:15.213811 rename /var/lib/lava/dispatcher/tmp/943216/extract-overlay-ramdisk-1xhq0rkc/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/943216/tftp-deploy-0b9nxwej/ramdisk/ramdisk.cpio.gz.uboot
261 23:27:15.214524 end: 1.6.8 compress-ramdisk (duration 00:00:11) [common]
262 23:27:15.215068 end: 1.6 prepare-tftp-overlay (duration 00:00:30) [common]
263 23:27:15.215589 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:56) [common]
264 23:27:15.216074 No LXC device requested
265 23:27:15.216582 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
266 23:27:15.217089 start: 1.8 deploy-device-env (timeout 00:08:56) [common]
267 23:27:15.217581 end: 1.8 deploy-device-env (duration 00:00:00) [common]
268 23:27:15.217988 Checking files for TFTP limit of 4294967296 bytes.
269 23:27:15.220985 end: 1 tftp-deploy (duration 00:01:04) [common]
270 23:27:15.221657 start: 2 uboot-action (timeout 00:05:00) [common]
271 23:27:15.222237 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
272 23:27:15.222785 end: 2.1 uboot-from-media (duration 00:00:00) [common]
273 23:27:15.223335 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
274 23:27:15.223916 Using kernel file from prepare-kernel: 943216/tftp-deploy-0b9nxwej/kernel/uImage
275 23:27:15.224711 substitutions:
276 23:27:15.225165 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
277 23:27:15.225613 - {DTB_ADDR}: 0x01070000
278 23:27:15.226054 - {DTB}: 943216/tftp-deploy-0b9nxwej/dtb/meson-g12b-a311d-libretech-cc.dtb
279 23:27:15.226490 - {INITRD}: 943216/tftp-deploy-0b9nxwej/ramdisk/ramdisk.cpio.gz.uboot
280 23:27:15.226928 - {KERNEL_ADDR}: 0x01080000
281 23:27:15.227386 - {KERNEL}: 943216/tftp-deploy-0b9nxwej/kernel/uImage
282 23:27:15.227827 - {LAVA_MAC}: None
283 23:27:15.228340 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/943216/extract-nfsrootfs-sw6ei2s2
284 23:27:15.228785 - {NFS_SERVER_IP}: 192.168.6.2
285 23:27:15.229218 - {PRESEED_CONFIG}: None
286 23:27:15.229646 - {PRESEED_LOCAL}: None
287 23:27:15.230075 - {RAMDISK_ADDR}: 0x08000000
288 23:27:15.230526 - {RAMDISK}: 943216/tftp-deploy-0b9nxwej/ramdisk/ramdisk.cpio.gz.uboot
289 23:27:15.230988 - {ROOT_PART}: None
290 23:27:15.231450 - {ROOT}: None
291 23:27:15.231899 - {SERVER_IP}: 192.168.6.2
292 23:27:15.232381 - {TEE_ADDR}: 0x83000000
293 23:27:15.232846 - {TEE}: None
294 23:27:15.233291 Parsed boot commands:
295 23:27:15.233708 - setenv autoload no
296 23:27:15.234135 - setenv initrd_high 0xffffffff
297 23:27:15.234561 - setenv fdt_high 0xffffffff
298 23:27:15.234986 - dhcp
299 23:27:15.235410 - setenv serverip 192.168.6.2
300 23:27:15.235833 - tftpboot 0x01080000 943216/tftp-deploy-0b9nxwej/kernel/uImage
301 23:27:15.236296 - tftpboot 0x08000000 943216/tftp-deploy-0b9nxwej/ramdisk/ramdisk.cpio.gz.uboot
302 23:27:15.236724 - tftpboot 0x01070000 943216/tftp-deploy-0b9nxwej/dtb/meson-g12b-a311d-libretech-cc.dtb
303 23:27:15.237152 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/943216/extract-nfsrootfs-sw6ei2s2,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
304 23:27:15.237594 - bootm 0x01080000 0x08000000 0x01070000
305 23:27:15.238152 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
307 23:27:15.239783 start: 2.3 connect-device (timeout 00:05:00) [common]
308 23:27:15.240292 [common] connect-device Connecting to device using 'telnet conserv1 3007'
309 23:27:15.256314 Setting prompt string to ['lava-test: # ']
310 23:27:15.257940 end: 2.3 connect-device (duration 00:00:00) [common]
311 23:27:15.258596 start: 2.4 uboot-commands (timeout 00:05:00) [common]
312 23:27:15.259201 start: 2.4.1 reset-device (timeout 00:05:00) [common]
313 23:27:15.259777 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
314 23:27:15.261015 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
315 23:27:15.314456 >> OK - accepted request
316 23:27:15.316715 Returned 0 in 0 seconds
317 23:27:15.417956 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
319 23:27:15.419727 end: 2.4.1 reset-device (duration 00:00:00) [common]
320 23:27:15.420422 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
321 23:27:15.421001 Setting prompt string to ['Hit any key to stop autoboot']
322 23:27:15.421510 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
323 23:27:15.423234 Trying 192.168.56.21...
324 23:27:15.423781 Connected to conserv1.
325 23:27:15.424286 Escape character is '^]'.
326 23:27:15.424743
327 23:27:15.425201 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
328 23:27:15.425665
329 23:27:27.389753 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.�!,K��х��}���с0x01
330 23:27:27.390431 bl2_stage_init 0x81
331 23:27:27.395365 hw id: 0x0000 - pwm id 0x01
332 23:27:27.395865 bl2_stage_init 0xc1
333 23:27:27.396401 bl2_stage_init 0x02
334 23:27:27.396851
335 23:27:27.400818 L0:00000000
336 23:27:27.401293 L1:20000703
337 23:27:27.401741 L2:00008067
338 23:27:27.402167 L3:14000000
339 23:27:27.402598 B2:00402000
340 23:27:27.403822 B1:e0f83180
341 23:27:27.404312
342 23:27:27.404741 TE: 58150
343 23:27:27.405171
344 23:27:27.414862 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
345 23:27:27.415378
346 23:27:27.415815 Board ID = 1
347 23:27:27.416329 Set A53 clk to 24M
348 23:27:27.416760 Set A73 clk to 24M
349 23:27:27.420405 Set clk81 to 24M
350 23:27:27.420870 A53 clk: 1200 MHz
351 23:27:27.421295 A73 clk: 1200 MHz
352 23:27:27.423860 CLK81: 166.6M
353 23:27:27.424350 smccc: 00012aab
354 23:27:27.429439 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
355 23:27:27.435048 board id: 1
356 23:27:27.440296 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
357 23:27:27.450885 fw parse done
358 23:27:27.456868 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
359 23:27:27.499456 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
360 23:27:27.510429 PIEI prepare done
361 23:27:27.510908 fastboot data load
362 23:27:27.511339 fastboot data verify
363 23:27:27.515945 verify result: 266
364 23:27:27.521640 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
365 23:27:27.522112 LPDDR4 probe
366 23:27:27.522543 ddr clk to 1584MHz
367 23:27:27.529583 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
368 23:27:27.566921
369 23:27:27.567462 dmc_version 0001
370 23:27:27.573509 Check phy result
371 23:27:27.579412 INFO : End of CA training
372 23:27:27.579883 INFO : End of initialization
373 23:27:27.585011 INFO : Training has run successfully!
374 23:27:27.585484 Check phy result
375 23:27:27.590618 INFO : End of initialization
376 23:27:27.591090 INFO : End of read enable training
377 23:27:27.593887 INFO : End of fine write leveling
378 23:27:27.599477 INFO : End of Write leveling coarse delay
379 23:27:27.605071 INFO : Training has run successfully!
380 23:27:27.605535 Check phy result
381 23:27:27.605964 INFO : End of initialization
382 23:27:27.610586 INFO : End of read dq deskew training
383 23:27:27.616246 INFO : End of MPR read delay center optimization
384 23:27:27.616718 INFO : End of write delay center optimization
385 23:27:27.621803 INFO : End of read delay center optimization
386 23:27:27.627321 INFO : End of max read latency training
387 23:27:27.627782 INFO : Training has run successfully!
388 23:27:27.633031 1D training succeed
389 23:27:27.638961 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
390 23:27:27.686607 Check phy result
391 23:27:27.687101 INFO : End of initialization
392 23:27:27.708347 INFO : End of 2D read delay Voltage center optimization
393 23:27:27.729472 INFO : End of 2D read delay Voltage center optimization
394 23:27:27.781523 INFO : End of 2D write delay Voltage center optimization
395 23:27:27.831234 INFO : End of 2D write delay Voltage center optimization
396 23:27:27.836718 INFO : Training has run successfully!
397 23:27:27.837197
398 23:27:27.837645 channel==0
399 23:27:27.842016 RxClkDly_Margin_A0==88 ps 9
400 23:27:27.842509 TxDqDly_Margin_A0==98 ps 10
401 23:27:27.847657 RxClkDly_Margin_A1==88 ps 9
402 23:27:27.848169 TxDqDly_Margin_A1==98 ps 10
403 23:27:27.848625 TrainedVREFDQ_A0==74
404 23:27:27.853245 TrainedVREFDQ_A1==74
405 23:27:27.853724 VrefDac_Margin_A0==25
406 23:27:27.854170 DeviceVref_Margin_A0==40
407 23:27:27.859177 VrefDac_Margin_A1==24
408 23:27:27.859659 DeviceVref_Margin_A1==40
409 23:27:27.860136
410 23:27:27.860581
411 23:27:27.864762 channel==1
412 23:27:27.865240 RxClkDly_Margin_A0==98 ps 10
413 23:27:27.865685 TxDqDly_Margin_A0==98 ps 10
414 23:27:27.870049 RxClkDly_Margin_A1==88 ps 9
415 23:27:27.870518 TxDqDly_Margin_A1==88 ps 9
416 23:27:27.875616 TrainedVREFDQ_A0==77
417 23:27:27.876120 TrainedVREFDQ_A1==77
418 23:27:27.876572 VrefDac_Margin_A0==23
419 23:27:27.881191 DeviceVref_Margin_A0==37
420 23:27:27.881679 VrefDac_Margin_A1==24
421 23:27:27.886785 DeviceVref_Margin_A1==37
422 23:27:27.887255
423 23:27:27.887700 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
424 23:27:27.888181
425 23:27:27.920448 soc_vref_reg_value 0x 00000019 0000001a 00000018 00000019 00000018 00000019 00000019 00000018 00000018 00000016 00000018 00000015 00000018 00000019 00000018 00000019 00000018 0000001a 0000001a 00000018 00000016 00000018 00000017 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
426 23:27:27.921039 2D training succeed
427 23:27:27.925969 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
428 23:27:27.931597 auto size-- 65535DDR cs0 size: 2048MB
429 23:27:27.932140 DDR cs1 size: 2048MB
430 23:27:27.937128 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
431 23:27:27.937605 cs0 DataBus test pass
432 23:27:27.942709 cs1 DataBus test pass
433 23:27:27.943181 cs0 AddrBus test pass
434 23:27:27.943629 cs1 AddrBus test pass
435 23:27:27.944102
436 23:27:27.948334 100bdlr_step_size ps== 420
437 23:27:27.948821 result report
438 23:27:27.953984 boot times 0Enable ddr reg access
439 23:27:27.959339 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
440 23:27:27.972848 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
441 23:27:28.546517 0.0;M3 CHK:0;cm4_sp_mode 0
442 23:27:28.547137 MVN_1=0x00000000
443 23:27:28.551880 MVN_2=0x00000000
444 23:27:28.557730 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
445 23:27:28.558227 OPS=0x10
446 23:27:28.558678 ring efuse init
447 23:27:28.559116 chipver efuse init
448 23:27:28.565958 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
449 23:27:28.566451 [0.018961 Inits done]
450 23:27:28.566892 secure task start!
451 23:27:28.573502 high task start!
452 23:27:28.574009 low task start!
453 23:27:28.574455 run into bl31
454 23:27:28.580937 NOTICE: BL31: v1.3(release):4fc40b1
455 23:27:28.587160 NOTICE: BL31: Built : 15:58:17, May 22 2019
456 23:27:28.587645 NOTICE: BL31: G12A normal boot!
457 23:27:28.613408 NOTICE: BL31: BL33 decompress pass
458 23:27:28.619000 ERROR: Error initializing runtime service opteed_fast
459 23:27:29.851886
460 23:27:29.852566
461 23:27:29.860249 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
462 23:27:29.860737
463 23:27:29.861185 Model: Libre Computer AML-A311D-CC Alta
464 23:27:30.068773 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
465 23:27:30.092133 DRAM: 2 GiB (effective 3.8 GiB)
466 23:27:30.235097 Core: 408 devices, 31 uclasses, devicetree: separate
467 23:27:30.240948 WDT: Not starting watchdog@f0d0
468 23:27:30.273221 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
469 23:27:30.285940 Loading Environment from FAT... Card did not respond to voltage select! : -110
470 23:27:30.289894 ** Bad device specification mmc 0 **
471 23:27:30.300996 Card did not respond to voltage select! : -110
472 23:27:30.308904 ** Bad device specification mmc 0 **
473 23:27:30.309429 Couldn't find partition mmc 0
474 23:27:30.317042 Card did not respond to voltage select! : -110
475 23:27:30.322557 ** Bad device specification mmc 0 **
476 23:27:30.323085 Couldn't find partition mmc 0
477 23:27:30.327639 Error: could not access storage.
478 23:27:31.590133 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.�!,K��х��}���с0x01
479 23:27:31.590779 bl2_stage_init 0x81
480 23:27:31.595780 hw id: 0x0000 - pwm id 0x01
481 23:27:31.596313 bl2_stage_init 0xc1
482 23:27:31.596769 bl2_stage_init 0x02
483 23:27:31.597218
484 23:27:31.601290 L0:00000000
485 23:27:31.601769 L1:20000703
486 23:27:31.602215 L2:00008067
487 23:27:31.602653 L3:14000000
488 23:27:31.603086 B2:00402000
489 23:27:31.604076 B1:e0f83180
490 23:27:31.604559
491 23:27:31.605011 TE: 58150
492 23:27:31.605452
493 23:27:31.615303 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
494 23:27:31.615797
495 23:27:31.616285 Board ID = 1
496 23:27:31.616732 Set A53 clk to 24M
497 23:27:31.617171 Set A73 clk to 24M
498 23:27:31.626654 Set clk81 to 24M
499 23:27:31.627171 A53 clk: 1200 MHz
500 23:27:31.627616 A73 clk: 1200 MHz
501 23:27:31.628641 CLK81: 166.6M
502 23:27:31.629119 smccc: 00012aab
503 23:27:31.632598 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
504 23:27:31.633111 board id: 1
505 23:27:31.641517 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
506 23:27:31.652526 fw parse done
507 23:27:31.658738 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
508 23:27:31.703304 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
509 23:27:31.712941 PIEI prepare done
510 23:27:31.713450 fastboot data load
511 23:27:31.713907 fastboot data verify
512 23:27:31.718593 verify result: 266
513 23:27:31.724172 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
514 23:27:31.724660 LPDDR4 probe
515 23:27:31.725107 ddr clk to 1584MHz
516 23:27:31.732098 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
517 23:27:31.771641
518 23:27:31.772210 dmc_version 0001
519 23:27:31.774119 Check phy result
520 23:27:31.779879 INFO : End of CA training
521 23:27:31.780402 INFO : End of initialization
522 23:27:31.785473 INFO : Training has run successfully!
523 23:27:31.785962 Check phy result
524 23:27:31.791068 INFO : End of initialization
525 23:27:31.791573 INFO : End of read enable training
526 23:27:31.796705 INFO : End of fine write leveling
527 23:27:31.802266 INFO : End of Write leveling coarse delay
528 23:27:31.802771 INFO : Training has run successfully!
529 23:27:31.803220 Check phy result
530 23:27:31.807887 INFO : End of initialization
531 23:27:31.808412 INFO : End of read dq deskew training
532 23:27:31.813460 INFO : End of MPR read delay center optimization
533 23:27:31.819056 INFO : End of write delay center optimization
534 23:27:31.824674 INFO : End of read delay center optimization
535 23:27:31.825150 INFO : End of max read latency training
536 23:27:31.830310 INFO : Training has run successfully!
537 23:27:31.830781 1D training succeed
538 23:27:31.839447 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
539 23:27:31.887064 Check phy result
540 23:27:31.887560 INFO : End of initialization
541 23:27:31.910798 INFO : End of 2D read delay Voltage center optimization
542 23:27:31.929040 INFO : End of 2D read delay Voltage center optimization
543 23:27:31.980225 INFO : End of 2D write delay Voltage center optimization
544 23:27:32.030513 INFO : End of 2D write delay Voltage center optimization
545 23:27:32.036069 INFO : Training has run successfully!
546 23:27:32.036563
547 23:27:32.037013 channel==0
548 23:27:32.041653 RxClkDly_Margin_A0==88 ps 9
549 23:27:32.042126 TxDqDly_Margin_A0==98 ps 10
550 23:27:32.045164 RxClkDly_Margin_A1==88 ps 9
551 23:27:32.045639 TxDqDly_Margin_A1==98 ps 10
552 23:27:32.050517 TrainedVREFDQ_A0==74
553 23:27:32.051002 TrainedVREFDQ_A1==74
554 23:27:32.051445 VrefDac_Margin_A0==25
555 23:27:32.056253 DeviceVref_Margin_A0==40
556 23:27:32.056724 VrefDac_Margin_A1==25
557 23:27:32.061745 DeviceVref_Margin_A1==40
558 23:27:32.062258
559 23:27:32.062710
560 23:27:32.063150 channel==1
561 23:27:32.063581 RxClkDly_Margin_A0==98 ps 10
562 23:27:32.067323 TxDqDly_Margin_A0==98 ps 10
563 23:27:32.067802 RxClkDly_Margin_A1==98 ps 10
564 23:27:32.072910 TxDqDly_Margin_A1==88 ps 9
565 23:27:32.073407 TrainedVREFDQ_A0==77
566 23:27:32.073854 TrainedVREFDQ_A1==77
567 23:27:32.078565 VrefDac_Margin_A0==22
568 23:27:32.079050 DeviceVref_Margin_A0==37
569 23:27:32.084210 VrefDac_Margin_A1==22
570 23:27:32.084682 DeviceVref_Margin_A1==37
571 23:27:32.085124
572 23:27:32.089901 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
573 23:27:32.090380
574 23:27:32.117748 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000019 00000017 00000019 00000018 00000019 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
575 23:27:32.123597 2D training succeed
576 23:27:32.128916 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
577 23:27:32.129410 auto size-- 65535DDR cs0 size: 2048MB
578 23:27:32.134543 DDR cs1 size: 2048MB
579 23:27:32.135022 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
580 23:27:32.140269 cs0 DataBus test pass
581 23:27:32.140763 cs1 DataBus test pass
582 23:27:32.141212 cs0 AddrBus test pass
583 23:27:32.145775 cs1 AddrBus test pass
584 23:27:32.146256
585 23:27:32.146700 100bdlr_step_size ps== 420
586 23:27:32.147151 result report
587 23:27:32.151325 boot times 0Enable ddr reg access
588 23:27:32.159038 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
589 23:27:32.171955 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
590 23:27:32.746314 0.0;M3 CHK:0;cm4_sp_mode 0
591 23:27:32.746966 MVN_1=0x00000000
592 23:27:32.751848 MVN_2=0x00000000
593 23:27:32.757566 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
594 23:27:32.758090 OPS=0x10
595 23:27:32.758551 ring efuse init
596 23:27:32.759016 chipver efuse init
597 23:27:32.765782 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
598 23:27:32.766311 [0.018960 Inits done]
599 23:27:32.766743 secure task start!
600 23:27:32.773327 high task start!
601 23:27:32.773802 low task start!
602 23:27:32.774225 run into bl31
603 23:27:32.780079 NOTICE: BL31: v1.3(release):4fc40b1
604 23:27:32.787872 NOTICE: BL31: Built : 15:58:17, May 22 2019
605 23:27:32.788494 NOTICE: BL31: G12A normal boot!
606 23:27:32.813390 NOTICE: BL31: BL33 decompress pass
607 23:27:32.818073 ERROR: Error initializing runtime service opteed_fast
608 23:27:34.051846
609 23:27:34.052478
610 23:27:34.060378 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
611 23:27:34.060849
612 23:27:34.061263 Model: Libre Computer AML-A311D-CC Alta
613 23:27:34.267894 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
614 23:27:34.292053 DRAM: 2 GiB (effective 3.8 GiB)
615 23:27:34.435051 Core: 408 devices, 31 uclasses, devicetree: separate
616 23:27:34.440038 WDT: Not starting watchdog@f0d0
617 23:27:34.473068 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
618 23:27:34.485507 Loading Environment from FAT... Card did not respond to voltage select! : -110
619 23:27:34.490541 ** Bad device specification mmc 0 **
620 23:27:34.501135 Card did not respond to voltage select! : -110
621 23:27:34.508726 ** Bad device specification mmc 0 **
622 23:27:34.509196 Couldn't find partition mmc 0
623 23:27:34.516852 Card did not respond to voltage select! : -110
624 23:27:34.522461 ** Bad device specification mmc 0 **
625 23:27:34.522977 Couldn't find partition mmc 0
626 23:27:34.527472 Error: could not access storage.
627 23:27:34.870374 Net: eth0: ethernet@ff3f0000
628 23:27:34.870975 starting USB...
629 23:27:35.122190 Bus usb@ff500000: Register 3000140 NbrPorts 3
630 23:27:35.122748 Starting the controller
631 23:27:35.128938 USB XHCI 1.10
632 23:27:36.840278 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
633 23:27:36.840876 bl2_stage_init 0x01
634 23:27:36.841298 bl2_stage_init 0x81
635 23:27:36.845972 hw id: 0x0000 - pwm id 0x01
636 23:27:36.846445 bl2_stage_init 0xc1
637 23:27:36.846858 bl2_stage_init 0x02
638 23:27:36.847256
639 23:27:36.851509 L0:00000000
640 23:27:36.852024 L1:20000703
641 23:27:36.852439 L2:00008067
642 23:27:36.852840 L3:14000000
643 23:27:36.854469 B2:00402000
644 23:27:36.854927 B1:e0f83180
645 23:27:36.855331
646 23:27:36.855724 TE: 58167
647 23:27:36.856159
648 23:27:36.865673 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
649 23:27:36.866162
650 23:27:36.866571 Board ID = 1
651 23:27:36.866975 Set A53 clk to 24M
652 23:27:36.867371 Set A73 clk to 24M
653 23:27:36.871172 Set clk81 to 24M
654 23:27:36.871642 A53 clk: 1200 MHz
655 23:27:36.872077 A73 clk: 1200 MHz
656 23:27:36.876874 CLK81: 166.6M
657 23:27:36.877339 smccc: 00012abd
658 23:27:36.882904 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
659 23:27:36.883370 board id: 1
660 23:27:36.890661 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
661 23:27:36.901723 fw parse done
662 23:27:36.907778 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
663 23:27:36.949327 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
664 23:27:36.961150 PIEI prepare done
665 23:27:36.961631 fastboot data load
666 23:27:36.962043 fastboot data verify
667 23:27:36.966827 verify result: 266
668 23:27:36.972420 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
669 23:27:36.972898 LPDDR4 probe
670 23:27:36.973306 ddr clk to 1584MHz
671 23:27:36.980331 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
672 23:27:37.017615
673 23:27:37.018113 dmc_version 0001
674 23:27:37.024360 Check phy result
675 23:27:37.030171 INFO : End of CA training
676 23:27:37.030635 INFO : End of initialization
677 23:27:37.035788 INFO : Training has run successfully!
678 23:27:37.036280 Check phy result
679 23:27:37.041381 INFO : End of initialization
680 23:27:37.041840 INFO : End of read enable training
681 23:27:37.044770 INFO : End of fine write leveling
682 23:27:37.050422 INFO : End of Write leveling coarse delay
683 23:27:37.056092 INFO : Training has run successfully!
684 23:27:37.056580 Check phy result
685 23:27:37.056994 INFO : End of initialization
686 23:27:37.061666 INFO : End of read dq deskew training
687 23:27:37.064994 INFO : End of MPR read delay center optimization
688 23:27:37.070505 INFO : End of write delay center optimization
689 23:27:37.076139 INFO : End of read delay center optimization
690 23:27:37.076631 INFO : End of max read latency training
691 23:27:37.081766 INFO : Training has run successfully!
692 23:27:37.082250 1D training succeed
693 23:27:37.089889 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
694 23:27:37.137390 Check phy result
695 23:27:37.137914 INFO : End of initialization
696 23:27:37.159154 INFO : End of 2D read delay Voltage center optimization
697 23:27:37.178535 INFO : End of 2D read delay Voltage center optimization
698 23:27:37.230538 INFO : End of 2D write delay Voltage center optimization
699 23:27:37.280832 INFO : End of 2D write delay Voltage center optimization
700 23:27:37.286319 INFO : Training has run successfully!
701 23:27:37.286813
702 23:27:37.287230 channel==0
703 23:27:37.292114 RxClkDly_Margin_A0==88 ps 9
704 23:27:37.292599 TxDqDly_Margin_A0==98 ps 10
705 23:27:37.295373 RxClkDly_Margin_A1==88 ps 9
706 23:27:37.295834 TxDqDly_Margin_A1==98 ps 10
707 23:27:37.300900 TrainedVREFDQ_A0==74
708 23:27:37.301383 TrainedVREFDQ_A1==74
709 23:27:37.301794 VrefDac_Margin_A0==25
710 23:27:37.306536 DeviceVref_Margin_A0==40
711 23:27:37.307006 VrefDac_Margin_A1==25
712 23:27:37.312147 DeviceVref_Margin_A1==40
713 23:27:37.312628
714 23:27:37.313039
715 23:27:37.313436 channel==1
716 23:27:37.313825 RxClkDly_Margin_A0==98 ps 10
717 23:27:37.315652 TxDqDly_Margin_A0==88 ps 9
718 23:27:37.321218 RxClkDly_Margin_A1==88 ps 9
719 23:27:37.321709 TxDqDly_Margin_A1==88 ps 9
720 23:27:37.322125 TrainedVREFDQ_A0==77
721 23:27:37.326817 TrainedVREFDQ_A1==77
722 23:27:37.327299 VrefDac_Margin_A0==22
723 23:27:37.332445 DeviceVref_Margin_A0==37
724 23:27:37.332923 VrefDac_Margin_A1==24
725 23:27:37.333328 DeviceVref_Margin_A1==37
726 23:27:37.333722
727 23:27:37.341324 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
728 23:27:37.341830
729 23:27:37.367214 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000019 00000017 00000019 00000018 0000001a 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
730 23:27:37.372771 2D training succeed
731 23:27:37.378380 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
732 23:27:37.378872 auto size-- 65535DDR cs0 size: 2048MB
733 23:27:37.384385 DDR cs1 size: 2048MB
734 23:27:37.384872 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
735 23:27:37.389584 cs0 DataBus test pass
736 23:27:37.390067 cs1 DataBus test pass
737 23:27:37.395212 cs0 AddrBus test pass
738 23:27:37.395693 cs1 AddrBus test pass
739 23:27:37.396155
740 23:27:37.396574 100bdlr_step_size ps== 420
741 23:27:37.400789 result report
742 23:27:37.401271 boot times 0Enable ddr reg access
743 23:27:37.408282 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
744 23:27:37.422638 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
745 23:27:37.996399 0.0;M3 CHK:0;cm4_sp_mode 0
746 23:27:37.997018 MVN_1=0x00000000
747 23:27:38.002041 MVN_2=0x00000000
748 23:27:38.007753 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
749 23:27:38.008347 OPS=0x10
750 23:27:38.008754 ring efuse init
751 23:27:38.009144 chipver efuse init
752 23:27:38.013432 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
753 23:27:38.018887 [0.018961 Inits done]
754 23:27:38.019359 secure task start!
755 23:27:38.019749 high task start!
756 23:27:38.023461 low task start!
757 23:27:38.023912 run into bl31
758 23:27:38.030080 NOTICE: BL31: v1.3(release):4fc40b1
759 23:27:38.037205 NOTICE: BL31: Built : 15:58:17, May 22 2019
760 23:27:38.037686 NOTICE: BL31: G12A normal boot!
761 23:27:38.063393 NOTICE: BL31: BL33 decompress pass
762 23:27:38.068173 ERROR: Error initializing runtime service opteed_fast
763 23:27:39.301850
764 23:27:39.302482
765 23:27:39.310352 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
766 23:27:39.310908
767 23:27:39.311367 Model: Libre Computer AML-A311D-CC Alta
768 23:27:39.518604 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
769 23:27:39.542188 DRAM: 2 GiB (effective 3.8 GiB)
770 23:27:39.685010 Core: 408 devices, 31 uclasses, devicetree: separate
771 23:27:39.690916 WDT: Not starting watchdog@f0d0
772 23:27:39.723257 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
773 23:27:39.735596 Loading Environment from FAT... Card did not respond to voltage select! : -110
774 23:27:39.740537 ** Bad device specification mmc 0 **
775 23:27:39.750863 Card did not respond to voltage select! : -110
776 23:27:39.758541 ** Bad device specification mmc 0 **
777 23:27:39.759100 Couldn't find partition mmc 0
778 23:27:39.766977 Card did not respond to voltage select! : -110
779 23:27:39.772399 ** Bad device specification mmc 0 **
780 23:27:39.772906 Couldn't find partition mmc 0
781 23:27:39.777470 Error: could not access storage.
782 23:27:40.120078 Net: eth0: ethernet@ff3f0000
783 23:27:40.120682 starting USB...
784 23:27:40.371774 Bus usb@ff500000: Register 3000140 NbrPorts 3
785 23:27:40.372428 Starting the controller
786 23:27:40.378734 USB XHCI 1.10
787 23:27:42.541860 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
788 23:27:42.542468 bl2_stage_init 0x01
789 23:27:42.542890 bl2_stage_init 0x81
790 23:27:42.547465 hw id: 0x0000 - pwm id 0x01
791 23:27:42.547953 bl2_stage_init 0xc1
792 23:27:42.548415 bl2_stage_init 0x02
793 23:27:42.548820
794 23:27:42.552816 L0:00000000
795 23:27:42.553282 L1:20000703
796 23:27:42.553692 L2:00008067
797 23:27:42.554090 L3:14000000
798 23:27:42.555822 B2:00402000
799 23:27:42.556449 B1:e0f83180
800 23:27:42.556940
801 23:27:42.557417 TE: 58124
802 23:27:42.557915
803 23:27:42.566860 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
804 23:27:42.567457
805 23:27:42.568025 Board ID = 1
806 23:27:42.568546 Set A53 clk to 24M
807 23:27:42.569056 Set A73 clk to 24M
808 23:27:42.572436 Set clk81 to 24M
809 23:27:42.573262 A53 clk: 1200 MHz
810 23:27:42.573831 A73 clk: 1200 MHz
811 23:27:42.575870 CLK81: 166.6M
812 23:27:42.576476 smccc: 00012a92
813 23:27:42.581399 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
814 23:27:42.587142 board id: 1
815 23:27:42.592297 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
816 23:27:42.603013 fw parse done
817 23:27:42.608983 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
818 23:27:42.651509 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
819 23:27:42.662486 PIEI prepare done
820 23:27:42.663021 fastboot data load
821 23:27:42.663482 fastboot data verify
822 23:27:42.668080 verify result: 266
823 23:27:42.673650 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
824 23:27:42.674148 LPDDR4 probe
825 23:27:42.674597 ddr clk to 1584MHz
826 23:27:42.681630 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
827 23:27:42.718897
828 23:27:42.719417 dmc_version 0001
829 23:27:42.725541 Check phy result
830 23:27:42.731415 INFO : End of CA training
831 23:27:42.731908 INFO : End of initialization
832 23:27:42.737034 INFO : Training has run successfully!
833 23:27:42.737526 Check phy result
834 23:27:42.742628 INFO : End of initialization
835 23:27:42.743117 INFO : End of read enable training
836 23:27:42.748206 INFO : End of fine write leveling
837 23:27:42.753849 INFO : End of Write leveling coarse delay
838 23:27:42.754350 INFO : Training has run successfully!
839 23:27:42.754803 Check phy result
840 23:27:42.759429 INFO : End of initialization
841 23:27:42.759920 INFO : End of read dq deskew training
842 23:27:42.765036 INFO : End of MPR read delay center optimization
843 23:27:42.770664 INFO : End of write delay center optimization
844 23:27:42.776358 INFO : End of read delay center optimization
845 23:27:42.776951 INFO : End of max read latency training
846 23:27:42.782046 INFO : Training has run successfully!
847 23:27:42.782615 1D training succeed
848 23:27:42.790341 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
849 23:27:42.837872 Check phy result
850 23:27:42.839035 INFO : End of initialization
851 23:27:42.860451 INFO : End of 2D read delay Voltage center optimization
852 23:27:42.880522 INFO : End of 2D read delay Voltage center optimization
853 23:27:42.932470 INFO : End of 2D write delay Voltage center optimization
854 23:27:42.981699 INFO : End of 2D write delay Voltage center optimization
855 23:27:42.987256 INFO : Training has run successfully!
856 23:27:42.988289
857 23:27:42.988853 channel==0
858 23:27:42.992899 RxClkDly_Margin_A0==88 ps 9
859 23:27:42.993934 TxDqDly_Margin_A0==108 ps 11
860 23:27:42.998354 RxClkDly_Margin_A1==88 ps 9
861 23:27:42.998964 TxDqDly_Margin_A1==98 ps 10
862 23:27:42.999467 TrainedVREFDQ_A0==74
863 23:27:43.003903 TrainedVREFDQ_A1==74
864 23:27:43.004482 VrefDac_Margin_A0==25
865 23:27:43.009702 DeviceVref_Margin_A0==40
866 23:27:43.010285 VrefDac_Margin_A1==25
867 23:27:43.010778 DeviceVref_Margin_A1==40
868 23:27:43.011265
869 23:27:43.011754
870 23:27:43.015231 channel==1
871 23:27:43.015793 RxClkDly_Margin_A0==98 ps 10
872 23:27:43.016299 TxDqDly_Margin_A0==98 ps 10
873 23:27:43.020739 RxClkDly_Margin_A1==98 ps 10
874 23:27:43.021301 TxDqDly_Margin_A1==88 ps 9
875 23:27:43.026272 TrainedVREFDQ_A0==77
876 23:27:43.026813 TrainedVREFDQ_A1==77
877 23:27:43.027266 VrefDac_Margin_A0==22
878 23:27:43.031977 DeviceVref_Margin_A0==37
879 23:27:43.032581 VrefDac_Margin_A1==22
880 23:27:43.037524 DeviceVref_Margin_A1==37
881 23:27:43.038064
882 23:27:43.038521 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
883 23:27:43.043133
884 23:27:43.071168 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000019 00000018 00000018 00000016 00000018 00000015 00000018 00000019 00000018 00000019 00000018 00000019 00000019 00000018 00000017 00000018 00000017 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
885 23:27:43.071956 2D training succeed
886 23:27:43.076693 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
887 23:27:43.082253 auto size-- 65535DDR cs0 size: 2048MB
888 23:27:43.083018 DDR cs1 size: 2048MB
889 23:27:43.087920 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
890 23:27:43.089120 cs0 DataBus test pass
891 23:27:43.093594 cs1 DataBus test pass
892 23:27:43.094664 cs0 AddrBus test pass
893 23:27:43.095670 cs1 AddrBus test pass
894 23:27:43.096882
895 23:27:43.099122 100bdlr_step_size ps== 420
896 23:27:43.100123 result report
897 23:27:43.104743 boot times 0Enable ddr reg access
898 23:27:43.110339 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
899 23:27:43.123669 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
900 23:27:43.695670 0.0;M3 CHK:0;cm4_sp_mode 0
901 23:27:43.696450 MVN_1=0x00000000
902 23:27:43.701079 MVN_2=0x00000000
903 23:27:43.706852 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
904 23:27:43.707432 OPS=0x10
905 23:27:43.707967 ring efuse init
906 23:27:43.708535 chipver efuse init
907 23:27:43.712536 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
908 23:27:43.718035 [0.018961 Inits done]
909 23:27:43.718617 secure task start!
910 23:27:43.719149 high task start!
911 23:27:43.721653 low task start!
912 23:27:43.722193 run into bl31
913 23:27:43.729323 NOTICE: BL31: v1.3(release):4fc40b1
914 23:27:43.737091 NOTICE: BL31: Built : 15:58:17, May 22 2019
915 23:27:43.737658 NOTICE: BL31: G12A normal boot!
916 23:27:43.762552 NOTICE: BL31: BL33 decompress pass
917 23:27:43.768298 ERROR: Error initializing runtime service opteed_fast
918 23:27:45.001030
919 23:27:45.001716
920 23:27:45.008488 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
921 23:27:45.009226
922 23:27:45.009797 Model: Libre Computer AML-A311D-CC Alta
923 23:27:45.217934 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
924 23:27:45.241011 DRAM: 2 GiB (effective 3.8 GiB)
925 23:27:45.384238 Core: 408 devices, 31 uclasses, devicetree: separate
926 23:27:45.390066 WDT: Not starting watchdog@f0d0
927 23:27:45.422347 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
928 23:27:45.434813 Loading Environment from FAT... Card did not respond to voltage select! : -110
929 23:27:45.439761 ** Bad device specification mmc 0 **
930 23:27:45.450077 Card did not respond to voltage select! : -110
931 23:27:45.457802 ** Bad device specification mmc 0 **
932 23:27:45.458373 Couldn't find partition mmc 0
933 23:27:45.466111 Card did not respond to voltage select! : -110
934 23:27:45.471704 ** Bad device specification mmc 0 **
935 23:27:45.472284 Couldn't find partition mmc 0
936 23:27:45.476766 Error: could not access storage.
937 23:27:45.818999 Net: eth0: ethernet@ff3f0000
938 23:27:45.820257 starting USB...
939 23:27:46.071091 Bus usb@ff500000: Register 3000140 NbrPorts 3
940 23:27:46.071823 Starting the controller
941 23:27:46.078030 USB XHCI 1.10
942 23:27:47.941514 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
943 23:27:47.941984 bl2_stage_init 0x01
944 23:27:47.942237 bl2_stage_init 0x81
945 23:27:47.947065 hw id: 0x0000 - pwm id 0x01
946 23:27:47.947352 bl2_stage_init 0xc1
947 23:27:47.947634 bl2_stage_init 0x02
948 23:27:47.947866
949 23:27:47.952655 L0:00000000
950 23:27:47.952983 L1:20000703
951 23:27:47.953256 L2:00008067
952 23:27:47.953499 L3:14000000
953 23:27:47.955551 B2:00402000
954 23:27:47.955864 B1:e0f83180
955 23:27:47.956121
956 23:27:47.956400 TE: 58159
957 23:27:47.956666
958 23:27:47.966787 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
959 23:27:47.967083
960 23:27:47.967315 Board ID = 1
961 23:27:47.967543 Set A53 clk to 24M
962 23:27:47.967760 Set A73 clk to 24M
963 23:27:47.972381 Set clk81 to 24M
964 23:27:47.972819 A53 clk: 1200 MHz
965 23:27:47.973132 A73 clk: 1200 MHz
966 23:27:47.978048 CLK81: 166.6M
967 23:27:47.978491 smccc: 00012ab5
968 23:27:47.983568 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
969 23:27:47.984040 board id: 1
970 23:27:47.992155 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
971 23:27:48.002856 fw parse done
972 23:27:48.008152 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
973 23:27:48.051421 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
974 23:27:48.062463 PIEI prepare done
975 23:27:48.062938 fastboot data load
976 23:27:48.063184 fastboot data verify
977 23:27:48.068265 verify result: 266
978 23:27:48.073730 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
979 23:27:48.074184 LPDDR4 probe
980 23:27:48.074428 ddr clk to 1584MHz
981 23:27:48.081821 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
982 23:27:48.118191
983 23:27:48.118685 dmc_version 0001
984 23:27:48.124949 Check phy result
985 23:27:48.131548 INFO : End of CA training
986 23:27:48.132048 INFO : End of initialization
987 23:27:48.137043 INFO : Training has run successfully!
988 23:27:48.137488 Check phy result
989 23:27:48.142738 INFO : End of initialization
990 23:27:48.143187 INFO : End of read enable training
991 23:27:48.146016 INFO : End of fine write leveling
992 23:27:48.151551 INFO : End of Write leveling coarse delay
993 23:27:48.157233 INFO : Training has run successfully!
994 23:27:48.157673 Check phy result
995 23:27:48.157969 INFO : End of initialization
996 23:27:48.162588 INFO : End of read dq deskew training
997 23:27:48.168239 INFO : End of MPR read delay center optimization
998 23:27:48.168647 INFO : End of write delay center optimization
999 23:27:48.174068 INFO : End of read delay center optimization
1000 23:27:48.179497 INFO : End of max read latency training
1001 23:27:48.180173 INFO : Training has run successfully!
1002 23:27:48.185157 1D training succeed
1003 23:27:48.191055 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
1004 23:27:48.238674 Check phy result
1005 23:27:48.239154 INFO : End of initialization
1006 23:27:48.261067 INFO : End of 2D read delay Voltage center optimization
1007 23:27:48.281394 INFO : End of 2D read delay Voltage center optimization
1008 23:27:48.333137 INFO : End of 2D write delay Voltage center optimization
1009 23:27:48.382374 INFO : End of 2D write delay Voltage center optimization
1010 23:27:48.387955 INFO : Training has run successfully!
1011 23:27:48.388613
1012 23:27:48.389029 channel==0
1013 23:27:48.393492 RxClkDly_Margin_A0==88 ps 9
1014 23:27:48.394052 TxDqDly_Margin_A0==98 ps 10
1015 23:27:48.399157 RxClkDly_Margin_A1==88 ps 9
1016 23:27:48.399612 TxDqDly_Margin_A1==98 ps 10
1017 23:27:48.399914 TrainedVREFDQ_A0==74
1018 23:27:48.404655 TrainedVREFDQ_A1==74
1019 23:27:48.405096 VrefDac_Margin_A0==25
1020 23:27:48.405389 DeviceVref_Margin_A0==40
1021 23:27:48.410285 VrefDac_Margin_A1==24
1022 23:27:48.410697 DeviceVref_Margin_A1==40
1023 23:27:48.411025
1024 23:27:48.411244
1025 23:27:48.415917 channel==1
1026 23:27:48.416372 RxClkDly_Margin_A0==98 ps 10
1027 23:27:48.416593 TxDqDly_Margin_A0==88 ps 9
1028 23:27:48.421460 RxClkDly_Margin_A1==98 ps 10
1029 23:27:48.421895 TxDqDly_Margin_A1==108 ps 11
1030 23:27:48.427207 TrainedVREFDQ_A0==77
1031 23:27:48.427643 TrainedVREFDQ_A1==78
1032 23:27:48.427916 VrefDac_Margin_A0==22
1033 23:27:48.432676 DeviceVref_Margin_A0==37
1034 23:27:48.433123 VrefDac_Margin_A1==22
1035 23:27:48.438264 DeviceVref_Margin_A1==36
1036 23:27:48.438693
1037 23:27:48.438997 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
1038 23:27:48.444013
1039 23:27:48.471958 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000019 00000017 00000018 00000016 00000018 00000015 00000018 00000019 00000018 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
1040 23:27:48.472451 2D training succeed
1041 23:27:48.477476 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
1042 23:27:48.483179 auto size-- 65535DDR cs0 size: 2048MB
1043 23:27:48.483615 DDR cs1 size: 2048MB
1044 23:27:48.488683 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
1045 23:27:48.489141 cs0 DataBus test pass
1046 23:27:48.494307 cs1 DataBus test pass
1047 23:27:48.494707 cs0 AddrBus test pass
1048 23:27:48.495017 cs1 AddrBus test pass
1049 23:27:48.495255
1050 23:27:48.499925 100bdlr_step_size ps== 420
1051 23:27:48.500405 result report
1052 23:27:48.505492 boot times 0Enable ddr reg access
1053 23:27:48.511004 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
1054 23:27:48.524485 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
1055 23:27:49.096497 0.0;M3 CHK:0;cm4_sp_mode 0
1056 23:27:49.096918 MVN_1=0x00000000
1057 23:27:49.101974 MVN_2=0x00000000
1058 23:27:49.107712 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
1059 23:27:49.108070 OPS=0x10
1060 23:27:49.108316 ring efuse init
1061 23:27:49.108537 chipver efuse init
1062 23:27:49.113310 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
1063 23:27:49.119034 [0.018961 Inits done]
1064 23:27:49.119328 secure task start!
1065 23:27:49.119602 high task start!
1066 23:27:49.122681 low task start!
1067 23:27:49.122957 run into bl31
1068 23:27:49.130233 NOTICE: BL31: v1.3(release):4fc40b1
1069 23:27:49.137946 NOTICE: BL31: Built : 15:58:17, May 22 2019
1070 23:27:49.138294 NOTICE: BL31: G12A normal boot!
1071 23:27:49.163372 NOTICE: BL31: BL33 decompress pass
1072 23:27:49.167960 ERROR: Error initializing runtime service opteed_fast
1073 23:27:50.402089
1074 23:27:50.403255
1075 23:27:50.410407 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
1076 23:27:50.411152
1077 23:27:50.411608 Model: Libre Computer AML-A311D-CC Alta
1078 23:27:50.846296 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
1079 23:27:50.847010 DRAM: 2 GiB (effective 3.8 GiB)
1080 23:27:50.847473 Core: 408 devices, 31 uclasses, devicetree: separate
1081 23:27:50.847976 WDT: Not starting watchdog@f0d0
1082 23:27:50.848466 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
1083 23:27:50.848961 Loading Environment from FAT... Card did not respond to voltage select! : -110
1084 23:27:50.849893 ** Bad device specification mmc 0 **
1085 23:27:50.854922 Card did not respond to voltage select! : -110
1086 23:27:50.855496 ** Bad device specification mmc 0 **
1087 23:27:50.858672 Couldn't find partition mmc 0
1088 23:27:50.867008 Card did not respond to voltage select! : -110
1089 23:27:50.872519 ** Bad device specification mmc 0 **
1090 23:27:50.873069 Couldn't find partition mmc 0
1091 23:27:50.877613 Error: could not access storage.
1092 23:27:51.220306 Net: eth0: ethernet@ff3f0000
1093 23:27:51.221438 starting USB...
1094 23:27:51.472115 Bus usb@ff500000: Register 3000140 NbrPorts 3
1095 23:27:51.472814 Starting the controller
1096 23:27:51.478893 USB XHCI 1.10
1097 23:27:53.032947 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
1098 23:27:53.041176 scanning usb for storage devices... 0 Storage Device(s) found
1100 23:27:53.093232 Hit any key to stop autoboot: 1
1101 23:27:53.094366 end: 2.4.2 bootloader-interrupt (duration 00:00:38) [common]
1102 23:27:53.095175 start: 2.4.3 bootloader-commands (timeout 00:04:22) [common]
1103 23:27:53.095818 Setting prompt string to ['=>']
1104 23:27:53.096518 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:22)
1105 23:27:53.108656 0
1106 23:27:53.109749 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1107 23:27:53.110387 Sending with 10 millisecond of delay
1109 23:27:54.246228 => setenv autoload no
1110 23:27:54.257051 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:21)
1111 23:27:54.261989 setenv autoload no
1112 23:27:54.262745 Sending with 10 millisecond of delay
1114 23:27:56.059287 => setenv initrd_high 0xffffffff
1115 23:27:56.070054 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:19)
1116 23:27:56.070882 setenv initrd_high 0xffffffff
1117 23:27:56.071596 Sending with 10 millisecond of delay
1119 23:27:57.688600 => setenv fdt_high 0xffffffff
1120 23:27:57.699409 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1121 23:27:57.700296 setenv fdt_high 0xffffffff
1122 23:27:57.701009 Sending with 10 millisecond of delay
1124 23:27:57.992870 => dhcp
1125 23:27:58.003673 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:17)
1126 23:27:58.004559 dhcp
1127 23:27:58.005008 Speed: 1000, full duplex
1128 23:27:58.005424 BOOTP broadcast 1
1129 23:27:58.015915 DHCP client bound to address 192.168.6.27 (12 ms)
1130 23:27:58.016694 Sending with 10 millisecond of delay
1132 23:27:59.693998 => setenv serverip 192.168.6.2
1133 23:27:59.704813 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:16)
1134 23:27:59.705731 setenv serverip 192.168.6.2
1135 23:27:59.706418 Sending with 10 millisecond of delay
1137 23:28:03.430399 => tftpboot 0x01080000 943216/tftp-deploy-0b9nxwej/kernel/uImage
1138 23:28:03.441210 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:12)
1139 23:28:03.442018 tftpboot 0x01080000 943216/tftp-deploy-0b9nxwej/kernel/uImage
1140 23:28:03.442461 Speed: 1000, full duplex
1141 23:28:03.442875 Using ethernet@ff3f0000 device
1142 23:28:03.444034 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1143 23:28:03.449517 Filename '943216/tftp-deploy-0b9nxwej/kernel/uImage'.
1144 23:28:03.453379 Load address: 0x1080000
1145 23:28:04.704852 Loading: *###################### UDP wrong checksum 000000ff 0000ed63
1146 23:28:04.754622 # UDP wrong checksum 000000ff 00007256
1147 23:28:06.254950 ########################### 43.6 MiB
1148 23:28:06.255547 15.5 MiB/s
1149 23:28:06.255968 done
1150 23:28:06.259358 Bytes transferred = 45716032 (2b99240 hex)
1151 23:28:06.260107 Sending with 10 millisecond of delay
1153 23:28:10.948094 => tftpboot 0x08000000 943216/tftp-deploy-0b9nxwej/ramdisk/ramdisk.cpio.gz.uboot
1154 23:28:10.958921 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:04)
1155 23:28:10.959812 tftpboot 0x08000000 943216/tftp-deploy-0b9nxwej/ramdisk/ramdisk.cpio.gz.uboot
1156 23:28:10.960284 Speed: 1000, full duplex
1157 23:28:10.960682 Using ethernet@ff3f0000 device
1158 23:28:10.961643 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1159 23:28:10.970313 Filename '943216/tftp-deploy-0b9nxwej/ramdisk/ramdisk.cpio.gz.uboot'.
1160 23:28:10.970850 Load address: 0x8000000
1161 23:28:18.048035 Loading: *########################T ######################### UDP wrong checksum 00000005 00003169
1162 23:28:22.929121 T UDP wrong checksum 00000005 00003169
1163 23:28:32.931005 T T UDP wrong checksum 00000005 00003169
1164 23:28:39.610249 T UDP wrong checksum 000000ff 00005f4d
1165 23:28:39.623311 UDP wrong checksum 000000ff 0000f53f
1166 23:28:49.198090 T T UDP wrong checksum 000000ff 0000debc
1167 23:28:49.243032 UDP wrong checksum 000000ff 000068af
1168 23:28:52.932964 UDP wrong checksum 00000005 00003169
1169 23:29:07.938882 T T T
1170 23:29:07.939264 Retry count exceeded; starting again
1172 23:29:07.940121 end: 2.4.3 bootloader-commands (duration 00:01:15) [common]
1175 23:29:07.941052 end: 2.4 uboot-commands (duration 00:01:53) [common]
1177 23:29:07.941733 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
1179 23:29:07.942233 end: 2 uboot-action (duration 00:01:53) [common]
1181 23:29:07.943011 Cleaning after the job
1182 23:29:07.943309 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/943216/tftp-deploy-0b9nxwej/ramdisk
1183 23:29:07.943976 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/943216/tftp-deploy-0b9nxwej/kernel
1184 23:29:07.968869 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/943216/tftp-deploy-0b9nxwej/dtb
1185 23:29:07.969677 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/943216/tftp-deploy-0b9nxwej/nfsrootfs
1186 23:29:08.334567 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/943216/tftp-deploy-0b9nxwej/modules
1187 23:29:08.362205 start: 4.1 power-off (timeout 00:00:30) [common]
1188 23:29:08.362870 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1189 23:29:08.397970 >> OK - accepted request
1190 23:29:08.400022 Returned 0 in 0 seconds
1191 23:29:08.501014 end: 4.1 power-off (duration 00:00:00) [common]
1193 23:29:08.502081 start: 4.2 read-feedback (timeout 00:10:00) [common]
1194 23:29:08.502918 Listened to connection for namespace 'common' for up to 1s
1195 23:29:09.503718 Finalising connection for namespace 'common'
1196 23:29:09.504235 Disconnecting from shell: Finalise
1197 23:29:09.504539 =>
1198 23:29:09.605221 end: 4.2 read-feedback (duration 00:00:01) [common]
1199 23:29:09.605750 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/943216
1200 23:29:12.389919 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/943216
1201 23:29:12.390564 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.